979 // Rather than put a barrier on only those writes which are required
980 // to complete, we force all writes to complete.
981 //
982 // 2. On PPC64, also add MemBarRelease for constructors which write
983 // volatile fields. As support_IRIW_for_not_multiple_copy_atomic_cpu
984 // is set on PPC64, no sync instruction is issued after volatile
985 // stores. We want to guarantee the same behavior as on platforms
986 // with total store order, although this is not required by the Java
987 // memory model. So as with finals, we add a barrier here.
988 //
989 // 3. Experimental VM option is used to force the barrier if any field
990 // was written out in the constructor.
991 //
992 // "All bets are off" unless the first publication occurs after a
993 // normal return from the constructor. We do not attempt to detect
994 // such unusual early publications. But no barrier is needed on
995 // exceptional returns, since they cannot publish normally.
996 //
997 if (method()->is_initializer() &&
998 (wrote_final() ||
999 PPC64_ONLY(wrote_volatile() ||)
1000 (AlwaysSafeConstructors && wrote_fields()))) {
1001 _exits.insert_mem_bar(Op_MemBarRelease, alloc_with_final());
1002
1003 // If Memory barrier is created for final fields write
1004 // and allocation node does not escape the initialize method,
1005 // then barrier introduced by allocation node can be removed.
1006 if (DoEscapeAnalysis && alloc_with_final()) {
1007 AllocateNode *alloc = AllocateNode::Ideal_allocation(alloc_with_final(), &_gvn);
1008 alloc->compute_MemBar_redundancy(method());
1009 }
1010 if (PrintOpto && (Verbose || WizardMode)) {
1011 method()->print_name();
1012 tty->print_cr(" writes finals and needs a memory barrier");
1013 }
1014 }
1015
1016 // Any method can write a @Stable field; insert memory barriers
1017 // after those also. Can't bind predecessor allocation node (if any)
1018 // with barrier because allocation doesn't always dominate
1019 // MemBarRelease.
1020 if (wrote_stable()) {
|
979 // Rather than put a barrier on only those writes which are required
980 // to complete, we force all writes to complete.
981 //
982 // 2. On PPC64, also add MemBarRelease for constructors which write
983 // volatile fields. As support_IRIW_for_not_multiple_copy_atomic_cpu
984 // is set on PPC64, no sync instruction is issued after volatile
985 // stores. We want to guarantee the same behavior as on platforms
986 // with total store order, although this is not required by the Java
987 // memory model. So as with finals, we add a barrier here.
988 //
989 // 3. Experimental VM option is used to force the barrier if any field
990 // was written out in the constructor.
991 //
992 // "All bets are off" unless the first publication occurs after a
993 // normal return from the constructor. We do not attempt to detect
994 // such unusual early publications. But no barrier is needed on
995 // exceptional returns, since they cannot publish normally.
996 //
997 if (method()->is_initializer() &&
998 (wrote_final() ||
999 (AlwaysSafeConstructors && wrote_fields()) ||
1000 (support_IRIW_for_not_multiple_copy_atomic_cpu && wrote_volatile())
1001 )
1002 ) {
1003 _exits.insert_mem_bar(Op_MemBarRelease, alloc_with_final());
1004
1005 // If Memory barrier is created for final fields write
1006 // and allocation node does not escape the initialize method,
1007 // then barrier introduced by allocation node can be removed.
1008 if (DoEscapeAnalysis && alloc_with_final()) {
1009 AllocateNode *alloc = AllocateNode::Ideal_allocation(alloc_with_final(), &_gvn);
1010 alloc->compute_MemBar_redundancy(method());
1011 }
1012 if (PrintOpto && (Verbose || WizardMode)) {
1013 method()->print_name();
1014 tty->print_cr(" writes finals and needs a memory barrier");
1015 }
1016 }
1017
1018 // Any method can write a @Stable field; insert memory barriers
1019 // after those also. Can't bind predecessor allocation node (if any)
1020 // with barrier because allocation doesn't always dominate
1021 // MemBarRelease.
1022 if (wrote_stable()) {
|