1 /*
2 * Copyright (c) 2002, 2018, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2012, 2017 SAP SE. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
282
283 NEG_OPCODE = (31u << OPCODE_SHIFT | 104u << 1),
284
285 RLWINM_OPCODE = (21u << OPCODE_SHIFT),
286 CLRRWI_OPCODE = RLWINM_OPCODE,
287 CLRLWI_OPCODE = RLWINM_OPCODE,
288
289 RLWIMI_OPCODE = (20u << OPCODE_SHIFT),
290
291 SLW_OPCODE = (31u << OPCODE_SHIFT | 24u << 1),
292 SLWI_OPCODE = RLWINM_OPCODE,
293 SRW_OPCODE = (31u << OPCODE_SHIFT | 536u << 1),
294 SRWI_OPCODE = RLWINM_OPCODE,
295 SRAW_OPCODE = (31u << OPCODE_SHIFT | 792u << 1),
296 SRAWI_OPCODE = (31u << OPCODE_SHIFT | 824u << 1),
297
298 CMP_OPCODE = (31u << OPCODE_SHIFT | 0u << 1),
299 CMPI_OPCODE = (11u << OPCODE_SHIFT),
300 CMPL_OPCODE = (31u << OPCODE_SHIFT | 32u << 1),
301 CMPLI_OPCODE = (10u << OPCODE_SHIFT),
302
303 ISEL_OPCODE = (31u << OPCODE_SHIFT | 15u << 1),
304
305 // Special purpose registers
306 MTSPR_OPCODE = (31u << OPCODE_SHIFT | 467u << 1),
307 MFSPR_OPCODE = (31u << OPCODE_SHIFT | 339u << 1),
308
309 MTXER_OPCODE = (MTSPR_OPCODE | 1 << SPR_0_4_SHIFT),
310 MFXER_OPCODE = (MFSPR_OPCODE | 1 << SPR_0_4_SHIFT),
311
312 MTDSCR_OPCODE = (MTSPR_OPCODE | 3 << SPR_0_4_SHIFT),
313 MFDSCR_OPCODE = (MFSPR_OPCODE | 3 << SPR_0_4_SHIFT),
314
315 MTLR_OPCODE = (MTSPR_OPCODE | 8 << SPR_0_4_SHIFT),
316 MFLR_OPCODE = (MFSPR_OPCODE | 8 << SPR_0_4_SHIFT),
317
318 MTCTR_OPCODE = (MTSPR_OPCODE | 9 << SPR_0_4_SHIFT),
319 MFCTR_OPCODE = (MFSPR_OPCODE | 9 << SPR_0_4_SHIFT),
320
321 // Attention: Higher and lower half are inserted in reversed order.
322 MTTFHAR_OPCODE = (MTSPR_OPCODE | 4 << SPR_5_9_SHIFT | 0 << SPR_0_4_SHIFT),
323 MFTFHAR_OPCODE = (MFSPR_OPCODE | 4 << SPR_5_9_SHIFT | 0 << SPR_0_4_SHIFT),
324 MTTFIAR_OPCODE = (MTSPR_OPCODE | 4 << SPR_5_9_SHIFT | 1 << SPR_0_4_SHIFT),
325 MFTFIAR_OPCODE = (MFSPR_OPCODE | 4 << SPR_5_9_SHIFT | 1 << SPR_0_4_SHIFT),
326 MTTEXASR_OPCODE = (MTSPR_OPCODE | 4 << SPR_5_9_SHIFT | 2 << SPR_0_4_SHIFT),
327 MFTEXASR_OPCODE = (MFSPR_OPCODE | 4 << SPR_5_9_SHIFT | 2 << SPR_0_4_SHIFT),
328 MTTEXASRU_OPCODE = (MTSPR_OPCODE | 4 << SPR_5_9_SHIFT | 3 << SPR_0_4_SHIFT),
329 MFTEXASRU_OPCODE = (MFSPR_OPCODE | 4 << SPR_5_9_SHIFT | 3 << SPR_0_4_SHIFT),
330
331 MTVRSAVE_OPCODE = (MTSPR_OPCODE | 8 << SPR_5_9_SHIFT | 0 << SPR_0_4_SHIFT),
332 MFVRSAVE_OPCODE = (MFSPR_OPCODE | 8 << SPR_5_9_SHIFT | 0 << SPR_0_4_SHIFT),
333
334 MFTB_OPCODE = (MFSPR_OPCODE | 8 << SPR_5_9_SHIFT | 12 << SPR_0_4_SHIFT),
335
336 MTCRF_OPCODE = (31u << OPCODE_SHIFT | 144u << 1),
337 MFCR_OPCODE = (31u << OPCODE_SHIFT | 19u << 1),
338 MCRF_OPCODE = (19u << OPCODE_SHIFT | 0u << 1),
339
340 // condition register logic instructions
341 CRAND_OPCODE = (19u << OPCODE_SHIFT | 257u << 1),
342 CRNAND_OPCODE = (19u << OPCODE_SHIFT | 225u << 1),
343 CROR_OPCODE = (19u << OPCODE_SHIFT | 449u << 1),
344 CRXOR_OPCODE = (19u << OPCODE_SHIFT | 193u << 1),
345 CRNOR_OPCODE = (19u << OPCODE_SHIFT | 33u << 1),
346 CREQV_OPCODE = (19u << OPCODE_SHIFT | 289u << 1),
347 CRANDC_OPCODE = (19u << OPCODE_SHIFT | 129u << 1),
348 CRORC_OPCODE = (19u << OPCODE_SHIFT | 417u << 1),
349
350 BCLR_OPCODE = (19u << OPCODE_SHIFT | 16u << 1),
351 BXX_OPCODE = (18u << OPCODE_SHIFT),
352 BCXX_OPCODE = (16u << OPCODE_SHIFT),
353
354 // CTR-related opcodes
355 BCCTR_OPCODE = (19u << OPCODE_SHIFT | 528u << 1),
356
357 LWZ_OPCODE = (32u << OPCODE_SHIFT),
358 LWZX_OPCODE = (31u << OPCODE_SHIFT | 23u << 1),
1059 static int bh( int x) { return opp_u_field(x, 20, 19); }
1060 static int bi( int x) { return opp_u_field(x, 15, 11); }
1061 static int bi0(ConditionRegister cr, Condition c) { return (cr->encoding() << 2) | c; }
1062 static int bo( int x) { return opp_u_field(x, 10, 6); }
1063 static int bt( int x) { return opp_u_field(x, 10, 6); }
1064 static int d1( int x) { return opp_s_field(x, 31, 16); }
1065 static int ds( int x) { assert((x & 0x3) == 0, "unaligned offset"); return opp_s_field(x, 31, 16); }
1066 static int eh( int x) { return opp_u_field(x, 31, 31); }
1067 static int flm( int x) { return opp_u_field(x, 14, 7); }
1068 static int fra( FloatRegister r) { return fra(r->encoding());}
1069 static int frb( FloatRegister r) { return frb(r->encoding());}
1070 static int frc( FloatRegister r) { return frc(r->encoding());}
1071 static int frs( FloatRegister r) { return frs(r->encoding());}
1072 static int frt( FloatRegister r) { return frt(r->encoding());}
1073 static int fra( int x) { return opp_u_field(x, 15, 11); }
1074 static int frb( int x) { return opp_u_field(x, 20, 16); }
1075 static int frc( int x) { return opp_u_field(x, 25, 21); }
1076 static int frs( int x) { return opp_u_field(x, 10, 6); }
1077 static int frt( int x) { return opp_u_field(x, 10, 6); }
1078 static int fxm( int x) { return opp_u_field(x, 19, 12); }
1079 static int l10( int x) { return opp_u_field(x, 10, 10); }
1080 static int l14( int x) { return opp_u_field(x, 15, 14); }
1081 static int l15( int x) { return opp_u_field(x, 15, 15); }
1082 static int l910( int x) { return opp_u_field(x, 10, 9); }
1083 static int e1215( int x) { return opp_u_field(x, 15, 12); }
1084 static int lev( int x) { return opp_u_field(x, 26, 20); }
1085 static int li( int x) { return opp_s_field(x, 29, 6); }
1086 static int lk( int x) { return opp_u_field(x, 31, 31); }
1087 static int mb2125( int x) { return opp_u_field(x, 25, 21); }
1088 static int me2630( int x) { return opp_u_field(x, 30, 26); }
1089 static int mb2126( int x) { return opp_u_field(((x & 0x1f) << 1) | ((x & 0x20) >> 5), 26, 21); }
1090 static int me2126( int x) { return mb2126(x); }
1091 static int nb( int x) { return opp_u_field(x, 20, 16); }
1092 //static int opcd( int x) { return opp_u_field(x, 5, 0); } // is contained in our opcodes
1093 static int oe( int x) { return opp_u_field(x, 21, 21); }
1094 static int ra( Register r) { return ra(r->encoding()); }
1095 static int ra( int x) { return opp_u_field(x, 15, 11); }
1096 static int rb( Register r) { return rb(r->encoding()); }
1097 static int rb( int x) { return opp_u_field(x, 20, 16); }
1098 static int rc( int x) { return opp_u_field(x, 31, 31); }
1099 static int rs( Register r) { return rs(r->encoding()); }
1426
1427
1428 private:
1429 // PPC 1, section 3.3.9, Fixed-Point Compare Instructions
1430 inline void cmpi( ConditionRegister bf, int l, Register a, int si16);
1431 inline void cmp( ConditionRegister bf, int l, Register a, Register b);
1432 inline void cmpli(ConditionRegister bf, int l, Register a, int ui16);
1433 inline void cmpl( ConditionRegister bf, int l, Register a, Register b);
1434
1435 public:
1436 // extended mnemonics of Compare Instructions
1437 inline void cmpwi( ConditionRegister crx, Register a, int si16);
1438 inline void cmpdi( ConditionRegister crx, Register a, int si16);
1439 inline void cmpw( ConditionRegister crx, Register a, Register b);
1440 inline void cmpd( ConditionRegister crx, Register a, Register b);
1441 inline void cmplwi(ConditionRegister crx, Register a, int ui16);
1442 inline void cmpldi(ConditionRegister crx, Register a, int ui16);
1443 inline void cmplw( ConditionRegister crx, Register a, Register b);
1444 inline void cmpld( ConditionRegister crx, Register a, Register b);
1445
1446 inline void isel( Register d, Register a, Register b, int bc);
1447 // Convenient version which takes: Condition register, Condition code and invert flag. Omit b to keep old value.
1448 inline void isel( Register d, ConditionRegister cr, Condition cc, bool inv, Register a, Register b = noreg);
1449 // Set d = 0 if (cr.cc) equals 1, otherwise b.
1450 inline void isel_0( Register d, ConditionRegister cr, Condition cc, Register b = noreg);
1451
1452 // PPC 1, section 3.3.11, Fixed-Point Logical Instructions
1453 void andi( Register a, Register s, long ui16); // optimized version
1454 inline void andi_( Register a, Register s, int ui16);
1455 inline void andis_( Register a, Register s, int ui16);
1456 inline void ori( Register a, Register s, int ui16);
1457 inline void oris( Register a, Register s, int ui16);
1458 inline void xori( Register a, Register s, int ui16);
1459 inline void xoris( Register a, Register s, int ui16);
1460 inline void andr( Register a, Register s, Register b); // suffixed by 'r' as 'and' is C++ keyword
1461 inline void and_( Register a, Register s, Register b);
1462 // Turn or0(rx,rx,rx) into a nop and avoid that we accidently emit a
1463 // SMT-priority change instruction (see SMT instructions below).
1464 inline void or_unchecked(Register a, Register s, Register b);
1465 inline void orr( Register a, Register s, Register b); // suffixed by 'r' as 'or' is C++ keyword
1625 inline void stbu( Register d, int si16, Register s1);
1626
1627 inline void stdx( Register d, Register s1, Register s2);
1628 inline void std( Register d, int si16, Register s1);
1629 inline void stdu( Register d, int si16, Register s1);
1630 inline void stdux(Register s, Register a, Register b);
1631 inline void stdbrx( Register d, Register s1, Register s2);
1632
1633 inline void st_ptr(Register d, int si16, Register s1);
1634 DEBUG_ONLY(inline void st_ptr(Register d, ByteSize b, Register s1);)
1635
1636 // PPC 1, section 3.3.13 Move To/From System Register Instructions
1637 inline void mtlr( Register s1);
1638 inline void mflr( Register d);
1639 inline void mtctr(Register s1);
1640 inline void mfctr(Register d);
1641 inline void mtcrf(int fxm, Register s);
1642 inline void mfcr( Register d);
1643 inline void mcrf( ConditionRegister crd, ConditionRegister cra);
1644 inline void mtcr( Register s);
1645
1646 // Special purpose registers
1647 // Exception Register
1648 inline void mtxer(Register s1);
1649 inline void mfxer(Register d);
1650 // Vector Register Save Register
1651 inline void mtvrsave(Register s1);
1652 inline void mfvrsave(Register d);
1653 // Timebase
1654 inline void mftb(Register d);
1655 // Introduced with Power 8:
1656 // Data Stream Control Register
1657 inline void mtdscr(Register s1);
1658 inline void mfdscr(Register d );
1659 // Transactional Memory Registers
1660 inline void mftfhar(Register d);
1661 inline void mftfiar(Register d);
1662 inline void mftexasr(Register d);
1663 inline void mftexasru(Register d);
1664
|
1 /*
2 * Copyright (c) 2002, 2018, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2012, 2018 SAP SE. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
282
283 NEG_OPCODE = (31u << OPCODE_SHIFT | 104u << 1),
284
285 RLWINM_OPCODE = (21u << OPCODE_SHIFT),
286 CLRRWI_OPCODE = RLWINM_OPCODE,
287 CLRLWI_OPCODE = RLWINM_OPCODE,
288
289 RLWIMI_OPCODE = (20u << OPCODE_SHIFT),
290
291 SLW_OPCODE = (31u << OPCODE_SHIFT | 24u << 1),
292 SLWI_OPCODE = RLWINM_OPCODE,
293 SRW_OPCODE = (31u << OPCODE_SHIFT | 536u << 1),
294 SRWI_OPCODE = RLWINM_OPCODE,
295 SRAW_OPCODE = (31u << OPCODE_SHIFT | 792u << 1),
296 SRAWI_OPCODE = (31u << OPCODE_SHIFT | 824u << 1),
297
298 CMP_OPCODE = (31u << OPCODE_SHIFT | 0u << 1),
299 CMPI_OPCODE = (11u << OPCODE_SHIFT),
300 CMPL_OPCODE = (31u << OPCODE_SHIFT | 32u << 1),
301 CMPLI_OPCODE = (10u << OPCODE_SHIFT),
302 CMPRB_OPCODE = (31u << OPCODE_SHIFT | 192u << 1),
303 CMPEQB_OPCODE = (31u << OPCODE_SHIFT | 224u << 1),
304
305 ISEL_OPCODE = (31u << OPCODE_SHIFT | 15u << 1),
306
307 // Special purpose registers
308 MTSPR_OPCODE = (31u << OPCODE_SHIFT | 467u << 1),
309 MFSPR_OPCODE = (31u << OPCODE_SHIFT | 339u << 1),
310
311 MTXER_OPCODE = (MTSPR_OPCODE | 1 << SPR_0_4_SHIFT),
312 MFXER_OPCODE = (MFSPR_OPCODE | 1 << SPR_0_4_SHIFT),
313
314 MTDSCR_OPCODE = (MTSPR_OPCODE | 3 << SPR_0_4_SHIFT),
315 MFDSCR_OPCODE = (MFSPR_OPCODE | 3 << SPR_0_4_SHIFT),
316
317 MTLR_OPCODE = (MTSPR_OPCODE | 8 << SPR_0_4_SHIFT),
318 MFLR_OPCODE = (MFSPR_OPCODE | 8 << SPR_0_4_SHIFT),
319
320 MTCTR_OPCODE = (MTSPR_OPCODE | 9 << SPR_0_4_SHIFT),
321 MFCTR_OPCODE = (MFSPR_OPCODE | 9 << SPR_0_4_SHIFT),
322
323 // Attention: Higher and lower half are inserted in reversed order.
324 MTTFHAR_OPCODE = (MTSPR_OPCODE | 4 << SPR_5_9_SHIFT | 0 << SPR_0_4_SHIFT),
325 MFTFHAR_OPCODE = (MFSPR_OPCODE | 4 << SPR_5_9_SHIFT | 0 << SPR_0_4_SHIFT),
326 MTTFIAR_OPCODE = (MTSPR_OPCODE | 4 << SPR_5_9_SHIFT | 1 << SPR_0_4_SHIFT),
327 MFTFIAR_OPCODE = (MFSPR_OPCODE | 4 << SPR_5_9_SHIFT | 1 << SPR_0_4_SHIFT),
328 MTTEXASR_OPCODE = (MTSPR_OPCODE | 4 << SPR_5_9_SHIFT | 2 << SPR_0_4_SHIFT),
329 MFTEXASR_OPCODE = (MFSPR_OPCODE | 4 << SPR_5_9_SHIFT | 2 << SPR_0_4_SHIFT),
330 MTTEXASRU_OPCODE = (MTSPR_OPCODE | 4 << SPR_5_9_SHIFT | 3 << SPR_0_4_SHIFT),
331 MFTEXASRU_OPCODE = (MFSPR_OPCODE | 4 << SPR_5_9_SHIFT | 3 << SPR_0_4_SHIFT),
332
333 MTVRSAVE_OPCODE = (MTSPR_OPCODE | 8 << SPR_5_9_SHIFT | 0 << SPR_0_4_SHIFT),
334 MFVRSAVE_OPCODE = (MFSPR_OPCODE | 8 << SPR_5_9_SHIFT | 0 << SPR_0_4_SHIFT),
335
336 MFTB_OPCODE = (MFSPR_OPCODE | 8 << SPR_5_9_SHIFT | 12 << SPR_0_4_SHIFT),
337
338 MTCRF_OPCODE = (31u << OPCODE_SHIFT | 144u << 1),
339 MFCR_OPCODE = (31u << OPCODE_SHIFT | 19u << 1),
340 MCRF_OPCODE = (19u << OPCODE_SHIFT | 0u << 1),
341 SETB_OPCODE = (31u << OPCODE_SHIFT | 128u << 1),
342
343 // condition register logic instructions
344 CRAND_OPCODE = (19u << OPCODE_SHIFT | 257u << 1),
345 CRNAND_OPCODE = (19u << OPCODE_SHIFT | 225u << 1),
346 CROR_OPCODE = (19u << OPCODE_SHIFT | 449u << 1),
347 CRXOR_OPCODE = (19u << OPCODE_SHIFT | 193u << 1),
348 CRNOR_OPCODE = (19u << OPCODE_SHIFT | 33u << 1),
349 CREQV_OPCODE = (19u << OPCODE_SHIFT | 289u << 1),
350 CRANDC_OPCODE = (19u << OPCODE_SHIFT | 129u << 1),
351 CRORC_OPCODE = (19u << OPCODE_SHIFT | 417u << 1),
352
353 BCLR_OPCODE = (19u << OPCODE_SHIFT | 16u << 1),
354 BXX_OPCODE = (18u << OPCODE_SHIFT),
355 BCXX_OPCODE = (16u << OPCODE_SHIFT),
356
357 // CTR-related opcodes
358 BCCTR_OPCODE = (19u << OPCODE_SHIFT | 528u << 1),
359
360 LWZ_OPCODE = (32u << OPCODE_SHIFT),
361 LWZX_OPCODE = (31u << OPCODE_SHIFT | 23u << 1),
1062 static int bh( int x) { return opp_u_field(x, 20, 19); }
1063 static int bi( int x) { return opp_u_field(x, 15, 11); }
1064 static int bi0(ConditionRegister cr, Condition c) { return (cr->encoding() << 2) | c; }
1065 static int bo( int x) { return opp_u_field(x, 10, 6); }
1066 static int bt( int x) { return opp_u_field(x, 10, 6); }
1067 static int d1( int x) { return opp_s_field(x, 31, 16); }
1068 static int ds( int x) { assert((x & 0x3) == 0, "unaligned offset"); return opp_s_field(x, 31, 16); }
1069 static int eh( int x) { return opp_u_field(x, 31, 31); }
1070 static int flm( int x) { return opp_u_field(x, 14, 7); }
1071 static int fra( FloatRegister r) { return fra(r->encoding());}
1072 static int frb( FloatRegister r) { return frb(r->encoding());}
1073 static int frc( FloatRegister r) { return frc(r->encoding());}
1074 static int frs( FloatRegister r) { return frs(r->encoding());}
1075 static int frt( FloatRegister r) { return frt(r->encoding());}
1076 static int fra( int x) { return opp_u_field(x, 15, 11); }
1077 static int frb( int x) { return opp_u_field(x, 20, 16); }
1078 static int frc( int x) { return opp_u_field(x, 25, 21); }
1079 static int frs( int x) { return opp_u_field(x, 10, 6); }
1080 static int frt( int x) { return opp_u_field(x, 10, 6); }
1081 static int fxm( int x) { return opp_u_field(x, 19, 12); }
1082 static int l10( int x) { assert(x == 0 || x == 1, "must be 0 or 1"); return opp_u_field(x, 10, 10); }
1083 static int l14( int x) { return opp_u_field(x, 15, 14); }
1084 static int l15( int x) { return opp_u_field(x, 15, 15); }
1085 static int l910( int x) { return opp_u_field(x, 10, 9); }
1086 static int e1215( int x) { return opp_u_field(x, 15, 12); }
1087 static int lev( int x) { return opp_u_field(x, 26, 20); }
1088 static int li( int x) { return opp_s_field(x, 29, 6); }
1089 static int lk( int x) { return opp_u_field(x, 31, 31); }
1090 static int mb2125( int x) { return opp_u_field(x, 25, 21); }
1091 static int me2630( int x) { return opp_u_field(x, 30, 26); }
1092 static int mb2126( int x) { return opp_u_field(((x & 0x1f) << 1) | ((x & 0x20) >> 5), 26, 21); }
1093 static int me2126( int x) { return mb2126(x); }
1094 static int nb( int x) { return opp_u_field(x, 20, 16); }
1095 //static int opcd( int x) { return opp_u_field(x, 5, 0); } // is contained in our opcodes
1096 static int oe( int x) { return opp_u_field(x, 21, 21); }
1097 static int ra( Register r) { return ra(r->encoding()); }
1098 static int ra( int x) { return opp_u_field(x, 15, 11); }
1099 static int rb( Register r) { return rb(r->encoding()); }
1100 static int rb( int x) { return opp_u_field(x, 20, 16); }
1101 static int rc( int x) { return opp_u_field(x, 31, 31); }
1102 static int rs( Register r) { return rs(r->encoding()); }
1429
1430
1431 private:
1432 // PPC 1, section 3.3.9, Fixed-Point Compare Instructions
1433 inline void cmpi( ConditionRegister bf, int l, Register a, int si16);
1434 inline void cmp( ConditionRegister bf, int l, Register a, Register b);
1435 inline void cmpli(ConditionRegister bf, int l, Register a, int ui16);
1436 inline void cmpl( ConditionRegister bf, int l, Register a, Register b);
1437
1438 public:
1439 // extended mnemonics of Compare Instructions
1440 inline void cmpwi( ConditionRegister crx, Register a, int si16);
1441 inline void cmpdi( ConditionRegister crx, Register a, int si16);
1442 inline void cmpw( ConditionRegister crx, Register a, Register b);
1443 inline void cmpd( ConditionRegister crx, Register a, Register b);
1444 inline void cmplwi(ConditionRegister crx, Register a, int ui16);
1445 inline void cmpldi(ConditionRegister crx, Register a, int ui16);
1446 inline void cmplw( ConditionRegister crx, Register a, Register b);
1447 inline void cmpld( ConditionRegister crx, Register a, Register b);
1448
1449 // >= Power9
1450 inline void cmprb( ConditionRegister bf, int l, Register a, Register b);
1451 inline void cmpeqb(ConditionRegister bf, Register a, Register b);
1452
1453 inline void isel( Register d, Register a, Register b, int bc);
1454 // Convenient version which takes: Condition register, Condition code and invert flag. Omit b to keep old value.
1455 inline void isel( Register d, ConditionRegister cr, Condition cc, bool inv, Register a, Register b = noreg);
1456 // Set d = 0 if (cr.cc) equals 1, otherwise b.
1457 inline void isel_0( Register d, ConditionRegister cr, Condition cc, Register b = noreg);
1458
1459 // PPC 1, section 3.3.11, Fixed-Point Logical Instructions
1460 void andi( Register a, Register s, long ui16); // optimized version
1461 inline void andi_( Register a, Register s, int ui16);
1462 inline void andis_( Register a, Register s, int ui16);
1463 inline void ori( Register a, Register s, int ui16);
1464 inline void oris( Register a, Register s, int ui16);
1465 inline void xori( Register a, Register s, int ui16);
1466 inline void xoris( Register a, Register s, int ui16);
1467 inline void andr( Register a, Register s, Register b); // suffixed by 'r' as 'and' is C++ keyword
1468 inline void and_( Register a, Register s, Register b);
1469 // Turn or0(rx,rx,rx) into a nop and avoid that we accidently emit a
1470 // SMT-priority change instruction (see SMT instructions below).
1471 inline void or_unchecked(Register a, Register s, Register b);
1472 inline void orr( Register a, Register s, Register b); // suffixed by 'r' as 'or' is C++ keyword
1632 inline void stbu( Register d, int si16, Register s1);
1633
1634 inline void stdx( Register d, Register s1, Register s2);
1635 inline void std( Register d, int si16, Register s1);
1636 inline void stdu( Register d, int si16, Register s1);
1637 inline void stdux(Register s, Register a, Register b);
1638 inline void stdbrx( Register d, Register s1, Register s2);
1639
1640 inline void st_ptr(Register d, int si16, Register s1);
1641 DEBUG_ONLY(inline void st_ptr(Register d, ByteSize b, Register s1);)
1642
1643 // PPC 1, section 3.3.13 Move To/From System Register Instructions
1644 inline void mtlr( Register s1);
1645 inline void mflr( Register d);
1646 inline void mtctr(Register s1);
1647 inline void mfctr(Register d);
1648 inline void mtcrf(int fxm, Register s);
1649 inline void mfcr( Register d);
1650 inline void mcrf( ConditionRegister crd, ConditionRegister cra);
1651 inline void mtcr( Register s);
1652 // >= Power9
1653 inline void setb( Register d, ConditionRegister cra);
1654
1655 // Special purpose registers
1656 // Exception Register
1657 inline void mtxer(Register s1);
1658 inline void mfxer(Register d);
1659 // Vector Register Save Register
1660 inline void mtvrsave(Register s1);
1661 inline void mfvrsave(Register d);
1662 // Timebase
1663 inline void mftb(Register d);
1664 // Introduced with Power 8:
1665 // Data Stream Control Register
1666 inline void mtdscr(Register s1);
1667 inline void mfdscr(Register d );
1668 // Transactional Memory Registers
1669 inline void mftfhar(Register d);
1670 inline void mftfiar(Register d);
1671 inline void mftexasr(Register d);
1672 inline void mftexasru(Register d);
1673
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