419 RLDICL_OPCODE = (30u << OPCODE_SHIFT | 0u << XO_27_29_SHIFT), // MD-FORM
420 RLDIC_OPCODE = (30u << OPCODE_SHIFT | 2u << XO_27_29_SHIFT), // MD-FORM
421 RLDIMI_OPCODE = (30u << OPCODE_SHIFT | 3u << XO_27_29_SHIFT), // MD-FORM
422
423 SRADI_OPCODE = (31u << OPCODE_SHIFT | 413u << XO_21_29_SHIFT), // XS-FORM
424
425 SLD_OPCODE = (31u << OPCODE_SHIFT | 27u << 1), // X-FORM
426 SRD_OPCODE = (31u << OPCODE_SHIFT | 539u << 1), // X-FORM
427 SRAD_OPCODE = (31u << OPCODE_SHIFT | 794u << 1), // X-FORM
428
429 MULLD_OPCODE = (31u << OPCODE_SHIFT | 233u << 1), // XO-FORM
430 MULHD_OPCODE = (31u << OPCODE_SHIFT | 73u << 1), // XO-FORM
431 MULHDU_OPCODE = (31u << OPCODE_SHIFT | 9u << 1), // XO-FORM
432 DIVD_OPCODE = (31u << OPCODE_SHIFT | 489u << 1), // XO-FORM
433
434 CNTLZD_OPCODE = (31u << OPCODE_SHIFT | 58u << XO_21_30_SHIFT), // X-FORM
435 CNTTZD_OPCODE = (31u << OPCODE_SHIFT | 570u << XO_21_30_SHIFT), // X-FORM
436 NAND_OPCODE = (31u << OPCODE_SHIFT | 476u << XO_21_30_SHIFT), // X-FORM
437 NOR_OPCODE = (31u << OPCODE_SHIFT | 124u << XO_21_30_SHIFT), // X-FORM
438
439
440 // opcodes only used for floating arithmetic
441 FADD_OPCODE = (63u << OPCODE_SHIFT | 21u << 1),
442 FADDS_OPCODE = (59u << OPCODE_SHIFT | 21u << 1),
443 FCMPU_OPCODE = (63u << OPCODE_SHIFT | 00u << 1),
444 FDIV_OPCODE = (63u << OPCODE_SHIFT | 18u << 1),
445 FDIVS_OPCODE = (59u << OPCODE_SHIFT | 18u << 1),
446 FMR_OPCODE = (63u << OPCODE_SHIFT | 72u << 1),
447 FRIN_OPCODE = (63u << OPCODE_SHIFT | 392u << 1),
448 FRIP_OPCODE = (63u << OPCODE_SHIFT | 456u << 1),
449 FRIM_OPCODE = (63u << OPCODE_SHIFT | 488u << 1),
450 // These are special Power6 opcodes, reused for "lfdepx" and "stfdepx"
451 // on Power7. Do not use.
452 // MFFGPR_OPCODE = (31u << OPCODE_SHIFT | 607u << 1),
453 // MFTGPR_OPCODE = (31u << OPCODE_SHIFT | 735u << 1),
454 CMPB_OPCODE = (31u << OPCODE_SHIFT | 508 << 1),
455 POPCNTB_OPCODE = (31u << OPCODE_SHIFT | 122 << 1),
456 POPCNTW_OPCODE = (31u << OPCODE_SHIFT | 378 << 1),
457 POPCNTD_OPCODE = (31u << OPCODE_SHIFT | 506 << 1),
458 FABS_OPCODE = (63u << OPCODE_SHIFT | 264u << 1),
498
499 FSQRT_OPCODE = (63u << OPCODE_SHIFT | 22u << 1), // A-FORM
500 FSQRTS_OPCODE = (59u << OPCODE_SHIFT | 22u << 1), // A-FORM
501
502 // Vector instruction support for >= Power6
503 // Vector Storage Access
504 LVEBX_OPCODE = (31u << OPCODE_SHIFT | 7u << 1),
505 LVEHX_OPCODE = (31u << OPCODE_SHIFT | 39u << 1),
506 LVEWX_OPCODE = (31u << OPCODE_SHIFT | 71u << 1),
507 LVX_OPCODE = (31u << OPCODE_SHIFT | 103u << 1),
508 LVXL_OPCODE = (31u << OPCODE_SHIFT | 359u << 1),
509 STVEBX_OPCODE = (31u << OPCODE_SHIFT | 135u << 1),
510 STVEHX_OPCODE = (31u << OPCODE_SHIFT | 167u << 1),
511 STVEWX_OPCODE = (31u << OPCODE_SHIFT | 199u << 1),
512 STVX_OPCODE = (31u << OPCODE_SHIFT | 231u << 1),
513 STVXL_OPCODE = (31u << OPCODE_SHIFT | 487u << 1),
514 LVSL_OPCODE = (31u << OPCODE_SHIFT | 6u << 1),
515 LVSR_OPCODE = (31u << OPCODE_SHIFT | 38u << 1),
516
517 // Vector-Scalar (VSX) instruction support.
518 LXVD2X_OPCODE = (31u << OPCODE_SHIFT | 844u << 1),
519 STXVD2X_OPCODE = (31u << OPCODE_SHIFT | 972u << 1),
520 MTVSRD_OPCODE = (31u << OPCODE_SHIFT | 179u << 1),
521 MTVSRWZ_OPCODE = (31u << OPCODE_SHIFT | 243u << 1),
522 MFVSRD_OPCODE = (31u << OPCODE_SHIFT | 51u << 1),
523 MTVSRWA_OPCODE = (31u << OPCODE_SHIFT | 211u << 1),
524 MFVSRWZ_OPCODE = (31u << OPCODE_SHIFT | 115u << 1),
525 XXPERMDI_OPCODE= (60u << OPCODE_SHIFT | 10u << 3),
526 XXMRGHW_OPCODE = (60u << OPCODE_SHIFT | 18u << 3),
527 XXMRGLW_OPCODE = (60u << OPCODE_SHIFT | 50u << 3),
528 XXSPLTW_OPCODE = (60u << OPCODE_SHIFT | 164u << 2),
529 XXLOR_OPCODE = (60u << OPCODE_SHIFT | 146u << 3),
530 XXLXOR_OPCODE = (60u << OPCODE_SHIFT | 154u << 3),
531 XXLEQV_OPCODE = (60u << OPCODE_SHIFT | 186u << 3),
532 XVDIVSP_OPCODE = (60u << OPCODE_SHIFT | 88u << 3),
533 XXBRD_OPCODE = (60u << OPCODE_SHIFT | 475u << 2 | 23u << 16), // XX2-FORM
534 XXBRW_OPCODE = (60u << OPCODE_SHIFT | 475u << 2 | 15u << 16), // XX2-FORM
535 XVDIVDP_OPCODE = (60u << OPCODE_SHIFT | 120u << 3),
536 XVABSSP_OPCODE = (60u << OPCODE_SHIFT | 409u << 2),
537 XVABSDP_OPCODE = (60u << OPCODE_SHIFT | 473u << 2),
538 XVNEGSP_OPCODE = (60u << OPCODE_SHIFT | 441u << 2),
539 XVNEGDP_OPCODE = (60u << OPCODE_SHIFT | 505u << 2),
540 XVSQRTSP_OPCODE= (60u << OPCODE_SHIFT | 139u << 2),
541 XVSQRTDP_OPCODE= (60u << OPCODE_SHIFT | 203u << 2),
542 XSCVDPSPN_OPCODE=(60u << OPCODE_SHIFT | 267u << 2),
543 XVADDDP_OPCODE = (60u << OPCODE_SHIFT | 96u << 3),
544 XVSUBDP_OPCODE = (60u << OPCODE_SHIFT | 104u << 3),
545 XVMULSP_OPCODE = (60u << OPCODE_SHIFT | 80u << 3),
546 XVMULDP_OPCODE = (60u << OPCODE_SHIFT | 112u << 3),
547 XVMADDASP_OPCODE=(60u << OPCODE_SHIFT | 65u << 3),
548 XVMADDADP_OPCODE=(60u << OPCODE_SHIFT | 97u << 3),
549 XVMSUBASP_OPCODE=(60u << OPCODE_SHIFT | 81u << 3),
550 XVMSUBADP_OPCODE=(60u << OPCODE_SHIFT | 113u << 3),
551 XVNMSUBASP_OPCODE=(60u<< OPCODE_SHIFT | 209u << 3),
552 XVNMSUBADP_OPCODE=(60u<< OPCODE_SHIFT | 241u << 3),
553 XVRDPI_OPCODE = (60u << OPCODE_SHIFT | 201u << 2),
554 XVRDPIM_OPCODE = (60u << OPCODE_SHIFT | 249u << 2),
571 VUPKHSB_OPCODE = (4u << OPCODE_SHIFT | 526u ),
572 VUPKHSH_OPCODE = (4u << OPCODE_SHIFT | 590u ),
573 VUPKLPX_OPCODE = (4u << OPCODE_SHIFT | 974u ),
574 VUPKLSB_OPCODE = (4u << OPCODE_SHIFT | 654u ),
575 VUPKLSH_OPCODE = (4u << OPCODE_SHIFT | 718u ),
576
577 VMRGHB_OPCODE = (4u << OPCODE_SHIFT | 12u ),
578 VMRGHW_OPCODE = (4u << OPCODE_SHIFT | 140u ),
579 VMRGHH_OPCODE = (4u << OPCODE_SHIFT | 76u ),
580 VMRGLB_OPCODE = (4u << OPCODE_SHIFT | 268u ),
581 VMRGLW_OPCODE = (4u << OPCODE_SHIFT | 396u ),
582 VMRGLH_OPCODE = (4u << OPCODE_SHIFT | 332u ),
583
584 VSPLT_OPCODE = (4u << OPCODE_SHIFT | 524u ),
585 VSPLTH_OPCODE = (4u << OPCODE_SHIFT | 588u ),
586 VSPLTW_OPCODE = (4u << OPCODE_SHIFT | 652u ),
587 VSPLTISB_OPCODE= (4u << OPCODE_SHIFT | 780u ),
588 VSPLTISH_OPCODE= (4u << OPCODE_SHIFT | 844u ),
589 VSPLTISW_OPCODE= (4u << OPCODE_SHIFT | 908u ),
590
591 VPERM_OPCODE = (4u << OPCODE_SHIFT | 43u ),
592 VSEL_OPCODE = (4u << OPCODE_SHIFT | 42u ),
593
594 VSL_OPCODE = (4u << OPCODE_SHIFT | 452u ),
595 VSLDOI_OPCODE = (4u << OPCODE_SHIFT | 44u ),
596 VSLO_OPCODE = (4u << OPCODE_SHIFT | 1036u ),
597 VSR_OPCODE = (4u << OPCODE_SHIFT | 708u ),
598 VSRO_OPCODE = (4u << OPCODE_SHIFT | 1100u ),
599
600 // Vector Integer
601 VADDCUW_OPCODE = (4u << OPCODE_SHIFT | 384u ),
602 VADDSHS_OPCODE = (4u << OPCODE_SHIFT | 832u ),
603 VADDSBS_OPCODE = (4u << OPCODE_SHIFT | 768u ),
604 VADDSWS_OPCODE = (4u << OPCODE_SHIFT | 896u ),
605 VADDUBM_OPCODE = (4u << OPCODE_SHIFT | 0u ),
606 VADDUWM_OPCODE = (4u << OPCODE_SHIFT | 128u ),
607 VADDUHM_OPCODE = (4u << OPCODE_SHIFT | 64u ),
608 VADDUDM_OPCODE = (4u << OPCODE_SHIFT | 192u ),
609 VADDUBS_OPCODE = (4u << OPCODE_SHIFT | 512u ),
610 VADDUWS_OPCODE = (4u << OPCODE_SHIFT | 640u ),
1078 static int bh( int x) { return opp_u_field(x, 20, 19); }
1079 static int bi( int x) { return opp_u_field(x, 15, 11); }
1080 static int bi0(ConditionRegister cr, Condition c) { return (cr->encoding() << 2) | c; }
1081 static int bo( int x) { return opp_u_field(x, 10, 6); }
1082 static int bt( int x) { return opp_u_field(x, 10, 6); }
1083 static int d1( int x) { return opp_s_field(x, 31, 16); }
1084 static int ds( int x) { assert((x & 0x3) == 0, "unaligned offset"); return opp_s_field(x, 31, 16); }
1085 static int eh( int x) { return opp_u_field(x, 31, 31); }
1086 static int flm( int x) { return opp_u_field(x, 14, 7); }
1087 static int fra( FloatRegister r) { return fra(r->encoding());}
1088 static int frb( FloatRegister r) { return frb(r->encoding());}
1089 static int frc( FloatRegister r) { return frc(r->encoding());}
1090 static int frs( FloatRegister r) { return frs(r->encoding());}
1091 static int frt( FloatRegister r) { return frt(r->encoding());}
1092 static int fra( int x) { return opp_u_field(x, 15, 11); }
1093 static int frb( int x) { return opp_u_field(x, 20, 16); }
1094 static int frc( int x) { return opp_u_field(x, 25, 21); }
1095 static int frs( int x) { return opp_u_field(x, 10, 6); }
1096 static int frt( int x) { return opp_u_field(x, 10, 6); }
1097 static int fxm( int x) { return opp_u_field(x, 19, 12); }
1098 static int l10( int x) { assert(x == 0 || x == 1, "must be 0 or 1"); return opp_u_field(x, 10, 10); }
1099 static int l14( int x) { return opp_u_field(x, 15, 14); }
1100 static int l15( int x) { return opp_u_field(x, 15, 15); }
1101 static int l910( int x) { return opp_u_field(x, 10, 9); }
1102 static int e1215( int x) { return opp_u_field(x, 15, 12); }
1103 static int lev( int x) { return opp_u_field(x, 26, 20); }
1104 static int li( int x) { return opp_s_field(x, 29, 6); }
1105 static int lk( int x) { return opp_u_field(x, 31, 31); }
1106 static int mb2125( int x) { return opp_u_field(x, 25, 21); }
1107 static int me2630( int x) { return opp_u_field(x, 30, 26); }
1108 static int mb2126( int x) { return opp_u_field(((x & 0x1f) << 1) | ((x & 0x20) >> 5), 26, 21); }
1109 static int me2126( int x) { return mb2126(x); }
1110 static int nb( int x) { return opp_u_field(x, 20, 16); }
1111 //static int opcd( int x) { return opp_u_field(x, 5, 0); } // is contained in our opcodes
1112 static int oe( int x) { return opp_u_field(x, 21, 21); }
1113 static int ra( Register r) { return ra(r->encoding()); }
1114 static int ra( int x) { return opp_u_field(x, 15, 11); }
1115 static int rb( Register r) { return rb(r->encoding()); }
1116 static int rb( int x) { return opp_u_field(x, 20, 16); }
1117 static int rc( int x) { return opp_u_field(x, 31, 31); }
1144 // Support vector instructions for >= Power6.
1145 static int vra( int x) { return opp_u_field(x, 15, 11); }
1146 static int vrb( int x) { return opp_u_field(x, 20, 16); }
1147 static int vrc( int x) { return opp_u_field(x, 25, 21); }
1148 static int vrs( int x) { return opp_u_field(x, 10, 6); }
1149 static int vrt( int x) { return opp_u_field(x, 10, 6); }
1150
1151 static int vra( VectorRegister r) { return vra(r->encoding());}
1152 static int vrb( VectorRegister r) { return vrb(r->encoding());}
1153 static int vrc( VectorRegister r) { return vrc(r->encoding());}
1154 static int vrs( VectorRegister r) { return vrs(r->encoding());}
1155 static int vrt( VectorRegister r) { return vrt(r->encoding());}
1156
1157 // Only used on SHA sigma instructions (VX-form)
1158 static int vst( int x) { return opp_u_field(x, 16, 16); }
1159 static int vsix( int x) { return opp_u_field(x, 20, 17); }
1160
1161 // Support Vector-Scalar (VSX) instructions.
1162 static int vsra( int x) { return opp_u_field(x & 0x1F, 15, 11) | opp_u_field((x & 0x20) >> 5, 29, 29); }
1163 static int vsrb( int x) { return opp_u_field(x & 0x1F, 20, 16) | opp_u_field((x & 0x20) >> 5, 30, 30); }
1164 static int vsrs( int x) { return opp_u_field(x & 0x1F, 10, 6) | opp_u_field((x & 0x20) >> 5, 31, 31); }
1165 static int vsrt( int x) { return vsrs(x); }
1166 static int vsdm( int x) { return opp_u_field(x, 23, 22); }
1167
1168 static int vsra( VectorSRegister r) { return vsra(r->encoding());}
1169 static int vsrb( VectorSRegister r) { return vsrb(r->encoding());}
1170 static int vsrs( VectorSRegister r) { return vsrs(r->encoding());}
1171 static int vsrt( VectorSRegister r) { return vsrt(r->encoding());}
1172
1173 static int vsplt_uim( int x) { return opp_u_field(x, 15, 12); } // for vsplt* instructions
1174 static int vsplti_sim(int x) { return opp_u_field(x, 15, 11); } // for vsplti* instructions
1175 static int vsldoi_shb(int x) { return opp_u_field(x, 25, 22); } // for vsldoi instruction
1176 static int vcmp_rc( int x) { return opp_u_field(x, 21, 21); } // for vcmp* instructions
1177 static int xxsplt_uim(int x) { return opp_u_field(x, 15, 14); } // for xxsplt* instructions
1178
1179 //static int xo1( int x) { return opp_u_field(x, 29, 21); }// is contained in our opcodes
1180 //static int xo2( int x) { return opp_u_field(x, 30, 21); }// is contained in our opcodes
1181 //static int xo3( int x) { return opp_u_field(x, 30, 22); }// is contained in our opcodes
1182 //static int xo4( int x) { return opp_u_field(x, 30, 26); }// is contained in our opcodes
1183 //static int xo5( int x) { return opp_u_field(x, 29, 27); }// is contained in our opcodes
1184 //static int xo6( int x) { return opp_u_field(x, 30, 27); }// is contained in our opcodes
1185 //static int xo7( int x) { return opp_u_field(x, 31, 30); }// is contained in our opcodes
1186
1187 protected:
1188 // Compute relative address for branch.
1189 static intptr_t disp(intptr_t x, intptr_t off) {
1190 int xx = x - off;
1191 xx = xx >> 2;
1551 // extended mnemonics for Shift Instructions
1552 inline void sldi( Register a, Register s, int sh6);
1553 inline void sldi_( Register a, Register s, int sh6);
1554 inline void slwi( Register a, Register s, int sh5);
1555 inline void slwi_( Register a, Register s, int sh5);
1556 inline void srdi( Register a, Register s, int sh6);
1557 inline void srdi_( Register a, Register s, int sh6);
1558 inline void srwi( Register a, Register s, int sh5);
1559 inline void srwi_( Register a, Register s, int sh5);
1560
1561 inline void clrrdi( Register a, Register s, int ui6);
1562 inline void clrrdi_( Register a, Register s, int ui6);
1563 inline void clrldi( Register a, Register s, int ui6);
1564 inline void clrldi_( Register a, Register s, int ui6);
1565 inline void clrlsldi(Register a, Register s, int clrl6, int shl6);
1566 inline void clrlsldi_(Register a, Register s, int clrl6, int shl6);
1567 inline void extrdi( Register a, Register s, int n, int b);
1568 // testbit with condition register
1569 inline void testbitdi(ConditionRegister cr, Register a, Register s, int ui6);
1570
1571 // rotate instructions
1572 inline void rotldi( Register a, Register s, int n);
1573 inline void rotrdi( Register a, Register s, int n);
1574 inline void rotlwi( Register a, Register s, int n);
1575 inline void rotrwi( Register a, Register s, int n);
1576
1577 // Rotate Instructions
1578 inline void rldic( Register a, Register s, int sh6, int mb6);
1579 inline void rldic_( Register a, Register s, int sh6, int mb6);
1580 inline void rldicr( Register a, Register s, int sh6, int mb6);
1581 inline void rldicr_( Register a, Register s, int sh6, int mb6);
1582 inline void rldicl( Register a, Register s, int sh6, int mb6);
1583 inline void rldicl_( Register a, Register s, int sh6, int mb6);
1584 inline void rlwinm( Register a, Register s, int sh5, int mb5, int me5);
1585 inline void rlwinm_( Register a, Register s, int sh5, int mb5, int me5);
1586 inline void rldimi( Register a, Register s, int sh6, int mb6);
1587 inline void rldimi_( Register a, Register s, int sh6, int mb6);
1588 inline void rlwimi( Register a, Register s, int sh5, int mb5, int me5);
1589 inline void insrdi( Register a, Register s, int n, int b);
1590 inline void insrwi( Register a, Register s, int n, int b);
2093 inline void vpkuwus( VectorRegister d, VectorRegister a, VectorRegister b);
2094 inline void vupkhpx( VectorRegister d, VectorRegister b);
2095 inline void vupkhsb( VectorRegister d, VectorRegister b);
2096 inline void vupkhsh( VectorRegister d, VectorRegister b);
2097 inline void vupklpx( VectorRegister d, VectorRegister b);
2098 inline void vupklsb( VectorRegister d, VectorRegister b);
2099 inline void vupklsh( VectorRegister d, VectorRegister b);
2100 inline void vmrghb( VectorRegister d, VectorRegister a, VectorRegister b);
2101 inline void vmrghw( VectorRegister d, VectorRegister a, VectorRegister b);
2102 inline void vmrghh( VectorRegister d, VectorRegister a, VectorRegister b);
2103 inline void vmrglb( VectorRegister d, VectorRegister a, VectorRegister b);
2104 inline void vmrglw( VectorRegister d, VectorRegister a, VectorRegister b);
2105 inline void vmrglh( VectorRegister d, VectorRegister a, VectorRegister b);
2106 inline void vsplt( VectorRegister d, int ui4, VectorRegister b);
2107 inline void vsplth( VectorRegister d, int ui3, VectorRegister b);
2108 inline void vspltw( VectorRegister d, int ui2, VectorRegister b);
2109 inline void vspltisb( VectorRegister d, int si5);
2110 inline void vspltish( VectorRegister d, int si5);
2111 inline void vspltisw( VectorRegister d, int si5);
2112 inline void vperm( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c);
2113 inline void vsel( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c);
2114 inline void vsl( VectorRegister d, VectorRegister a, VectorRegister b);
2115 inline void vsldoi( VectorRegister d, VectorRegister a, VectorRegister b, int ui4);
2116 inline void vslo( VectorRegister d, VectorRegister a, VectorRegister b);
2117 inline void vsr( VectorRegister d, VectorRegister a, VectorRegister b);
2118 inline void vsro( VectorRegister d, VectorRegister a, VectorRegister b);
2119 inline void vaddcuw( VectorRegister d, VectorRegister a, VectorRegister b);
2120 inline void vaddshs( VectorRegister d, VectorRegister a, VectorRegister b);
2121 inline void vaddsbs( VectorRegister d, VectorRegister a, VectorRegister b);
2122 inline void vaddsws( VectorRegister d, VectorRegister a, VectorRegister b);
2123 inline void vaddubm( VectorRegister d, VectorRegister a, VectorRegister b);
2124 inline void vadduwm( VectorRegister d, VectorRegister a, VectorRegister b);
2125 inline void vadduhm( VectorRegister d, VectorRegister a, VectorRegister b);
2126 inline void vaddudm( VectorRegister d, VectorRegister a, VectorRegister b);
2127 inline void vaddubs( VectorRegister d, VectorRegister a, VectorRegister b);
2128 inline void vadduws( VectorRegister d, VectorRegister a, VectorRegister b);
2129 inline void vadduhs( VectorRegister d, VectorRegister a, VectorRegister b);
2130 inline void vaddfp( VectorRegister d, VectorRegister a, VectorRegister b);
2131 inline void vsubcuw( VectorRegister d, VectorRegister a, VectorRegister b);
2132 inline void vsubshs( VectorRegister d, VectorRegister a, VectorRegister b);
2209 inline void vxor( VectorRegister d, VectorRegister a, VectorRegister b);
2210 inline void vrld( VectorRegister d, VectorRegister a, VectorRegister b);
2211 inline void vrlb( VectorRegister d, VectorRegister a, VectorRegister b);
2212 inline void vrlw( VectorRegister d, VectorRegister a, VectorRegister b);
2213 inline void vrlh( VectorRegister d, VectorRegister a, VectorRegister b);
2214 inline void vslb( VectorRegister d, VectorRegister a, VectorRegister b);
2215 inline void vskw( VectorRegister d, VectorRegister a, VectorRegister b);
2216 inline void vslh( VectorRegister d, VectorRegister a, VectorRegister b);
2217 inline void vsrb( VectorRegister d, VectorRegister a, VectorRegister b);
2218 inline void vsrw( VectorRegister d, VectorRegister a, VectorRegister b);
2219 inline void vsrh( VectorRegister d, VectorRegister a, VectorRegister b);
2220 inline void vsrab( VectorRegister d, VectorRegister a, VectorRegister b);
2221 inline void vsraw( VectorRegister d, VectorRegister a, VectorRegister b);
2222 inline void vsrah( VectorRegister d, VectorRegister a, VectorRegister b);
2223 inline void vpopcntw( VectorRegister d, VectorRegister b);
2224 // Vector Floating-Point not implemented yet
2225 inline void mtvscr( VectorRegister b);
2226 inline void mfvscr( VectorRegister d);
2227
2228 // Vector-Scalar (VSX) instructions.
2229 inline void lxvd2x( VectorSRegister d, Register a);
2230 inline void lxvd2x( VectorSRegister d, Register a, Register b);
2231 inline void stxvd2x( VectorSRegister d, Register a);
2232 inline void stxvd2x( VectorSRegister d, Register a, Register b);
2233 inline void mtvrwz( VectorRegister d, Register a);
2234 inline void mfvrwz( Register a, VectorRegister d);
2235 inline void mtvrd( VectorRegister d, Register a);
2236 inline void mfvrd( Register a, VectorRegister d);
2237 inline void xxpermdi( VectorSRegister d, VectorSRegister a, VectorSRegister b, int dm);
2238 inline void xxmrghw( VectorSRegister d, VectorSRegister a, VectorSRegister b);
2239 inline void xxmrglw( VectorSRegister d, VectorSRegister a, VectorSRegister b);
2240 inline void mtvsrd( VectorSRegister d, Register a);
2241 inline void mfvsrd( Register d, VectorSRegister a);
2242 inline void mtvsrwz( VectorSRegister d, Register a);
2243 inline void mfvsrwz( Register d, VectorSRegister a);
2244 inline void xxspltw( VectorSRegister d, VectorSRegister b, int ui2);
2245 inline void xxlor( VectorSRegister d, VectorSRegister a, VectorSRegister b);
2246 inline void xxlxor( VectorSRegister d, VectorSRegister a, VectorSRegister b);
2247 inline void xxleqv( VectorSRegister d, VectorSRegister a, VectorSRegister b);
2248 inline void xxbrd( VectorSRegister d, VectorSRegister b);
2249 inline void xxbrw( VectorSRegister d, VectorSRegister b);
2250 inline void xvdivsp( VectorSRegister d, VectorSRegister a, VectorSRegister b);
2251 inline void xvdivdp( VectorSRegister d, VectorSRegister a, VectorSRegister b);
2252 inline void xvabssp( VectorSRegister d, VectorSRegister b);
2253 inline void xvabsdp( VectorSRegister d, VectorSRegister b);
2254 inline void xvnegsp( VectorSRegister d, VectorSRegister b);
2255 inline void xvnegdp( VectorSRegister d, VectorSRegister b);
2256 inline void xvsqrtsp( VectorSRegister d, VectorSRegister b);
2257 inline void xvsqrtdp( VectorSRegister d, VectorSRegister b);
2258 inline void xscvdpspn(VectorSRegister d, VectorSRegister b);
2259 inline void xvadddp( VectorSRegister d, VectorSRegister a, VectorSRegister b);
2260 inline void xvsubdp( VectorSRegister d, VectorSRegister a, VectorSRegister b);
2261 inline void xvmulsp( VectorSRegister d, VectorSRegister a, VectorSRegister b);
2262 inline void xvmuldp( VectorSRegister d, VectorSRegister a, VectorSRegister b);
2263 inline void xvmaddasp(VectorSRegister d, VectorSRegister a, VectorSRegister b);
2264 inline void xvmaddadp(VectorSRegister d, VectorSRegister a, VectorSRegister b);
2265 inline void xvmsubasp(VectorSRegister d, VectorSRegister a, VectorSRegister b);
2266 inline void xvmsubadp(VectorSRegister d, VectorSRegister a, VectorSRegister b);
2267 inline void xvnmsubasp(VectorSRegister d, VectorSRegister a, VectorSRegister b);
2268 inline void xvnmsubadp(VectorSRegister d, VectorSRegister a, VectorSRegister b);
2269 inline void xvrdpi( VectorSRegister d, VectorSRegister b);
|
419 RLDICL_OPCODE = (30u << OPCODE_SHIFT | 0u << XO_27_29_SHIFT), // MD-FORM
420 RLDIC_OPCODE = (30u << OPCODE_SHIFT | 2u << XO_27_29_SHIFT), // MD-FORM
421 RLDIMI_OPCODE = (30u << OPCODE_SHIFT | 3u << XO_27_29_SHIFT), // MD-FORM
422
423 SRADI_OPCODE = (31u << OPCODE_SHIFT | 413u << XO_21_29_SHIFT), // XS-FORM
424
425 SLD_OPCODE = (31u << OPCODE_SHIFT | 27u << 1), // X-FORM
426 SRD_OPCODE = (31u << OPCODE_SHIFT | 539u << 1), // X-FORM
427 SRAD_OPCODE = (31u << OPCODE_SHIFT | 794u << 1), // X-FORM
428
429 MULLD_OPCODE = (31u << OPCODE_SHIFT | 233u << 1), // XO-FORM
430 MULHD_OPCODE = (31u << OPCODE_SHIFT | 73u << 1), // XO-FORM
431 MULHDU_OPCODE = (31u << OPCODE_SHIFT | 9u << 1), // XO-FORM
432 DIVD_OPCODE = (31u << OPCODE_SHIFT | 489u << 1), // XO-FORM
433
434 CNTLZD_OPCODE = (31u << OPCODE_SHIFT | 58u << XO_21_30_SHIFT), // X-FORM
435 CNTTZD_OPCODE = (31u << OPCODE_SHIFT | 570u << XO_21_30_SHIFT), // X-FORM
436 NAND_OPCODE = (31u << OPCODE_SHIFT | 476u << XO_21_30_SHIFT), // X-FORM
437 NOR_OPCODE = (31u << OPCODE_SHIFT | 124u << XO_21_30_SHIFT), // X-FORM
438
439 // Byte reverse opcodes (introduced with Power10)
440 BRW_OPCODE = (31u << OPCODE_SHIFT | 155u << 1), // X-FORM
441
442 // opcodes only used for floating arithmetic
443 FADD_OPCODE = (63u << OPCODE_SHIFT | 21u << 1),
444 FADDS_OPCODE = (59u << OPCODE_SHIFT | 21u << 1),
445 FCMPU_OPCODE = (63u << OPCODE_SHIFT | 00u << 1),
446 FDIV_OPCODE = (63u << OPCODE_SHIFT | 18u << 1),
447 FDIVS_OPCODE = (59u << OPCODE_SHIFT | 18u << 1),
448 FMR_OPCODE = (63u << OPCODE_SHIFT | 72u << 1),
449 FRIN_OPCODE = (63u << OPCODE_SHIFT | 392u << 1),
450 FRIP_OPCODE = (63u << OPCODE_SHIFT | 456u << 1),
451 FRIM_OPCODE = (63u << OPCODE_SHIFT | 488u << 1),
452 // These are special Power6 opcodes, reused for "lfdepx" and "stfdepx"
453 // on Power7. Do not use.
454 // MFFGPR_OPCODE = (31u << OPCODE_SHIFT | 607u << 1),
455 // MFTGPR_OPCODE = (31u << OPCODE_SHIFT | 735u << 1),
456 CMPB_OPCODE = (31u << OPCODE_SHIFT | 508 << 1),
457 POPCNTB_OPCODE = (31u << OPCODE_SHIFT | 122 << 1),
458 POPCNTW_OPCODE = (31u << OPCODE_SHIFT | 378 << 1),
459 POPCNTD_OPCODE = (31u << OPCODE_SHIFT | 506 << 1),
460 FABS_OPCODE = (63u << OPCODE_SHIFT | 264u << 1),
500
501 FSQRT_OPCODE = (63u << OPCODE_SHIFT | 22u << 1), // A-FORM
502 FSQRTS_OPCODE = (59u << OPCODE_SHIFT | 22u << 1), // A-FORM
503
504 // Vector instruction support for >= Power6
505 // Vector Storage Access
506 LVEBX_OPCODE = (31u << OPCODE_SHIFT | 7u << 1),
507 LVEHX_OPCODE = (31u << OPCODE_SHIFT | 39u << 1),
508 LVEWX_OPCODE = (31u << OPCODE_SHIFT | 71u << 1),
509 LVX_OPCODE = (31u << OPCODE_SHIFT | 103u << 1),
510 LVXL_OPCODE = (31u << OPCODE_SHIFT | 359u << 1),
511 STVEBX_OPCODE = (31u << OPCODE_SHIFT | 135u << 1),
512 STVEHX_OPCODE = (31u << OPCODE_SHIFT | 167u << 1),
513 STVEWX_OPCODE = (31u << OPCODE_SHIFT | 199u << 1),
514 STVX_OPCODE = (31u << OPCODE_SHIFT | 231u << 1),
515 STVXL_OPCODE = (31u << OPCODE_SHIFT | 487u << 1),
516 LVSL_OPCODE = (31u << OPCODE_SHIFT | 6u << 1),
517 LVSR_OPCODE = (31u << OPCODE_SHIFT | 38u << 1),
518
519 // Vector-Scalar (VSX) instruction support.
520 LXV_OPCODE = (61u << OPCODE_SHIFT | 1u ),
521 STXV_OPCODE = (61u << OPCODE_SHIFT | 5u ),
522 LXVD2X_OPCODE = (31u << OPCODE_SHIFT | 844u << 1),
523 STXVD2X_OPCODE = (31u << OPCODE_SHIFT | 972u << 1),
524 MTVSRD_OPCODE = (31u << OPCODE_SHIFT | 179u << 1),
525 MTVSRWZ_OPCODE = (31u << OPCODE_SHIFT | 243u << 1),
526 MFVSRD_OPCODE = (31u << OPCODE_SHIFT | 51u << 1),
527 MTVSRWA_OPCODE = (31u << OPCODE_SHIFT | 211u << 1),
528 MFVSRWZ_OPCODE = (31u << OPCODE_SHIFT | 115u << 1),
529 XXPERMDI_OPCODE= (60u << OPCODE_SHIFT | 10u << 3),
530 XXMRGHW_OPCODE = (60u << OPCODE_SHIFT | 18u << 3),
531 XXMRGLW_OPCODE = (60u << OPCODE_SHIFT | 50u << 3),
532 XXSPLTW_OPCODE = (60u << OPCODE_SHIFT | 164u << 2),
533 XXLAND_OPCODE = (60u << OPCODE_SHIFT | 130u << 3),
534 XXLOR_OPCODE = (60u << OPCODE_SHIFT | 146u << 3),
535 XXLXOR_OPCODE = (60u << OPCODE_SHIFT | 154u << 3),
536 XXLEQV_OPCODE = (60u << OPCODE_SHIFT | 186u << 3),
537 XVDIVSP_OPCODE = (60u << OPCODE_SHIFT | 88u << 3),
538 XXBRD_OPCODE = (60u << OPCODE_SHIFT | 475u << 2 | 23u << 16), // XX2-FORM
539 XXBRW_OPCODE = (60u << OPCODE_SHIFT | 475u << 2 | 15u << 16), // XX2-FORM
540 XXPERM_OPCODE = (60u << OPCODE_SHIFT | 26u << 3),
541 XXSEL_OPCODE = (60u << OPCODE_SHIFT | 3u << 4),
542 XXSPLTIB_OPCODE= (60u << OPCODE_SHIFT | 360u << 1),
543 XVDIVDP_OPCODE = (60u << OPCODE_SHIFT | 120u << 3),
544 XVABSSP_OPCODE = (60u << OPCODE_SHIFT | 409u << 2),
545 XVABSDP_OPCODE = (60u << OPCODE_SHIFT | 473u << 2),
546 XVNEGSP_OPCODE = (60u << OPCODE_SHIFT | 441u << 2),
547 XVNEGDP_OPCODE = (60u << OPCODE_SHIFT | 505u << 2),
548 XVSQRTSP_OPCODE= (60u << OPCODE_SHIFT | 139u << 2),
549 XVSQRTDP_OPCODE= (60u << OPCODE_SHIFT | 203u << 2),
550 XSCVDPSPN_OPCODE=(60u << OPCODE_SHIFT | 267u << 2),
551 XVADDDP_OPCODE = (60u << OPCODE_SHIFT | 96u << 3),
552 XVSUBDP_OPCODE = (60u << OPCODE_SHIFT | 104u << 3),
553 XVMULSP_OPCODE = (60u << OPCODE_SHIFT | 80u << 3),
554 XVMULDP_OPCODE = (60u << OPCODE_SHIFT | 112u << 3),
555 XVMADDASP_OPCODE=(60u << OPCODE_SHIFT | 65u << 3),
556 XVMADDADP_OPCODE=(60u << OPCODE_SHIFT | 97u << 3),
557 XVMSUBASP_OPCODE=(60u << OPCODE_SHIFT | 81u << 3),
558 XVMSUBADP_OPCODE=(60u << OPCODE_SHIFT | 113u << 3),
559 XVNMSUBASP_OPCODE=(60u<< OPCODE_SHIFT | 209u << 3),
560 XVNMSUBADP_OPCODE=(60u<< OPCODE_SHIFT | 241u << 3),
561 XVRDPI_OPCODE = (60u << OPCODE_SHIFT | 201u << 2),
562 XVRDPIM_OPCODE = (60u << OPCODE_SHIFT | 249u << 2),
579 VUPKHSB_OPCODE = (4u << OPCODE_SHIFT | 526u ),
580 VUPKHSH_OPCODE = (4u << OPCODE_SHIFT | 590u ),
581 VUPKLPX_OPCODE = (4u << OPCODE_SHIFT | 974u ),
582 VUPKLSB_OPCODE = (4u << OPCODE_SHIFT | 654u ),
583 VUPKLSH_OPCODE = (4u << OPCODE_SHIFT | 718u ),
584
585 VMRGHB_OPCODE = (4u << OPCODE_SHIFT | 12u ),
586 VMRGHW_OPCODE = (4u << OPCODE_SHIFT | 140u ),
587 VMRGHH_OPCODE = (4u << OPCODE_SHIFT | 76u ),
588 VMRGLB_OPCODE = (4u << OPCODE_SHIFT | 268u ),
589 VMRGLW_OPCODE = (4u << OPCODE_SHIFT | 396u ),
590 VMRGLH_OPCODE = (4u << OPCODE_SHIFT | 332u ),
591
592 VSPLT_OPCODE = (4u << OPCODE_SHIFT | 524u ),
593 VSPLTH_OPCODE = (4u << OPCODE_SHIFT | 588u ),
594 VSPLTW_OPCODE = (4u << OPCODE_SHIFT | 652u ),
595 VSPLTISB_OPCODE= (4u << OPCODE_SHIFT | 780u ),
596 VSPLTISH_OPCODE= (4u << OPCODE_SHIFT | 844u ),
597 VSPLTISW_OPCODE= (4u << OPCODE_SHIFT | 908u ),
598
599 VPEXTD_OPCODE = (4u << OPCODE_SHIFT | 1421u ),
600 VPERM_OPCODE = (4u << OPCODE_SHIFT | 43u ),
601 VSEL_OPCODE = (4u << OPCODE_SHIFT | 42u ),
602
603 VSL_OPCODE = (4u << OPCODE_SHIFT | 452u ),
604 VSLDOI_OPCODE = (4u << OPCODE_SHIFT | 44u ),
605 VSLO_OPCODE = (4u << OPCODE_SHIFT | 1036u ),
606 VSR_OPCODE = (4u << OPCODE_SHIFT | 708u ),
607 VSRO_OPCODE = (4u << OPCODE_SHIFT | 1100u ),
608
609 // Vector Integer
610 VADDCUW_OPCODE = (4u << OPCODE_SHIFT | 384u ),
611 VADDSHS_OPCODE = (4u << OPCODE_SHIFT | 832u ),
612 VADDSBS_OPCODE = (4u << OPCODE_SHIFT | 768u ),
613 VADDSWS_OPCODE = (4u << OPCODE_SHIFT | 896u ),
614 VADDUBM_OPCODE = (4u << OPCODE_SHIFT | 0u ),
615 VADDUWM_OPCODE = (4u << OPCODE_SHIFT | 128u ),
616 VADDUHM_OPCODE = (4u << OPCODE_SHIFT | 64u ),
617 VADDUDM_OPCODE = (4u << OPCODE_SHIFT | 192u ),
618 VADDUBS_OPCODE = (4u << OPCODE_SHIFT | 512u ),
619 VADDUWS_OPCODE = (4u << OPCODE_SHIFT | 640u ),
1087 static int bh( int x) { return opp_u_field(x, 20, 19); }
1088 static int bi( int x) { return opp_u_field(x, 15, 11); }
1089 static int bi0(ConditionRegister cr, Condition c) { return (cr->encoding() << 2) | c; }
1090 static int bo( int x) { return opp_u_field(x, 10, 6); }
1091 static int bt( int x) { return opp_u_field(x, 10, 6); }
1092 static int d1( int x) { return opp_s_field(x, 31, 16); }
1093 static int ds( int x) { assert((x & 0x3) == 0, "unaligned offset"); return opp_s_field(x, 31, 16); }
1094 static int eh( int x) { return opp_u_field(x, 31, 31); }
1095 static int flm( int x) { return opp_u_field(x, 14, 7); }
1096 static int fra( FloatRegister r) { return fra(r->encoding());}
1097 static int frb( FloatRegister r) { return frb(r->encoding());}
1098 static int frc( FloatRegister r) { return frc(r->encoding());}
1099 static int frs( FloatRegister r) { return frs(r->encoding());}
1100 static int frt( FloatRegister r) { return frt(r->encoding());}
1101 static int fra( int x) { return opp_u_field(x, 15, 11); }
1102 static int frb( int x) { return opp_u_field(x, 20, 16); }
1103 static int frc( int x) { return opp_u_field(x, 25, 21); }
1104 static int frs( int x) { return opp_u_field(x, 10, 6); }
1105 static int frt( int x) { return opp_u_field(x, 10, 6); }
1106 static int fxm( int x) { return opp_u_field(x, 19, 12); }
1107 static int imm8( int x) { return opp_u_field(uimm(x, 8), 20, 13); }
1108 static int l10( int x) { assert(x == 0 || x == 1, "must be 0 or 1"); return opp_u_field(x, 10, 10); }
1109 static int l14( int x) { return opp_u_field(x, 15, 14); }
1110 static int l15( int x) { return opp_u_field(x, 15, 15); }
1111 static int l910( int x) { return opp_u_field(x, 10, 9); }
1112 static int e1215( int x) { return opp_u_field(x, 15, 12); }
1113 static int lev( int x) { return opp_u_field(x, 26, 20); }
1114 static int li( int x) { return opp_s_field(x, 29, 6); }
1115 static int lk( int x) { return opp_u_field(x, 31, 31); }
1116 static int mb2125( int x) { return opp_u_field(x, 25, 21); }
1117 static int me2630( int x) { return opp_u_field(x, 30, 26); }
1118 static int mb2126( int x) { return opp_u_field(((x & 0x1f) << 1) | ((x & 0x20) >> 5), 26, 21); }
1119 static int me2126( int x) { return mb2126(x); }
1120 static int nb( int x) { return opp_u_field(x, 20, 16); }
1121 //static int opcd( int x) { return opp_u_field(x, 5, 0); } // is contained in our opcodes
1122 static int oe( int x) { return opp_u_field(x, 21, 21); }
1123 static int ra( Register r) { return ra(r->encoding()); }
1124 static int ra( int x) { return opp_u_field(x, 15, 11); }
1125 static int rb( Register r) { return rb(r->encoding()); }
1126 static int rb( int x) { return opp_u_field(x, 20, 16); }
1127 static int rc( int x) { return opp_u_field(x, 31, 31); }
1154 // Support vector instructions for >= Power6.
1155 static int vra( int x) { return opp_u_field(x, 15, 11); }
1156 static int vrb( int x) { return opp_u_field(x, 20, 16); }
1157 static int vrc( int x) { return opp_u_field(x, 25, 21); }
1158 static int vrs( int x) { return opp_u_field(x, 10, 6); }
1159 static int vrt( int x) { return opp_u_field(x, 10, 6); }
1160
1161 static int vra( VectorRegister r) { return vra(r->encoding());}
1162 static int vrb( VectorRegister r) { return vrb(r->encoding());}
1163 static int vrc( VectorRegister r) { return vrc(r->encoding());}
1164 static int vrs( VectorRegister r) { return vrs(r->encoding());}
1165 static int vrt( VectorRegister r) { return vrt(r->encoding());}
1166
1167 // Only used on SHA sigma instructions (VX-form)
1168 static int vst( int x) { return opp_u_field(x, 16, 16); }
1169 static int vsix( int x) { return opp_u_field(x, 20, 17); }
1170
1171 // Support Vector-Scalar (VSX) instructions.
1172 static int vsra( int x) { return opp_u_field(x & 0x1F, 15, 11) | opp_u_field((x & 0x20) >> 5, 29, 29); }
1173 static int vsrb( int x) { return opp_u_field(x & 0x1F, 20, 16) | opp_u_field((x & 0x20) >> 5, 30, 30); }
1174 static int vsrc( int x) { return opp_u_field(x & 0x1F, 25, 21) | opp_u_field((x & 0x20) >> 5, 28, 28); }
1175 static int vsrs( int x) { return opp_u_field(x & 0x1F, 10, 6) | opp_u_field((x & 0x20) >> 5, 31, 31); }
1176 static int vsrt( int x) { return vsrs(x); }
1177 static int vsdm( int x) { return opp_u_field(x, 23, 22); }
1178 static int vsrs_dq( int x) { return opp_u_field(x & 0x1F, 10, 6) | opp_u_field((x & 0x20) >> 5, 28, 28); }
1179 static int vsrt_dq( int x) { return vsrs_dq(x); }
1180
1181 static int vsra( VectorSRegister r) { return vsra(r->encoding());}
1182 static int vsrb( VectorSRegister r) { return vsrb(r->encoding());}
1183 static int vsrc( VectorSRegister r) { return vsrc(r->encoding());}
1184 static int vsrs( VectorSRegister r) { return vsrs(r->encoding());}
1185 static int vsrt( VectorSRegister r) { return vsrt(r->encoding());}
1186 static int vsrs_dq(VectorSRegister r) { return vsrs_dq(r->encoding());}
1187 static int vsrt_dq(VectorSRegister r) { return vsrt_dq(r->encoding());}
1188
1189 static int vsplt_uim( int x) { return opp_u_field(x, 15, 12); } // for vsplt* instructions
1190 static int vsplti_sim(int x) { return opp_u_field(x, 15, 11); } // for vsplti* instructions
1191 static int vsldoi_shb(int x) { return opp_u_field(x, 25, 22); } // for vsldoi instruction
1192 static int vcmp_rc( int x) { return opp_u_field(x, 21, 21); } // for vcmp* instructions
1193 static int xxsplt_uim(int x) { return opp_u_field(x, 15, 14); } // for xxsplt* instructions
1194
1195 //static int xo1( int x) { return opp_u_field(x, 29, 21); }// is contained in our opcodes
1196 //static int xo2( int x) { return opp_u_field(x, 30, 21); }// is contained in our opcodes
1197 //static int xo3( int x) { return opp_u_field(x, 30, 22); }// is contained in our opcodes
1198 //static int xo4( int x) { return opp_u_field(x, 30, 26); }// is contained in our opcodes
1199 //static int xo5( int x) { return opp_u_field(x, 29, 27); }// is contained in our opcodes
1200 //static int xo6( int x) { return opp_u_field(x, 30, 27); }// is contained in our opcodes
1201 //static int xo7( int x) { return opp_u_field(x, 31, 30); }// is contained in our opcodes
1202
1203 protected:
1204 // Compute relative address for branch.
1205 static intptr_t disp(intptr_t x, intptr_t off) {
1206 int xx = x - off;
1207 xx = xx >> 2;
1567 // extended mnemonics for Shift Instructions
1568 inline void sldi( Register a, Register s, int sh6);
1569 inline void sldi_( Register a, Register s, int sh6);
1570 inline void slwi( Register a, Register s, int sh5);
1571 inline void slwi_( Register a, Register s, int sh5);
1572 inline void srdi( Register a, Register s, int sh6);
1573 inline void srdi_( Register a, Register s, int sh6);
1574 inline void srwi( Register a, Register s, int sh5);
1575 inline void srwi_( Register a, Register s, int sh5);
1576
1577 inline void clrrdi( Register a, Register s, int ui6);
1578 inline void clrrdi_( Register a, Register s, int ui6);
1579 inline void clrldi( Register a, Register s, int ui6);
1580 inline void clrldi_( Register a, Register s, int ui6);
1581 inline void clrlsldi(Register a, Register s, int clrl6, int shl6);
1582 inline void clrlsldi_(Register a, Register s, int clrl6, int shl6);
1583 inline void extrdi( Register a, Register s, int n, int b);
1584 // testbit with condition register
1585 inline void testbitdi(ConditionRegister cr, Register a, Register s, int ui6);
1586
1587 // Byte reverse instructions (introduced with Power10)
1588 inline void brw( Register a, Register s);
1589
1590 // rotate instructions
1591 inline void rotldi( Register a, Register s, int n);
1592 inline void rotrdi( Register a, Register s, int n);
1593 inline void rotlwi( Register a, Register s, int n);
1594 inline void rotrwi( Register a, Register s, int n);
1595
1596 // Rotate Instructions
1597 inline void rldic( Register a, Register s, int sh6, int mb6);
1598 inline void rldic_( Register a, Register s, int sh6, int mb6);
1599 inline void rldicr( Register a, Register s, int sh6, int mb6);
1600 inline void rldicr_( Register a, Register s, int sh6, int mb6);
1601 inline void rldicl( Register a, Register s, int sh6, int mb6);
1602 inline void rldicl_( Register a, Register s, int sh6, int mb6);
1603 inline void rlwinm( Register a, Register s, int sh5, int mb5, int me5);
1604 inline void rlwinm_( Register a, Register s, int sh5, int mb5, int me5);
1605 inline void rldimi( Register a, Register s, int sh6, int mb6);
1606 inline void rldimi_( Register a, Register s, int sh6, int mb6);
1607 inline void rlwimi( Register a, Register s, int sh5, int mb5, int me5);
1608 inline void insrdi( Register a, Register s, int n, int b);
1609 inline void insrwi( Register a, Register s, int n, int b);
2112 inline void vpkuwus( VectorRegister d, VectorRegister a, VectorRegister b);
2113 inline void vupkhpx( VectorRegister d, VectorRegister b);
2114 inline void vupkhsb( VectorRegister d, VectorRegister b);
2115 inline void vupkhsh( VectorRegister d, VectorRegister b);
2116 inline void vupklpx( VectorRegister d, VectorRegister b);
2117 inline void vupklsb( VectorRegister d, VectorRegister b);
2118 inline void vupklsh( VectorRegister d, VectorRegister b);
2119 inline void vmrghb( VectorRegister d, VectorRegister a, VectorRegister b);
2120 inline void vmrghw( VectorRegister d, VectorRegister a, VectorRegister b);
2121 inline void vmrghh( VectorRegister d, VectorRegister a, VectorRegister b);
2122 inline void vmrglb( VectorRegister d, VectorRegister a, VectorRegister b);
2123 inline void vmrglw( VectorRegister d, VectorRegister a, VectorRegister b);
2124 inline void vmrglh( VectorRegister d, VectorRegister a, VectorRegister b);
2125 inline void vsplt( VectorRegister d, int ui4, VectorRegister b);
2126 inline void vsplth( VectorRegister d, int ui3, VectorRegister b);
2127 inline void vspltw( VectorRegister d, int ui2, VectorRegister b);
2128 inline void vspltisb( VectorRegister d, int si5);
2129 inline void vspltish( VectorRegister d, int si5);
2130 inline void vspltisw( VectorRegister d, int si5);
2131 inline void vperm( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c);
2132 inline void vpextd( VectorRegister d, VectorRegister a, VectorRegister b);
2133 inline void vsel( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c);
2134 inline void vsl( VectorRegister d, VectorRegister a, VectorRegister b);
2135 inline void vsldoi( VectorRegister d, VectorRegister a, VectorRegister b, int ui4);
2136 inline void vslo( VectorRegister d, VectorRegister a, VectorRegister b);
2137 inline void vsr( VectorRegister d, VectorRegister a, VectorRegister b);
2138 inline void vsro( VectorRegister d, VectorRegister a, VectorRegister b);
2139 inline void vaddcuw( VectorRegister d, VectorRegister a, VectorRegister b);
2140 inline void vaddshs( VectorRegister d, VectorRegister a, VectorRegister b);
2141 inline void vaddsbs( VectorRegister d, VectorRegister a, VectorRegister b);
2142 inline void vaddsws( VectorRegister d, VectorRegister a, VectorRegister b);
2143 inline void vaddubm( VectorRegister d, VectorRegister a, VectorRegister b);
2144 inline void vadduwm( VectorRegister d, VectorRegister a, VectorRegister b);
2145 inline void vadduhm( VectorRegister d, VectorRegister a, VectorRegister b);
2146 inline void vaddudm( VectorRegister d, VectorRegister a, VectorRegister b);
2147 inline void vaddubs( VectorRegister d, VectorRegister a, VectorRegister b);
2148 inline void vadduws( VectorRegister d, VectorRegister a, VectorRegister b);
2149 inline void vadduhs( VectorRegister d, VectorRegister a, VectorRegister b);
2150 inline void vaddfp( VectorRegister d, VectorRegister a, VectorRegister b);
2151 inline void vsubcuw( VectorRegister d, VectorRegister a, VectorRegister b);
2152 inline void vsubshs( VectorRegister d, VectorRegister a, VectorRegister b);
2229 inline void vxor( VectorRegister d, VectorRegister a, VectorRegister b);
2230 inline void vrld( VectorRegister d, VectorRegister a, VectorRegister b);
2231 inline void vrlb( VectorRegister d, VectorRegister a, VectorRegister b);
2232 inline void vrlw( VectorRegister d, VectorRegister a, VectorRegister b);
2233 inline void vrlh( VectorRegister d, VectorRegister a, VectorRegister b);
2234 inline void vslb( VectorRegister d, VectorRegister a, VectorRegister b);
2235 inline void vskw( VectorRegister d, VectorRegister a, VectorRegister b);
2236 inline void vslh( VectorRegister d, VectorRegister a, VectorRegister b);
2237 inline void vsrb( VectorRegister d, VectorRegister a, VectorRegister b);
2238 inline void vsrw( VectorRegister d, VectorRegister a, VectorRegister b);
2239 inline void vsrh( VectorRegister d, VectorRegister a, VectorRegister b);
2240 inline void vsrab( VectorRegister d, VectorRegister a, VectorRegister b);
2241 inline void vsraw( VectorRegister d, VectorRegister a, VectorRegister b);
2242 inline void vsrah( VectorRegister d, VectorRegister a, VectorRegister b);
2243 inline void vpopcntw( VectorRegister d, VectorRegister b);
2244 // Vector Floating-Point not implemented yet
2245 inline void mtvscr( VectorRegister b);
2246 inline void mfvscr( VectorRegister d);
2247
2248 // Vector-Scalar (VSX) instructions.
2249 inline void lxv( VectorSRegister d, int si16, Register a);
2250 inline void stxv( VectorSRegister d, int si16, Register a);
2251 inline void lxvd2x( VectorSRegister d, Register a);
2252 inline void lxvd2x( VectorSRegister d, Register a, Register b);
2253 inline void stxvd2x( VectorSRegister d, Register a);
2254 inline void stxvd2x( VectorSRegister d, Register a, Register b);
2255 inline void mtvrwz( VectorRegister d, Register a);
2256 inline void mfvrwz( Register a, VectorRegister d);
2257 inline void mtvrd( VectorRegister d, Register a);
2258 inline void mfvrd( Register a, VectorRegister d);
2259 inline void xxperm( VectorSRegister d, VectorSRegister a, VectorSRegister b);
2260 inline void xxpermdi( VectorSRegister d, VectorSRegister a, VectorSRegister b, int dm);
2261 inline void xxmrghw( VectorSRegister d, VectorSRegister a, VectorSRegister b);
2262 inline void xxmrglw( VectorSRegister d, VectorSRegister a, VectorSRegister b);
2263 inline void mtvsrd( VectorSRegister d, Register a);
2264 inline void mfvsrd( Register d, VectorSRegister a);
2265 inline void mtvsrwz( VectorSRegister d, Register a);
2266 inline void mfvsrwz( Register d, VectorSRegister a);
2267 inline void xxspltw( VectorSRegister d, VectorSRegister b, int ui2);
2268 inline void xxlor( VectorSRegister d, VectorSRegister a, VectorSRegister b);
2269 inline void xxlxor( VectorSRegister d, VectorSRegister a, VectorSRegister b);
2270 inline void xxleqv( VectorSRegister d, VectorSRegister a, VectorSRegister b);
2271 inline void xxbrd( VectorSRegister d, VectorSRegister b);
2272 inline void xxbrw( VectorSRegister d, VectorSRegister b);
2273 inline void xxland( VectorSRegister d, VectorSRegister a, VectorSRegister b);
2274 inline void xxsel( VectorSRegister d, VectorSRegister a, VectorSRegister b, VectorSRegister c);
2275 inline void xxspltib( VectorSRegister d, int ui8);
2276 inline void xvdivsp( VectorSRegister d, VectorSRegister a, VectorSRegister b);
2277 inline void xvdivdp( VectorSRegister d, VectorSRegister a, VectorSRegister b);
2278 inline void xvabssp( VectorSRegister d, VectorSRegister b);
2279 inline void xvabsdp( VectorSRegister d, VectorSRegister b);
2280 inline void xvnegsp( VectorSRegister d, VectorSRegister b);
2281 inline void xvnegdp( VectorSRegister d, VectorSRegister b);
2282 inline void xvsqrtsp( VectorSRegister d, VectorSRegister b);
2283 inline void xvsqrtdp( VectorSRegister d, VectorSRegister b);
2284 inline void xscvdpspn(VectorSRegister d, VectorSRegister b);
2285 inline void xvadddp( VectorSRegister d, VectorSRegister a, VectorSRegister b);
2286 inline void xvsubdp( VectorSRegister d, VectorSRegister a, VectorSRegister b);
2287 inline void xvmulsp( VectorSRegister d, VectorSRegister a, VectorSRegister b);
2288 inline void xvmuldp( VectorSRegister d, VectorSRegister a, VectorSRegister b);
2289 inline void xvmaddasp(VectorSRegister d, VectorSRegister a, VectorSRegister b);
2290 inline void xvmaddadp(VectorSRegister d, VectorSRegister a, VectorSRegister b);
2291 inline void xvmsubasp(VectorSRegister d, VectorSRegister a, VectorSRegister b);
2292 inline void xvmsubadp(VectorSRegister d, VectorSRegister a, VectorSRegister b);
2293 inline void xvnmsubasp(VectorSRegister d, VectorSRegister a, VectorSRegister b);
2294 inline void xvnmsubadp(VectorSRegister d, VectorSRegister a, VectorSRegister b);
2295 inline void xvrdpi( VectorSRegister d, VectorSRegister b);
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