1 /*
2 * Copyright (c) 1997, 2020, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2012, 2020 SAP SE. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #include "precompiled.hpp"
27 #include "jvm.h"
28 #include "asm/assembler.inline.hpp"
29 #include "asm/macroAssembler.inline.hpp"
30 #include "compiler/disassembler.hpp"
31 #include "memory/resourceArea.hpp"
32 #include "runtime/java.hpp"
33 #include "runtime/os.hpp"
34 #include "runtime/stubCodeGenerator.hpp"
35 #include "runtime/vm_version.hpp"
36 #include "utilities/align.hpp"
37 #include "utilities/defaultStream.hpp"
38 #include "utilities/globalDefinitions.hpp"
39 #include "utilities/powerOfTwo.hpp"
40
41 #include <sys/sysinfo.h>
42 #if defined(_AIX)
43 #include <libperfstat.h>
44 #endif
45
46 #if defined(LINUX) && defined(VM_LITTLE_ENDIAN)
47 #include <sys/auxv.h>
48
49 #ifndef PPC_FEATURE2_HTM_NOSC
50 #define PPC_FEATURE2_HTM_NOSC (1 << 24)
51 #endif
52 #endif
53
54 bool VM_Version::_is_determine_features_test_running = false;
55 uint64_t VM_Version::_dscr_val = 0;
56
57 #define MSG(flag) \
58 if (flag && !FLAG_IS_DEFAULT(flag)) \
59 jio_fprintf(defaultStream::error_stream(), \
60 "warning: -XX:+" #flag " requires -XX:+UseSIGTRAP\n" \
61 " -XX:+" #flag " will be disabled!\n");
62
63 void VM_Version::initialize() {
64
65 // Test which instructions are supported and measure cache line size.
66 determine_features();
67
68 // If PowerArchitecturePPC64 hasn't been specified explicitly determine from features.
69 if (FLAG_IS_DEFAULT(PowerArchitecturePPC64)) {
70 if (VM_Version::has_darn()) {
71 FLAG_SET_ERGO(PowerArchitecturePPC64, 9);
72 } else if (VM_Version::has_lqarx()) {
73 FLAG_SET_ERGO(PowerArchitecturePPC64, 8);
74 } else if (VM_Version::has_popcntw()) {
75 FLAG_SET_ERGO(PowerArchitecturePPC64, 7);
76 } else if (VM_Version::has_cmpb()) {
77 FLAG_SET_ERGO(PowerArchitecturePPC64, 6);
78 } else if (VM_Version::has_popcntb()) {
79 FLAG_SET_ERGO(PowerArchitecturePPC64, 5);
80 } else {
81 FLAG_SET_ERGO(PowerArchitecturePPC64, 0);
82 }
83 }
84
85 bool PowerArchitecturePPC64_ok = false;
86 switch (PowerArchitecturePPC64) {
87 case 9: if (!VM_Version::has_darn() ) break;
88 case 8: if (!VM_Version::has_lqarx() ) break;
89 case 7: if (!VM_Version::has_popcntw()) break;
90 case 6: if (!VM_Version::has_cmpb() ) break;
91 case 5: if (!VM_Version::has_popcntb()) break;
92 case 0: PowerArchitecturePPC64_ok = true; break;
93 default: break;
94 }
95 guarantee(PowerArchitecturePPC64_ok, "PowerArchitecturePPC64 cannot be set to "
96 UINTX_FORMAT " on this machine", PowerArchitecturePPC64);
97
98 // Power 8: Configure Data Stream Control Register.
99 if (PowerArchitecturePPC64 >= 8 && has_mfdscr()) {
100 config_dscr();
101 }
102
103 if (!UseSIGTRAP) {
104 MSG(TrapBasedICMissChecks);
105 MSG(TrapBasedNullChecks);
106 FLAG_SET_ERGO(TrapBasedNullChecks, false);
107 FLAG_SET_ERGO(TrapBasedICMissChecks, false);
108 }
109
110 #ifdef COMPILER2
111 if (!UseSIGTRAP) {
112 MSG(TrapBasedRangeChecks);
113 FLAG_SET_ERGO(TrapBasedRangeChecks, false);
114 }
115
116 // On Power6 test for section size.
117 if (PowerArchitecturePPC64 == 6) {
118 determine_section_size();
119 // TODO: PPC port } else {
120 // TODO: PPC port PdScheduling::power6SectorSize = 0x20;
121 }
122
123 if (PowerArchitecturePPC64 >= 8) {
124 if (FLAG_IS_DEFAULT(SuperwordUseVSX)) {
125 FLAG_SET_ERGO(SuperwordUseVSX, true);
126 }
127 } else {
128 if (SuperwordUseVSX) {
129 warning("SuperwordUseVSX specified, but needs at least Power8.");
130 FLAG_SET_DEFAULT(SuperwordUseVSX, false);
131 }
132 }
133 MaxVectorSize = SuperwordUseVSX ? 16 : 8;
134
135 if (PowerArchitecturePPC64 >= 9) {
136 if (FLAG_IS_DEFAULT(UseCountTrailingZerosInstructionsPPC64)) {
137 FLAG_SET_ERGO(UseCountTrailingZerosInstructionsPPC64, true);
138 }
139 if (FLAG_IS_DEFAULT(UseCharacterCompareIntrinsics)) {
140 FLAG_SET_ERGO(UseCharacterCompareIntrinsics, true);
141 }
142 if (FLAG_IS_DEFAULT(UseVectorByteReverseInstructionsPPC64)) {
143 FLAG_SET_ERGO(UseVectorByteReverseInstructionsPPC64, true);
144 }
145 } else {
146 if (UseCountTrailingZerosInstructionsPPC64) {
147 warning("UseCountTrailingZerosInstructionsPPC64 specified, but needs at least Power9.");
148 FLAG_SET_DEFAULT(UseCountTrailingZerosInstructionsPPC64, false);
149 }
150 if (UseCharacterCompareIntrinsics) {
151 warning("UseCharacterCompareIntrinsics specified, but needs at least Power9.");
152 FLAG_SET_DEFAULT(UseCharacterCompareIntrinsics, false);
153 }
154 if (UseVectorByteReverseInstructionsPPC64) {
155 warning("UseVectorByteReverseInstructionsPPC64 specified, but needs at least Power9.");
156 FLAG_SET_DEFAULT(UseVectorByteReverseInstructionsPPC64, false);
157 }
158 }
159 #endif
160
161 // Create and print feature-string.
162 char buf[(num_features+1) * 16]; // Max 16 chars per feature.
163 jio_snprintf(buf, sizeof(buf),
164 "ppc64%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
165 (has_fsqrt() ? " fsqrt" : ""),
166 (has_isel() ? " isel" : ""),
167 (has_lxarxeh() ? " lxarxeh" : ""),
168 (has_cmpb() ? " cmpb" : ""),
169 (has_popcntb() ? " popcntb" : ""),
170 (has_popcntw() ? " popcntw" : ""),
171 (has_fcfids() ? " fcfids" : ""),
172 (has_vand() ? " vand" : ""),
173 (has_lqarx() ? " lqarx" : ""),
174 (has_vcipher() ? " aes" : ""),
175 (has_vpmsumb() ? " vpmsumb" : ""),
176 (has_mfdscr() ? " mfdscr" : ""),
177 (has_vsx() ? " vsx" : ""),
178 (has_ldbrx() ? " ldbrx" : ""),
179 (has_stdbrx() ? " stdbrx" : ""),
180 (has_vshasig() ? " sha" : ""),
181 (has_tm() ? " rtm" : ""),
182 (has_darn() ? " darn" : "")
183 // Make sure number of %s matches num_features!
184 );
185 _features_string = os::strdup(buf);
186 if (Verbose) {
187 print_features();
188 }
189
190 // PPC64 supports 8-byte compare-exchange operations (see Atomic::cmpxchg)
191 // and 'atomic long memory ops' (see Unsafe_GetLongVolatile).
192 _supports_cx8 = true;
193
194 // Used by C1.
195 _supports_atomic_getset4 = true;
196 _supports_atomic_getadd4 = true;
197 _supports_atomic_getset8 = true;
198 _supports_atomic_getadd8 = true;
199
200 intx cache_line_size = L1_data_cache_line_size();
201
202 if (PowerArchitecturePPC64 >= 9) {
203 if (os::supports_map_sync() == true) {
204 _data_cache_line_flush_size = cache_line_size;
205 }
206 }
207
208 if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) AllocatePrefetchStyle = 1;
209
210 if (cache_line_size > AllocatePrefetchStepSize) AllocatePrefetchStepSize = cache_line_size;
211 // PPC processors have an automatic prefetch engine.
212 if (FLAG_IS_DEFAULT(AllocatePrefetchLines)) AllocatePrefetchLines = 1;
213 if (AllocatePrefetchDistance < 0) AllocatePrefetchDistance = 3 * cache_line_size;
214
215 assert(AllocatePrefetchLines > 0, "invalid value");
216 if (AllocatePrefetchLines < 1) { // Set valid value in product VM.
217 AllocatePrefetchLines = 1; // Conservative value.
218 }
219
220 if (AllocatePrefetchStyle == 3 && AllocatePrefetchDistance < cache_line_size) {
221 AllocatePrefetchStyle = 1; // Fall back if inappropriate.
222 }
223
224 assert(AllocatePrefetchStyle >= 0, "AllocatePrefetchStyle should be positive");
225
226 if (FLAG_IS_DEFAULT(ContendedPaddingWidth) && (cache_line_size > ContendedPaddingWidth)) {
227 ContendedPaddingWidth = cache_line_size;
228 }
229
230 // If running on Power8 or newer hardware, the implementation uses the available vector instructions.
231 // In all other cases, the implementation uses only generally available instructions.
232 if (!UseCRC32Intrinsics) {
233 if (FLAG_IS_DEFAULT(UseCRC32Intrinsics)) {
234 FLAG_SET_DEFAULT(UseCRC32Intrinsics, true);
235 }
236 }
237
238 // Implementation does not use any of the vector instructions available with Power8.
239 // Their exploitation is still pending (aka "work in progress").
240 if (!UseCRC32CIntrinsics) {
241 if (FLAG_IS_DEFAULT(UseCRC32CIntrinsics)) {
242 FLAG_SET_DEFAULT(UseCRC32CIntrinsics, true);
243 }
244 }
245
246 // TODO: Provide implementation.
247 if (UseAdler32Intrinsics) {
248 warning("Adler32Intrinsics not available on this CPU.");
249 FLAG_SET_DEFAULT(UseAdler32Intrinsics, false);
250 }
251
252 // The AES intrinsic stubs require AES instruction support.
253 if (has_vcipher()) {
254 if (FLAG_IS_DEFAULT(UseAES)) {
255 UseAES = true;
256 }
257 } else if (UseAES) {
258 if (!FLAG_IS_DEFAULT(UseAES))
259 warning("AES instructions are not available on this CPU");
260 FLAG_SET_DEFAULT(UseAES, false);
261 }
262
263 if (UseAES && has_vcipher()) {
264 if (FLAG_IS_DEFAULT(UseAESIntrinsics)) {
265 UseAESIntrinsics = true;
266 }
267 } else if (UseAESIntrinsics) {
268 if (!FLAG_IS_DEFAULT(UseAESIntrinsics))
269 warning("AES intrinsics are not available on this CPU");
270 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
271 }
272
273 if (UseAESCTRIntrinsics) {
274 warning("AES/CTR intrinsics are not available on this CPU");
275 FLAG_SET_DEFAULT(UseAESCTRIntrinsics, false);
276 }
277
278 if (UseGHASHIntrinsics) {
279 warning("GHASH intrinsics are not available on this CPU");
280 FLAG_SET_DEFAULT(UseGHASHIntrinsics, false);
281 }
282
283 if (FLAG_IS_DEFAULT(UseFMA)) {
284 FLAG_SET_DEFAULT(UseFMA, true);
285 }
286
287 if (UseMD5Intrinsics) {
288 warning("MD5 intrinsics are not available on this CPU");
289 FLAG_SET_DEFAULT(UseMD5Intrinsics, false);
290 }
291
292 if (has_vshasig()) {
293 if (FLAG_IS_DEFAULT(UseSHA)) {
294 UseSHA = true;
295 }
296 } else if (UseSHA) {
297 if (!FLAG_IS_DEFAULT(UseSHA))
298 warning("SHA instructions are not available on this CPU");
299 FLAG_SET_DEFAULT(UseSHA, false);
300 }
301
302 if (UseSHA1Intrinsics) {
303 warning("Intrinsics for SHA-1 crypto hash functions not available on this CPU.");
304 FLAG_SET_DEFAULT(UseSHA1Intrinsics, false);
305 }
306
307 if (UseSHA && has_vshasig()) {
308 if (FLAG_IS_DEFAULT(UseSHA256Intrinsics)) {
309 FLAG_SET_DEFAULT(UseSHA256Intrinsics, true);
310 }
311 } else if (UseSHA256Intrinsics) {
312 warning("Intrinsics for SHA-224 and SHA-256 crypto hash functions not available on this CPU.");
313 FLAG_SET_DEFAULT(UseSHA256Intrinsics, false);
314 }
315
316 if (UseSHA && has_vshasig()) {
317 if (FLAG_IS_DEFAULT(UseSHA512Intrinsics)) {
318 FLAG_SET_DEFAULT(UseSHA512Intrinsics, true);
319 }
320 } else if (UseSHA512Intrinsics) {
321 warning("Intrinsics for SHA-384 and SHA-512 crypto hash functions not available on this CPU.");
322 FLAG_SET_DEFAULT(UseSHA512Intrinsics, false);
323 }
324
325 if (!(UseSHA1Intrinsics || UseSHA256Intrinsics || UseSHA512Intrinsics)) {
326 FLAG_SET_DEFAULT(UseSHA, false);
327 }
328
329 #ifdef COMPILER2
330 if (FLAG_IS_DEFAULT(UseSquareToLenIntrinsic)) {
331 UseSquareToLenIntrinsic = true;
332 }
333 if (FLAG_IS_DEFAULT(UseMulAddIntrinsic)) {
334 UseMulAddIntrinsic = true;
335 }
336 if (FLAG_IS_DEFAULT(UseMultiplyToLenIntrinsic)) {
337 UseMultiplyToLenIntrinsic = true;
338 }
339 if (FLAG_IS_DEFAULT(UseMontgomeryMultiplyIntrinsic)) {
340 UseMontgomeryMultiplyIntrinsic = true;
341 }
342 if (FLAG_IS_DEFAULT(UseMontgomerySquareIntrinsic)) {
343 UseMontgomerySquareIntrinsic = true;
344 }
345 #endif
346
347 if (UseVectorizedMismatchIntrinsic) {
348 warning("UseVectorizedMismatchIntrinsic specified, but not available on this CPU.");
349 FLAG_SET_DEFAULT(UseVectorizedMismatchIntrinsic, false);
350 }
351
352
353 // Adjust RTM (Restricted Transactional Memory) flags.
354 if (UseRTMLocking) {
355 // If CPU or OS do not support TM:
356 // Can't continue because UseRTMLocking affects UseBiasedLocking flag
357 // setting during arguments processing. See use_biased_locking().
358 // VM_Version_init() is executed after UseBiasedLocking is used
359 // in Thread::allocate().
360 if (PowerArchitecturePPC64 < 8) {
361 vm_exit_during_initialization("RTM instructions are not available on this CPU.");
362 }
363
364 if (!has_tm()) {
365 vm_exit_during_initialization("RTM is not supported on this OS version.");
366 }
367 }
368
369 if (UseRTMLocking) {
370 #if INCLUDE_RTM_OPT
371 if (!FLAG_IS_CMDLINE(UseRTMLocking)) {
372 // RTM locking should be used only for applications with
373 // high lock contention. For now we do not use it by default.
374 vm_exit_during_initialization("UseRTMLocking flag should be only set on command line");
375 }
376 #else
377 // Only C2 does RTM locking optimization.
378 // Can't continue because UseRTMLocking affects UseBiasedLocking flag
379 // setting during arguments processing. See use_biased_locking().
380 vm_exit_during_initialization("RTM locking optimization is not supported in this VM");
381 #endif
382 } else { // !UseRTMLocking
383 if (UseRTMForStackLocks) {
384 if (!FLAG_IS_DEFAULT(UseRTMForStackLocks)) {
385 warning("UseRTMForStackLocks flag should be off when UseRTMLocking flag is off");
386 }
387 FLAG_SET_DEFAULT(UseRTMForStackLocks, false);
388 }
389 if (UseRTMDeopt) {
390 FLAG_SET_DEFAULT(UseRTMDeopt, false);
391 }
392 #ifdef COMPILER2
393 if (PrintPreciseRTMLockingStatistics) {
394 FLAG_SET_DEFAULT(PrintPreciseRTMLockingStatistics, false);
395 }
396 #endif
397 }
398
399 // This machine allows unaligned memory accesses
400 if (FLAG_IS_DEFAULT(UseUnalignedAccesses)) {
401 FLAG_SET_DEFAULT(UseUnalignedAccesses, true);
402 }
403
404 check_virtualizations();
405 }
406
407 void VM_Version::check_virtualizations() {
408 #if defined(_AIX)
409 int rc = 0;
410 perfstat_partition_total_t pinfo;
411 rc = perfstat_partition_total(NULL, &pinfo, sizeof(perfstat_partition_total_t), 1);
412 if (rc == 1) {
413 Abstract_VM_Version::_detected_virtualization = PowerVM;
414 }
415 #else
416 const char* info_file = "/proc/ppc64/lparcfg";
417 // system_type=...qemu indicates PowerKVM
418 // e.g. system_type=IBM pSeries (emulated by qemu)
419 char line[500];
420 FILE* fp = fopen(info_file, "r");
421 if (fp == NULL) {
422 return;
423 }
424 const char* system_type="system_type="; // in case this line contains qemu, it is KVM
425 const char* num_lpars="NumLpars="; // in case of non-KVM : if this line is found it is PowerVM
426 bool num_lpars_found = false;
427
428 while (fgets(line, sizeof(line), fp) != NULL) {
429 if (strncmp(line, system_type, strlen(system_type)) == 0) {
430 if (strstr(line, "qemu") != 0) {
431 Abstract_VM_Version::_detected_virtualization = PowerKVM;
432 fclose(fp);
433 return;
434 }
435 }
436 if (strncmp(line, num_lpars, strlen(num_lpars)) == 0) {
437 num_lpars_found = true;
438 }
439 }
440 if (num_lpars_found) {
441 Abstract_VM_Version::_detected_virtualization = PowerVM;
442 } else {
443 Abstract_VM_Version::_detected_virtualization = PowerFullPartitionMode;
444 }
445 fclose(fp);
446 #endif
447 }
448
449 void VM_Version::print_platform_virtualization_info(outputStream* st) {
450 #if defined(_AIX)
451 // more info about perfstat API see
452 // https://www.ibm.com/support/knowledgecenter/en/ssw_aix_72/com.ibm.aix.prftools/idprftools_perfstat_glob_partition.htm
453 int rc = 0;
454 perfstat_partition_total_t pinfo;
455 memset(&pinfo, 0, sizeof(perfstat_partition_total_t));
456 rc = perfstat_partition_total(NULL, &pinfo, sizeof(perfstat_partition_total_t), 1);
457 if (rc != 1) {
458 return;
459 } else {
460 st->print_cr("Virtualization type : PowerVM");
461 }
462 // CPU information
463 perfstat_cpu_total_t cpuinfo;
464 memset(&cpuinfo, 0, sizeof(perfstat_cpu_total_t));
465 rc = perfstat_cpu_total(NULL, &cpuinfo, sizeof(perfstat_cpu_total_t), 1);
466 if (rc != 1) {
467 return;
468 }
469
470 st->print_cr("Processor description : %s", cpuinfo.description);
471 st->print_cr("Processor speed : %llu Hz", cpuinfo.processorHZ);
472
473 st->print_cr("LPAR partition name : %s", pinfo.name);
474 st->print_cr("LPAR partition number : %u", pinfo.lpar_id);
475 st->print_cr("LPAR partition type : %s", pinfo.type.b.shared_enabled ? "shared" : "dedicated");
476 st->print_cr("LPAR mode : %s", pinfo.type.b.donate_enabled ? "donating" : pinfo.type.b.capped ? "capped" : "uncapped");
477 st->print_cr("LPAR partition group ID : %u", pinfo.group_id);
478 st->print_cr("LPAR shared pool ID : %u", pinfo.pool_id);
479
480 st->print_cr("AMS (active memory sharing) : %s", pinfo.type.b.ams_capable ? "capable" : "not capable");
481 st->print_cr("AMS (active memory sharing) : %s", pinfo.type.b.ams_enabled ? "on" : "off");
482 st->print_cr("AME (active memory expansion) : %s", pinfo.type.b.ame_enabled ? "on" : "off");
483
484 if (pinfo.type.b.ame_enabled) {
485 st->print_cr("AME true memory in bytes : %llu", pinfo.true_memory);
486 st->print_cr("AME expanded memory in bytes : %llu", pinfo.expanded_memory);
487 }
488
489 st->print_cr("SMT : %s", pinfo.type.b.smt_capable ? "capable" : "not capable");
490 st->print_cr("SMT : %s", pinfo.type.b.smt_enabled ? "on" : "off");
491 int ocpus = pinfo.online_cpus > 0 ? pinfo.online_cpus : 1;
492 st->print_cr("LPAR threads : %d", cpuinfo.ncpus/ocpus);
493 st->print_cr("LPAR online virtual cpus : %d", pinfo.online_cpus);
494 st->print_cr("LPAR logical cpus : %d", cpuinfo.ncpus);
495 st->print_cr("LPAR maximum virtual cpus : %u", pinfo.max_cpus);
496 st->print_cr("LPAR minimum virtual cpus : %u", pinfo.min_cpus);
497 st->print_cr("LPAR entitled capacity : %4.2f", (double) (pinfo.entitled_proc_capacity/100.0));
498 st->print_cr("LPAR online memory : %llu MB", pinfo.online_memory);
499 st->print_cr("LPAR maximum memory : %llu MB", pinfo.max_memory);
500 st->print_cr("LPAR minimum memory : %llu MB", pinfo.min_memory);
501 #else
502 const char* info_file = "/proc/ppc64/lparcfg";
503 const char* kw[] = { "system_type=", // qemu indicates PowerKVM
504 "partition_entitled_capacity=", // entitled processor capacity percentage
505 "partition_max_entitled_capacity=",
506 "capacity_weight=", // partition CPU weight
507 "partition_active_processors=",
508 "partition_potential_processors=",
509 "entitled_proc_capacity_available=",
510 "capped=", // 0 - uncapped, 1 - vcpus capped at entitled processor capacity percentage
511 "shared_processor_mode=", // (non)dedicated partition
512 "system_potential_processors=",
513 "pool=", // CPU-pool number
514 "pool_capacity=",
515 "NumLpars=", // on non-KVM machines, NumLpars is not found for full partition mode machines
516 NULL };
517 if (!print_matching_lines_from_file(info_file, st, kw)) {
518 st->print_cr(" <%s Not Available>", info_file);
519 }
520 #endif
521 }
522
523 bool VM_Version::use_biased_locking() {
524 #if INCLUDE_RTM_OPT
525 // RTM locking is most useful when there is high lock contention and
526 // low data contention. With high lock contention the lock is usually
527 // inflated and biased locking is not suitable for that case.
528 // RTM locking code requires that biased locking is off.
529 // Note: we can't switch off UseBiasedLocking in get_processor_features()
530 // because it is used by Thread::allocate() which is called before
531 // VM_Version::initialize().
532 if (UseRTMLocking && UseBiasedLocking) {
533 if (FLAG_IS_DEFAULT(UseBiasedLocking)) {
534 FLAG_SET_DEFAULT(UseBiasedLocking, false);
535 } else {
536 warning("Biased locking is not supported with RTM locking; ignoring UseBiasedLocking flag." );
537 UseBiasedLocking = false;
538 }
539 }
540 #endif
541 return UseBiasedLocking;
542 }
543
544 void VM_Version::print_features() {
545 tty->print_cr("Version: %s L1_data_cache_line_size=%d", features_string(), L1_data_cache_line_size());
546
547 if (Verbose) {
548 if (ContendedPaddingWidth > 0) {
549 tty->cr();
550 tty->print_cr("ContendedPaddingWidth " INTX_FORMAT, ContendedPaddingWidth);
551 }
552 }
553 }
554
555 #ifdef COMPILER2
556 // Determine section size on power6: If section size is 8 instructions,
557 // there should be a difference between the two testloops of ~15 %. If
558 // no difference is detected the section is assumed to be 32 instructions.
559 void VM_Version::determine_section_size() {
560
561 int unroll = 80;
562
563 const int code_size = (2* unroll * 32 + 100)*BytesPerInstWord;
564
565 // Allocate space for the code.
566 ResourceMark rm;
567 CodeBuffer cb("detect_section_size", code_size, 0);
568 MacroAssembler* a = new MacroAssembler(&cb);
569
570 uint32_t *code = (uint32_t *)a->pc();
571 // Emit code.
572 void (*test1)() = (void(*)())(void *)a->function_entry();
573
574 Label l1;
575
576 a->li(R4, 1);
577 a->sldi(R4, R4, 28);
578 a->b(l1);
579 a->align(CodeEntryAlignment);
580
581 a->bind(l1);
582
583 for (int i = 0; i < unroll; i++) {
584 // Schleife 1
585 // ------- sector 0 ------------
586 // ;; 0
587 a->nop(); // 1
588 a->fpnop0(); // 2
589 a->fpnop1(); // 3
590 a->addi(R4,R4, -1); // 4
591
592 // ;; 1
593 a->nop(); // 5
594 a->fmr(F6, F6); // 6
595 a->fmr(F7, F7); // 7
596 a->endgroup(); // 8
597 // ------- sector 8 ------------
598
599 // ;; 2
600 a->nop(); // 9
601 a->nop(); // 10
602 a->fmr(F8, F8); // 11
603 a->fmr(F9, F9); // 12
604
605 // ;; 3
606 a->nop(); // 13
607 a->fmr(F10, F10); // 14
608 a->fmr(F11, F11); // 15
609 a->endgroup(); // 16
610 // -------- sector 16 -------------
611
612 // ;; 4
613 a->nop(); // 17
614 a->nop(); // 18
615 a->fmr(F15, F15); // 19
616 a->fmr(F16, F16); // 20
617
618 // ;; 5
619 a->nop(); // 21
620 a->fmr(F17, F17); // 22
621 a->fmr(F18, F18); // 23
622 a->endgroup(); // 24
623 // ------- sector 24 ------------
624
625 // ;; 6
626 a->nop(); // 25
627 a->nop(); // 26
628 a->fmr(F19, F19); // 27
629 a->fmr(F20, F20); // 28
630
631 // ;; 7
632 a->nop(); // 29
633 a->fmr(F21, F21); // 30
634 a->fmr(F22, F22); // 31
635 a->brnop0(); // 32
636
637 // ------- sector 32 ------------
638 }
639
640 // ;; 8
641 a->cmpdi(CCR0, R4, unroll); // 33
642 a->bge(CCR0, l1); // 34
643 a->blr();
644
645 // Emit code.
646 void (*test2)() = (void(*)())(void *)a->function_entry();
647 // uint32_t *code = (uint32_t *)a->pc();
648
649 Label l2;
650
651 a->li(R4, 1);
652 a->sldi(R4, R4, 28);
653 a->b(l2);
654 a->align(CodeEntryAlignment);
655
656 a->bind(l2);
657
658 for (int i = 0; i < unroll; i++) {
659 // Schleife 2
660 // ------- sector 0 ------------
661 // ;; 0
662 a->brnop0(); // 1
663 a->nop(); // 2
664 //a->cmpdi(CCR0, R4, unroll);
665 a->fpnop0(); // 3
666 a->fpnop1(); // 4
667 a->addi(R4,R4, -1); // 5
668
669 // ;; 1
670
671 a->nop(); // 6
672 a->fmr(F6, F6); // 7
673 a->fmr(F7, F7); // 8
674 // ------- sector 8 ---------------
675
676 // ;; 2
677 a->endgroup(); // 9
678
679 // ;; 3
680 a->nop(); // 10
681 a->nop(); // 11
682 a->fmr(F8, F8); // 12
683
684 // ;; 4
685 a->fmr(F9, F9); // 13
686 a->nop(); // 14
687 a->fmr(F10, F10); // 15
688
689 // ;; 5
690 a->fmr(F11, F11); // 16
691 // -------- sector 16 -------------
692
693 // ;; 6
694 a->endgroup(); // 17
695
696 // ;; 7
697 a->nop(); // 18
698 a->nop(); // 19
699 a->fmr(F15, F15); // 20
700
701 // ;; 8
702 a->fmr(F16, F16); // 21
703 a->nop(); // 22
704 a->fmr(F17, F17); // 23
705
706 // ;; 9
707 a->fmr(F18, F18); // 24
708 // -------- sector 24 -------------
709
710 // ;; 10
711 a->endgroup(); // 25
712
713 // ;; 11
714 a->nop(); // 26
715 a->nop(); // 27
716 a->fmr(F19, F19); // 28
717
718 // ;; 12
719 a->fmr(F20, F20); // 29
720 a->nop(); // 30
721 a->fmr(F21, F21); // 31
722
723 // ;; 13
724 a->fmr(F22, F22); // 32
725 }
726
727 // -------- sector 32 -------------
728 // ;; 14
729 a->cmpdi(CCR0, R4, unroll); // 33
730 a->bge(CCR0, l2); // 34
731
732 a->blr();
733 uint32_t *code_end = (uint32_t *)a->pc();
734 a->flush();
735
736 cb.insts()->set_end((u_char*)code_end);
737
738 double loop1_seconds,loop2_seconds, rel_diff;
739 uint64_t start1, stop1;
740
741 start1 = os::current_thread_cpu_time(false);
742 (*test1)();
743 stop1 = os::current_thread_cpu_time(false);
744 loop1_seconds = (stop1- start1) / (1000 *1000 *1000.0);
745
746
747 start1 = os::current_thread_cpu_time(false);
748 (*test2)();
749 stop1 = os::current_thread_cpu_time(false);
750
751 loop2_seconds = (stop1 - start1) / (1000 *1000 *1000.0);
752
753 rel_diff = (loop2_seconds - loop1_seconds) / loop1_seconds *100;
754
755 if (PrintAssembly || PrintStubCode) {
756 ttyLocker ttyl;
757 tty->print_cr("Decoding section size detection stub at " INTPTR_FORMAT " before execution:", p2i(code));
758 // Use existing decode function. This enables the [MachCode] format which is needed to DecodeErrorFile.
759 Disassembler::decode(&cb, (u_char*)code, (u_char*)code_end, tty);
760 tty->print_cr("Time loop1 :%f", loop1_seconds);
761 tty->print_cr("Time loop2 :%f", loop2_seconds);
762 tty->print_cr("(time2 - time1) / time1 = %f %%", rel_diff);
763
764 if (rel_diff > 12.0) {
765 tty->print_cr("Section Size 8 Instructions");
766 } else{
767 tty->print_cr("Section Size 32 Instructions or Power5");
768 }
769 }
770
771 #if 0 // TODO: PPC port
772 // Set sector size (if not set explicitly).
773 if (FLAG_IS_DEFAULT(Power6SectorSize128PPC64)) {
774 if (rel_diff > 12.0) {
775 PdScheduling::power6SectorSize = 0x20;
776 } else {
777 PdScheduling::power6SectorSize = 0x80;
778 }
779 } else if (Power6SectorSize128PPC64) {
780 PdScheduling::power6SectorSize = 0x80;
781 } else {
782 PdScheduling::power6SectorSize = 0x20;
783 }
784 #endif
785 if (UsePower6SchedulerPPC64) Unimplemented();
786 }
787 #endif // COMPILER2
788
789 void VM_Version::determine_features() {
790 #if defined(ABI_ELFv2)
791 // 1 InstWord per call for the blr instruction.
792 const int code_size = (num_features+1+2*1)*BytesPerInstWord;
793 #else
794 // 7 InstWords for each call (function descriptor + blr instruction).
795 const int code_size = (num_features+1+2*7)*BytesPerInstWord;
796 #endif
797 int features = 0;
798
799 // create test area
800 enum { BUFFER_SIZE = 2*4*K }; // Needs to be >=2* max cache line size (cache line size can't exceed min page size).
801 char test_area[BUFFER_SIZE];
802 char *mid_of_test_area = &test_area[BUFFER_SIZE>>1];
803
804 // Allocate space for the code.
805 ResourceMark rm;
806 CodeBuffer cb("detect_cpu_features", code_size, 0);
807 MacroAssembler* a = new MacroAssembler(&cb);
808
809 // Must be set to true so we can generate the test code.
810 _features = VM_Version::all_features_m;
811
812 // Emit code.
813 void (*test)(address addr, uint64_t offset)=(void(*)(address addr, uint64_t offset))(void *)a->function_entry();
814 uint32_t *code = (uint32_t *)a->pc();
815 // Don't use R0 in ldarx.
816 // Keep R3_ARG1 unmodified, it contains &field (see below).
817 // Keep R4_ARG2 unmodified, it contains offset = 0 (see below).
818 a->fsqrt(F3, F4); // code[0] -> fsqrt_m
819 a->fsqrts(F3, F4); // code[1] -> fsqrts_m
820 a->isel(R7, R5, R6, 0); // code[2] -> isel_m
821 a->ldarx_unchecked(R7, R3_ARG1, R4_ARG2, 1); // code[3] -> lxarx_m
822 a->cmpb(R7, R5, R6); // code[4] -> cmpb
823 a->popcntb(R7, R5); // code[5] -> popcntb
824 a->popcntw(R7, R5); // code[6] -> popcntw
825 a->fcfids(F3, F4); // code[7] -> fcfids
826 a->vand(VR0, VR0, VR0); // code[8] -> vand
827 // arg0 of lqarx must be an even register, (arg1 + arg2) must be a multiple of 16
828 a->lqarx_unchecked(R6, R3_ARG1, R4_ARG2, 1); // code[9] -> lqarx_m
829 a->vcipher(VR0, VR1, VR2); // code[10] -> vcipher
830 a->vpmsumb(VR0, VR1, VR2); // code[11] -> vpmsumb
831 a->mfdscr(R0); // code[12] -> mfdscr
832 a->lxvd2x(VSR0, R3_ARG1); // code[13] -> vsx
833 a->ldbrx(R7, R3_ARG1, R4_ARG2); // code[14] -> ldbrx
834 a->stdbrx(R7, R3_ARG1, R4_ARG2); // code[15] -> stdbrx
835 a->vshasigmaw(VR0, VR1, 1, 0xF); // code[16] -> vshasig
836 // rtm is determined by OS
837 a->darn(R7); // code[17] -> darn
838 a->blr();
839
840 // Emit function to set one cache line to zero. Emit function descriptor and get pointer to it.
841 void (*zero_cacheline_func_ptr)(char*) = (void(*)(char*))(void *)a->function_entry();
842 a->dcbz(R3_ARG1); // R3_ARG1 = addr
843 a->blr();
844
845 uint32_t *code_end = (uint32_t *)a->pc();
846 a->flush();
847 _features = VM_Version::unknown_m;
848
849 // Print the detection code.
850 if (PrintAssembly) {
851 ttyLocker ttyl;
852 tty->print_cr("Decoding cpu-feature detection stub at " INTPTR_FORMAT " before execution:", p2i(code));
853 Disassembler::decode((u_char*)code, (u_char*)code_end, tty);
854 }
855
856 // Measure cache line size.
857 memset(test_area, 0xFF, BUFFER_SIZE); // Fill test area with 0xFF.
858 (*zero_cacheline_func_ptr)(mid_of_test_area); // Call function which executes dcbz to the middle.
859 int count = 0; // count zeroed bytes
860 for (int i = 0; i < BUFFER_SIZE; i++) if (test_area[i] == 0) count++;
861 guarantee(is_power_of_2(count), "cache line size needs to be a power of 2");
862 _L1_data_cache_line_size = count;
863
864 // Execute code. Illegal instructions will be replaced by 0 in the signal handler.
865 VM_Version::_is_determine_features_test_running = true;
866 // We must align the first argument to 16 bytes because of the lqarx check.
867 (*test)(align_up((address)mid_of_test_area, 16), 0);
868 VM_Version::_is_determine_features_test_running = false;
869
870 // determine which instructions are legal.
871 int feature_cntr = 0;
872 if (code[feature_cntr++]) features |= fsqrt_m;
873 if (code[feature_cntr++]) features |= fsqrts_m;
874 if (code[feature_cntr++]) features |= isel_m;
875 if (code[feature_cntr++]) features |= lxarxeh_m;
876 if (code[feature_cntr++]) features |= cmpb_m;
877 if (code[feature_cntr++]) features |= popcntb_m;
878 if (code[feature_cntr++]) features |= popcntw_m;
879 if (code[feature_cntr++]) features |= fcfids_m;
880 if (code[feature_cntr++]) features |= vand_m;
881 if (code[feature_cntr++]) features |= lqarx_m;
882 if (code[feature_cntr++]) features |= vcipher_m;
883 if (code[feature_cntr++]) features |= vpmsumb_m;
884 if (code[feature_cntr++]) features |= mfdscr_m;
885 if (code[feature_cntr++]) features |= vsx_m;
886 if (code[feature_cntr++]) features |= ldbrx_m;
887 if (code[feature_cntr++]) features |= stdbrx_m;
888 if (code[feature_cntr++]) features |= vshasig_m;
889 // feature rtm_m is determined by OS
890 if (code[feature_cntr++]) features |= darn_m;
891
892 // Print the detection code.
893 if (PrintAssembly) {
894 ttyLocker ttyl;
895 tty->print_cr("Decoding cpu-feature detection stub at " INTPTR_FORMAT " after execution:", p2i(code));
896 Disassembler::decode((u_char*)code, (u_char*)code_end, tty);
897 }
898
899 _features = features;
900
901 #ifdef AIX
902 // To enable it on AIX it's necessary POWER8 or above and at least AIX 7.2.
903 // Actually, this is supported since AIX 7.1.. Unfortunately, this first
904 // contained bugs, so that it can only be enabled after AIX 7.1.3.30.
905 // The Java property os.version, which is used in RTM tests to decide
906 // whether the feature is available, only knows major and minor versions.
907 // We don't want to change this property, as user code might depend on it.
908 // So the tests can not check on subversion 3.30, and we only enable RTM
909 // with AIX 7.2.
910 if (has_lqarx()) { // POWER8 or above
911 if (os::Aix::os_version() >= 0x07020000) { // At least AIX 7.2.
912 _features |= rtm_m;
913 }
914 }
915 #endif
916 #if defined(LINUX) && defined(VM_LITTLE_ENDIAN)
917 unsigned long auxv = getauxval(AT_HWCAP2);
918
919 if (auxv & PPC_FEATURE2_HTM_NOSC) {
920 if (auxv & PPC_FEATURE2_HAS_HTM) {
921 // TM on POWER8 and POWER9 in compat mode (VM) is supported by the JVM.
922 // TM on POWER9 DD2.1 NV (baremetal) is not supported by the JVM (TM on
923 // POWER9 DD2.1 NV has a few issues that need a couple of firmware
924 // and kernel workarounds, so there is a new mode only supported
925 // on non-virtualized P9 machines called HTM with no Suspend Mode).
926 // TM on POWER9 D2.2+ NV is not supported at all by Linux.
927 _features |= rtm_m;
928 }
929 }
930 #endif
931 }
932
933 // Power 8: Configure Data Stream Control Register.
934 void VM_Version::config_dscr() {
935 // 7 InstWords for each call (function descriptor + blr instruction).
936 const int code_size = (2+2*7)*BytesPerInstWord;
937
938 // Allocate space for the code.
939 ResourceMark rm;
940 CodeBuffer cb("config_dscr", code_size, 0);
941 MacroAssembler* a = new MacroAssembler(&cb);
942
943 // Emit code.
944 uint64_t (*get_dscr)() = (uint64_t(*)())(void *)a->function_entry();
945 uint32_t *code = (uint32_t *)a->pc();
946 a->mfdscr(R3);
947 a->blr();
948
949 void (*set_dscr)(long) = (void(*)(long))(void *)a->function_entry();
950 a->mtdscr(R3);
951 a->blr();
952
953 uint32_t *code_end = (uint32_t *)a->pc();
954 a->flush();
955
956 // Print the detection code.
957 if (PrintAssembly) {
958 ttyLocker ttyl;
959 tty->print_cr("Decoding dscr configuration stub at " INTPTR_FORMAT " before execution:", p2i(code));
960 Disassembler::decode((u_char*)code, (u_char*)code_end, tty);
961 }
962
963 // Apply the configuration if needed.
964 _dscr_val = (*get_dscr)();
965 if (Verbose) {
966 tty->print_cr("dscr value was 0x%lx" , _dscr_val);
967 }
968 bool change_requested = false;
969 if (DSCR_PPC64 != (uintx)-1) {
970 _dscr_val = DSCR_PPC64;
971 change_requested = true;
972 }
973 if (DSCR_DPFD_PPC64 <= 7) {
974 uint64_t mask = 0x7;
975 if ((_dscr_val & mask) != DSCR_DPFD_PPC64) {
976 _dscr_val = (_dscr_val & ~mask) | (DSCR_DPFD_PPC64);
977 change_requested = true;
978 }
979 }
980 if (DSCR_URG_PPC64 <= 7) {
981 uint64_t mask = 0x7 << 6;
982 if ((_dscr_val & mask) != DSCR_DPFD_PPC64 << 6) {
983 _dscr_val = (_dscr_val & ~mask) | (DSCR_URG_PPC64 << 6);
984 change_requested = true;
985 }
986 }
987 if (change_requested) {
988 (*set_dscr)(_dscr_val);
989 if (Verbose) {
990 tty->print_cr("dscr was set to 0x%lx" , (*get_dscr)());
991 }
992 }
993 }
994
995 static uint64_t saved_features = 0;
996
997 void VM_Version::allow_all() {
998 saved_features = _features;
999 _features = all_features_m;
1000 }
1001
1002 void VM_Version::revert() {
1003 _features = saved_features;
1004 }