1652 
1653 // Register for MODI projection of divmodI
1654 RegMask Matcher::modI_proj_mask() {
1655   return INT_RDX_REG_mask();
1656 }
1657 
1658 // Register for DIVL projection of divmodL
1659 RegMask Matcher::divL_proj_mask() {
1660   return LONG_RAX_REG_mask();
1661 }
1662 
1663 // Register for MODL projection of divmodL
1664 RegMask Matcher::modL_proj_mask() {
1665   return LONG_RDX_REG_mask();
1666 }
1667 
1668 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
1669   return PTR_RBP_REG_mask();
1670 }
1671 
1672 static Address build_address(int b, int i, int s, int d) {
1673   Register index = as_Register(i);
1674   Address::ScaleFactor scale = (Address::ScaleFactor)s;
1675   if (index == rsp) {
1676     index = noreg;
1677     scale = Address::no_scale;
1678   }
1679   Address addr(as_Register(b), index, scale, d);
1680   return addr;
1681 }
1682 
1683 %}
1684 
1685 //----------ENCODING BLOCK-----------------------------------------------------
1686 // This block specifies the encoding classes used by the compiler to
1687 // output byte streams.  Encoding classes are parameterized macros
1688 // used by Machine Instruction Nodes in order to generate the bit
1689 // encoding of the instruction.  Operands specify their base encoding
1690 // interface with the interface keyword.  There are currently
1691 // supported four interfaces, REG_INTER, CONST_INTER, MEMORY_INTER, &
1692 // COND_INTER.  REG_INTER causes an operand to generate a function
1693 // which returns its register number when queried.  CONST_INTER causes
1694 // an operand to generate a function which returns the value of the
1695 // constant when queried.  MEMORY_INTER causes an operand to generate
1696 // four functions which return the Base Register, the Index Register,
1697 // the Scale Value, and the Offset Value of the operand when queried.
1698 // COND_INTER causes an operand to generate six functions which return
1699 // the encoding code (ie - encoding bits for the instruction)
1700 // associated with each basic boolean condition for a conditional
1701 // instruction.
1702 //

1652 
1653 // Register for MODI projection of divmodI
1654 RegMask Matcher::modI_proj_mask() {
1655   return INT_RDX_REG_mask();
1656 }
1657 
1658 // Register for DIVL projection of divmodL
1659 RegMask Matcher::divL_proj_mask() {
1660   return LONG_RAX_REG_mask();
1661 }
1662 
1663 // Register for MODL projection of divmodL
1664 RegMask Matcher::modL_proj_mask() {
1665   return LONG_RDX_REG_mask();
1666 }
1667 
1668 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
1669   return PTR_RBP_REG_mask();
1670 }
1671 











1672 %}
1673 
1674 //----------ENCODING BLOCK-----------------------------------------------------
1675 // This block specifies the encoding classes used by the compiler to
1676 // output byte streams.  Encoding classes are parameterized macros
1677 // used by Machine Instruction Nodes in order to generate the bit
1678 // encoding of the instruction.  Operands specify their base encoding
1679 // interface with the interface keyword.  There are currently
1680 // supported four interfaces, REG_INTER, CONST_INTER, MEMORY_INTER, &
1681 // COND_INTER.  REG_INTER causes an operand to generate a function
1682 // which returns its register number when queried.  CONST_INTER causes
1683 // an operand to generate a function which returns the value of the
1684 // constant when queried.  MEMORY_INTER causes an operand to generate
1685 // four functions which return the Base Register, the Index Register,
1686 // the Scale Value, and the Offset Value of the operand when queried.
1687 // COND_INTER causes an operand to generate six functions which return
1688 // the encoding code (ie - encoding bits for the instruction)
1689 // associated with each basic boolean condition for a conditional
1690 // instruction.
1691 //