src/hotspot/share/c1/c1_LinearScan.cpp

rev 59103 : imported patch hotspot

*** 2127,2141 ****
          }
  
  #ifdef _LP64
          return LIR_OprFact::double_cpu(assigned_reg, assigned_reg);
  #else
! #if defined(SPARC) || defined(PPC32)
          return LIR_OprFact::double_cpu(assigned_regHi, assigned_reg);
  #else
          return LIR_OprFact::double_cpu(assigned_reg, assigned_regHi);
! #endif // SPARC
  #endif // LP64
        }
  
  #ifndef __SOFTFP__
        case T_FLOAT: {
--- 2127,2141 ----
          }
  
  #ifdef _LP64
          return LIR_OprFact::double_cpu(assigned_reg, assigned_reg);
  #else
! #if defined(PPC32)
          return LIR_OprFact::double_cpu(assigned_regHi, assigned_reg);
  #else
          return LIR_OprFact::double_cpu(assigned_reg, assigned_regHi);
! #endif // PPC32
  #endif // LP64
        }
  
  #ifndef __SOFTFP__
        case T_FLOAT: {
*** 2171,2186 ****
            assert(interval->assigned_regHi() == any_reg, "must not have hi register (double xmm values are stored in one register)");
            return LIR_OprFact::double_xmm(assigned_reg - pd_first_xmm_reg);
          }
  #endif // X86
  
! #ifdef SPARC
!         assert(assigned_reg >= pd_first_fpu_reg && assigned_reg <= pd_last_fpu_reg, "no fpu register");
!         assert(interval->assigned_regHi() >= pd_first_fpu_reg && interval->assigned_regHi() <= pd_last_fpu_reg, "no fpu register");
!         assert(assigned_reg % 2 == 0 && assigned_reg + 1 == interval->assigned_regHi(), "must be sequential and even");
!         LIR_Opr result = LIR_OprFact::double_fpu(interval->assigned_regHi() - pd_first_fpu_reg, assigned_reg - pd_first_fpu_reg);
! #elif defined(ARM32)
          assert(assigned_reg >= pd_first_fpu_reg && assigned_reg <= pd_last_fpu_reg, "no fpu register");
          assert(interval->assigned_regHi() >= pd_first_fpu_reg && interval->assigned_regHi() <= pd_last_fpu_reg, "no fpu register");
          assert(assigned_reg % 2 == 0 && assigned_reg + 1 == interval->assigned_regHi(), "must be sequential and even");
          LIR_Opr result = LIR_OprFact::double_fpu(assigned_reg - pd_first_fpu_reg, interval->assigned_regHi() - pd_first_fpu_reg);
  #else
--- 2171,2181 ----
            assert(interval->assigned_regHi() == any_reg, "must not have hi register (double xmm values are stored in one register)");
            return LIR_OprFact::double_xmm(assigned_reg - pd_first_xmm_reg);
          }
  #endif // X86
  
! #if defined(ARM32)
          assert(assigned_reg >= pd_first_fpu_reg && assigned_reg <= pd_last_fpu_reg, "no fpu register");
          assert(interval->assigned_regHi() >= pd_first_fpu_reg && interval->assigned_regHi() <= pd_last_fpu_reg, "no fpu register");
          assert(assigned_reg % 2 == 0 && assigned_reg + 1 == interval->assigned_regHi(), "must be sequential and even");
          LIR_Opr result = LIR_OprFact::double_fpu(assigned_reg - pd_first_fpu_reg, interval->assigned_regHi() - pd_first_fpu_reg);
  #else
*** 2776,2788 ****
        assert(opr->fpu_regnrLo() == opr->fpu_regnrHi(), "assumed in calculation (only fpu_regnrLo is used)");
  #endif
  #ifdef AMD64
        assert(false, "FPU not used on x86-64");
  #endif
- #ifdef SPARC
-       assert(opr->fpu_regnrLo() == opr->fpu_regnrHi() + 1, "assumed in calculation (only fpu_regnrHi is used)");
- #endif
  #ifdef ARM32
        assert(opr->fpu_regnrHi() == opr->fpu_regnrLo() + 1, "assumed in calculation (only fpu_regnrLo is used)");
  #endif
  #ifdef PPC32
        assert(opr->fpu_regnrLo() == opr->fpu_regnrHi(), "assumed in calculation (only fpu_regnrHi is used)");
--- 2771,2780 ----