1175 if( deflrg.reg() >= LRG::SPILL_REG ) { // Spilled?
1176 uint slidx = lrg2reach[defidx];
1177 // Add to defs list for later assignment of new live range number
1178 defs->push(n);
1179 // Set a flag on the Node indicating it has already spilled.
1180 // Only do it for capacity spills not conflict spills.
1181 if( !deflrg._direct_conflict )
1182 set_was_spilled(n);
1183 assert(!n->is_Phi(),"Cannot insert Phi into DEFS list");
1184 // Grab UP info for DEF
1185 const RegMask &dmask = n->out_RegMask();
1186 bool defup = dmask.is_UP();
1187 uint ireg = n->ideal_reg();
1188 bool is_vect = RegMask::is_vector(ireg);
1189 // Only split at Def if this is a HRP block or bound (and spilled once)
1190 if( !n->rematerialize() &&
1191 (((dmask.is_bound(ireg) || (!is_vect && dmask.is_misaligned_pair())) &&
1192 (deflrg._direct_conflict || deflrg._must_spill)) ||
1193 // Check for LRG being up in a register and we are inside a high
1194 // pressure area. Spill it down immediately.
1195 (defup && is_high_pressure(b,&deflrg,insidx))) ) {
1196 assert( !n->rematerialize(), "" );
1197 assert( !n->is_SpillCopy(), "" );
1198 // Do a split at the def site.
1199 maxlrg = split_DEF( n, b, insidx, maxlrg, Reachblock, debug_defs, splits, slidx );
1200 // If it wasn't split bail
1201 if (!maxlrg) {
1202 return 0;
1203 }
1204 // Split DEF's Down
1205 UPblock[slidx] = 0;
1206 #ifndef PRODUCT
1207 // DEBUG
1208 if( trace_spilling() ) {
1209 tty->print("\nNew Split DOWN DEF of Spill Idx ");
1210 tty->print("%d, UP %d:\n",slidx,false);
1211 n->dump();
1212 }
1213 #endif
1214 }
1215 else { // Neither bound nor HRP, must be LRP
1216 // otherwise, just record the def
1217 Reachblock[slidx] = n;
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1175 if( deflrg.reg() >= LRG::SPILL_REG ) { // Spilled?
1176 uint slidx = lrg2reach[defidx];
1177 // Add to defs list for later assignment of new live range number
1178 defs->push(n);
1179 // Set a flag on the Node indicating it has already spilled.
1180 // Only do it for capacity spills not conflict spills.
1181 if( !deflrg._direct_conflict )
1182 set_was_spilled(n);
1183 assert(!n->is_Phi(),"Cannot insert Phi into DEFS list");
1184 // Grab UP info for DEF
1185 const RegMask &dmask = n->out_RegMask();
1186 bool defup = dmask.is_UP();
1187 uint ireg = n->ideal_reg();
1188 bool is_vect = RegMask::is_vector(ireg);
1189 // Only split at Def if this is a HRP block or bound (and spilled once)
1190 if( !n->rematerialize() &&
1191 (((dmask.is_bound(ireg) || (!is_vect && dmask.is_misaligned_pair())) &&
1192 (deflrg._direct_conflict || deflrg._must_spill)) ||
1193 // Check for LRG being up in a register and we are inside a high
1194 // pressure area. Spill it down immediately.
1195 (defup && is_high_pressure(b,&deflrg,insidx) && !n->is_SpillCopy())) ) {
1196 assert( !n->rematerialize(), "" );
1197 // Do a split at the def site.
1198 maxlrg = split_DEF( n, b, insidx, maxlrg, Reachblock, debug_defs, splits, slidx );
1199 // If it wasn't split bail
1200 if (!maxlrg) {
1201 return 0;
1202 }
1203 // Split DEF's Down
1204 UPblock[slidx] = 0;
1205 #ifndef PRODUCT
1206 // DEBUG
1207 if( trace_spilling() ) {
1208 tty->print("\nNew Split DOWN DEF of Spill Idx ");
1209 tty->print("%d, UP %d:\n",slidx,false);
1210 n->dump();
1211 }
1212 #endif
1213 }
1214 else { // Neither bound nor HRP, must be LRP
1215 // otherwise, just record the def
1216 Reachblock[slidx] = n;
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