386 void InterpreterMacroAssembler::prepare_to_jump_from_interpreted() {
387 // set sender sp
388 lea(rsi, Address(rsp, wordSize));
389 // record last_sp
390 movptr(Address(rbp, frame::interpreter_frame_last_sp_offset * wordSize), rsi);
391 }
392
393
394 // Jump to from_interpreted entry of a call unless single stepping is possible
395 // in this thread in which case we must call the i2i entry
396 void InterpreterMacroAssembler::jump_from_interpreted(Register method, Register temp) {
397 prepare_to_jump_from_interpreted();
398
399 if (JvmtiExport::can_post_interpreter_events()) {
400 Label run_compiled_code;
401 // JVMTI events, such as single-stepping, are implemented partly by avoiding running
402 // compiled code in threads for which the event is enabled. Check here for
403 // interp_only_mode if these events CAN be enabled.
404 get_thread(temp);
405 // interp_only is an int, on little endian it is sufficient to test the byte only
406 // Is a cmpl faster (ce
407 cmpb(Address(temp, JavaThread::interp_only_mode_offset()), 0);
408 jcc(Assembler::zero, run_compiled_code);
409 jmp(Address(method, methodOopDesc::interpreter_entry_offset()));
410 bind(run_compiled_code);
411 }
412
413 jmp(Address(method, methodOopDesc::from_interpreted_offset()));
414
415 }
416
417
418 // The following two routines provide a hook so that an implementation
419 // can schedule the dispatch in two parts. Intel does not do this.
420 void InterpreterMacroAssembler::dispatch_prolog(TosState state, int step) {
421 // Nothing Intel-specific to be done here.
422 }
423
424 void InterpreterMacroAssembler::dispatch_epilog(TosState state, int step) {
425 dispatch_next(state, step);
426 }
427
428 void InterpreterMacroAssembler::dispatch_base(TosState state, address* table,
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386 void InterpreterMacroAssembler::prepare_to_jump_from_interpreted() {
387 // set sender sp
388 lea(rsi, Address(rsp, wordSize));
389 // record last_sp
390 movptr(Address(rbp, frame::interpreter_frame_last_sp_offset * wordSize), rsi);
391 }
392
393
394 // Jump to from_interpreted entry of a call unless single stepping is possible
395 // in this thread in which case we must call the i2i entry
396 void InterpreterMacroAssembler::jump_from_interpreted(Register method, Register temp) {
397 prepare_to_jump_from_interpreted();
398
399 if (JvmtiExport::can_post_interpreter_events()) {
400 Label run_compiled_code;
401 // JVMTI events, such as single-stepping, are implemented partly by avoiding running
402 // compiled code in threads for which the event is enabled. Check here for
403 // interp_only_mode if these events CAN be enabled.
404 get_thread(temp);
405 // interp_only is an int, on little endian it is sufficient to test the byte only
406 // Is a cmpl faster?
407 cmpb(Address(temp, JavaThread::interp_only_mode_offset()), 0);
408 jccb(Assembler::zero, run_compiled_code);
409 jmp(Address(method, methodOopDesc::interpreter_entry_offset()));
410 bind(run_compiled_code);
411 }
412
413 jmp(Address(method, methodOopDesc::from_interpreted_offset()));
414
415 }
416
417
418 // The following two routines provide a hook so that an implementation
419 // can schedule the dispatch in two parts. Intel does not do this.
420 void InterpreterMacroAssembler::dispatch_prolog(TosState state, int step) {
421 // Nothing Intel-specific to be done here.
422 }
423
424 void InterpreterMacroAssembler::dispatch_epilog(TosState state, int step) {
425 dispatch_next(state, step);
426 }
427
428 void InterpreterMacroAssembler::dispatch_base(TosState state, address* table,
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