1 /*
   2  * Copyright (c) 1997, 2018, Oracle and/or its affiliates. All rights reserved.
   3  * Copyright (c) 2014, 2015, Red Hat Inc. All rights reserved.
   4  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   5  *
   6  * This code is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License version 2 only, as
   8  * published by the Free Software Foundation.
   9  *
  10  * This code is distributed in the hope that it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  13  * version 2 for more details (a copy is included in the LICENSE file that
  14  * accompanied this code).
  15  *
  16  * You should have received a copy of the GNU General Public License version
  17  * 2 along with this work; if not, write to the Free Software Foundation,
  18  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  19  *
  20  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  21  * or visit www.oracle.com if you need additional information or have any
  22  * questions.

1101 
1102 #undef INSN
1103 
1104 #define INSN(NAME, opc)                         \
1105   void NAME() {                 \
1106     branch_reg(dummy_reg, opc);         \
1107   }
1108 
1109   INSN(eret, 0b0100);
1110   INSN(drps, 0b0101);
1111 
1112 #undef INSN
1113 
1114   // Load/store exclusive
1115   enum operand_size { byte, halfword, word, xword };
1116 
1117   void load_store_exclusive(Register Rs, Register Rt1, Register Rt2,
1118     Register Rn, enum operand_size sz, int op, bool ordered) {
1119     starti;
1120     f(sz, 31, 30), f(0b001000, 29, 24), f(op, 23, 21);
1121     rf(Rs, 16), f(ordered, 15), rf(Rt2, 10), srf(Rn, 5), rf(Rt1, 0);
1122   }
1123 
1124   void load_exclusive(Register dst, Register addr,
1125                       enum operand_size sz, bool ordered) {
1126     load_store_exclusive(dummy_reg, dst, dummy_reg, addr,
1127                          sz, 0b010, ordered);
1128   }
1129 
1130   void store_exclusive(Register status, Register new_val, Register addr,
1131                        enum operand_size sz, bool ordered) {
1132     load_store_exclusive(status, new_val, dummy_reg, addr,
1133                          sz, 0b000, ordered);
1134   }
1135 
1136 #define INSN4(NAME, sz, op, o0) /* Four registers */                    \
1137   void NAME(Register Rs, Register Rt1, Register Rt2, Register Rn) {     \
1138     guarantee(Rs != Rn && Rs != Rt1 && Rs != Rt2, "unpredictable instruction"); \
1139     load_store_exclusive(Rs, Rt1, Rt2, Rn, sz, op, o0);                 \
1140   }
1141 

   1 /*
   2  * Copyright (c) 1997, 2019, Oracle and/or its affiliates. All rights reserved.
   3  * Copyright (c) 2014, 2015, Red Hat Inc. All rights reserved.
   4  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   5  *
   6  * This code is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License version 2 only, as
   8  * published by the Free Software Foundation.
   9  *
  10  * This code is distributed in the hope that it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  13  * version 2 for more details (a copy is included in the LICENSE file that
  14  * accompanied this code).
  15  *
  16  * You should have received a copy of the GNU General Public License version
  17  * 2 along with this work; if not, write to the Free Software Foundation,
  18  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  19  *
  20  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  21  * or visit www.oracle.com if you need additional information or have any
  22  * questions.

1101 
1102 #undef INSN
1103 
1104 #define INSN(NAME, opc)                         \
1105   void NAME() {                 \
1106     branch_reg(dummy_reg, opc);         \
1107   }
1108 
1109   INSN(eret, 0b0100);
1110   INSN(drps, 0b0101);
1111 
1112 #undef INSN
1113 
1114   // Load/store exclusive
1115   enum operand_size { byte, halfword, word, xword };
1116 
1117   void load_store_exclusive(Register Rs, Register Rt1, Register Rt2,
1118     Register Rn, enum operand_size sz, int op, bool ordered) {
1119     starti;
1120     f(sz, 31, 30), f(0b001000, 29, 24), f(op, 23, 21);
1121     rf(Rs, 16), f(ordered, 15), rf(Rt2, 10), srf(Rn, 5), zrf(Rt1, 0);
1122   }
1123 
1124   void load_exclusive(Register dst, Register addr,
1125                       enum operand_size sz, bool ordered) {
1126     load_store_exclusive(dummy_reg, dst, dummy_reg, addr,
1127                          sz, 0b010, ordered);
1128   }
1129 
1130   void store_exclusive(Register status, Register new_val, Register addr,
1131                        enum operand_size sz, bool ordered) {
1132     load_store_exclusive(status, new_val, dummy_reg, addr,
1133                          sz, 0b000, ordered);
1134   }
1135 
1136 #define INSN4(NAME, sz, op, o0) /* Four registers */                    \
1137   void NAME(Register Rs, Register Rt1, Register Rt2, Register Rn) {     \
1138     guarantee(Rs != Rn && Rs != Rt1 && Rs != Rt2, "unpredictable instruction"); \
1139     load_store_exclusive(Rs, Rt1, Rt2, Rn, sz, op, o0);                 \
1140   }
1141