1 /*
2 * Copyright (c) 1997, 2020, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2014, 2020, Red Hat Inc. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #ifndef CPU_AARCH64_ASSEMBLER_AARCH64_HPP
27 #define CPU_AARCH64_ASSEMBLER_AARCH64_HPP
28
29 #include "asm/register.hpp"
30
31 // definitions of various symbolic names for machine registers
32
33 // First intercalls between C and Java which use 8 general registers
34 // and 8 floating registers
35
36 // we also have to copy between x86 and ARM registers but that's a
37 // secondary complication -- not all code employing C call convention
38 // executes as x86 code though -- we generate some of it
39
40 class Argument {
41 public:
42 enum {
43 n_int_register_parameters_c = 8, // r0, r1, ... r7 (c_rarg0, c_rarg1, ...)
44 n_float_register_parameters_c = 8, // v0, v1, ... v7 (c_farg0, c_farg1, ... )
45
46 n_int_register_parameters_j = 8, // r1, ... r7, r0 (rj_rarg0, j_rarg1, ...
47 n_float_register_parameters_j = 8 // v0, v1, ... v7 (j_farg0, j_farg1, ...
48 };
49 };
50
51 REGISTER_DECLARATION(Register, c_rarg0, r0);
52 REGISTER_DECLARATION(Register, c_rarg1, r1);
53 REGISTER_DECLARATION(Register, c_rarg2, r2);
54 REGISTER_DECLARATION(Register, c_rarg3, r3);
55 REGISTER_DECLARATION(Register, c_rarg4, r4);
56 REGISTER_DECLARATION(Register, c_rarg5, r5);
57 REGISTER_DECLARATION(Register, c_rarg6, r6);
58 REGISTER_DECLARATION(Register, c_rarg7, r7);
59
60 REGISTER_DECLARATION(FloatRegister, c_farg0, v0);
61 REGISTER_DECLARATION(FloatRegister, c_farg1, v1);
62 REGISTER_DECLARATION(FloatRegister, c_farg2, v2);
63 REGISTER_DECLARATION(FloatRegister, c_farg3, v3);
64 REGISTER_DECLARATION(FloatRegister, c_farg4, v4);
65 REGISTER_DECLARATION(FloatRegister, c_farg5, v5);
66 REGISTER_DECLARATION(FloatRegister, c_farg6, v6);
67 REGISTER_DECLARATION(FloatRegister, c_farg7, v7);
68
69 // Symbolically name the register arguments used by the Java calling convention.
70 // We have control over the convention for java so we can do what we please.
71 // What pleases us is to offset the java calling convention so that when
72 // we call a suitable jni method the arguments are lined up and we don't
73 // have to do much shuffling. A suitable jni method is non-static and a
74 // small number of arguments
75 //
76 // |--------------------------------------------------------------------|
77 // | c_rarg0 c_rarg1 c_rarg2 c_rarg3 c_rarg4 c_rarg5 c_rarg6 c_rarg7 |
78 // |--------------------------------------------------------------------|
79 // | r0 r1 r2 r3 r4 r5 r6 r7 |
80 // |--------------------------------------------------------------------|
81 // | j_rarg7 j_rarg0 j_rarg1 j_rarg2 j_rarg3 j_rarg4 j_rarg5 j_rarg6 |
82 // |--------------------------------------------------------------------|
83
84
85 REGISTER_DECLARATION(Register, j_rarg0, c_rarg1);
86 REGISTER_DECLARATION(Register, j_rarg1, c_rarg2);
87 REGISTER_DECLARATION(Register, j_rarg2, c_rarg3);
88 REGISTER_DECLARATION(Register, j_rarg3, c_rarg4);
89 REGISTER_DECLARATION(Register, j_rarg4, c_rarg5);
90 REGISTER_DECLARATION(Register, j_rarg5, c_rarg6);
91 REGISTER_DECLARATION(Register, j_rarg6, c_rarg7);
92 REGISTER_DECLARATION(Register, j_rarg7, c_rarg0);
93
94 // Java floating args are passed as per C
95
96 REGISTER_DECLARATION(FloatRegister, j_farg0, v0);
97 REGISTER_DECLARATION(FloatRegister, j_farg1, v1);
98 REGISTER_DECLARATION(FloatRegister, j_farg2, v2);
99 REGISTER_DECLARATION(FloatRegister, j_farg3, v3);
100 REGISTER_DECLARATION(FloatRegister, j_farg4, v4);
101 REGISTER_DECLARATION(FloatRegister, j_farg5, v5);
102 REGISTER_DECLARATION(FloatRegister, j_farg6, v6);
103 REGISTER_DECLARATION(FloatRegister, j_farg7, v7);
104
105 // registers used to hold VM data either temporarily within a method
106 // or across method calls
107
108 // volatile (caller-save) registers
109
110 // r8 is used for indirect result location return
111 // we use it and r9 as scratch registers
112 REGISTER_DECLARATION(Register, rscratch1, r8);
113 REGISTER_DECLARATION(Register, rscratch2, r9);
114
115 // current method -- must be in a call-clobbered register
116 REGISTER_DECLARATION(Register, rmethod, r12);
117
118 // non-volatile (callee-save) registers are r16-29
119 // of which the following are dedicated global state
120
121 // link register
122 REGISTER_DECLARATION(Register, lr, r30);
123 // frame pointer
124 REGISTER_DECLARATION(Register, rfp, r29);
125 // current thread
126 REGISTER_DECLARATION(Register, rthread, r28);
127 // base of heap
128 REGISTER_DECLARATION(Register, rheapbase, r27);
129 // constant pool cache
130 REGISTER_DECLARATION(Register, rcpool, r26);
131 // monitors allocated on stack
132 REGISTER_DECLARATION(Register, rmonitors, r25);
133 // locals on stack
134 REGISTER_DECLARATION(Register, rlocals, r24);
135 // bytecode pointer
136 REGISTER_DECLARATION(Register, rbcp, r22);
137 // Dispatch table base
138 REGISTER_DECLARATION(Register, rdispatch, r21);
139 // Java stack pointer
140 REGISTER_DECLARATION(Register, esp, r20);
141
142 #define assert_cond(ARG1) assert(ARG1, #ARG1)
143
144 namespace asm_util {
145 uint32_t encode_logical_immediate(bool is32, uint64_t imm);
146 };
147
148 using namespace asm_util;
149
150
151 class Assembler;
152
153 class Instruction_aarch64 {
154 unsigned insn;
155 #ifdef ASSERT
156 unsigned bits;
157 #endif
158 Assembler *assem;
159
160 public:
161
162 Instruction_aarch64(class Assembler *as) {
163 #ifdef ASSERT
164 bits = 0;
165 #endif
166 insn = 0;
167 assem = as;
168 }
169
170 inline ~Instruction_aarch64();
171
172 unsigned &get_insn() { return insn; }
173 #ifdef ASSERT
174 unsigned &get_bits() { return bits; }
175 #endif
176
177 static inline int32_t extend(unsigned val, int hi = 31, int lo = 0) {
178 union {
179 unsigned u;
180 int n;
181 };
182
183 u = val << (31 - hi);
184 n = n >> (31 - hi + lo);
185 return n;
186 }
187
188 static inline uint32_t extract(uint32_t val, int msb, int lsb) {
189 int nbits = msb - lsb + 1;
190 assert_cond(msb >= lsb);
191 uint32_t mask = (1U << nbits) - 1;
192 uint32_t result = val >> lsb;
193 result &= mask;
194 return result;
195 }
196
197 static inline int32_t sextract(uint32_t val, int msb, int lsb) {
198 uint32_t uval = extract(val, msb, lsb);
199 return extend(uval, msb - lsb);
200 }
201
202 static void patch(address a, int msb, int lsb, uint64_t val) {
203 int nbits = msb - lsb + 1;
204 guarantee(val < (1U << nbits), "Field too big for insn");
205 assert_cond(msb >= lsb);
206 unsigned mask = (1U << nbits) - 1;
207 val <<= lsb;
208 mask <<= lsb;
209 unsigned target = *(unsigned *)a;
210 target &= ~mask;
211 target |= val;
212 *(unsigned *)a = target;
213 }
214
215 static void spatch(address a, int msb, int lsb, int64_t val) {
216 int nbits = msb - lsb + 1;
217 int64_t chk = val >> (nbits - 1);
218 guarantee (chk == -1 || chk == 0, "Field too big for insn");
219 unsigned uval = val;
220 unsigned mask = (1U << nbits) - 1;
221 uval &= mask;
222 uval <<= lsb;
223 mask <<= lsb;
224 unsigned target = *(unsigned *)a;
225 target &= ~mask;
226 target |= uval;
227 *(unsigned *)a = target;
228 }
229
230 void f(unsigned val, int msb, int lsb) {
231 int nbits = msb - lsb + 1;
232 guarantee(val < (1U << nbits), "Field too big for insn");
233 assert_cond(msb >= lsb);
234 unsigned mask = (1U << nbits) - 1;
235 val <<= lsb;
236 mask <<= lsb;
237 insn |= val;
238 assert_cond((bits & mask) == 0);
239 #ifdef ASSERT
240 bits |= mask;
241 #endif
242 }
243
244 void f(unsigned val, int bit) {
245 f(val, bit, bit);
246 }
247
248 void sf(int64_t val, int msb, int lsb) {
249 int nbits = msb - lsb + 1;
250 int64_t chk = val >> (nbits - 1);
251 guarantee (chk == -1 || chk == 0, "Field too big for insn");
252 unsigned uval = val;
253 unsigned mask = (1U << nbits) - 1;
254 uval &= mask;
255 f(uval, lsb + nbits - 1, lsb);
256 }
257
258 void rf(Register r, int lsb) {
259 f(r->encoding_nocheck(), lsb + 4, lsb);
260 }
261
262 // reg|ZR
263 void zrf(Register r, int lsb) {
264 f(r->encoding_nocheck() - (r == zr), lsb + 4, lsb);
265 }
266
267 // reg|SP
268 void srf(Register r, int lsb) {
269 f(r == sp ? 31 : r->encoding_nocheck(), lsb + 4, lsb);
270 }
271
272 void rf(FloatRegister r, int lsb) {
273 f(r->encoding_nocheck(), lsb + 4, lsb);
274 }
275
276 void prf(PRegister r, int lsb) {
277 f(r->encoding_nocheck(), lsb + 3, lsb);
278 }
279
280 void pgrf(PRegister r, int lsb) {
281 f(r->encoding_nocheck(), lsb + 2, lsb);
282 }
283
284 unsigned get(int msb = 31, int lsb = 0) {
285 int nbits = msb - lsb + 1;
286 unsigned mask = ((1U << nbits) - 1) << lsb;
287 assert_cond((bits & mask) == mask);
288 return (insn & mask) >> lsb;
289 }
290
291 void fixed(unsigned value, unsigned mask) {
292 assert_cond ((mask & bits) == 0);
293 #ifdef ASSERT
294 bits |= mask;
295 #endif
296 insn |= value;
297 }
298 };
299
300 #define starti Instruction_aarch64 do_not_use(this); set_current(&do_not_use)
301
302 class PrePost {
303 int _offset;
304 Register _r;
305 public:
306 PrePost(Register reg, int o) : _offset(o), _r(reg) { }
307 int offset() { return _offset; }
308 Register reg() { return _r; }
309 };
310
311 class Pre : public PrePost {
312 public:
313 Pre(Register reg, int o) : PrePost(reg, o) { }
314 };
315 class Post : public PrePost {
316 Register _idx;
317 bool _is_postreg;
318 public:
319 Post(Register reg, int o) : PrePost(reg, o) { _idx = NULL; _is_postreg = false; }
320 Post(Register reg, Register idx) : PrePost(reg, 0) { _idx = idx; _is_postreg = true; }
321 Register idx_reg() { return _idx; }
322 bool is_postreg() {return _is_postreg; }
323 };
324
325 namespace ext
326 {
327 enum operation { uxtb, uxth, uxtw, uxtx, sxtb, sxth, sxtw, sxtx };
328 };
329
330 // Addressing modes
331 class Address {
332 public:
333
334 enum mode { no_mode, base_plus_offset, pre, post, post_reg, pcrel,
335 base_plus_offset_reg, literal };
336
337 // Shift and extend for base reg + reg offset addressing
338 class extend {
339 int _option, _shift;
340 ext::operation _op;
341 public:
342 extend() { }
343 extend(int s, int o, ext::operation op) : _option(o), _shift(s), _op(op) { }
344 int option() const{ return _option; }
345 int shift() const { return _shift; }
346 ext::operation op() const { return _op; }
347 };
348 class uxtw : public extend {
349 public:
350 uxtw(int shift = -1): extend(shift, 0b010, ext::uxtw) { }
351 };
352 class lsl : public extend {
353 public:
354 lsl(int shift = -1): extend(shift, 0b011, ext::uxtx) { }
355 };
356 class sxtw : public extend {
357 public:
358 sxtw(int shift = -1): extend(shift, 0b110, ext::sxtw) { }
359 };
360 class sxtx : public extend {
361 public:
362 sxtx(int shift = -1): extend(shift, 0b111, ext::sxtx) { }
363 };
364
365 private:
366 Register _base;
367 Register _index;
368 int64_t _offset;
369 enum mode _mode;
370 extend _ext;
371
372 RelocationHolder _rspec;
373
374 // Typically we use AddressLiterals we want to use their rval
375 // However in some situations we want the lval (effect address) of
376 // the item. We provide a special factory for making those lvals.
377 bool _is_lval;
378
379 // If the target is far we'll need to load the ea of this to a
380 // register to reach it. Otherwise if near we can do PC-relative
381 // addressing.
382 address _target;
383
384 public:
385 Address()
386 : _mode(no_mode) { }
387 Address(Register r)
388 : _base(r), _index(noreg), _offset(0), _mode(base_plus_offset), _target(0) { }
389 Address(Register r, int o)
390 : _base(r), _index(noreg), _offset(o), _mode(base_plus_offset), _target(0) { }
391 Address(Register r, int64_t o)
392 : _base(r), _index(noreg), _offset(o), _mode(base_plus_offset), _target(0) { }
393 Address(Register r, uint64_t o)
394 : _base(r), _index(noreg), _offset(o), _mode(base_plus_offset), _target(0) { }
395 #ifdef ASSERT
396 Address(Register r, ByteSize disp)
397 : _base(r), _index(noreg), _offset(in_bytes(disp)), _mode(base_plus_offset), _target(0) { }
398 #endif
399 Address(Register r, Register r1, extend ext = lsl())
400 : _base(r), _index(r1), _offset(0), _mode(base_plus_offset_reg),
401 _ext(ext), _target(0) { }
402 Address(Pre p)
403 : _base(p.reg()), _offset(p.offset()), _mode(pre) { }
404 Address(Post p)
405 : _base(p.reg()), _index(p.idx_reg()), _offset(p.offset()),
406 _mode(p.is_postreg() ? post_reg : post), _target(0) { }
407 Address(address target, RelocationHolder const& rspec)
408 : _mode(literal),
409 _rspec(rspec),
410 _is_lval(false),
411 _target(target) { }
412 Address(address target, relocInfo::relocType rtype = relocInfo::external_word_type);
413 Address(Register base, RegisterOrConstant index, extend ext = lsl())
414 : _base (base),
415 _offset(0), _ext(ext), _target(0) {
416 if (index.is_register()) {
417 _mode = base_plus_offset_reg;
418 _index = index.as_register();
419 } else {
420 guarantee(ext.option() == ext::uxtx, "should be");
421 assert(index.is_constant(), "should be");
422 _mode = base_plus_offset;
423 _offset = index.as_constant() << ext.shift();
424 }
425 }
426
427 Register base() const {
428 guarantee((_mode == base_plus_offset | _mode == base_plus_offset_reg
429 | _mode == post | _mode == post_reg),
430 "wrong mode");
431 return _base;
432 }
433 int64_t offset() const {
434 return _offset;
435 }
436 Register index() const {
437 return _index;
438 }
439 mode getMode() const {
440 return _mode;
441 }
442 bool uses(Register reg) const { return _base == reg || _index == reg; }
443 address target() const { return _target; }
444 const RelocationHolder& rspec() const { return _rspec; }
445
446 void encode(Instruction_aarch64 *i) const {
447 i->f(0b111, 29, 27);
448 i->srf(_base, 5);
449
450 switch(_mode) {
451 case base_plus_offset:
452 {
453 unsigned size = i->get(31, 30);
454 if (i->get(26, 26) && i->get(23, 23)) {
455 // SIMD Q Type - Size = 128 bits
456 assert(size == 0, "bad size");
457 size = 0b100;
458 }
459 unsigned mask = (1 << size) - 1;
460 if (_offset < 0 || _offset & mask)
461 {
462 i->f(0b00, 25, 24);
463 i->f(0, 21), i->f(0b00, 11, 10);
464 i->sf(_offset, 20, 12);
465 } else {
466 i->f(0b01, 25, 24);
467 i->f(_offset >> size, 21, 10);
468 }
469 }
470 break;
471
472 case base_plus_offset_reg:
473 {
474 i->f(0b00, 25, 24);
475 i->f(1, 21);
476 i->rf(_index, 16);
477 i->f(_ext.option(), 15, 13);
478 unsigned size = i->get(31, 30);
479 if (i->get(26, 26) && i->get(23, 23)) {
480 // SIMD Q Type - Size = 128 bits
481 assert(size == 0, "bad size");
482 size = 0b100;
483 }
484 if (size == 0) // It's a byte
485 i->f(_ext.shift() >= 0, 12);
486 else {
487 if (_ext.shift() > 0)
488 assert(_ext.shift() == (int)size, "bad shift");
489 i->f(_ext.shift() > 0, 12);
490 }
491 i->f(0b10, 11, 10);
492 }
493 break;
494
495 case pre:
496 i->f(0b00, 25, 24);
497 i->f(0, 21), i->f(0b11, 11, 10);
498 i->sf(_offset, 20, 12);
499 break;
500
501 case post:
502 i->f(0b00, 25, 24);
503 i->f(0, 21), i->f(0b01, 11, 10);
504 i->sf(_offset, 20, 12);
505 break;
506
507 default:
508 ShouldNotReachHere();
509 }
510 }
511
512 void encode_pair(Instruction_aarch64 *i) const {
513 switch(_mode) {
514 case base_plus_offset:
515 i->f(0b010, 25, 23);
516 break;
517 case pre:
518 i->f(0b011, 25, 23);
519 break;
520 case post:
521 i->f(0b001, 25, 23);
522 break;
523 default:
524 ShouldNotReachHere();
525 }
526
527 unsigned size; // Operand shift in 32-bit words
528
529 if (i->get(26, 26)) { // float
530 switch(i->get(31, 30)) {
531 case 0b10:
532 size = 2; break;
533 case 0b01:
534 size = 1; break;
535 case 0b00:
536 size = 0; break;
537 default:
538 ShouldNotReachHere();
539 size = 0; // unreachable
540 }
541 } else {
542 size = i->get(31, 31);
543 }
544
545 size = 4 << size;
546 guarantee(_offset % size == 0, "bad offset");
547 i->sf(_offset / size, 21, 15);
548 i->srf(_base, 5);
549 }
550
551 void encode_nontemporal_pair(Instruction_aarch64 *i) const {
552 // Only base + offset is allowed
553 i->f(0b000, 25, 23);
554 unsigned size = i->get(31, 31);
555 size = 4 << size;
556 guarantee(_offset % size == 0, "bad offset");
557 i->sf(_offset / size, 21, 15);
558 i->srf(_base, 5);
559 guarantee(_mode == Address::base_plus_offset,
560 "Bad addressing mode for non-temporal op");
561 }
562
563 void lea(MacroAssembler *, Register) const;
564
565 static bool offset_ok_for_immed(int64_t offset, uint shift);
566 };
567
568 // Convience classes
569 class RuntimeAddress: public Address {
570
571 public:
572
573 RuntimeAddress(address target) : Address(target, relocInfo::runtime_call_type) {}
574
575 };
576
577 class OopAddress: public Address {
578
579 public:
580
581 OopAddress(address target) : Address(target, relocInfo::oop_type){}
582
583 };
584
585 class ExternalAddress: public Address {
586 private:
587 static relocInfo::relocType reloc_for_target(address target) {
588 // Sometimes ExternalAddress is used for values which aren't
589 // exactly addresses, like the card table base.
590 // external_word_type can't be used for values in the first page
591 // so just skip the reloc in that case.
592 return external_word_Relocation::can_be_relocated(target) ? relocInfo::external_word_type : relocInfo::none;
593 }
594
595 public:
596
597 ExternalAddress(address target) : Address(target, reloc_for_target(target)) {}
598
599 };
600
601 class InternalAddress: public Address {
602
603 public:
604
605 InternalAddress(address target) : Address(target, relocInfo::internal_word_type) {}
606 };
607
608 const int FPUStateSizeInWords = FloatRegisterImpl::number_of_registers *
609 FloatRegisterImpl::save_slots_per_register;
610
611 typedef enum {
612 PLDL1KEEP = 0b00000, PLDL1STRM, PLDL2KEEP, PLDL2STRM, PLDL3KEEP, PLDL3STRM,
613 PSTL1KEEP = 0b10000, PSTL1STRM, PSTL2KEEP, PSTL2STRM, PSTL3KEEP, PSTL3STRM,
614 PLIL1KEEP = 0b01000, PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP, PLIL3STRM
615 } prfop;
616
617 class Assembler : public AbstractAssembler {
618
619 #ifndef PRODUCT
620 static const uintptr_t asm_bp;
621
622 void emit_long(jint x) {
623 if ((uintptr_t)pc() == asm_bp)
624 asm volatile ("nop");
625 AbstractAssembler::emit_int32(x);
626 }
627 #else
628 void emit_long(jint x) {
629 AbstractAssembler::emit_int32(x);
630 }
631 #endif
632
633 public:
634
635 enum { instruction_size = 4 };
636
637 //---< calculate length of instruction >---
638 // We just use the values set above.
639 // instruction must start at passed address
640 static unsigned int instr_len(unsigned char *instr) { return instruction_size; }
641
642 //---< longest instructions >---
643 static unsigned int instr_maxlen() { return instruction_size; }
644
645 Address adjust(Register base, int offset, bool preIncrement) {
646 if (preIncrement)
647 return Address(Pre(base, offset));
648 else
649 return Address(Post(base, offset));
650 }
651
652 Address pre(Register base, int offset) {
653 return adjust(base, offset, true);
654 }
655
656 Address post(Register base, int offset) {
657 return adjust(base, offset, false);
658 }
659
660 Address post(Register base, Register idx) {
661 return Address(Post(base, idx));
662 }
663
664 Instruction_aarch64* current;
665
666 void set_current(Instruction_aarch64* i) { current = i; }
667
668 void f(unsigned val, int msb, int lsb) {
669 current->f(val, msb, lsb);
670 }
671 void f(unsigned val, int msb) {
672 current->f(val, msb, msb);
673 }
674 void sf(int64_t val, int msb, int lsb) {
675 current->sf(val, msb, lsb);
676 }
677 void rf(Register reg, int lsb) {
678 current->rf(reg, lsb);
679 }
680 void srf(Register reg, int lsb) {
681 current->srf(reg, lsb);
682 }
683 void zrf(Register reg, int lsb) {
684 current->zrf(reg, lsb);
685 }
686 void rf(FloatRegister reg, int lsb) {
687 current->rf(reg, lsb);
688 }
689 void prf(PRegister reg, int lsb) {
690 current->prf(reg, lsb);
691 }
692 void pgrf(PRegister reg, int lsb) {
693 current->pgrf(reg, lsb);
694 }
695 void fixed(unsigned value, unsigned mask) {
696 current->fixed(value, mask);
697 }
698
699 void emit() {
700 emit_long(current->get_insn());
701 assert_cond(current->get_bits() == 0xffffffff);
702 current = NULL;
703 }
704
705 typedef void (Assembler::* uncond_branch_insn)(address dest);
706 typedef void (Assembler::* compare_and_branch_insn)(Register Rt, address dest);
707 typedef void (Assembler::* test_and_branch_insn)(Register Rt, int bitpos, address dest);
708 typedef void (Assembler::* prefetch_insn)(address target, prfop);
709
710 void wrap_label(Label &L, uncond_branch_insn insn);
711 void wrap_label(Register r, Label &L, compare_and_branch_insn insn);
712 void wrap_label(Register r, int bitpos, Label &L, test_and_branch_insn insn);
713 void wrap_label(Label &L, prfop, prefetch_insn insn);
714
715 // PC-rel. addressing
716
717 void adr(Register Rd, address dest);
718 void _adrp(Register Rd, address dest);
719
720 void adr(Register Rd, const Address &dest);
721 void _adrp(Register Rd, const Address &dest);
722
723 void adr(Register Rd, Label &L) {
724 wrap_label(Rd, L, &Assembler::Assembler::adr);
725 }
726 void _adrp(Register Rd, Label &L) {
727 wrap_label(Rd, L, &Assembler::_adrp);
728 }
729
730 void adrp(Register Rd, const Address &dest, uint64_t &offset);
731
732 #undef INSN
733
734 void add_sub_immediate(Register Rd, Register Rn, unsigned uimm, int op,
735 int negated_op);
736
737 // Add/subtract (immediate)
738 #define INSN(NAME, decode, negated) \
739 void NAME(Register Rd, Register Rn, unsigned imm, unsigned shift) { \
740 starti; \
741 f(decode, 31, 29), f(0b10001, 28, 24), f(shift, 23, 22), f(imm, 21, 10); \
742 zrf(Rd, 0), srf(Rn, 5); \
743 } \
744 \
745 void NAME(Register Rd, Register Rn, unsigned imm) { \
746 starti; \
747 add_sub_immediate(Rd, Rn, imm, decode, negated); \
748 }
749
750 INSN(addsw, 0b001, 0b011);
751 INSN(subsw, 0b011, 0b001);
752 INSN(adds, 0b101, 0b111);
753 INSN(subs, 0b111, 0b101);
754
755 #undef INSN
756
757 #define INSN(NAME, decode, negated) \
758 void NAME(Register Rd, Register Rn, unsigned imm) { \
759 starti; \
760 add_sub_immediate(Rd, Rn, imm, decode, negated); \
761 }
762
763 INSN(addw, 0b000, 0b010);
764 INSN(subw, 0b010, 0b000);
765 INSN(add, 0b100, 0b110);
766 INSN(sub, 0b110, 0b100);
767
768 #undef INSN
769
770 // Logical (immediate)
771 #define INSN(NAME, decode, is32) \
772 void NAME(Register Rd, Register Rn, uint64_t imm) { \
773 starti; \
774 uint32_t val = encode_logical_immediate(is32, imm); \
775 f(decode, 31, 29), f(0b100100, 28, 23), f(val, 22, 10); \
776 srf(Rd, 0), zrf(Rn, 5); \
777 }
778
779 INSN(andw, 0b000, true);
780 INSN(orrw, 0b001, true);
781 INSN(eorw, 0b010, true);
782 INSN(andr, 0b100, false);
783 INSN(orr, 0b101, false);
784 INSN(eor, 0b110, false);
785
786 #undef INSN
787
788 #define INSN(NAME, decode, is32) \
789 void NAME(Register Rd, Register Rn, uint64_t imm) { \
790 starti; \
791 uint32_t val = encode_logical_immediate(is32, imm); \
792 f(decode, 31, 29), f(0b100100, 28, 23), f(val, 22, 10); \
793 zrf(Rd, 0), zrf(Rn, 5); \
794 }
795
796 INSN(ands, 0b111, false);
797 INSN(andsw, 0b011, true);
798
799 #undef INSN
800
801 // Move wide (immediate)
802 #define INSN(NAME, opcode) \
803 void NAME(Register Rd, unsigned imm, unsigned shift = 0) { \
804 assert_cond((shift/16)*16 == shift); \
805 starti; \
806 f(opcode, 31, 29), f(0b100101, 28, 23), f(shift/16, 22, 21), \
807 f(imm, 20, 5); \
808 rf(Rd, 0); \
809 }
810
811 INSN(movnw, 0b000);
812 INSN(movzw, 0b010);
813 INSN(movkw, 0b011);
814 INSN(movn, 0b100);
815 INSN(movz, 0b110);
816 INSN(movk, 0b111);
817
818 #undef INSN
819
820 // Bitfield
821 #define INSN(NAME, opcode, size) \
822 void NAME(Register Rd, Register Rn, unsigned immr, unsigned imms) { \
823 starti; \
824 guarantee(size == 1 || (immr < 32 && imms < 32), "incorrect immr/imms");\
825 f(opcode, 31, 22), f(immr, 21, 16), f(imms, 15, 10); \
826 zrf(Rn, 5), rf(Rd, 0); \
827 }
828
829 INSN(sbfmw, 0b0001001100, 0);
830 INSN(bfmw, 0b0011001100, 0);
831 INSN(ubfmw, 0b0101001100, 0);
832 INSN(sbfm, 0b1001001101, 1);
833 INSN(bfm, 0b1011001101, 1);
834 INSN(ubfm, 0b1101001101, 1);
835
836 #undef INSN
837
838 // Extract
839 #define INSN(NAME, opcode, size) \
840 void NAME(Register Rd, Register Rn, Register Rm, unsigned imms) { \
841 starti; \
842 guarantee(size == 1 || imms < 32, "incorrect imms"); \
843 f(opcode, 31, 21), f(imms, 15, 10); \
844 zrf(Rm, 16), zrf(Rn, 5), zrf(Rd, 0); \
845 }
846
847 INSN(extrw, 0b00010011100, 0);
848 INSN(extr, 0b10010011110, 1);
849
850 #undef INSN
851
852 // The maximum range of a branch is fixed for the AArch64
853 // architecture. In debug mode we shrink it in order to test
854 // trampolines, but not so small that branches in the interpreter
855 // are out of range.
856 static const uint64_t branch_range = NOT_DEBUG(128 * M) DEBUG_ONLY(2 * M);
857
858 static bool reachable_from_branch_at(address branch, address target) {
859 return uabs(target - branch) < branch_range;
860 }
861
862 // Unconditional branch (immediate)
863 #define INSN(NAME, opcode) \
864 void NAME(address dest) { \
865 starti; \
866 int64_t offset = (dest - pc()) >> 2; \
867 DEBUG_ONLY(assert(reachable_from_branch_at(pc(), dest), "debug only")); \
868 f(opcode, 31), f(0b00101, 30, 26), sf(offset, 25, 0); \
869 } \
870 void NAME(Label &L) { \
871 wrap_label(L, &Assembler::NAME); \
872 } \
873 void NAME(const Address &dest);
874
875 INSN(b, 0);
876 INSN(bl, 1);
877
878 #undef INSN
879
880 // Compare & branch (immediate)
881 #define INSN(NAME, opcode) \
882 void NAME(Register Rt, address dest) { \
883 int64_t offset = (dest - pc()) >> 2; \
884 starti; \
885 f(opcode, 31, 24), sf(offset, 23, 5), rf(Rt, 0); \
886 } \
887 void NAME(Register Rt, Label &L) { \
888 wrap_label(Rt, L, &Assembler::NAME); \
889 }
890
891 INSN(cbzw, 0b00110100);
892 INSN(cbnzw, 0b00110101);
893 INSN(cbz, 0b10110100);
894 INSN(cbnz, 0b10110101);
895
896 #undef INSN
897
898 // Test & branch (immediate)
899 #define INSN(NAME, opcode) \
900 void NAME(Register Rt, int bitpos, address dest) { \
901 int64_t offset = (dest - pc()) >> 2; \
902 int b5 = bitpos >> 5; \
903 bitpos &= 0x1f; \
904 starti; \
905 f(b5, 31), f(opcode, 30, 24), f(bitpos, 23, 19), sf(offset, 18, 5); \
906 rf(Rt, 0); \
907 } \
908 void NAME(Register Rt, int bitpos, Label &L) { \
909 wrap_label(Rt, bitpos, L, &Assembler::NAME); \
910 }
911
912 INSN(tbz, 0b0110110);
913 INSN(tbnz, 0b0110111);
914
915 #undef INSN
916
917 // Conditional branch (immediate)
918 enum Condition
919 {EQ, NE, HS, CS=HS, LO, CC=LO, MI, PL, VS, VC, HI, LS, GE, LT, GT, LE, AL, NV};
920
921 void br(Condition cond, address dest) {
922 int64_t offset = (dest - pc()) >> 2;
923 starti;
924 f(0b0101010, 31, 25), f(0, 24), sf(offset, 23, 5), f(0, 4), f(cond, 3, 0);
925 }
926
927 #define INSN(NAME, cond) \
928 void NAME(address dest) { \
929 br(cond, dest); \
930 }
931
932 INSN(beq, EQ);
933 INSN(bne, NE);
934 INSN(bhs, HS);
935 INSN(bcs, CS);
936 INSN(blo, LO);
937 INSN(bcc, CC);
938 INSN(bmi, MI);
939 INSN(bpl, PL);
940 INSN(bvs, VS);
941 INSN(bvc, VC);
942 INSN(bhi, HI);
943 INSN(bls, LS);
944 INSN(bge, GE);
945 INSN(blt, LT);
946 INSN(bgt, GT);
947 INSN(ble, LE);
948 INSN(bal, AL);
949 INSN(bnv, NV);
950
951 void br(Condition cc, Label &L);
952
953 #undef INSN
954
955 // Exception generation
956 void generate_exception(int opc, int op2, int LL, unsigned imm) {
957 starti;
958 f(0b11010100, 31, 24);
959 f(opc, 23, 21), f(imm, 20, 5), f(op2, 4, 2), f(LL, 1, 0);
960 }
961
962 #define INSN(NAME, opc, op2, LL) \
963 void NAME(unsigned imm) { \
964 generate_exception(opc, op2, LL, imm); \
965 }
966
967 INSN(svc, 0b000, 0, 0b01);
968 INSN(hvc, 0b000, 0, 0b10);
969 INSN(smc, 0b000, 0, 0b11);
970 INSN(brk, 0b001, 0, 0b00);
971 INSN(hlt, 0b010, 0, 0b00);
972 INSN(dcps1, 0b101, 0, 0b01);
973 INSN(dcps2, 0b101, 0, 0b10);
974 INSN(dcps3, 0b101, 0, 0b11);
975
976 #undef INSN
977
978 // System
979 void system(int op0, int op1, int CRn, int CRm, int op2,
980 Register rt = dummy_reg)
981 {
982 starti;
983 f(0b11010101000, 31, 21);
984 f(op0, 20, 19);
985 f(op1, 18, 16);
986 f(CRn, 15, 12);
987 f(CRm, 11, 8);
988 f(op2, 7, 5);
989 rf(rt, 0);
990 }
991
992 void hint(int imm) {
993 system(0b00, 0b011, 0b0010, 0b0000, imm);
994 }
995
996 void nop() {
997 hint(0);
998 }
999
1000 void yield() {
1001 hint(1);
1002 }
1003
1004 void wfe() {
1005 hint(2);
1006 }
1007
1008 void wfi() {
1009 hint(3);
1010 }
1011
1012 void sev() {
1013 hint(4);
1014 }
1015
1016 void sevl() {
1017 hint(5);
1018 }
1019
1020 // we only provide mrs and msr for the special purpose system
1021 // registers where op1 (instr[20:19]) == 11 and, (currently) only
1022 // use it for FPSR n.b msr has L (instr[21]) == 0 mrs has L == 1
1023
1024 void msr(int op1, int CRn, int CRm, int op2, Register rt) {
1025 starti;
1026 f(0b1101010100011, 31, 19);
1027 f(op1, 18, 16);
1028 f(CRn, 15, 12);
1029 f(CRm, 11, 8);
1030 f(op2, 7, 5);
1031 // writing zr is ok
1032 zrf(rt, 0);
1033 }
1034
1035 void mrs(int op1, int CRn, int CRm, int op2, Register rt) {
1036 starti;
1037 f(0b1101010100111, 31, 19);
1038 f(op1, 18, 16);
1039 f(CRn, 15, 12);
1040 f(CRm, 11, 8);
1041 f(op2, 7, 5);
1042 // reading to zr is a mistake
1043 rf(rt, 0);
1044 }
1045
1046 enum barrier {OSHLD = 0b0001, OSHST, OSH, NSHLD=0b0101, NSHST, NSH,
1047 ISHLD = 0b1001, ISHST, ISH, LD=0b1101, ST, SY};
1048
1049 void dsb(barrier imm) {
1050 system(0b00, 0b011, 0b00011, imm, 0b100);
1051 }
1052
1053 void dmb(barrier imm) {
1054 system(0b00, 0b011, 0b00011, imm, 0b101);
1055 }
1056
1057 void isb() {
1058 system(0b00, 0b011, 0b00011, SY, 0b110);
1059 }
1060
1061 void sys(int op1, int CRn, int CRm, int op2,
1062 Register rt = (Register)0b11111) {
1063 system(0b01, op1, CRn, CRm, op2, rt);
1064 }
1065
1066 // Only implement operations accessible from EL0 or higher, i.e.,
1067 // op1 CRn CRm op2
1068 // IC IVAU 3 7 5 1
1069 // DC CVAC 3 7 10 1
1070 // DC CVAP 3 7 12 1
1071 // DC CVAU 3 7 11 1
1072 // DC CIVAC 3 7 14 1
1073 // DC ZVA 3 7 4 1
1074 // So only deal with the CRm field.
1075 enum icache_maintenance {IVAU = 0b0101};
1076 enum dcache_maintenance {CVAC = 0b1010, CVAP = 0b1100, CVAU = 0b1011, CIVAC = 0b1110, ZVA = 0b100};
1077
1078 void dc(dcache_maintenance cm, Register Rt) {
1079 sys(0b011, 0b0111, cm, 0b001, Rt);
1080 }
1081
1082 void ic(icache_maintenance cm, Register Rt) {
1083 sys(0b011, 0b0111, cm, 0b001, Rt);
1084 }
1085
1086 // A more convenient access to dmb for our purposes
1087 enum Membar_mask_bits {
1088 // We can use ISH for a barrier because the ARM ARM says "This
1089 // architecture assumes that all Processing Elements that use the
1090 // same operating system or hypervisor are in the same Inner
1091 // Shareable shareability domain."
1092 StoreStore = ISHST,
1093 LoadStore = ISHLD,
1094 LoadLoad = ISHLD,
1095 StoreLoad = ISH,
1096 AnyAny = ISH
1097 };
1098
1099 void membar(Membar_mask_bits order_constraint) {
1100 dmb(Assembler::barrier(order_constraint));
1101 }
1102
1103 // Unconditional branch (register)
1104 void branch_reg(Register R, int opc) {
1105 starti;
1106 f(0b1101011, 31, 25);
1107 f(opc, 24, 21);
1108 f(0b11111000000, 20, 10);
1109 rf(R, 5);
1110 f(0b00000, 4, 0);
1111 }
1112
1113 #define INSN(NAME, opc) \
1114 void NAME(Register R) { \
1115 branch_reg(R, opc); \
1116 }
1117
1118 INSN(br, 0b0000);
1119 INSN(blr, 0b0001);
1120 INSN(ret, 0b0010);
1121
1122 void ret(void *p); // This forces a compile-time error for ret(0)
1123
1124 #undef INSN
1125
1126 #define INSN(NAME, opc) \
1127 void NAME() { \
1128 branch_reg(dummy_reg, opc); \
1129 }
1130
1131 INSN(eret, 0b0100);
1132 INSN(drps, 0b0101);
1133
1134 #undef INSN
1135
1136 // Load/store exclusive
1137 enum operand_size { byte, halfword, word, xword };
1138
1139 void load_store_exclusive(Register Rs, Register Rt1, Register Rt2,
1140 Register Rn, enum operand_size sz, int op, bool ordered) {
1141 starti;
1142 f(sz, 31, 30), f(0b001000, 29, 24), f(op, 23, 21);
1143 rf(Rs, 16), f(ordered, 15), zrf(Rt2, 10), srf(Rn, 5), zrf(Rt1, 0);
1144 }
1145
1146 void load_exclusive(Register dst, Register addr,
1147 enum operand_size sz, bool ordered) {
1148 load_store_exclusive(dummy_reg, dst, dummy_reg, addr,
1149 sz, 0b010, ordered);
1150 }
1151
1152 void store_exclusive(Register status, Register new_val, Register addr,
1153 enum operand_size sz, bool ordered) {
1154 load_store_exclusive(status, new_val, dummy_reg, addr,
1155 sz, 0b000, ordered);
1156 }
1157
1158 #define INSN4(NAME, sz, op, o0) /* Four registers */ \
1159 void NAME(Register Rs, Register Rt1, Register Rt2, Register Rn) { \
1160 guarantee(Rs != Rn && Rs != Rt1 && Rs != Rt2, "unpredictable instruction"); \
1161 load_store_exclusive(Rs, Rt1, Rt2, Rn, sz, op, o0); \
1162 }
1163
1164 #define INSN3(NAME, sz, op, o0) /* Three registers */ \
1165 void NAME(Register Rs, Register Rt, Register Rn) { \
1166 guarantee(Rs != Rn && Rs != Rt, "unpredictable instruction"); \
1167 load_store_exclusive(Rs, Rt, dummy_reg, Rn, sz, op, o0); \
1168 }
1169
1170 #define INSN2(NAME, sz, op, o0) /* Two registers */ \
1171 void NAME(Register Rt, Register Rn) { \
1172 load_store_exclusive(dummy_reg, Rt, dummy_reg, \
1173 Rn, sz, op, o0); \
1174 }
1175
1176 #define INSN_FOO(NAME, sz, op, o0) /* Three registers, encoded differently */ \
1177 void NAME(Register Rt1, Register Rt2, Register Rn) { \
1178 guarantee(Rt1 != Rt2, "unpredictable instruction"); \
1179 load_store_exclusive(dummy_reg, Rt1, Rt2, Rn, sz, op, o0); \
1180 }
1181
1182 // bytes
1183 INSN3(stxrb, byte, 0b000, 0);
1184 INSN3(stlxrb, byte, 0b000, 1);
1185 INSN2(ldxrb, byte, 0b010, 0);
1186 INSN2(ldaxrb, byte, 0b010, 1);
1187 INSN2(stlrb, byte, 0b100, 1);
1188 INSN2(ldarb, byte, 0b110, 1);
1189
1190 // halfwords
1191 INSN3(stxrh, halfword, 0b000, 0);
1192 INSN3(stlxrh, halfword, 0b000, 1);
1193 INSN2(ldxrh, halfword, 0b010, 0);
1194 INSN2(ldaxrh, halfword, 0b010, 1);
1195 INSN2(stlrh, halfword, 0b100, 1);
1196 INSN2(ldarh, halfword, 0b110, 1);
1197
1198 // words
1199 INSN3(stxrw, word, 0b000, 0);
1200 INSN3(stlxrw, word, 0b000, 1);
1201 INSN4(stxpw, word, 0b001, 0);
1202 INSN4(stlxpw, word, 0b001, 1);
1203 INSN2(ldxrw, word, 0b010, 0);
1204 INSN2(ldaxrw, word, 0b010, 1);
1205 INSN_FOO(ldxpw, word, 0b011, 0);
1206 INSN_FOO(ldaxpw, word, 0b011, 1);
1207 INSN2(stlrw, word, 0b100, 1);
1208 INSN2(ldarw, word, 0b110, 1);
1209
1210 // xwords
1211 INSN3(stxr, xword, 0b000, 0);
1212 INSN3(stlxr, xword, 0b000, 1);
1213 INSN4(stxp, xword, 0b001, 0);
1214 INSN4(stlxp, xword, 0b001, 1);
1215 INSN2(ldxr, xword, 0b010, 0);
1216 INSN2(ldaxr, xword, 0b010, 1);
1217 INSN_FOO(ldxp, xword, 0b011, 0);
1218 INSN_FOO(ldaxp, xword, 0b011, 1);
1219 INSN2(stlr, xword, 0b100, 1);
1220 INSN2(ldar, xword, 0b110, 1);
1221
1222 #undef INSN2
1223 #undef INSN3
1224 #undef INSN4
1225 #undef INSN_FOO
1226
1227 // 8.1 Compare and swap extensions
1228 void lse_cas(Register Rs, Register Rt, Register Rn,
1229 enum operand_size sz, bool a, bool r, bool not_pair) {
1230 starti;
1231 if (! not_pair) { // Pair
1232 assert(sz == word || sz == xword, "invalid size");
1233 /* The size bit is in bit 30, not 31 */
1234 sz = (operand_size)(sz == word ? 0b00:0b01);
1235 }
1236 f(sz, 31, 30), f(0b001000, 29, 24), f(not_pair ? 1 : 0, 23), f(a, 22), f(1, 21);
1237 zrf(Rs, 16), f(r, 15), f(0b11111, 14, 10), srf(Rn, 5), zrf(Rt, 0);
1238 }
1239
1240 // CAS
1241 #define INSN(NAME, a, r) \
1242 void NAME(operand_size sz, Register Rs, Register Rt, Register Rn) { \
1243 assert(Rs != Rn && Rs != Rt, "unpredictable instruction"); \
1244 lse_cas(Rs, Rt, Rn, sz, a, r, true); \
1245 }
1246 INSN(cas, false, false)
1247 INSN(casa, true, false)
1248 INSN(casl, false, true)
1249 INSN(casal, true, true)
1250 #undef INSN
1251
1252 // CASP
1253 #define INSN(NAME, a, r) \
1254 void NAME(operand_size sz, Register Rs, Register Rs1, \
1255 Register Rt, Register Rt1, Register Rn) { \
1256 assert((Rs->encoding() & 1) == 0 && (Rt->encoding() & 1) == 0 && \
1257 Rs->successor() == Rs1 && Rt->successor() == Rt1 && \
1258 Rs != Rn && Rs1 != Rn && Rs != Rt, "invalid registers"); \
1259 lse_cas(Rs, Rt, Rn, sz, a, r, false); \
1260 }
1261 INSN(casp, false, false)
1262 INSN(caspa, true, false)
1263 INSN(caspl, false, true)
1264 INSN(caspal, true, true)
1265 #undef INSN
1266
1267 // 8.1 Atomic operations
1268 void lse_atomic(Register Rs, Register Rt, Register Rn,
1269 enum operand_size sz, int op1, int op2, bool a, bool r) {
1270 starti;
1271 f(sz, 31, 30), f(0b111000, 29, 24), f(a, 23), f(r, 22), f(1, 21);
1272 zrf(Rs, 16), f(op1, 15), f(op2, 14, 12), f(0, 11, 10), srf(Rn, 5), zrf(Rt, 0);
1273 }
1274
1275 #define INSN(NAME, NAME_A, NAME_L, NAME_AL, op1, op2) \
1276 void NAME(operand_size sz, Register Rs, Register Rt, Register Rn) { \
1277 lse_atomic(Rs, Rt, Rn, sz, op1, op2, false, false); \
1278 } \
1279 void NAME_A(operand_size sz, Register Rs, Register Rt, Register Rn) { \
1280 lse_atomic(Rs, Rt, Rn, sz, op1, op2, true, false); \
1281 } \
1282 void NAME_L(operand_size sz, Register Rs, Register Rt, Register Rn) { \
1283 lse_atomic(Rs, Rt, Rn, sz, op1, op2, false, true); \
1284 } \
1285 void NAME_AL(operand_size sz, Register Rs, Register Rt, Register Rn) {\
1286 lse_atomic(Rs, Rt, Rn, sz, op1, op2, true, true); \
1287 }
1288 INSN(ldadd, ldadda, ldaddl, ldaddal, 0, 0b000);
1289 INSN(ldbic, ldbica, ldbicl, ldbical, 0, 0b001);
1290 INSN(ldeor, ldeora, ldeorl, ldeoral, 0, 0b010);
1291 INSN(ldorr, ldorra, ldorrl, ldorral, 0, 0b011);
1292 INSN(ldsmax, ldsmaxa, ldsmaxl, ldsmaxal, 0, 0b100);
1293 INSN(ldsmin, ldsmina, ldsminl, ldsminal, 0, 0b101);
1294 INSN(ldumax, ldumaxa, ldumaxl, ldumaxal, 0, 0b110);
1295 INSN(ldumin, ldumina, lduminl, lduminal, 0, 0b111);
1296 INSN(swp, swpa, swpl, swpal, 1, 0b000);
1297 #undef INSN
1298
1299 // Load register (literal)
1300 #define INSN(NAME, opc, V) \
1301 void NAME(Register Rt, address dest) { \
1302 int64_t offset = (dest - pc()) >> 2; \
1303 starti; \
1304 f(opc, 31, 30), f(0b011, 29, 27), f(V, 26), f(0b00, 25, 24), \
1305 sf(offset, 23, 5); \
1306 rf(Rt, 0); \
1307 } \
1308 void NAME(Register Rt, address dest, relocInfo::relocType rtype) { \
1309 InstructionMark im(this); \
1310 guarantee(rtype == relocInfo::internal_word_type, \
1311 "only internal_word_type relocs make sense here"); \
1312 code_section()->relocate(inst_mark(), InternalAddress(dest).rspec()); \
1313 NAME(Rt, dest); \
1314 } \
1315 void NAME(Register Rt, Label &L) { \
1316 wrap_label(Rt, L, &Assembler::NAME); \
1317 }
1318
1319 INSN(ldrw, 0b00, 0);
1320 INSN(ldr, 0b01, 0);
1321 INSN(ldrsw, 0b10, 0);
1322
1323 #undef INSN
1324
1325 #define INSN(NAME, opc, V) \
1326 void NAME(FloatRegister Rt, address dest) { \
1327 int64_t offset = (dest - pc()) >> 2; \
1328 starti; \
1329 f(opc, 31, 30), f(0b011, 29, 27), f(V, 26), f(0b00, 25, 24), \
1330 sf(offset, 23, 5); \
1331 rf((Register)Rt, 0); \
1332 }
1333
1334 INSN(ldrs, 0b00, 1);
1335 INSN(ldrd, 0b01, 1);
1336 INSN(ldrq, 0b10, 1);
1337
1338 #undef INSN
1339
1340 #define INSN(NAME, opc, V) \
1341 void NAME(address dest, prfop op = PLDL1KEEP) { \
1342 int64_t offset = (dest - pc()) >> 2; \
1343 starti; \
1344 f(opc, 31, 30), f(0b011, 29, 27), f(V, 26), f(0b00, 25, 24), \
1345 sf(offset, 23, 5); \
1346 f(op, 4, 0); \
1347 } \
1348 void NAME(Label &L, prfop op = PLDL1KEEP) { \
1349 wrap_label(L, op, &Assembler::NAME); \
1350 }
1351
1352 INSN(prfm, 0b11, 0);
1353
1354 #undef INSN
1355
1356 // Load/store
1357 void ld_st1(int opc, int p1, int V, int L,
1358 Register Rt1, Register Rt2, Address adr, bool no_allocate) {
1359 starti;
1360 f(opc, 31, 30), f(p1, 29, 27), f(V, 26), f(L, 22);
1361 zrf(Rt2, 10), zrf(Rt1, 0);
1362 if (no_allocate) {
1363 adr.encode_nontemporal_pair(current);
1364 } else {
1365 adr.encode_pair(current);
1366 }
1367 }
1368
1369 // Load/store register pair (offset)
1370 #define INSN(NAME, size, p1, V, L, no_allocate) \
1371 void NAME(Register Rt1, Register Rt2, Address adr) { \
1372 ld_st1(size, p1, V, L, Rt1, Rt2, adr, no_allocate); \
1373 }
1374
1375 INSN(stpw, 0b00, 0b101, 0, 0, false);
1376 INSN(ldpw, 0b00, 0b101, 0, 1, false);
1377 INSN(ldpsw, 0b01, 0b101, 0, 1, false);
1378 INSN(stp, 0b10, 0b101, 0, 0, false);
1379 INSN(ldp, 0b10, 0b101, 0, 1, false);
1380
1381 // Load/store no-allocate pair (offset)
1382 INSN(stnpw, 0b00, 0b101, 0, 0, true);
1383 INSN(ldnpw, 0b00, 0b101, 0, 1, true);
1384 INSN(stnp, 0b10, 0b101, 0, 0, true);
1385 INSN(ldnp, 0b10, 0b101, 0, 1, true);
1386
1387 #undef INSN
1388
1389 #define INSN(NAME, size, p1, V, L, no_allocate) \
1390 void NAME(FloatRegister Rt1, FloatRegister Rt2, Address adr) { \
1391 ld_st1(size, p1, V, L, (Register)Rt1, (Register)Rt2, adr, no_allocate); \
1392 }
1393
1394 INSN(stps, 0b00, 0b101, 1, 0, false);
1395 INSN(ldps, 0b00, 0b101, 1, 1, false);
1396 INSN(stpd, 0b01, 0b101, 1, 0, false);
1397 INSN(ldpd, 0b01, 0b101, 1, 1, false);
1398 INSN(stpq, 0b10, 0b101, 1, 0, false);
1399 INSN(ldpq, 0b10, 0b101, 1, 1, false);
1400
1401 #undef INSN
1402
1403 // Load/store register (all modes)
1404 void ld_st2(Register Rt, const Address &adr, int size, int op, int V = 0) {
1405 starti;
1406
1407 f(V, 26); // general reg?
1408 zrf(Rt, 0);
1409
1410 // Encoding for literal loads is done here (rather than pushed
1411 // down into Address::encode) because the encoding of this
1412 // instruction is too different from all of the other forms to
1413 // make it worth sharing.
1414 if (adr.getMode() == Address::literal) {
1415 assert(size == 0b10 || size == 0b11, "bad operand size in ldr");
1416 assert(op == 0b01, "literal form can only be used with loads");
1417 f(size & 0b01, 31, 30), f(0b011, 29, 27), f(0b00, 25, 24);
1418 int64_t offset = (adr.target() - pc()) >> 2;
1419 sf(offset, 23, 5);
1420 code_section()->relocate(pc(), adr.rspec());
1421 return;
1422 }
1423
1424 f(size, 31, 30);
1425 f(op, 23, 22); // str
1426 adr.encode(current);
1427 }
1428
1429 #define INSN(NAME, size, op) \
1430 void NAME(Register Rt, const Address &adr) { \
1431 ld_st2(Rt, adr, size, op); \
1432 } \
1433
1434 INSN(str, 0b11, 0b00);
1435 INSN(strw, 0b10, 0b00);
1436 INSN(strb, 0b00, 0b00);
1437 INSN(strh, 0b01, 0b00);
1438
1439 INSN(ldr, 0b11, 0b01);
1440 INSN(ldrw, 0b10, 0b01);
1441 INSN(ldrb, 0b00, 0b01);
1442 INSN(ldrh, 0b01, 0b01);
1443
1444 INSN(ldrsb, 0b00, 0b10);
1445 INSN(ldrsbw, 0b00, 0b11);
1446 INSN(ldrsh, 0b01, 0b10);
1447 INSN(ldrshw, 0b01, 0b11);
1448 INSN(ldrsw, 0b10, 0b10);
1449
1450 #undef INSN
1451
1452 #define INSN(NAME, size, op) \
1453 void NAME(const Address &adr, prfop pfop = PLDL1KEEP) { \
1454 ld_st2((Register)pfop, adr, size, op); \
1455 }
1456
1457 INSN(prfm, 0b11, 0b10); // FIXME: PRFM should not be used with
1458 // writeback modes, but the assembler
1459 // doesn't enfore that.
1460
1461 #undef INSN
1462
1463 #define INSN(NAME, size, op) \
1464 void NAME(FloatRegister Rt, const Address &adr) { \
1465 ld_st2((Register)Rt, adr, size, op, 1); \
1466 }
1467
1468 INSN(strd, 0b11, 0b00);
1469 INSN(strs, 0b10, 0b00);
1470 INSN(ldrd, 0b11, 0b01);
1471 INSN(ldrs, 0b10, 0b01);
1472 INSN(strq, 0b00, 0b10);
1473 INSN(ldrq, 0x00, 0b11);
1474
1475 #undef INSN
1476
1477 enum shift_kind { LSL, LSR, ASR, ROR };
1478
1479 void op_shifted_reg(unsigned decode,
1480 enum shift_kind kind, unsigned shift,
1481 unsigned size, unsigned op) {
1482 f(size, 31);
1483 f(op, 30, 29);
1484 f(decode, 28, 24);
1485 f(shift, 15, 10);
1486 f(kind, 23, 22);
1487 }
1488
1489 // Logical (shifted register)
1490 #define INSN(NAME, size, op, N) \
1491 void NAME(Register Rd, Register Rn, Register Rm, \
1492 enum shift_kind kind = LSL, unsigned shift = 0) { \
1493 starti; \
1494 guarantee(size == 1 || shift < 32, "incorrect shift"); \
1495 f(N, 21); \
1496 zrf(Rm, 16), zrf(Rn, 5), zrf(Rd, 0); \
1497 op_shifted_reg(0b01010, kind, shift, size, op); \
1498 }
1499
1500 INSN(andr, 1, 0b00, 0);
1501 INSN(orr, 1, 0b01, 0);
1502 INSN(eor, 1, 0b10, 0);
1503 INSN(ands, 1, 0b11, 0);
1504 INSN(andw, 0, 0b00, 0);
1505 INSN(orrw, 0, 0b01, 0);
1506 INSN(eorw, 0, 0b10, 0);
1507 INSN(andsw, 0, 0b11, 0);
1508
1509 #undef INSN
1510
1511 #define INSN(NAME, size, op, N) \
1512 void NAME(Register Rd, Register Rn, Register Rm, \
1513 enum shift_kind kind = LSL, unsigned shift = 0) { \
1514 starti; \
1515 f(N, 21); \
1516 zrf(Rm, 16), zrf(Rn, 5), zrf(Rd, 0); \
1517 op_shifted_reg(0b01010, kind, shift, size, op); \
1518 } \
1519 \
1520 /* These instructions have no immediate form. Provide an overload so \
1521 that if anyone does try to use an immediate operand -- this has \
1522 happened! -- we'll get a compile-time error. */ \
1523 void NAME(Register Rd, Register Rn, unsigned imm, \
1524 enum shift_kind kind = LSL, unsigned shift = 0) { \
1525 assert(false, " can't be used with immediate operand"); \
1526 }
1527
1528 INSN(bic, 1, 0b00, 1);
1529 INSN(orn, 1, 0b01, 1);
1530 INSN(eon, 1, 0b10, 1);
1531 INSN(bics, 1, 0b11, 1);
1532 INSN(bicw, 0, 0b00, 1);
1533 INSN(ornw, 0, 0b01, 1);
1534 INSN(eonw, 0, 0b10, 1);
1535 INSN(bicsw, 0, 0b11, 1);
1536
1537 #undef INSN
1538
1539 // Aliases for short forms of orn
1540 void mvn(Register Rd, Register Rm,
1541 enum shift_kind kind = LSL, unsigned shift = 0) {
1542 orn(Rd, zr, Rm, kind, shift);
1543 }
1544
1545 void mvnw(Register Rd, Register Rm,
1546 enum shift_kind kind = LSL, unsigned shift = 0) {
1547 ornw(Rd, zr, Rm, kind, shift);
1548 }
1549
1550 // Add/subtract (shifted register)
1551 #define INSN(NAME, size, op) \
1552 void NAME(Register Rd, Register Rn, Register Rm, \
1553 enum shift_kind kind, unsigned shift = 0) { \
1554 starti; \
1555 f(0, 21); \
1556 assert_cond(kind != ROR); \
1557 guarantee(size == 1 || shift < 32, "incorrect shift");\
1558 zrf(Rd, 0), zrf(Rn, 5), zrf(Rm, 16); \
1559 op_shifted_reg(0b01011, kind, shift, size, op); \
1560 }
1561
1562 INSN(add, 1, 0b000);
1563 INSN(sub, 1, 0b10);
1564 INSN(addw, 0, 0b000);
1565 INSN(subw, 0, 0b10);
1566
1567 INSN(adds, 1, 0b001);
1568 INSN(subs, 1, 0b11);
1569 INSN(addsw, 0, 0b001);
1570 INSN(subsw, 0, 0b11);
1571
1572 #undef INSN
1573
1574 // Add/subtract (extended register)
1575 #define INSN(NAME, op) \
1576 void NAME(Register Rd, Register Rn, Register Rm, \
1577 ext::operation option, int amount = 0) { \
1578 starti; \
1579 zrf(Rm, 16), srf(Rn, 5), srf(Rd, 0); \
1580 add_sub_extended_reg(op, 0b01011, Rd, Rn, Rm, 0b00, option, amount); \
1581 }
1582
1583 void add_sub_extended_reg(unsigned op, unsigned decode,
1584 Register Rd, Register Rn, Register Rm,
1585 unsigned opt, ext::operation option, unsigned imm) {
1586 guarantee(imm <= 4, "shift amount must be <= 4");
1587 f(op, 31, 29), f(decode, 28, 24), f(opt, 23, 22), f(1, 21);
1588 f(option, 15, 13), f(imm, 12, 10);
1589 }
1590
1591 INSN(addw, 0b000);
1592 INSN(subw, 0b010);
1593 INSN(add, 0b100);
1594 INSN(sub, 0b110);
1595
1596 #undef INSN
1597
1598 #define INSN(NAME, op) \
1599 void NAME(Register Rd, Register Rn, Register Rm, \
1600 ext::operation option, int amount = 0) { \
1601 starti; \
1602 zrf(Rm, 16), srf(Rn, 5), zrf(Rd, 0); \
1603 add_sub_extended_reg(op, 0b01011, Rd, Rn, Rm, 0b00, option, amount); \
1604 }
1605
1606 INSN(addsw, 0b001);
1607 INSN(subsw, 0b011);
1608 INSN(adds, 0b101);
1609 INSN(subs, 0b111);
1610
1611 #undef INSN
1612
1613 // Aliases for short forms of add and sub
1614 #define INSN(NAME) \
1615 void NAME(Register Rd, Register Rn, Register Rm) { \
1616 if (Rd == sp || Rn == sp) \
1617 NAME(Rd, Rn, Rm, ext::uxtx); \
1618 else \
1619 NAME(Rd, Rn, Rm, LSL); \
1620 }
1621
1622 INSN(addw);
1623 INSN(subw);
1624 INSN(add);
1625 INSN(sub);
1626
1627 INSN(addsw);
1628 INSN(subsw);
1629 INSN(adds);
1630 INSN(subs);
1631
1632 #undef INSN
1633
1634 // Add/subtract (with carry)
1635 void add_sub_carry(unsigned op, Register Rd, Register Rn, Register Rm) {
1636 starti;
1637 f(op, 31, 29);
1638 f(0b11010000, 28, 21);
1639 f(0b000000, 15, 10);
1640 zrf(Rm, 16), zrf(Rn, 5), zrf(Rd, 0);
1641 }
1642
1643 #define INSN(NAME, op) \
1644 void NAME(Register Rd, Register Rn, Register Rm) { \
1645 add_sub_carry(op, Rd, Rn, Rm); \
1646 }
1647
1648 INSN(adcw, 0b000);
1649 INSN(adcsw, 0b001);
1650 INSN(sbcw, 0b010);
1651 INSN(sbcsw, 0b011);
1652 INSN(adc, 0b100);
1653 INSN(adcs, 0b101);
1654 INSN(sbc,0b110);
1655 INSN(sbcs, 0b111);
1656
1657 #undef INSN
1658
1659 // Conditional compare (both kinds)
1660 void conditional_compare(unsigned op, int o1, int o2, int o3,
1661 Register Rn, unsigned imm5, unsigned nzcv,
1662 unsigned cond) {
1663 starti;
1664 f(op, 31, 29);
1665 f(0b11010010, 28, 21);
1666 f(cond, 15, 12);
1667 f(o1, 11);
1668 f(o2, 10);
1669 f(o3, 4);
1670 f(nzcv, 3, 0);
1671 f(imm5, 20, 16), zrf(Rn, 5);
1672 }
1673
1674 #define INSN(NAME, op) \
1675 void NAME(Register Rn, Register Rm, int imm, Condition cond) { \
1676 int regNumber = (Rm == zr ? 31 : (uintptr_t)Rm); \
1677 conditional_compare(op, 0, 0, 0, Rn, regNumber, imm, cond); \
1678 } \
1679 \
1680 void NAME(Register Rn, int imm5, int imm, Condition cond) { \
1681 conditional_compare(op, 1, 0, 0, Rn, imm5, imm, cond); \
1682 }
1683
1684 INSN(ccmnw, 0b001);
1685 INSN(ccmpw, 0b011);
1686 INSN(ccmn, 0b101);
1687 INSN(ccmp, 0b111);
1688
1689 #undef INSN
1690
1691 // Conditional select
1692 void conditional_select(unsigned op, unsigned op2,
1693 Register Rd, Register Rn, Register Rm,
1694 unsigned cond) {
1695 starti;
1696 f(op, 31, 29);
1697 f(0b11010100, 28, 21);
1698 f(cond, 15, 12);
1699 f(op2, 11, 10);
1700 zrf(Rm, 16), zrf(Rn, 5), rf(Rd, 0);
1701 }
1702
1703 #define INSN(NAME, op, op2) \
1704 void NAME(Register Rd, Register Rn, Register Rm, Condition cond) { \
1705 conditional_select(op, op2, Rd, Rn, Rm, cond); \
1706 }
1707
1708 INSN(cselw, 0b000, 0b00);
1709 INSN(csincw, 0b000, 0b01);
1710 INSN(csinvw, 0b010, 0b00);
1711 INSN(csnegw, 0b010, 0b01);
1712 INSN(csel, 0b100, 0b00);
1713 INSN(csinc, 0b100, 0b01);
1714 INSN(csinv, 0b110, 0b00);
1715 INSN(csneg, 0b110, 0b01);
1716
1717 #undef INSN
1718
1719 // Data processing
1720 void data_processing(unsigned op29, unsigned opcode,
1721 Register Rd, Register Rn) {
1722 f(op29, 31, 29), f(0b11010110, 28, 21);
1723 f(opcode, 15, 10);
1724 rf(Rn, 5), rf(Rd, 0);
1725 }
1726
1727 // (1 source)
1728 #define INSN(NAME, op29, opcode2, opcode) \
1729 void NAME(Register Rd, Register Rn) { \
1730 starti; \
1731 f(opcode2, 20, 16); \
1732 data_processing(op29, opcode, Rd, Rn); \
1733 }
1734
1735 INSN(rbitw, 0b010, 0b00000, 0b00000);
1736 INSN(rev16w, 0b010, 0b00000, 0b00001);
1737 INSN(revw, 0b010, 0b00000, 0b00010);
1738 INSN(clzw, 0b010, 0b00000, 0b00100);
1739 INSN(clsw, 0b010, 0b00000, 0b00101);
1740
1741 INSN(rbit, 0b110, 0b00000, 0b00000);
1742 INSN(rev16, 0b110, 0b00000, 0b00001);
1743 INSN(rev32, 0b110, 0b00000, 0b00010);
1744 INSN(rev, 0b110, 0b00000, 0b00011);
1745 INSN(clz, 0b110, 0b00000, 0b00100);
1746 INSN(cls, 0b110, 0b00000, 0b00101);
1747
1748 #undef INSN
1749
1750 // (2 sources)
1751 #define INSN(NAME, op29, opcode) \
1752 void NAME(Register Rd, Register Rn, Register Rm) { \
1753 starti; \
1754 rf(Rm, 16); \
1755 data_processing(op29, opcode, Rd, Rn); \
1756 }
1757
1758 INSN(udivw, 0b000, 0b000010);
1759 INSN(sdivw, 0b000, 0b000011);
1760 INSN(lslvw, 0b000, 0b001000);
1761 INSN(lsrvw, 0b000, 0b001001);
1762 INSN(asrvw, 0b000, 0b001010);
1763 INSN(rorvw, 0b000, 0b001011);
1764
1765 INSN(udiv, 0b100, 0b000010);
1766 INSN(sdiv, 0b100, 0b000011);
1767 INSN(lslv, 0b100, 0b001000);
1768 INSN(lsrv, 0b100, 0b001001);
1769 INSN(asrv, 0b100, 0b001010);
1770 INSN(rorv, 0b100, 0b001011);
1771
1772 #undef INSN
1773
1774 // (3 sources)
1775 void data_processing(unsigned op54, unsigned op31, unsigned o0,
1776 Register Rd, Register Rn, Register Rm,
1777 Register Ra) {
1778 starti;
1779 f(op54, 31, 29), f(0b11011, 28, 24);
1780 f(op31, 23, 21), f(o0, 15);
1781 zrf(Rm, 16), zrf(Ra, 10), zrf(Rn, 5), zrf(Rd, 0);
1782 }
1783
1784 #define INSN(NAME, op54, op31, o0) \
1785 void NAME(Register Rd, Register Rn, Register Rm, Register Ra) { \
1786 data_processing(op54, op31, o0, Rd, Rn, Rm, Ra); \
1787 }
1788
1789 INSN(maddw, 0b000, 0b000, 0);
1790 INSN(msubw, 0b000, 0b000, 1);
1791 INSN(madd, 0b100, 0b000, 0);
1792 INSN(msub, 0b100, 0b000, 1);
1793 INSN(smaddl, 0b100, 0b001, 0);
1794 INSN(smsubl, 0b100, 0b001, 1);
1795 INSN(umaddl, 0b100, 0b101, 0);
1796 INSN(umsubl, 0b100, 0b101, 1);
1797
1798 #undef INSN
1799
1800 #define INSN(NAME, op54, op31, o0) \
1801 void NAME(Register Rd, Register Rn, Register Rm) { \
1802 data_processing(op54, op31, o0, Rd, Rn, Rm, (Register)31); \
1803 }
1804
1805 INSN(smulh, 0b100, 0b010, 0);
1806 INSN(umulh, 0b100, 0b110, 0);
1807
1808 #undef INSN
1809
1810 // Floating-point data-processing (1 source)
1811 void data_processing(unsigned op31, unsigned type, unsigned opcode,
1812 FloatRegister Vd, FloatRegister Vn) {
1813 starti;
1814 f(op31, 31, 29);
1815 f(0b11110, 28, 24);
1816 f(type, 23, 22), f(1, 21), f(opcode, 20, 15), f(0b10000, 14, 10);
1817 rf(Vn, 5), rf(Vd, 0);
1818 }
1819
1820 #define INSN(NAME, op31, type, opcode) \
1821 void NAME(FloatRegister Vd, FloatRegister Vn) { \
1822 data_processing(op31, type, opcode, Vd, Vn); \
1823 }
1824
1825 private:
1826 INSN(i_fmovs, 0b000, 0b00, 0b000000);
1827 public:
1828 INSN(fabss, 0b000, 0b00, 0b000001);
1829 INSN(fnegs, 0b000, 0b00, 0b000010);
1830 INSN(fsqrts, 0b000, 0b00, 0b000011);
1831 INSN(fcvts, 0b000, 0b00, 0b000101); // Single-precision to double-precision
1832
1833 private:
1834 INSN(i_fmovd, 0b000, 0b01, 0b000000);
1835 public:
1836 INSN(fabsd, 0b000, 0b01, 0b000001);
1837 INSN(fnegd, 0b000, 0b01, 0b000010);
1838 INSN(fsqrtd, 0b000, 0b01, 0b000011);
1839 INSN(fcvtd, 0b000, 0b01, 0b000100); // Double-precision to single-precision
1840
1841 void fmovd(FloatRegister Vd, FloatRegister Vn) {
1842 assert(Vd != Vn, "should be");
1843 i_fmovd(Vd, Vn);
1844 }
1845
1846 void fmovs(FloatRegister Vd, FloatRegister Vn) {
1847 assert(Vd != Vn, "should be");
1848 i_fmovs(Vd, Vn);
1849 }
1850
1851 #undef INSN
1852
1853 // Floating-point data-processing (2 source)
1854 void data_processing(unsigned op31, unsigned type, unsigned opcode,
1855 FloatRegister Vd, FloatRegister Vn, FloatRegister Vm) {
1856 starti;
1857 f(op31, 31, 29);
1858 f(0b11110, 28, 24);
1859 f(type, 23, 22), f(1, 21), f(opcode, 15, 12), f(0b10, 11, 10);
1860 rf(Vm, 16), rf(Vn, 5), rf(Vd, 0);
1861 }
1862
1863 #define INSN(NAME, op31, type, opcode) \
1864 void NAME(FloatRegister Vd, FloatRegister Vn, FloatRegister Vm) { \
1865 data_processing(op31, type, opcode, Vd, Vn, Vm); \
1866 }
1867
1868 INSN(fmuls, 0b000, 0b00, 0b0000);
1869 INSN(fdivs, 0b000, 0b00, 0b0001);
1870 INSN(fadds, 0b000, 0b00, 0b0010);
1871 INSN(fsubs, 0b000, 0b00, 0b0011);
1872 INSN(fmaxs, 0b000, 0b00, 0b0100);
1873 INSN(fmins, 0b000, 0b00, 0b0101);
1874 INSN(fnmuls, 0b000, 0b00, 0b1000);
1875
1876 INSN(fmuld, 0b000, 0b01, 0b0000);
1877 INSN(fdivd, 0b000, 0b01, 0b0001);
1878 INSN(faddd, 0b000, 0b01, 0b0010);
1879 INSN(fsubd, 0b000, 0b01, 0b0011);
1880 INSN(fmaxd, 0b000, 0b01, 0b0100);
1881 INSN(fmind, 0b000, 0b01, 0b0101);
1882 INSN(fnmuld, 0b000, 0b01, 0b1000);
1883
1884 #undef INSN
1885
1886 // Floating-point data-processing (3 source)
1887 void data_processing(unsigned op31, unsigned type, unsigned o1, unsigned o0,
1888 FloatRegister Vd, FloatRegister Vn, FloatRegister Vm,
1889 FloatRegister Va) {
1890 starti;
1891 f(op31, 31, 29);
1892 f(0b11111, 28, 24);
1893 f(type, 23, 22), f(o1, 21), f(o0, 15);
1894 rf(Vm, 16), rf(Va, 10), rf(Vn, 5), rf(Vd, 0);
1895 }
1896
1897 #define INSN(NAME, op31, type, o1, o0) \
1898 void NAME(FloatRegister Vd, FloatRegister Vn, FloatRegister Vm, \
1899 FloatRegister Va) { \
1900 data_processing(op31, type, o1, o0, Vd, Vn, Vm, Va); \
1901 }
1902
1903 INSN(fmadds, 0b000, 0b00, 0, 0);
1904 INSN(fmsubs, 0b000, 0b00, 0, 1);
1905 INSN(fnmadds, 0b000, 0b00, 1, 0);
1906 INSN(fnmsubs, 0b000, 0b00, 1, 1);
1907
1908 INSN(fmaddd, 0b000, 0b01, 0, 0);
1909 INSN(fmsubd, 0b000, 0b01, 0, 1);
1910 INSN(fnmaddd, 0b000, 0b01, 1, 0);
1911 INSN(fnmsub, 0b000, 0b01, 1, 1);
1912
1913 #undef INSN
1914
1915 // Floating-point conditional select
1916 void fp_conditional_select(unsigned op31, unsigned type,
1917 unsigned op1, unsigned op2,
1918 Condition cond, FloatRegister Vd,
1919 FloatRegister Vn, FloatRegister Vm) {
1920 starti;
1921 f(op31, 31, 29);
1922 f(0b11110, 28, 24);
1923 f(type, 23, 22);
1924 f(op1, 21, 21);
1925 f(op2, 11, 10);
1926 f(cond, 15, 12);
1927 rf(Vm, 16), rf(Vn, 5), rf(Vd, 0);
1928 }
1929
1930 #define INSN(NAME, op31, type, op1, op2) \
1931 void NAME(FloatRegister Vd, FloatRegister Vn, \
1932 FloatRegister Vm, Condition cond) { \
1933 fp_conditional_select(op31, type, op1, op2, cond, Vd, Vn, Vm); \
1934 }
1935
1936 INSN(fcsels, 0b000, 0b00, 0b1, 0b11);
1937 INSN(fcseld, 0b000, 0b01, 0b1, 0b11);
1938
1939 #undef INSN
1940
1941 // Floating-point<->integer conversions
1942 void float_int_convert(unsigned op31, unsigned type,
1943 unsigned rmode, unsigned opcode,
1944 Register Rd, Register Rn) {
1945 starti;
1946 f(op31, 31, 29);
1947 f(0b11110, 28, 24);
1948 f(type, 23, 22), f(1, 21), f(rmode, 20, 19);
1949 f(opcode, 18, 16), f(0b000000, 15, 10);
1950 zrf(Rn, 5), zrf(Rd, 0);
1951 }
1952
1953 #define INSN(NAME, op31, type, rmode, opcode) \
1954 void NAME(Register Rd, FloatRegister Vn) { \
1955 float_int_convert(op31, type, rmode, opcode, Rd, (Register)Vn); \
1956 }
1957
1958 INSN(fcvtzsw, 0b000, 0b00, 0b11, 0b000);
1959 INSN(fcvtzs, 0b100, 0b00, 0b11, 0b000);
1960 INSN(fcvtzdw, 0b000, 0b01, 0b11, 0b000);
1961 INSN(fcvtzd, 0b100, 0b01, 0b11, 0b000);
1962
1963 INSN(fmovs, 0b000, 0b00, 0b00, 0b110);
1964 INSN(fmovd, 0b100, 0b01, 0b00, 0b110);
1965
1966 // INSN(fmovhid, 0b100, 0b10, 0b01, 0b110);
1967
1968 #undef INSN
1969
1970 #define INSN(NAME, op31, type, rmode, opcode) \
1971 void NAME(FloatRegister Vd, Register Rn) { \
1972 float_int_convert(op31, type, rmode, opcode, (Register)Vd, Rn); \
1973 }
1974
1975 INSN(fmovs, 0b000, 0b00, 0b00, 0b111);
1976 INSN(fmovd, 0b100, 0b01, 0b00, 0b111);
1977
1978 INSN(scvtfws, 0b000, 0b00, 0b00, 0b010);
1979 INSN(scvtfs, 0b100, 0b00, 0b00, 0b010);
1980 INSN(scvtfwd, 0b000, 0b01, 0b00, 0b010);
1981 INSN(scvtfd, 0b100, 0b01, 0b00, 0b010);
1982
1983 // INSN(fmovhid, 0b100, 0b10, 0b01, 0b111);
1984
1985 #undef INSN
1986
1987 // Floating-point compare
1988 void float_compare(unsigned op31, unsigned type,
1989 unsigned op, unsigned op2,
1990 FloatRegister Vn, FloatRegister Vm = (FloatRegister)0) {
1991 starti;
1992 f(op31, 31, 29);
1993 f(0b11110, 28, 24);
1994 f(type, 23, 22), f(1, 21);
1995 f(op, 15, 14), f(0b1000, 13, 10), f(op2, 4, 0);
1996 rf(Vn, 5), rf(Vm, 16);
1997 }
1998
1999
2000 #define INSN(NAME, op31, type, op, op2) \
2001 void NAME(FloatRegister Vn, FloatRegister Vm) { \
2002 float_compare(op31, type, op, op2, Vn, Vm); \
2003 }
2004
2005 #define INSN1(NAME, op31, type, op, op2) \
2006 void NAME(FloatRegister Vn, double d) { \
2007 assert_cond(d == 0.0); \
2008 float_compare(op31, type, op, op2, Vn); \
2009 }
2010
2011 INSN(fcmps, 0b000, 0b00, 0b00, 0b00000);
2012 INSN1(fcmps, 0b000, 0b00, 0b00, 0b01000);
2013 // INSN(fcmpes, 0b000, 0b00, 0b00, 0b10000);
2014 // INSN1(fcmpes, 0b000, 0b00, 0b00, 0b11000);
2015
2016 INSN(fcmpd, 0b000, 0b01, 0b00, 0b00000);
2017 INSN1(fcmpd, 0b000, 0b01, 0b00, 0b01000);
2018 // INSN(fcmped, 0b000, 0b01, 0b00, 0b10000);
2019 // INSN1(fcmped, 0b000, 0b01, 0b00, 0b11000);
2020
2021 #undef INSN
2022 #undef INSN1
2023
2024 // Floating-point Move (immediate)
2025 private:
2026 unsigned pack(double value);
2027
2028 void fmov_imm(FloatRegister Vn, double value, unsigned size) {
2029 starti;
2030 f(0b00011110, 31, 24), f(size, 23, 22), f(1, 21);
2031 f(pack(value), 20, 13), f(0b10000000, 12, 5);
2032 rf(Vn, 0);
2033 }
2034
2035 public:
2036
2037 void fmovs(FloatRegister Vn, double value) {
2038 if (value)
2039 fmov_imm(Vn, value, 0b00);
2040 else
2041 fmovs(Vn, zr);
2042 }
2043 void fmovd(FloatRegister Vn, double value) {
2044 if (value)
2045 fmov_imm(Vn, value, 0b01);
2046 else
2047 fmovd(Vn, zr);
2048 }
2049
2050 // Floating-point rounding
2051 // type: half-precision = 11
2052 // single = 00
2053 // double = 01
2054 // rmode: A = Away = 100
2055 // I = current = 111
2056 // M = MinusInf = 010
2057 // N = eveN = 000
2058 // P = PlusInf = 001
2059 // X = eXact = 110
2060 // Z = Zero = 011
2061 void float_round(unsigned type, unsigned rmode, FloatRegister Rd, FloatRegister Rn) {
2062 starti;
2063 f(0b00011110, 31, 24);
2064 f(type, 23, 22);
2065 f(0b1001, 21, 18);
2066 f(rmode, 17, 15);
2067 f(0b10000, 14, 10);
2068 rf(Rn, 5), rf(Rd, 0);
2069 }
2070 #define INSN(NAME, type, rmode) \
2071 void NAME(FloatRegister Vd, FloatRegister Vn) { \
2072 float_round(type, rmode, Vd, Vn); \
2073 }
2074
2075 public:
2076 INSN(frintah, 0b11, 0b100);
2077 INSN(frintih, 0b11, 0b111);
2078 INSN(frintmh, 0b11, 0b010);
2079 INSN(frintnh, 0b11, 0b000);
2080 INSN(frintph, 0b11, 0b001);
2081 INSN(frintxh, 0b11, 0b110);
2082 INSN(frintzh, 0b11, 0b011);
2083
2084 INSN(frintas, 0b00, 0b100);
2085 INSN(frintis, 0b00, 0b111);
2086 INSN(frintms, 0b00, 0b010);
2087 INSN(frintns, 0b00, 0b000);
2088 INSN(frintps, 0b00, 0b001);
2089 INSN(frintxs, 0b00, 0b110);
2090 INSN(frintzs, 0b00, 0b011);
2091
2092 INSN(frintad, 0b01, 0b100);
2093 INSN(frintid, 0b01, 0b111);
2094 INSN(frintmd, 0b01, 0b010);
2095 INSN(frintnd, 0b01, 0b000);
2096 INSN(frintpd, 0b01, 0b001);
2097 INSN(frintxd, 0b01, 0b110);
2098 INSN(frintzd, 0b01, 0b011);
2099 #undef INSN
2100
2101 /* SIMD extensions
2102 *
2103 * We just use FloatRegister in the following. They are exactly the same
2104 * as SIMD registers.
2105 */
2106 public:
2107
2108 enum SIMD_Arrangement {
2109 T8B, T16B, T4H, T8H, T2S, T4S, T1D, T2D, T1Q
2110 };
2111
2112 enum SIMD_RegVariant {
2113 B, H, S, D, Q
2114 };
2115
2116 private:
2117 static short SIMD_Size_in_bytes[];
2118
2119 public:
2120 #define INSN(NAME, op) \
2121 void NAME(FloatRegister Rt, SIMD_RegVariant T, const Address &adr) { \
2122 ld_st2((Register)Rt, adr, (int)T & 3, op + ((T==Q) ? 0b10:0b00), 1); \
2123 } \
2124
2125 INSN(ldr, 1);
2126 INSN(str, 0);
2127
2128 #undef INSN
2129
2130 private:
2131
2132 void ld_st(FloatRegister Vt, SIMD_Arrangement T, Register Xn, int op1, int op2) {
2133 starti;
2134 f(0,31), f((int)T & 1, 30);
2135 f(op1, 29, 21), f(0, 20, 16), f(op2, 15, 12);
2136 f((int)T >> 1, 11, 10), srf(Xn, 5), rf(Vt, 0);
2137 }
2138 void ld_st(FloatRegister Vt, SIMD_Arrangement T, Register Xn,
2139 int imm, int op1, int op2, int regs) {
2140
2141 bool replicate = op2 >> 2 == 3;
2142 // post-index value (imm) is formed differently for replicate/non-replicate ld* instructions
2143 int expectedImmediate = replicate ? regs * (1 << (T >> 1)) : SIMD_Size_in_bytes[T] * regs;
2144 guarantee(T < T1Q , "incorrect arrangement");
2145 guarantee(imm == expectedImmediate, "bad offset");
2146 starti;
2147 f(0,31), f((int)T & 1, 30);
2148 f(op1 | 0b100, 29, 21), f(0b11111, 20, 16), f(op2, 15, 12);
2149 f((int)T >> 1, 11, 10), srf(Xn, 5), rf(Vt, 0);
2150 }
2151 void ld_st(FloatRegister Vt, SIMD_Arrangement T, Register Xn,
2152 Register Xm, int op1, int op2) {
2153 starti;
2154 f(0,31), f((int)T & 1, 30);
2155 f(op1 | 0b100, 29, 21), rf(Xm, 16), f(op2, 15, 12);
2156 f((int)T >> 1, 11, 10), srf(Xn, 5), rf(Vt, 0);
2157 }
2158
2159 void ld_st(FloatRegister Vt, SIMD_Arrangement T, Address a, int op1, int op2, int regs) {
2160 switch (a.getMode()) {
2161 case Address::base_plus_offset:
2162 guarantee(a.offset() == 0, "no offset allowed here");
2163 ld_st(Vt, T, a.base(), op1, op2);
2164 break;
2165 case Address::post:
2166 ld_st(Vt, T, a.base(), a.offset(), op1, op2, regs);
2167 break;
2168 case Address::post_reg:
2169 ld_st(Vt, T, a.base(), a.index(), op1, op2);
2170 break;
2171 default:
2172 ShouldNotReachHere();
2173 }
2174 }
2175
2176 public:
2177
2178 #define INSN1(NAME, op1, op2) \
2179 void NAME(FloatRegister Vt, SIMD_Arrangement T, const Address &a) { \
2180 ld_st(Vt, T, a, op1, op2, 1); \
2181 }
2182
2183 #define INSN2(NAME, op1, op2) \
2184 void NAME(FloatRegister Vt, FloatRegister Vt2, SIMD_Arrangement T, const Address &a) { \
2185 assert(Vt->successor() == Vt2, "Registers must be ordered"); \
2186 ld_st(Vt, T, a, op1, op2, 2); \
2187 }
2188
2189 #define INSN3(NAME, op1, op2) \
2190 void NAME(FloatRegister Vt, FloatRegister Vt2, FloatRegister Vt3, \
2191 SIMD_Arrangement T, const Address &a) { \
2192 assert(Vt->successor() == Vt2 && Vt2->successor() == Vt3, \
2193 "Registers must be ordered"); \
2194 ld_st(Vt, T, a, op1, op2, 3); \
2195 }
2196
2197 #define INSN4(NAME, op1, op2) \
2198 void NAME(FloatRegister Vt, FloatRegister Vt2, FloatRegister Vt3, \
2199 FloatRegister Vt4, SIMD_Arrangement T, const Address &a) { \
2200 assert(Vt->successor() == Vt2 && Vt2->successor() == Vt3 && \
2201 Vt3->successor() == Vt4, "Registers must be ordered"); \
2202 ld_st(Vt, T, a, op1, op2, 4); \
2203 }
2204
2205 INSN1(ld1, 0b001100010, 0b0111);
2206 INSN2(ld1, 0b001100010, 0b1010);
2207 INSN3(ld1, 0b001100010, 0b0110);
2208 INSN4(ld1, 0b001100010, 0b0010);
2209
2210 INSN2(ld2, 0b001100010, 0b1000);
2211 INSN3(ld3, 0b001100010, 0b0100);
2212 INSN4(ld4, 0b001100010, 0b0000);
2213
2214 INSN1(st1, 0b001100000, 0b0111);
2215 INSN2(st1, 0b001100000, 0b1010);
2216 INSN3(st1, 0b001100000, 0b0110);
2217 INSN4(st1, 0b001100000, 0b0010);
2218
2219 INSN2(st2, 0b001100000, 0b1000);
2220 INSN3(st3, 0b001100000, 0b0100);
2221 INSN4(st4, 0b001100000, 0b0000);
2222
2223 INSN1(ld1r, 0b001101010, 0b1100);
2224 INSN2(ld2r, 0b001101011, 0b1100);
2225 INSN3(ld3r, 0b001101010, 0b1110);
2226 INSN4(ld4r, 0b001101011, 0b1110);
2227
2228 #undef INSN1
2229 #undef INSN2
2230 #undef INSN3
2231 #undef INSN4
2232
2233 #define INSN(NAME, opc) \
2234 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm) { \
2235 starti; \
2236 assert(T == T8B || T == T16B, "must be T8B or T16B"); \
2237 f(0, 31), f((int)T & 1, 30), f(opc, 29, 21); \
2238 rf(Vm, 16), f(0b000111, 15, 10), rf(Vn, 5), rf(Vd, 0); \
2239 }
2240
2241 INSN(eor, 0b101110001);
2242 INSN(orr, 0b001110101);
2243 INSN(andr, 0b001110001);
2244 INSN(bic, 0b001110011);
2245 INSN(bif, 0b101110111);
2246 INSN(bit, 0b101110101);
2247 INSN(bsl, 0b101110011);
2248 INSN(orn, 0b001110111);
2249
2250 #undef INSN
2251
2252 #define INSN(NAME, opc, opc2, acceptT2D) \
2253 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm) { \
2254 guarantee(T != T1Q && T != T1D, "incorrect arrangement"); \
2255 if (!acceptT2D) guarantee(T != T2D, "incorrect arrangement"); \
2256 starti; \
2257 f(0, 31), f((int)T & 1, 30), f(opc, 29), f(0b01110, 28, 24); \
2258 f((int)T >> 1, 23, 22), f(1, 21), rf(Vm, 16), f(opc2, 15, 10); \
2259 rf(Vn, 5), rf(Vd, 0); \
2260 }
2261
2262 INSN(addv, 0, 0b100001, true); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S, T2D
2263 INSN(subv, 1, 0b100001, true); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S, T2D
2264 INSN(mulv, 0, 0b100111, false); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S
2265 INSN(mlav, 0, 0b100101, false); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S
2266 INSN(mlsv, 1, 0b100101, false); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S
2267 INSN(sshl, 0, 0b010001, true); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S, T2D
2268 INSN(ushl, 1, 0b010001, true); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S, T2D
2269 INSN(addpv, 0, 0b101111, true); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S, T2D
2270 INSN(smullv, 0, 0b110000, false); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S
2271 INSN(umullv, 1, 0b110000, false); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S
2272 INSN(umlalv, 1, 0b100000, false); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S
2273
2274 #undef INSN
2275
2276 #define INSN(NAME, opc, opc2, accepted) \
2277 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) { \
2278 guarantee(T != T1Q && T != T1D, "incorrect arrangement"); \
2279 if (accepted < 3) guarantee(T != T2D, "incorrect arrangement"); \
2280 if (accepted < 2) guarantee(T != T2S, "incorrect arrangement"); \
2281 if (accepted < 1) guarantee(T == T8B || T == T16B, "incorrect arrangement"); \
2282 starti; \
2283 f(0, 31), f((int)T & 1, 30), f(opc, 29), f(0b01110, 28, 24); \
2284 f((int)T >> 1, 23, 22), f(opc2, 21, 10); \
2285 rf(Vn, 5), rf(Vd, 0); \
2286 }
2287
2288 INSN(absr, 0, 0b100000101110, 3); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S, T2D
2289 INSN(negr, 1, 0b100000101110, 3); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S, T2D
2290 INSN(notr, 1, 0b100000010110, 0); // accepted arrangements: T8B, T16B
2291 INSN(addv, 0, 0b110001101110, 1); // accepted arrangements: T8B, T16B, T4H, T8H, T4S
2292 INSN(cls, 0, 0b100000010010, 2); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S
2293 INSN(clz, 1, 0b100000010010, 2); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S
2294 INSN(cnt, 0, 0b100000010110, 0); // accepted arrangements: T8B, T16B
2295 INSN(uaddlp, 1, 0b100000001010, 2); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S
2296 INSN(uaddlv, 1, 0b110000001110, 1); // accepted arrangements: T8B, T16B, T4H, T8H, T4S
2297
2298 #undef INSN
2299
2300 #define INSN(NAME, opc) \
2301 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) { \
2302 starti; \
2303 assert(T == T4S, "arrangement must be T4S"); \
2304 f(0, 31), f((int)T & 1, 30), f(0b101110, 29, 24), f(opc, 23), \
2305 f(T == T4S ? 0 : 1, 22), f(0b110000111110, 21, 10); rf(Vn, 5), rf(Vd, 0); \
2306 }
2307
2308 INSN(fmaxv, 0);
2309 INSN(fminv, 1);
2310
2311 #undef INSN
2312
2313 #define INSN(NAME, op0, cmode0) \
2314 void NAME(FloatRegister Vd, SIMD_Arrangement T, unsigned imm8, unsigned lsl = 0) { \
2315 unsigned cmode = cmode0; \
2316 unsigned op = op0; \
2317 starti; \
2318 assert(lsl == 0 || \
2319 ((T == T4H || T == T8H) && lsl == 8) || \
2320 ((T == T2S || T == T4S) && ((lsl >> 3) < 4) && ((lsl & 7) == 0)), "invalid shift");\
2321 cmode |= lsl >> 2; \
2322 if (T == T4H || T == T8H) cmode |= 0b1000; \
2323 if (!(T == T4H || T == T8H || T == T2S || T == T4S)) { \
2324 assert(op == 0 && cmode0 == 0, "must be MOVI"); \
2325 cmode = 0b1110; \
2326 if (T == T1D || T == T2D) op = 1; \
2327 } \
2328 f(0, 31), f((int)T & 1, 30), f(op, 29), f(0b0111100000, 28, 19); \
2329 f(imm8 >> 5, 18, 16), f(cmode, 15, 12), f(0x01, 11, 10), f(imm8 & 0b11111, 9, 5); \
2330 rf(Vd, 0); \
2331 }
2332
2333 INSN(movi, 0, 0);
2334 INSN(orri, 0, 1);
2335 INSN(mvni, 1, 0);
2336 INSN(bici, 1, 1);
2337
2338 #undef INSN
2339
2340 #define INSN(NAME, op1, op2, op3) \
2341 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm) { \
2342 starti; \
2343 assert(T == T2S || T == T4S || T == T2D, "invalid arrangement"); \
2344 f(0, 31), f((int)T & 1, 30), f(op1, 29), f(0b01110, 28, 24), f(op2, 23); \
2345 f(T==T2D ? 1:0, 22); f(1, 21), rf(Vm, 16), f(op3, 15, 10), rf(Vn, 5), rf(Vd, 0); \
2346 }
2347
2348 INSN(fadd, 0, 0, 0b110101);
2349 INSN(fdiv, 1, 0, 0b111111);
2350 INSN(fmul, 1, 0, 0b110111);
2351 INSN(fsub, 0, 1, 0b110101);
2352 INSN(fmla, 0, 0, 0b110011);
2353 INSN(fmls, 0, 1, 0b110011);
2354 INSN(fmax, 0, 0, 0b111101);
2355 INSN(fmin, 0, 1, 0b111101);
2356
2357 #undef INSN
2358
2359 #define INSN(NAME, opc) \
2360 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm) { \
2361 starti; \
2362 assert(T == T4S, "arrangement must be T4S"); \
2363 f(0b01011110000, 31, 21), rf(Vm, 16), f(opc, 15, 10), rf(Vn, 5), rf(Vd, 0); \
2364 }
2365
2366 INSN(sha1c, 0b000000);
2367 INSN(sha1m, 0b001000);
2368 INSN(sha1p, 0b000100);
2369 INSN(sha1su0, 0b001100);
2370 INSN(sha256h2, 0b010100);
2371 INSN(sha256h, 0b010000);
2372 INSN(sha256su1, 0b011000);
2373
2374 #undef INSN
2375
2376 #define INSN(NAME, opc) \
2377 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) { \
2378 starti; \
2379 assert(T == T4S, "arrangement must be T4S"); \
2380 f(0b0101111000101000, 31, 16), f(opc, 15, 10), rf(Vn, 5), rf(Vd, 0); \
2381 }
2382
2383 INSN(sha1h, 0b000010);
2384 INSN(sha1su1, 0b000110);
2385 INSN(sha256su0, 0b001010);
2386
2387 #undef INSN
2388
2389 #define INSN(NAME, opc) \
2390 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm) { \
2391 starti; \
2392 assert(T == T2D, "arrangement must be T2D"); \
2393 f(0b11001110011, 31, 21), rf(Vm, 16), f(opc, 15, 10), rf(Vn, 5), rf(Vd, 0); \
2394 }
2395
2396 INSN(sha512h, 0b100000);
2397 INSN(sha512h2, 0b100001);
2398 INSN(sha512su1, 0b100010);
2399
2400 #undef INSN
2401
2402 #define INSN(NAME, opc) \
2403 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) { \
2404 starti; \
2405 assert(T == T2D, "arrangement must be T2D"); \
2406 f(opc, 31, 10), rf(Vn, 5), rf(Vd, 0); \
2407 }
2408
2409 INSN(sha512su0, 0b1100111011000000100000);
2410
2411 #undef INSN
2412
2413 #define INSN(NAME, opc) \
2414 void NAME(FloatRegister Vd, FloatRegister Vn) { \
2415 starti; \
2416 f(opc, 31, 10), rf(Vn, 5), rf(Vd, 0); \
2417 }
2418
2419 INSN(aese, 0b0100111000101000010010);
2420 INSN(aesd, 0b0100111000101000010110);
2421 INSN(aesmc, 0b0100111000101000011010);
2422 INSN(aesimc, 0b0100111000101000011110);
2423
2424 #undef INSN
2425
2426 #define INSN(NAME, op1, op2) \
2427 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm, int index = 0) { \
2428 starti; \
2429 assert(T == T2S || T == T4S || T == T2D, "invalid arrangement"); \
2430 assert(index >= 0 && ((T == T2D && index <= 1) || (T != T2D && index <= 3)), "invalid index"); \
2431 f(0, 31), f((int)T & 1, 30), f(op1, 29); f(0b011111, 28, 23); \
2432 f(T == T2D ? 1 : 0, 22), f(T == T2D ? 0 : index & 1, 21), rf(Vm, 16); \
2433 f(op2, 15, 12), f(T == T2D ? index : (index >> 1), 11), f(0, 10); \
2434 rf(Vn, 5), rf(Vd, 0); \
2435 }
2436
2437 // FMLA/FMLS - Vector - Scalar
2438 INSN(fmlavs, 0, 0b0001);
2439 INSN(fmlsvs, 0, 0b0101);
2440 // FMULX - Vector - Scalar
2441 INSN(fmulxvs, 1, 0b1001);
2442
2443 #undef INSN
2444
2445 // Floating-point Reciprocal Estimate
2446 void frecpe(FloatRegister Vd, FloatRegister Vn, SIMD_RegVariant type) {
2447 assert(type == D || type == S, "Wrong type for frecpe");
2448 starti;
2449 f(0b010111101, 31, 23);
2450 f(type == D ? 1 : 0, 22);
2451 f(0b100001110110, 21, 10);
2452 rf(Vn, 5), rf(Vd, 0);
2453 }
2454
2455 // (double) {a, b} -> (a + b)
2456 void faddpd(FloatRegister Vd, FloatRegister Vn) {
2457 starti;
2458 f(0b0111111001110000110110, 31, 10);
2459 rf(Vn, 5), rf(Vd, 0);
2460 }
2461
2462 void ins(FloatRegister Vd, SIMD_RegVariant T, FloatRegister Vn, int didx, int sidx) {
2463 starti;
2464 assert(T != Q, "invalid register variant");
2465 f(0b01101110000, 31, 21), f(((didx<<1)|1)<<(int)T, 20, 16), f(0, 15);
2466 f(sidx<<(int)T, 14, 11), f(1, 10), rf(Vn, 5), rf(Vd, 0);
2467 }
2468
2469 void umov(Register Rd, FloatRegister Vn, SIMD_RegVariant T, int idx) {
2470 starti;
2471 f(0, 31), f(T==D ? 1:0, 30), f(0b001110000, 29, 21);
2472 f(((idx<<1)|1)<<(int)T, 20, 16), f(0b001111, 15, 10);
2473 rf(Vn, 5), rf(Rd, 0);
2474 }
2475
2476 #define INSN(NAME, opc, opc2, isSHR) \
2477 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, int shift){ \
2478 starti; \
2479 /* The encodings for the immh:immb fields (bits 22:16) in *SHR are \
2480 * 0001 xxx 8B/16B, shift = 16 - UInt(immh:immb) \
2481 * 001x xxx 4H/8H, shift = 32 - UInt(immh:immb) \
2482 * 01xx xxx 2S/4S, shift = 64 - UInt(immh:immb) \
2483 * 1xxx xxx 1D/2D, shift = 128 - UInt(immh:immb) \
2484 * (1D is RESERVED) \
2485 * for SHL shift is calculated as: \
2486 * 0001 xxx 8B/16B, shift = UInt(immh:immb) - 8 \
2487 * 001x xxx 4H/8H, shift = UInt(immh:immb) - 16 \
2488 * 01xx xxx 2S/4S, shift = UInt(immh:immb) - 32 \
2489 * 1xxx xxx 1D/2D, shift = UInt(immh:immb) - 64 \
2490 * (1D is RESERVED) \
2491 */ \
2492 assert((1 << ((T>>1)+3)) > shift, "Invalid Shift value"); \
2493 int cVal = (1 << (((T >> 1) + 3) + (isSHR ? 1 : 0))); \
2494 int encodedShift = isSHR ? cVal - shift : cVal + shift; \
2495 f(0, 31), f(T & 1, 30), f(opc, 29), f(0b011110, 28, 23), \
2496 f(encodedShift, 22, 16); f(opc2, 15, 10), rf(Vn, 5), rf(Vd, 0); \
2497 }
2498
2499 INSN(shl, 0, 0b010101, /* isSHR = */ false);
2500 INSN(sshr, 0, 0b000001, /* isSHR = */ true);
2501 INSN(ushr, 1, 0b000001, /* isSHR = */ true);
2502
2503 #undef INSN
2504
2505 private:
2506 void _ushll(FloatRegister Vd, SIMD_Arrangement Ta, FloatRegister Vn, SIMD_Arrangement Tb, int shift) {
2507 starti;
2508 /* The encodings for the immh:immb fields (bits 22:16) are
2509 * 0001 xxx 8H, 8B/16b shift = xxx
2510 * 001x xxx 4S, 4H/8H shift = xxxx
2511 * 01xx xxx 2D, 2S/4S shift = xxxxx
2512 * 1xxx xxx RESERVED
2513 */
2514 assert((Tb >> 1) + 1 == (Ta >> 1), "Incompatible arrangement");
2515 assert((1 << ((Tb>>1)+3)) > shift, "Invalid shift value");
2516 f(0, 31), f(Tb & 1, 30), f(0b1011110, 29, 23), f((1 << ((Tb>>1)+3))|shift, 22, 16);
2517 f(0b101001, 15, 10), rf(Vn, 5), rf(Vd, 0);
2518 }
2519
2520 public:
2521 void ushll(FloatRegister Vd, SIMD_Arrangement Ta, FloatRegister Vn, SIMD_Arrangement Tb, int shift) {
2522 assert(Tb == T8B || Tb == T4H || Tb == T2S, "invalid arrangement");
2523 _ushll(Vd, Ta, Vn, Tb, shift);
2524 }
2525
2526 void ushll2(FloatRegister Vd, SIMD_Arrangement Ta, FloatRegister Vn, SIMD_Arrangement Tb, int shift) {
2527 assert(Tb == T16B || Tb == T8H || Tb == T4S, "invalid arrangement");
2528 _ushll(Vd, Ta, Vn, Tb, shift);
2529 }
2530
2531 // Move from general purpose register
2532 // mov Vd.T[index], Rn
2533 void mov(FloatRegister Vd, SIMD_Arrangement T, int index, Register Xn) {
2534 starti;
2535 f(0b01001110000, 31, 21), f(((1 << (T >> 1)) | (index << ((T >> 1) + 1))), 20, 16);
2536 f(0b000111, 15, 10), zrf(Xn, 5), rf(Vd, 0);
2537 }
2538
2539 // Move to general purpose register
2540 // mov Rd, Vn.T[index]
2541 void mov(Register Xd, FloatRegister Vn, SIMD_Arrangement T, int index) {
2542 guarantee(T >= T2S && T < T1Q, "only D and S arrangements are supported");
2543 starti;
2544 f(0, 31), f((T >= T1D) ? 1:0, 30), f(0b001110000, 29, 21);
2545 f(((1 << (T >> 1)) | (index << ((T >> 1) + 1))), 20, 16);
2546 f(0b001111, 15, 10), rf(Vn, 5), rf(Xd, 0);
2547 }
2548
2549 private:
2550 void _pmull(FloatRegister Vd, SIMD_Arrangement Ta, FloatRegister Vn, FloatRegister Vm, SIMD_Arrangement Tb) {
2551 starti;
2552 assert((Ta == T1Q && (Tb == T1D || Tb == T2D)) ||
2553 (Ta == T8H && (Tb == T8B || Tb == T16B)), "Invalid Size specifier");
2554 int size = (Ta == T1Q) ? 0b11 : 0b00;
2555 f(0, 31), f(Tb & 1, 30), f(0b001110, 29, 24), f(size, 23, 22);
2556 f(1, 21), rf(Vm, 16), f(0b111000, 15, 10), rf(Vn, 5), rf(Vd, 0);
2557 }
2558
2559 public:
2560 void pmull(FloatRegister Vd, SIMD_Arrangement Ta, FloatRegister Vn, FloatRegister Vm, SIMD_Arrangement Tb) {
2561 assert(Tb == T1D || Tb == T8B, "pmull assumes T1D or T8B as the second size specifier");
2562 _pmull(Vd, Ta, Vn, Vm, Tb);
2563 }
2564
2565 void pmull2(FloatRegister Vd, SIMD_Arrangement Ta, FloatRegister Vn, FloatRegister Vm, SIMD_Arrangement Tb) {
2566 assert(Tb == T2D || Tb == T16B, "pmull2 assumes T2D or T16B as the second size specifier");
2567 _pmull(Vd, Ta, Vn, Vm, Tb);
2568 }
2569
2570 void uqxtn(FloatRegister Vd, SIMD_Arrangement Tb, FloatRegister Vn, SIMD_Arrangement Ta) {
2571 starti;
2572 int size_b = (int)Tb >> 1;
2573 int size_a = (int)Ta >> 1;
2574 assert(size_b < 3 && size_b == size_a - 1, "Invalid size specifier");
2575 f(0, 31), f(Tb & 1, 30), f(0b101110, 29, 24), f(size_b, 23, 22);
2576 f(0b100001010010, 21, 10), rf(Vn, 5), rf(Vd, 0);
2577 }
2578
2579 void dup(FloatRegister Vd, SIMD_Arrangement T, Register Xs)
2580 {
2581 starti;
2582 assert(T != T1D, "reserved encoding");
2583 f(0,31), f((int)T & 1, 30), f(0b001110000, 29, 21);
2584 f((1 << (T >> 1)), 20, 16), f(0b000011, 15, 10), zrf(Xs, 5), rf(Vd, 0);
2585 }
2586
2587 void dup(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, int index = 0)
2588 {
2589 starti;
2590 assert(T != T1D, "reserved encoding");
2591 f(0, 31), f((int)T & 1, 30), f(0b001110000, 29, 21);
2592 f(((1 << (T >> 1)) | (index << ((T >> 1) + 1))), 20, 16);
2593 f(0b000001, 15, 10), rf(Vn, 5), rf(Vd, 0);
2594 }
2595
2596 // AdvSIMD ZIP/UZP/TRN
2597 #define INSN(NAME, opcode) \
2598 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm) { \
2599 guarantee(T != T1D && T != T1Q, "invalid arrangement"); \
2600 starti; \
2601 f(0, 31), f(0b001110, 29, 24), f(0, 21), f(0, 15); \
2602 f(opcode, 14, 12), f(0b10, 11, 10); \
2603 rf(Vm, 16), rf(Vn, 5), rf(Vd, 0); \
2604 f(T & 1, 30), f(T >> 1, 23, 22); \
2605 }
2606
2607 INSN(uzp1, 0b001);
2608 INSN(trn1, 0b010);
2609 INSN(zip1, 0b011);
2610 INSN(uzp2, 0b101);
2611 INSN(trn2, 0b110);
2612 INSN(zip2, 0b111);
2613
2614 #undef INSN
2615
2616 // CRC32 instructions
2617 #define INSN(NAME, c, sf, sz) \
2618 void NAME(Register Rd, Register Rn, Register Rm) { \
2619 starti; \
2620 f(sf, 31), f(0b0011010110, 30, 21), f(0b010, 15, 13), f(c, 12); \
2621 f(sz, 11, 10), rf(Rm, 16), rf(Rn, 5), rf(Rd, 0); \
2622 }
2623
2624 INSN(crc32b, 0, 0, 0b00);
2625 INSN(crc32h, 0, 0, 0b01);
2626 INSN(crc32w, 0, 0, 0b10);
2627 INSN(crc32x, 0, 1, 0b11);
2628 INSN(crc32cb, 1, 0, 0b00);
2629 INSN(crc32ch, 1, 0, 0b01);
2630 INSN(crc32cw, 1, 0, 0b10);
2631 INSN(crc32cx, 1, 1, 0b11);
2632
2633 #undef INSN
2634
2635 // Table vector lookup
2636 #define INSN(NAME, op) \
2637 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, unsigned registers, FloatRegister Vm) { \
2638 starti; \
2639 assert(T == T8B || T == T16B, "invalid arrangement"); \
2640 assert(0 < registers && registers <= 4, "invalid number of registers"); \
2641 f(0, 31), f((int)T & 1, 30), f(0b001110000, 29, 21), rf(Vm, 16), f(0, 15); \
2642 f(registers - 1, 14, 13), f(op, 12),f(0b00, 11, 10), rf(Vn, 5), rf(Vd, 0); \
2643 }
2644
2645 INSN(tbl, 0);
2646 INSN(tbx, 1);
2647
2648 #undef INSN
2649
2650 // AdvSIMD two-reg misc
2651 // In this instruction group, the 2 bits in the size field ([23:22]) may be
2652 // fixed or determined by the "SIMD_Arrangement T", or both. The additional
2653 // parameter "tmask" is a 2-bit mask used to indicate which bits in the size
2654 // field are determined by the SIMD_Arrangement. The bit of "tmask" should be
2655 // set to 1 if corresponding bit marked as "x" in the ArmARM.
2656 #define INSN(NAME, U, size, tmask, opcode) \
2657 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) { \
2658 starti; \
2659 assert((ASSERTION), MSG); \
2660 f(0, 31), f((int)T & 1, 30), f(U, 29), f(0b01110, 28, 24); \
2661 f(size | ((int)(T >> 1) & tmask), 23, 22), f(0b10000, 21, 17); \
2662 f(opcode, 16, 12), f(0b10, 11, 10), rf(Vn, 5), rf(Vd, 0); \
2663 }
2664
2665 #define MSG "invalid arrangement"
2666
2667 #define ASSERTION (T == T2S || T == T4S || T == T2D)
2668 INSN(fsqrt, 1, 0b10, 0b01, 0b11111);
2669 INSN(fabs, 0, 0b10, 0b01, 0b01111);
2670 INSN(fneg, 1, 0b10, 0b01, 0b01111);
2671 INSN(frintn, 0, 0b00, 0b01, 0b11000);
2672 INSN(frintm, 0, 0b00, 0b01, 0b11001);
2673 INSN(frintp, 0, 0b10, 0b01, 0b11000);
2674 #undef ASSERTION
2675
2676 #define ASSERTION (T == T8B || T == T16B || T == T4H || T == T8H || T == T2S || T == T4S)
2677 INSN(rev64, 0, 0b00, 0b11, 0b00000);
2678 #undef ASSERTION
2679
2680 #define ASSERTION (T == T8B || T == T16B || T == T4H || T == T8H)
2681 INSN(rev32, 1, 0b00, 0b11, 0b00000);
2682 #undef ASSERTION
2683
2684 #define ASSERTION (T == T8B || T == T16B)
2685 INSN(rev16, 0, 0b00, 0b11, 0b00001);
2686 INSN(rbit, 1, 0b01, 0b00, 0b00101);
2687 #undef ASSERTION
2688
2689 #undef MSG
2690
2691 #undef INSN
2692
2693 void ext(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm, int index)
2694 {
2695 starti;
2696 assert(T == T8B || T == T16B, "invalid arrangement");
2697 assert((T == T8B && index <= 0b0111) || (T == T16B && index <= 0b1111), "Invalid index value");
2698 f(0, 31), f((int)T & 1, 30), f(0b101110000, 29, 21);
2699 rf(Vm, 16), f(0, 15), f(index, 14, 11);
2700 f(0, 10), rf(Vn, 5), rf(Vd, 0);
2701 }
2702
2703 void sve_inc(Register Xdn, SIMD_RegVariant T, unsigned imm4 = 1, int pattern = 0b11111) {
2704 starti;
2705 assert(T != Q, "invalid size");
2706 f(0b00000100,31, 24), f(T, 23, 22), f(0b11, 21, 20);
2707 f(imm4 - 1, 19, 16), f(0b111000, 15, 10), f(pattern, 9, 5), rf(Xdn, 0);
2708 }
2709
2710 Assembler(CodeBuffer* code) : AbstractAssembler(code) {
2711 }
2712
2713 virtual RegisterOrConstant delayed_value_impl(intptr_t* delayed_value_addr,
2714 Register tmp,
2715 int offset) {
2716 ShouldNotCallThis();
2717 return RegisterOrConstant();
2718 }
2719
2720 // Stack overflow checking
2721 virtual void bang_stack_with_offset(int offset);
2722
2723 static bool operand_valid_for_logical_immediate(bool is32, uint64_t imm);
2724 static bool operand_valid_for_add_sub_immediate(int64_t imm);
2725 static bool operand_valid_for_float_immediate(double imm);
2726
2727 void emit_data64(jlong data, relocInfo::relocType rtype, int format = 0);
2728 void emit_data64(jlong data, RelocationHolder const& rspec, int format = 0);
2729 };
2730
2731 inline Assembler::Membar_mask_bits operator|(Assembler::Membar_mask_bits a,
2732 Assembler::Membar_mask_bits b) {
2733 return Assembler::Membar_mask_bits(unsigned(a)|unsigned(b));
2734 }
2735
2736 Instruction_aarch64::~Instruction_aarch64() {
2737 assem->emit();
2738 }
2739
2740 #undef starti
2741
2742 // Invert a condition
2743 inline const Assembler::Condition operator~(const Assembler::Condition cond) {
2744 return Assembler::Condition(int(cond) ^ 1);
2745 }
2746
2747 class BiasedLockingCounters;
2748
2749 extern "C" void das(uint64_t start, int len);
2750
2751 #endif // CPU_AARCH64_ASSEMBLER_AARCH64_HPP