src/hotspot/cpu/aarch64/assembler_aarch64.hpp

*** 2674,20 ***
  
  #undef MSG
  
  #undef INSN
  
! void ext(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm, int index)
    {
      starti;
      assert(T == T8B || T == T16B, "invalid arrangement");
      assert((T == T8B && index <= 0b0111) || (T == T16B && index <= 0b1111), "Invalid index value");
      f(0, 31), f((int)T & 1, 30), f(0b101110000, 29, 21);
      rf(Vm, 16), f(0, 15), f(index, 14, 11);
      f(0, 10), rf(Vn, 5), rf(Vd, 0);
    }
  
    Assembler(CodeBuffer* code) : AbstractAssembler(code) {
    }
  
    virtual RegisterOrConstant delayed_value_impl(intptr_t* delayed_value_addr,
                                                  Register tmp,
--- 2674,27 ---
  
  #undef MSG
  
  #undef INSN
  
!   void ext(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm, int index)
    {
      starti;
      assert(T == T8B || T == T16B, "invalid arrangement");
      assert((T == T8B && index <= 0b0111) || (T == T16B && index <= 0b1111), "Invalid index value");
      f(0, 31), f((int)T & 1, 30), f(0b101110000, 29, 21);
      rf(Vm, 16), f(0, 15), f(index, 14, 11);
      f(0, 10), rf(Vn, 5), rf(Vd, 0);
    }
  
+   void sve_inc(Register Xdn, SIMD_RegVariant T, unsigned imm4 = 1, int pattern = 0b11111) {
+     starti;
+     assert(T != Q, "invalid size");
+     f(0b00000100,31, 24), f(T, 23, 22), f(0b11, 21, 20);
+     f(imm4 - 1, 19, 16), f(0b111000, 15, 10), f(pattern, 9, 5), rf(Xdn, 0);
+   }
+ 
    Assembler(CodeBuffer* code) : AbstractAssembler(code) {
    }
  
    virtual RegisterOrConstant delayed_value_impl(intptr_t* delayed_value_addr,
                                                  Register tmp,