5208   assert(line.getMode() == Address::base_plus_offset, "mode should be base_plus_offset");
5209   assert(line.index() == noreg, "index should be noreg");
5210   assert(line.offset() == 0, "offset should be 0");
5211   // would like to assert this
5212   // assert(line._ext.shift == 0, "shift should be zero");
5213   if (VM_Version::supports_dcpop()) {
5214     // writeback using clear virtual address to point of persistence
5215     dc(Assembler::CVAP, line.base());
5216   } else {
5217     // no need to generate anything as Unsafe.writebackMemory should
5218     // never invoke this stub
5219   }
5220 }
5221 
5222 void MacroAssembler::cache_wbsync(bool is_pre) {
5223   // we only need a barrier post sync
5224   if (!is_pre) {
5225     membar(Assembler::AnyAny);
5226   }
5227 }

5208   assert(line.getMode() == Address::base_plus_offset, "mode should be base_plus_offset");
5209   assert(line.index() == noreg, "index should be noreg");
5210   assert(line.offset() == 0, "offset should be 0");
5211   // would like to assert this
5212   // assert(line._ext.shift == 0, "shift should be zero");
5213   if (VM_Version::supports_dcpop()) {
5214     // writeback using clear virtual address to point of persistence
5215     dc(Assembler::CVAP, line.base());
5216   } else {
5217     // no need to generate anything as Unsafe.writebackMemory should
5218     // never invoke this stub
5219   }
5220 }
5221 
5222 void MacroAssembler::cache_wbsync(bool is_pre) {
5223   // we only need a barrier post sync
5224   if (!is_pre) {
5225     membar(Assembler::AnyAny);
5226   }
5227 }
5228 
5229 void MacroAssembler::verify_sve_vector_length() {
5230   Label verify_ok;
5231   assert(UseSVE > 0, "should only be used for SVE");
5232   movw(rscratch1, zr);
5233   sve_inc(rscratch1, B);
5234   subsw(zr, rscratch1, VM_Version::get_initial_sve_vector_length());
5235   br(EQ, verify_ok);
5236   stop("Error: SVE vector length has changed since jvm startup");
5237   bind(verify_ok);
5238 }