1 /*
2 * Copyright (c) 2000, 2019, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2014, 2020, Red Hat Inc. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
112 CONSTANT_REGISTER_DECLARATION(Register, r31_sp, (31));
113 CONSTANT_REGISTER_DECLARATION(Register, zr, (32));
114 CONSTANT_REGISTER_DECLARATION(Register, sp, (33));
115
116 // Used as a filler in instructions where a register field is unused.
117 const Register dummy_reg = r31_sp;
118
119 // Use FloatRegister as shortcut
120 class FloatRegisterImpl;
121 typedef FloatRegisterImpl* FloatRegister;
122
123 inline FloatRegister as_FloatRegister(int encoding) {
124 return (FloatRegister)(intptr_t) encoding;
125 }
126
127 // The implementation of floating point registers for the architecture
128 class FloatRegisterImpl: public AbstractRegisterImpl {
129 public:
130 enum {
131 number_of_registers = 32,
132 max_slots_per_register = 4,
133 save_slots_per_register = 2,
134 extra_save_slots_per_register = max_slots_per_register - save_slots_per_register
135 };
136
137 // construction
138 inline friend FloatRegister as_FloatRegister(int encoding);
139
140 VMReg as_VMReg();
141
142 // derived registers, offsets, and addresses
143 FloatRegister successor() const { return as_FloatRegister((encoding() + 1) % 32); }
144
145 // accessors
146 int encoding() const { assert(is_valid(), "invalid register"); return (intptr_t)this; }
147 int encoding_nocheck() const { return (intptr_t)this; }
148 bool is_valid() const { return 0 <= (intptr_t)this && (intptr_t)this < number_of_registers; }
149 const char* name() const;
150
151 };
152
153 // The float registers of the AARCH64 architecture
154
170 CONSTANT_REGISTER_DECLARATION(FloatRegister, v13 , (13));
171 CONSTANT_REGISTER_DECLARATION(FloatRegister, v14 , (14));
172 CONSTANT_REGISTER_DECLARATION(FloatRegister, v15 , (15));
173 CONSTANT_REGISTER_DECLARATION(FloatRegister, v16 , (16));
174 CONSTANT_REGISTER_DECLARATION(FloatRegister, v17 , (17));
175 CONSTANT_REGISTER_DECLARATION(FloatRegister, v18 , (18));
176 CONSTANT_REGISTER_DECLARATION(FloatRegister, v19 , (19));
177 CONSTANT_REGISTER_DECLARATION(FloatRegister, v20 , (20));
178 CONSTANT_REGISTER_DECLARATION(FloatRegister, v21 , (21));
179 CONSTANT_REGISTER_DECLARATION(FloatRegister, v22 , (22));
180 CONSTANT_REGISTER_DECLARATION(FloatRegister, v23 , (23));
181 CONSTANT_REGISTER_DECLARATION(FloatRegister, v24 , (24));
182 CONSTANT_REGISTER_DECLARATION(FloatRegister, v25 , (25));
183 CONSTANT_REGISTER_DECLARATION(FloatRegister, v26 , (26));
184 CONSTANT_REGISTER_DECLARATION(FloatRegister, v27 , (27));
185 CONSTANT_REGISTER_DECLARATION(FloatRegister, v28 , (28));
186 CONSTANT_REGISTER_DECLARATION(FloatRegister, v29 , (29));
187 CONSTANT_REGISTER_DECLARATION(FloatRegister, v30 , (30));
188 CONSTANT_REGISTER_DECLARATION(FloatRegister, v31 , (31));
189
190 // Need to know the total number of registers of all sorts for SharedInfo.
191 // Define a class that exports it.
192 class ConcreteRegisterImpl : public AbstractRegisterImpl {
193 public:
194 enum {
195 // A big enough number for C2: all the registers plus flags
196 // This number must be large enough to cover REG_COUNT (defined by c2) registers.
197 // There is no requirement that any ordering here matches any ordering c2 gives
198 // it's optoregs.
199
200 number_of_registers = (RegisterImpl::max_slots_per_register * RegisterImpl::number_of_registers +
201 FloatRegisterImpl::max_slots_per_register * FloatRegisterImpl::number_of_registers +
202 1) // flags
203 };
204
205 // added to make it compile
206 static const int max_gpr;
207 static const int max_fpr;
208 };
209
210 // A set of registers
211 class RegSet {
212 uint32_t _bitset;
213
214 RegSet(uint32_t bitset) : _bitset(bitset) { }
215
216 public:
217
218 RegSet() : _bitset(0) { }
219
220 RegSet(Register r1) : _bitset(r1->bit()) { }
221
222 RegSet operator+(const RegSet aSet) const {
223 RegSet result(_bitset | aSet._bitset);
224 return result;
225 }
226
227 RegSet operator-(const RegSet aSet) const {
|
1 /*
2 * Copyright (c) 2000, 2020, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2014, 2020, Red Hat Inc. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
112 CONSTANT_REGISTER_DECLARATION(Register, r31_sp, (31));
113 CONSTANT_REGISTER_DECLARATION(Register, zr, (32));
114 CONSTANT_REGISTER_DECLARATION(Register, sp, (33));
115
116 // Used as a filler in instructions where a register field is unused.
117 const Register dummy_reg = r31_sp;
118
119 // Use FloatRegister as shortcut
120 class FloatRegisterImpl;
121 typedef FloatRegisterImpl* FloatRegister;
122
123 inline FloatRegister as_FloatRegister(int encoding) {
124 return (FloatRegister)(intptr_t) encoding;
125 }
126
127 // The implementation of floating point registers for the architecture
128 class FloatRegisterImpl: public AbstractRegisterImpl {
129 public:
130 enum {
131 number_of_registers = 32,
132 max_slots_per_register = 8,
133 save_slots_per_register = 2,
134 slots_per_neon_register = 4,
135 extra_save_slots_per_neon_register = slots_per_neon_register - save_slots_per_register
136 };
137
138 // construction
139 inline friend FloatRegister as_FloatRegister(int encoding);
140
141 VMReg as_VMReg();
142
143 // derived registers, offsets, and addresses
144 FloatRegister successor() const { return as_FloatRegister((encoding() + 1) % 32); }
145
146 // accessors
147 int encoding() const { assert(is_valid(), "invalid register"); return (intptr_t)this; }
148 int encoding_nocheck() const { return (intptr_t)this; }
149 bool is_valid() const { return 0 <= (intptr_t)this && (intptr_t)this < number_of_registers; }
150 const char* name() const;
151
152 };
153
154 // The float registers of the AARCH64 architecture
155
171 CONSTANT_REGISTER_DECLARATION(FloatRegister, v13 , (13));
172 CONSTANT_REGISTER_DECLARATION(FloatRegister, v14 , (14));
173 CONSTANT_REGISTER_DECLARATION(FloatRegister, v15 , (15));
174 CONSTANT_REGISTER_DECLARATION(FloatRegister, v16 , (16));
175 CONSTANT_REGISTER_DECLARATION(FloatRegister, v17 , (17));
176 CONSTANT_REGISTER_DECLARATION(FloatRegister, v18 , (18));
177 CONSTANT_REGISTER_DECLARATION(FloatRegister, v19 , (19));
178 CONSTANT_REGISTER_DECLARATION(FloatRegister, v20 , (20));
179 CONSTANT_REGISTER_DECLARATION(FloatRegister, v21 , (21));
180 CONSTANT_REGISTER_DECLARATION(FloatRegister, v22 , (22));
181 CONSTANT_REGISTER_DECLARATION(FloatRegister, v23 , (23));
182 CONSTANT_REGISTER_DECLARATION(FloatRegister, v24 , (24));
183 CONSTANT_REGISTER_DECLARATION(FloatRegister, v25 , (25));
184 CONSTANT_REGISTER_DECLARATION(FloatRegister, v26 , (26));
185 CONSTANT_REGISTER_DECLARATION(FloatRegister, v27 , (27));
186 CONSTANT_REGISTER_DECLARATION(FloatRegister, v28 , (28));
187 CONSTANT_REGISTER_DECLARATION(FloatRegister, v29 , (29));
188 CONSTANT_REGISTER_DECLARATION(FloatRegister, v30 , (30));
189 CONSTANT_REGISTER_DECLARATION(FloatRegister, v31 , (31));
190
191 // SVE vector registers, shared with the SIMD&FP v0-v31. Vn maps to Zn[127:0].
192 CONSTANT_REGISTER_DECLARATION(FloatRegister, z0 , ( 0));
193 CONSTANT_REGISTER_DECLARATION(FloatRegister, z1 , ( 1));
194 CONSTANT_REGISTER_DECLARATION(FloatRegister, z2 , ( 2));
195 CONSTANT_REGISTER_DECLARATION(FloatRegister, z3 , ( 3));
196 CONSTANT_REGISTER_DECLARATION(FloatRegister, z4 , ( 4));
197 CONSTANT_REGISTER_DECLARATION(FloatRegister, z5 , ( 5));
198 CONSTANT_REGISTER_DECLARATION(FloatRegister, z6 , ( 6));
199 CONSTANT_REGISTER_DECLARATION(FloatRegister, z7 , ( 7));
200 CONSTANT_REGISTER_DECLARATION(FloatRegister, z8 , ( 8));
201 CONSTANT_REGISTER_DECLARATION(FloatRegister, z9 , ( 9));
202 CONSTANT_REGISTER_DECLARATION(FloatRegister, z10 , (10));
203 CONSTANT_REGISTER_DECLARATION(FloatRegister, z11 , (11));
204 CONSTANT_REGISTER_DECLARATION(FloatRegister, z12 , (12));
205 CONSTANT_REGISTER_DECLARATION(FloatRegister, z13 , (13));
206 CONSTANT_REGISTER_DECLARATION(FloatRegister, z14 , (14));
207 CONSTANT_REGISTER_DECLARATION(FloatRegister, z15 , (15));
208 CONSTANT_REGISTER_DECLARATION(FloatRegister, z16 , (16));
209 CONSTANT_REGISTER_DECLARATION(FloatRegister, z17 , (17));
210 CONSTANT_REGISTER_DECLARATION(FloatRegister, z18 , (18));
211 CONSTANT_REGISTER_DECLARATION(FloatRegister, z19 , (19));
212 CONSTANT_REGISTER_DECLARATION(FloatRegister, z20 , (20));
213 CONSTANT_REGISTER_DECLARATION(FloatRegister, z21 , (21));
214 CONSTANT_REGISTER_DECLARATION(FloatRegister, z22 , (22));
215 CONSTANT_REGISTER_DECLARATION(FloatRegister, z23 , (23));
216 CONSTANT_REGISTER_DECLARATION(FloatRegister, z24 , (24));
217 CONSTANT_REGISTER_DECLARATION(FloatRegister, z25 , (25));
218 CONSTANT_REGISTER_DECLARATION(FloatRegister, z26 , (26));
219 CONSTANT_REGISTER_DECLARATION(FloatRegister, z27 , (27));
220 CONSTANT_REGISTER_DECLARATION(FloatRegister, z28 , (28));
221 CONSTANT_REGISTER_DECLARATION(FloatRegister, z29 , (29));
222 CONSTANT_REGISTER_DECLARATION(FloatRegister, z30 , (30));
223 CONSTANT_REGISTER_DECLARATION(FloatRegister, z31 , (31));
224
225
226 class PRegisterImpl;
227 typedef PRegisterImpl* PRegister;
228 inline PRegister as_PRegister(int encoding) {
229 return (PRegister)(intptr_t)encoding;
230 }
231
232 // The implementation of predicate registers for the architecture
233 class PRegisterImpl: public AbstractRegisterImpl {
234 public:
235 enum {
236 number_of_registers = 16,
237 max_slots_per_register = 1
238 };
239
240 // construction
241 inline friend PRegister as_PRegister(int encoding);
242
243 VMReg as_VMReg();
244
245 // derived registers, offsets, and addresses
246 PRegister successor() const { return as_PRegister(encoding() + 1); }
247
248 // accessors
249 int encoding() const { assert(is_valid(), "invalid register"); return (intptr_t)this; }
250 int encoding_nocheck() const { return (intptr_t)this; }
251 bool is_valid() const { return 0 <= (intptr_t)this && (intptr_t)this < number_of_registers; }
252 const char* name() const;
253 };
254
255 // The predicate registers of SVE.
256 CONSTANT_REGISTER_DECLARATION(PRegister, p0, ( 0));
257 CONSTANT_REGISTER_DECLARATION(PRegister, p1, ( 1));
258 CONSTANT_REGISTER_DECLARATION(PRegister, p2, ( 2));
259 CONSTANT_REGISTER_DECLARATION(PRegister, p3, ( 3));
260 CONSTANT_REGISTER_DECLARATION(PRegister, p4, ( 4));
261 CONSTANT_REGISTER_DECLARATION(PRegister, p5, ( 5));
262 CONSTANT_REGISTER_DECLARATION(PRegister, p6, ( 6));
263 CONSTANT_REGISTER_DECLARATION(PRegister, p7, ( 7));
264 CONSTANT_REGISTER_DECLARATION(PRegister, p8, ( 8));
265 CONSTANT_REGISTER_DECLARATION(PRegister, p9, ( 9));
266 CONSTANT_REGISTER_DECLARATION(PRegister, p10, (10));
267 CONSTANT_REGISTER_DECLARATION(PRegister, p11, (11));
268 CONSTANT_REGISTER_DECLARATION(PRegister, p12, (12));
269 CONSTANT_REGISTER_DECLARATION(PRegister, p13, (13));
270 CONSTANT_REGISTER_DECLARATION(PRegister, p14, (14));
271 CONSTANT_REGISTER_DECLARATION(PRegister, p15, (15));
272
273 // Need to know the total number of registers of all sorts for SharedInfo.
274 // Define a class that exports it.
275 class ConcreteRegisterImpl : public AbstractRegisterImpl {
276 public:
277 enum {
278 // A big enough number for C2: all the registers plus flags
279 // This number must be large enough to cover REG_COUNT (defined by c2) registers.
280 // There is no requirement that any ordering here matches any ordering c2 gives
281 // it's optoregs.
282
283 number_of_registers = (RegisterImpl::max_slots_per_register * RegisterImpl::number_of_registers +
284 FloatRegisterImpl::max_slots_per_register * FloatRegisterImpl::number_of_registers +
285 PRegisterImpl::max_slots_per_register * PRegisterImpl::number_of_registers +
286 1) // flags
287 };
288
289 // added to make it compile
290 static const int max_gpr;
291 static const int max_fpr;
292 static const int max_pr;
293 };
294
295 // A set of registers
296 class RegSet {
297 uint32_t _bitset;
298
299 RegSet(uint32_t bitset) : _bitset(bitset) { }
300
301 public:
302
303 RegSet() : _bitset(0) { }
304
305 RegSet(Register r1) : _bitset(r1->bit()) { }
306
307 RegSet operator+(const RegSet aSet) const {
308 RegSet result(_bitset | aSet._bitset);
309 return result;
310 }
311
312 RegSet operator-(const RegSet aSet) const {
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