1 // 2 // Copyright (c) 2017, 2020, Oracle and/or its affiliates. All rights reserved. 3 // Copyright (c) 2017, 2020 SAP SE. All rights reserved. 4 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 5 // 6 // This code is free software; you can redistribute it and/or modify it 7 // under the terms of the GNU General Public License version 2 only, as 8 // published by the Free Software Foundation. 9 // 10 // This code is distributed in the hope that it will be useful, but WITHOUT 11 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 13 // version 2 for more details (a copy is included in the LICENSE file that 14 // accompanied this code). 15 // 16 // You should have received a copy of the GNU General Public License version 17 // 2 along with this work; if not, write to the Free Software Foundation, 18 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 19 // 20 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 21 // or visit www.oracle.com if you need additional information or have any 22 // questions. 23 // 24 25 // z/Architecture Architecture Description File 26 27 // Major contributions by AS, JL, LS. 28 29 // 30 // Following information is derived from private mail communication 31 // (Oct. 2011). 32 // 33 // General branch target alignment considerations 34 // 35 // z/Architecture does not imply a general branch target alignment requirement. 36 // There are side effects and side considerations, though, which may 37 // provide some performance benefit. These are: 38 // - Align branch target on octoword (32-byte) boundary 39 // On more recent models (from z9 on), I-fetch is done on a Octoword 40 // (32 bytes at a time) basis. To avoid I-fetching unnecessary 41 // instructions, branch targets should be 32-byte aligend. If this 42 // exact alingment cannot be achieved, having the branch target in 43 // the first doubleword still provides some benefit. 44 // - Avoid branch targets at the end of cache lines (> 64 bytes distance). 45 // Sequential instruction prefetching after the branch target starts 46 // immediately after having fetched the octoword containing the 47 // branch target. When I-fetching crosses a cache line, there may be 48 // a small stall. The worst case: the branch target (at the end of 49 // a cache line) is a L1 I-cache miss and the next line as well. 50 // Then, the entire target line must be filled first (to contine at the 51 // branch target). Only then can the next sequential line be filled. 52 // - Avoid multiple poorly predicted branches in a row. 53 // 54 55 //----------REGISTER DEFINITION BLOCK------------------------------------------ 56 // This information is used by the matcher and the register allocator to 57 // describe individual registers and classes of registers within the target 58 // architecture. 59 60 register %{ 61 62 //----------Architecture Description Register Definitions---------------------- 63 // General Registers 64 // "reg_def" name (register save type, C convention save type, 65 // ideal register type, encoding); 66 // 67 // Register Save Types: 68 // 69 // NS = No-Save: The register allocator assumes that these registers 70 // can be used without saving upon entry to the method, & 71 // that they do not need to be saved at call sites. 72 // 73 // SOC = Save-On-Call: The register allocator assumes that these registers 74 // can be used without saving upon entry to the method, 75 // but that they must be saved at call sites. 76 // 77 // SOE = Save-On-Entry: The register allocator assumes that these registers 78 // must be saved before using them upon entry to the 79 // method, but they do not need to be saved at call sites. 80 // 81 // AS = Always-Save: The register allocator assumes that these registers 82 // must be saved before using them upon entry to the 83 // method, & that they must be saved at call sites. 84 // 85 // Ideal Register Type is used to determine how to save & restore a 86 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get 87 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI. 88 // 89 // The encoding number is the actual bit-pattern placed into the opcodes. 90 91 // z/Architecture register definitions, based on the z/Architecture Principles 92 // of Operation, 5th Edition, September 2005, and z/Linux Elf ABI Supplement, 93 // 5th Edition, March 2001. 94 // 95 // For each 64-bit register we must define two registers: the register 96 // itself, e.g. Z_R3, and a corresponding virtual other (32-bit-)'half', 97 // e.g. Z_R3_H, which is needed by the allocator, but is not used 98 // for stores, loads, etc. 99 100 // Integer/Long Registers 101 // ---------------------------- 102 103 // z/Architecture has 16 64-bit integer registers. 104 105 // types: v = volatile, nv = non-volatile, s = system 106 reg_def Z_R0 (SOC, SOC, Op_RegI, 0, Z_R0->as_VMReg()); // v scratch1 107 reg_def Z_R0_H (SOC, SOC, Op_RegI, 99, Z_R0->as_VMReg()->next()); 108 reg_def Z_R1 (SOC, SOC, Op_RegI, 1, Z_R1->as_VMReg()); // v scratch2 109 reg_def Z_R1_H (SOC, SOC, Op_RegI, 99, Z_R1->as_VMReg()->next()); 110 reg_def Z_R2 (SOC, SOC, Op_RegI, 2, Z_R2->as_VMReg()); // v iarg1 & iret 111 reg_def Z_R2_H (SOC, SOC, Op_RegI, 99, Z_R2->as_VMReg()->next()); 112 reg_def Z_R3 (SOC, SOC, Op_RegI, 3, Z_R3->as_VMReg()); // v iarg2 113 reg_def Z_R3_H (SOC, SOC, Op_RegI, 99, Z_R3->as_VMReg()->next()); 114 reg_def Z_R4 (SOC, SOC, Op_RegI, 4, Z_R4->as_VMReg()); // v iarg3 115 reg_def Z_R4_H (SOC, SOC, Op_RegI, 99, Z_R4->as_VMReg()->next()); 116 reg_def Z_R5 (SOC, SOC, Op_RegI, 5, Z_R5->as_VMReg()); // v iarg4 117 reg_def Z_R5_H (SOC, SOC, Op_RegI, 99, Z_R5->as_VMReg()->next()); 118 reg_def Z_R6 (SOC, SOE, Op_RegI, 6, Z_R6->as_VMReg()); // v iarg5 119 reg_def Z_R6_H (SOC, SOE, Op_RegI, 99, Z_R6->as_VMReg()->next()); 120 reg_def Z_R7 (SOC, SOE, Op_RegI, 7, Z_R7->as_VMReg()); 121 reg_def Z_R7_H (SOC, SOE, Op_RegI, 99, Z_R7->as_VMReg()->next()); 122 reg_def Z_R8 (SOC, SOE, Op_RegI, 8, Z_R8->as_VMReg()); 123 reg_def Z_R8_H (SOC, SOE, Op_RegI, 99, Z_R8->as_VMReg()->next()); 124 reg_def Z_R9 (SOC, SOE, Op_RegI, 9, Z_R9->as_VMReg()); 125 reg_def Z_R9_H (SOC, SOE, Op_RegI, 99, Z_R9->as_VMReg()->next()); 126 reg_def Z_R10 (SOC, SOE, Op_RegI, 10, Z_R10->as_VMReg()); 127 reg_def Z_R10_H(SOC, SOE, Op_RegI, 99, Z_R10->as_VMReg()->next()); 128 reg_def Z_R11 (SOC, SOE, Op_RegI, 11, Z_R11->as_VMReg()); 129 reg_def Z_R11_H(SOC, SOE, Op_RegI, 99, Z_R11->as_VMReg()->next()); 130 reg_def Z_R12 (SOC, SOE, Op_RegI, 12, Z_R12->as_VMReg()); 131 reg_def Z_R12_H(SOC, SOE, Op_RegI, 99, Z_R12->as_VMReg()->next()); 132 reg_def Z_R13 (SOC, SOE, Op_RegI, 13, Z_R13->as_VMReg()); 133 reg_def Z_R13_H(SOC, SOE, Op_RegI, 99, Z_R13->as_VMReg()->next()); 134 reg_def Z_R14 (NS, NS, Op_RegI, 14, Z_R14->as_VMReg()); // s return_pc 135 reg_def Z_R14_H(NS, NS, Op_RegI, 99, Z_R14->as_VMReg()->next()); 136 reg_def Z_R15 (NS, NS, Op_RegI, 15, Z_R15->as_VMReg()); // s SP 137 reg_def Z_R15_H(NS, NS, Op_RegI, 99, Z_R15->as_VMReg()->next()); 138 139 // Float/Double Registers 140 141 // The rules of ADL require that double registers be defined in pairs. 142 // Each pair must be two 32-bit values, but not necessarily a pair of 143 // single float registers. In each pair, ADLC-assigned register numbers 144 // must be adjacent, with the lower number even. Finally, when the 145 // CPU stores such a register pair to memory, the word associated with 146 // the lower ADLC-assigned number must be stored to the lower address. 147 148 // z/Architecture has 16 64-bit floating-point registers. Each can store a single 149 // or double precision floating-point value. 150 151 // types: v = volatile, nv = non-volatile, s = system 152 reg_def Z_F0 (SOC, SOC, Op_RegF, 0, Z_F0->as_VMReg()); // v farg1 & fret 153 reg_def Z_F0_H (SOC, SOC, Op_RegF, 99, Z_F0->as_VMReg()->next()); 154 reg_def Z_F1 (SOC, SOC, Op_RegF, 1, Z_F1->as_VMReg()); 155 reg_def Z_F1_H (SOC, SOC, Op_RegF, 99, Z_F1->as_VMReg()->next()); 156 reg_def Z_F2 (SOC, SOC, Op_RegF, 2, Z_F2->as_VMReg()); // v farg2 157 reg_def Z_F2_H (SOC, SOC, Op_RegF, 99, Z_F2->as_VMReg()->next()); 158 reg_def Z_F3 (SOC, SOC, Op_RegF, 3, Z_F3->as_VMReg()); 159 reg_def Z_F3_H (SOC, SOC, Op_RegF, 99, Z_F3->as_VMReg()->next()); 160 reg_def Z_F4 (SOC, SOC, Op_RegF, 4, Z_F4->as_VMReg()); // v farg3 161 reg_def Z_F4_H (SOC, SOC, Op_RegF, 99, Z_F4->as_VMReg()->next()); 162 reg_def Z_F5 (SOC, SOC, Op_RegF, 5, Z_F5->as_VMReg()); 163 reg_def Z_F5_H (SOC, SOC, Op_RegF, 99, Z_F5->as_VMReg()->next()); 164 reg_def Z_F6 (SOC, SOC, Op_RegF, 6, Z_F6->as_VMReg()); 165 reg_def Z_F6_H (SOC, SOC, Op_RegF, 99, Z_F6->as_VMReg()->next()); 166 reg_def Z_F7 (SOC, SOC, Op_RegF, 7, Z_F7->as_VMReg()); 167 reg_def Z_F7_H (SOC, SOC, Op_RegF, 99, Z_F7->as_VMReg()->next()); 168 reg_def Z_F8 (SOC, SOE, Op_RegF, 8, Z_F8->as_VMReg()); 169 reg_def Z_F8_H (SOC, SOE, Op_RegF, 99, Z_F8->as_VMReg()->next()); 170 reg_def Z_F9 (SOC, SOE, Op_RegF, 9, Z_F9->as_VMReg()); 171 reg_def Z_F9_H (SOC, SOE, Op_RegF, 99, Z_F9->as_VMReg()->next()); 172 reg_def Z_F10 (SOC, SOE, Op_RegF, 10, Z_F10->as_VMReg()); 173 reg_def Z_F10_H(SOC, SOE, Op_RegF, 99, Z_F10->as_VMReg()->next()); 174 reg_def Z_F11 (SOC, SOE, Op_RegF, 11, Z_F11->as_VMReg()); 175 reg_def Z_F11_H(SOC, SOE, Op_RegF, 99, Z_F11->as_VMReg()->next()); 176 reg_def Z_F12 (SOC, SOE, Op_RegF, 12, Z_F12->as_VMReg()); 177 reg_def Z_F12_H(SOC, SOE, Op_RegF, 99, Z_F12->as_VMReg()->next()); 178 reg_def Z_F13 (SOC, SOE, Op_RegF, 13, Z_F13->as_VMReg()); 179 reg_def Z_F13_H(SOC, SOE, Op_RegF, 99, Z_F13->as_VMReg()->next()); 180 reg_def Z_F14 (SOC, SOE, Op_RegF, 14, Z_F14->as_VMReg()); 181 reg_def Z_F14_H(SOC, SOE, Op_RegF, 99, Z_F14->as_VMReg()->next()); 182 reg_def Z_F15 (SOC, SOE, Op_RegF, 15, Z_F15->as_VMReg()); 183 reg_def Z_F15_H(SOC, SOE, Op_RegF, 99, Z_F15->as_VMReg()->next()); 184 185 186 // Special Registers 187 188 // Condition Codes Flag Registers 189 190 // z/Architecture has the PSW (program status word) that contains 191 // (among other information) the condition code. We treat this 192 // part of the PSW as a condition register CR. It consists of 4 193 // bits. Floating point instructions influence the same condition register CR. 194 195 reg_def Z_CR(SOC, SOC, Op_RegFlags, 0, Z_CR->as_VMReg()); // volatile 196 197 198 // Specify priority of register selection within phases of register 199 // allocation. Highest priority is first. A useful heuristic is to 200 // give registers a low priority when they are required by machine 201 // instructions, and choose no-save registers before save-on-call, and 202 // save-on-call before save-on-entry. Registers which participate in 203 // fix calling sequences should come last. Registers which are used 204 // as pairs must fall on an even boundary. 205 206 // It's worth about 1% on SPEC geomean to get this right. 207 208 // Chunk0, chunk1, and chunk2 form the MachRegisterNumbers enumeration 209 // in adGlobals_s390.hpp which defines the <register>_num values, e.g. 210 // Z_R3_num. Therefore, Z_R3_num may not be (and in reality is not) 211 // the same as Z_R3->encoding()! Furthermore, we cannot make any 212 // assumptions on ordering, e.g. Z_R3_num may be less than Z_R2_num. 213 // Additionally, the function 214 // static enum RC rc_class(OptoReg::Name reg) 215 // maps a given <register>_num value to its chunk type (except for flags) 216 // and its current implementation relies on chunk0 and chunk1 having a 217 // size of 64 each. 218 219 alloc_class chunk0( 220 // chunk0 contains *all* 32 integer registers halves. 221 222 // potential SOE regs 223 Z_R13,Z_R13_H, 224 Z_R12,Z_R12_H, 225 Z_R11,Z_R11_H, 226 Z_R10,Z_R10_H, 227 228 Z_R9,Z_R9_H, 229 Z_R8,Z_R8_H, 230 Z_R7,Z_R7_H, 231 232 Z_R1,Z_R1_H, 233 Z_R0,Z_R0_H, 234 235 // argument registers 236 Z_R6,Z_R6_H, 237 Z_R5,Z_R5_H, 238 Z_R4,Z_R4_H, 239 Z_R3,Z_R3_H, 240 Z_R2,Z_R2_H, 241 242 // special registers 243 Z_R14,Z_R14_H, 244 Z_R15,Z_R15_H 245 ); 246 247 alloc_class chunk1( 248 // Chunk1 contains *all* 64 floating-point registers halves. 249 250 Z_F15,Z_F15_H, 251 Z_F14,Z_F14_H, 252 Z_F13,Z_F13_H, 253 Z_F12,Z_F12_H, 254 Z_F11,Z_F11_H, 255 Z_F10,Z_F10_H, 256 Z_F9,Z_F9_H, 257 Z_F8,Z_F8_H, 258 // scratch register 259 Z_F7,Z_F7_H, 260 Z_F5,Z_F5_H, 261 Z_F3,Z_F3_H, 262 Z_F1,Z_F1_H, 263 // argument registers 264 Z_F6,Z_F6_H, 265 Z_F4,Z_F4_H, 266 Z_F2,Z_F2_H, 267 Z_F0,Z_F0_H 268 ); 269 270 alloc_class chunk2( 271 Z_CR 272 ); 273 274 275 //-------Architecture Description Register Classes----------------------- 276 277 // Several register classes are automatically defined based upon 278 // information in this architecture description. 279 280 // 1) reg_class inline_cache_reg (as defined in frame section) 281 // 2) reg_class compiler_method_oop_reg (as defined in frame section) 282 // 2) reg_class interpreter_method_oop_reg (as defined in frame section) 283 // 3) reg_class stack_slots(/* one chunk of stack-based "registers" */) 284 285 // Integer Register Classes 286 reg_class z_int_reg( 287 /*Z_R0*/ // R0 288 /*Z_R1*/ 289 Z_R2, 290 Z_R3, 291 Z_R4, 292 Z_R5, 293 Z_R6, 294 Z_R7, 295 /*Z_R8,*/ // Z_thread 296 Z_R9, 297 Z_R10, 298 Z_R11, 299 Z_R12, 300 Z_R13 301 /*Z_R14*/ // return_pc 302 /*Z_R15*/ // SP 303 ); 304 305 reg_class z_no_odd_int_reg( 306 /*Z_R0*/ // R0 307 /*Z_R1*/ 308 Z_R2, 309 Z_R3, 310 Z_R4, 311 /*Z_R5,*/ // odd part of fix register pair 312 Z_R6, 313 Z_R7, 314 /*Z_R8,*/ // Z_thread 315 Z_R9, 316 Z_R10, 317 Z_R11, 318 Z_R12, 319 Z_R13 320 /*Z_R14*/ // return_pc 321 /*Z_R15*/ // SP 322 ); 323 324 reg_class z_no_arg_int_reg( 325 /*Z_R0*/ // R0 326 /*Z_R1*/ // scratch 327 /*Z_R2*/ 328 /*Z_R3*/ 329 /*Z_R4*/ 330 /*Z_R5*/ 331 /*Z_R6*/ 332 Z_R7, 333 /*Z_R8*/ // Z_thread 334 Z_R9, 335 Z_R10, 336 Z_R11, 337 Z_R12, 338 Z_R13 339 /*Z_R14*/ // return_pc 340 /*Z_R15*/ // SP 341 ); 342 343 reg_class z_rarg1_int_reg(Z_R2); 344 reg_class z_rarg2_int_reg(Z_R3); 345 reg_class z_rarg3_int_reg(Z_R4); 346 reg_class z_rarg4_int_reg(Z_R5); 347 reg_class z_rarg5_int_reg(Z_R6); 348 349 // Pointer Register Classes 350 351 // 64-bit build means 64-bit pointers means hi/lo pairs. 352 353 reg_class z_rarg5_ptrN_reg(Z_R6); 354 355 reg_class z_rarg1_ptr_reg(Z_R2_H,Z_R2); 356 reg_class z_rarg2_ptr_reg(Z_R3_H,Z_R3); 357 reg_class z_rarg3_ptr_reg(Z_R4_H,Z_R4); 358 reg_class z_rarg4_ptr_reg(Z_R5_H,Z_R5); 359 reg_class z_rarg5_ptr_reg(Z_R6_H,Z_R6); 360 reg_class z_thread_ptr_reg(Z_R8_H,Z_R8); 361 362 reg_class z_ptr_reg( 363 /*Z_R0_H,Z_R0*/ // R0 364 /*Z_R1_H,Z_R1*/ 365 Z_R2_H,Z_R2, 366 Z_R3_H,Z_R3, 367 Z_R4_H,Z_R4, 368 Z_R5_H,Z_R5, 369 Z_R6_H,Z_R6, 370 Z_R7_H,Z_R7, 371 /*Z_R8_H,Z_R8,*/ // Z_thread 372 Z_R9_H,Z_R9, 373 Z_R10_H,Z_R10, 374 Z_R11_H,Z_R11, 375 Z_R12_H,Z_R12, 376 Z_R13_H,Z_R13 377 /*Z_R14_H,Z_R14*/ // return_pc 378 /*Z_R15_H,Z_R15*/ // SP 379 ); 380 381 reg_class z_lock_ptr_reg( 382 /*Z_R0_H,Z_R0*/ // R0 383 /*Z_R1_H,Z_R1*/ 384 Z_R2_H,Z_R2, 385 Z_R3_H,Z_R3, 386 Z_R4_H,Z_R4, 387 /*Z_R5_H,Z_R5,*/ 388 /*Z_R6_H,Z_R6,*/ 389 Z_R7_H,Z_R7, 390 /*Z_R8_H,Z_R8,*/ // Z_thread 391 Z_R9_H,Z_R9, 392 Z_R10_H,Z_R10, 393 Z_R11_H,Z_R11, 394 Z_R12_H,Z_R12, 395 Z_R13_H,Z_R13 396 /*Z_R14_H,Z_R14*/ // return_pc 397 /*Z_R15_H,Z_R15*/ // SP 398 ); 399 400 reg_class z_no_arg_ptr_reg( 401 /*Z_R0_H,Z_R0*/ // R0 402 /*Z_R1_H,Z_R1*/ // scratch 403 /*Z_R2_H,Z_R2*/ 404 /*Z_R3_H,Z_R3*/ 405 /*Z_R4_H,Z_R4*/ 406 /*Z_R5_H,Z_R5*/ 407 /*Z_R6_H,Z_R6*/ 408 Z_R7_H, Z_R7, 409 /*Z_R8_H,Z_R8*/ // Z_thread 410 Z_R9_H,Z_R9, 411 Z_R10_H,Z_R10, 412 Z_R11_H,Z_R11, 413 Z_R12_H,Z_R12, 414 Z_R13_H,Z_R13 415 /*Z_R14_H,Z_R14*/ // return_pc 416 /*Z_R15_H,Z_R15*/ // SP 417 ); 418 419 // Special class for storeP instructions, which can store SP or RPC to 420 // TLS. (Note: Do not generalize this to "any_reg". If you add 421 // another register, such as FP, to this mask, the allocator may try 422 // to put a temp in it.) 423 // Register class for memory access base registers, 424 // This class is a superset of z_ptr_reg including Z_thread. 425 reg_class z_memory_ptr_reg( 426 /*Z_R0_H,Z_R0*/ // R0 427 /*Z_R1_H,Z_R1*/ 428 Z_R2_H,Z_R2, 429 Z_R3_H,Z_R3, 430 Z_R4_H,Z_R4, 431 Z_R5_H,Z_R5, 432 Z_R6_H,Z_R6, 433 Z_R7_H,Z_R7, 434 Z_R8_H,Z_R8, // Z_thread 435 Z_R9_H,Z_R9, 436 Z_R10_H,Z_R10, 437 Z_R11_H,Z_R11, 438 Z_R12_H,Z_R12, 439 Z_R13_H,Z_R13 440 /*Z_R14_H,Z_R14*/ // return_pc 441 /*Z_R15_H,Z_R15*/ // SP 442 ); 443 444 // Other special pointer regs. 445 reg_class z_r1_regP(Z_R1_H,Z_R1); 446 reg_class z_r9_regP(Z_R9_H,Z_R9); 447 448 449 // Long Register Classes 450 451 reg_class z_rarg1_long_reg(Z_R2_H,Z_R2); 452 reg_class z_rarg2_long_reg(Z_R3_H,Z_R3); 453 reg_class z_rarg3_long_reg(Z_R4_H,Z_R4); 454 reg_class z_rarg4_long_reg(Z_R5_H,Z_R5); 455 reg_class z_rarg5_long_reg(Z_R6_H,Z_R6); 456 457 // Longs in 1 register. Aligned adjacent hi/lo pairs. 458 reg_class z_long_reg( 459 /*Z_R0_H,Z_R0*/ // R0 460 /*Z_R1_H,Z_R1*/ 461 Z_R2_H,Z_R2, 462 Z_R3_H,Z_R3, 463 Z_R4_H,Z_R4, 464 Z_R5_H,Z_R5, 465 Z_R6_H,Z_R6, 466 Z_R7_H,Z_R7, 467 /*Z_R8_H,Z_R8,*/ // Z_thread 468 Z_R9_H,Z_R9, 469 Z_R10_H,Z_R10, 470 Z_R11_H,Z_R11, 471 Z_R12_H,Z_R12, 472 Z_R13_H,Z_R13 473 /*Z_R14_H,Z_R14,*/ // return_pc 474 /*Z_R15_H,Z_R15*/ // SP 475 ); 476 477 // z_long_reg without even registers 478 reg_class z_long_odd_reg( 479 /*Z_R0_H,Z_R0*/ // R0 480 /*Z_R1_H,Z_R1*/ 481 Z_R3_H,Z_R3, 482 Z_R5_H,Z_R5, 483 Z_R7_H,Z_R7, 484 Z_R9_H,Z_R9, 485 Z_R11_H,Z_R11, 486 Z_R13_H,Z_R13 487 /*Z_R14_H,Z_R14,*/ // return_pc 488 /*Z_R15_H,Z_R15*/ // SP 489 ); 490 491 // Special Class for Condition Code Flags Register 492 493 reg_class z_condition_reg( 494 Z_CR 495 ); 496 497 // Scratch register for late profiling. Callee saved. 498 reg_class z_rscratch2_bits64_reg(Z_R2_H, Z_R2); 499 500 501 // Float Register Classes 502 503 reg_class z_flt_reg( 504 Z_F0, 505 /*Z_F1,*/ // scratch 506 Z_F2, 507 Z_F3, 508 Z_F4, 509 Z_F5, 510 Z_F6, 511 Z_F7, 512 Z_F8, 513 Z_F9, 514 Z_F10, 515 Z_F11, 516 Z_F12, 517 Z_F13, 518 Z_F14, 519 Z_F15 520 ); 521 reg_class z_rscratch1_flt_reg(Z_F1); 522 523 // Double precision float registers have virtual `high halves' that 524 // are needed by the allocator. 525 reg_class z_dbl_reg( 526 Z_F0,Z_F0_H, 527 /*Z_F1,Z_F1_H,*/ // scratch 528 Z_F2,Z_F2_H, 529 Z_F3,Z_F3_H, 530 Z_F4,Z_F4_H, 531 Z_F5,Z_F5_H, 532 Z_F6,Z_F6_H, 533 Z_F7,Z_F7_H, 534 Z_F8,Z_F8_H, 535 Z_F9,Z_F9_H, 536 Z_F10,Z_F10_H, 537 Z_F11,Z_F11_H, 538 Z_F12,Z_F12_H, 539 Z_F13,Z_F13_H, 540 Z_F14,Z_F14_H, 541 Z_F15,Z_F15_H 542 ); 543 reg_class z_rscratch1_dbl_reg(Z_F1,Z_F1_H); 544 545 %} 546 547 //----------DEFINITION BLOCK--------------------------------------------------- 548 // Define 'name --> value' mappings to inform the ADLC of an integer valued name. 549 // Current support includes integer values in the range [0, 0x7FFFFFFF]. 550 // Format: 551 // int_def <name> (<int_value>, <expression>); 552 // Generated Code in ad_<arch>.hpp 553 // #define <name> (<expression>) 554 // // value == <int_value> 555 // Generated code in ad_<arch>.cpp adlc_verification() 556 // assert(<name> == <int_value>, "Expect (<expression>) to equal <int_value>"); 557 // 558 definitions %{ 559 // The default cost (of an ALU instruction). 560 int_def DEFAULT_COST ( 100, 100); 561 int_def DEFAULT_COST_LOW ( 80, 80); 562 int_def DEFAULT_COST_HIGH ( 120, 120); 563 int_def HUGE_COST (1000000, 1000000); 564 565 // Put an advantage on REG_MEM vs. MEM+REG_REG operations. 566 int_def ALU_REG_COST ( 100, DEFAULT_COST); 567 int_def ALU_MEMORY_COST ( 150, 150); 568 569 // Memory refs are twice as expensive as run-of-the-mill. 570 int_def MEMORY_REF_COST_HI ( 220, 2 * DEFAULT_COST+20); 571 int_def MEMORY_REF_COST ( 200, 2 * DEFAULT_COST); 572 int_def MEMORY_REF_COST_LO ( 180, 2 * DEFAULT_COST-20); 573 574 // Branches are even more expensive. 575 int_def BRANCH_COST ( 300, DEFAULT_COST * 3); 576 int_def CALL_COST ( 300, DEFAULT_COST * 3); 577 %} 578 579 source %{ 580 581 #ifdef PRODUCT 582 #define BLOCK_COMMENT(str) 583 #define BIND(label) __ bind(label) 584 #else 585 #define BLOCK_COMMENT(str) __ block_comment(str) 586 #define BIND(label) __ bind(label); BLOCK_COMMENT(#label ":") 587 #endif 588 589 #define __ _masm. 590 591 #define Z_DISP_SIZE Immediate::is_uimm12((long)opnd_array(1)->disp(ra_,this,2)) ? 4 : 6 592 #define Z_DISP3_SIZE 6 593 594 // Tertiary op of a LoadP or StoreP encoding. 595 #define REGP_OP true 596 597 // Given a register encoding, produce an Integer Register object. 598 static Register reg_to_register_object(int register_encoding); 599 600 // **************************************************************************** 601 602 // REQUIRED FUNCTIONALITY 603 604 // !!!!! Special hack to get all type of calls to specify the byte offset 605 // from the start of the call to the point where the return address 606 // will point. 607 608 void PhaseOutput::pd_perform_mach_node_analysis() { 609 } 610 611 int MachNode::pd_alignment_required() const { 612 return 1; 613 } 614 615 int MachNode::compute_padding(int current_offset) const { 616 return 0; 617 } 618 619 int MachCallStaticJavaNode::ret_addr_offset() { 620 if (_method) { 621 return 8; 622 } else { 623 return MacroAssembler::call_far_patchable_ret_addr_offset(); 624 } 625 } 626 627 int MachCallDynamicJavaNode::ret_addr_offset() { 628 // Consider size of receiver type profiling (C2 tiers). 629 int profile_receiver_type_size = 0; 630 631 int vtable_index = this->_vtable_index; 632 if (vtable_index == -4) { 633 return 14 + profile_receiver_type_size; 634 } else { 635 assert(!UseInlineCaches, "expect vtable calls only if not using ICs"); 636 return 36 + profile_receiver_type_size; 637 } 638 } 639 640 int MachCallRuntimeNode::ret_addr_offset() { 641 return 12 + MacroAssembler::call_far_patchable_ret_addr_offset(); 642 } 643 644 // Compute padding required for nodes which need alignment 645 // 646 // The addresses of the call instructions needs to be 4-byte aligned to 647 // ensure that they don't span a cache line so that they are atomically patchable. 648 // The actual calls get emitted at different offsets within the node emitters. 649 // ins_alignment needs to be set to 2 which means that up to 1 nop may get inserted. 650 651 int CallStaticJavaDirect_dynTOCNode::compute_padding(int current_offset) const { 652 return (0 - current_offset) & 2; 653 } 654 655 int CallDynamicJavaDirect_dynTOCNode::compute_padding(int current_offset) const { 656 return (6 - current_offset) & 2; 657 } 658 659 int CallRuntimeDirectNode::compute_padding(int current_offset) const { 660 return (12 - current_offset) & 2; 661 } 662 663 int CallLeafDirectNode::compute_padding(int current_offset) const { 664 return (12 - current_offset) & 2; 665 } 666 667 int CallLeafNoFPDirectNode::compute_padding(int current_offset) const { 668 return (12 - current_offset) & 2; 669 } 670 671 // Indicate if the safepoint node needs the polling page as an input. 672 // Since z/Architecture does not have absolute addressing, it does. 673 bool SafePointNode::needs_polling_address_input() { 674 return true; 675 } 676 677 void emit_nop(CodeBuffer &cbuf) { 678 C2_MacroAssembler _masm(&cbuf); 679 __ z_nop(); 680 } 681 682 // Emit an interrupt that is caught by the debugger (for debugging compiler). 683 void emit_break(CodeBuffer &cbuf) { 684 C2_MacroAssembler _masm(&cbuf); 685 __ z_illtrap(); 686 } 687 688 #if !defined(PRODUCT) 689 void MachBreakpointNode::format(PhaseRegAlloc *, outputStream *os) const { 690 os->print("TA"); 691 } 692 #endif 693 694 void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 695 emit_break(cbuf); 696 } 697 698 uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const { 699 return MachNode::size(ra_); 700 } 701 702 static inline void z_emit16(CodeBuffer &cbuf, long value) { 703 // 32bit instructions may become sign extended. 704 assert(value >= 0, "unintended sign extension (int->long)"); 705 assert(value < (1L << 16), "instruction too large"); 706 *((unsigned short*)(cbuf.insts_end())) = (unsigned short)value; 707 cbuf.set_insts_end(cbuf.insts_end() + sizeof(unsigned short)); 708 } 709 710 static inline void z_emit32(CodeBuffer &cbuf, long value) { 711 // 32bit instructions may become sign extended. 712 assert(value < (1L << 32), "instruction too large"); 713 *((unsigned int*)(cbuf.insts_end())) = (unsigned int)value; 714 cbuf.set_insts_end(cbuf.insts_end() + sizeof(unsigned int)); 715 } 716 717 static inline void z_emit48(CodeBuffer &cbuf, long value) { 718 // 32bit instructions may become sign extended. 719 assert(value >= 0, "unintended sign extension (int->long)"); 720 assert(value < (1L << 48), "instruction too large"); 721 value = value<<16; 722 memcpy(cbuf.insts_end(), (unsigned char*)&value, 6); 723 cbuf.set_insts_end(cbuf.insts_end() + 6); 724 } 725 726 static inline unsigned int z_emit_inst(CodeBuffer &cbuf, long value) { 727 if (value < 0) { 728 // There obviously has been an unintended sign extension (int->long). Revert it. 729 value = (long)((unsigned long)((unsigned int)value)); 730 } 731 732 if (value < (1L << 16)) { // 2-byte instruction 733 z_emit16(cbuf, value); 734 return 2; 735 } 736 737 if (value < (1L << 32)) { // 4-byte instruction, might be unaligned store 738 z_emit32(cbuf, value); 739 return 4; 740 } 741 742 // 6-byte instruction, probably unaligned store. 743 z_emit48(cbuf, value); 744 return 6; 745 } 746 747 // Check effective address (at runtime) for required alignment. 748 static inline void z_assert_aligned(CodeBuffer &cbuf, int disp, Register index, Register base, int alignment) { 749 C2_MacroAssembler _masm(&cbuf); 750 751 __ z_lay(Z_R0, disp, index, base); 752 __ z_nill(Z_R0, alignment-1); 753 __ z_brc(Assembler::bcondEqual, +3); 754 __ z_illtrap(); 755 } 756 757 int emit_call_reloc(C2_MacroAssembler &_masm, intptr_t entry_point, relocInfo::relocType rtype, 758 PhaseRegAlloc* ra_, bool is_native_call = false) { 759 __ set_inst_mark(); // Used in z_enc_java_static_call() and emit_java_to_interp(). 760 address old_mark = __ inst_mark(); 761 unsigned int start_off = __ offset(); 762 763 if (is_native_call) { 764 ShouldNotReachHere(); 765 } 766 767 if (rtype == relocInfo::runtime_call_w_cp_type) { 768 assert((__ offset() & 2) == 0, "misaligned emit_call_reloc"); 769 address call_addr = __ call_c_opt((address)entry_point); 770 if (call_addr == NULL) { 771 Compile::current()->env()->record_out_of_memory_failure(); 772 return -1; 773 } 774 } else { 775 assert(rtype == relocInfo::none || rtype == relocInfo::opt_virtual_call_type || 776 rtype == relocInfo::static_call_type, "unexpected rtype"); 777 __ relocate(rtype); 778 // BRASL must be prepended with a nop to identify it in the instruction stream. 779 __ z_nop(); 780 __ z_brasl(Z_R14, (address)entry_point); 781 } 782 783 unsigned int ret_off = __ offset(); 784 785 return (ret_off - start_off); 786 } 787 788 static int emit_call_reloc(C2_MacroAssembler &_masm, intptr_t entry_point, RelocationHolder const& rspec) { 789 __ set_inst_mark(); // Used in z_enc_java_static_call() and emit_java_to_interp(). 790 address old_mark = __ inst_mark(); 791 unsigned int start_off = __ offset(); 792 793 relocInfo::relocType rtype = rspec.type(); 794 assert(rtype == relocInfo::opt_virtual_call_type || rtype == relocInfo::static_call_type, 795 "unexpected rtype"); 796 797 __ relocate(rspec); 798 __ z_nop(); 799 __ z_brasl(Z_R14, (address)entry_point); 800 801 unsigned int ret_off = __ offset(); 802 803 return (ret_off - start_off); 804 } 805 806 //============================================================================= 807 808 const RegMask& MachConstantBaseNode::_out_RegMask = _Z_PTR_REG_mask; 809 int ConstantTable::calculate_table_base_offset() const { 810 return 0; // absolute addressing, no offset 811 } 812 813 bool MachConstantBaseNode::requires_postalloc_expand() const { return false; } 814 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) { 815 ShouldNotReachHere(); 816 } 817 818 // Even with PC-relative TOC addressing, we still need this node. 819 // Float loads/stores do not support PC-relative addresses. 820 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const { 821 C2_MacroAssembler _masm(&cbuf); 822 Register Rtoc = as_Register(ra_->get_encode(this)); 823 __ load_toc(Rtoc); 824 } 825 826 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const { 827 // PCrelative TOC access. 828 return 6; // sizeof(LARL) 829 } 830 831 #if !defined(PRODUCT) 832 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const { 833 Register r = as_Register(ra_->get_encode(this)); 834 st->print("LARL %s,&constant_pool # MachConstantBaseNode", r->name()); 835 } 836 #endif 837 838 //============================================================================= 839 840 #if !defined(PRODUCT) 841 void MachPrologNode::format(PhaseRegAlloc *ra_, outputStream *st) const { 842 Compile* C = ra_->C; 843 st->print_cr("--- MachPrologNode ---"); 844 st->print("\t"); 845 for (int i = 0; i < OptoPrologueNops; i++) { 846 st->print_cr("NOP"); st->print("\t"); 847 } 848 849 if (VerifyThread) { 850 st->print_cr("Verify_Thread"); 851 st->print("\t"); 852 } 853 854 long framesize = C->output()->frame_size_in_bytes(); 855 int bangsize = C->output()->bang_size_in_bytes(); 856 857 // Calls to C2R adapters often do not accept exceptional returns. 858 // We require that their callers must bang for them. But be 859 // careful, because some VM calls (such as call site linkage) can 860 // use several kilobytes of stack. But the stack safety zone should 861 // account for that. See bugs 4446381, 4468289, 4497237. 862 if (C->output()->need_stack_bang(bangsize) && UseStackBanging) { 863 st->print_cr("# stack bang"); st->print("\t"); 864 } 865 st->print_cr("push_frame %d", (int)-framesize); 866 st->print("\t"); 867 } 868 #endif 869 870 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 871 Compile* C = ra_->C; 872 C2_MacroAssembler _masm(&cbuf); 873 874 __ verify_thread(); 875 876 size_t framesize = C->output()->frame_size_in_bytes(); 877 size_t bangsize = C->output()->bang_size_in_bytes(); 878 879 assert(framesize % wordSize == 0, "must preserve wordSize alignment"); 880 881 if (C->clinit_barrier_on_entry()) { 882 assert(!C->method()->holder()->is_not_initialized(), "initialization should have been started"); 883 884 Label L_skip_barrier; 885 Register klass = Z_R1_scratch; 886 887 // Notify OOP recorder (don't need the relocation) 888 AddressLiteral md = __ constant_metadata_address(C->method()->holder()->constant_encoding()); 889 __ load_const_optimized(klass, md.value()); 890 __ clinit_barrier(klass, Z_thread, &L_skip_barrier /*L_fast_path*/); 891 892 __ load_const_optimized(klass, SharedRuntime::get_handle_wrong_method_stub()); 893 __ z_br(klass); 894 895 __ bind(L_skip_barrier); 896 } 897 898 // Calls to C2R adapters often do not accept exceptional returns. 899 // We require that their callers must bang for them. But be 900 // careful, because some VM calls (such as call site linkage) can 901 // use several kilobytes of stack. But the stack safety zone should 902 // account for that. See bugs 4446381, 4468289, 4497237. 903 if (C->output()->need_stack_bang(bangsize) && UseStackBanging) { 904 __ generate_stack_overflow_check(bangsize); 905 } 906 907 assert(Immediate::is_uimm32((long)framesize), "to do: choose suitable types!"); 908 __ save_return_pc(); 909 910 // The z/Architecture abi is already accounted for in `framesize' via the 911 // 'out_preserve_stack_slots' declaration. 912 __ push_frame((unsigned int)framesize/*includes JIT ABI*/); 913 914 if (C->has_mach_constant_base_node()) { 915 // NOTE: We set the table base offset here because users might be 916 // emitted before MachConstantBaseNode. 917 ConstantTable& constant_table = C->output()->constant_table(); 918 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset()); 919 } 920 } 921 922 uint MachPrologNode::size(PhaseRegAlloc *ra_) const { 923 // Variable size. Determine dynamically. 924 return MachNode::size(ra_); 925 } 926 927 int MachPrologNode::reloc() const { 928 // Return number of relocatable values contained in this instruction. 929 return 1; // One reloc entry for load_const(toc). 930 } 931 932 //============================================================================= 933 934 #if !defined(PRODUCT) 935 void MachEpilogNode::format(PhaseRegAlloc *ra_, outputStream *os) const { 936 os->print_cr("epilog"); 937 os->print("\t"); 938 if (do_polling() && ra_->C->is_method_compilation()) { 939 os->print_cr("load_from_polling_page Z_R1_scratch"); 940 os->print("\t"); 941 } 942 } 943 #endif 944 945 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 946 C2_MacroAssembler _masm(&cbuf); 947 Compile* C = ra_->C; 948 __ verify_thread(); 949 950 // If this does safepoint polling, then do it here. 951 bool need_polling = do_polling() && C->is_method_compilation(); 952 953 // Pop frame, restore return_pc, and all stuff needed by interpreter. 954 int frame_size_in_bytes = Assembler::align((C->output()->frame_slots() << LogBytesPerInt), frame::alignment_in_bytes); 955 __ pop_frame_restore_retPC(frame_size_in_bytes); 956 957 if (StackReservedPages > 0 && C->has_reserved_stack_access()) { 958 __ reserved_stack_check(Z_R14); 959 } 960 961 // Touch the polling page. 962 if (need_polling) { 963 __ z_lg(Z_R1_scratch, Address(Z_thread, Thread::polling_page_offset())); 964 // We need to mark the code position where the load from the safepoint 965 // polling page was emitted as relocInfo::poll_return_type here. 966 __ relocate(relocInfo::poll_return_type); 967 __ load_from_polling_page(Z_R1_scratch); 968 } 969 } 970 971 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const { 972 // Variable size. determine dynamically. 973 return MachNode::size(ra_); 974 } 975 976 int MachEpilogNode::reloc() const { 977 // Return number of relocatable values contained in this instruction. 978 return 1; // One for load_from_polling_page. 979 } 980 981 const Pipeline * MachEpilogNode::pipeline() const { 982 return MachNode::pipeline_class(); 983 } 984 985 //============================================================================= 986 987 // Figure out which register class each belongs in: rc_int, rc_float, rc_stack. 988 enum RC { rc_bad, rc_int, rc_float, rc_stack }; 989 990 static enum RC rc_class(OptoReg::Name reg) { 991 // Return the register class for the given register. The given register 992 // reg is a <register>_num value, which is an index into the MachRegisterNumbers 993 // enumeration in adGlobals_s390.hpp. 994 995 if (reg == OptoReg::Bad) { 996 return rc_bad; 997 } 998 999 // We have 32 integer register halves, starting at index 0. 1000 if (reg < 32) { 1001 return rc_int; 1002 } 1003 1004 // We have 32 floating-point register halves, starting at index 32. 1005 if (reg < 32+32) { 1006 return rc_float; 1007 } 1008 1009 // Between float regs & stack are the flags regs. 1010 assert(reg >= OptoReg::stack0(), "blow up if spilling flags"); 1011 return rc_stack; 1012 } 1013 1014 // Returns size as obtained from z_emit_instr. 1015 static unsigned int z_ld_st_helper(CodeBuffer *cbuf, const char *op_str, unsigned long opcode, 1016 int reg, int offset, bool do_print, outputStream *os) { 1017 1018 if (cbuf) { 1019 if (opcode > (1L<<32)) { 1020 return z_emit_inst(*cbuf, opcode | Assembler::reg(Matcher::_regEncode[reg], 8, 48) | 1021 Assembler::simm20(offset) | Assembler::reg(Z_R0, 12, 48) | Assembler::regz(Z_SP, 16, 48)); 1022 } else { 1023 return z_emit_inst(*cbuf, opcode | Assembler::reg(Matcher::_regEncode[reg], 8, 32) | 1024 Assembler::uimm12(offset, 20, 32) | Assembler::reg(Z_R0, 12, 32) | Assembler::regz(Z_SP, 16, 32)); 1025 } 1026 } 1027 1028 #if !defined(PRODUCT) 1029 if (do_print) { 1030 os->print("%s %s,#%d[,SP]\t # MachCopy spill code",op_str, Matcher::regName[reg], offset); 1031 } 1032 #endif 1033 return (opcode > (1L << 32)) ? 6 : 4; 1034 } 1035 1036 static unsigned int z_mvc_helper(CodeBuffer *cbuf, int len, int dst_off, int src_off, bool do_print, outputStream *os) { 1037 if (cbuf) { 1038 C2_MacroAssembler _masm(cbuf); 1039 __ z_mvc(dst_off, len-1, Z_SP, src_off, Z_SP); 1040 } 1041 1042 #if !defined(PRODUCT) 1043 else if (do_print) { 1044 os->print("MVC %d(%d,SP),%d(SP)\t # MachCopy spill code",dst_off, len, src_off); 1045 } 1046 #endif 1047 1048 return 6; 1049 } 1050 1051 uint MachSpillCopyNode::implementation(CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, outputStream *os) const { 1052 // Get registers to move. 1053 OptoReg::Name src_hi = ra_->get_reg_second(in(1)); 1054 OptoReg::Name src_lo = ra_->get_reg_first(in(1)); 1055 OptoReg::Name dst_hi = ra_->get_reg_second(this); 1056 OptoReg::Name dst_lo = ra_->get_reg_first(this); 1057 1058 enum RC src_hi_rc = rc_class(src_hi); 1059 enum RC src_lo_rc = rc_class(src_lo); 1060 enum RC dst_hi_rc = rc_class(dst_hi); 1061 enum RC dst_lo_rc = rc_class(dst_lo); 1062 1063 assert(src_lo != OptoReg::Bad && dst_lo != OptoReg::Bad, "must move at least 1 register"); 1064 bool is64 = (src_hi_rc != rc_bad); 1065 assert(!is64 || 1066 ((src_lo&1) == 0 && src_lo+1 == src_hi && (dst_lo&1) == 0 && dst_lo+1 == dst_hi), 1067 "expected aligned-adjacent pairs"); 1068 1069 // Generate spill code! 1070 1071 if (src_lo == dst_lo && src_hi == dst_hi) { 1072 return 0; // Self copy, no move. 1073 } 1074 1075 int src_offset = ra_->reg2offset(src_lo); 1076 int dst_offset = ra_->reg2offset(dst_lo); 1077 bool print = !do_size; 1078 bool src12 = Immediate::is_uimm12(src_offset); 1079 bool dst12 = Immediate::is_uimm12(dst_offset); 1080 1081 const char *mnemo = NULL; 1082 unsigned long opc = 0; 1083 1084 // Memory->Memory Spill. Use Z_R0 to hold the value. 1085 if (src_lo_rc == rc_stack && dst_lo_rc == rc_stack) { 1086 1087 assert(!is64 || (src_hi_rc==rc_stack && dst_hi_rc==rc_stack), 1088 "expected same type of move for high parts"); 1089 1090 if (src12 && dst12) { 1091 return z_mvc_helper(cbuf, is64 ? 8 : 4, dst_offset, src_offset, print, os); 1092 } 1093 1094 int r0 = Z_R0_num; 1095 if (is64) { 1096 return z_ld_st_helper(cbuf, "LG ", LG_ZOPC, r0, src_offset, print, os) + 1097 z_ld_st_helper(cbuf, "STG ", STG_ZOPC, r0, dst_offset, print, os); 1098 } 1099 1100 return z_ld_st_helper(cbuf, "LY ", LY_ZOPC, r0, src_offset, print, os) + 1101 z_ld_st_helper(cbuf, "STY ", STY_ZOPC, r0, dst_offset, print, os); 1102 } 1103 1104 // Check for float->int copy. Requires a trip through memory. 1105 if (src_lo_rc == rc_float && dst_lo_rc == rc_int) { 1106 Unimplemented(); // Unsafe, do not remove! 1107 } 1108 1109 // Check for integer reg-reg copy. 1110 if (src_lo_rc == rc_int && dst_lo_rc == rc_int) { 1111 if (cbuf) { 1112 C2_MacroAssembler _masm(cbuf); 1113 Register Rsrc = as_Register(Matcher::_regEncode[src_lo]); 1114 Register Rdst = as_Register(Matcher::_regEncode[dst_lo]); 1115 __ z_lgr(Rdst, Rsrc); 1116 return 4; 1117 } 1118 #if !defined(PRODUCT) 1119 // else 1120 if (print) { 1121 os->print("LGR %s,%s\t # MachCopy spill code", Matcher::regName[dst_lo], Matcher::regName[src_lo]); 1122 } 1123 #endif 1124 return 4; 1125 } 1126 1127 // Check for integer store. 1128 if (src_lo_rc == rc_int && dst_lo_rc == rc_stack) { 1129 assert(!is64 || (src_hi_rc==rc_int && dst_hi_rc==rc_stack), 1130 "expected same type of move for high parts"); 1131 1132 if (is64) { 1133 return z_ld_st_helper(cbuf, "STG ", STG_ZOPC, src_lo, dst_offset, print, os); 1134 } 1135 1136 // else 1137 mnemo = dst12 ? "ST " : "STY "; 1138 opc = dst12 ? ST_ZOPC : STY_ZOPC; 1139 1140 return z_ld_st_helper(cbuf, mnemo, opc, src_lo, dst_offset, print, os); 1141 } 1142 1143 // Check for integer load 1144 // Always load cOops zero-extended. That doesn't hurt int loads. 1145 if (dst_lo_rc == rc_int && src_lo_rc == rc_stack) { 1146 1147 assert(!is64 || (dst_hi_rc==rc_int && src_hi_rc==rc_stack), 1148 "expected same type of move for high parts"); 1149 1150 mnemo = is64 ? "LG " : "LLGF"; 1151 opc = is64 ? LG_ZOPC : LLGF_ZOPC; 1152 1153 return z_ld_st_helper(cbuf, mnemo, opc, dst_lo, src_offset, print, os); 1154 } 1155 1156 // Check for float reg-reg copy. 1157 if (src_lo_rc == rc_float && dst_lo_rc == rc_float) { 1158 if (cbuf) { 1159 C2_MacroAssembler _masm(cbuf); 1160 FloatRegister Rsrc = as_FloatRegister(Matcher::_regEncode[src_lo]); 1161 FloatRegister Rdst = as_FloatRegister(Matcher::_regEncode[dst_lo]); 1162 __ z_ldr(Rdst, Rsrc); 1163 return 2; 1164 } 1165 #if !defined(PRODUCT) 1166 // else 1167 if (print) { 1168 os->print("LDR %s,%s\t # MachCopy spill code", Matcher::regName[dst_lo], Matcher::regName[src_lo]); 1169 } 1170 #endif 1171 return 2; 1172 } 1173 1174 // Check for float store. 1175 if (src_lo_rc == rc_float && dst_lo_rc == rc_stack) { 1176 assert(!is64 || (src_hi_rc==rc_float && dst_hi_rc==rc_stack), 1177 "expected same type of move for high parts"); 1178 1179 if (is64) { 1180 mnemo = dst12 ? "STD " : "STDY "; 1181 opc = dst12 ? STD_ZOPC : STDY_ZOPC; 1182 return z_ld_st_helper(cbuf, mnemo, opc, src_lo, dst_offset, print, os); 1183 } 1184 // else 1185 1186 mnemo = dst12 ? "STE " : "STEY "; 1187 opc = dst12 ? STE_ZOPC : STEY_ZOPC; 1188 return z_ld_st_helper(cbuf, mnemo, opc, src_lo, dst_offset, print, os); 1189 } 1190 1191 // Check for float load. 1192 if (dst_lo_rc == rc_float && src_lo_rc == rc_stack) { 1193 assert(!is64 || (dst_hi_rc==rc_float && src_hi_rc==rc_stack), 1194 "expected same type of move for high parts"); 1195 1196 if (is64) { 1197 mnemo = src12 ? "LD " : "LDY "; 1198 opc = src12 ? LD_ZOPC : LDY_ZOPC; 1199 return z_ld_st_helper(cbuf, mnemo, opc, dst_lo, src_offset, print, os); 1200 } 1201 // else 1202 1203 mnemo = src12 ? "LE " : "LEY "; 1204 opc = src12 ? LE_ZOPC : LEY_ZOPC; 1205 return z_ld_st_helper(cbuf, mnemo, opc, dst_lo, src_offset, print, os); 1206 } 1207 1208 // -------------------------------------------------------------------- 1209 // Check for hi bits still needing moving. Only happens for misaligned 1210 // arguments to native calls. 1211 if (src_hi == dst_hi) { 1212 return 0; // Self copy, no move. 1213 } 1214 1215 assert(is64 && dst_hi_rc != rc_bad, "src_hi & dst_hi cannot be Bad"); 1216 Unimplemented(); // Unsafe, do not remove! 1217 1218 return 0; // never reached, but make the compiler shut up! 1219 } 1220 1221 #if !defined(PRODUCT) 1222 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream *os) const { 1223 if (ra_ && ra_->node_regs_max_index() > 0) { 1224 implementation(NULL, ra_, false, os); 1225 } else { 1226 if (req() == 2 && in(1)) { 1227 os->print("N%d = N%d\n", _idx, in(1)->_idx); 1228 } else { 1229 const char *c = "("; 1230 os->print("N%d = ", _idx); 1231 for (uint i = 1; i < req(); ++i) { 1232 os->print("%sN%d", c, in(i)->_idx); 1233 c = ", "; 1234 } 1235 os->print(")"); 1236 } 1237 } 1238 } 1239 #endif 1240 1241 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 1242 implementation(&cbuf, ra_, false, NULL); 1243 } 1244 1245 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const { 1246 return implementation(NULL, ra_, true, NULL); 1247 } 1248 1249 //============================================================================= 1250 1251 #if !defined(PRODUCT) 1252 void MachNopNode::format(PhaseRegAlloc *, outputStream *os) const { 1253 os->print("NOP # pad for alignment (%d nops, %d bytes)", _count, _count*MacroAssembler::nop_size()); 1254 } 1255 #endif 1256 1257 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc * ra_) const { 1258 C2_MacroAssembler _masm(&cbuf); 1259 1260 int rem_space = 0; 1261 if (!(ra_->C->output()->in_scratch_emit_size())) { 1262 rem_space = cbuf.insts()->remaining(); 1263 if (rem_space <= _count*2 + 8) { 1264 tty->print("NopNode: _count = %3.3d, remaining space before = %d", _count, rem_space); 1265 } 1266 } 1267 1268 for (int i = 0; i < _count; i++) { 1269 __ z_nop(); 1270 } 1271 1272 if (!(ra_->C->output()->in_scratch_emit_size())) { 1273 if (rem_space <= _count*2 + 8) { 1274 int rem_space2 = cbuf.insts()->remaining(); 1275 tty->print_cr(", after = %d", rem_space2); 1276 } 1277 } 1278 } 1279 1280 uint MachNopNode::size(PhaseRegAlloc *ra_) const { 1281 return 2 * _count; 1282 } 1283 1284 #if !defined(PRODUCT) 1285 void BoxLockNode::format(PhaseRegAlloc *ra_, outputStream *os) const { 1286 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); 1287 if (ra_ && ra_->node_regs_max_index() > 0) { 1288 int reg = ra_->get_reg_first(this); 1289 os->print("ADDHI %s, SP, %d\t//box node", Matcher::regName[reg], offset); 1290 } else { 1291 os->print("ADDHI N%d = SP + %d\t// box node", _idx, offset); 1292 } 1293 } 1294 #endif 1295 1296 // Take care of the size function, if you make changes here! 1297 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 1298 C2_MacroAssembler _masm(&cbuf); 1299 1300 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); 1301 int reg = ra_->get_encode(this); 1302 __ z_lay(as_Register(reg), offset, Z_SP); 1303 } 1304 1305 uint BoxLockNode::size(PhaseRegAlloc *ra_) const { 1306 // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_) 1307 return 6; 1308 } 1309 1310 %} // end source section 1311 1312 //----------SOURCE BLOCK------------------------------------------------------- 1313 // This is a block of C++ code which provides values, functions, and 1314 // definitions necessary in the rest of the architecture description 1315 1316 source_hpp %{ 1317 1318 // Header information of the source block. 1319 // Method declarations/definitions which are used outside 1320 // the ad-scope can conveniently be defined here. 1321 // 1322 // To keep related declarations/definitions/uses close together, 1323 // we switch between source %{ }% and source_hpp %{ }% freely as needed. 1324 1325 //-------------------------------------------------------------- 1326 // Used for optimization in Compile::Shorten_branches 1327 //-------------------------------------------------------------- 1328 1329 class CallStubImpl { 1330 public: 1331 1332 // call trampolines 1333 // Size of call trampoline stub. For add'l comments, see size_java_to_interp(). 1334 static uint size_call_trampoline() { 1335 return 0; // no call trampolines on this platform 1336 } 1337 1338 // call trampolines 1339 // Number of relocations needed by a call trampoline stub. 1340 static uint reloc_call_trampoline() { 1341 return 0; // No call trampolines on this platform. 1342 } 1343 }; 1344 1345 %} // end source_hpp section 1346 1347 source %{ 1348 1349 #if !defined(PRODUCT) 1350 void MachUEPNode::format(PhaseRegAlloc *ra_, outputStream *os) const { 1351 os->print_cr("---- MachUEPNode ----"); 1352 os->print_cr("\tTA"); 1353 os->print_cr("\tload_const Z_R1, SharedRuntime::get_ic_miss_stub()"); 1354 os->print_cr("\tBR(Z_R1)"); 1355 os->print_cr("\tTA # pad with illtraps"); 1356 os->print_cr("\t..."); 1357 os->print_cr("\tTA"); 1358 os->print_cr("\tLTGR Z_R2, Z_R2"); 1359 os->print_cr("\tBRU ic_miss"); 1360 } 1361 #endif 1362 1363 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 1364 C2_MacroAssembler _masm(&cbuf); 1365 const int ic_miss_offset = 2; 1366 1367 // Inline_cache contains a klass. 1368 Register ic_klass = as_Register(Matcher::inline_cache_reg_encode()); 1369 // ARG1 is the receiver oop. 1370 Register R2_receiver = Z_ARG1; 1371 int klass_offset = oopDesc::klass_offset_in_bytes(); 1372 AddressLiteral icmiss(SharedRuntime::get_ic_miss_stub()); 1373 Register R1_ic_miss_stub_addr = Z_R1_scratch; 1374 1375 // Null check of receiver. 1376 // This is the null check of the receiver that actually should be 1377 // done in the caller. It's here because in case of implicit null 1378 // checks we get it for free. 1379 assert(!MacroAssembler::needs_explicit_null_check(oopDesc::klass_offset_in_bytes()), 1380 "second word in oop should not require explicit null check."); 1381 if (!ImplicitNullChecks) { 1382 Label valid; 1383 if (VM_Version::has_CompareBranch()) { 1384 __ z_cgij(R2_receiver, 0, Assembler::bcondNotEqual, valid); 1385 } else { 1386 __ z_ltgr(R2_receiver, R2_receiver); 1387 __ z_bre(valid); 1388 } 1389 // The ic_miss_stub will handle the null pointer exception. 1390 __ load_const_optimized(R1_ic_miss_stub_addr, icmiss); 1391 __ z_br(R1_ic_miss_stub_addr); 1392 __ bind(valid); 1393 } 1394 1395 // Check whether this method is the proper implementation for the class of 1396 // the receiver (ic miss check). 1397 { 1398 Label valid; 1399 // Compare cached class against klass from receiver. 1400 // This also does an implicit null check! 1401 __ compare_klass_ptr(ic_klass, klass_offset, R2_receiver, false); 1402 __ z_bre(valid); 1403 // The inline cache points to the wrong method. Call the 1404 // ic_miss_stub to find the proper method. 1405 __ load_const_optimized(R1_ic_miss_stub_addr, icmiss); 1406 __ z_br(R1_ic_miss_stub_addr); 1407 __ bind(valid); 1408 } 1409 } 1410 1411 uint MachUEPNode::size(PhaseRegAlloc *ra_) const { 1412 // Determine size dynamically. 1413 return MachNode::size(ra_); 1414 } 1415 1416 //============================================================================= 1417 1418 %} // interrupt source section 1419 1420 source_hpp %{ // Header information of the source block. 1421 1422 class HandlerImpl { 1423 public: 1424 1425 static int emit_exception_handler(CodeBuffer &cbuf); 1426 static int emit_deopt_handler(CodeBuffer& cbuf); 1427 1428 static uint size_exception_handler() { 1429 return NativeJump::max_instruction_size(); 1430 } 1431 1432 static uint size_deopt_handler() { 1433 return NativeCall::max_instruction_size(); 1434 } 1435 }; 1436 1437 class Node::PD { 1438 public: 1439 enum NodeFlags { 1440 _last_flag = Node::_last_flag 1441 }; 1442 }; 1443 1444 %} // end source_hpp section 1445 1446 source %{ 1447 1448 // This exception handler code snippet is placed after the method's 1449 // code. It is the return point if an exception occurred. it jumps to 1450 // the exception blob. 1451 // 1452 // If the method gets deoptimized, the method and this code snippet 1453 // get patched. 1454 // 1455 // 1) Trampoline code gets patched into the end of this exception 1456 // handler. the trampoline code jumps to the deoptimization blob. 1457 // 1458 // 2) The return address in the method's code will get patched such 1459 // that it jumps to the trampoline. 1460 // 1461 // 3) The handler will get patched such that it does not jump to the 1462 // exception blob, but to an entry in the deoptimization blob being 1463 // aware of the exception. 1464 int HandlerImpl::emit_exception_handler(CodeBuffer &cbuf) { 1465 Register temp_reg = Z_R1; 1466 C2_MacroAssembler _masm(&cbuf); 1467 1468 address base = __ start_a_stub(size_exception_handler()); 1469 if (base == NULL) { 1470 return 0; // CodeBuffer::expand failed 1471 } 1472 1473 int offset = __ offset(); 1474 // Use unconditional pc-relative jump with 32-bit range here. 1475 __ load_const_optimized(temp_reg, (address)OptoRuntime::exception_blob()->content_begin()); 1476 __ z_br(temp_reg); 1477 1478 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow"); 1479 1480 __ end_a_stub(); 1481 1482 return offset; 1483 } 1484 1485 // Emit deopt handler code. 1486 int HandlerImpl::emit_deopt_handler(CodeBuffer& cbuf) { 1487 C2_MacroAssembler _masm(&cbuf); 1488 address base = __ start_a_stub(size_deopt_handler()); 1489 1490 if (base == NULL) { 1491 return 0; // CodeBuffer::expand failed 1492 } 1493 1494 int offset = __ offset(); 1495 1496 // Size_deopt_handler() must be exact on zarch, so for simplicity 1497 // we do not use load_const_opt here. 1498 __ load_const(Z_R1, SharedRuntime::deopt_blob()->unpack()); 1499 __ call(Z_R1); 1500 assert(__ offset() - offset == (int) size_deopt_handler(), "must be fixed size"); 1501 1502 __ end_a_stub(); 1503 return offset; 1504 } 1505 1506 //============================================================================= 1507 1508 1509 // Given a register encoding, produce an Integer Register object. 1510 static Register reg_to_register_object(int register_encoding) { 1511 assert(Z_R12->encoding() == Z_R12_enc, "wrong coding"); 1512 return as_Register(register_encoding); 1513 } 1514 1515 const bool Matcher::match_rule_supported(int opcode) { 1516 if (!has_match_rule(opcode)) return false; 1517 1518 switch (opcode) { 1519 case Op_CountLeadingZerosI: 1520 case Op_CountLeadingZerosL: 1521 case Op_CountTrailingZerosI: 1522 case Op_CountTrailingZerosL: 1523 // Implementation requires FLOGR instruction, which is available since z9. 1524 return true; 1525 1526 case Op_ReverseBytesI: 1527 case Op_ReverseBytesL: 1528 return UseByteReverseInstruction; 1529 1530 // PopCount supported by H/W from z/Architecture G5 (z196) on. 1531 case Op_PopCountI: 1532 case Op_PopCountL: 1533 return UsePopCountInstruction && VM_Version::has_PopCount(); 1534 1535 case Op_StrComp: 1536 return SpecialStringCompareTo; 1537 case Op_StrEquals: 1538 return SpecialStringEquals; 1539 case Op_StrIndexOf: 1540 case Op_StrIndexOfChar: 1541 return SpecialStringIndexOf; 1542 1543 case Op_GetAndAddI: 1544 case Op_GetAndAddL: 1545 return true; 1546 // return VM_Version::has_AtomicMemWithImmALUOps(); 1547 case Op_GetAndSetI: 1548 case Op_GetAndSetL: 1549 case Op_GetAndSetP: 1550 case Op_GetAndSetN: 1551 return true; // General CAS implementation, always available. 1552 1553 default: 1554 return true; // Per default match rules are supported. 1555 // BUT: make sure match rule is not disabled by a false predicate! 1556 } 1557 1558 return true; // Per default match rules are supported. 1559 // BUT: make sure match rule is not disabled by a false predicate! 1560 } 1561 1562 const bool Matcher::match_rule_supported_vector(int opcode, int vlen, BasicType bt) { 1563 // TODO 1564 // Identify extra cases that we might want to provide match rules for 1565 // e.g. Op_ vector nodes and other intrinsics while guarding with vlen. 1566 bool ret_value = match_rule_supported(opcode); 1567 // Add rules here. 1568 1569 return ret_value; // Per default match rules are supported. 1570 } 1571 1572 int Matcher::regnum_to_fpu_offset(int regnum) { 1573 ShouldNotReachHere(); 1574 return regnum - 32; // The FP registers are in the second chunk. 1575 } 1576 1577 const bool Matcher::has_predicated_vectors(void) { 1578 return false; 1579 } 1580 1581 const int Matcher::float_pressure(int default_pressure_threshold) { 1582 return default_pressure_threshold; 1583 } 1584 1585 const bool Matcher::convL2FSupported(void) { 1586 return true; // False means that conversion is done by runtime call. 1587 } 1588 1589 //----------SUPERWORD HELPERS---------------------------------------- 1590 1591 // Vector width in bytes. 1592 const int Matcher::vector_width_in_bytes(BasicType bt) { 1593 assert(MaxVectorSize == 8, ""); 1594 return 8; 1595 } 1596 1597 // Vector ideal reg. 1598 const uint Matcher::vector_ideal_reg(int size) { 1599 assert(MaxVectorSize == 8 && size == 8, ""); 1600 return Op_RegL; 1601 } 1602 1603 // Limits on vector size (number of elements) loaded into vector. 1604 const int Matcher::max_vector_size(const BasicType bt) { 1605 assert(is_java_primitive(bt), "only primitive type vectors"); 1606 return vector_width_in_bytes(bt)/type2aelembytes(bt); 1607 } 1608 1609 const int Matcher::min_vector_size(const BasicType bt) { 1610 return max_vector_size(bt); // Same as max. 1611 } 1612 1613 const bool Matcher::supports_scalable_vector() { 1614 return false; 1615 } 1616 1617 const int Matcher::scalable_vector_reg_size(const BasicType bt) { 1618 return -1; 1619 } 1620 1621 // z/Architecture does support misaligned store/load at minimal extra cost. 1622 const bool Matcher::misaligned_vectors_ok() { 1623 return true; 1624 } 1625 1626 // Not yet ported to z/Architecture. 1627 const bool Matcher::pass_original_key_for_aes() { 1628 return false; 1629 } 1630 1631 // RETURNS: whether this branch offset is short enough that a short 1632 // branch can be used. 1633 // 1634 // If the platform does not provide any short branch variants, then 1635 // this method should return `false' for offset 0. 1636 // 1637 // `Compile::Fill_buffer' will decide on basis of this information 1638 // whether to do the pass `Compile::Shorten_branches' at all. 1639 // 1640 // And `Compile::Shorten_branches' will decide on basis of this 1641 // information whether to replace particular branch sites by short 1642 // ones. 1643 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) { 1644 // On zarch short branches use a 16 bit signed immediate that 1645 // is the pc-relative offset in halfword (= 2 bytes) units. 1646 return Assembler::is_within_range_of_RelAddr16((address)((long)offset), (address)0); 1647 } 1648 1649 const bool Matcher::isSimpleConstant64(jlong value) { 1650 // Probably always true, even if a temp register is required. 1651 return true; 1652 } 1653 1654 // Should correspond to setting above 1655 const bool Matcher::init_array_count_is_in_bytes = false; 1656 1657 // Suppress CMOVL. Conditional move available on z/Architecture only from z196 onwards. Not exploited yet. 1658 const int Matcher::long_cmove_cost() { return ConditionalMoveLimit; } 1659 1660 // Suppress CMOVF. Conditional move available on z/Architecture only from z196 onwards. Not exploited yet. 1661 const int Matcher::float_cmove_cost() { return ConditionalMoveLimit; } 1662 1663 // Does the CPU require postalloc expand (see block.cpp for description of postalloc expand)? 1664 const bool Matcher::require_postalloc_expand = false; 1665 1666 // Do we need to mask the count passed to shift instructions or does 1667 // the cpu only look at the lower 5/6 bits anyway? 1668 // 32bit shifts mask in emitter, 64bit shifts need no mask. 1669 // Constant shift counts are handled in Ideal phase. 1670 const bool Matcher::need_masked_shift_count = false; 1671 1672 // No support for generic vector operands. 1673 const bool Matcher::supports_generic_vector_operands = false; 1674 1675 MachOper* Matcher::pd_specialize_generic_vector_operand(MachOper* original_opnd, uint ideal_reg, bool is_temp) { 1676 ShouldNotReachHere(); // generic vector operands not supported 1677 return NULL; 1678 } 1679 1680 bool Matcher::is_generic_reg2reg_move(MachNode* m) { 1681 ShouldNotReachHere(); // generic vector operands not supported 1682 return false; 1683 } 1684 1685 bool Matcher::is_generic_vector(MachOper* opnd) { 1686 ShouldNotReachHere(); // generic vector operands not supported 1687 return false; 1688 } 1689 1690 // Set this as clone_shift_expressions. 1691 bool Matcher::narrow_oop_use_complex_address() { 1692 if (CompressedOops::base() == NULL && CompressedOops::shift() == 0) return true; 1693 return false; 1694 } 1695 1696 bool Matcher::narrow_klass_use_complex_address() { 1697 NOT_LP64(ShouldNotCallThis()); 1698 assert(UseCompressedClassPointers, "only for compressed klass code"); 1699 // TODO HS25: z port if (MatchDecodeNodes) return true; 1700 return false; 1701 } 1702 1703 bool Matcher::const_oop_prefer_decode() { 1704 // Prefer ConN+DecodeN over ConP in simple compressed oops mode. 1705 return CompressedOops::base() == NULL; 1706 } 1707 1708 bool Matcher::const_klass_prefer_decode() { 1709 // Prefer ConNKlass+DecodeNKlass over ConP in simple compressed klass mode. 1710 return CompressedKlassPointers::base() == NULL; 1711 } 1712 1713 // Is it better to copy float constants, or load them directly from memory? 1714 // Most RISCs will have to materialize an address into a 1715 // register first, so they would do better to copy the constant from stack. 1716 const bool Matcher::rematerialize_float_constants = false; 1717 1718 // If CPU can load and store mis-aligned doubles directly then no fixup is 1719 // needed. Else we split the double into 2 integer pieces and move it 1720 // piece-by-piece. Only happens when passing doubles into C code as the 1721 // Java calling convention forces doubles to be aligned. 1722 const bool Matcher::misaligned_doubles_ok = true; 1723 1724 // Advertise here if the CPU requires explicit rounding operations to implement strictfp mode. 1725 const bool Matcher::strict_fp_requires_explicit_rounding = false; 1726 1727 // Do floats take an entire double register or just half? 1728 // 1729 // A float in resides in a zarch double register. When storing it by 1730 // z_std, it cannot be restored in C-code by reloading it as a double 1731 // and casting it into a float afterwards. 1732 bool Matcher::float_in_double() { return false; } 1733 1734 // Do ints take an entire long register or just half? 1735 // The relevant question is how the int is callee-saved: 1736 // the whole long is written but de-opt'ing will have to extract 1737 // the relevant 32 bits. 1738 const bool Matcher::int_in_long = true; 1739 1740 // Constants for c2c and c calling conventions. 1741 1742 const MachRegisterNumbers z_iarg_reg[5] = { 1743 Z_R2_num, Z_R3_num, Z_R4_num, Z_R5_num, Z_R6_num 1744 }; 1745 1746 const MachRegisterNumbers z_farg_reg[4] = { 1747 Z_F0_num, Z_F2_num, Z_F4_num, Z_F6_num 1748 }; 1749 1750 const int z_num_iarg_registers = sizeof(z_iarg_reg) / sizeof(z_iarg_reg[0]); 1751 1752 const int z_num_farg_registers = sizeof(z_farg_reg) / sizeof(z_farg_reg[0]); 1753 1754 // Return whether or not this register is ever used as an argument. This 1755 // function is used on startup to build the trampoline stubs in generateOptoStub. 1756 // Registers not mentioned will be killed by the VM call in the trampoline, and 1757 // arguments in those registers not be available to the callee. 1758 bool Matcher::can_be_java_arg(int reg) { 1759 // We return true for all registers contained in z_iarg_reg[] and 1760 // z_farg_reg[] and their virtual halves. 1761 // We must include the virtual halves in order to get STDs and LDs 1762 // instead of STWs and LWs in the trampoline stubs. 1763 1764 if (reg == Z_R2_num || reg == Z_R2_H_num || 1765 reg == Z_R3_num || reg == Z_R3_H_num || 1766 reg == Z_R4_num || reg == Z_R4_H_num || 1767 reg == Z_R5_num || reg == Z_R5_H_num || 1768 reg == Z_R6_num || reg == Z_R6_H_num) { 1769 return true; 1770 } 1771 1772 if (reg == Z_F0_num || reg == Z_F0_H_num || 1773 reg == Z_F2_num || reg == Z_F2_H_num || 1774 reg == Z_F4_num || reg == Z_F4_H_num || 1775 reg == Z_F6_num || reg == Z_F6_H_num) { 1776 return true; 1777 } 1778 1779 return false; 1780 } 1781 1782 bool Matcher::is_spillable_arg(int reg) { 1783 return can_be_java_arg(reg); 1784 } 1785 1786 bool Matcher::use_asm_for_ldiv_by_con(jlong divisor) { 1787 return false; 1788 } 1789 1790 // Register for DIVI projection of divmodI 1791 RegMask Matcher::divI_proj_mask() { 1792 return _Z_RARG4_INT_REG_mask; 1793 } 1794 1795 // Register for MODI projection of divmodI 1796 RegMask Matcher::modI_proj_mask() { 1797 return _Z_RARG3_INT_REG_mask; 1798 } 1799 1800 // Register for DIVL projection of divmodL 1801 RegMask Matcher::divL_proj_mask() { 1802 return _Z_RARG4_LONG_REG_mask; 1803 } 1804 1805 // Register for MODL projection of divmodL 1806 RegMask Matcher::modL_proj_mask() { 1807 return _Z_RARG3_LONG_REG_mask; 1808 } 1809 1810 // Copied from sparc. 1811 const RegMask Matcher::method_handle_invoke_SP_save_mask() { 1812 return RegMask(); 1813 } 1814 1815 const bool Matcher::convi2l_type_required = true; 1816 1817 // Should the matcher clone input 'm' of node 'n'? 1818 bool Matcher::pd_clone_node(Node* n, Node* m, Matcher::MStack& mstack) { 1819 return false; 1820 } 1821 1822 // Should the Matcher clone shifts on addressing modes, expecting them 1823 // to be subsumed into complex addressing expressions or compute them 1824 // into registers? 1825 bool Matcher::pd_clone_address_expressions(AddPNode* m, Matcher::MStack& mstack, VectorSet& address_visited) { 1826 return clone_base_plus_offset_address(m, mstack, address_visited); 1827 } 1828 1829 void Compile::reshape_address(AddPNode* addp) { 1830 } 1831 1832 %} // source 1833 1834 //----------ENCODING BLOCK----------------------------------------------------- 1835 // This block specifies the encoding classes used by the compiler to output 1836 // byte streams. Encoding classes are parameterized macros used by 1837 // Machine Instruction Nodes in order to generate the bit encoding of the 1838 // instruction. Operands specify their base encoding interface with the 1839 // interface keyword. There are currently supported four interfaces, 1840 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an 1841 // operand to generate a function which returns its register number when 1842 // queried. CONST_INTER causes an operand to generate a function which 1843 // returns the value of the constant when queried. MEMORY_INTER causes an 1844 // operand to generate four functions which return the Base Register, the 1845 // Index Register, the Scale Value, and the Offset Value of the operand when 1846 // queried. COND_INTER causes an operand to generate six functions which 1847 // return the encoding code (ie - encoding bits for the instruction) 1848 // associated with each basic boolean condition for a conditional instruction. 1849 // 1850 // Instructions specify two basic values for encoding. Again, a function 1851 // is available to check if the constant displacement is an oop. They use the 1852 // ins_encode keyword to specify their encoding classes (which must be 1853 // a sequence of enc_class names, and their parameters, specified in 1854 // the encoding block), and they use the 1855 // opcode keyword to specify, in order, their primary, secondary, and 1856 // tertiary opcode. Only the opcode sections which a particular instruction 1857 // needs for encoding need to be specified. 1858 encode %{ 1859 enc_class enc_unimplemented %{ 1860 C2_MacroAssembler _masm(&cbuf); 1861 __ unimplemented("Unimplemented mach node encoding in AD file.", 13); 1862 %} 1863 1864 enc_class enc_untested %{ 1865 #ifdef ASSERT 1866 C2_MacroAssembler _masm(&cbuf); 1867 __ untested("Untested mach node encoding in AD file."); 1868 #endif 1869 %} 1870 1871 enc_class z_rrform(iRegI dst, iRegI src) %{ 1872 assert((($primary >> 14) & 0x03) == 0, "Instruction format error"); 1873 assert( ($primary >> 16) == 0, "Instruction format error"); 1874 z_emit16(cbuf, $primary | 1875 Assembler::reg($dst$$reg,8,16) | 1876 Assembler::reg($src$$reg,12,16)); 1877 %} 1878 1879 enc_class z_rreform(iRegI dst1, iRegI src2) %{ 1880 assert((($primary >> 30) & 0x03) == 2, "Instruction format error"); 1881 z_emit32(cbuf, $primary | 1882 Assembler::reg($dst1$$reg,24,32) | 1883 Assembler::reg($src2$$reg,28,32)); 1884 %} 1885 1886 enc_class z_rrfform(iRegI dst1, iRegI src2, iRegI src3) %{ 1887 assert((($primary >> 30) & 0x03) == 2, "Instruction format error"); 1888 z_emit32(cbuf, $primary | 1889 Assembler::reg($dst1$$reg,24,32) | 1890 Assembler::reg($src2$$reg,28,32) | 1891 Assembler::reg($src3$$reg,16,32)); 1892 %} 1893 1894 enc_class z_riform_signed(iRegI dst, immI16 src) %{ 1895 assert((($primary>>30) & 0x03) == 2, "Instruction format error"); 1896 z_emit32(cbuf, $primary | 1897 Assembler::reg($dst$$reg,8,32) | 1898 Assembler::simm16($src$$constant,16,32)); 1899 %} 1900 1901 enc_class z_riform_unsigned(iRegI dst, uimmI16 src) %{ 1902 assert((($primary>>30) & 0x03) == 2, "Instruction format error"); 1903 z_emit32(cbuf, $primary | 1904 Assembler::reg($dst$$reg,8,32) | 1905 Assembler::uimm16($src$$constant,16,32)); 1906 %} 1907 1908 enc_class z_rieform_d(iRegI dst1, iRegI src3, immI src2) %{ 1909 assert((($primary>>46) & 0x03) == 3, "Instruction format error"); 1910 z_emit48(cbuf, $primary | 1911 Assembler::reg($dst1$$reg,8,48) | 1912 Assembler::reg($src3$$reg,12,48) | 1913 Assembler::simm16($src2$$constant,16,48)); 1914 %} 1915 1916 enc_class z_rilform_signed(iRegI dst, immL32 src) %{ 1917 assert((($primary>>46) & 0x03) == 3, "Instruction format error"); 1918 z_emit48(cbuf, $primary | 1919 Assembler::reg($dst$$reg,8,48) | 1920 Assembler::simm32($src$$constant,16,48)); 1921 %} 1922 1923 enc_class z_rilform_unsigned(iRegI dst, uimmL32 src) %{ 1924 assert((($primary>>46) & 0x03) == 3, "Instruction format error"); 1925 z_emit48(cbuf, $primary | 1926 Assembler::reg($dst$$reg,8,48) | 1927 Assembler::uimm32($src$$constant,16,48)); 1928 %} 1929 1930 enc_class z_rsyform_const(iRegI dst, iRegI src1, immI src2) %{ 1931 z_emit48(cbuf, $primary | 1932 Assembler::reg($dst$$reg,8,48) | 1933 Assembler::reg($src1$$reg,12,48) | 1934 Assembler::simm20($src2$$constant)); 1935 %} 1936 1937 enc_class z_rsyform_reg_reg(iRegI dst, iRegI src, iRegI shft) %{ 1938 z_emit48(cbuf, $primary | 1939 Assembler::reg($dst$$reg,8,48) | 1940 Assembler::reg($src$$reg,12,48) | 1941 Assembler::reg($shft$$reg,16,48) | 1942 Assembler::simm20(0)); 1943 %} 1944 1945 enc_class z_rxform_imm_reg_reg(iRegL dst, immL con, iRegL src1, iRegL src2) %{ 1946 assert((($primary>>30) & 0x03) == 1, "Instruction format error"); 1947 z_emit32(cbuf, $primary | 1948 Assembler::reg($dst$$reg,8,32) | 1949 Assembler::reg($src1$$reg,12,32) | 1950 Assembler::reg($src2$$reg,16,32) | 1951 Assembler::uimm12($con$$constant,20,32)); 1952 %} 1953 1954 enc_class z_rxform_imm_reg(iRegL dst, immL con, iRegL src) %{ 1955 assert((($primary>>30) & 0x03) == 1, "Instruction format error"); 1956 z_emit32(cbuf, $primary | 1957 Assembler::reg($dst$$reg,8,32) | 1958 Assembler::reg($src$$reg,16,32) | 1959 Assembler::uimm12($con$$constant,20,32)); 1960 %} 1961 1962 enc_class z_rxyform_imm_reg_reg(iRegL dst, immL con, iRegL src1, iRegL src2) %{ 1963 z_emit48(cbuf, $primary | 1964 Assembler::reg($dst$$reg,8,48) | 1965 Assembler::reg($src1$$reg,12,48) | 1966 Assembler::reg($src2$$reg,16,48) | 1967 Assembler::simm20($con$$constant)); 1968 %} 1969 1970 enc_class z_rxyform_imm_reg(iRegL dst, immL con, iRegL src) %{ 1971 z_emit48(cbuf, $primary | 1972 Assembler::reg($dst$$reg,8,48) | 1973 Assembler::reg($src$$reg,16,48) | 1974 Assembler::simm20($con$$constant)); 1975 %} 1976 1977 // Direct memory arithmetic. 1978 enc_class z_siyform(memoryRSY mem, immI8 src) %{ 1979 int disp = $mem$$disp; 1980 Register base = reg_to_register_object($mem$$base); 1981 int con = $src$$constant; 1982 1983 assert(VM_Version::has_MemWithImmALUOps(), "unsupported CPU"); 1984 z_emit_inst(cbuf, $primary | 1985 Assembler::regz(base,16,48) | 1986 Assembler::simm20(disp) | 1987 Assembler::simm8(con,8,48)); 1988 %} 1989 1990 enc_class z_silform(memoryRS mem, immI16 src) %{ 1991 z_emit_inst(cbuf, $primary | 1992 Assembler::regz(reg_to_register_object($mem$$base),16,48) | 1993 Assembler::uimm12($mem$$disp,20,48) | 1994 Assembler::simm16($src$$constant,32,48)); 1995 %} 1996 1997 // Encoder for FP ALU reg/mem instructions (support only short displacements). 1998 enc_class z_form_rt_memFP(RegF dst, memoryRX mem) %{ 1999 Register Ridx = $mem$$index$$Register; 2000 if (Ridx == noreg) { Ridx = Z_R0; } // Index is 0. 2001 if ($primary > (1L << 32)) { 2002 z_emit_inst(cbuf, $primary | 2003 Assembler::reg($dst$$reg, 8, 48) | 2004 Assembler::uimm12($mem$$disp, 20, 48) | 2005 Assembler::reg(Ridx, 12, 48) | 2006 Assembler::regz(reg_to_register_object($mem$$base), 16, 48)); 2007 } else { 2008 z_emit_inst(cbuf, $primary | 2009 Assembler::reg($dst$$reg, 8, 32) | 2010 Assembler::uimm12($mem$$disp, 20, 32) | 2011 Assembler::reg(Ridx, 12, 32) | 2012 Assembler::regz(reg_to_register_object($mem$$base), 16, 32)); 2013 } 2014 %} 2015 2016 enc_class z_form_rt_mem(iRegI dst, memory mem) %{ 2017 Register Ridx = $mem$$index$$Register; 2018 if (Ridx == noreg) { Ridx = Z_R0; } // Index is 0. 2019 if ($primary > (1L<<32)) { 2020 z_emit_inst(cbuf, $primary | 2021 Assembler::reg($dst$$reg, 8, 48) | 2022 Assembler::simm20($mem$$disp) | 2023 Assembler::reg(Ridx, 12, 48) | 2024 Assembler::regz(reg_to_register_object($mem$$base), 16, 48)); 2025 } else { 2026 z_emit_inst(cbuf, $primary | 2027 Assembler::reg($dst$$reg, 8, 32) | 2028 Assembler::uimm12($mem$$disp, 20, 32) | 2029 Assembler::reg(Ridx, 12, 32) | 2030 Assembler::regz(reg_to_register_object($mem$$base), 16, 32)); 2031 } 2032 %} 2033 2034 enc_class z_form_rt_mem_opt(iRegI dst, memory mem) %{ 2035 int isize = $secondary > 1L << 32 ? 48 : 32; 2036 Register Ridx = $mem$$index$$Register; 2037 if (Ridx == noreg) { Ridx = Z_R0; } // Index is 0. 2038 2039 if (Displacement::is_shortDisp((long)$mem$$disp)) { 2040 z_emit_inst(cbuf, $secondary | 2041 Assembler::reg($dst$$reg, 8, isize) | 2042 Assembler::uimm12($mem$$disp, 20, isize) | 2043 Assembler::reg(Ridx, 12, isize) | 2044 Assembler::regz(reg_to_register_object($mem$$base), 16, isize)); 2045 } else if (Displacement::is_validDisp((long)$mem$$disp)) { 2046 z_emit_inst(cbuf, $primary | 2047 Assembler::reg($dst$$reg, 8, 48) | 2048 Assembler::simm20($mem$$disp) | 2049 Assembler::reg(Ridx, 12, 48) | 2050 Assembler::regz(reg_to_register_object($mem$$base), 16, 48)); 2051 } else { 2052 C2_MacroAssembler _masm(&cbuf); 2053 __ load_const_optimized(Z_R1_scratch, $mem$$disp); 2054 if (Ridx != Z_R0) { __ z_agr(Z_R1_scratch, Ridx); } 2055 z_emit_inst(cbuf, $secondary | 2056 Assembler::reg($dst$$reg, 8, isize) | 2057 Assembler::uimm12(0, 20, isize) | 2058 Assembler::reg(Z_R1_scratch, 12, isize) | 2059 Assembler::regz(reg_to_register_object($mem$$base), 16, isize)); 2060 } 2061 %} 2062 2063 enc_class z_enc_brul(Label lbl) %{ 2064 C2_MacroAssembler _masm(&cbuf); 2065 Label* p = $lbl$$label; 2066 2067 // 'p' is `NULL' when this encoding class is used only to 2068 // determine the size of the encoded instruction. 2069 // Use a bound dummy label in that case. 2070 Label d; 2071 __ bind(d); 2072 Label& l = (NULL == p) ? d : *(p); 2073 __ z_brul(l); 2074 %} 2075 2076 enc_class z_enc_bru(Label lbl) %{ 2077 C2_MacroAssembler _masm(&cbuf); 2078 Label* p = $lbl$$label; 2079 2080 // 'p' is `NULL' when this encoding class is used only to 2081 // determine the size of the encoded instruction. 2082 // Use a bound dummy label in that case. 2083 Label d; 2084 __ bind(d); 2085 Label& l = (NULL == p) ? d : *(p); 2086 __ z_bru(l); 2087 %} 2088 2089 enc_class z_enc_branch_con_far(cmpOp cmp, Label lbl) %{ 2090 C2_MacroAssembler _masm(&cbuf); 2091 Label* p = $lbl$$label; 2092 2093 // 'p' is `NULL' when this encoding class is used only to 2094 // determine the size of the encoded instruction. 2095 // Use a bound dummy label in that case. 2096 Label d; 2097 __ bind(d); 2098 Label& l = (NULL == p) ? d : *(p); 2099 __ z_brcl((Assembler::branch_condition)$cmp$$cmpcode, l); 2100 %} 2101 2102 enc_class z_enc_branch_con_short(cmpOp cmp, Label lbl) %{ 2103 C2_MacroAssembler _masm(&cbuf); 2104 Label* p = $lbl$$label; 2105 2106 // 'p' is `NULL' when this encoding class is used only to 2107 // determine the size of the encoded instruction. 2108 // Use a bound dummy label in that case. 2109 Label d; 2110 __ bind(d); 2111 Label& l = (NULL == p) ? d : *(p); 2112 __ z_brc((Assembler::branch_condition)$cmp$$cmpcode, l); 2113 %} 2114 2115 enc_class z_enc_cmpb_regreg(iRegI src1, iRegI src2, Label lbl, cmpOpT cmp) %{ 2116 C2_MacroAssembler _masm(&cbuf); 2117 Label* p = $lbl$$label; 2118 2119 // 'p' is `NULL' when this encoding class is used only to 2120 // determine the size of the encoded instruction. 2121 // Use a bound dummy label in that case. 2122 Label d; 2123 __ bind(d); 2124 Label& l = (NULL == p) ? d : *(p); 2125 Assembler::branch_condition cc = (Assembler::branch_condition)$cmp$$cmpcode; 2126 unsigned long instr = $primary; 2127 if (instr == CRJ_ZOPC) { 2128 __ z_crj($src1$$Register, $src2$$Register, cc, l); 2129 } else if (instr == CLRJ_ZOPC) { 2130 __ z_clrj($src1$$Register, $src2$$Register, cc, l); 2131 } else if (instr == CGRJ_ZOPC) { 2132 __ z_cgrj($src1$$Register, $src2$$Register, cc, l); 2133 } else { 2134 guarantee(instr == CLGRJ_ZOPC, "opcode not implemented"); 2135 __ z_clgrj($src1$$Register, $src2$$Register, cc, l); 2136 } 2137 %} 2138 2139 enc_class z_enc_cmpb_regregFar(iRegI src1, iRegI src2, Label lbl, cmpOpT cmp) %{ 2140 C2_MacroAssembler _masm(&cbuf); 2141 Label* p = $lbl$$label; 2142 2143 // 'p' is `NULL' when this encoding class is used only to 2144 // determine the size of the encoded instruction. 2145 // Use a bound dummy label in that case. 2146 Label d; 2147 __ bind(d); 2148 Label& l = (NULL == p) ? d : *(p); 2149 2150 unsigned long instr = $primary; 2151 if (instr == CR_ZOPC) { 2152 __ z_cr($src1$$Register, $src2$$Register); 2153 } else if (instr == CLR_ZOPC) { 2154 __ z_clr($src1$$Register, $src2$$Register); 2155 } else if (instr == CGR_ZOPC) { 2156 __ z_cgr($src1$$Register, $src2$$Register); 2157 } else { 2158 guarantee(instr == CLGR_ZOPC, "opcode not implemented"); 2159 __ z_clgr($src1$$Register, $src2$$Register); 2160 } 2161 2162 __ z_brcl((Assembler::branch_condition)$cmp$$cmpcode, l); 2163 %} 2164 2165 enc_class z_enc_cmpb_regimm(iRegI src1, immI8 src2, Label lbl, cmpOpT cmp) %{ 2166 C2_MacroAssembler _masm(&cbuf); 2167 Label* p = $lbl$$label; 2168 2169 // 'p' is `NULL' when this encoding class is used only to 2170 // determine the size of the encoded instruction. 2171 // Use a bound dummy label in that case. 2172 Label d; 2173 __ bind(d); 2174 Label& l = (NULL == p) ? d : *(p); 2175 2176 Assembler::branch_condition cc = (Assembler::branch_condition)$cmp$$cmpcode; 2177 unsigned long instr = $primary; 2178 if (instr == CIJ_ZOPC) { 2179 __ z_cij($src1$$Register, $src2$$constant, cc, l); 2180 } else if (instr == CLIJ_ZOPC) { 2181 __ z_clij($src1$$Register, $src2$$constant, cc, l); 2182 } else if (instr == CGIJ_ZOPC) { 2183 __ z_cgij($src1$$Register, $src2$$constant, cc, l); 2184 } else { 2185 guarantee(instr == CLGIJ_ZOPC, "opcode not implemented"); 2186 __ z_clgij($src1$$Register, $src2$$constant, cc, l); 2187 } 2188 %} 2189 2190 enc_class z_enc_cmpb_regimmFar(iRegI src1, immI8 src2, Label lbl, cmpOpT cmp) %{ 2191 C2_MacroAssembler _masm(&cbuf); 2192 Label* p = $lbl$$label; 2193 2194 // 'p' is `NULL' when this encoding class is used only to 2195 // determine the size of the encoded instruction. 2196 // Use a bound dummy label in that case. 2197 Label d; 2198 __ bind(d); 2199 Label& l = (NULL == p) ? d : *(p); 2200 2201 unsigned long instr = $primary; 2202 if (instr == CHI_ZOPC) { 2203 __ z_chi($src1$$Register, $src2$$constant); 2204 } else if (instr == CLFI_ZOPC) { 2205 __ z_clfi($src1$$Register, $src2$$constant); 2206 } else if (instr == CGHI_ZOPC) { 2207 __ z_cghi($src1$$Register, $src2$$constant); 2208 } else { 2209 guarantee(instr == CLGFI_ZOPC, "opcode not implemented"); 2210 __ z_clgfi($src1$$Register, $src2$$constant); 2211 } 2212 2213 __ z_brcl((Assembler::branch_condition)$cmp$$cmpcode, l); 2214 %} 2215 2216 // Call from Java to runtime. 2217 enc_class z_enc_java_to_runtime_call(method meth) %{ 2218 C2_MacroAssembler _masm(&cbuf); 2219 2220 // Save return pc before call to the place where we need it, since 2221 // callee doesn't. 2222 unsigned int start_off = __ offset(); 2223 // Compute size of "larl + stg + call_c_opt". 2224 const int size_of_code = 6 + 6 + MacroAssembler::call_far_patchable_size(); 2225 __ get_PC(Z_R14, size_of_code); 2226 __ save_return_pc(); 2227 assert(__ offset() - start_off == 12, "bad prelude len: %d", __ offset() - start_off); 2228 2229 assert((__ offset() & 2) == 0, "misaligned z_enc_java_to_runtime_call"); 2230 address call_addr = __ call_c_opt((address)$meth$$method); 2231 if (call_addr == NULL) { 2232 Compile::current()->env()->record_out_of_memory_failure(); 2233 return; 2234 } 2235 2236 #ifdef ASSERT 2237 // Plausibility check for size_of_code assumptions. 2238 unsigned int actual_ret_off = __ offset(); 2239 assert(start_off + size_of_code == actual_ret_off, "wrong return_pc"); 2240 #endif 2241 %} 2242 2243 enc_class z_enc_java_static_call(method meth) %{ 2244 // Call to fixup routine. Fixup routine uses ScopeDesc info to determine 2245 // whom we intended to call. 2246 C2_MacroAssembler _masm(&cbuf); 2247 int ret_offset = 0; 2248 2249 if (!_method) { 2250 ret_offset = emit_call_reloc(_masm, $meth$$method, 2251 relocInfo::runtime_call_w_cp_type, ra_); 2252 } else { 2253 int method_index = resolved_method_index(cbuf); 2254 if (_optimized_virtual) { 2255 ret_offset = emit_call_reloc(_masm, $meth$$method, 2256 opt_virtual_call_Relocation::spec(method_index)); 2257 } else { 2258 ret_offset = emit_call_reloc(_masm, $meth$$method, 2259 static_call_Relocation::spec(method_index)); 2260 } 2261 } 2262 assert(__ inst_mark() != NULL, "emit_call_reloc must set_inst_mark()"); 2263 2264 if (_method) { // Emit stub for static call. 2265 address stub = CompiledStaticCall::emit_to_interp_stub(cbuf); 2266 if (stub == NULL) { 2267 ciEnv::current()->record_failure("CodeCache is full"); 2268 return; 2269 } 2270 } 2271 %} 2272 2273 // Java dynamic call 2274 enc_class z_enc_java_dynamic_call(method meth) %{ 2275 C2_MacroAssembler _masm(&cbuf); 2276 unsigned int start_off = __ offset(); 2277 2278 int vtable_index = this->_vtable_index; 2279 if (vtable_index == -4) { 2280 Register ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode()); 2281 address virtual_call_oop_addr = NULL; 2282 2283 AddressLiteral empty_ic((address) Universe::non_oop_word()); 2284 virtual_call_oop_addr = __ pc(); 2285 bool success = __ load_const_from_toc(ic_reg, empty_ic); 2286 if (!success) { 2287 Compile::current()->env()->record_out_of_memory_failure(); 2288 return; 2289 } 2290 2291 // Call to fixup routine. Fixup routine uses ScopeDesc info 2292 // to determine who we intended to call. 2293 int method_index = resolved_method_index(cbuf); 2294 __ relocate(virtual_call_Relocation::spec(virtual_call_oop_addr, method_index)); 2295 unsigned int ret_off = __ offset(); 2296 assert(__ offset() - start_off == 6, "bad prelude len: %d", __ offset() - start_off); 2297 ret_off += emit_call_reloc(_masm, $meth$$method, relocInfo::none, ra_); 2298 assert(_method, "lazy_constant may be wrong when _method==null"); 2299 } else { 2300 assert(!UseInlineCaches, "expect vtable calls only if not using ICs"); 2301 // Go through the vtable. Get receiver klass. Receiver already 2302 // checked for non-null. If we'll go thru a C2I adapter, the 2303 // interpreter expects method in Z_method. 2304 // Use Z_method to temporarily hold the klass oop. 2305 // Z_R1_scratch is destroyed. 2306 __ load_klass(Z_method, Z_R2); 2307 2308 int entry_offset = in_bytes(Klass::vtable_start_offset()) + vtable_index * vtableEntry::size_in_bytes(); 2309 int v_off = entry_offset + vtableEntry::method_offset_in_bytes(); 2310 2311 if (Displacement::is_validDisp(v_off) ) { 2312 // Can use load instruction with large offset. 2313 __ z_lg(Z_method, Address(Z_method /*class oop*/, v_off /*method offset*/)); 2314 } else { 2315 // Worse case, must load offset into register. 2316 __ load_const(Z_R1_scratch, v_off); 2317 __ z_lg(Z_method, Address(Z_method /*class oop*/, Z_R1_scratch /*method offset*/)); 2318 } 2319 // NOTE: for vtable dispatches, the vtable entry will never be 2320 // null. However it may very well end up in handle_wrong_method 2321 // if the method is abstract for the particular class. 2322 __ z_lg(Z_R1_scratch, Address(Z_method, Method::from_compiled_offset())); 2323 // Call target. Either compiled code or C2I adapter. 2324 __ z_basr(Z_R14, Z_R1_scratch); 2325 unsigned int ret_off = __ offset(); 2326 } 2327 %} 2328 2329 enc_class z_enc_cmov_reg(cmpOp cmp, iRegI dst, iRegI src) %{ 2330 C2_MacroAssembler _masm(&cbuf); 2331 Register Rdst = reg_to_register_object($dst$$reg); 2332 Register Rsrc = reg_to_register_object($src$$reg); 2333 2334 // Don't emit code if operands are identical (same register). 2335 if (Rsrc != Rdst) { 2336 Assembler::branch_condition cc = (Assembler::branch_condition)$cmp$$cmpcode; 2337 2338 if (VM_Version::has_LoadStoreConditional()) { 2339 __ z_locgr(Rdst, Rsrc, cc); 2340 } else { 2341 // Branch if not (cmp cr). 2342 Label done; 2343 __ z_brc(Assembler::inverse_condition(cc), done); 2344 __ z_lgr(Rdst, Rsrc); // Used for int and long+ptr. 2345 __ bind(done); 2346 } 2347 } 2348 %} 2349 2350 enc_class z_enc_cmov_imm(cmpOp cmp, iRegI dst, immI16 src) %{ 2351 C2_MacroAssembler _masm(&cbuf); 2352 Register Rdst = reg_to_register_object($dst$$reg); 2353 int Csrc = $src$$constant; 2354 Assembler::branch_condition cc = (Assembler::branch_condition)$cmp$$cmpcode; 2355 Label done; 2356 // Branch if not (cmp cr). 2357 __ z_brc(Assembler::inverse_condition(cc), done); 2358 if (Csrc == 0) { 2359 // Don't set CC. 2360 __ clear_reg(Rdst, true, false); // Use for int, long & ptr. 2361 } else { 2362 __ z_lghi(Rdst, Csrc); // Use for int, long & ptr. 2363 } 2364 __ bind(done); 2365 %} 2366 2367 enc_class z_enc_cctobool(iRegI res) %{ 2368 C2_MacroAssembler _masm(&cbuf); 2369 Register Rres = reg_to_register_object($res$$reg); 2370 2371 if (VM_Version::has_LoadStoreConditional()) { 2372 __ load_const_optimized(Z_R0_scratch, 0L); // false (failed) 2373 __ load_const_optimized(Rres, 1L); // true (succeed) 2374 __ z_locgr(Rres, Z_R0_scratch, Assembler::bcondNotEqual); 2375 } else { 2376 Label done; 2377 __ load_const_optimized(Rres, 0L); // false (failed) 2378 __ z_brne(done); // Assume true to be the common case. 2379 __ load_const_optimized(Rres, 1L); // true (succeed) 2380 __ bind(done); 2381 } 2382 %} 2383 2384 enc_class z_enc_casI(iRegI compare_value, iRegI exchange_value, iRegP addr_ptr) %{ 2385 C2_MacroAssembler _masm(&cbuf); 2386 Register Rcomp = reg_to_register_object($compare_value$$reg); 2387 Register Rnew = reg_to_register_object($exchange_value$$reg); 2388 Register Raddr = reg_to_register_object($addr_ptr$$reg); 2389 2390 __ z_cs(Rcomp, Rnew, 0, Raddr); 2391 %} 2392 2393 enc_class z_enc_casL(iRegL compare_value, iRegL exchange_value, iRegP addr_ptr) %{ 2394 C2_MacroAssembler _masm(&cbuf); 2395 Register Rcomp = reg_to_register_object($compare_value$$reg); 2396 Register Rnew = reg_to_register_object($exchange_value$$reg); 2397 Register Raddr = reg_to_register_object($addr_ptr$$reg); 2398 2399 __ z_csg(Rcomp, Rnew, 0, Raddr); 2400 %} 2401 2402 enc_class z_enc_SwapI(memoryRSY mem, iRegI dst, iRegI tmp) %{ 2403 C2_MacroAssembler _masm(&cbuf); 2404 Register Rdst = reg_to_register_object($dst$$reg); 2405 Register Rtmp = reg_to_register_object($tmp$$reg); 2406 guarantee(Rdst != Rtmp, "Fix match rule to use TEMP_DEF"); 2407 Label retry; 2408 2409 // Iterate until swap succeeds. 2410 __ z_llgf(Rtmp, $mem$$Address); // current contents 2411 __ bind(retry); 2412 // Calculate incremented value. 2413 __ z_csy(Rtmp, Rdst, $mem$$Address); // Try to store new value. 2414 __ z_brne(retry); // Yikes, concurrent update, need to retry. 2415 __ z_lgr(Rdst, Rtmp); // Exchanged value from memory is return value. 2416 %} 2417 2418 enc_class z_enc_SwapL(memoryRSY mem, iRegL dst, iRegL tmp) %{ 2419 C2_MacroAssembler _masm(&cbuf); 2420 Register Rdst = reg_to_register_object($dst$$reg); 2421 Register Rtmp = reg_to_register_object($tmp$$reg); 2422 guarantee(Rdst != Rtmp, "Fix match rule to use TEMP_DEF"); 2423 Label retry; 2424 2425 // Iterate until swap succeeds. 2426 __ z_lg(Rtmp, $mem$$Address); // current contents 2427 __ bind(retry); 2428 // Calculate incremented value. 2429 __ z_csg(Rtmp, Rdst, $mem$$Address); // Try to store new value. 2430 __ z_brne(retry); // Yikes, concurrent update, need to retry. 2431 __ z_lgr(Rdst, Rtmp); // Exchanged value from memory is return value. 2432 %} 2433 2434 %} // encode 2435 2436 source %{ 2437 2438 // Check whether outs are all Stores. If so, we can omit clearing the upper 2439 // 32 bits after encoding. 2440 static bool all_outs_are_Stores(const Node *n) { 2441 for (DUIterator_Fast imax, k = n->fast_outs(imax); k < imax; k++) { 2442 Node *out = n->fast_out(k); 2443 if (!out->is_Mach() || out->as_Mach()->ideal_Opcode() != Op_StoreN) { 2444 // Most other outs are SpillCopy, but there are various other. 2445 // jvm98 has arond 9% Encodes where we return false. 2446 return false; 2447 } 2448 } 2449 return true; 2450 } 2451 2452 %} // source 2453 2454 2455 //----------FRAME-------------------------------------------------------------- 2456 // Definition of frame structure and management information. 2457 2458 frame %{ 2459 // What direction does stack grow in (assumed to be same for native & Java). 2460 stack_direction(TOWARDS_LOW); 2461 2462 // These two registers define part of the calling convention between 2463 // compiled code and the interpreter. 2464 2465 // Inline Cache Register 2466 inline_cache_reg(Z_R9); // Z_inline_cache 2467 2468 // Argument pointer for I2C adapters 2469 // 2470 // Tos is loaded in run_compiled_code to Z_ARG5=Z_R6. 2471 // interpreter_arg_ptr_reg(Z_R6); 2472 2473 // Temporary in compiled entry-points 2474 // compiler_method_oop_reg(Z_R1);//Z_R1_scratch 2475 2476 // Method Oop Register when calling interpreter 2477 interpreter_method_oop_reg(Z_R9);//Z_method 2478 2479 // Optional: name the operand used by cisc-spilling to access 2480 // [stack_pointer + offset]. 2481 cisc_spilling_operand_name(indOffset12); 2482 2483 // Number of stack slots consumed by a Monitor enter. 2484 sync_stack_slots(frame::jit_monitor_size_in_4_byte_units); 2485 2486 // Compiled code's Frame Pointer 2487 // 2488 // z/Architecture stack pointer 2489 frame_pointer(Z_R15); // Z_SP 2490 2491 // Interpreter stores its frame pointer in a register which is 2492 // stored to the stack by I2CAdaptors. I2CAdaptors convert from 2493 // interpreted java to compiled java. 2494 // 2495 // Z_state holds pointer to caller's cInterpreter. 2496 interpreter_frame_pointer(Z_R7); // Z_state 2497 2498 // Use alignment_in_bytes instead of log_2_of_alignment_in_bits. 2499 stack_alignment(frame::alignment_in_bytes); 2500 2501 in_preserve_stack_slots(frame::jit_in_preserve_size_in_4_byte_units); 2502 2503 // A `slot' is assumed 4 bytes here! 2504 // out_preserve_stack_slots(frame::jit_out_preserve_size_in_4_byte_units); 2505 2506 // Number of outgoing stack slots killed above the 2507 // out_preserve_stack_slots for calls to C. Supports the var-args 2508 // backing area for register parms. 2509 varargs_C_out_slots_killed(((frame::z_abi_160_size - frame::z_jit_out_preserve_size) / VMRegImpl::stack_slot_size)); 2510 2511 // The after-PROLOG location of the return address. Location of 2512 // return address specifies a type (REG or STACK) and a number 2513 // representing the register number (i.e. - use a register name) or 2514 // stack slot. 2515 return_addr(REG Z_R14); 2516 2517 // This is the body of the function 2518 // 2519 // void Matcher::calling_convention(OptoRegPair* sig /* array of ideal regs */, 2520 // uint length /* length of array */, 2521 // bool is_outgoing) 2522 // 2523 // The `sig' array is to be updated. Sig[j] represents the location 2524 // of the j-th argument, either a register or a stack slot. 2525 2526 // Body of function which returns an integer array locating 2527 // arguments either in registers or in stack slots. Passed an array 2528 // of ideal registers called "sig" and a "length" count. Stack-slot 2529 // offsets are based on outgoing arguments, i.e. a CALLER setting up 2530 // arguments for a CALLEE. Incoming stack arguments are 2531 // automatically biased by the preserve_stack_slots field above. 2532 calling_convention %{ 2533 // No difference between ingoing/outgoing just pass false. 2534 SharedRuntime::java_calling_convention(sig_bt, regs, length, false); 2535 %} 2536 2537 // Body of function which returns an integer array locating 2538 // arguments either in registers or in stack slots. Passed an array 2539 // of ideal registers called "sig" and a "length" count. Stack-slot 2540 // offsets are based on outgoing arguments, i.e. a CALLER setting up 2541 // arguments for a CALLEE. Incoming stack arguments are 2542 // automatically biased by the preserve_stack_slots field above. 2543 c_calling_convention %{ 2544 // This is obviously always outgoing. 2545 // C argument must be in register AND stack slot. 2546 (void) SharedRuntime::c_calling_convention(sig_bt, regs, /*regs2=*/NULL, length); 2547 %} 2548 2549 // Location of native (C/C++) and interpreter return values. This 2550 // is specified to be the same as Java. In the 32-bit VM, long 2551 // values are actually returned from native calls in O0:O1 and 2552 // returned to the interpreter in I0:I1. The copying to and from 2553 // the register pairs is done by the appropriate call and epilog 2554 // opcodes. This simplifies the register allocator. 2555 // 2556 // Use register pair for c return value. 2557 c_return_value %{ 2558 assert(ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values"); 2559 static int typeToRegLo[Op_RegL+1] = { 0, 0, Z_R2_num, Z_R2_num, Z_R2_num, Z_F0_num, Z_F0_num, Z_R2_num }; 2560 static int typeToRegHi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, Z_R2_H_num, OptoReg::Bad, Z_F0_H_num, Z_R2_H_num }; 2561 return OptoRegPair(typeToRegHi[ideal_reg], typeToRegLo[ideal_reg]); 2562 %} 2563 2564 // Use register pair for return value. 2565 // Location of compiled Java return values. Same as C 2566 return_value %{ 2567 assert(ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values"); 2568 static int typeToRegLo[Op_RegL+1] = { 0, 0, Z_R2_num, Z_R2_num, Z_R2_num, Z_F0_num, Z_F0_num, Z_R2_num }; 2569 static int typeToRegHi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, Z_R2_H_num, OptoReg::Bad, Z_F0_H_num, Z_R2_H_num }; 2570 return OptoRegPair(typeToRegHi[ideal_reg], typeToRegLo[ideal_reg]); 2571 %} 2572 %} 2573 2574 2575 //----------ATTRIBUTES--------------------------------------------------------- 2576 2577 //----------Operand Attributes------------------------------------------------- 2578 op_attrib op_cost(1); // Required cost attribute 2579 2580 //----------Instruction Attributes--------------------------------------------- 2581 2582 // Cost attribute. required. 2583 ins_attrib ins_cost(DEFAULT_COST); 2584 2585 // Is this instruction a non-matching short branch variant of some 2586 // long branch? Not required. 2587 ins_attrib ins_short_branch(0); 2588 2589 // Indicates this is a trap based check node and final control-flow fixup 2590 // must generate a proper fall through. 2591 ins_attrib ins_is_TrapBasedCheckNode(true); 2592 2593 // Attribute of instruction to tell how many constants the instruction will generate. 2594 // (optional attribute). Default: 0. 2595 ins_attrib ins_num_consts(0); 2596 2597 // Required alignment attribute (must be a power of 2) 2598 // specifies the alignment that some part of the instruction (not 2599 // necessarily the start) requires. If > 1, a compute_padding() 2600 // function must be provided for the instruction. 2601 // 2602 // WARNING: Don't use size(FIXED_SIZE) or size(VARIABLE_SIZE) in 2603 // instructions which depend on the proper alignment, because the 2604 // desired alignment isn't guaranteed for the call to "emit()" during 2605 // the size computation. 2606 ins_attrib ins_alignment(1); 2607 2608 // Enforce/prohibit rematerializations. 2609 // - If an instruction is attributed with 'ins_cannot_rematerialize(true)' 2610 // then rematerialization of that instruction is prohibited and the 2611 // instruction's value will be spilled if necessary. 2612 // - If an instruction is attributed with 'ins_should_rematerialize(true)' 2613 // then rematerialization is enforced and the instruction's value will 2614 // never get spilled. a copy of the instruction will be inserted if 2615 // necessary. 2616 // Note: this may result in rematerializations in front of every use. 2617 // (optional attribute) 2618 ins_attrib ins_cannot_rematerialize(false); 2619 ins_attrib ins_should_rematerialize(false); 2620 2621 //----------OPERANDS----------------------------------------------------------- 2622 // Operand definitions must precede instruction definitions for correct 2623 // parsing in the ADLC because operands constitute user defined types 2624 // which are used in instruction definitions. 2625 2626 //----------Simple Operands---------------------------------------------------- 2627 // Immediate Operands 2628 // Please note: 2629 // Formats are generated automatically for constants and base registers. 2630 2631 //---------------------------------------------- 2632 // SIGNED (shorter than INT) immediate operands 2633 //---------------------------------------------- 2634 2635 // Byte Immediate: constant 'int -1' 2636 operand immB_minus1() %{ 2637 // sign-ext constant zero-ext constant 2638 predicate((n->get_int() == -1) || ((n->get_int()&0x000000ff) == 0x000000ff)); 2639 match(ConI); 2640 op_cost(1); 2641 format %{ %} 2642 interface(CONST_INTER); 2643 %} 2644 2645 // Byte Immediate: constant, but not 'int 0' nor 'int -1'. 2646 operand immB_n0m1() %{ 2647 // sign-ext constant zero-ext constant 2648 predicate(n->get_int() != 0 && n->get_int() != -1 && (n->get_int()&0x000000ff) != 0x000000ff); 2649 match(ConI); 2650 op_cost(1); 2651 format %{ %} 2652 interface(CONST_INTER); 2653 %} 2654 2655 // Short Immediate: constant 'int -1' 2656 operand immS_minus1() %{ 2657 // sign-ext constant zero-ext constant 2658 predicate((n->get_int() == -1) || ((n->get_int()&0x0000ffff) == 0x0000ffff)); 2659 match(ConI); 2660 op_cost(1); 2661 format %{ %} 2662 interface(CONST_INTER); 2663 %} 2664 2665 // Short Immediate: constant, but not 'int 0' nor 'int -1'. 2666 operand immS_n0m1() %{ 2667 // sign-ext constant zero-ext constant 2668 predicate(n->get_int() != 0 && n->get_int() != -1 && (n->get_int()&0x0000ffff) != 0x0000ffff); 2669 match(ConI); 2670 op_cost(1); 2671 format %{ %} 2672 interface(CONST_INTER); 2673 %} 2674 2675 //----------------------------------------- 2676 // SIGNED INT immediate operands 2677 //----------------------------------------- 2678 2679 // Integer Immediate: 32-bit 2680 operand immI() %{ 2681 match(ConI); 2682 op_cost(1); 2683 format %{ %} 2684 interface(CONST_INTER); 2685 %} 2686 2687 // Int Immediate: 20-bit 2688 operand immI20() %{ 2689 predicate(Immediate::is_simm20(n->get_int())); 2690 match(ConI); 2691 op_cost(1); 2692 format %{ %} 2693 interface(CONST_INTER); 2694 %} 2695 2696 // Integer Immediate: 16-bit 2697 operand immI16() %{ 2698 predicate(Immediate::is_simm16(n->get_int())); 2699 match(ConI); 2700 op_cost(1); 2701 format %{ %} 2702 interface(CONST_INTER); 2703 %} 2704 2705 // Integer Immediate: 8-bit 2706 operand immI8() %{ 2707 predicate(Immediate::is_simm8(n->get_int())); 2708 match(ConI); 2709 op_cost(1); 2710 format %{ %} 2711 interface(CONST_INTER); 2712 %} 2713 2714 // Integer Immediate: constant 'int 0' 2715 operand immI_0() %{ 2716 predicate(n->get_int() == 0); 2717 match(ConI); 2718 op_cost(1); 2719 format %{ %} 2720 interface(CONST_INTER); 2721 %} 2722 2723 // Integer Immediate: constant 'int -1' 2724 operand immI_minus1() %{ 2725 predicate(n->get_int() == -1); 2726 match(ConI); 2727 op_cost(1); 2728 format %{ %} 2729 interface(CONST_INTER); 2730 %} 2731 2732 // Integer Immediate: constant, but not 'int 0' nor 'int -1'. 2733 operand immI_n0m1() %{ 2734 predicate(n->get_int() != 0 && n->get_int() != -1); 2735 match(ConI); 2736 op_cost(1); 2737 format %{ %} 2738 interface(CONST_INTER); 2739 %} 2740 2741 //------------------------------------------- 2742 // UNSIGNED INT immediate operands 2743 //------------------------------------------- 2744 2745 // Unsigned Integer Immediate: 32-bit 2746 operand uimmI() %{ 2747 match(ConI); 2748 op_cost(1); 2749 format %{ %} 2750 interface(CONST_INTER); 2751 %} 2752 2753 // Unsigned Integer Immediate: 16-bit 2754 operand uimmI16() %{ 2755 predicate(Immediate::is_uimm16(n->get_int())); 2756 match(ConI); 2757 op_cost(1); 2758 format %{ %} 2759 interface(CONST_INTER); 2760 %} 2761 2762 // Unsigned Integer Immediate: 12-bit 2763 operand uimmI12() %{ 2764 predicate(Immediate::is_uimm12(n->get_int())); 2765 match(ConI); 2766 op_cost(1); 2767 format %{ %} 2768 interface(CONST_INTER); 2769 %} 2770 2771 // Unsigned Integer Immediate: 12-bit 2772 operand uimmI8() %{ 2773 predicate(Immediate::is_uimm8(n->get_int())); 2774 match(ConI); 2775 op_cost(1); 2776 format %{ %} 2777 interface(CONST_INTER); 2778 %} 2779 2780 // Integer Immediate: 6-bit 2781 operand uimmI6() %{ 2782 predicate(Immediate::is_uimm(n->get_int(), 6)); 2783 match(ConI); 2784 op_cost(1); 2785 format %{ %} 2786 interface(CONST_INTER); 2787 %} 2788 2789 // Integer Immediate: 5-bit 2790 operand uimmI5() %{ 2791 predicate(Immediate::is_uimm(n->get_int(), 5)); 2792 match(ConI); 2793 op_cost(1); 2794 format %{ %} 2795 interface(CONST_INTER); 2796 %} 2797 2798 // Length for SS instructions, given in DWs, 2799 // possible range [1..512], i.e. [8..4096] Bytes 2800 // used range [1..256], i.e. [8..2048] Bytes 2801 // operand type int 2802 // Unsigned Integer Immediate: 9-bit 2803 operand SSlenDW() %{ 2804 predicate(Immediate::is_uimm8(n->get_long()-1)); 2805 match(ConL); 2806 op_cost(1); 2807 format %{ %} 2808 interface(CONST_INTER); 2809 %} 2810 2811 //------------------------------------------ 2812 // (UN)SIGNED INT specific values 2813 //------------------------------------------ 2814 2815 // Integer Immediate: the value 1 2816 operand immI_1() %{ 2817 predicate(n->get_int() == 1); 2818 match(ConI); 2819 op_cost(1); 2820 format %{ %} 2821 interface(CONST_INTER); 2822 %} 2823 2824 // Integer Immediate: the value 16. 2825 operand immI_16() %{ 2826 predicate(n->get_int() == 16); 2827 match(ConI); 2828 op_cost(1); 2829 format %{ %} 2830 interface(CONST_INTER); 2831 %} 2832 2833 // Integer Immediate: the value 24. 2834 operand immI_24() %{ 2835 predicate(n->get_int() == 24); 2836 match(ConI); 2837 op_cost(1); 2838 format %{ %} 2839 interface(CONST_INTER); 2840 %} 2841 2842 // Integer Immediate: the value 255 2843 operand immI_255() %{ 2844 predicate(n->get_int() == 255); 2845 match(ConI); 2846 op_cost(1); 2847 format %{ %} 2848 interface(CONST_INTER); 2849 %} 2850 2851 // Integer Immediate: the values 32-63 2852 operand immI_32_63() %{ 2853 predicate(n->get_int() >= 32 && n->get_int() <= 63); 2854 match(ConI); 2855 op_cost(1); 2856 format %{ %} 2857 interface(CONST_INTER); 2858 %} 2859 2860 // Unsigned Integer Immediate: LL-part, extended by 1s. 2861 operand uimmI_LL1() %{ 2862 predicate((n->get_int() & 0xFFFF0000) == 0xFFFF0000); 2863 match(ConI); 2864 op_cost(1); 2865 format %{ %} 2866 interface(CONST_INTER); 2867 %} 2868 2869 // Unsigned Integer Immediate: LH-part, extended by 1s. 2870 operand uimmI_LH1() %{ 2871 predicate((n->get_int() & 0xFFFF) == 0xFFFF); 2872 match(ConI); 2873 op_cost(1); 2874 format %{ %} 2875 interface(CONST_INTER); 2876 %} 2877 2878 //------------------------------------------ 2879 // SIGNED LONG immediate operands 2880 //------------------------------------------ 2881 2882 operand immL() %{ 2883 match(ConL); 2884 op_cost(1); 2885 format %{ %} 2886 interface(CONST_INTER); 2887 %} 2888 2889 // Long Immediate: 32-bit 2890 operand immL32() %{ 2891 predicate(Immediate::is_simm32(n->get_long())); 2892 match(ConL); 2893 op_cost(1); 2894 format %{ %} 2895 interface(CONST_INTER); 2896 %} 2897 2898 // Long Immediate: 20-bit 2899 operand immL20() %{ 2900 predicate(Immediate::is_simm20(n->get_long())); 2901 match(ConL); 2902 op_cost(1); 2903 format %{ %} 2904 interface(CONST_INTER); 2905 %} 2906 2907 // Long Immediate: 16-bit 2908 operand immL16() %{ 2909 predicate(Immediate::is_simm16(n->get_long())); 2910 match(ConL); 2911 op_cost(1); 2912 format %{ %} 2913 interface(CONST_INTER); 2914 %} 2915 2916 // Long Immediate: 8-bit 2917 operand immL8() %{ 2918 predicate(Immediate::is_simm8(n->get_long())); 2919 match(ConL); 2920 op_cost(1); 2921 format %{ %} 2922 interface(CONST_INTER); 2923 %} 2924 2925 //-------------------------------------------- 2926 // UNSIGNED LONG immediate operands 2927 //-------------------------------------------- 2928 2929 operand uimmL32() %{ 2930 predicate(Immediate::is_uimm32(n->get_long())); 2931 match(ConL); 2932 op_cost(1); 2933 format %{ %} 2934 interface(CONST_INTER); 2935 %} 2936 2937 // Unsigned Long Immediate: 16-bit 2938 operand uimmL16() %{ 2939 predicate(Immediate::is_uimm16(n->get_long())); 2940 match(ConL); 2941 op_cost(1); 2942 format %{ %} 2943 interface(CONST_INTER); 2944 %} 2945 2946 // Unsigned Long Immediate: 12-bit 2947 operand uimmL12() %{ 2948 predicate(Immediate::is_uimm12(n->get_long())); 2949 match(ConL); 2950 op_cost(1); 2951 format %{ %} 2952 interface(CONST_INTER); 2953 %} 2954 2955 // Unsigned Long Immediate: 8-bit 2956 operand uimmL8() %{ 2957 predicate(Immediate::is_uimm8(n->get_long())); 2958 match(ConL); 2959 op_cost(1); 2960 format %{ %} 2961 interface(CONST_INTER); 2962 %} 2963 2964 //------------------------------------------- 2965 // (UN)SIGNED LONG specific values 2966 //------------------------------------------- 2967 2968 // Long Immediate: the value FF 2969 operand immL_FF() %{ 2970 predicate(n->get_long() == 0xFFL); 2971 match(ConL); 2972 op_cost(1); 2973 format %{ %} 2974 interface(CONST_INTER); 2975 %} 2976 2977 // Long Immediate: the value FFFF 2978 operand immL_FFFF() %{ 2979 predicate(n->get_long() == 0xFFFFL); 2980 match(ConL); 2981 op_cost(1); 2982 format %{ %} 2983 interface(CONST_INTER); 2984 %} 2985 2986 // Long Immediate: the value FFFFFFFF 2987 operand immL_FFFFFFFF() %{ 2988 predicate(n->get_long() == 0xFFFFFFFFL); 2989 match(ConL); 2990 op_cost(1); 2991 format %{ %} 2992 interface(CONST_INTER); 2993 %} 2994 2995 operand immL_0() %{ 2996 predicate(n->get_long() == 0L); 2997 match(ConL); 2998 op_cost(1); 2999 format %{ %} 3000 interface(CONST_INTER); 3001 %} 3002 3003 // Unsigned Long Immediate: LL-part, extended by 1s. 3004 operand uimmL_LL1() %{ 3005 predicate((n->get_long() & 0xFFFFFFFFFFFF0000L) == 0xFFFFFFFFFFFF0000L); 3006 match(ConL); 3007 op_cost(1); 3008 format %{ %} 3009 interface(CONST_INTER); 3010 %} 3011 3012 // Unsigned Long Immediate: LH-part, extended by 1s. 3013 operand uimmL_LH1() %{ 3014 predicate((n->get_long() & 0xFFFFFFFF0000FFFFL) == 0xFFFFFFFF0000FFFFL); 3015 match(ConL); 3016 op_cost(1); 3017 format %{ %} 3018 interface(CONST_INTER); 3019 %} 3020 3021 // Unsigned Long Immediate: HL-part, extended by 1s. 3022 operand uimmL_HL1() %{ 3023 predicate((n->get_long() & 0xFFFF0000FFFFFFFFL) == 0xFFFF0000FFFFFFFFL); 3024 match(ConL); 3025 op_cost(1); 3026 format %{ %} 3027 interface(CONST_INTER); 3028 %} 3029 3030 // Unsigned Long Immediate: HH-part, extended by 1s. 3031 operand uimmL_HH1() %{ 3032 predicate((n->get_long() & 0xFFFFFFFFFFFFL) == 0xFFFFFFFFFFFFL); 3033 match(ConL); 3034 op_cost(1); 3035 format %{ %} 3036 interface(CONST_INTER); 3037 %} 3038 3039 // Long Immediate: low 32-bit mask 3040 operand immL_32bits() %{ 3041 predicate(n->get_long() == 0xFFFFFFFFL); 3042 match(ConL); 3043 op_cost(1); 3044 format %{ %} 3045 interface(CONST_INTER); 3046 %} 3047 3048 //-------------------------------------- 3049 // POINTER immediate operands 3050 //-------------------------------------- 3051 3052 // Pointer Immediate: 64-bit 3053 operand immP() %{ 3054 match(ConP); 3055 op_cost(1); 3056 format %{ %} 3057 interface(CONST_INTER); 3058 %} 3059 3060 // Pointer Immediate: 32-bit 3061 operand immP32() %{ 3062 predicate(Immediate::is_uimm32(n->get_ptr())); 3063 match(ConP); 3064 op_cost(1); 3065 format %{ %} 3066 interface(CONST_INTER); 3067 %} 3068 3069 // Pointer Immediate: 16-bit 3070 operand immP16() %{ 3071 predicate(Immediate::is_uimm16(n->get_ptr())); 3072 match(ConP); 3073 op_cost(1); 3074 format %{ %} 3075 interface(CONST_INTER); 3076 %} 3077 3078 // Pointer Immediate: 8-bit 3079 operand immP8() %{ 3080 predicate(Immediate::is_uimm8(n->get_ptr())); 3081 match(ConP); 3082 op_cost(1); 3083 format %{ %} 3084 interface(CONST_INTER); 3085 %} 3086 3087 //----------------------------------- 3088 // POINTER specific values 3089 //----------------------------------- 3090 3091 // Pointer Immediate: NULL 3092 operand immP0() %{ 3093 predicate(n->get_ptr() == 0); 3094 match(ConP); 3095 op_cost(1); 3096 format %{ %} 3097 interface(CONST_INTER); 3098 %} 3099 3100 //--------------------------------------------- 3101 // NARROW POINTER immediate operands 3102 //--------------------------------------------- 3103 3104 // Narrow Pointer Immediate 3105 operand immN() %{ 3106 match(ConN); 3107 op_cost(1); 3108 format %{ %} 3109 interface(CONST_INTER); 3110 %} 3111 3112 operand immNKlass() %{ 3113 match(ConNKlass); 3114 op_cost(1); 3115 format %{ %} 3116 interface(CONST_INTER); 3117 %} 3118 3119 // Narrow Pointer Immediate 3120 operand immN8() %{ 3121 predicate(Immediate::is_uimm8(n->get_narrowcon())); 3122 match(ConN); 3123 op_cost(1); 3124 format %{ %} 3125 interface(CONST_INTER); 3126 %} 3127 3128 // Narrow NULL Pointer Immediate 3129 operand immN0() %{ 3130 predicate(n->get_narrowcon() == 0); 3131 match(ConN); 3132 op_cost(1); 3133 format %{ %} 3134 interface(CONST_INTER); 3135 %} 3136 3137 // FLOAT and DOUBLE immediate operands 3138 3139 // Double Immediate 3140 operand immD() %{ 3141 match(ConD); 3142 op_cost(1); 3143 format %{ %} 3144 interface(CONST_INTER); 3145 %} 3146 3147 // Double Immediate: +-0 3148 operand immDpm0() %{ 3149 predicate(n->getd() == 0); 3150 match(ConD); 3151 op_cost(1); 3152 format %{ %} 3153 interface(CONST_INTER); 3154 %} 3155 3156 // Double Immediate: +0 3157 operand immDp0() %{ 3158 predicate(jlong_cast(n->getd()) == 0); 3159 match(ConD); 3160 op_cost(1); 3161 format %{ %} 3162 interface(CONST_INTER); 3163 %} 3164 3165 // Float Immediate 3166 operand immF() %{ 3167 match(ConF); 3168 op_cost(1); 3169 format %{ %} 3170 interface(CONST_INTER); 3171 %} 3172 3173 // Float Immediate: +-0 3174 operand immFpm0() %{ 3175 predicate(n->getf() == 0); 3176 match(ConF); 3177 op_cost(1); 3178 format %{ %} 3179 interface(CONST_INTER); 3180 %} 3181 3182 // Float Immediate: +0 3183 operand immFp0() %{ 3184 predicate(jint_cast(n->getf()) == 0); 3185 match(ConF); 3186 op_cost(1); 3187 format %{ %} 3188 interface(CONST_INTER); 3189 %} 3190 3191 // End of Immediate Operands 3192 3193 // Integer Register Operands 3194 // Integer Register 3195 operand iRegI() %{ 3196 constraint(ALLOC_IN_RC(z_int_reg)); 3197 match(RegI); 3198 match(noArg_iRegI); 3199 match(rarg1RegI); 3200 match(rarg2RegI); 3201 match(rarg3RegI); 3202 match(rarg4RegI); 3203 match(rarg5RegI); 3204 match(noOdd_iRegI); 3205 match(revenRegI); 3206 match(roddRegI); 3207 format %{ %} 3208 interface(REG_INTER); 3209 %} 3210 3211 operand noArg_iRegI() %{ 3212 constraint(ALLOC_IN_RC(z_no_arg_int_reg)); 3213 match(RegI); 3214 format %{ %} 3215 interface(REG_INTER); 3216 %} 3217 3218 // revenRegI and roddRegI constitute and even-odd-pair. 3219 operand revenRegI() %{ 3220 constraint(ALLOC_IN_RC(z_rarg3_int_reg)); 3221 match(iRegI); 3222 format %{ %} 3223 interface(REG_INTER); 3224 %} 3225 3226 // revenRegI and roddRegI constitute and even-odd-pair. 3227 operand roddRegI() %{ 3228 constraint(ALLOC_IN_RC(z_rarg4_int_reg)); 3229 match(iRegI); 3230 format %{ %} 3231 interface(REG_INTER); 3232 %} 3233 3234 operand rarg1RegI() %{ 3235 constraint(ALLOC_IN_RC(z_rarg1_int_reg)); 3236 match(iRegI); 3237 format %{ %} 3238 interface(REG_INTER); 3239 %} 3240 3241 operand rarg2RegI() %{ 3242 constraint(ALLOC_IN_RC(z_rarg2_int_reg)); 3243 match(iRegI); 3244 format %{ %} 3245 interface(REG_INTER); 3246 %} 3247 3248 operand rarg3RegI() %{ 3249 constraint(ALLOC_IN_RC(z_rarg3_int_reg)); 3250 match(iRegI); 3251 format %{ %} 3252 interface(REG_INTER); 3253 %} 3254 3255 operand rarg4RegI() %{ 3256 constraint(ALLOC_IN_RC(z_rarg4_int_reg)); 3257 match(iRegI); 3258 format %{ %} 3259 interface(REG_INTER); 3260 %} 3261 3262 operand rarg5RegI() %{ 3263 constraint(ALLOC_IN_RC(z_rarg5_int_reg)); 3264 match(iRegI); 3265 format %{ %} 3266 interface(REG_INTER); 3267 %} 3268 3269 operand noOdd_iRegI() %{ 3270 constraint(ALLOC_IN_RC(z_no_odd_int_reg)); 3271 match(RegI); 3272 match(revenRegI); 3273 format %{ %} 3274 interface(REG_INTER); 3275 %} 3276 3277 // Pointer Register 3278 operand iRegP() %{ 3279 constraint(ALLOC_IN_RC(z_ptr_reg)); 3280 match(RegP); 3281 match(noArg_iRegP); 3282 match(rarg1RegP); 3283 match(rarg2RegP); 3284 match(rarg3RegP); 3285 match(rarg4RegP); 3286 match(rarg5RegP); 3287 match(revenRegP); 3288 match(roddRegP); 3289 format %{ %} 3290 interface(REG_INTER); 3291 %} 3292 3293 // thread operand 3294 operand threadRegP() %{ 3295 constraint(ALLOC_IN_RC(z_thread_ptr_reg)); 3296 match(RegP); 3297 format %{ "Z_THREAD" %} 3298 interface(REG_INTER); 3299 %} 3300 3301 operand noArg_iRegP() %{ 3302 constraint(ALLOC_IN_RC(z_no_arg_ptr_reg)); 3303 match(iRegP); 3304 format %{ %} 3305 interface(REG_INTER); 3306 %} 3307 3308 operand rarg1RegP() %{ 3309 constraint(ALLOC_IN_RC(z_rarg1_ptr_reg)); 3310 match(iRegP); 3311 format %{ %} 3312 interface(REG_INTER); 3313 %} 3314 3315 operand rarg2RegP() %{ 3316 constraint(ALLOC_IN_RC(z_rarg2_ptr_reg)); 3317 match(iRegP); 3318 format %{ %} 3319 interface(REG_INTER); 3320 %} 3321 3322 operand rarg3RegP() %{ 3323 constraint(ALLOC_IN_RC(z_rarg3_ptr_reg)); 3324 match(iRegP); 3325 format %{ %} 3326 interface(REG_INTER); 3327 %} 3328 3329 operand rarg4RegP() %{ 3330 constraint(ALLOC_IN_RC(z_rarg4_ptr_reg)); 3331 match(iRegP); 3332 format %{ %} 3333 interface(REG_INTER); 3334 %} 3335 3336 operand rarg5RegP() %{ 3337 constraint(ALLOC_IN_RC(z_rarg5_ptr_reg)); 3338 match(iRegP); 3339 format %{ %} 3340 interface(REG_INTER); 3341 %} 3342 3343 operand memoryRegP() %{ 3344 constraint(ALLOC_IN_RC(z_memory_ptr_reg)); 3345 match(RegP); 3346 match(iRegP); 3347 match(threadRegP); 3348 format %{ %} 3349 interface(REG_INTER); 3350 %} 3351 3352 // revenRegP and roddRegP constitute and even-odd-pair. 3353 operand revenRegP() %{ 3354 constraint(ALLOC_IN_RC(z_rarg3_ptr_reg)); 3355 match(iRegP); 3356 format %{ %} 3357 interface(REG_INTER); 3358 %} 3359 3360 // revenRegP and roddRegP constitute and even-odd-pair. 3361 operand roddRegP() %{ 3362 constraint(ALLOC_IN_RC(z_rarg4_ptr_reg)); 3363 match(iRegP); 3364 format %{ %} 3365 interface(REG_INTER); 3366 %} 3367 3368 operand lock_ptr_RegP() %{ 3369 constraint(ALLOC_IN_RC(z_lock_ptr_reg)); 3370 match(RegP); 3371 format %{ %} 3372 interface(REG_INTER); 3373 %} 3374 3375 operand rscratch2RegP() %{ 3376 constraint(ALLOC_IN_RC(z_rscratch2_bits64_reg)); 3377 match(RegP); 3378 format %{ %} 3379 interface(REG_INTER); 3380 %} 3381 3382 operand iRegN() %{ 3383 constraint(ALLOC_IN_RC(z_int_reg)); 3384 match(RegN); 3385 match(noArg_iRegN); 3386 match(rarg1RegN); 3387 match(rarg2RegN); 3388 match(rarg3RegN); 3389 match(rarg4RegN); 3390 match(rarg5RegN); 3391 format %{ %} 3392 interface(REG_INTER); 3393 %} 3394 3395 operand noArg_iRegN() %{ 3396 constraint(ALLOC_IN_RC(z_no_arg_int_reg)); 3397 match(iRegN); 3398 format %{ %} 3399 interface(REG_INTER); 3400 %} 3401 3402 operand rarg1RegN() %{ 3403 constraint(ALLOC_IN_RC(z_rarg1_int_reg)); 3404 match(iRegN); 3405 format %{ %} 3406 interface(REG_INTER); 3407 %} 3408 3409 operand rarg2RegN() %{ 3410 constraint(ALLOC_IN_RC(z_rarg2_int_reg)); 3411 match(iRegN); 3412 format %{ %} 3413 interface(REG_INTER); 3414 %} 3415 3416 operand rarg3RegN() %{ 3417 constraint(ALLOC_IN_RC(z_rarg3_int_reg)); 3418 match(iRegN); 3419 format %{ %} 3420 interface(REG_INTER); 3421 %} 3422 3423 operand rarg4RegN() %{ 3424 constraint(ALLOC_IN_RC(z_rarg4_int_reg)); 3425 match(iRegN); 3426 format %{ %} 3427 interface(REG_INTER); 3428 %} 3429 3430 operand rarg5RegN() %{ 3431 constraint(ALLOC_IN_RC(z_rarg5_ptrN_reg)); 3432 match(iRegN); 3433 format %{ %} 3434 interface(REG_INTER); 3435 %} 3436 3437 // Long Register 3438 operand iRegL() %{ 3439 constraint(ALLOC_IN_RC(z_long_reg)); 3440 match(RegL); 3441 match(revenRegL); 3442 match(roddRegL); 3443 match(allRoddRegL); 3444 match(rarg1RegL); 3445 match(rarg5RegL); 3446 format %{ %} 3447 interface(REG_INTER); 3448 %} 3449 3450 // revenRegL and roddRegL constitute and even-odd-pair. 3451 operand revenRegL() %{ 3452 constraint(ALLOC_IN_RC(z_rarg3_long_reg)); 3453 match(iRegL); 3454 format %{ %} 3455 interface(REG_INTER); 3456 %} 3457 3458 // revenRegL and roddRegL constitute and even-odd-pair. 3459 operand roddRegL() %{ 3460 constraint(ALLOC_IN_RC(z_rarg4_long_reg)); 3461 match(iRegL); 3462 format %{ %} 3463 interface(REG_INTER); 3464 %} 3465 3466 // available odd registers for iRegL 3467 operand allRoddRegL() %{ 3468 constraint(ALLOC_IN_RC(z_long_odd_reg)); 3469 match(iRegL); 3470 format %{ %} 3471 interface(REG_INTER); 3472 %} 3473 3474 operand rarg1RegL() %{ 3475 constraint(ALLOC_IN_RC(z_rarg1_long_reg)); 3476 match(iRegL); 3477 format %{ %} 3478 interface(REG_INTER); 3479 %} 3480 3481 operand rarg5RegL() %{ 3482 constraint(ALLOC_IN_RC(z_rarg5_long_reg)); 3483 match(iRegL); 3484 format %{ %} 3485 interface(REG_INTER); 3486 %} 3487 3488 // Condition Code Flag Registers 3489 operand flagsReg() %{ 3490 constraint(ALLOC_IN_RC(z_condition_reg)); 3491 match(RegFlags); 3492 format %{ "CR" %} 3493 interface(REG_INTER); 3494 %} 3495 3496 // Condition Code Flag Registers for rules with result tuples 3497 operand TD_flagsReg() %{ 3498 constraint(ALLOC_IN_RC(z_condition_reg)); 3499 match(RegFlags); 3500 format %{ "CR" %} 3501 interface(REG_TUPLE_DEST_INTER); 3502 %} 3503 3504 operand regD() %{ 3505 constraint(ALLOC_IN_RC(z_dbl_reg)); 3506 match(RegD); 3507 format %{ %} 3508 interface(REG_INTER); 3509 %} 3510 3511 operand rscratchRegD() %{ 3512 constraint(ALLOC_IN_RC(z_rscratch1_dbl_reg)); 3513 match(RegD); 3514 format %{ %} 3515 interface(REG_INTER); 3516 %} 3517 3518 operand regF() %{ 3519 constraint(ALLOC_IN_RC(z_flt_reg)); 3520 match(RegF); 3521 format %{ %} 3522 interface(REG_INTER); 3523 %} 3524 3525 operand rscratchRegF() %{ 3526 constraint(ALLOC_IN_RC(z_rscratch1_flt_reg)); 3527 match(RegF); 3528 format %{ %} 3529 interface(REG_INTER); 3530 %} 3531 3532 // Special Registers 3533 3534 // Method Register 3535 operand inline_cache_regP(iRegP reg) %{ 3536 constraint(ALLOC_IN_RC(z_r9_regP)); // inline_cache_reg 3537 match(reg); 3538 format %{ %} 3539 interface(REG_INTER); 3540 %} 3541 3542 operand compiler_method_oop_regP(iRegP reg) %{ 3543 constraint(ALLOC_IN_RC(z_r1_RegP)); // compiler_method_oop_reg 3544 match(reg); 3545 format %{ %} 3546 interface(REG_INTER); 3547 %} 3548 3549 operand interpreter_method_oop_regP(iRegP reg) %{ 3550 constraint(ALLOC_IN_RC(z_r9_regP)); // interpreter_method_oop_reg 3551 match(reg); 3552 format %{ %} 3553 interface(REG_INTER); 3554 %} 3555 3556 // Operands to remove register moves in unscaled mode. 3557 // Match read/write registers with an EncodeP node if neither shift nor add are required. 3558 operand iRegP2N(iRegP reg) %{ 3559 predicate(CompressedOops::shift() == 0 && _leaf->as_EncodeP()->in(0) == NULL); 3560 constraint(ALLOC_IN_RC(z_memory_ptr_reg)); 3561 match(EncodeP reg); 3562 format %{ "$reg" %} 3563 interface(REG_INTER) 3564 %} 3565 3566 operand iRegN2P(iRegN reg) %{ 3567 predicate(CompressedOops::base() == NULL && CompressedOops::shift() == 0 && 3568 _leaf->as_DecodeN()->in(0) == NULL); 3569 constraint(ALLOC_IN_RC(z_memory_ptr_reg)); 3570 match(DecodeN reg); 3571 format %{ "$reg" %} 3572 interface(REG_INTER) 3573 %} 3574 3575 3576 //----------Complex Operands--------------------------------------------------- 3577 3578 // Indirect Memory Reference 3579 operand indirect(memoryRegP base) %{ 3580 constraint(ALLOC_IN_RC(z_memory_ptr_reg)); 3581 match(base); 3582 op_cost(1); 3583 format %{ "#0[,$base]" %} 3584 interface(MEMORY_INTER) %{ 3585 base($base); 3586 index(0xffffFFFF); // noreg 3587 scale(0x0); 3588 disp(0x0); 3589 %} 3590 %} 3591 3592 // Indirect with Offset (long) 3593 operand indOffset20(memoryRegP base, immL20 offset) %{ 3594 constraint(ALLOC_IN_RC(z_memory_ptr_reg)); 3595 match(AddP base offset); 3596 op_cost(1); 3597 format %{ "$offset[,$base]" %} 3598 interface(MEMORY_INTER) %{ 3599 base($base); 3600 index(0xffffFFFF); // noreg 3601 scale(0x0); 3602 disp($offset); 3603 %} 3604 %} 3605 3606 operand indOffset20Narrow(iRegN base, immL20 offset) %{ 3607 predicate(Matcher::narrow_oop_use_complex_address()); 3608 constraint(ALLOC_IN_RC(z_memory_ptr_reg)); 3609 match(AddP (DecodeN base) offset); 3610 op_cost(1); 3611 format %{ "$offset[,$base]" %} 3612 interface(MEMORY_INTER) %{ 3613 base($base); 3614 index(0xffffFFFF); // noreg 3615 scale(0x0); 3616 disp($offset); 3617 %} 3618 %} 3619 3620 // Indirect with Offset (short) 3621 operand indOffset12(memoryRegP base, uimmL12 offset) %{ 3622 constraint(ALLOC_IN_RC(z_memory_ptr_reg)); 3623 match(AddP base offset); 3624 op_cost(1); 3625 format %{ "$offset[[,$base]]" %} 3626 interface(MEMORY_INTER) %{ 3627 base($base); 3628 index(0xffffFFFF); // noreg 3629 scale(0x0); 3630 disp($offset); 3631 %} 3632 %} 3633 3634 operand indOffset12Narrow(iRegN base, uimmL12 offset) %{ 3635 predicate(Matcher::narrow_oop_use_complex_address()); 3636 constraint(ALLOC_IN_RC(z_memory_ptr_reg)); 3637 match(AddP (DecodeN base) offset); 3638 op_cost(1); 3639 format %{ "$offset[[,$base]]" %} 3640 interface(MEMORY_INTER) %{ 3641 base($base); 3642 index(0xffffFFFF); // noreg 3643 scale(0x0); 3644 disp($offset); 3645 %} 3646 %} 3647 3648 // Indirect with Register Index 3649 operand indIndex(memoryRegP base, iRegL index) %{ 3650 constraint(ALLOC_IN_RC(z_memory_ptr_reg)); 3651 match(AddP base index); 3652 op_cost(1); 3653 format %{ "#0[($index,$base)]" %} 3654 interface(MEMORY_INTER) %{ 3655 base($base); 3656 index($index); 3657 scale(0x0); 3658 disp(0x0); 3659 %} 3660 %} 3661 3662 // Indirect with Offset (long) and index 3663 operand indOffset20index(memoryRegP base, immL20 offset, iRegL index) %{ 3664 constraint(ALLOC_IN_RC(z_memory_ptr_reg)); 3665 match(AddP (AddP base index) offset); 3666 op_cost(1); 3667 format %{ "$offset[($index,$base)]" %} 3668 interface(MEMORY_INTER) %{ 3669 base($base); 3670 index($index); 3671 scale(0x0); 3672 disp($offset); 3673 %} 3674 %} 3675 3676 operand indOffset20indexNarrow(iRegN base, immL20 offset, iRegL index) %{ 3677 predicate(Matcher::narrow_oop_use_complex_address()); 3678 constraint(ALLOC_IN_RC(z_memory_ptr_reg)); 3679 match(AddP (AddP (DecodeN base) index) offset); 3680 op_cost(1); 3681 format %{ "$offset[($index,$base)]" %} 3682 interface(MEMORY_INTER) %{ 3683 base($base); 3684 index($index); 3685 scale(0x0); 3686 disp($offset); 3687 %} 3688 %} 3689 3690 // Indirect with Offset (short) and index 3691 operand indOffset12index(memoryRegP base, uimmL12 offset, iRegL index) %{ 3692 constraint(ALLOC_IN_RC(z_memory_ptr_reg)); 3693 match(AddP (AddP base index) offset); 3694 op_cost(1); 3695 format %{ "$offset[[($index,$base)]]" %} 3696 interface(MEMORY_INTER) %{ 3697 base($base); 3698 index($index); 3699 scale(0x0); 3700 disp($offset); 3701 %} 3702 %} 3703 3704 operand indOffset12indexNarrow(iRegN base, uimmL12 offset, iRegL index) %{ 3705 predicate(Matcher::narrow_oop_use_complex_address()); 3706 constraint(ALLOC_IN_RC(z_memory_ptr_reg)); 3707 match(AddP (AddP (DecodeN base) index) offset); 3708 op_cost(1); 3709 format %{ "$offset[[($index,$base)]]" %} 3710 interface(MEMORY_INTER) %{ 3711 base($base); 3712 index($index); 3713 scale(0x0); 3714 disp($offset); 3715 %} 3716 %} 3717 3718 //----------Special Memory Operands-------------------------------------------- 3719 3720 // Stack Slot Operand 3721 // This operand is used for loading and storing temporary values on 3722 // the stack where a match requires a value to flow through memory. 3723 operand stackSlotI(sRegI reg) %{ 3724 constraint(ALLOC_IN_RC(stack_slots)); 3725 op_cost(1); 3726 format %{ "[$reg(stackSlotI)]" %} 3727 interface(MEMORY_INTER) %{ 3728 base(0xf); // Z_SP 3729 index(0xffffFFFF); // noreg 3730 scale(0x0); 3731 disp($reg); // stack offset 3732 %} 3733 %} 3734 3735 operand stackSlotP(sRegP reg) %{ 3736 constraint(ALLOC_IN_RC(stack_slots)); 3737 op_cost(1); 3738 format %{ "[$reg(stackSlotP)]" %} 3739 interface(MEMORY_INTER) %{ 3740 base(0xf); // Z_SP 3741 index(0xffffFFFF); // noreg 3742 scale(0x0); 3743 disp($reg); // Stack Offset 3744 %} 3745 %} 3746 3747 operand stackSlotF(sRegF reg) %{ 3748 constraint(ALLOC_IN_RC(stack_slots)); 3749 op_cost(1); 3750 format %{ "[$reg(stackSlotF)]" %} 3751 interface(MEMORY_INTER) %{ 3752 base(0xf); // Z_SP 3753 index(0xffffFFFF); // noreg 3754 scale(0x0); 3755 disp($reg); // Stack Offset 3756 %} 3757 %} 3758 3759 operand stackSlotD(sRegD reg) %{ 3760 constraint(ALLOC_IN_RC(stack_slots)); 3761 op_cost(1); 3762 //match(RegD); 3763 format %{ "[$reg(stackSlotD)]" %} 3764 interface(MEMORY_INTER) %{ 3765 base(0xf); // Z_SP 3766 index(0xffffFFFF); // noreg 3767 scale(0x0); 3768 disp($reg); // Stack Offset 3769 %} 3770 %} 3771 3772 operand stackSlotL(sRegL reg) %{ 3773 constraint(ALLOC_IN_RC(stack_slots)); 3774 op_cost(1); //match(RegL); 3775 format %{ "[$reg(stackSlotL)]" %} 3776 interface(MEMORY_INTER) %{ 3777 base(0xf); // Z_SP 3778 index(0xffffFFFF); // noreg 3779 scale(0x0); 3780 disp($reg); // Stack Offset 3781 %} 3782 %} 3783 3784 // Operands for expressing Control Flow 3785 // NOTE: Label is a predefined operand which should not be redefined in 3786 // the AD file. It is generically handled within the ADLC. 3787 3788 //----------Conditional Branch Operands---------------------------------------- 3789 // Comparison Op - This is the operation of the comparison, and is limited to 3790 // the following set of codes: 3791 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=) 3792 // 3793 // Other attributes of the comparison, such as unsignedness, are specified 3794 // by the comparison instruction that sets a condition code flags register. 3795 // That result is represented by a flags operand whose subtype is appropriate 3796 // to the unsignedness (etc.) of the comparison. 3797 // 3798 // Later, the instruction which matches both the Comparison Op (a Bool) and 3799 // the flags (produced by the Cmp) specifies the coding of the comparison op 3800 // by matching a specific subtype of Bool operand below. 3801 3802 // INT cmpOps for CompareAndBranch and CompareAndTrap instructions should not 3803 // have mask bit #3 set. 3804 operand cmpOpT() %{ 3805 match(Bool); 3806 format %{ "" %} 3807 interface(COND_INTER) %{ 3808 equal(0x8); // Assembler::bcondEqual 3809 not_equal(0x6); // Assembler::bcondNotEqual 3810 less(0x4); // Assembler::bcondLow 3811 greater_equal(0xa); // Assembler::bcondNotLow 3812 less_equal(0xc); // Assembler::bcondNotHigh 3813 greater(0x2); // Assembler::bcondHigh 3814 overflow(0x1); // Assembler::bcondOverflow 3815 no_overflow(0xe); // Assembler::bcondNotOverflow 3816 %} 3817 %} 3818 3819 // When used for floating point comparisons: unordered is treated as less. 3820 operand cmpOpF() %{ 3821 match(Bool); 3822 format %{ "" %} 3823 interface(COND_INTER) %{ 3824 equal(0x8); 3825 not_equal(0x7); // Includes 'unordered'. 3826 less(0x5); // Includes 'unordered'. 3827 greater_equal(0xa); 3828 less_equal(0xd); // Includes 'unordered'. 3829 greater(0x2); 3830 overflow(0x0); // Not meaningful on z/Architecture. 3831 no_overflow(0x0); // leave unchanged (zero) therefore 3832 %} 3833 %} 3834 3835 // "Regular" cmpOp for int comparisons, includes bit #3 (overflow). 3836 operand cmpOp() %{ 3837 match(Bool); 3838 format %{ "" %} 3839 interface(COND_INTER) %{ 3840 equal(0x8); 3841 not_equal(0x7); // Includes 'unordered'. 3842 less(0x5); // Includes 'unordered'. 3843 greater_equal(0xa); 3844 less_equal(0xd); // Includes 'unordered'. 3845 greater(0x2); 3846 overflow(0x1); // Assembler::bcondOverflow 3847 no_overflow(0xe); // Assembler::bcondNotOverflow 3848 %} 3849 %} 3850 3851 //----------OPERAND CLASSES---------------------------------------------------- 3852 // Operand Classes are groups of operands that are used to simplify 3853 // instruction definitions by not requiring the AD writer to specify 3854 // seperate instructions for every form of operand when the 3855 // instruction accepts multiple operand types with the same basic 3856 // encoding and format. The classic case of this is memory operands. 3857 // Indirect is not included since its use is limited to Compare & Swap 3858 3859 // Most general memory operand, allows base, index, and long displacement. 3860 opclass memory(indirect, indIndex, indOffset20, indOffset20Narrow, indOffset20index, indOffset20indexNarrow); 3861 opclass memoryRXY(indirect, indIndex, indOffset20, indOffset20Narrow, indOffset20index, indOffset20indexNarrow); 3862 3863 // General memory operand, allows base, index, and short displacement. 3864 opclass memoryRX(indirect, indIndex, indOffset12, indOffset12Narrow, indOffset12index, indOffset12indexNarrow); 3865 3866 // Memory operand, allows only base and long displacement. 3867 opclass memoryRSY(indirect, indOffset20, indOffset20Narrow); 3868 3869 // Memory operand, allows only base and short displacement. 3870 opclass memoryRS(indirect, indOffset12, indOffset12Narrow); 3871 3872 // Operand classes to match encode and decode. 3873 opclass iRegN_P2N(iRegN); 3874 opclass iRegP_N2P(iRegP); 3875 3876 3877 //----------PIPELINE----------------------------------------------------------- 3878 pipeline %{ 3879 3880 //----------ATTRIBUTES--------------------------------------------------------- 3881 attributes %{ 3882 // z/Architecture instructions are of length 2, 4, or 6 bytes. 3883 variable_size_instructions; 3884 instruction_unit_size = 2; 3885 3886 // Meaningless on z/Architecture. 3887 max_instructions_per_bundle = 1; 3888 3889 // The z/Architecture processor fetches 64 bytes... 3890 instruction_fetch_unit_size = 64; 3891 3892 // ...in one line. 3893 instruction_fetch_units = 1 3894 %} 3895 3896 //----------RESOURCES---------------------------------------------------------- 3897 // Resources are the functional units available to the machine. 3898 resources( 3899 Z_BR, // branch unit 3900 Z_CR, // condition unit 3901 Z_FX1, // integer arithmetic unit 1 3902 Z_FX2, // integer arithmetic unit 2 3903 Z_LDST1, // load/store unit 1 3904 Z_LDST2, // load/store unit 2 3905 Z_FP1, // float arithmetic unit 1 3906 Z_FP2, // float arithmetic unit 2 3907 Z_LDST = Z_LDST1 | Z_LDST2, 3908 Z_FX = Z_FX1 | Z_FX2, 3909 Z_FP = Z_FP1 | Z_FP2 3910 ); 3911 3912 //----------PIPELINE DESCRIPTION----------------------------------------------- 3913 // Pipeline Description specifies the stages in the machine's pipeline. 3914 pipe_desc( 3915 // TODO: adapt 3916 Z_IF, // instruction fetch 3917 Z_IC, 3918 Z_D0, // decode 3919 Z_D1, // decode 3920 Z_D2, // decode 3921 Z_D3, // decode 3922 Z_Xfer1, 3923 Z_GD, // group definition 3924 Z_MP, // map 3925 Z_ISS, // issue 3926 Z_RF, // resource fetch 3927 Z_EX1, // execute (all units) 3928 Z_EX2, // execute (FP, LDST) 3929 Z_EX3, // execute (FP, LDST) 3930 Z_EX4, // execute (FP) 3931 Z_EX5, // execute (FP) 3932 Z_EX6, // execute (FP) 3933 Z_WB, // write back 3934 Z_Xfer2, 3935 Z_CP 3936 ); 3937 3938 //----------PIPELINE CLASSES--------------------------------------------------- 3939 // Pipeline Classes describe the stages in which input and output are 3940 // referenced by the hardware pipeline. 3941 3942 // Providing the `ins_pipe' declarations in the instruction 3943 // specifications seems to be of little use. So we use 3944 // `pipe_class_dummy' for all our instructions at present. 3945 pipe_class pipe_class_dummy() %{ 3946 single_instruction; 3947 fixed_latency(4); 3948 %} 3949 3950 // SIGTRAP based implicit range checks in compiled code. 3951 // Currently, no pipe classes are used on z/Architecture. 3952 pipe_class pipe_class_trap() %{ 3953 single_instruction; 3954 %} 3955 3956 pipe_class pipe_class_fx_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 3957 single_instruction; 3958 dst : Z_EX1(write); 3959 src1 : Z_RF(read); 3960 src2 : Z_RF(read); 3961 Z_FX : Z_RF; 3962 %} 3963 3964 pipe_class pipe_class_ldst(iRegP dst, memory mem) %{ 3965 single_instruction; 3966 mem : Z_RF(read); 3967 dst : Z_WB(write); 3968 Z_LDST : Z_RF; 3969 %} 3970 3971 define %{ 3972 MachNop = pipe_class_dummy; 3973 %} 3974 3975 %} 3976 3977 //----------INSTRUCTIONS------------------------------------------------------- 3978 3979 //---------- Chain stack slots between similar types -------- 3980 3981 // Load integer from stack slot. 3982 instruct stkI_to_regI(iRegI dst, stackSlotI src) %{ 3983 match(Set dst src); 3984 ins_cost(MEMORY_REF_COST); 3985 // TODO: s390 port size(FIXED_SIZE); 3986 format %{ "L $dst,$src\t # stk reload int" %} 3987 opcode(L_ZOPC); 3988 ins_encode(z_form_rt_mem(dst, src)); 3989 ins_pipe(pipe_class_dummy); 3990 %} 3991 3992 // Store integer to stack slot. 3993 instruct regI_to_stkI(stackSlotI dst, iRegI src) %{ 3994 match(Set dst src); 3995 ins_cost(MEMORY_REF_COST); 3996 // TODO: s390 port size(FIXED_SIZE); 3997 format %{ "ST $src,$dst\t # stk spill int" %} 3998 opcode(ST_ZOPC); 3999 ins_encode(z_form_rt_mem(src, dst)); // rs=rt 4000 ins_pipe(pipe_class_dummy); 4001 %} 4002 4003 // Load long from stack slot. 4004 instruct stkL_to_regL(iRegL dst, stackSlotL src) %{ 4005 match(Set dst src); 4006 ins_cost(MEMORY_REF_COST); 4007 // TODO: s390 port size(FIXED_SIZE); 4008 format %{ "LG $dst,$src\t # stk reload long" %} 4009 opcode(LG_ZOPC); 4010 ins_encode(z_form_rt_mem(dst, src)); 4011 ins_pipe(pipe_class_dummy); 4012 %} 4013 4014 // Store long to stack slot. 4015 instruct regL_to_stkL(stackSlotL dst, iRegL src) %{ 4016 match(Set dst src); 4017 ins_cost(MEMORY_REF_COST); 4018 size(6); 4019 format %{ "STG $src,$dst\t # stk spill long" %} 4020 opcode(STG_ZOPC); 4021 ins_encode(z_form_rt_mem(src, dst)); // rs=rt 4022 ins_pipe(pipe_class_dummy); 4023 %} 4024 4025 // Load pointer from stack slot, 64-bit encoding. 4026 instruct stkP_to_regP(iRegP dst, stackSlotP src) %{ 4027 match(Set dst src); 4028 ins_cost(MEMORY_REF_COST); 4029 // TODO: s390 port size(FIXED_SIZE); 4030 format %{ "LG $dst,$src\t # stk reload ptr" %} 4031 opcode(LG_ZOPC); 4032 ins_encode(z_form_rt_mem(dst, src)); 4033 ins_pipe(pipe_class_dummy); 4034 %} 4035 4036 // Store pointer to stack slot. 4037 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{ 4038 match(Set dst src); 4039 ins_cost(MEMORY_REF_COST); 4040 // TODO: s390 port size(FIXED_SIZE); 4041 format %{ "STG $src,$dst\t # stk spill ptr" %} 4042 opcode(STG_ZOPC); 4043 ins_encode(z_form_rt_mem(src, dst)); // rs=rt 4044 ins_pipe(pipe_class_dummy); 4045 %} 4046 4047 // Float types 4048 4049 // Load float value from stack slot. 4050 instruct stkF_to_regF(regF dst, stackSlotF src) %{ 4051 match(Set dst src); 4052 ins_cost(MEMORY_REF_COST); 4053 size(4); 4054 format %{ "LE(Y) $dst,$src\t # stk reload float" %} 4055 opcode(LE_ZOPC); 4056 ins_encode(z_form_rt_mem(dst, src)); 4057 ins_pipe(pipe_class_dummy); 4058 %} 4059 4060 // Store float value to stack slot. 4061 instruct regF_to_stkF(stackSlotF dst, regF src) %{ 4062 match(Set dst src); 4063 ins_cost(MEMORY_REF_COST); 4064 size(4); 4065 format %{ "STE(Y) $src,$dst\t # stk spill float" %} 4066 opcode(STE_ZOPC); 4067 ins_encode(z_form_rt_mem(src, dst)); 4068 ins_pipe(pipe_class_dummy); 4069 %} 4070 4071 // Load double value from stack slot. 4072 instruct stkD_to_regD(regD dst, stackSlotD src) %{ 4073 match(Set dst src); 4074 ins_cost(MEMORY_REF_COST); 4075 // TODO: s390 port size(FIXED_SIZE); 4076 format %{ "LD(Y) $dst,$src\t # stk reload double" %} 4077 opcode(LD_ZOPC); 4078 ins_encode(z_form_rt_mem(dst, src)); 4079 ins_pipe(pipe_class_dummy); 4080 %} 4081 4082 // Store double value to stack slot. 4083 instruct regD_to_stkD(stackSlotD dst, regD src) %{ 4084 match(Set dst src); 4085 ins_cost(MEMORY_REF_COST); 4086 size(4); 4087 format %{ "STD(Y) $src,$dst\t # stk spill double" %} 4088 opcode(STD_ZOPC); 4089 ins_encode(z_form_rt_mem(src, dst)); 4090 ins_pipe(pipe_class_dummy); 4091 %} 4092 4093 //----------Load/Store/Move Instructions--------------------------------------- 4094 4095 //----------Load Instructions-------------------------------------------------- 4096 4097 //------------------ 4098 // MEMORY 4099 //------------------ 4100 4101 // BYTE 4102 // Load Byte (8bit signed) 4103 instruct loadB(iRegI dst, memory mem) %{ 4104 match(Set dst (LoadB mem)); 4105 ins_cost(MEMORY_REF_COST); 4106 size(Z_DISP3_SIZE); 4107 format %{ "LB $dst, $mem\t # sign-extend byte to int" %} 4108 opcode(LB_ZOPC, LB_ZOPC); 4109 ins_encode(z_form_rt_mem_opt(dst, mem)); 4110 ins_pipe(pipe_class_dummy); 4111 %} 4112 4113 // Load Byte (8bit signed) 4114 instruct loadB2L(iRegL dst, memory mem) %{ 4115 match(Set dst (ConvI2L (LoadB mem))); 4116 ins_cost(MEMORY_REF_COST); 4117 size(Z_DISP3_SIZE); 4118 format %{ "LGB $dst, $mem\t # sign-extend byte to long" %} 4119 opcode(LGB_ZOPC, LGB_ZOPC); 4120 ins_encode(z_form_rt_mem_opt(dst, mem)); 4121 ins_pipe(pipe_class_dummy); 4122 %} 4123 4124 // Load Unsigned Byte (8bit UNsigned) into an int reg. 4125 instruct loadUB(iRegI dst, memory mem) %{ 4126 match(Set dst (LoadUB mem)); 4127 ins_cost(MEMORY_REF_COST); 4128 size(Z_DISP3_SIZE); 4129 format %{ "LLGC $dst,$mem\t # zero-extend byte to int" %} 4130 opcode(LLGC_ZOPC, LLGC_ZOPC); 4131 ins_encode(z_form_rt_mem_opt(dst, mem)); 4132 ins_pipe(pipe_class_dummy); 4133 %} 4134 4135 // Load Unsigned Byte (8bit UNsigned) into a Long Register. 4136 instruct loadUB2L(iRegL dst, memory mem) %{ 4137 match(Set dst (ConvI2L (LoadUB mem))); 4138 ins_cost(MEMORY_REF_COST); 4139 size(Z_DISP3_SIZE); 4140 format %{ "LLGC $dst,$mem\t # zero-extend byte to long" %} 4141 opcode(LLGC_ZOPC, LLGC_ZOPC); 4142 ins_encode(z_form_rt_mem_opt(dst, mem)); 4143 ins_pipe(pipe_class_dummy); 4144 %} 4145 4146 // CHAR/SHORT 4147 4148 // Load Short (16bit signed) 4149 instruct loadS(iRegI dst, memory mem) %{ 4150 match(Set dst (LoadS mem)); 4151 ins_cost(MEMORY_REF_COST); 4152 size(Z_DISP_SIZE); 4153 format %{ "LH(Y) $dst,$mem\t # sign-extend short to int" %} 4154 opcode(LHY_ZOPC, LH_ZOPC); 4155 ins_encode(z_form_rt_mem_opt(dst, mem)); 4156 ins_pipe(pipe_class_dummy); 4157 %} 4158 4159 // Load Short (16bit signed) 4160 instruct loadS2L(iRegL dst, memory mem) %{ 4161 match(Set dst (ConvI2L (LoadS mem))); 4162 ins_cost(MEMORY_REF_COST); 4163 size(Z_DISP3_SIZE); 4164 format %{ "LGH $dst,$mem\t # sign-extend short to long" %} 4165 opcode(LGH_ZOPC, LGH_ZOPC); 4166 ins_encode(z_form_rt_mem_opt(dst, mem)); 4167 ins_pipe(pipe_class_dummy); 4168 %} 4169 4170 // Load Char (16bit Unsigned) 4171 instruct loadUS(iRegI dst, memory mem) %{ 4172 match(Set dst (LoadUS mem)); 4173 ins_cost(MEMORY_REF_COST); 4174 size(Z_DISP3_SIZE); 4175 format %{ "LLGH $dst,$mem\t # zero-extend short to int" %} 4176 opcode(LLGH_ZOPC, LLGH_ZOPC); 4177 ins_encode(z_form_rt_mem_opt(dst, mem)); 4178 ins_pipe(pipe_class_dummy); 4179 %} 4180 4181 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register. 4182 instruct loadUS2L(iRegL dst, memory mem) %{ 4183 match(Set dst (ConvI2L (LoadUS mem))); 4184 ins_cost(MEMORY_REF_COST); 4185 size(Z_DISP3_SIZE); 4186 format %{ "LLGH $dst,$mem\t # zero-extend short to long" %} 4187 opcode(LLGH_ZOPC, LLGH_ZOPC); 4188 ins_encode(z_form_rt_mem_opt(dst, mem)); 4189 ins_pipe(pipe_class_dummy); 4190 %} 4191 4192 // INT 4193 4194 // Load Integer 4195 instruct loadI(iRegI dst, memory mem) %{ 4196 match(Set dst (LoadI mem)); 4197 ins_cost(MEMORY_REF_COST); 4198 size(Z_DISP_SIZE); 4199 format %{ "L(Y) $dst,$mem\t #" %} 4200 opcode(LY_ZOPC, L_ZOPC); 4201 ins_encode(z_form_rt_mem_opt(dst, mem)); 4202 ins_pipe(pipe_class_dummy); 4203 %} 4204 4205 // Load and convert to long. 4206 instruct loadI2L(iRegL dst, memory mem) %{ 4207 match(Set dst (ConvI2L (LoadI mem))); 4208 ins_cost(MEMORY_REF_COST); 4209 size(Z_DISP3_SIZE); 4210 format %{ "LGF $dst,$mem\t #" %} 4211 opcode(LGF_ZOPC, LGF_ZOPC); 4212 ins_encode(z_form_rt_mem_opt(dst, mem)); 4213 ins_pipe(pipe_class_dummy); 4214 %} 4215 4216 // Load Unsigned Integer into a Long Register 4217 instruct loadUI2L(iRegL dst, memory mem, immL_FFFFFFFF mask) %{ 4218 match(Set dst (AndL (ConvI2L (LoadI mem)) mask)); 4219 ins_cost(MEMORY_REF_COST); 4220 size(Z_DISP3_SIZE); 4221 format %{ "LLGF $dst,$mem\t # zero-extend int to long" %} 4222 opcode(LLGF_ZOPC, LLGF_ZOPC); 4223 ins_encode(z_form_rt_mem_opt(dst, mem)); 4224 ins_pipe(pipe_class_dummy); 4225 %} 4226 4227 // range = array length (=jint) 4228 // Load Range 4229 instruct loadRange(iRegI dst, memory mem) %{ 4230 match(Set dst (LoadRange mem)); 4231 ins_cost(MEMORY_REF_COST); 4232 size(Z_DISP_SIZE); 4233 format %{ "L(Y) $dst,$mem\t # range" %} 4234 opcode(LY_ZOPC, L_ZOPC); 4235 ins_encode(z_form_rt_mem_opt(dst, mem)); 4236 ins_pipe(pipe_class_dummy); 4237 %} 4238 4239 // LONG 4240 4241 // Load Long - aligned 4242 instruct loadL(iRegL dst, memory mem) %{ 4243 match(Set dst (LoadL mem)); 4244 ins_cost(MEMORY_REF_COST); 4245 size(Z_DISP3_SIZE); 4246 format %{ "LG $dst,$mem\t # long" %} 4247 opcode(LG_ZOPC, LG_ZOPC); 4248 ins_encode(z_form_rt_mem_opt(dst, mem)); 4249 ins_pipe(pipe_class_dummy); 4250 %} 4251 4252 // Load Long - UNaligned 4253 instruct loadL_unaligned(iRegL dst, memory mem) %{ 4254 match(Set dst (LoadL_unaligned mem)); 4255 ins_cost(MEMORY_REF_COST); 4256 size(Z_DISP3_SIZE); 4257 format %{ "LG $dst,$mem\t # unaligned long" %} 4258 opcode(LG_ZOPC, LG_ZOPC); 4259 ins_encode(z_form_rt_mem_opt(dst, mem)); 4260 ins_pipe(pipe_class_dummy); 4261 %} 4262 4263 4264 // PTR 4265 4266 // Load Pointer 4267 instruct loadP(iRegP dst, memory mem) %{ 4268 match(Set dst (LoadP mem)); 4269 ins_cost(MEMORY_REF_COST); 4270 size(Z_DISP3_SIZE); 4271 format %{ "LG $dst,$mem\t # ptr" %} 4272 opcode(LG_ZOPC, LG_ZOPC); 4273 ins_encode(z_form_rt_mem_opt(dst, mem)); 4274 ins_pipe(pipe_class_dummy); 4275 %} 4276 4277 // LoadP + CastP2L 4278 instruct castP2X_loadP(iRegL dst, memory mem) %{ 4279 match(Set dst (CastP2X (LoadP mem))); 4280 ins_cost(MEMORY_REF_COST); 4281 size(Z_DISP3_SIZE); 4282 format %{ "LG $dst,$mem\t # ptr + p2x" %} 4283 opcode(LG_ZOPC, LG_ZOPC); 4284 ins_encode(z_form_rt_mem_opt(dst, mem)); 4285 ins_pipe(pipe_class_dummy); 4286 %} 4287 4288 // Load Klass Pointer 4289 instruct loadKlass(iRegP dst, memory mem) %{ 4290 match(Set dst (LoadKlass mem)); 4291 ins_cost(MEMORY_REF_COST); 4292 size(Z_DISP3_SIZE); 4293 format %{ "LG $dst,$mem\t # klass ptr" %} 4294 opcode(LG_ZOPC, LG_ZOPC); 4295 ins_encode(z_form_rt_mem_opt(dst, mem)); 4296 ins_pipe(pipe_class_dummy); 4297 %} 4298 4299 instruct loadTOC(iRegL dst) %{ 4300 effect(DEF dst); 4301 ins_cost(DEFAULT_COST); 4302 // TODO: s390 port size(FIXED_SIZE); 4303 // TODO: check why this attribute causes many unnecessary rematerializations. 4304 // 4305 // The graphs I saw just had high register pressure. Further the 4306 // register TOC is loaded to is overwritten by the constant short 4307 // after. Here something as round robin register allocation might 4308 // help. But rematerializing seems not to hurt, jack even seems to 4309 // improve slightly. 4310 // 4311 // Without this flag we get spill-split recycle sanity check 4312 // failures in 4313 // spec.benchmarks._228_jack.NfaState::GenerateCode. This happens in 4314 // a block with three loadConP_dynTOC nodes and a tlsLoadP. The 4315 // tlsLoadP has a huge amount of outs and forces the TOC down to the 4316 // stack. Later tlsLoadP is rematerialized, leaving the register 4317 // allocator with TOC on the stack and a badly placed reload. 4318 ins_should_rematerialize(true); 4319 format %{ "LARL $dst, &constant_pool\t; load dynTOC" %} 4320 ins_encode %{ __ load_toc($dst$$Register); %} 4321 ins_pipe(pipe_class_dummy); 4322 %} 4323 4324 // FLOAT 4325 4326 // Load Float 4327 instruct loadF(regF dst, memory mem) %{ 4328 match(Set dst (LoadF mem)); 4329 ins_cost(MEMORY_REF_COST); 4330 size(Z_DISP_SIZE); 4331 format %{ "LE(Y) $dst,$mem" %} 4332 opcode(LEY_ZOPC, LE_ZOPC); 4333 ins_encode(z_form_rt_mem_opt(dst, mem)); 4334 ins_pipe(pipe_class_dummy); 4335 %} 4336 4337 // DOUBLE 4338 4339 // Load Double 4340 instruct loadD(regD dst, memory mem) %{ 4341 match(Set dst (LoadD mem)); 4342 ins_cost(MEMORY_REF_COST); 4343 size(Z_DISP_SIZE); 4344 format %{ "LD(Y) $dst,$mem" %} 4345 opcode(LDY_ZOPC, LD_ZOPC); 4346 ins_encode(z_form_rt_mem_opt(dst, mem)); 4347 ins_pipe(pipe_class_dummy); 4348 %} 4349 4350 // Load Double - UNaligned 4351 instruct loadD_unaligned(regD dst, memory mem) %{ 4352 match(Set dst (LoadD_unaligned mem)); 4353 ins_cost(MEMORY_REF_COST); 4354 size(Z_DISP_SIZE); 4355 format %{ "LD(Y) $dst,$mem" %} 4356 opcode(LDY_ZOPC, LD_ZOPC); 4357 ins_encode(z_form_rt_mem_opt(dst, mem)); 4358 ins_pipe(pipe_class_dummy); 4359 %} 4360 4361 4362 //---------------------- 4363 // IMMEDIATES 4364 //---------------------- 4365 4366 instruct loadConI(iRegI dst, immI src) %{ 4367 match(Set dst src); 4368 ins_cost(DEFAULT_COST); 4369 size(6); 4370 format %{ "LGFI $dst,$src\t # (int)" %} 4371 ins_encode %{ __ z_lgfi($dst$$Register, $src$$constant); %} // Sign-extend to 64 bit, it's at no cost. 4372 ins_pipe(pipe_class_dummy); 4373 %} 4374 4375 instruct loadConI16(iRegI dst, immI16 src) %{ 4376 match(Set dst src); 4377 ins_cost(DEFAULT_COST_LOW); 4378 size(4); 4379 format %{ "LGHI $dst,$src\t # (int)" %} 4380 ins_encode %{ __ z_lghi($dst$$Register, $src$$constant); %} // Sign-extend to 64 bit, it's at no cost. 4381 ins_pipe(pipe_class_dummy); 4382 %} 4383 4384 instruct loadConI_0(iRegI dst, immI_0 src, flagsReg cr) %{ 4385 match(Set dst src); 4386 effect(KILL cr); 4387 ins_cost(DEFAULT_COST_LOW); 4388 size(4); 4389 format %{ "loadConI $dst,$src\t # (int) XGR because ZERO is loaded" %} 4390 opcode(XGR_ZOPC); 4391 ins_encode(z_rreform(dst, dst)); 4392 ins_pipe(pipe_class_dummy); 4393 %} 4394 4395 instruct loadConUI16(iRegI dst, uimmI16 src) %{ 4396 match(Set dst src); 4397 // TODO: s390 port size(FIXED_SIZE); 4398 format %{ "LLILL $dst,$src" %} 4399 opcode(LLILL_ZOPC); 4400 ins_encode(z_riform_unsigned(dst, src) ); 4401 ins_pipe(pipe_class_dummy); 4402 %} 4403 4404 // Load long constant from TOC with pcrelative address. 4405 instruct loadConL_pcrelTOC(iRegL dst, immL src) %{ 4406 match(Set dst src); 4407 ins_cost(MEMORY_REF_COST_LO); 4408 size(6); 4409 format %{ "LGRL $dst,[pcrelTOC]\t # load long $src from table" %} 4410 ins_encode %{ 4411 address long_address = __ long_constant($src$$constant); 4412 if (long_address == NULL) { 4413 Compile::current()->env()->record_out_of_memory_failure(); 4414 return; 4415 } 4416 __ load_long_pcrelative($dst$$Register, long_address); 4417 %} 4418 ins_pipe(pipe_class_dummy); 4419 %} 4420 4421 instruct loadConL32(iRegL dst, immL32 src) %{ 4422 match(Set dst src); 4423 ins_cost(DEFAULT_COST); 4424 size(6); 4425 format %{ "LGFI $dst,$src\t # (long)" %} 4426 ins_encode %{ __ z_lgfi($dst$$Register, $src$$constant); %} // Sign-extend to 64 bit, it's at no cost. 4427 ins_pipe(pipe_class_dummy); 4428 %} 4429 4430 instruct loadConL16(iRegL dst, immL16 src) %{ 4431 match(Set dst src); 4432 ins_cost(DEFAULT_COST_LOW); 4433 size(4); 4434 format %{ "LGHI $dst,$src\t # (long)" %} 4435 ins_encode %{ __ z_lghi($dst$$Register, $src$$constant); %} // Sign-extend to 64 bit, it's at no cost. 4436 ins_pipe(pipe_class_dummy); 4437 %} 4438 4439 instruct loadConL_0(iRegL dst, immL_0 src, flagsReg cr) %{ 4440 match(Set dst src); 4441 effect(KILL cr); 4442 ins_cost(DEFAULT_COST_LOW); 4443 format %{ "LoadConL $dst,$src\t # (long) XGR because ZERO is loaded" %} 4444 opcode(XGR_ZOPC); 4445 ins_encode(z_rreform(dst, dst)); 4446 ins_pipe(pipe_class_dummy); 4447 %} 4448 4449 // Load ptr constant from TOC with pc relative address. 4450 // Special handling for oop constants required. 4451 instruct loadConP_pcrelTOC(iRegP dst, immP src) %{ 4452 match(Set dst src); 4453 ins_cost(MEMORY_REF_COST_LO); 4454 size(6); 4455 format %{ "LGRL $dst,[pcrelTOC]\t # load ptr $src from table" %} 4456 ins_encode %{ 4457 relocInfo::relocType constant_reloc = $src->constant_reloc(); 4458 if (constant_reloc == relocInfo::oop_type) { 4459 AddressLiteral a = __ allocate_oop_address((jobject)$src$$constant); 4460 bool success = __ load_oop_from_toc($dst$$Register, a); 4461 if (!success) { 4462 Compile::current()->env()->record_out_of_memory_failure(); 4463 return; 4464 } 4465 } else if (constant_reloc == relocInfo::metadata_type) { 4466 AddressLiteral a = __ constant_metadata_address((Metadata *)$src$$constant); 4467 address const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none); 4468 if (const_toc_addr == NULL) { 4469 Compile::current()->env()->record_out_of_memory_failure(); 4470 return; 4471 } 4472 __ load_long_pcrelative($dst$$Register, const_toc_addr); 4473 } else { // Non-oop pointers, e.g. card mark base, heap top. 4474 address long_address = __ long_constant((jlong)$src$$constant); 4475 if (long_address == NULL) { 4476 Compile::current()->env()->record_out_of_memory_failure(); 4477 return; 4478 } 4479 __ load_long_pcrelative($dst$$Register, long_address); 4480 } 4481 %} 4482 ins_pipe(pipe_class_dummy); 4483 %} 4484 4485 // We don't use immP16 to avoid problems with oops. 4486 instruct loadConP0(iRegP dst, immP0 src, flagsReg cr) %{ 4487 match(Set dst src); 4488 effect(KILL cr); 4489 size(4); 4490 format %{ "XGR $dst,$dst\t # NULL ptr" %} 4491 opcode(XGR_ZOPC); 4492 ins_encode(z_rreform(dst, dst)); 4493 ins_pipe(pipe_class_dummy); 4494 %} 4495 4496 //----------Load Float Constant Instructions------------------------------------------------- 4497 4498 // We may not specify this instruction via an `expand' rule. If we do, 4499 // code selection will forget that this instruction needs a floating 4500 // point constant inserted into the code buffer. So `Shorten_branches' 4501 // will fail. 4502 instruct loadConF_dynTOC(regF dst, immF src, flagsReg cr) %{ 4503 match(Set dst src); 4504 effect(KILL cr); 4505 ins_cost(MEMORY_REF_COST); 4506 size(6); 4507 // If this instruction rematerializes, it prolongs the live range 4508 // of the toc node, causing illegal graphs. 4509 ins_cannot_rematerialize(true); 4510 format %{ "LE(Y) $dst,$constantoffset[,$constanttablebase]\t # load FLOAT $src from table" %} 4511 ins_encode %{ 4512 __ load_float_largeoffset($dst$$FloatRegister, $constantoffset($src), $constanttablebase, Z_R1_scratch); 4513 %} 4514 ins_pipe(pipe_class_dummy); 4515 %} 4516 4517 // E may not specify this instruction via an `expand' rule. If we do, 4518 // code selection will forget that this instruction needs a floating 4519 // point constant inserted into the code buffer. So `Shorten_branches' 4520 // will fail. 4521 instruct loadConD_dynTOC(regD dst, immD src, flagsReg cr) %{ 4522 match(Set dst src); 4523 effect(KILL cr); 4524 ins_cost(MEMORY_REF_COST); 4525 size(6); 4526 // If this instruction rematerializes, it prolongs the live range 4527 // of the toc node, causing illegal graphs. 4528 ins_cannot_rematerialize(true); 4529 format %{ "LD(Y) $dst,$constantoffset[,$constanttablebase]\t # load DOUBLE $src from table" %} 4530 ins_encode %{ 4531 __ load_double_largeoffset($dst$$FloatRegister, $constantoffset($src), $constanttablebase, Z_R1_scratch); 4532 %} 4533 ins_pipe(pipe_class_dummy); 4534 %} 4535 4536 // Special case: Load Const 0.0F 4537 4538 // There's a special instr to clear a FP register. 4539 instruct loadConF0(regF dst, immFp0 src) %{ 4540 match(Set dst src); 4541 ins_cost(DEFAULT_COST_LOW); 4542 size(4); 4543 format %{ "LZER $dst,$src\t # clear to zero" %} 4544 opcode(LZER_ZOPC); 4545 ins_encode(z_rreform(dst, Z_F0)); 4546 ins_pipe(pipe_class_dummy); 4547 %} 4548 4549 // There's a special instr to clear a FP register. 4550 instruct loadConD0(regD dst, immDp0 src) %{ 4551 match(Set dst src); 4552 ins_cost(DEFAULT_COST_LOW); 4553 size(4); 4554 format %{ "LZDR $dst,$src\t # clear to zero" %} 4555 opcode(LZDR_ZOPC); 4556 ins_encode(z_rreform(dst, Z_F0)); 4557 ins_pipe(pipe_class_dummy); 4558 %} 4559 4560 4561 //----------Store Instructions------------------------------------------------- 4562 4563 // BYTE 4564 4565 // Store Byte 4566 instruct storeB(memory mem, iRegI src) %{ 4567 match(Set mem (StoreB mem src)); 4568 ins_cost(MEMORY_REF_COST); 4569 size(Z_DISP_SIZE); 4570 format %{ "STC(Y) $src,$mem\t # byte" %} 4571 opcode(STCY_ZOPC, STC_ZOPC); 4572 ins_encode(z_form_rt_mem_opt(src, mem)); 4573 ins_pipe(pipe_class_dummy); 4574 %} 4575 4576 instruct storeCM(memory mem, immI_0 src) %{ 4577 match(Set mem (StoreCM mem src)); 4578 ins_cost(MEMORY_REF_COST); 4579 // TODO: s390 port size(VARIABLE_SIZE); 4580 format %{ "STC(Y) $src,$mem\t # CMS card-mark byte (must be 0!)" %} 4581 ins_encode %{ 4582 guarantee($mem$$index$$Register != Z_R0, "content will not be used."); 4583 if ($mem$$index$$Register != noreg) { 4584 // Can't use clear_mem --> load const zero and store character. 4585 __ load_const_optimized(Z_R0_scratch, (long)0); 4586 if (Immediate::is_uimm12($mem$$disp)) { 4587 __ z_stc(Z_R0_scratch, $mem$$Address); 4588 } else { 4589 __ z_stcy(Z_R0_scratch, $mem$$Address); 4590 } 4591 } else { 4592 __ clear_mem(Address($mem$$Address), 1); 4593 } 4594 %} 4595 ins_pipe(pipe_class_dummy); 4596 %} 4597 4598 // CHAR/SHORT 4599 4600 // Store Char/Short 4601 instruct storeC(memory mem, iRegI src) %{ 4602 match(Set mem (StoreC mem src)); 4603 ins_cost(MEMORY_REF_COST); 4604 size(Z_DISP_SIZE); 4605 format %{ "STH(Y) $src,$mem\t # short" %} 4606 opcode(STHY_ZOPC, STH_ZOPC); 4607 ins_encode(z_form_rt_mem_opt(src, mem)); 4608 ins_pipe(pipe_class_dummy); 4609 %} 4610 4611 // INT 4612 4613 // Store Integer 4614 instruct storeI(memory mem, iRegI src) %{ 4615 match(Set mem (StoreI mem src)); 4616 ins_cost(MEMORY_REF_COST); 4617 size(Z_DISP_SIZE); 4618 format %{ "ST(Y) $src,$mem\t # int" %} 4619 opcode(STY_ZOPC, ST_ZOPC); 4620 ins_encode(z_form_rt_mem_opt(src, mem)); 4621 ins_pipe(pipe_class_dummy); 4622 %} 4623 4624 // LONG 4625 4626 // Store Long 4627 instruct storeL(memory mem, iRegL src) %{ 4628 match(Set mem (StoreL mem src)); 4629 ins_cost(MEMORY_REF_COST); 4630 size(Z_DISP3_SIZE); 4631 format %{ "STG $src,$mem\t # long" %} 4632 opcode(STG_ZOPC, STG_ZOPC); 4633 ins_encode(z_form_rt_mem_opt(src, mem)); 4634 ins_pipe(pipe_class_dummy); 4635 %} 4636 4637 // PTR 4638 4639 // Store Pointer 4640 instruct storeP(memory dst, memoryRegP src) %{ 4641 match(Set dst (StoreP dst src)); 4642 ins_cost(MEMORY_REF_COST); 4643 size(Z_DISP3_SIZE); 4644 format %{ "STG $src,$dst\t # ptr" %} 4645 opcode(STG_ZOPC, STG_ZOPC); 4646 ins_encode(z_form_rt_mem_opt(src, dst)); 4647 ins_pipe(pipe_class_dummy); 4648 %} 4649 4650 // FLOAT 4651 4652 // Store Float 4653 instruct storeF(memory mem, regF src) %{ 4654 match(Set mem (StoreF mem src)); 4655 ins_cost(MEMORY_REF_COST); 4656 size(Z_DISP_SIZE); 4657 format %{ "STE(Y) $src,$mem\t # float" %} 4658 opcode(STEY_ZOPC, STE_ZOPC); 4659 ins_encode(z_form_rt_mem_opt(src, mem)); 4660 ins_pipe(pipe_class_dummy); 4661 %} 4662 4663 // DOUBLE 4664 4665 // Store Double 4666 instruct storeD(memory mem, regD src) %{ 4667 match(Set mem (StoreD mem src)); 4668 ins_cost(MEMORY_REF_COST); 4669 size(Z_DISP_SIZE); 4670 format %{ "STD(Y) $src,$mem\t # double" %} 4671 opcode(STDY_ZOPC, STD_ZOPC); 4672 ins_encode(z_form_rt_mem_opt(src, mem)); 4673 ins_pipe(pipe_class_dummy); 4674 %} 4675 4676 // Prefetch instructions. Must be safe to execute with invalid address (cannot fault). 4677 4678 // Should support match rule for PrefetchAllocation. 4679 // Still needed after 8068977 for PrefetchAllocate. 4680 instruct prefetchAlloc(memory mem) %{ 4681 match(PrefetchAllocation mem); 4682 predicate(VM_Version::has_Prefetch()); 4683 ins_cost(DEFAULT_COST); 4684 format %{ "PREFETCH 2, $mem\t # Prefetch allocation, z10 only" %} 4685 ins_encode %{ __ z_pfd(0x02, $mem$$Address); %} 4686 ins_pipe(pipe_class_dummy); 4687 %} 4688 4689 //----------Memory init instructions------------------------------------------ 4690 4691 // Move Immediate to 1-byte memory. 4692 instruct memInitB(memoryRSY mem, immI8 src) %{ 4693 match(Set mem (StoreB mem src)); 4694 ins_cost(MEMORY_REF_COST); 4695 // TODO: s390 port size(VARIABLE_SIZE); 4696 format %{ "MVI $mem,$src\t # direct mem init 1" %} 4697 ins_encode %{ 4698 if (Immediate::is_uimm12((long)$mem$$disp)) { 4699 __ z_mvi($mem$$Address, $src$$constant); 4700 } else { 4701 __ z_mviy($mem$$Address, $src$$constant); 4702 } 4703 %} 4704 ins_pipe(pipe_class_dummy); 4705 %} 4706 4707 // Move Immediate to 2-byte memory. 4708 instruct memInitC(memoryRS mem, immI16 src) %{ 4709 match(Set mem (StoreC mem src)); 4710 ins_cost(MEMORY_REF_COST); 4711 size(6); 4712 format %{ "MVHHI $mem,$src\t # direct mem init 2" %} 4713 opcode(MVHHI_ZOPC); 4714 ins_encode(z_silform(mem, src)); 4715 ins_pipe(pipe_class_dummy); 4716 %} 4717 4718 // Move Immediate to 4-byte memory. 4719 instruct memInitI(memoryRS mem, immI16 src) %{ 4720 match(Set mem (StoreI mem src)); 4721 ins_cost(MEMORY_REF_COST); 4722 size(6); 4723 format %{ "MVHI $mem,$src\t # direct mem init 4" %} 4724 opcode(MVHI_ZOPC); 4725 ins_encode(z_silform(mem, src)); 4726 ins_pipe(pipe_class_dummy); 4727 %} 4728 4729 4730 // Move Immediate to 8-byte memory. 4731 instruct memInitL(memoryRS mem, immL16 src) %{ 4732 match(Set mem (StoreL mem src)); 4733 ins_cost(MEMORY_REF_COST); 4734 size(6); 4735 format %{ "MVGHI $mem,$src\t # direct mem init 8" %} 4736 opcode(MVGHI_ZOPC); 4737 ins_encode(z_silform(mem, src)); 4738 ins_pipe(pipe_class_dummy); 4739 %} 4740 4741 // Move Immediate to 8-byte memory. 4742 instruct memInitP(memoryRS mem, immP16 src) %{ 4743 match(Set mem (StoreP mem src)); 4744 ins_cost(MEMORY_REF_COST); 4745 size(6); 4746 format %{ "MVGHI $mem,$src\t # direct mem init 8" %} 4747 opcode(MVGHI_ZOPC); 4748 ins_encode(z_silform(mem, src)); 4749 ins_pipe(pipe_class_dummy); 4750 %} 4751 4752 4753 //----------Instructions for compressed pointers (cOop and NKlass)------------- 4754 4755 // See cOop encoding classes for elaborate comment. 4756 4757 // Moved here because it is needed in expand rules for encode. 4758 // Long negation. 4759 instruct negL_reg_reg(iRegL dst, immL_0 zero, iRegL src, flagsReg cr) %{ 4760 match(Set dst (SubL zero src)); 4761 effect(KILL cr); 4762 size(4); 4763 format %{ "NEG $dst, $src\t # long" %} 4764 ins_encode %{ __ z_lcgr($dst$$Register, $src$$Register); %} 4765 ins_pipe(pipe_class_dummy); 4766 %} 4767 4768 // Load Compressed Pointer 4769 4770 // Load narrow oop 4771 instruct loadN(iRegN dst, memory mem) %{ 4772 match(Set dst (LoadN mem)); 4773 ins_cost(MEMORY_REF_COST); 4774 size(Z_DISP3_SIZE); 4775 format %{ "LoadN $dst,$mem\t # (cOop)" %} 4776 opcode(LLGF_ZOPC, LLGF_ZOPC); 4777 ins_encode(z_form_rt_mem_opt(dst, mem)); 4778 ins_pipe(pipe_class_dummy); 4779 %} 4780 4781 // Load narrow Klass Pointer 4782 instruct loadNKlass(iRegN dst, memory mem) %{ 4783 match(Set dst (LoadNKlass mem)); 4784 ins_cost(MEMORY_REF_COST); 4785 size(Z_DISP3_SIZE); 4786 format %{ "LoadNKlass $dst,$mem\t # (klass cOop)" %} 4787 opcode(LLGF_ZOPC, LLGF_ZOPC); 4788 ins_encode(z_form_rt_mem_opt(dst, mem)); 4789 ins_pipe(pipe_class_dummy); 4790 %} 4791 4792 // Load constant Compressed Pointer 4793 4794 instruct loadConN(iRegN dst, immN src) %{ 4795 match(Set dst src); 4796 ins_cost(DEFAULT_COST); 4797 size(6); 4798 format %{ "loadConN $dst,$src\t # (cOop)" %} 4799 ins_encode %{ 4800 AddressLiteral cOop = __ constant_oop_address((jobject)$src$$constant); 4801 __ relocate(cOop.rspec(), 1); 4802 __ load_narrow_oop($dst$$Register, (narrowOop)cOop.value()); 4803 %} 4804 ins_pipe(pipe_class_dummy); 4805 %} 4806 4807 instruct loadConN0(iRegN dst, immN0 src, flagsReg cr) %{ 4808 match(Set dst src); 4809 effect(KILL cr); 4810 ins_cost(DEFAULT_COST_LOW); 4811 size(4); 4812 format %{ "loadConN $dst,$src\t # (cOop) XGR because ZERO is loaded" %} 4813 opcode(XGR_ZOPC); 4814 ins_encode(z_rreform(dst, dst)); 4815 ins_pipe(pipe_class_dummy); 4816 %} 4817 4818 instruct loadConNKlass(iRegN dst, immNKlass src) %{ 4819 match(Set dst src); 4820 ins_cost(DEFAULT_COST); 4821 size(6); 4822 format %{ "loadConNKlass $dst,$src\t # (cKlass)" %} 4823 ins_encode %{ 4824 AddressLiteral NKlass = __ constant_metadata_address((Metadata*)$src$$constant); 4825 __ relocate(NKlass.rspec(), 1); 4826 __ load_narrow_klass($dst$$Register, (Klass*)NKlass.value()); 4827 %} 4828 ins_pipe(pipe_class_dummy); 4829 %} 4830 4831 // Load and Decode Compressed Pointer 4832 // optimized variants for Unscaled cOops 4833 4834 instruct decodeLoadN(iRegP dst, memory mem) %{ 4835 match(Set dst (DecodeN (LoadN mem))); 4836 predicate(false && (CompressedOops::base()==NULL)&&(CompressedOops::shift()==0)); 4837 ins_cost(MEMORY_REF_COST); 4838 size(Z_DISP3_SIZE); 4839 format %{ "DecodeLoadN $dst,$mem\t # (cOop Load+Decode)" %} 4840 opcode(LLGF_ZOPC, LLGF_ZOPC); 4841 ins_encode(z_form_rt_mem_opt(dst, mem)); 4842 ins_pipe(pipe_class_dummy); 4843 %} 4844 4845 instruct decodeLoadNKlass(iRegP dst, memory mem) %{ 4846 match(Set dst (DecodeNKlass (LoadNKlass mem))); 4847 predicate(false && (CompressedKlassPointers::base()==NULL)&&(CompressedKlassPointers::shift()==0)); 4848 ins_cost(MEMORY_REF_COST); 4849 size(Z_DISP3_SIZE); 4850 format %{ "DecodeLoadNKlass $dst,$mem\t # (load/decode NKlass)" %} 4851 opcode(LLGF_ZOPC, LLGF_ZOPC); 4852 ins_encode(z_form_rt_mem_opt(dst, mem)); 4853 ins_pipe(pipe_class_dummy); 4854 %} 4855 4856 instruct decodeLoadConNKlass(iRegP dst, immNKlass src) %{ 4857 match(Set dst (DecodeNKlass src)); 4858 ins_cost(3 * DEFAULT_COST); 4859 size(12); 4860 format %{ "DecodeLoadConNKlass $dst,$src\t # decode(cKlass)" %} 4861 ins_encode %{ 4862 AddressLiteral NKlass = __ constant_metadata_address((Metadata*)$src$$constant); 4863 __ relocate(NKlass.rspec(), 1); 4864 __ load_const($dst$$Register, (Klass*)NKlass.value()); 4865 %} 4866 ins_pipe(pipe_class_dummy); 4867 %} 4868 4869 // Decode Compressed Pointer 4870 4871 // General decoder 4872 instruct decodeN(iRegP dst, iRegN src, flagsReg cr) %{ 4873 match(Set dst (DecodeN src)); 4874 effect(KILL cr); 4875 predicate(CompressedOops::base() == NULL || !ExpandLoadingBaseDecode); 4876 ins_cost(MEMORY_REF_COST+3 * DEFAULT_COST + BRANCH_COST); 4877 // TODO: s390 port size(VARIABLE_SIZE); 4878 format %{ "decodeN $dst,$src\t # (decode cOop)" %} 4879 ins_encode %{ __ oop_decoder($dst$$Register, $src$$Register, true); %} 4880 ins_pipe(pipe_class_dummy); 4881 %} 4882 4883 // General Klass decoder 4884 instruct decodeKlass(iRegP dst, iRegN src, flagsReg cr) %{ 4885 match(Set dst (DecodeNKlass src)); 4886 effect(KILL cr); 4887 ins_cost(3 * DEFAULT_COST); 4888 format %{ "decode_klass $dst,$src" %} 4889 ins_encode %{ __ decode_klass_not_null($dst$$Register, $src$$Register); %} 4890 ins_pipe(pipe_class_dummy); 4891 %} 4892 4893 // General decoder 4894 instruct decodeN_NN(iRegP dst, iRegN src, flagsReg cr) %{ 4895 match(Set dst (DecodeN src)); 4896 effect(KILL cr); 4897 predicate((n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull || 4898 n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant) && 4899 (CompressedOops::base()== NULL || !ExpandLoadingBaseDecode_NN)); 4900 ins_cost(MEMORY_REF_COST+2 * DEFAULT_COST); 4901 // TODO: s390 port size(VARIABLE_SIZE); 4902 format %{ "decodeN $dst,$src\t # (decode cOop NN)" %} 4903 ins_encode %{ __ oop_decoder($dst$$Register, $src$$Register, false); %} 4904 ins_pipe(pipe_class_dummy); 4905 %} 4906 4907 instruct loadBase(iRegL dst, immL baseImm) %{ 4908 effect(DEF dst, USE baseImm); 4909 predicate(false); 4910 format %{ "llihl $dst=$baseImm \t// load heap base" %} 4911 ins_encode %{ __ get_oop_base($dst$$Register, $baseImm$$constant); %} 4912 ins_pipe(pipe_class_dummy); 4913 %} 4914 4915 // Decoder for heapbased mode peeling off loading the base. 4916 instruct decodeN_base(iRegP dst, iRegN src, iRegL base, flagsReg cr) %{ 4917 match(Set dst (DecodeN src base)); 4918 // Note: Effect TEMP dst was used with the intention to get 4919 // different regs for dst and base, but this has caused ADLC to 4920 // generate wrong code. Oop_decoder generates additional lgr when 4921 // dst==base. 4922 effect(KILL cr); 4923 predicate(false); 4924 // TODO: s390 port size(VARIABLE_SIZE); 4925 format %{ "decodeN $dst = ($src == 0) ? NULL : ($src << 3) + $base + pow2_offset\t # (decode cOop)" %} 4926 ins_encode %{ 4927 __ oop_decoder($dst$$Register, $src$$Register, true, $base$$Register, 4928 (jlong)MacroAssembler::get_oop_base_pow2_offset((uint64_t)(intptr_t)CompressedOops::base())); 4929 %} 4930 ins_pipe(pipe_class_dummy); 4931 %} 4932 4933 // Decoder for heapbased mode peeling off loading the base. 4934 instruct decodeN_NN_base(iRegP dst, iRegN src, iRegL base, flagsReg cr) %{ 4935 match(Set dst (DecodeN src base)); 4936 effect(KILL cr); 4937 predicate(false); 4938 // TODO: s390 port size(VARIABLE_SIZE); 4939 format %{ "decodeN $dst = ($src << 3) + $base + pow2_offset\t # (decode cOop)" %} 4940 ins_encode %{ 4941 __ oop_decoder($dst$$Register, $src$$Register, false, $base$$Register, 4942 (jlong)MacroAssembler::get_oop_base_pow2_offset((uint64_t)(intptr_t)CompressedOops::base())); 4943 %} 4944 ins_pipe(pipe_class_dummy); 4945 %} 4946 4947 // Decoder for heapbased mode peeling off loading the base. 4948 instruct decodeN_Ex(iRegP dst, iRegN src, flagsReg cr) %{ 4949 match(Set dst (DecodeN src)); 4950 predicate(CompressedOops::base() != NULL && ExpandLoadingBaseDecode); 4951 ins_cost(MEMORY_REF_COST+3 * DEFAULT_COST + BRANCH_COST); 4952 // TODO: s390 port size(VARIABLE_SIZE); 4953 expand %{ 4954 immL baseImm %{ (jlong)(intptr_t)CompressedOops::base() %} 4955 iRegL base; 4956 loadBase(base, baseImm); 4957 decodeN_base(dst, src, base, cr); 4958 %} 4959 %} 4960 4961 // Decoder for heapbased mode peeling off loading the base. 4962 instruct decodeN_NN_Ex(iRegP dst, iRegN src, flagsReg cr) %{ 4963 match(Set dst (DecodeN src)); 4964 predicate((n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull || 4965 n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant) && 4966 CompressedOops::base() != NULL && ExpandLoadingBaseDecode_NN); 4967 ins_cost(MEMORY_REF_COST+2 * DEFAULT_COST); 4968 // TODO: s390 port size(VARIABLE_SIZE); 4969 expand %{ 4970 immL baseImm %{ (jlong)(intptr_t)CompressedOops::base() %} 4971 iRegL base; 4972 loadBase(base, baseImm); 4973 decodeN_NN_base(dst, src, base, cr); 4974 %} 4975 %} 4976 4977 // Encode Compressed Pointer 4978 4979 // General encoder 4980 instruct encodeP(iRegN dst, iRegP src, flagsReg cr) %{ 4981 match(Set dst (EncodeP src)); 4982 effect(KILL cr); 4983 predicate((n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull) && 4984 (CompressedOops::base() == 0 || 4985 CompressedOops::base_disjoint() || 4986 !ExpandLoadingBaseEncode)); 4987 ins_cost(MEMORY_REF_COST+3 * DEFAULT_COST); 4988 // TODO: s390 port size(VARIABLE_SIZE); 4989 format %{ "encodeP $dst,$src\t # (encode cOop)" %} 4990 ins_encode %{ __ oop_encoder($dst$$Register, $src$$Register, true, Z_R1_scratch, -1, all_outs_are_Stores(this)); %} 4991 ins_pipe(pipe_class_dummy); 4992 %} 4993 4994 // General class encoder 4995 instruct encodeKlass(iRegN dst, iRegP src, flagsReg cr) %{ 4996 match(Set dst (EncodePKlass src)); 4997 effect(KILL cr); 4998 format %{ "encode_klass $dst,$src" %} 4999 ins_encode %{ __ encode_klass_not_null($dst$$Register, $src$$Register); %} 5000 ins_pipe(pipe_class_dummy); 5001 %} 5002 5003 instruct encodeP_NN(iRegN dst, iRegP src, flagsReg cr) %{ 5004 match(Set dst (EncodeP src)); 5005 effect(KILL cr); 5006 predicate((n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull) && 5007 (CompressedOops::base() == 0 || 5008 CompressedOops::base_disjoint() || 5009 !ExpandLoadingBaseEncode_NN)); 5010 ins_cost(MEMORY_REF_COST+3 * DEFAULT_COST); 5011 // TODO: s390 port size(VARIABLE_SIZE); 5012 format %{ "encodeP $dst,$src\t # (encode cOop)" %} 5013 ins_encode %{ __ oop_encoder($dst$$Register, $src$$Register, false, Z_R1_scratch, -1, all_outs_are_Stores(this)); %} 5014 ins_pipe(pipe_class_dummy); 5015 %} 5016 5017 // Encoder for heapbased mode peeling off loading the base. 5018 instruct encodeP_base(iRegN dst, iRegP src, iRegL base) %{ 5019 match(Set dst (EncodeP src (Binary base dst))); 5020 effect(TEMP_DEF dst); 5021 predicate(false); 5022 ins_cost(MEMORY_REF_COST+2 * DEFAULT_COST); 5023 // TODO: s390 port size(VARIABLE_SIZE); 5024 format %{ "encodeP $dst = ($src>>3) +$base + pow2_offset\t # (encode cOop)" %} 5025 ins_encode %{ 5026 jlong offset = -(jlong)MacroAssembler::get_oop_base_pow2_offset 5027 (((uint64_t)(intptr_t)CompressedOops::base()) >> CompressedOops::shift()); 5028 __ oop_encoder($dst$$Register, $src$$Register, true, $base$$Register, offset); 5029 %} 5030 ins_pipe(pipe_class_dummy); 5031 %} 5032 5033 // Encoder for heapbased mode peeling off loading the base. 5034 instruct encodeP_NN_base(iRegN dst, iRegP src, iRegL base, immL pow2_offset) %{ 5035 match(Set dst (EncodeP src base)); 5036 effect(USE pow2_offset); 5037 predicate(false); 5038 ins_cost(MEMORY_REF_COST+2 * DEFAULT_COST); 5039 // TODO: s390 port size(VARIABLE_SIZE); 5040 format %{ "encodeP $dst = ($src>>3) +$base + $pow2_offset\t # (encode cOop)" %} 5041 ins_encode %{ __ oop_encoder($dst$$Register, $src$$Register, false, $base$$Register, $pow2_offset$$constant); %} 5042 ins_pipe(pipe_class_dummy); 5043 %} 5044 5045 // Encoder for heapbased mode peeling off loading the base. 5046 instruct encodeP_Ex(iRegN dst, iRegP src, flagsReg cr) %{ 5047 match(Set dst (EncodeP src)); 5048 effect(KILL cr); 5049 predicate((n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull) && 5050 (CompressedOops::base_overlaps() && ExpandLoadingBaseEncode)); 5051 ins_cost(MEMORY_REF_COST+3 * DEFAULT_COST); 5052 // TODO: s390 port size(VARIABLE_SIZE); 5053 expand %{ 5054 immL baseImm %{ ((jlong)(intptr_t)CompressedOops::base()) >> CompressedOops::shift() %} 5055 immL_0 zero %{ (0) %} 5056 flagsReg ccr; 5057 iRegL base; 5058 iRegL negBase; 5059 loadBase(base, baseImm); 5060 negL_reg_reg(negBase, zero, base, ccr); 5061 encodeP_base(dst, src, negBase); 5062 %} 5063 %} 5064 5065 // Encoder for heapbased mode peeling off loading the base. 5066 instruct encodeP_NN_Ex(iRegN dst, iRegP src, flagsReg cr) %{ 5067 match(Set dst (EncodeP src)); 5068 effect(KILL cr); 5069 predicate((n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull) && 5070 (CompressedOops::base_overlaps() && ExpandLoadingBaseEncode_NN)); 5071 ins_cost(MEMORY_REF_COST+3 * DEFAULT_COST); 5072 // TODO: s390 port size(VARIABLE_SIZE); 5073 expand %{ 5074 immL baseImm %{ (jlong)(intptr_t)CompressedOops::base() %} 5075 immL pow2_offset %{ -(jlong)MacroAssembler::get_oop_base_pow2_offset(((uint64_t)(intptr_t)CompressedOops::base())) %} 5076 immL_0 zero %{ 0 %} 5077 flagsReg ccr; 5078 iRegL base; 5079 iRegL negBase; 5080 loadBase(base, baseImm); 5081 negL_reg_reg(negBase, zero, base, ccr); 5082 encodeP_NN_base(dst, src, negBase, pow2_offset); 5083 %} 5084 %} 5085 5086 // Store Compressed Pointer 5087 5088 // Store Compressed Pointer 5089 instruct storeN(memory mem, iRegN_P2N src) %{ 5090 match(Set mem (StoreN mem src)); 5091 ins_cost(MEMORY_REF_COST); 5092 size(Z_DISP_SIZE); 5093 format %{ "ST $src,$mem\t # (cOop)" %} 5094 opcode(STY_ZOPC, ST_ZOPC); 5095 ins_encode(z_form_rt_mem_opt(src, mem)); 5096 ins_pipe(pipe_class_dummy); 5097 %} 5098 5099 // Store Compressed Klass pointer 5100 instruct storeNKlass(memory mem, iRegN src) %{ 5101 match(Set mem (StoreNKlass mem src)); 5102 ins_cost(MEMORY_REF_COST); 5103 size(Z_DISP_SIZE); 5104 format %{ "ST $src,$mem\t # (cKlass)" %} 5105 opcode(STY_ZOPC, ST_ZOPC); 5106 ins_encode(z_form_rt_mem_opt(src, mem)); 5107 ins_pipe(pipe_class_dummy); 5108 %} 5109 5110 // Compare Compressed Pointers 5111 5112 instruct compN_iRegN(iRegN_P2N src1, iRegN_P2N src2, flagsReg cr) %{ 5113 match(Set cr (CmpN src1 src2)); 5114 ins_cost(DEFAULT_COST); 5115 size(2); 5116 format %{ "CLR $src1,$src2\t # (cOop)" %} 5117 opcode(CLR_ZOPC); 5118 ins_encode(z_rrform(src1, src2)); 5119 ins_pipe(pipe_class_dummy); 5120 %} 5121 5122 instruct compN_iRegN_immN(iRegN_P2N src1, immN src2, flagsReg cr) %{ 5123 match(Set cr (CmpN src1 src2)); 5124 ins_cost(DEFAULT_COST); 5125 size(6); 5126 format %{ "CLFI $src1,$src2\t # (cOop) compare immediate narrow" %} 5127 ins_encode %{ 5128 AddressLiteral cOop = __ constant_oop_address((jobject)$src2$$constant); 5129 __ relocate(cOop.rspec(), 1); 5130 __ compare_immediate_narrow_oop($src1$$Register, (narrowOop)cOop.value()); 5131 %} 5132 ins_pipe(pipe_class_dummy); 5133 %} 5134 5135 instruct compNKlass_iRegN_immN(iRegN src1, immNKlass src2, flagsReg cr) %{ 5136 match(Set cr (CmpN src1 src2)); 5137 ins_cost(DEFAULT_COST); 5138 size(6); 5139 format %{ "CLFI $src1,$src2\t # (NKlass) compare immediate narrow" %} 5140 ins_encode %{ 5141 AddressLiteral NKlass = __ constant_metadata_address((Metadata*)$src2$$constant); 5142 __ relocate(NKlass.rspec(), 1); 5143 __ compare_immediate_narrow_klass($src1$$Register, (Klass*)NKlass.value()); 5144 %} 5145 ins_pipe(pipe_class_dummy); 5146 %} 5147 5148 instruct compN_iRegN_immN0(iRegN_P2N src1, immN0 src2, flagsReg cr) %{ 5149 match(Set cr (CmpN src1 src2)); 5150 ins_cost(DEFAULT_COST); 5151 size(2); 5152 format %{ "LTR $src1,$src2\t # (cOop) LTR because comparing against zero" %} 5153 opcode(LTR_ZOPC); 5154 ins_encode(z_rrform(src1, src1)); 5155 ins_pipe(pipe_class_dummy); 5156 %} 5157 5158 5159 //----------MemBar Instructions----------------------------------------------- 5160 5161 // Memory barrier flavors 5162 5163 instruct membar_acquire() %{ 5164 match(MemBarAcquire); 5165 match(LoadFence); 5166 ins_cost(4*MEMORY_REF_COST); 5167 size(0); 5168 format %{ "MEMBAR-acquire" %} 5169 ins_encode %{ __ z_acquire(); %} 5170 ins_pipe(pipe_class_dummy); 5171 %} 5172 5173 instruct membar_acquire_lock() %{ 5174 match(MemBarAcquireLock); 5175 ins_cost(0); 5176 size(0); 5177 format %{ "MEMBAR-acquire (CAS in prior FastLock so empty encoding)" %} 5178 ins_encode(/*empty*/); 5179 ins_pipe(pipe_class_dummy); 5180 %} 5181 5182 instruct membar_release() %{ 5183 match(MemBarRelease); 5184 match(StoreFence); 5185 ins_cost(4 * MEMORY_REF_COST); 5186 size(0); 5187 format %{ "MEMBAR-release" %} 5188 ins_encode %{ __ z_release(); %} 5189 ins_pipe(pipe_class_dummy); 5190 %} 5191 5192 instruct membar_release_lock() %{ 5193 match(MemBarReleaseLock); 5194 ins_cost(0); 5195 size(0); 5196 format %{ "MEMBAR-release (CAS in succeeding FastUnlock so empty encoding)" %} 5197 ins_encode(/*empty*/); 5198 ins_pipe(pipe_class_dummy); 5199 %} 5200 5201 instruct membar_volatile() %{ 5202 match(MemBarVolatile); 5203 ins_cost(4 * MEMORY_REF_COST); 5204 size(2); 5205 format %{ "MEMBAR-volatile" %} 5206 ins_encode %{ __ z_fence(); %} 5207 ins_pipe(pipe_class_dummy); 5208 %} 5209 5210 instruct unnecessary_membar_volatile() %{ 5211 match(MemBarVolatile); 5212 predicate(Matcher::post_store_load_barrier(n)); 5213 ins_cost(0); 5214 size(0); 5215 format %{ "# MEMBAR-volatile (empty)" %} 5216 ins_encode(/*empty*/); 5217 ins_pipe(pipe_class_dummy); 5218 %} 5219 5220 instruct membar_CPUOrder() %{ 5221 match(MemBarCPUOrder); 5222 ins_cost(0); 5223 // TODO: s390 port size(FIXED_SIZE); 5224 format %{ "MEMBAR-CPUOrder (empty)" %} 5225 ins_encode(/*empty*/); 5226 ins_pipe(pipe_class_dummy); 5227 %} 5228 5229 instruct membar_storestore() %{ 5230 match(MemBarStoreStore); 5231 ins_cost(0); 5232 size(0); 5233 format %{ "MEMBAR-storestore (empty)" %} 5234 ins_encode(); 5235 ins_pipe(pipe_class_dummy); 5236 %} 5237 5238 5239 //----------Register Move Instructions----------------------------------------- 5240 instruct roundDouble_nop(regD dst) %{ 5241 match(Set dst (RoundDouble dst)); 5242 ins_cost(0); 5243 // TODO: s390 port size(FIXED_SIZE); 5244 // z/Architecture results are already "rounded" (i.e., normal-format IEEE). 5245 ins_encode(); 5246 ins_pipe(pipe_class_dummy); 5247 %} 5248 5249 instruct roundFloat_nop(regF dst) %{ 5250 match(Set dst (RoundFloat dst)); 5251 ins_cost(0); 5252 // TODO: s390 port size(FIXED_SIZE); 5253 // z/Architecture results are already "rounded" (i.e., normal-format IEEE). 5254 ins_encode(); 5255 ins_pipe(pipe_class_dummy); 5256 %} 5257 5258 // Cast Long to Pointer for unsafe natives. 5259 instruct castX2P(iRegP dst, iRegL src) %{ 5260 match(Set dst (CastX2P src)); 5261 // TODO: s390 port size(VARIABLE_SIZE); 5262 format %{ "LGR $dst,$src\t # CastX2P" %} 5263 ins_encode %{ __ lgr_if_needed($dst$$Register, $src$$Register); %} 5264 ins_pipe(pipe_class_dummy); 5265 %} 5266 5267 // Cast Pointer to Long for unsafe natives. 5268 instruct castP2X(iRegL dst, iRegP_N2P src) %{ 5269 match(Set dst (CastP2X src)); 5270 // TODO: s390 port size(VARIABLE_SIZE); 5271 format %{ "LGR $dst,$src\t # CastP2X" %} 5272 ins_encode %{ __ lgr_if_needed($dst$$Register, $src$$Register); %} 5273 ins_pipe(pipe_class_dummy); 5274 %} 5275 5276 instruct stfSSD(stackSlotD stkSlot, regD src) %{ 5277 // %%%% TODO: Tell the coalescer that this kind of node is a copy! 5278 match(Set stkSlot src); // chain rule 5279 ins_cost(MEMORY_REF_COST); 5280 // TODO: s390 port size(FIXED_SIZE); 5281 format %{ " STD $src,$stkSlot\t # stk" %} 5282 opcode(STD_ZOPC); 5283 ins_encode(z_form_rt_mem(src, stkSlot)); 5284 ins_pipe(pipe_class_dummy); 5285 %} 5286 5287 instruct stfSSF(stackSlotF stkSlot, regF src) %{ 5288 // %%%% TODO: Tell the coalescer that this kind of node is a copy! 5289 match(Set stkSlot src); // chain rule 5290 ins_cost(MEMORY_REF_COST); 5291 // TODO: s390 port size(FIXED_SIZE); 5292 format %{ "STE $src,$stkSlot\t # stk" %} 5293 opcode(STE_ZOPC); 5294 ins_encode(z_form_rt_mem(src, stkSlot)); 5295 ins_pipe(pipe_class_dummy); 5296 %} 5297 5298 //----------Conditional Move--------------------------------------------------- 5299 5300 instruct cmovN_reg(cmpOp cmp, flagsReg cr, iRegN dst, iRegN_P2N src) %{ 5301 match(Set dst (CMoveN (Binary cmp cr) (Binary dst src))); 5302 ins_cost(DEFAULT_COST + BRANCH_COST); 5303 // TODO: s390 port size(VARIABLE_SIZE); 5304 format %{ "CMoveN,$cmp $dst,$src" %} 5305 ins_encode(z_enc_cmov_reg(cmp,dst,src)); 5306 ins_pipe(pipe_class_dummy); 5307 %} 5308 5309 instruct cmovN_imm(cmpOp cmp, flagsReg cr, iRegN dst, immN0 src) %{ 5310 match(Set dst (CMoveN (Binary cmp cr) (Binary dst src))); 5311 ins_cost(DEFAULT_COST + BRANCH_COST); 5312 // TODO: s390 port size(VARIABLE_SIZE); 5313 format %{ "CMoveN,$cmp $dst,$src" %} 5314 ins_encode(z_enc_cmov_imm(cmp,dst,src)); 5315 ins_pipe(pipe_class_dummy); 5316 %} 5317 5318 instruct cmovI_reg(cmpOp cmp, flagsReg cr, iRegI dst, iRegI src) %{ 5319 match(Set dst (CMoveI (Binary cmp cr) (Binary dst src))); 5320 ins_cost(DEFAULT_COST + BRANCH_COST); 5321 // TODO: s390 port size(VARIABLE_SIZE); 5322 format %{ "CMoveI,$cmp $dst,$src" %} 5323 ins_encode(z_enc_cmov_reg(cmp,dst,src)); 5324 ins_pipe(pipe_class_dummy); 5325 %} 5326 5327 instruct cmovI_imm(cmpOp cmp, flagsReg cr, iRegI dst, immI16 src) %{ 5328 match(Set dst (CMoveI (Binary cmp cr) (Binary dst src))); 5329 ins_cost(DEFAULT_COST + BRANCH_COST); 5330 // TODO: s390 port size(VARIABLE_SIZE); 5331 format %{ "CMoveI,$cmp $dst,$src" %} 5332 ins_encode(z_enc_cmov_imm(cmp,dst,src)); 5333 ins_pipe(pipe_class_dummy); 5334 %} 5335 5336 instruct cmovP_reg(cmpOp cmp, flagsReg cr, iRegP dst, iRegP_N2P src) %{ 5337 match(Set dst (CMoveP (Binary cmp cr) (Binary dst src))); 5338 ins_cost(DEFAULT_COST + BRANCH_COST); 5339 // TODO: s390 port size(VARIABLE_SIZE); 5340 format %{ "CMoveP,$cmp $dst,$src" %} 5341 ins_encode(z_enc_cmov_reg(cmp,dst,src)); 5342 ins_pipe(pipe_class_dummy); 5343 %} 5344 5345 instruct cmovP_imm(cmpOp cmp, flagsReg cr, iRegP dst, immP0 src) %{ 5346 match(Set dst (CMoveP (Binary cmp cr) (Binary dst src))); 5347 ins_cost(DEFAULT_COST + BRANCH_COST); 5348 // TODO: s390 port size(VARIABLE_SIZE); 5349 format %{ "CMoveP,$cmp $dst,$src" %} 5350 ins_encode(z_enc_cmov_imm(cmp,dst,src)); 5351 ins_pipe(pipe_class_dummy); 5352 %} 5353 5354 instruct cmovF_reg(cmpOpF cmp, flagsReg cr, regF dst, regF src) %{ 5355 match(Set dst (CMoveF (Binary cmp cr) (Binary dst src))); 5356 ins_cost(DEFAULT_COST + BRANCH_COST); 5357 // TODO: s390 port size(VARIABLE_SIZE); 5358 format %{ "CMoveF,$cmp $dst,$src" %} 5359 ins_encode %{ 5360 // Don't emit code if operands are identical (same register). 5361 if ($dst$$FloatRegister != $src$$FloatRegister) { 5362 Label done; 5363 __ z_brc(Assembler::inverse_float_condition((Assembler::branch_condition)$cmp$$cmpcode), done); 5364 __ z_ler($dst$$FloatRegister, $src$$FloatRegister); 5365 __ bind(done); 5366 } 5367 %} 5368 ins_pipe(pipe_class_dummy); 5369 %} 5370 5371 instruct cmovD_reg(cmpOpF cmp, flagsReg cr, regD dst, regD src) %{ 5372 match(Set dst (CMoveD (Binary cmp cr) (Binary dst src))); 5373 ins_cost(DEFAULT_COST + BRANCH_COST); 5374 // TODO: s390 port size(VARIABLE_SIZE); 5375 format %{ "CMoveD,$cmp $dst,$src" %} 5376 ins_encode %{ 5377 // Don't emit code if operands are identical (same register). 5378 if ($dst$$FloatRegister != $src$$FloatRegister) { 5379 Label done; 5380 __ z_brc(Assembler::inverse_float_condition((Assembler::branch_condition)$cmp$$cmpcode), done); 5381 __ z_ldr($dst$$FloatRegister, $src$$FloatRegister); 5382 __ bind(done); 5383 } 5384 %} 5385 ins_pipe(pipe_class_dummy); 5386 %} 5387 5388 instruct cmovL_reg(cmpOp cmp, flagsReg cr, iRegL dst, iRegL src) %{ 5389 match(Set dst (CMoveL (Binary cmp cr) (Binary dst src))); 5390 ins_cost(DEFAULT_COST + BRANCH_COST); 5391 // TODO: s390 port size(VARIABLE_SIZE); 5392 format %{ "CMoveL,$cmp $dst,$src" %} 5393 ins_encode(z_enc_cmov_reg(cmp,dst,src)); 5394 ins_pipe(pipe_class_dummy); 5395 %} 5396 5397 instruct cmovL_imm(cmpOp cmp, flagsReg cr, iRegL dst, immL16 src) %{ 5398 match(Set dst (CMoveL (Binary cmp cr) (Binary dst src))); 5399 ins_cost(DEFAULT_COST + BRANCH_COST); 5400 // TODO: s390 port size(VARIABLE_SIZE); 5401 format %{ "CMoveL,$cmp $dst,$src" %} 5402 ins_encode(z_enc_cmov_imm(cmp,dst,src)); 5403 ins_pipe(pipe_class_dummy); 5404 %} 5405 5406 //----------OS and Locking Instructions---------------------------------------- 5407 5408 // This name is KNOWN by the ADLC and cannot be changed. 5409 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type 5410 // for this guy. 5411 instruct tlsLoadP(threadRegP dst) %{ 5412 match(Set dst (ThreadLocal)); 5413 ins_cost(0); 5414 size(0); 5415 ins_should_rematerialize(true); 5416 format %{ "# $dst=ThreadLocal" %} 5417 ins_encode(/* empty */); 5418 ins_pipe(pipe_class_dummy); 5419 %} 5420 5421 instruct checkCastPP(iRegP dst) %{ 5422 match(Set dst (CheckCastPP dst)); 5423 size(0); 5424 format %{ "# checkcastPP of $dst" %} 5425 ins_encode(/*empty*/); 5426 ins_pipe(pipe_class_dummy); 5427 %} 5428 5429 instruct castPP(iRegP dst) %{ 5430 match(Set dst (CastPP dst)); 5431 size(0); 5432 format %{ "# castPP of $dst" %} 5433 ins_encode(/*empty*/); 5434 ins_pipe(pipe_class_dummy); 5435 %} 5436 5437 instruct castII(iRegI dst) %{ 5438 match(Set dst (CastII dst)); 5439 size(0); 5440 format %{ "# castII of $dst" %} 5441 ins_encode(/*empty*/); 5442 ins_pipe(pipe_class_dummy); 5443 %} 5444 5445 5446 //----------Conditional_store-------------------------------------------------- 5447 // Conditional-store of the updated heap-top. 5448 // Used during allocation of the shared heap. 5449 // Sets flags (EQ) on success. 5450 5451 // Implement LoadPLocked. Must be ordered against changes of the memory location 5452 // by storePConditional. 5453 // Don't know whether this is ever used. 5454 instruct loadPLocked(iRegP dst, memory mem) %{ 5455 match(Set dst (LoadPLocked mem)); 5456 ins_cost(MEMORY_REF_COST); 5457 size(Z_DISP3_SIZE); 5458 format %{ "LG $dst,$mem\t # LoadPLocked" %} 5459 opcode(LG_ZOPC, LG_ZOPC); 5460 ins_encode(z_form_rt_mem_opt(dst, mem)); 5461 ins_pipe(pipe_class_dummy); 5462 %} 5463 5464 // As compareAndSwapP, but return flag register instead of boolean value in 5465 // int register. 5466 // This instruction is matched if UseTLAB is off. Needed to pass 5467 // option tests. Mem_ptr must be a memory operand, else this node 5468 // does not get Flag_needs_anti_dependence_check set by adlc. If this 5469 // is not set this node can be rematerialized which leads to errors. 5470 instruct storePConditional(indirect mem_ptr, rarg5RegP oldval, iRegP_N2P newval, flagsReg cr) %{ 5471 match(Set cr (StorePConditional mem_ptr (Binary oldval newval))); 5472 effect(KILL oldval); 5473 // TODO: s390 port size(FIXED_SIZE); 5474 format %{ "storePConditional $oldval,$newval,$mem_ptr" %} 5475 ins_encode(z_enc_casL(oldval, newval, mem_ptr)); 5476 ins_pipe(pipe_class_dummy); 5477 %} 5478 5479 // As compareAndSwapL, but return flag register instead of boolean value in 5480 // int register. 5481 // Used by sun/misc/AtomicLongCSImpl.java. Mem_ptr must be a memory 5482 // operand, else this node does not get 5483 // Flag_needs_anti_dependence_check set by adlc. If this is not set 5484 // this node can be rematerialized which leads to errors. 5485 instruct storeLConditional(indirect mem_ptr, rarg5RegL oldval, iRegL newval, flagsReg cr) %{ 5486 match(Set cr (StoreLConditional mem_ptr (Binary oldval newval))); 5487 effect(KILL oldval); 5488 // TODO: s390 port size(FIXED_SIZE); 5489 format %{ "storePConditional $oldval,$newval,$mem_ptr" %} 5490 ins_encode(z_enc_casL(oldval, newval, mem_ptr)); 5491 ins_pipe(pipe_class_dummy); 5492 %} 5493 5494 // No flag versions for CompareAndSwap{P,I,L,N} because matcher can't match them. 5495 5496 instruct compareAndSwapI_bool(iRegP mem_ptr, rarg5RegI oldval, iRegI newval, iRegI res, flagsReg cr) %{ 5497 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval))); 5498 effect(USE mem_ptr, USE_KILL oldval, KILL cr); 5499 size(16); 5500 format %{ "$res = CompareAndSwapI $oldval,$newval,$mem_ptr" %} 5501 ins_encode(z_enc_casI(oldval, newval, mem_ptr), 5502 z_enc_cctobool(res)); 5503 ins_pipe(pipe_class_dummy); 5504 %} 5505 5506 instruct compareAndSwapL_bool(iRegP mem_ptr, rarg5RegL oldval, iRegL newval, iRegI res, flagsReg cr) %{ 5507 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval))); 5508 effect(USE mem_ptr, USE_KILL oldval, KILL cr); 5509 size(18); 5510 format %{ "$res = CompareAndSwapL $oldval,$newval,$mem_ptr" %} 5511 ins_encode(z_enc_casL(oldval, newval, mem_ptr), 5512 z_enc_cctobool(res)); 5513 ins_pipe(pipe_class_dummy); 5514 %} 5515 5516 instruct compareAndSwapP_bool(iRegP mem_ptr, rarg5RegP oldval, iRegP_N2P newval, iRegI res, flagsReg cr) %{ 5517 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval))); 5518 effect(USE mem_ptr, USE_KILL oldval, KILL cr); 5519 size(18); 5520 format %{ "$res = CompareAndSwapP $oldval,$newval,$mem_ptr" %} 5521 ins_encode(z_enc_casL(oldval, newval, mem_ptr), 5522 z_enc_cctobool(res)); 5523 ins_pipe(pipe_class_dummy); 5524 %} 5525 5526 instruct compareAndSwapN_bool(iRegP mem_ptr, rarg5RegN oldval, iRegN_P2N newval, iRegI res, flagsReg cr) %{ 5527 match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval))); 5528 effect(USE mem_ptr, USE_KILL oldval, KILL cr); 5529 size(16); 5530 format %{ "$res = CompareAndSwapN $oldval,$newval,$mem_ptr" %} 5531 ins_encode(z_enc_casI(oldval, newval, mem_ptr), 5532 z_enc_cctobool(res)); 5533 ins_pipe(pipe_class_dummy); 5534 %} 5535 5536 //----------Atomic operations on memory (GetAndSet*, GetAndAdd*)--------------- 5537 5538 // Exploit: direct memory arithmetic 5539 // Prereqs: - instructions available 5540 // - instructions guarantee atomicity 5541 // - immediate operand to be added 5542 // - immediate operand is small enough (8-bit signed). 5543 // - result of instruction is not used 5544 instruct addI_mem_imm8_atomic_no_res(memoryRSY mem, Universe dummy, immI8 src, flagsReg cr) %{ 5545 match(Set dummy (GetAndAddI mem src)); 5546 effect(KILL cr); 5547 predicate(VM_Version::has_AtomicMemWithImmALUOps() && n->as_LoadStore()->result_not_used()); 5548 ins_cost(MEMORY_REF_COST); 5549 size(6); 5550 format %{ "ASI [$mem],$src\t # GetAndAddI (atomic)" %} 5551 opcode(ASI_ZOPC); 5552 ins_encode(z_siyform(mem, src)); 5553 ins_pipe(pipe_class_dummy); 5554 %} 5555 5556 // Fallback: direct memory arithmetic not available 5557 // Disadvantages: - CS-Loop required, very expensive. 5558 // - more code generated (26 to xx bytes vs. 6 bytes) 5559 instruct addI_mem_imm16_atomic(memoryRSY mem, iRegI dst, immI16 src, iRegI tmp, flagsReg cr) %{ 5560 match(Set dst (GetAndAddI mem src)); 5561 effect(KILL cr, TEMP_DEF dst, TEMP tmp); 5562 ins_cost(MEMORY_REF_COST+100*DEFAULT_COST); 5563 format %{ "BEGIN ATOMIC {\n\t" 5564 " LGF $dst,[$mem]\n\t" 5565 " AHIK $tmp,$dst,$src\n\t" 5566 " CSY $dst,$tmp,$mem\n\t" 5567 " retry if failed\n\t" 5568 "} END ATOMIC" 5569 %} 5570 ins_encode %{ 5571 Register Rdst = $dst$$Register; 5572 Register Rtmp = $tmp$$Register; 5573 int Isrc = $src$$constant; 5574 Label retry; 5575 5576 // Iterate until update with incremented value succeeds. 5577 __ z_lgf(Rdst, $mem$$Address); // current contents 5578 __ bind(retry); 5579 // Calculate incremented value. 5580 if (VM_Version::has_DistinctOpnds()) { 5581 __ z_ahik(Rtmp, Rdst, Isrc); 5582 } else { 5583 __ z_lr(Rtmp, Rdst); 5584 __ z_ahi(Rtmp, Isrc); 5585 } 5586 // Swap into memory location. 5587 __ z_csy(Rdst, Rtmp, $mem$$Address); // Try to store new value. 5588 __ z_brne(retry); // Yikes, concurrent update, need to retry. 5589 %} 5590 ins_pipe(pipe_class_dummy); 5591 %} 5592 5593 instruct addI_mem_imm32_atomic(memoryRSY mem, iRegI dst, immI src, iRegI tmp, flagsReg cr) %{ 5594 match(Set dst (GetAndAddI mem src)); 5595 effect(KILL cr, TEMP_DEF dst, TEMP tmp); 5596 ins_cost(MEMORY_REF_COST+200*DEFAULT_COST); 5597 format %{ "BEGIN ATOMIC {\n\t" 5598 " LGF $dst,[$mem]\n\t" 5599 " LGR $tmp,$dst\n\t" 5600 " AFI $tmp,$src\n\t" 5601 " CSY $dst,$tmp,$mem\n\t" 5602 " retry if failed\n\t" 5603 "} END ATOMIC" 5604 %} 5605 ins_encode %{ 5606 Register Rdst = $dst$$Register; 5607 Register Rtmp = $tmp$$Register; 5608 int Isrc = $src$$constant; 5609 Label retry; 5610 5611 // Iterate until update with incremented value succeeds. 5612 __ z_lgf(Rdst, $mem$$Address); // current contents 5613 __ bind(retry); 5614 // Calculate incremented value. 5615 __ z_lr(Rtmp, Rdst); 5616 __ z_afi(Rtmp, Isrc); 5617 // Swap into memory location. 5618 __ z_csy(Rdst, Rtmp, $mem$$Address); // Try to store new value. 5619 __ z_brne(retry); // Yikes, concurrent update, need to retry. 5620 %} 5621 ins_pipe(pipe_class_dummy); 5622 %} 5623 5624 instruct addI_mem_reg_atomic(memoryRSY mem, iRegI dst, iRegI src, iRegI tmp, flagsReg cr) %{ 5625 match(Set dst (GetAndAddI mem src)); 5626 effect(KILL cr, TEMP_DEF dst, TEMP tmp); 5627 ins_cost(MEMORY_REF_COST+100*DEFAULT_COST); 5628 format %{ "BEGIN ATOMIC {\n\t" 5629 " LGF $dst,[$mem]\n\t" 5630 " ARK $tmp,$dst,$src\n\t" 5631 " CSY $dst,$tmp,$mem\n\t" 5632 " retry if failed\n\t" 5633 "} END ATOMIC" 5634 %} 5635 ins_encode %{ 5636 Register Rsrc = $src$$Register; 5637 Register Rdst = $dst$$Register; 5638 Register Rtmp = $tmp$$Register; 5639 Label retry; 5640 5641 // Iterate until update with incremented value succeeds. 5642 __ z_lgf(Rdst, $mem$$Address); // current contents 5643 __ bind(retry); 5644 // Calculate incremented value. 5645 if (VM_Version::has_DistinctOpnds()) { 5646 __ z_ark(Rtmp, Rdst, Rsrc); 5647 } else { 5648 __ z_lr(Rtmp, Rdst); 5649 __ z_ar(Rtmp, Rsrc); 5650 } 5651 __ z_csy(Rdst, Rtmp, $mem$$Address); // Try to store new value. 5652 __ z_brne(retry); // Yikes, concurrent update, need to retry. 5653 %} 5654 ins_pipe(pipe_class_dummy); 5655 %} 5656 5657 5658 // Exploit: direct memory arithmetic 5659 // Prereqs: - instructions available 5660 // - instructions guarantee atomicity 5661 // - immediate operand to be added 5662 // - immediate operand is small enough (8-bit signed). 5663 // - result of instruction is not used 5664 instruct addL_mem_imm8_atomic_no_res(memoryRSY mem, Universe dummy, immL8 src, flagsReg cr) %{ 5665 match(Set dummy (GetAndAddL mem src)); 5666 effect(KILL cr); 5667 predicate(VM_Version::has_AtomicMemWithImmALUOps() && n->as_LoadStore()->result_not_used()); 5668 ins_cost(MEMORY_REF_COST); 5669 size(6); 5670 format %{ "AGSI [$mem],$src\t # GetAndAddL (atomic)" %} 5671 opcode(AGSI_ZOPC); 5672 ins_encode(z_siyform(mem, src)); 5673 ins_pipe(pipe_class_dummy); 5674 %} 5675 5676 // Fallback: direct memory arithmetic not available 5677 // Disadvantages: - CS-Loop required, very expensive. 5678 // - more code generated (26 to xx bytes vs. 6 bytes) 5679 instruct addL_mem_imm16_atomic(memoryRSY mem, iRegL dst, immL16 src, iRegL tmp, flagsReg cr) %{ 5680 match(Set dst (GetAndAddL mem src)); 5681 effect(KILL cr, TEMP_DEF dst, TEMP tmp); 5682 ins_cost(MEMORY_REF_COST+100*DEFAULT_COST); 5683 format %{ "BEGIN ATOMIC {\n\t" 5684 " LG $dst,[$mem]\n\t" 5685 " AGHIK $tmp,$dst,$src\n\t" 5686 " CSG $dst,$tmp,$mem\n\t" 5687 " retry if failed\n\t" 5688 "} END ATOMIC" 5689 %} 5690 ins_encode %{ 5691 Register Rdst = $dst$$Register; 5692 Register Rtmp = $tmp$$Register; 5693 int Isrc = $src$$constant; 5694 Label retry; 5695 5696 // Iterate until update with incremented value succeeds. 5697 __ z_lg(Rdst, $mem$$Address); // current contents 5698 __ bind(retry); 5699 // Calculate incremented value. 5700 if (VM_Version::has_DistinctOpnds()) { 5701 __ z_aghik(Rtmp, Rdst, Isrc); 5702 } else { 5703 __ z_lgr(Rtmp, Rdst); 5704 __ z_aghi(Rtmp, Isrc); 5705 } 5706 __ z_csg(Rdst, Rtmp, $mem$$Address); // Try to store new value. 5707 __ z_brne(retry); // Yikes, concurrent update, need to retry. 5708 %} 5709 ins_pipe(pipe_class_dummy); 5710 %} 5711 5712 instruct addL_mem_imm32_atomic(memoryRSY mem, iRegL dst, immL32 src, iRegL tmp, flagsReg cr) %{ 5713 match(Set dst (GetAndAddL mem src)); 5714 effect(KILL cr, TEMP_DEF dst, TEMP tmp); 5715 ins_cost(MEMORY_REF_COST+100*DEFAULT_COST); 5716 format %{ "BEGIN ATOMIC {\n\t" 5717 " LG $dst,[$mem]\n\t" 5718 " LGR $tmp,$dst\n\t" 5719 " AGFI $tmp,$src\n\t" 5720 " CSG $dst,$tmp,$mem\n\t" 5721 " retry if failed\n\t" 5722 "} END ATOMIC" 5723 %} 5724 ins_encode %{ 5725 Register Rdst = $dst$$Register; 5726 Register Rtmp = $tmp$$Register; 5727 int Isrc = $src$$constant; 5728 Label retry; 5729 5730 // Iterate until update with incremented value succeeds. 5731 __ z_lg(Rdst, $mem$$Address); // current contents 5732 __ bind(retry); 5733 // Calculate incremented value. 5734 __ z_lgr(Rtmp, Rdst); 5735 __ z_agfi(Rtmp, Isrc); 5736 __ z_csg(Rdst, Rtmp, $mem$$Address); // Try to store new value. 5737 __ z_brne(retry); // Yikes, concurrent update, need to retry. 5738 %} 5739 ins_pipe(pipe_class_dummy); 5740 %} 5741 5742 instruct addL_mem_reg_atomic(memoryRSY mem, iRegL dst, iRegL src, iRegL tmp, flagsReg cr) %{ 5743 match(Set dst (GetAndAddL mem src)); 5744 effect(KILL cr, TEMP_DEF dst, TEMP tmp); 5745 ins_cost(MEMORY_REF_COST+100*DEFAULT_COST); 5746 format %{ "BEGIN ATOMIC {\n\t" 5747 " LG $dst,[$mem]\n\t" 5748 " AGRK $tmp,$dst,$src\n\t" 5749 " CSG $dst,$tmp,$mem\n\t" 5750 " retry if failed\n\t" 5751 "} END ATOMIC" 5752 %} 5753 ins_encode %{ 5754 Register Rsrc = $src$$Register; 5755 Register Rdst = $dst$$Register; 5756 Register Rtmp = $tmp$$Register; 5757 Label retry; 5758 5759 // Iterate until update with incremented value succeeds. 5760 __ z_lg(Rdst, $mem$$Address); // current contents 5761 __ bind(retry); 5762 // Calculate incremented value. 5763 if (VM_Version::has_DistinctOpnds()) { 5764 __ z_agrk(Rtmp, Rdst, Rsrc); 5765 } else { 5766 __ z_lgr(Rtmp, Rdst); 5767 __ z_agr(Rtmp, Rsrc); 5768 } 5769 __ z_csg(Rdst, Rtmp, $mem$$Address); // Try to store new value. 5770 __ z_brne(retry); // Yikes, concurrent update, need to retry. 5771 %} 5772 ins_pipe(pipe_class_dummy); 5773 %} 5774 5775 // Increment value in memory, save old value in dst. 5776 instruct addI_mem_reg_atomic_z196(memoryRSY mem, iRegI dst, iRegI src) %{ 5777 match(Set dst (GetAndAddI mem src)); 5778 predicate(VM_Version::has_LoadAndALUAtomicV1()); 5779 ins_cost(MEMORY_REF_COST + DEFAULT_COST); 5780 size(6); 5781 format %{ "LAA $dst,$src,[$mem]" %} 5782 ins_encode %{ __ z_laa($dst$$Register, $src$$Register, $mem$$Address); %} 5783 ins_pipe(pipe_class_dummy); 5784 %} 5785 5786 // Increment value in memory, save old value in dst. 5787 instruct addL_mem_reg_atomic_z196(memoryRSY mem, iRegL dst, iRegL src) %{ 5788 match(Set dst (GetAndAddL mem src)); 5789 predicate(VM_Version::has_LoadAndALUAtomicV1()); 5790 ins_cost(MEMORY_REF_COST + DEFAULT_COST); 5791 size(6); 5792 format %{ "LAAG $dst,$src,[$mem]" %} 5793 ins_encode %{ __ z_laag($dst$$Register, $src$$Register, $mem$$Address); %} 5794 ins_pipe(pipe_class_dummy); 5795 %} 5796 5797 5798 instruct xchgI_reg_mem(memoryRSY mem, iRegI dst, iRegI tmp, flagsReg cr) %{ 5799 match(Set dst (GetAndSetI mem dst)); 5800 effect(KILL cr, TEMP tmp); // USE_DEF dst by match rule. 5801 format %{ "XCHGI $dst,[$mem]\t # EXCHANGE (int, atomic), temp $tmp" %} 5802 ins_encode(z_enc_SwapI(mem, dst, tmp)); 5803 ins_pipe(pipe_class_dummy); 5804 %} 5805 5806 instruct xchgL_reg_mem(memoryRSY mem, iRegL dst, iRegL tmp, flagsReg cr) %{ 5807 match(Set dst (GetAndSetL mem dst)); 5808 effect(KILL cr, TEMP tmp); // USE_DEF dst by match rule. 5809 format %{ "XCHGL $dst,[$mem]\t # EXCHANGE (long, atomic), temp $tmp" %} 5810 ins_encode(z_enc_SwapL(mem, dst, tmp)); 5811 ins_pipe(pipe_class_dummy); 5812 %} 5813 5814 instruct xchgN_reg_mem(memoryRSY mem, iRegN dst, iRegI tmp, flagsReg cr) %{ 5815 match(Set dst (GetAndSetN mem dst)); 5816 effect(KILL cr, TEMP tmp); // USE_DEF dst by match rule. 5817 format %{ "XCHGN $dst,[$mem]\t # EXCHANGE (coop, atomic), temp $tmp" %} 5818 ins_encode(z_enc_SwapI(mem, dst, tmp)); 5819 ins_pipe(pipe_class_dummy); 5820 %} 5821 5822 instruct xchgP_reg_mem(memoryRSY mem, iRegP dst, iRegL tmp, flagsReg cr) %{ 5823 match(Set dst (GetAndSetP mem dst)); 5824 effect(KILL cr, TEMP tmp); // USE_DEF dst by match rule. 5825 format %{ "XCHGP $dst,[$mem]\t # EXCHANGE (oop, atomic), temp $tmp" %} 5826 ins_encode(z_enc_SwapL(mem, dst, tmp)); 5827 ins_pipe(pipe_class_dummy); 5828 %} 5829 5830 5831 //----------Arithmetic Instructions-------------------------------------------- 5832 5833 // The rules are sorted by right operand type and operand length. Please keep 5834 // it that way. 5835 // Left operand type is always reg. Left operand len is I, L, P 5836 // Right operand type is reg, imm, mem. Right operand len is S, I, L, P 5837 // Special instruction formats, e.g. multi-operand, are inserted at the end. 5838 5839 // ADD 5840 5841 // REG = REG + REG 5842 5843 // Register Addition 5844 instruct addI_reg_reg_CISC(iRegI dst, iRegI src, flagsReg cr) %{ 5845 match(Set dst (AddI dst src)); 5846 effect(KILL cr); 5847 // TODO: s390 port size(FIXED_SIZE); 5848 format %{ "AR $dst,$src\t # int CISC ALU" %} 5849 opcode(AR_ZOPC); 5850 ins_encode(z_rrform(dst, src)); 5851 ins_pipe(pipe_class_dummy); 5852 %} 5853 5854 // Avoid use of LA(Y) for general ALU operation. 5855 instruct addI_reg_reg_RISC(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{ 5856 match(Set dst (AddI src1 src2)); 5857 effect(KILL cr); 5858 predicate(VM_Version::has_DistinctOpnds()); 5859 ins_cost(DEFAULT_COST); 5860 size(4); 5861 format %{ "ARK $dst,$src1,$src2\t # int RISC ALU" %} 5862 opcode(ARK_ZOPC); 5863 ins_encode(z_rrfform(dst, src1, src2)); 5864 ins_pipe(pipe_class_dummy); 5865 %} 5866 5867 // REG = REG + IMM 5868 5869 // Avoid use of LA(Y) for general ALU operation. 5870 // Immediate Addition 5871 instruct addI_reg_imm16_CISC(iRegI dst, immI16 con, flagsReg cr) %{ 5872 match(Set dst (AddI dst con)); 5873 effect(KILL cr); 5874 ins_cost(DEFAULT_COST); 5875 // TODO: s390 port size(FIXED_SIZE); 5876 format %{ "AHI $dst,$con\t # int CISC ALU" %} 5877 opcode(AHI_ZOPC); 5878 ins_encode(z_riform_signed(dst, con)); 5879 ins_pipe(pipe_class_dummy); 5880 %} 5881 5882 // Avoid use of LA(Y) for general ALU operation. 5883 // Immediate Addition 5884 instruct addI_reg_imm16_RISC(iRegI dst, iRegI src, immI16 con, flagsReg cr) %{ 5885 match(Set dst (AddI src con)); 5886 effect(KILL cr); 5887 predicate( VM_Version::has_DistinctOpnds()); 5888 ins_cost(DEFAULT_COST); 5889 // TODO: s390 port size(FIXED_SIZE); 5890 format %{ "AHIK $dst,$src,$con\t # int RISC ALU" %} 5891 opcode(AHIK_ZOPC); 5892 ins_encode(z_rieform_d(dst, src, con)); 5893 ins_pipe(pipe_class_dummy); 5894 %} 5895 5896 // Immediate Addition 5897 instruct addI_reg_imm32(iRegI dst, immI src, flagsReg cr) %{ 5898 match(Set dst (AddI dst src)); 5899 effect(KILL cr); 5900 ins_cost(DEFAULT_COST_HIGH); 5901 size(6); 5902 format %{ "AFI $dst,$src" %} 5903 opcode(AFI_ZOPC); 5904 ins_encode(z_rilform_signed(dst, src)); 5905 ins_pipe(pipe_class_dummy); 5906 %} 5907 5908 // Immediate Addition 5909 instruct addI_reg_imm12(iRegI dst, iRegI src, uimmI12 con) %{ 5910 match(Set dst (AddI src con)); 5911 predicate(PreferLAoverADD); 5912 ins_cost(DEFAULT_COST_LOW); 5913 size(4); 5914 format %{ "LA $dst,$con(,$src)\t # int d12(,b)" %} 5915 opcode(LA_ZOPC); 5916 ins_encode(z_rxform_imm_reg(dst, con, src)); 5917 ins_pipe(pipe_class_dummy); 5918 %} 5919 5920 // Immediate Addition 5921 instruct addI_reg_imm20(iRegI dst, iRegI src, immI20 con) %{ 5922 match(Set dst (AddI src con)); 5923 predicate(PreferLAoverADD); 5924 ins_cost(DEFAULT_COST); 5925 size(6); 5926 format %{ "LAY $dst,$con(,$src)\t # int d20(,b)" %} 5927 opcode(LAY_ZOPC); 5928 ins_encode(z_rxyform_imm_reg(dst, con, src)); 5929 ins_pipe(pipe_class_dummy); 5930 %} 5931 5932 instruct addI_reg_reg_imm12(iRegI dst, iRegI src1, iRegI src2, uimmI12 con) %{ 5933 match(Set dst (AddI (AddI src1 src2) con)); 5934 predicate( PreferLAoverADD); 5935 ins_cost(DEFAULT_COST_LOW); 5936 size(4); 5937 format %{ "LA $dst,$con($src1,$src2)\t # int d12(x,b)" %} 5938 opcode(LA_ZOPC); 5939 ins_encode(z_rxform_imm_reg_reg(dst, con, src1, src2)); 5940 ins_pipe(pipe_class_dummy); 5941 %} 5942 5943 instruct addI_reg_reg_imm20(iRegI dst, iRegI src1, iRegI src2, immI20 con) %{ 5944 match(Set dst (AddI (AddI src1 src2) con)); 5945 predicate(PreferLAoverADD); 5946 ins_cost(DEFAULT_COST); 5947 size(6); 5948 format %{ "LAY $dst,$con($src1,$src2)\t # int d20(x,b)" %} 5949 opcode(LAY_ZOPC); 5950 ins_encode(z_rxyform_imm_reg_reg(dst, con, src1, src2)); 5951 ins_pipe(pipe_class_dummy); 5952 %} 5953 5954 // REG = REG + MEM 5955 5956 instruct addI_Reg_mem(iRegI dst, memory src, flagsReg cr)%{ 5957 match(Set dst (AddI dst (LoadI src))); 5958 effect(KILL cr); 5959 ins_cost(MEMORY_REF_COST); 5960 // TODO: s390 port size(VARIABLE_SIZE); 5961 format %{ "A(Y) $dst, $src\t # int" %} 5962 opcode(AY_ZOPC, A_ZOPC); 5963 ins_encode(z_form_rt_mem_opt(dst, src)); 5964 ins_pipe(pipe_class_dummy); 5965 %} 5966 5967 // MEM = MEM + IMM 5968 5969 // Add Immediate to 4-byte memory operand and result 5970 instruct addI_mem_imm(memoryRSY mem, immI8 src, flagsReg cr) %{ 5971 match(Set mem (StoreI mem (AddI (LoadI mem) src))); 5972 effect(KILL cr); 5973 predicate(VM_Version::has_MemWithImmALUOps()); 5974 ins_cost(MEMORY_REF_COST); 5975 size(6); 5976 format %{ "ASI $mem,$src\t # direct mem add 4" %} 5977 opcode(ASI_ZOPC); 5978 ins_encode(z_siyform(mem, src)); 5979 ins_pipe(pipe_class_dummy); 5980 %} 5981 5982 5983 // 5984 5985 // REG = REG + REG 5986 5987 instruct addL_reg_regI(iRegL dst, iRegI src, flagsReg cr) %{ 5988 match(Set dst (AddL dst (ConvI2L src))); 5989 effect(KILL cr); 5990 size(4); 5991 format %{ "AGFR $dst,$src\t # long<-int CISC ALU" %} 5992 opcode(AGFR_ZOPC); 5993 ins_encode(z_rreform(dst, src)); 5994 ins_pipe(pipe_class_dummy); 5995 %} 5996 5997 instruct addL_reg_reg_CISC(iRegL dst, iRegL src, flagsReg cr) %{ 5998 match(Set dst (AddL dst src)); 5999 effect(KILL cr); 6000 // TODO: s390 port size(FIXED_SIZE); 6001 format %{ "AGR $dst, $src\t # long CISC ALU" %} 6002 opcode(AGR_ZOPC); 6003 ins_encode(z_rreform(dst, src)); 6004 ins_pipe(pipe_class_dummy); 6005 %} 6006 6007 // Avoid use of LA(Y) for general ALU operation. 6008 instruct addL_reg_reg_RISC(iRegL dst, iRegL src1, iRegL src2, flagsReg cr) %{ 6009 match(Set dst (AddL src1 src2)); 6010 effect(KILL cr); 6011 predicate(VM_Version::has_DistinctOpnds()); 6012 ins_cost(DEFAULT_COST); 6013 size(4); 6014 format %{ "AGRK $dst,$src1,$src2\t # long RISC ALU" %} 6015 opcode(AGRK_ZOPC); 6016 ins_encode(z_rrfform(dst, src1, src2)); 6017 ins_pipe(pipe_class_dummy); 6018 %} 6019 6020 // REG = REG + IMM 6021 6022 instruct addL_reg_imm12(iRegL dst, iRegL src, uimmL12 con) %{ 6023 match(Set dst (AddL src con)); 6024 predicate( PreferLAoverADD); 6025 ins_cost(DEFAULT_COST_LOW); 6026 size(4); 6027 format %{ "LA $dst,$con(,$src)\t # long d12(,b)" %} 6028 opcode(LA_ZOPC); 6029 ins_encode(z_rxform_imm_reg(dst, con, src)); 6030 ins_pipe(pipe_class_dummy); 6031 %} 6032 6033 instruct addL_reg_imm20(iRegL dst, iRegL src, immL20 con) %{ 6034 match(Set dst (AddL src con)); 6035 predicate(PreferLAoverADD); 6036 ins_cost(DEFAULT_COST); 6037 size(6); 6038 format %{ "LAY $dst,$con(,$src)\t # long d20(,b)" %} 6039 opcode(LAY_ZOPC); 6040 ins_encode(z_rxyform_imm_reg(dst, con, src)); 6041 ins_pipe(pipe_class_dummy); 6042 %} 6043 6044 instruct addL_reg_imm32(iRegL dst, immL32 con, flagsReg cr) %{ 6045 match(Set dst (AddL dst con)); 6046 effect(KILL cr); 6047 ins_cost(DEFAULT_COST_HIGH); 6048 size(6); 6049 format %{ "AGFI $dst,$con\t # long CISC ALU" %} 6050 opcode(AGFI_ZOPC); 6051 ins_encode(z_rilform_signed(dst, con)); 6052 ins_pipe(pipe_class_dummy); 6053 %} 6054 6055 // Avoid use of LA(Y) for general ALU operation. 6056 instruct addL_reg_imm16_CISC(iRegL dst, immL16 con, flagsReg cr) %{ 6057 match(Set dst (AddL dst con)); 6058 effect(KILL cr); 6059 ins_cost(DEFAULT_COST); 6060 // TODO: s390 port size(FIXED_SIZE); 6061 format %{ "AGHI $dst,$con\t # long CISC ALU" %} 6062 opcode(AGHI_ZOPC); 6063 ins_encode(z_riform_signed(dst, con)); 6064 ins_pipe(pipe_class_dummy); 6065 %} 6066 6067 // Avoid use of LA(Y) for general ALU operation. 6068 instruct addL_reg_imm16_RISC(iRegL dst, iRegL src, immL16 con, flagsReg cr) %{ 6069 match(Set dst (AddL src con)); 6070 effect(KILL cr); 6071 predicate( VM_Version::has_DistinctOpnds()); 6072 ins_cost(DEFAULT_COST); 6073 size(6); 6074 format %{ "AGHIK $dst,$src,$con\t # long RISC ALU" %} 6075 opcode(AGHIK_ZOPC); 6076 ins_encode(z_rieform_d(dst, src, con)); 6077 ins_pipe(pipe_class_dummy); 6078 %} 6079 6080 // REG = REG + MEM 6081 6082 instruct addL_Reg_memI(iRegL dst, memory src, flagsReg cr)%{ 6083 match(Set dst (AddL dst (ConvI2L (LoadI src)))); 6084 effect(KILL cr); 6085 ins_cost(MEMORY_REF_COST); 6086 size(Z_DISP3_SIZE); 6087 format %{ "AGF $dst, $src\t # long/int" %} 6088 opcode(AGF_ZOPC, AGF_ZOPC); 6089 ins_encode(z_form_rt_mem_opt(dst, src)); 6090 ins_pipe(pipe_class_dummy); 6091 %} 6092 6093 instruct addL_Reg_mem(iRegL dst, memory src, flagsReg cr)%{ 6094 match(Set dst (AddL dst (LoadL src))); 6095 effect(KILL cr); 6096 ins_cost(MEMORY_REF_COST); 6097 size(Z_DISP3_SIZE); 6098 format %{ "AG $dst, $src\t # long" %} 6099 opcode(AG_ZOPC, AG_ZOPC); 6100 ins_encode(z_form_rt_mem_opt(dst, src)); 6101 ins_pipe(pipe_class_dummy); 6102 %} 6103 6104 instruct addL_reg_reg_imm12(iRegL dst, iRegL src1, iRegL src2, uimmL12 con) %{ 6105 match(Set dst (AddL (AddL src1 src2) con)); 6106 predicate( PreferLAoverADD); 6107 ins_cost(DEFAULT_COST_LOW); 6108 size(4); 6109 format %{ "LA $dst,$con($src1,$src2)\t # long d12(x,b)" %} 6110 opcode(LA_ZOPC); 6111 ins_encode(z_rxform_imm_reg_reg(dst, con, src1, src2)); 6112 ins_pipe(pipe_class_dummy); 6113 %} 6114 6115 instruct addL_reg_reg_imm20(iRegL dst, iRegL src1, iRegL src2, immL20 con) %{ 6116 match(Set dst (AddL (AddL src1 src2) con)); 6117 predicate(PreferLAoverADD); 6118 ins_cost(DEFAULT_COST); 6119 size(6); 6120 format %{ "LAY $dst,$con($src1,$src2)\t # long d20(x,b)" %} 6121 opcode(LAY_ZOPC); 6122 ins_encode(z_rxyform_imm_reg_reg(dst, con, src1, src2)); 6123 ins_pipe(pipe_class_dummy); 6124 %} 6125 6126 // MEM = MEM + IMM 6127 6128 // Add Immediate to 8-byte memory operand and result. 6129 instruct addL_mem_imm(memoryRSY mem, immL8 src, flagsReg cr) %{ 6130 match(Set mem (StoreL mem (AddL (LoadL mem) src))); 6131 effect(KILL cr); 6132 predicate(VM_Version::has_MemWithImmALUOps()); 6133 ins_cost(MEMORY_REF_COST); 6134 size(6); 6135 format %{ "AGSI $mem,$src\t # direct mem add 8" %} 6136 opcode(AGSI_ZOPC); 6137 ins_encode(z_siyform(mem, src)); 6138 ins_pipe(pipe_class_dummy); 6139 %} 6140 6141 6142 // REG = REG + REG 6143 6144 // Ptr Addition 6145 instruct addP_reg_reg_LA(iRegP dst, iRegP_N2P src1, iRegL src2) %{ 6146 match(Set dst (AddP src1 src2)); 6147 predicate( PreferLAoverADD); 6148 ins_cost(DEFAULT_COST); 6149 size(4); 6150 format %{ "LA $dst,#0($src1,$src2)\t # ptr 0(x,b)" %} 6151 opcode(LA_ZOPC); 6152 ins_encode(z_rxform_imm_reg_reg(dst, 0x0, src1, src2)); 6153 ins_pipe(pipe_class_dummy); 6154 %} 6155 6156 // Ptr Addition 6157 // Avoid use of LA(Y) for general ALU operation. 6158 instruct addP_reg_reg_CISC(iRegP dst, iRegL src, flagsReg cr) %{ 6159 match(Set dst (AddP dst src)); 6160 effect(KILL cr); 6161 predicate(!PreferLAoverADD && !VM_Version::has_DistinctOpnds()); 6162 ins_cost(DEFAULT_COST); 6163 // TODO: s390 port size(FIXED_SIZE); 6164 format %{ "ALGR $dst,$src\t # ptr CICS ALU" %} 6165 opcode(ALGR_ZOPC); 6166 ins_encode(z_rreform(dst, src)); 6167 ins_pipe(pipe_class_dummy); 6168 %} 6169 6170 // Ptr Addition 6171 // Avoid use of LA(Y) for general ALU operation. 6172 instruct addP_reg_reg_RISC(iRegP dst, iRegP_N2P src1, iRegL src2, flagsReg cr) %{ 6173 match(Set dst (AddP src1 src2)); 6174 effect(KILL cr); 6175 predicate(!PreferLAoverADD && VM_Version::has_DistinctOpnds()); 6176 ins_cost(DEFAULT_COST); 6177 // TODO: s390 port size(FIXED_SIZE); 6178 format %{ "ALGRK $dst,$src1,$src2\t # ptr RISC ALU" %} 6179 opcode(ALGRK_ZOPC); 6180 ins_encode(z_rrfform(dst, src1, src2)); 6181 ins_pipe(pipe_class_dummy); 6182 %} 6183 6184 // REG = REG + IMM 6185 6186 instruct addP_reg_imm12(iRegP dst, iRegP_N2P src, uimmL12 con) %{ 6187 match(Set dst (AddP src con)); 6188 predicate( PreferLAoverADD); 6189 ins_cost(DEFAULT_COST_LOW); 6190 size(4); 6191 format %{ "LA $dst,$con(,$src)\t # ptr d12(,b)" %} 6192 opcode(LA_ZOPC); 6193 ins_encode(z_rxform_imm_reg(dst, con, src)); 6194 ins_pipe(pipe_class_dummy); 6195 %} 6196 6197 // Avoid use of LA(Y) for general ALU operation. 6198 instruct addP_reg_imm16_CISC(iRegP dst, immL16 src, flagsReg cr) %{ 6199 match(Set dst (AddP dst src)); 6200 effect(KILL cr); 6201 predicate(!PreferLAoverADD && !VM_Version::has_DistinctOpnds()); 6202 ins_cost(DEFAULT_COST); 6203 // TODO: s390 port size(FIXED_SIZE); 6204 format %{ "AGHI $dst,$src\t # ptr CISC ALU" %} 6205 opcode(AGHI_ZOPC); 6206 ins_encode(z_riform_signed(dst, src)); 6207 ins_pipe(pipe_class_dummy); 6208 %} 6209 6210 // Avoid use of LA(Y) for general ALU operation. 6211 instruct addP_reg_imm16_RISC(iRegP dst, iRegP_N2P src, immL16 con, flagsReg cr) %{ 6212 match(Set dst (AddP src con)); 6213 effect(KILL cr); 6214 predicate(!PreferLAoverADD && VM_Version::has_DistinctOpnds()); 6215 ins_cost(DEFAULT_COST); 6216 // TODO: s390 port size(FIXED_SIZE); 6217 format %{ "ALGHSIK $dst,$src,$con\t # ptr RISC ALU" %} 6218 opcode(ALGHSIK_ZOPC); 6219 ins_encode(z_rieform_d(dst, src, con)); 6220 ins_pipe(pipe_class_dummy); 6221 %} 6222 6223 instruct addP_reg_imm20(iRegP dst, memoryRegP src, immL20 con) %{ 6224 match(Set dst (AddP src con)); 6225 predicate(PreferLAoverADD); 6226 ins_cost(DEFAULT_COST); 6227 size(6); 6228 format %{ "LAY $dst,$con(,$src)\t # ptr d20(,b)" %} 6229 opcode(LAY_ZOPC); 6230 ins_encode(z_rxyform_imm_reg(dst, con, src)); 6231 ins_pipe(pipe_class_dummy); 6232 %} 6233 6234 // Pointer Immediate Addition 6235 instruct addP_reg_imm32(iRegP dst, immL32 src, flagsReg cr) %{ 6236 match(Set dst (AddP dst src)); 6237 effect(KILL cr); 6238 ins_cost(DEFAULT_COST_HIGH); 6239 // TODO: s390 port size(FIXED_SIZE); 6240 format %{ "AGFI $dst,$src\t # ptr" %} 6241 opcode(AGFI_ZOPC); 6242 ins_encode(z_rilform_signed(dst, src)); 6243 ins_pipe(pipe_class_dummy); 6244 %} 6245 6246 // REG = REG1 + REG2 + IMM 6247 6248 instruct addP_reg_reg_imm12(iRegP dst, memoryRegP src1, iRegL src2, uimmL12 con) %{ 6249 match(Set dst (AddP (AddP src1 src2) con)); 6250 predicate( PreferLAoverADD); 6251 ins_cost(DEFAULT_COST_LOW); 6252 size(4); 6253 format %{ "LA $dst,$con($src1,$src2)\t # ptr d12(x,b)" %} 6254 opcode(LA_ZOPC); 6255 ins_encode(z_rxform_imm_reg_reg(dst, con, src1, src2)); 6256 ins_pipe(pipe_class_dummy); 6257 %} 6258 6259 instruct addP_regN_reg_imm12(iRegP dst, iRegP_N2P src1, iRegL src2, uimmL12 con) %{ 6260 match(Set dst (AddP (AddP src1 src2) con)); 6261 predicate( PreferLAoverADD && CompressedOops::base() == NULL && CompressedOops::shift() == 0); 6262 ins_cost(DEFAULT_COST_LOW); 6263 size(4); 6264 format %{ "LA $dst,$con($src1,$src2)\t # ptr d12(x,b)" %} 6265 opcode(LA_ZOPC); 6266 ins_encode(z_rxform_imm_reg_reg(dst, con, src1, src2)); 6267 ins_pipe(pipe_class_dummy); 6268 %} 6269 6270 instruct addP_reg_reg_imm20(iRegP dst, memoryRegP src1, iRegL src2, immL20 con) %{ 6271 match(Set dst (AddP (AddP src1 src2) con)); 6272 predicate(PreferLAoverADD); 6273 ins_cost(DEFAULT_COST); 6274 // TODO: s390 port size(FIXED_SIZE); 6275 format %{ "LAY $dst,$con($src1,$src2)\t # ptr d20(x,b)" %} 6276 opcode(LAY_ZOPC); 6277 ins_encode(z_rxyform_imm_reg_reg(dst, con, src1, src2)); 6278 ins_pipe(pipe_class_dummy); 6279 %} 6280 6281 instruct addP_regN_reg_imm20(iRegP dst, iRegP_N2P src1, iRegL src2, immL20 con) %{ 6282 match(Set dst (AddP (AddP src1 src2) con)); 6283 predicate( PreferLAoverADD && CompressedOops::base() == NULL && CompressedOops::shift() == 0); 6284 ins_cost(DEFAULT_COST); 6285 // TODO: s390 port size(FIXED_SIZE); 6286 format %{ "LAY $dst,$con($src1,$src2)\t # ptr d20(x,b)" %} 6287 opcode(LAY_ZOPC); 6288 ins_encode(z_rxyform_imm_reg_reg(dst, con, src1, src2)); 6289 ins_pipe(pipe_class_dummy); 6290 %} 6291 6292 // MEM = MEM + IMM 6293 6294 // Add Immediate to 8-byte memory operand and result 6295 instruct addP_mem_imm(memoryRSY mem, immL8 src, flagsReg cr) %{ 6296 match(Set mem (StoreP mem (AddP (LoadP mem) src))); 6297 effect(KILL cr); 6298 predicate(VM_Version::has_MemWithImmALUOps()); 6299 ins_cost(MEMORY_REF_COST); 6300 size(6); 6301 format %{ "AGSI $mem,$src\t # direct mem add 8 (ptr)" %} 6302 opcode(AGSI_ZOPC); 6303 ins_encode(z_siyform(mem, src)); 6304 ins_pipe(pipe_class_dummy); 6305 %} 6306 6307 // SUB 6308 6309 // Register Subtraction 6310 instruct subI_reg_reg_CISC(iRegI dst, iRegI src, flagsReg cr) %{ 6311 match(Set dst (SubI dst src)); 6312 effect(KILL cr); 6313 // TODO: s390 port size(FIXED_SIZE); 6314 format %{ "SR $dst,$src\t # int CISC ALU" %} 6315 opcode(SR_ZOPC); 6316 ins_encode(z_rrform(dst, src)); 6317 ins_pipe(pipe_class_dummy); 6318 %} 6319 6320 instruct subI_reg_reg_RISC(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{ 6321 match(Set dst (SubI src1 src2)); 6322 effect(KILL cr); 6323 predicate(VM_Version::has_DistinctOpnds()); 6324 ins_cost(DEFAULT_COST); 6325 size(4); 6326 format %{ "SRK $dst,$src1,$src2\t # int RISC ALU" %} 6327 opcode(SRK_ZOPC); 6328 ins_encode(z_rrfform(dst, src1, src2)); 6329 ins_pipe(pipe_class_dummy); 6330 %} 6331 6332 instruct subI_Reg_mem(iRegI dst, memory src, flagsReg cr)%{ 6333 match(Set dst (SubI dst (LoadI src))); 6334 effect(KILL cr); 6335 ins_cost(MEMORY_REF_COST); 6336 // TODO: s390 port size(VARIABLE_SIZE); 6337 format %{ "S(Y) $dst, $src\t # int" %} 6338 opcode(SY_ZOPC, S_ZOPC); 6339 ins_encode(z_form_rt_mem_opt(dst, src)); 6340 ins_pipe(pipe_class_dummy); 6341 %} 6342 6343 instruct subI_zero_reg(iRegI dst, immI_0 zero, iRegI src, flagsReg cr) %{ 6344 match(Set dst (SubI zero src)); 6345 effect(KILL cr); 6346 size(2); 6347 format %{ "NEG $dst, $src" %} 6348 ins_encode %{ __ z_lcr($dst$$Register, $src$$Register); %} 6349 ins_pipe(pipe_class_dummy); 6350 %} 6351 6352 // 6353 6354 // Long subtraction 6355 instruct subL_reg_reg_CISC(iRegL dst, iRegL src, flagsReg cr) %{ 6356 match(Set dst (SubL dst src)); 6357 effect(KILL cr); 6358 // TODO: s390 port size(FIXED_SIZE); 6359 format %{ "SGR $dst,$src\t # int CISC ALU" %} 6360 opcode(SGR_ZOPC); 6361 ins_encode(z_rreform(dst, src)); 6362 ins_pipe(pipe_class_dummy); 6363 %} 6364 6365 // Avoid use of LA(Y) for general ALU operation. 6366 instruct subL_reg_reg_RISC(iRegL dst, iRegL src1, iRegL src2, flagsReg cr) %{ 6367 match(Set dst (SubL src1 src2)); 6368 effect(KILL cr); 6369 predicate(VM_Version::has_DistinctOpnds()); 6370 ins_cost(DEFAULT_COST); 6371 size(4); 6372 format %{ "SGRK $dst,$src1,$src2\t # int RISC ALU" %} 6373 opcode(SGRK_ZOPC); 6374 ins_encode(z_rrfform(dst, src1, src2)); 6375 ins_pipe(pipe_class_dummy); 6376 %} 6377 6378 instruct subL_reg_regI_CISC(iRegL dst, iRegI src, flagsReg cr) %{ 6379 match(Set dst (SubL dst (ConvI2L src))); 6380 effect(KILL cr); 6381 size(4); 6382 format %{ "SGFR $dst, $src\t # int CISC ALU" %} 6383 opcode(SGFR_ZOPC); 6384 ins_encode(z_rreform(dst, src)); 6385 ins_pipe(pipe_class_dummy); 6386 %} 6387 6388 instruct subL_Reg_memI(iRegL dst, memory src, flagsReg cr)%{ 6389 match(Set dst (SubL dst (ConvI2L (LoadI src)))); 6390 effect(KILL cr); 6391 ins_cost(MEMORY_REF_COST); 6392 size(Z_DISP3_SIZE); 6393 format %{ "SGF $dst, $src\t # long/int" %} 6394 opcode(SGF_ZOPC, SGF_ZOPC); 6395 ins_encode(z_form_rt_mem_opt(dst, src)); 6396 ins_pipe(pipe_class_dummy); 6397 %} 6398 6399 instruct subL_Reg_mem(iRegL dst, memory src, flagsReg cr)%{ 6400 match(Set dst (SubL dst (LoadL src))); 6401 effect(KILL cr); 6402 ins_cost(MEMORY_REF_COST); 6403 size(Z_DISP3_SIZE); 6404 format %{ "SG $dst, $src\t # long" %} 6405 opcode(SG_ZOPC, SG_ZOPC); 6406 ins_encode(z_form_rt_mem_opt(dst, src)); 6407 ins_pipe(pipe_class_dummy); 6408 %} 6409 6410 // Moved declaration of negL_reg_reg before encode nodes, where it is used. 6411 6412 // MUL 6413 6414 // Register Multiplication 6415 instruct mulI_reg_reg(iRegI dst, iRegI src) %{ 6416 match(Set dst (MulI dst src)); 6417 ins_cost(DEFAULT_COST); 6418 size(4); 6419 format %{ "MSR $dst, $src" %} 6420 opcode(MSR_ZOPC); 6421 ins_encode(z_rreform(dst, src)); 6422 ins_pipe(pipe_class_dummy); 6423 %} 6424 6425 // Immediate Multiplication 6426 instruct mulI_reg_imm16(iRegI dst, immI16 con) %{ 6427 match(Set dst (MulI dst con)); 6428 ins_cost(DEFAULT_COST); 6429 // TODO: s390 port size(FIXED_SIZE); 6430 format %{ "MHI $dst,$con" %} 6431 opcode(MHI_ZOPC); 6432 ins_encode(z_riform_signed(dst,con)); 6433 ins_pipe(pipe_class_dummy); 6434 %} 6435 6436 // Immediate (32bit) Multiplication 6437 instruct mulI_reg_imm32(iRegI dst, immI con) %{ 6438 match(Set dst (MulI dst con)); 6439 ins_cost(DEFAULT_COST); 6440 size(6); 6441 format %{ "MSFI $dst,$con" %} 6442 opcode(MSFI_ZOPC); 6443 ins_encode(z_rilform_signed(dst,con)); 6444 ins_pipe(pipe_class_dummy); 6445 %} 6446 6447 instruct mulI_Reg_mem(iRegI dst, memory src)%{ 6448 match(Set dst (MulI dst (LoadI src))); 6449 ins_cost(MEMORY_REF_COST); 6450 // TODO: s390 port size(VARIABLE_SIZE); 6451 format %{ "MS(Y) $dst, $src\t # int" %} 6452 opcode(MSY_ZOPC, MS_ZOPC); 6453 ins_encode(z_form_rt_mem_opt(dst, src)); 6454 ins_pipe(pipe_class_dummy); 6455 %} 6456 6457 // 6458 6459 instruct mulL_reg_regI(iRegL dst, iRegI src) %{ 6460 match(Set dst (MulL dst (ConvI2L src))); 6461 ins_cost(DEFAULT_COST); 6462 // TODO: s390 port size(FIXED_SIZE); 6463 format %{ "MSGFR $dst $src\t # long/int" %} 6464 opcode(MSGFR_ZOPC); 6465 ins_encode(z_rreform(dst, src)); 6466 ins_pipe(pipe_class_dummy); 6467 %} 6468 6469 instruct mulL_reg_reg(iRegL dst, iRegL src) %{ 6470 match(Set dst (MulL dst src)); 6471 ins_cost(DEFAULT_COST); 6472 size(4); 6473 format %{ "MSGR $dst $src\t # long" %} 6474 opcode(MSGR_ZOPC); 6475 ins_encode(z_rreform(dst, src)); 6476 ins_pipe(pipe_class_dummy); 6477 %} 6478 6479 // Immediate Multiplication 6480 instruct mulL_reg_imm16(iRegL dst, immL16 src) %{ 6481 match(Set dst (MulL dst src)); 6482 ins_cost(DEFAULT_COST); 6483 // TODO: s390 port size(FIXED_SIZE); 6484 format %{ "MGHI $dst,$src\t # long" %} 6485 opcode(MGHI_ZOPC); 6486 ins_encode(z_riform_signed(dst, src)); 6487 ins_pipe(pipe_class_dummy); 6488 %} 6489 6490 // Immediate (32bit) Multiplication 6491 instruct mulL_reg_imm32(iRegL dst, immL32 con) %{ 6492 match(Set dst (MulL dst con)); 6493 ins_cost(DEFAULT_COST); 6494 size(6); 6495 format %{ "MSGFI $dst,$con" %} 6496 opcode(MSGFI_ZOPC); 6497 ins_encode(z_rilform_signed(dst,con)); 6498 ins_pipe(pipe_class_dummy); 6499 %} 6500 6501 instruct mulL_Reg_memI(iRegL dst, memory src)%{ 6502 match(Set dst (MulL dst (ConvI2L (LoadI src)))); 6503 ins_cost(MEMORY_REF_COST); 6504 size(Z_DISP3_SIZE); 6505 format %{ "MSGF $dst, $src\t # long" %} 6506 opcode(MSGF_ZOPC, MSGF_ZOPC); 6507 ins_encode(z_form_rt_mem_opt(dst, src)); 6508 ins_pipe(pipe_class_dummy); 6509 %} 6510 6511 instruct mulL_Reg_mem(iRegL dst, memory src)%{ 6512 match(Set dst (MulL dst (LoadL src))); 6513 ins_cost(MEMORY_REF_COST); 6514 size(Z_DISP3_SIZE); 6515 format %{ "MSG $dst, $src\t # long" %} 6516 opcode(MSG_ZOPC, MSG_ZOPC); 6517 ins_encode(z_form_rt_mem_opt(dst, src)); 6518 ins_pipe(pipe_class_dummy); 6519 %} 6520 6521 instruct mulHiL_reg_reg(revenRegL Rdst, roddRegL Rsrc1, iRegL Rsrc2, iRegL Rtmp1, flagsReg cr)%{ 6522 match(Set Rdst (MulHiL Rsrc1 Rsrc2)); 6523 effect(TEMP_DEF Rdst, USE_KILL Rsrc1, TEMP Rtmp1, KILL cr); 6524 ins_cost(7*DEFAULT_COST); 6525 // TODO: s390 port size(VARIABLE_SIZE); 6526 format %{ "MulHiL $Rdst, $Rsrc1, $Rsrc2\t # Multiply High Long" %} 6527 ins_encode%{ 6528 Register dst = $Rdst$$Register; 6529 Register src1 = $Rsrc1$$Register; 6530 Register src2 = $Rsrc2$$Register; 6531 Register tmp1 = $Rtmp1$$Register; 6532 Register tmp2 = $Rdst$$Register; 6533 // z/Architecture has only unsigned multiply (64 * 64 -> 128). 6534 // implementing mulhs(a,b) = mulhu(a,b) – (a & (b>>63)) – (b & (a>>63)) 6535 __ z_srag(tmp2, src1, 63); // a>>63 6536 __ z_srag(tmp1, src2, 63); // b>>63 6537 __ z_ngr(tmp2, src2); // b & (a>>63) 6538 __ z_ngr(tmp1, src1); // a & (b>>63) 6539 __ z_agr(tmp1, tmp2); // ((a & (b>>63)) + (b & (a>>63))) 6540 __ z_mlgr(dst, src2); // tricky: 128-bit product is written to even/odd pair (dst,src1), 6541 // multiplicand is taken from oddReg (src1), multiplier in src2. 6542 __ z_sgr(dst, tmp1); 6543 %} 6544 ins_pipe(pipe_class_dummy); 6545 %} 6546 6547 // DIV 6548 6549 // Integer DIVMOD with Register, both quotient and mod results 6550 instruct divModI_reg_divmod(roddRegI dst1src1, revenRegI dst2, noOdd_iRegI src2, flagsReg cr) %{ 6551 match(DivModI dst1src1 src2); 6552 effect(KILL cr); 6553 ins_cost(2 * DEFAULT_COST + BRANCH_COST); 6554 size((VM_Version::has_CompareBranch() ? 24 : 26)); 6555 format %{ "DIVMODI ($dst1src1, $dst2) $src2" %} 6556 ins_encode %{ 6557 Register d1s1 = $dst1src1$$Register; 6558 Register d2 = $dst2$$Register; 6559 Register s2 = $src2$$Register; 6560 6561 assert_different_registers(d1s1, s2); 6562 6563 Label do_div, done_div; 6564 if (VM_Version::has_CompareBranch()) { 6565 __ z_cij(s2, -1, Assembler::bcondNotEqual, do_div); 6566 } else { 6567 __ z_chi(s2, -1); 6568 __ z_brne(do_div); 6569 } 6570 __ z_lcr(d1s1, d1s1); 6571 __ clear_reg(d2, false, false); 6572 __ z_bru(done_div); 6573 __ bind(do_div); 6574 __ z_lgfr(d1s1, d1s1); 6575 __ z_dsgfr(d2, s2); 6576 __ bind(done_div); 6577 %} 6578 ins_pipe(pipe_class_dummy); 6579 %} 6580 6581 6582 // Register Division 6583 instruct divI_reg_reg(roddRegI dst, iRegI src1, noOdd_iRegI src2, revenRegI tmp, flagsReg cr) %{ 6584 match(Set dst (DivI src1 src2)); 6585 effect(KILL tmp, KILL cr); 6586 ins_cost(2 * DEFAULT_COST + BRANCH_COST); 6587 size((VM_Version::has_CompareBranch() ? 20 : 22)); 6588 format %{ "DIV_checked $dst, $src1,$src2\t # treats special case 0x80../-1" %} 6589 ins_encode %{ 6590 Register a = $src1$$Register; 6591 Register b = $src2$$Register; 6592 Register t = $dst$$Register; 6593 6594 assert_different_registers(t, b); 6595 6596 Label do_div, done_div; 6597 if (VM_Version::has_CompareBranch()) { 6598 __ z_cij(b, -1, Assembler::bcondNotEqual, do_div); 6599 } else { 6600 __ z_chi(b, -1); 6601 __ z_brne(do_div); 6602 } 6603 __ z_lcr(t, a); 6604 __ z_bru(done_div); 6605 __ bind(do_div); 6606 __ z_lgfr(t, a); 6607 __ z_dsgfr(t->predecessor()/* t is odd part of a register pair. */, b); 6608 __ bind(done_div); 6609 %} 6610 ins_pipe(pipe_class_dummy); 6611 %} 6612 6613 // Immediate Division 6614 instruct divI_reg_imm16(roddRegI dst, iRegI src1, immI16 src2, revenRegI tmp, flagsReg cr) %{ 6615 match(Set dst (DivI src1 src2)); 6616 effect(KILL tmp, KILL cr); // R0 is killed, too. 6617 ins_cost(2 * DEFAULT_COST); 6618 // TODO: s390 port size(VARIABLE_SIZE); 6619 format %{ "DIV_const $dst,$src1,$src2" %} 6620 ins_encode %{ 6621 // No sign extension of Rdividend needed here. 6622 if ($src2$$constant != -1) { 6623 __ z_lghi(Z_R0_scratch, $src2$$constant); 6624 __ z_lgfr($dst$$Register, $src1$$Register); 6625 __ z_dsgfr($dst$$Register->predecessor()/* Dst is odd part of a register pair. */, Z_R0_scratch); 6626 } else { 6627 __ z_lcr($dst$$Register, $src1$$Register); 6628 } 6629 %} 6630 ins_pipe(pipe_class_dummy); 6631 %} 6632 6633 // Long DIVMOD with Register, both quotient and mod results 6634 instruct divModL_reg_divmod(roddRegL dst1src1, revenRegL dst2, iRegL src2, flagsReg cr) %{ 6635 match(DivModL dst1src1 src2); 6636 effect(KILL cr); 6637 ins_cost(2 * DEFAULT_COST + BRANCH_COST); 6638 size((VM_Version::has_CompareBranch() ? 22 : 24)); 6639 format %{ "DIVMODL ($dst1src1, $dst2) $src2" %} 6640 ins_encode %{ 6641 Register d1s1 = $dst1src1$$Register; 6642 Register d2 = $dst2$$Register; 6643 Register s2 = $src2$$Register; 6644 6645 Label do_div, done_div; 6646 if (VM_Version::has_CompareBranch()) { 6647 __ z_cgij(s2, -1, Assembler::bcondNotEqual, do_div); 6648 } else { 6649 __ z_cghi(s2, -1); 6650 __ z_brne(do_div); 6651 } 6652 __ z_lcgr(d1s1, d1s1); 6653 // indicate unused result 6654 (void) __ clear_reg(d2, true, false); 6655 __ z_bru(done_div); 6656 __ bind(do_div); 6657 __ z_dsgr(d2, s2); 6658 __ bind(done_div); 6659 %} 6660 ins_pipe(pipe_class_dummy); 6661 %} 6662 6663 // Register Long Division 6664 instruct divL_reg_reg(roddRegL dst, iRegL src, revenRegL tmp, flagsReg cr) %{ 6665 match(Set dst (DivL dst src)); 6666 effect(KILL tmp, KILL cr); 6667 ins_cost(2 * DEFAULT_COST + BRANCH_COST); 6668 size((VM_Version::has_CompareBranch() ? 18 : 20)); 6669 format %{ "DIVG_checked $dst, $src\t # long, treats special case 0x80../-1" %} 6670 ins_encode %{ 6671 Register b = $src$$Register; 6672 Register t = $dst$$Register; 6673 6674 Label done_div; 6675 __ z_lcgr(t, t); // Does no harm. divisor is in other register. 6676 if (VM_Version::has_CompareBranch()) { 6677 __ z_cgij(b, -1, Assembler::bcondEqual, done_div); 6678 } else { 6679 __ z_cghi(b, -1); 6680 __ z_bre(done_div); 6681 } 6682 __ z_lcgr(t, t); // Restore sign. 6683 __ z_dsgr(t->predecessor()/* t is odd part of a register pair. */, b); 6684 __ bind(done_div); 6685 %} 6686 ins_pipe(pipe_class_dummy); 6687 %} 6688 6689 // Immediate Long Division 6690 instruct divL_reg_imm16(roddRegL dst, iRegL src1, immL16 src2, revenRegL tmp, flagsReg cr) %{ 6691 match(Set dst (DivL src1 src2)); 6692 effect(KILL tmp, KILL cr); // R0 is killed, too. 6693 ins_cost(2 * DEFAULT_COST); 6694 // TODO: s390 port size(VARIABLE_SIZE); 6695 format %{ "DIVG_const $dst,$src1,$src2\t # long" %} 6696 ins_encode %{ 6697 if ($src2$$constant != -1) { 6698 __ z_lghi(Z_R0_scratch, $src2$$constant); 6699 __ lgr_if_needed($dst$$Register, $src1$$Register); 6700 __ z_dsgr($dst$$Register->predecessor()/* Dst is odd part of a register pair. */, Z_R0_scratch); 6701 } else { 6702 __ z_lcgr($dst$$Register, $src1$$Register); 6703 } 6704 %} 6705 ins_pipe(pipe_class_dummy); 6706 %} 6707 6708 // REM 6709 6710 // Integer Remainder 6711 // Register Remainder 6712 instruct modI_reg_reg(revenRegI dst, iRegI src1, noOdd_iRegI src2, roddRegI tmp, flagsReg cr) %{ 6713 match(Set dst (ModI src1 src2)); 6714 effect(KILL tmp, KILL cr); 6715 ins_cost(2 * DEFAULT_COST + BRANCH_COST); 6716 // TODO: s390 port size(VARIABLE_SIZE); 6717 format %{ "MOD_checked $dst,$src1,$src2" %} 6718 ins_encode %{ 6719 Register a = $src1$$Register; 6720 Register b = $src2$$Register; 6721 Register t = $dst$$Register; 6722 assert_different_registers(t->successor(), b); 6723 6724 Label do_div, done_div; 6725 6726 if ((t->encoding() != b->encoding()) && (t->encoding() != a->encoding())) { 6727 (void) __ clear_reg(t, true, false); // Does no harm. Operands are in other regs. 6728 if (VM_Version::has_CompareBranch()) { 6729 __ z_cij(b, -1, Assembler::bcondEqual, done_div); 6730 } else { 6731 __ z_chi(b, -1); 6732 __ z_bre(done_div); 6733 } 6734 __ z_lgfr(t->successor(), a); 6735 __ z_dsgfr(t/* t is even part of a register pair. */, b); 6736 } else { 6737 if (VM_Version::has_CompareBranch()) { 6738 __ z_cij(b, -1, Assembler::bcondNotEqual, do_div); 6739 } else { 6740 __ z_chi(b, -1); 6741 __ z_brne(do_div); 6742 } 6743 __ clear_reg(t, true, false); 6744 __ z_bru(done_div); 6745 __ bind(do_div); 6746 __ z_lgfr(t->successor(), a); 6747 __ z_dsgfr(t/* t is even part of a register pair. */, b); 6748 } 6749 __ bind(done_div); 6750 %} 6751 ins_pipe(pipe_class_dummy); 6752 %} 6753 6754 // Immediate Remainder 6755 instruct modI_reg_imm16(revenRegI dst, iRegI src1, immI16 src2, roddRegI tmp, flagsReg cr) %{ 6756 match(Set dst (ModI src1 src2)); 6757 effect(KILL tmp, KILL cr); // R0 is killed, too. 6758 ins_cost(3 * DEFAULT_COST); 6759 // TODO: s390 port size(VARIABLE_SIZE); 6760 format %{ "MOD_const $dst,src1,$src2" %} 6761 ins_encode %{ 6762 assert_different_registers($dst$$Register, $src1$$Register); 6763 assert_different_registers($dst$$Register->successor(), $src1$$Register); 6764 int divisor = $src2$$constant; 6765 6766 if (divisor != -1) { 6767 __ z_lghi(Z_R0_scratch, divisor); 6768 __ z_lgfr($dst$$Register->successor(), $src1$$Register); 6769 __ z_dsgfr($dst$$Register/* Dst is even part of a register pair. */, Z_R0_scratch); // Instruction kills tmp. 6770 } else { 6771 __ clear_reg($dst$$Register, true, false); 6772 } 6773 %} 6774 ins_pipe(pipe_class_dummy); 6775 %} 6776 6777 // Register Long Remainder 6778 instruct modL_reg_reg(revenRegL dst, roddRegL src1, iRegL src2, flagsReg cr) %{ 6779 match(Set dst (ModL src1 src2)); 6780 effect(KILL src1, KILL cr); // R0 is killed, too. 6781 ins_cost(2 * DEFAULT_COST + BRANCH_COST); 6782 // TODO: s390 port size(VARIABLE_SIZE); 6783 format %{ "MODG_checked $dst,$src1,$src2" %} 6784 ins_encode %{ 6785 Register a = $src1$$Register; 6786 Register b = $src2$$Register; 6787 Register t = $dst$$Register; 6788 assert(t->successor() == a, "(t,a) is an even-odd pair" ); 6789 6790 Label do_div, done_div; 6791 if (t->encoding() != b->encoding()) { 6792 (void) __ clear_reg(t, true, false); // Does no harm. Dividend is in successor. 6793 if (VM_Version::has_CompareBranch()) { 6794 __ z_cgij(b, -1, Assembler::bcondEqual, done_div); 6795 } else { 6796 __ z_cghi(b, -1); 6797 __ z_bre(done_div); 6798 } 6799 __ z_dsgr(t, b); 6800 } else { 6801 if (VM_Version::has_CompareBranch()) { 6802 __ z_cgij(b, -1, Assembler::bcondNotEqual, do_div); 6803 } else { 6804 __ z_cghi(b, -1); 6805 __ z_brne(do_div); 6806 } 6807 __ clear_reg(t, true, false); 6808 __ z_bru(done_div); 6809 __ bind(do_div); 6810 __ z_dsgr(t, b); 6811 } 6812 __ bind(done_div); 6813 %} 6814 ins_pipe(pipe_class_dummy); 6815 %} 6816 6817 // Register Long Remainder 6818 instruct modL_reg_imm16(revenRegL dst, iRegL src1, immL16 src2, roddRegL tmp, flagsReg cr) %{ 6819 match(Set dst (ModL src1 src2)); 6820 effect(KILL tmp, KILL cr); // R0 is killed, too. 6821 ins_cost(3 * DEFAULT_COST); 6822 // TODO: s390 port size(VARIABLE_SIZE); 6823 format %{ "MODG_const $dst,src1,$src2\t # long" %} 6824 ins_encode %{ 6825 int divisor = $src2$$constant; 6826 if (divisor != -1) { 6827 __ z_lghi(Z_R0_scratch, divisor); 6828 __ z_lgr($dst$$Register->successor(), $src1$$Register); 6829 __ z_dsgr($dst$$Register /* Dst is even part of a register pair. */, Z_R0_scratch); // Instruction kills tmp. 6830 } else { 6831 __ clear_reg($dst$$Register, true, false); 6832 } 6833 %} 6834 ins_pipe(pipe_class_dummy); 6835 %} 6836 6837 // SHIFT 6838 6839 // Shift left logical 6840 6841 // Register Shift Left variable 6842 instruct sllI_reg_reg(iRegI dst, iRegI src, iRegI nbits, flagsReg cr) %{ 6843 match(Set dst (LShiftI src nbits)); 6844 effect(KILL cr); // R1 is killed, too. 6845 ins_cost(3 * DEFAULT_COST); 6846 size(14); 6847 format %{ "SLL $dst,$src,[$nbits] & 31\t # use RISC-like SLLG also for int" %} 6848 ins_encode %{ 6849 __ z_lgr(Z_R1_scratch, $nbits$$Register); 6850 __ z_nill(Z_R1_scratch, BitsPerJavaInteger-1); 6851 __ z_sllg($dst$$Register, $src$$Register, 0, Z_R1_scratch); 6852 %} 6853 ins_pipe(pipe_class_dummy); 6854 %} 6855 6856 // Register Shift Left Immediate 6857 // Constant shift count is masked in ideal graph already. 6858 instruct sllI_reg_imm(iRegI dst, iRegI src, immI nbits) %{ 6859 match(Set dst (LShiftI src nbits)); 6860 size(6); 6861 format %{ "SLL $dst,$src,$nbits\t # use RISC-like SLLG also for int" %} 6862 ins_encode %{ 6863 int Nbit = $nbits$$constant; 6864 assert((Nbit & (BitsPerJavaInteger - 1)) == Nbit, "Check shift mask in ideal graph"); 6865 __ z_sllg($dst$$Register, $src$$Register, Nbit & (BitsPerJavaInteger - 1), Z_R0); 6866 %} 6867 ins_pipe(pipe_class_dummy); 6868 %} 6869 6870 // Register Shift Left Immediate by 1bit 6871 instruct sllI_reg_imm_1(iRegI dst, iRegI src, immI_1 nbits) %{ 6872 match(Set dst (LShiftI src nbits)); 6873 predicate(PreferLAoverADD); 6874 ins_cost(DEFAULT_COST_LOW); 6875 size(4); 6876 format %{ "LA $dst,#0($src,$src)\t # SLL by 1 (int)" %} 6877 ins_encode %{ __ z_la($dst$$Register, 0, $src$$Register, $src$$Register); %} 6878 ins_pipe(pipe_class_dummy); 6879 %} 6880 6881 // Register Shift Left Long 6882 instruct sllL_reg_reg(iRegL dst, iRegL src1, iRegI nbits) %{ 6883 match(Set dst (LShiftL src1 nbits)); 6884 size(6); 6885 format %{ "SLLG $dst,$src1,[$nbits]" %} 6886 opcode(SLLG_ZOPC); 6887 ins_encode(z_rsyform_reg_reg(dst, src1, nbits)); 6888 ins_pipe(pipe_class_dummy); 6889 %} 6890 6891 // Register Shift Left Long Immediate 6892 instruct sllL_reg_imm(iRegL dst, iRegL src1, immI nbits) %{ 6893 match(Set dst (LShiftL src1 nbits)); 6894 size(6); 6895 format %{ "SLLG $dst,$src1,$nbits" %} 6896 opcode(SLLG_ZOPC); 6897 ins_encode(z_rsyform_const(dst, src1, nbits)); 6898 ins_pipe(pipe_class_dummy); 6899 %} 6900 6901 // Register Shift Left Long Immediate by 1bit 6902 instruct sllL_reg_imm_1(iRegL dst, iRegL src1, immI_1 nbits) %{ 6903 match(Set dst (LShiftL src1 nbits)); 6904 predicate(PreferLAoverADD); 6905 ins_cost(DEFAULT_COST_LOW); 6906 size(4); 6907 format %{ "LA $dst,#0($src1,$src1)\t # SLLG by 1 (long)" %} 6908 ins_encode %{ __ z_la($dst$$Register, 0, $src1$$Register, $src1$$Register); %} 6909 ins_pipe(pipe_class_dummy); 6910 %} 6911 6912 // Shift right arithmetic 6913 6914 // Register Arithmetic Shift Right 6915 instruct sraI_reg_reg(iRegI dst, iRegI src, flagsReg cr) %{ 6916 match(Set dst (RShiftI dst src)); 6917 effect(KILL cr); // R1 is killed, too. 6918 ins_cost(3 * DEFAULT_COST); 6919 size(12); 6920 format %{ "SRA $dst,[$src] & 31" %} 6921 ins_encode %{ 6922 __ z_lgr(Z_R1_scratch, $src$$Register); 6923 __ z_nill(Z_R1_scratch, BitsPerJavaInteger-1); 6924 __ z_sra($dst$$Register, 0, Z_R1_scratch); 6925 %} 6926 ins_pipe(pipe_class_dummy); 6927 %} 6928 6929 // Register Arithmetic Shift Right Immediate 6930 // Constant shift count is masked in ideal graph already. 6931 instruct sraI_reg_imm(iRegI dst, immI src, flagsReg cr) %{ 6932 match(Set dst (RShiftI dst src)); 6933 effect(KILL cr); 6934 size(4); 6935 format %{ "SRA $dst,$src" %} 6936 ins_encode %{ 6937 int Nbit = $src$$constant; 6938 assert((Nbit & (BitsPerJavaInteger - 1)) == Nbit, "Check shift mask in ideal graph"); 6939 __ z_sra($dst$$Register, Nbit & (BitsPerJavaInteger - 1), Z_R0); 6940 %} 6941 ins_pipe(pipe_class_dummy); 6942 %} 6943 6944 // Register Arithmetic Shift Right Long 6945 instruct sraL_reg_reg(iRegL dst, iRegL src1, iRegI src2, flagsReg cr) %{ 6946 match(Set dst (RShiftL src1 src2)); 6947 effect(KILL cr); 6948 size(6); 6949 format %{ "SRAG $dst,$src1,[$src2]" %} 6950 opcode(SRAG_ZOPC); 6951 ins_encode(z_rsyform_reg_reg(dst, src1, src2)); 6952 ins_pipe(pipe_class_dummy); 6953 %} 6954 6955 // Register Arithmetic Shift Right Long Immediate 6956 instruct sraL_reg_imm(iRegL dst, iRegL src1, immI src2, flagsReg cr) %{ 6957 match(Set dst (RShiftL src1 src2)); 6958 effect(KILL cr); 6959 size(6); 6960 format %{ "SRAG $dst,$src1,$src2" %} 6961 opcode(SRAG_ZOPC); 6962 ins_encode(z_rsyform_const(dst, src1, src2)); 6963 ins_pipe(pipe_class_dummy); 6964 %} 6965 6966 // Shift right logical 6967 6968 // Register Shift Right 6969 instruct srlI_reg_reg(iRegI dst, iRegI src, flagsReg cr) %{ 6970 match(Set dst (URShiftI dst src)); 6971 effect(KILL cr); // R1 is killed, too. 6972 ins_cost(3 * DEFAULT_COST); 6973 size(12); 6974 format %{ "SRL $dst,[$src] & 31" %} 6975 ins_encode %{ 6976 __ z_lgr(Z_R1_scratch, $src$$Register); 6977 __ z_nill(Z_R1_scratch, BitsPerJavaInteger-1); 6978 __ z_srl($dst$$Register, 0, Z_R1_scratch); 6979 %} 6980 ins_pipe(pipe_class_dummy); 6981 %} 6982 6983 // Register Shift Right Immediate 6984 // Constant shift count is masked in ideal graph already. 6985 instruct srlI_reg_imm(iRegI dst, immI src) %{ 6986 match(Set dst (URShiftI dst src)); 6987 size(4); 6988 format %{ "SRL $dst,$src" %} 6989 ins_encode %{ 6990 int Nbit = $src$$constant; 6991 assert((Nbit & (BitsPerJavaInteger - 1)) == Nbit, "Check shift mask in ideal graph"); 6992 __ z_srl($dst$$Register, Nbit & (BitsPerJavaInteger - 1), Z_R0); 6993 %} 6994 ins_pipe(pipe_class_dummy); 6995 %} 6996 6997 // Register Shift Right Long 6998 instruct srlL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{ 6999 match(Set dst (URShiftL src1 src2)); 7000 size(6); 7001 format %{ "SRLG $dst,$src1,[$src2]" %} 7002 opcode(SRLG_ZOPC); 7003 ins_encode(z_rsyform_reg_reg(dst, src1, src2)); 7004 ins_pipe(pipe_class_dummy); 7005 %} 7006 7007 // Register Shift Right Long Immediate 7008 instruct srlL_reg_imm(iRegL dst, iRegL src1, immI src2) %{ 7009 match(Set dst (URShiftL src1 src2)); 7010 size(6); 7011 format %{ "SRLG $dst,$src1,$src2" %} 7012 opcode(SRLG_ZOPC); 7013 ins_encode(z_rsyform_const(dst, src1, src2)); 7014 ins_pipe(pipe_class_dummy); 7015 %} 7016 7017 // Register Shift Right Immediate with a CastP2X 7018 instruct srlP_reg_imm(iRegL dst, iRegP_N2P src1, immI src2) %{ 7019 match(Set dst (URShiftL (CastP2X src1) src2)); 7020 size(6); 7021 format %{ "SRLG $dst,$src1,$src2\t # Cast ptr $src1 to long and shift" %} 7022 opcode(SRLG_ZOPC); 7023 ins_encode(z_rsyform_const(dst, src1, src2)); 7024 ins_pipe(pipe_class_dummy); 7025 %} 7026 7027 //----------Rotate Instructions------------------------------------------------ 7028 7029 // Rotate left 32bit. 7030 instruct rotlI_reg_immI8(iRegI dst, iRegI src, immI8 lshift, immI8 rshift) %{ 7031 match(Set dst (OrI (LShiftI src lshift) (URShiftI src rshift))); 7032 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f)); 7033 size(6); 7034 format %{ "RLL $dst,$src,$lshift\t # ROTL32" %} 7035 opcode(RLL_ZOPC); 7036 ins_encode(z_rsyform_const(dst, src, lshift)); 7037 ins_pipe(pipe_class_dummy); 7038 %} 7039 7040 // Rotate left 64bit. 7041 instruct rotlL_reg_immI8(iRegL dst, iRegL src, immI8 lshift, immI8 rshift) %{ 7042 match(Set dst (OrL (LShiftL src lshift) (URShiftL src rshift))); 7043 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f)); 7044 size(6); 7045 format %{ "RLLG $dst,$src,$lshift\t # ROTL64" %} 7046 opcode(RLLG_ZOPC); 7047 ins_encode(z_rsyform_const(dst, src, lshift)); 7048 ins_pipe(pipe_class_dummy); 7049 %} 7050 7051 // Rotate right 32bit. 7052 instruct rotrI_reg_immI8(iRegI dst, iRegI src, immI8 rshift, immI8 lshift) %{ 7053 match(Set dst (OrI (URShiftI src rshift) (LShiftI src lshift))); 7054 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f)); 7055 // TODO: s390 port size(FIXED_SIZE); 7056 format %{ "RLL $dst,$src,$rshift\t # ROTR32" %} 7057 opcode(RLL_ZOPC); 7058 ins_encode(z_rsyform_const(dst, src, rshift)); 7059 ins_pipe(pipe_class_dummy); 7060 %} 7061 7062 // Rotate right 64bit. 7063 instruct rotrL_reg_immI8(iRegL dst, iRegL src, immI8 rshift, immI8 lshift) %{ 7064 match(Set dst (OrL (URShiftL src rshift) (LShiftL src lshift))); 7065 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f)); 7066 // TODO: s390 port size(FIXED_SIZE); 7067 format %{ "RLLG $dst,$src,$rshift\t # ROTR64" %} 7068 opcode(RLLG_ZOPC); 7069 ins_encode(z_rsyform_const(dst, src, rshift)); 7070 ins_pipe(pipe_class_dummy); 7071 %} 7072 7073 7074 //----------Overflow Math Instructions----------------------------------------- 7075 7076 instruct overflowAddI_reg_reg(flagsReg cr, iRegI op1, iRegI op2) %{ 7077 match(Set cr (OverflowAddI op1 op2)); 7078 effect(DEF cr, USE op1, USE op2); 7079 // TODO: s390 port size(FIXED_SIZE); 7080 format %{ "AR $op1,$op2\t # overflow check int" %} 7081 ins_encode %{ 7082 __ z_lr(Z_R0_scratch, $op1$$Register); 7083 __ z_ar(Z_R0_scratch, $op2$$Register); 7084 %} 7085 ins_pipe(pipe_class_dummy); 7086 %} 7087 7088 instruct overflowAddI_reg_imm(flagsReg cr, iRegI op1, immI op2) %{ 7089 match(Set cr (OverflowAddI op1 op2)); 7090 effect(DEF cr, USE op1, USE op2); 7091 // TODO: s390 port size(VARIABLE_SIZE); 7092 format %{ "AR $op1,$op2\t # overflow check int" %} 7093 ins_encode %{ 7094 __ load_const_optimized(Z_R0_scratch, $op2$$constant); 7095 __ z_ar(Z_R0_scratch, $op1$$Register); 7096 %} 7097 ins_pipe(pipe_class_dummy); 7098 %} 7099 7100 instruct overflowAddL_reg_reg(flagsReg cr, iRegL op1, iRegL op2) %{ 7101 match(Set cr (OverflowAddL op1 op2)); 7102 effect(DEF cr, USE op1, USE op2); 7103 // TODO: s390 port size(FIXED_SIZE); 7104 format %{ "AGR $op1,$op2\t # overflow check long" %} 7105 ins_encode %{ 7106 __ z_lgr(Z_R0_scratch, $op1$$Register); 7107 __ z_agr(Z_R0_scratch, $op2$$Register); 7108 %} 7109 ins_pipe(pipe_class_dummy); 7110 %} 7111 7112 instruct overflowAddL_reg_imm(flagsReg cr, iRegL op1, immL op2) %{ 7113 match(Set cr (OverflowAddL op1 op2)); 7114 effect(DEF cr, USE op1, USE op2); 7115 // TODO: s390 port size(VARIABLE_SIZE); 7116 format %{ "AGR $op1,$op2\t # overflow check long" %} 7117 ins_encode %{ 7118 __ load_const_optimized(Z_R0_scratch, $op2$$constant); 7119 __ z_agr(Z_R0_scratch, $op1$$Register); 7120 %} 7121 ins_pipe(pipe_class_dummy); 7122 %} 7123 7124 instruct overflowSubI_reg_reg(flagsReg cr, iRegI op1, iRegI op2) %{ 7125 match(Set cr (OverflowSubI op1 op2)); 7126 effect(DEF cr, USE op1, USE op2); 7127 // TODO: s390 port size(FIXED_SIZE); 7128 format %{ "SR $op1,$op2\t # overflow check int" %} 7129 ins_encode %{ 7130 __ z_lr(Z_R0_scratch, $op1$$Register); 7131 __ z_sr(Z_R0_scratch, $op2$$Register); 7132 %} 7133 ins_pipe(pipe_class_dummy); 7134 %} 7135 7136 instruct overflowSubI_reg_imm(flagsReg cr, iRegI op1, immI op2) %{ 7137 match(Set cr (OverflowSubI op1 op2)); 7138 effect(DEF cr, USE op1, USE op2); 7139 // TODO: s390 port size(VARIABLE_SIZE); 7140 format %{ "SR $op1,$op2\t # overflow check int" %} 7141 ins_encode %{ 7142 __ load_const_optimized(Z_R1_scratch, $op2$$constant); 7143 __ z_lr(Z_R0_scratch, $op1$$Register); 7144 __ z_sr(Z_R0_scratch, Z_R1_scratch); 7145 %} 7146 ins_pipe(pipe_class_dummy); 7147 %} 7148 7149 instruct overflowSubL_reg_reg(flagsReg cr, iRegL op1, iRegL op2) %{ 7150 match(Set cr (OverflowSubL op1 op2)); 7151 effect(DEF cr, USE op1, USE op2); 7152 // TODO: s390 port size(FIXED_SIZE); 7153 format %{ "SGR $op1,$op2\t # overflow check long" %} 7154 ins_encode %{ 7155 __ z_lgr(Z_R0_scratch, $op1$$Register); 7156 __ z_sgr(Z_R0_scratch, $op2$$Register); 7157 %} 7158 ins_pipe(pipe_class_dummy); 7159 %} 7160 7161 instruct overflowSubL_reg_imm(flagsReg cr, iRegL op1, immL op2) %{ 7162 match(Set cr (OverflowSubL op1 op2)); 7163 effect(DEF cr, USE op1, USE op2); 7164 // TODO: s390 port size(VARIABLE_SIZE); 7165 format %{ "SGR $op1,$op2\t # overflow check long" %} 7166 ins_encode %{ 7167 __ load_const_optimized(Z_R1_scratch, $op2$$constant); 7168 __ z_lgr(Z_R0_scratch, $op1$$Register); 7169 __ z_sgr(Z_R0_scratch, Z_R1_scratch); 7170 %} 7171 ins_pipe(pipe_class_dummy); 7172 %} 7173 7174 instruct overflowNegI_rReg(flagsReg cr, immI_0 zero, iRegI op2) %{ 7175 match(Set cr (OverflowSubI zero op2)); 7176 effect(DEF cr, USE op2); 7177 format %{ "NEG $op2\t # overflow check int" %} 7178 ins_encode %{ 7179 __ clear_reg(Z_R0_scratch, false, false); 7180 __ z_sr(Z_R0_scratch, $op2$$Register); 7181 %} 7182 ins_pipe(pipe_class_dummy); 7183 %} 7184 7185 instruct overflowNegL_rReg(flagsReg cr, immL_0 zero, iRegL op2) %{ 7186 match(Set cr (OverflowSubL zero op2)); 7187 effect(DEF cr, USE op2); 7188 format %{ "NEGG $op2\t # overflow check long" %} 7189 ins_encode %{ 7190 __ clear_reg(Z_R0_scratch, true, false); 7191 __ z_sgr(Z_R0_scratch, $op2$$Register); 7192 %} 7193 ins_pipe(pipe_class_dummy); 7194 %} 7195 7196 // No intrinsics for multiplication, since there is no easy way 7197 // to check for overflow. 7198 7199 7200 //----------Floating Point Arithmetic Instructions----------------------------- 7201 7202 // ADD 7203 7204 // Add float single precision 7205 instruct addF_reg_reg(regF dst, regF src, flagsReg cr) %{ 7206 match(Set dst (AddF dst src)); 7207 effect(KILL cr); 7208 ins_cost(ALU_REG_COST); 7209 size(4); 7210 format %{ "AEBR $dst,$src" %} 7211 opcode(AEBR_ZOPC); 7212 ins_encode(z_rreform(dst, src)); 7213 ins_pipe(pipe_class_dummy); 7214 %} 7215 7216 instruct addF_reg_mem(regF dst, memoryRX src, flagsReg cr)%{ 7217 match(Set dst (AddF dst (LoadF src))); 7218 effect(KILL cr); 7219 ins_cost(ALU_MEMORY_COST); 7220 size(6); 7221 format %{ "AEB $dst,$src\t # floatMemory" %} 7222 opcode(AEB_ZOPC); 7223 ins_encode(z_form_rt_memFP(dst, src)); 7224 ins_pipe(pipe_class_dummy); 7225 %} 7226 7227 // Add float double precision 7228 instruct addD_reg_reg(regD dst, regD src, flagsReg cr) %{ 7229 match(Set dst (AddD dst src)); 7230 effect(KILL cr); 7231 ins_cost(ALU_REG_COST); 7232 size(4); 7233 format %{ "ADBR $dst,$src" %} 7234 opcode(ADBR_ZOPC); 7235 ins_encode(z_rreform(dst, src)); 7236 ins_pipe(pipe_class_dummy); 7237 %} 7238 7239 instruct addD_reg_mem(regD dst, memoryRX src, flagsReg cr)%{ 7240 match(Set dst (AddD dst (LoadD src))); 7241 effect(KILL cr); 7242 ins_cost(ALU_MEMORY_COST); 7243 size(6); 7244 format %{ "ADB $dst,$src\t # doubleMemory" %} 7245 opcode(ADB_ZOPC); 7246 ins_encode(z_form_rt_memFP(dst, src)); 7247 ins_pipe(pipe_class_dummy); 7248 %} 7249 7250 // SUB 7251 7252 // Sub float single precision 7253 instruct subF_reg_reg(regF dst, regF src, flagsReg cr) %{ 7254 match(Set dst (SubF dst src)); 7255 effect(KILL cr); 7256 ins_cost(ALU_REG_COST); 7257 size(4); 7258 format %{ "SEBR $dst,$src" %} 7259 opcode(SEBR_ZOPC); 7260 ins_encode(z_rreform(dst, src)); 7261 ins_pipe(pipe_class_dummy); 7262 %} 7263 7264 instruct subF_reg_mem(regF dst, memoryRX src, flagsReg cr)%{ 7265 match(Set dst (SubF dst (LoadF src))); 7266 effect(KILL cr); 7267 ins_cost(ALU_MEMORY_COST); 7268 size(6); 7269 format %{ "SEB $dst,$src\t # floatMemory" %} 7270 opcode(SEB_ZOPC); 7271 ins_encode(z_form_rt_memFP(dst, src)); 7272 ins_pipe(pipe_class_dummy); 7273 %} 7274 7275 // Sub float double precision 7276 instruct subD_reg_reg(regD dst, regD src, flagsReg cr) %{ 7277 match(Set dst (SubD dst src)); 7278 effect(KILL cr); 7279 ins_cost(ALU_REG_COST); 7280 size(4); 7281 format %{ "SDBR $dst,$src" %} 7282 opcode(SDBR_ZOPC); 7283 ins_encode(z_rreform(dst, src)); 7284 ins_pipe(pipe_class_dummy); 7285 %} 7286 7287 instruct subD_reg_mem(regD dst, memoryRX src, flagsReg cr)%{ 7288 match(Set dst (SubD dst (LoadD src))); 7289 effect(KILL cr); 7290 ins_cost(ALU_MEMORY_COST); 7291 size(6); 7292 format %{ "SDB $dst,$src\t # doubleMemory" %} 7293 opcode(SDB_ZOPC); 7294 ins_encode(z_form_rt_memFP(dst, src)); 7295 ins_pipe(pipe_class_dummy); 7296 %} 7297 7298 // MUL 7299 7300 // Mul float single precision 7301 instruct mulF_reg_reg(regF dst, regF src) %{ 7302 match(Set dst (MulF dst src)); 7303 // CC unchanged by MUL. 7304 ins_cost(ALU_REG_COST); 7305 size(4); 7306 format %{ "MEEBR $dst,$src" %} 7307 opcode(MEEBR_ZOPC); 7308 ins_encode(z_rreform(dst, src)); 7309 ins_pipe(pipe_class_dummy); 7310 %} 7311 7312 instruct mulF_reg_mem(regF dst, memoryRX src)%{ 7313 match(Set dst (MulF dst (LoadF src))); 7314 // CC unchanged by MUL. 7315 ins_cost(ALU_MEMORY_COST); 7316 size(6); 7317 format %{ "MEEB $dst,$src\t # floatMemory" %} 7318 opcode(MEEB_ZOPC); 7319 ins_encode(z_form_rt_memFP(dst, src)); 7320 ins_pipe(pipe_class_dummy); 7321 %} 7322 7323 // Mul float double precision 7324 instruct mulD_reg_reg(regD dst, regD src) %{ 7325 match(Set dst (MulD dst src)); 7326 // CC unchanged by MUL. 7327 ins_cost(ALU_REG_COST); 7328 size(4); 7329 format %{ "MDBR $dst,$src" %} 7330 opcode(MDBR_ZOPC); 7331 ins_encode(z_rreform(dst, src)); 7332 ins_pipe(pipe_class_dummy); 7333 %} 7334 7335 instruct mulD_reg_mem(regD dst, memoryRX src)%{ 7336 match(Set dst (MulD dst (LoadD src))); 7337 // CC unchanged by MUL. 7338 ins_cost(ALU_MEMORY_COST); 7339 size(6); 7340 format %{ "MDB $dst,$src\t # doubleMemory" %} 7341 opcode(MDB_ZOPC); 7342 ins_encode(z_form_rt_memFP(dst, src)); 7343 ins_pipe(pipe_class_dummy); 7344 %} 7345 7346 // Multiply-Accumulate 7347 // src1 * src2 + dst 7348 instruct maddF_reg_reg(regF dst, regF src1, regF src2) %{ 7349 match(Set dst (FmaF dst (Binary src1 src2))); 7350 // CC unchanged by MUL-ADD. 7351 ins_cost(ALU_REG_COST); 7352 size(4); 7353 format %{ "MAEBR $dst, $src1, $src2" %} 7354 ins_encode %{ 7355 __ z_maebr($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister); 7356 %} 7357 ins_pipe(pipe_class_dummy); 7358 %} 7359 7360 // src1 * src2 + dst 7361 instruct maddD_reg_reg(regD dst, regD src1, regD src2) %{ 7362 match(Set dst (FmaD dst (Binary src1 src2))); 7363 // CC unchanged by MUL-ADD. 7364 ins_cost(ALU_REG_COST); 7365 size(4); 7366 format %{ "MADBR $dst, $src1, $src2" %} 7367 ins_encode %{ 7368 __ z_madbr($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister); 7369 %} 7370 ins_pipe(pipe_class_dummy); 7371 %} 7372 7373 // src1 * src2 - dst 7374 instruct msubF_reg_reg(regF dst, regF src1, regF src2) %{ 7375 match(Set dst (FmaF (NegF dst) (Binary src1 src2))); 7376 // CC unchanged by MUL-SUB. 7377 ins_cost(ALU_REG_COST); 7378 size(4); 7379 format %{ "MSEBR $dst, $src1, $src2" %} 7380 ins_encode %{ 7381 __ z_msebr($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister); 7382 %} 7383 ins_pipe(pipe_class_dummy); 7384 %} 7385 7386 // src1 * src2 - dst 7387 instruct msubD_reg_reg(regD dst, regD src1, regD src2) %{ 7388 match(Set dst (FmaD (NegD dst) (Binary src1 src2))); 7389 // CC unchanged by MUL-SUB. 7390 ins_cost(ALU_REG_COST); 7391 size(4); 7392 format %{ "MSDBR $dst, $src1, $src2" %} 7393 ins_encode %{ 7394 __ z_msdbr($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister); 7395 %} 7396 ins_pipe(pipe_class_dummy); 7397 %} 7398 7399 // src1 * src2 + dst 7400 instruct maddF_reg_mem(regF dst, regF src1, memoryRX src2) %{ 7401 match(Set dst (FmaF dst (Binary src1 (LoadF src2)))); 7402 // CC unchanged by MUL-ADD. 7403 ins_cost(ALU_MEMORY_COST); 7404 size(6); 7405 format %{ "MAEB $dst, $src1, $src2" %} 7406 ins_encode %{ 7407 __ z_maeb($dst$$FloatRegister, $src1$$FloatRegister, 7408 Address(reg_to_register_object($src2$$base), $src2$$index$$Register, $src2$$disp)); 7409 %} 7410 ins_pipe(pipe_class_dummy); 7411 %} 7412 7413 // src1 * src2 + dst 7414 instruct maddD_reg_mem(regD dst, regD src1, memoryRX src2) %{ 7415 match(Set dst (FmaD dst (Binary src1 (LoadD src2)))); 7416 // CC unchanged by MUL-ADD. 7417 ins_cost(ALU_MEMORY_COST); 7418 size(6); 7419 format %{ "MADB $dst, $src1, $src2" %} 7420 ins_encode %{ 7421 __ z_madb($dst$$FloatRegister, $src1$$FloatRegister, 7422 Address(reg_to_register_object($src2$$base), $src2$$index$$Register, $src2$$disp)); 7423 %} 7424 ins_pipe(pipe_class_dummy); 7425 %} 7426 7427 // src1 * src2 - dst 7428 instruct msubF_reg_mem(regF dst, regF src1, memoryRX src2) %{ 7429 match(Set dst (FmaF (NegF dst) (Binary src1 (LoadF src2)))); 7430 // CC unchanged by MUL-SUB. 7431 ins_cost(ALU_MEMORY_COST); 7432 size(6); 7433 format %{ "MSEB $dst, $src1, $src2" %} 7434 ins_encode %{ 7435 __ z_mseb($dst$$FloatRegister, $src1$$FloatRegister, 7436 Address(reg_to_register_object($src2$$base), $src2$$index$$Register, $src2$$disp)); 7437 %} 7438 ins_pipe(pipe_class_dummy); 7439 %} 7440 7441 // src1 * src2 - dst 7442 instruct msubD_reg_mem(regD dst, regD src1, memoryRX src2) %{ 7443 match(Set dst (FmaD (NegD dst) (Binary src1 (LoadD src2)))); 7444 // CC unchanged by MUL-SUB. 7445 ins_cost(ALU_MEMORY_COST); 7446 size(6); 7447 format %{ "MSDB $dst, $src1, $src2" %} 7448 ins_encode %{ 7449 __ z_msdb($dst$$FloatRegister, $src1$$FloatRegister, 7450 Address(reg_to_register_object($src2$$base), $src2$$index$$Register, $src2$$disp)); 7451 %} 7452 ins_pipe(pipe_class_dummy); 7453 %} 7454 7455 // src1 * src2 + dst 7456 instruct maddF_mem_reg(regF dst, memoryRX src1, regF src2) %{ 7457 match(Set dst (FmaF dst (Binary (LoadF src1) src2))); 7458 // CC unchanged by MUL-ADD. 7459 ins_cost(ALU_MEMORY_COST); 7460 size(6); 7461 format %{ "MAEB $dst, $src1, $src2" %} 7462 ins_encode %{ 7463 __ z_maeb($dst$$FloatRegister, $src2$$FloatRegister, 7464 Address(reg_to_register_object($src1$$base), $src1$$index$$Register, $src1$$disp)); 7465 %} 7466 ins_pipe(pipe_class_dummy); 7467 %} 7468 7469 // src1 * src2 + dst 7470 instruct maddD_mem_reg(regD dst, memoryRX src1, regD src2) %{ 7471 match(Set dst (FmaD dst (Binary (LoadD src1) src2))); 7472 // CC unchanged by MUL-ADD. 7473 ins_cost(ALU_MEMORY_COST); 7474 size(6); 7475 format %{ "MADB $dst, $src1, $src2" %} 7476 ins_encode %{ 7477 __ z_madb($dst$$FloatRegister, $src2$$FloatRegister, 7478 Address(reg_to_register_object($src1$$base), $src1$$index$$Register, $src1$$disp)); 7479 %} 7480 ins_pipe(pipe_class_dummy); 7481 %} 7482 7483 // src1 * src2 - dst 7484 instruct msubF_mem_reg(regF dst, memoryRX src1, regF src2) %{ 7485 match(Set dst (FmaF (NegF dst) (Binary (LoadF src1) src2))); 7486 // CC unchanged by MUL-SUB. 7487 ins_cost(ALU_MEMORY_COST); 7488 size(6); 7489 format %{ "MSEB $dst, $src1, $src2" %} 7490 ins_encode %{ 7491 __ z_mseb($dst$$FloatRegister, $src2$$FloatRegister, 7492 Address(reg_to_register_object($src1$$base), $src1$$index$$Register, $src1$$disp)); 7493 %} 7494 ins_pipe(pipe_class_dummy); 7495 %} 7496 7497 // src1 * src2 - dst 7498 instruct msubD_mem_reg(regD dst, memoryRX src1, regD src2) %{ 7499 match(Set dst (FmaD (NegD dst) (Binary (LoadD src1) src2))); 7500 // CC unchanged by MUL-SUB. 7501 ins_cost(ALU_MEMORY_COST); 7502 size(6); 7503 format %{ "MSDB $dst, $src1, $src2" %} 7504 ins_encode %{ 7505 __ z_msdb($dst$$FloatRegister, $src2$$FloatRegister, 7506 Address(reg_to_register_object($src1$$base), $src1$$index$$Register, $src1$$disp)); 7507 %} 7508 ins_pipe(pipe_class_dummy); 7509 %} 7510 7511 // DIV 7512 7513 // Div float single precision 7514 instruct divF_reg_reg(regF dst, regF src) %{ 7515 match(Set dst (DivF dst src)); 7516 // CC unchanged by DIV. 7517 ins_cost(ALU_REG_COST); 7518 size(4); 7519 format %{ "DEBR $dst,$src" %} 7520 opcode(DEBR_ZOPC); 7521 ins_encode(z_rreform(dst, src)); 7522 ins_pipe(pipe_class_dummy); 7523 %} 7524 7525 instruct divF_reg_mem(regF dst, memoryRX src)%{ 7526 match(Set dst (DivF dst (LoadF src))); 7527 // CC unchanged by DIV. 7528 ins_cost(ALU_MEMORY_COST); 7529 size(6); 7530 format %{ "DEB $dst,$src\t # floatMemory" %} 7531 opcode(DEB_ZOPC); 7532 ins_encode(z_form_rt_memFP(dst, src)); 7533 ins_pipe(pipe_class_dummy); 7534 %} 7535 7536 // Div float double precision 7537 instruct divD_reg_reg(regD dst, regD src) %{ 7538 match(Set dst (DivD dst src)); 7539 // CC unchanged by DIV. 7540 ins_cost(ALU_REG_COST); 7541 size(4); 7542 format %{ "DDBR $dst,$src" %} 7543 opcode(DDBR_ZOPC); 7544 ins_encode(z_rreform(dst, src)); 7545 ins_pipe(pipe_class_dummy); 7546 %} 7547 7548 instruct divD_reg_mem(regD dst, memoryRX src)%{ 7549 match(Set dst (DivD dst (LoadD src))); 7550 // CC unchanged by DIV. 7551 ins_cost(ALU_MEMORY_COST); 7552 size(6); 7553 format %{ "DDB $dst,$src\t # doubleMemory" %} 7554 opcode(DDB_ZOPC); 7555 ins_encode(z_form_rt_memFP(dst, src)); 7556 ins_pipe(pipe_class_dummy); 7557 %} 7558 7559 // ABS 7560 7561 // Absolute float single precision 7562 instruct absF_reg(regF dst, regF src, flagsReg cr) %{ 7563 match(Set dst (AbsF src)); 7564 effect(KILL cr); 7565 size(4); 7566 format %{ "LPEBR $dst,$src\t float" %} 7567 opcode(LPEBR_ZOPC); 7568 ins_encode(z_rreform(dst, src)); 7569 ins_pipe(pipe_class_dummy); 7570 %} 7571 7572 // Absolute float double precision 7573 instruct absD_reg(regD dst, regD src, flagsReg cr) %{ 7574 match(Set dst (AbsD src)); 7575 effect(KILL cr); 7576 size(4); 7577 format %{ "LPDBR $dst,$src\t double" %} 7578 opcode(LPDBR_ZOPC); 7579 ins_encode(z_rreform(dst, src)); 7580 ins_pipe(pipe_class_dummy); 7581 %} 7582 7583 // NEG(ABS) 7584 7585 // Negative absolute float single precision 7586 instruct nabsF_reg(regF dst, regF src, flagsReg cr) %{ 7587 match(Set dst (NegF (AbsF src))); 7588 effect(KILL cr); 7589 size(4); 7590 format %{ "LNEBR $dst,$src\t float" %} 7591 opcode(LNEBR_ZOPC); 7592 ins_encode(z_rreform(dst, src)); 7593 ins_pipe(pipe_class_dummy); 7594 %} 7595 7596 // Negative absolute float double precision 7597 instruct nabsD_reg(regD dst, regD src, flagsReg cr) %{ 7598 match(Set dst (NegD (AbsD src))); 7599 effect(KILL cr); 7600 size(4); 7601 format %{ "LNDBR $dst,$src\t double" %} 7602 opcode(LNDBR_ZOPC); 7603 ins_encode(z_rreform(dst, src)); 7604 ins_pipe(pipe_class_dummy); 7605 %} 7606 7607 // NEG 7608 7609 instruct negF_reg(regF dst, regF src, flagsReg cr) %{ 7610 match(Set dst (NegF src)); 7611 effect(KILL cr); 7612 size(4); 7613 format %{ "NegF $dst,$src\t float" %} 7614 ins_encode %{ __ z_lcebr($dst$$FloatRegister, $src$$FloatRegister); %} 7615 ins_pipe(pipe_class_dummy); 7616 %} 7617 7618 instruct negD_reg(regD dst, regD src, flagsReg cr) %{ 7619 match(Set dst (NegD src)); 7620 effect(KILL cr); 7621 size(4); 7622 format %{ "NegD $dst,$src\t double" %} 7623 ins_encode %{ __ z_lcdbr($dst$$FloatRegister, $src$$FloatRegister); %} 7624 ins_pipe(pipe_class_dummy); 7625 %} 7626 7627 // SQRT 7628 7629 // Sqrt float precision 7630 instruct sqrtF_reg(regF dst, regF src) %{ 7631 match(Set dst (ConvD2F (SqrtD (ConvF2D src)))); 7632 // CC remains unchanged. 7633 ins_cost(ALU_REG_COST); 7634 size(4); 7635 format %{ "SQEBR $dst,$src" %} 7636 opcode(SQEBR_ZOPC); 7637 ins_encode(z_rreform(dst, src)); 7638 ins_pipe(pipe_class_dummy); 7639 %} 7640 7641 // Sqrt double precision 7642 instruct sqrtD_reg(regD dst, regD src) %{ 7643 match(Set dst (SqrtD src)); 7644 // CC remains unchanged. 7645 ins_cost(ALU_REG_COST); 7646 size(4); 7647 format %{ "SQDBR $dst,$src" %} 7648 opcode(SQDBR_ZOPC); 7649 ins_encode(z_rreform(dst, src)); 7650 ins_pipe(pipe_class_dummy); 7651 %} 7652 7653 instruct sqrtF_mem(regF dst, memoryRX src) %{ 7654 match(Set dst (ConvD2F (SqrtD (ConvF2D src)))); 7655 // CC remains unchanged. 7656 ins_cost(ALU_MEMORY_COST); 7657 size(6); 7658 format %{ "SQEB $dst,$src\t # floatMemory" %} 7659 opcode(SQEB_ZOPC); 7660 ins_encode(z_form_rt_memFP(dst, src)); 7661 ins_pipe(pipe_class_dummy); 7662 %} 7663 7664 instruct sqrtD_mem(regD dst, memoryRX src) %{ 7665 match(Set dst (SqrtD src)); 7666 // CC remains unchanged. 7667 ins_cost(ALU_MEMORY_COST); 7668 // TODO: s390 port size(FIXED_SIZE); 7669 format %{ "SQDB $dst,$src\t # doubleMemory" %} 7670 opcode(SQDB_ZOPC); 7671 ins_encode(z_form_rt_memFP(dst, src)); 7672 ins_pipe(pipe_class_dummy); 7673 %} 7674 7675 //----------Logical Instructions----------------------------------------------- 7676 7677 // Register And 7678 instruct andI_reg_reg(iRegI dst, iRegI src, flagsReg cr) %{ 7679 match(Set dst (AndI dst src)); 7680 effect(KILL cr); 7681 ins_cost(DEFAULT_COST_LOW); 7682 size(2); 7683 format %{ "NR $dst,$src\t # int" %} 7684 opcode(NR_ZOPC); 7685 ins_encode(z_rrform(dst, src)); 7686 ins_pipe(pipe_class_dummy); 7687 %} 7688 7689 instruct andI_Reg_mem(iRegI dst, memory src, flagsReg cr)%{ 7690 match(Set dst (AndI dst (LoadI src))); 7691 effect(KILL cr); 7692 ins_cost(MEMORY_REF_COST); 7693 // TODO: s390 port size(VARIABLE_SIZE); 7694 format %{ "N(Y) $dst, $src\t # int" %} 7695 opcode(NY_ZOPC, N_ZOPC); 7696 ins_encode(z_form_rt_mem_opt(dst, src)); 7697 ins_pipe(pipe_class_dummy); 7698 %} 7699 7700 // Immediate And 7701 instruct andI_reg_uimm32(iRegI dst, uimmI src, flagsReg cr) %{ 7702 match(Set dst (AndI dst src)); 7703 effect(KILL cr); 7704 ins_cost(DEFAULT_COST_HIGH); 7705 size(6); 7706 format %{ "NILF $dst,$src" %} 7707 opcode(NILF_ZOPC); 7708 ins_encode(z_rilform_unsigned(dst, src)); 7709 ins_pipe(pipe_class_dummy); 7710 %} 7711 7712 instruct andI_reg_uimmI_LH1(iRegI dst, uimmI_LH1 src, flagsReg cr) %{ 7713 match(Set dst (AndI dst src)); 7714 effect(KILL cr); 7715 ins_cost(DEFAULT_COST); 7716 size(4); 7717 format %{ "NILH $dst,$src" %} 7718 ins_encode %{ __ z_nilh($dst$$Register, ($src$$constant >> 16) & 0xFFFF); %} 7719 ins_pipe(pipe_class_dummy); 7720 %} 7721 7722 instruct andI_reg_uimmI_LL1(iRegI dst, uimmI_LL1 src, flagsReg cr) %{ 7723 match(Set dst (AndI dst src)); 7724 effect(KILL cr); 7725 ins_cost(DEFAULT_COST); 7726 size(4); 7727 format %{ "NILL $dst,$src" %} 7728 ins_encode %{ __ z_nill($dst$$Register, $src$$constant & 0xFFFF); %} 7729 ins_pipe(pipe_class_dummy); 7730 %} 7731 7732 // Register And Long 7733 instruct andL_reg_reg(iRegL dst, iRegL src, flagsReg cr) %{ 7734 match(Set dst (AndL dst src)); 7735 effect(KILL cr); 7736 ins_cost(DEFAULT_COST); 7737 size(4); 7738 format %{ "NGR $dst,$src\t # long" %} 7739 opcode(NGR_ZOPC); 7740 ins_encode(z_rreform(dst, src)); 7741 ins_pipe(pipe_class_dummy); 7742 %} 7743 7744 instruct andL_Reg_mem(iRegL dst, memory src, flagsReg cr)%{ 7745 match(Set dst (AndL dst (LoadL src))); 7746 effect(KILL cr); 7747 ins_cost(MEMORY_REF_COST); 7748 size(Z_DISP3_SIZE); 7749 format %{ "NG $dst, $src\t # long" %} 7750 opcode(NG_ZOPC, NG_ZOPC); 7751 ins_encode(z_form_rt_mem_opt(dst, src)); 7752 ins_pipe(pipe_class_dummy); 7753 %} 7754 7755 instruct andL_reg_uimmL_LL1(iRegL dst, uimmL_LL1 src, flagsReg cr) %{ 7756 match(Set dst (AndL dst src)); 7757 effect(KILL cr); 7758 ins_cost(DEFAULT_COST); 7759 size(4); 7760 format %{ "NILL $dst,$src\t # long" %} 7761 ins_encode %{ __ z_nill($dst$$Register, $src$$constant & 0xFFFF); %} 7762 ins_pipe(pipe_class_dummy); 7763 %} 7764 7765 instruct andL_reg_uimmL_LH1(iRegL dst, uimmL_LH1 src, flagsReg cr) %{ 7766 match(Set dst (AndL dst src)); 7767 effect(KILL cr); 7768 ins_cost(DEFAULT_COST); 7769 size(4); 7770 format %{ "NILH $dst,$src\t # long" %} 7771 ins_encode %{ __ z_nilh($dst$$Register, ($src$$constant >> 16) & 0xFFFF); %} 7772 ins_pipe(pipe_class_dummy); 7773 %} 7774 7775 instruct andL_reg_uimmL_HL1(iRegL dst, uimmL_HL1 src, flagsReg cr) %{ 7776 match(Set dst (AndL dst src)); 7777 effect(KILL cr); 7778 ins_cost(DEFAULT_COST); 7779 size(4); 7780 format %{ "NIHL $dst,$src\t # long" %} 7781 ins_encode %{ __ z_nihl($dst$$Register, ($src$$constant >> 32) & 0xFFFF); %} 7782 ins_pipe(pipe_class_dummy); 7783 %} 7784 7785 instruct andL_reg_uimmL_HH1(iRegL dst, uimmL_HH1 src, flagsReg cr) %{ 7786 match(Set dst (AndL dst src)); 7787 effect(KILL cr); 7788 ins_cost(DEFAULT_COST); 7789 size(4); 7790 format %{ "NIHH $dst,$src\t # long" %} 7791 ins_encode %{ __ z_nihh($dst$$Register, ($src$$constant >> 48) & 0xFFFF); %} 7792 ins_pipe(pipe_class_dummy); 7793 %} 7794 7795 // OR 7796 7797 // Or Instructions 7798 // Register Or 7799 instruct orI_reg_reg(iRegI dst, iRegI src, flagsReg cr) %{ 7800 match(Set dst (OrI dst src)); 7801 effect(KILL cr); 7802 size(2); 7803 format %{ "OR $dst,$src" %} 7804 opcode(OR_ZOPC); 7805 ins_encode(z_rrform(dst, src)); 7806 ins_pipe(pipe_class_dummy); 7807 %} 7808 7809 instruct orI_Reg_mem(iRegI dst, memory src, flagsReg cr)%{ 7810 match(Set dst (OrI dst (LoadI src))); 7811 effect(KILL cr); 7812 ins_cost(MEMORY_REF_COST); 7813 // TODO: s390 port size(VARIABLE_SIZE); 7814 format %{ "O(Y) $dst, $src\t # int" %} 7815 opcode(OY_ZOPC, O_ZOPC); 7816 ins_encode(z_form_rt_mem_opt(dst, src)); 7817 ins_pipe(pipe_class_dummy); 7818 %} 7819 7820 // Immediate Or 7821 instruct orI_reg_uimm16(iRegI dst, uimmI16 con, flagsReg cr) %{ 7822 match(Set dst (OrI dst con)); 7823 effect(KILL cr); 7824 size(4); 7825 format %{ "OILL $dst,$con" %} 7826 opcode(OILL_ZOPC); 7827 ins_encode(z_riform_unsigned(dst,con)); 7828 ins_pipe(pipe_class_dummy); 7829 %} 7830 7831 instruct orI_reg_uimm32(iRegI dst, uimmI con, flagsReg cr) %{ 7832 match(Set dst (OrI dst con)); 7833 effect(KILL cr); 7834 ins_cost(DEFAULT_COST_HIGH); 7835 size(6); 7836 format %{ "OILF $dst,$con" %} 7837 opcode(OILF_ZOPC); 7838 ins_encode(z_rilform_unsigned(dst,con)); 7839 ins_pipe(pipe_class_dummy); 7840 %} 7841 7842 // Register Or Long 7843 instruct orL_reg_reg(iRegL dst, iRegL src, flagsReg cr) %{ 7844 match(Set dst (OrL dst src)); 7845 effect(KILL cr); 7846 ins_cost(DEFAULT_COST); 7847 size(4); 7848 format %{ "OGR $dst,$src\t # long" %} 7849 opcode(OGR_ZOPC); 7850 ins_encode(z_rreform(dst, src)); 7851 ins_pipe(pipe_class_dummy); 7852 %} 7853 7854 instruct orL_Reg_mem(iRegL dst, memory src, flagsReg cr)%{ 7855 match(Set dst (OrL dst (LoadL src))); 7856 effect(KILL cr); 7857 ins_cost(MEMORY_REF_COST); 7858 size(Z_DISP3_SIZE); 7859 format %{ "OG $dst, $src\t # long" %} 7860 opcode(OG_ZOPC, OG_ZOPC); 7861 ins_encode(z_form_rt_mem_opt(dst, src)); 7862 ins_pipe(pipe_class_dummy); 7863 %} 7864 7865 // Immediate Or long 7866 instruct orL_reg_uimm16(iRegL dst, uimmL16 con, flagsReg cr) %{ 7867 match(Set dst (OrL dst con)); 7868 effect(KILL cr); 7869 ins_cost(DEFAULT_COST); 7870 size(4); 7871 format %{ "OILL $dst,$con\t # long" %} 7872 opcode(OILL_ZOPC); 7873 ins_encode(z_riform_unsigned(dst,con)); 7874 ins_pipe(pipe_class_dummy); 7875 %} 7876 7877 instruct orL_reg_uimm32(iRegI dst, uimmL32 con, flagsReg cr) %{ 7878 match(Set dst (OrI dst con)); 7879 effect(KILL cr); 7880 ins_cost(DEFAULT_COST_HIGH); 7881 // TODO: s390 port size(FIXED_SIZE); 7882 format %{ "OILF $dst,$con\t # long" %} 7883 opcode(OILF_ZOPC); 7884 ins_encode(z_rilform_unsigned(dst,con)); 7885 ins_pipe(pipe_class_dummy); 7886 %} 7887 7888 // XOR 7889 7890 // Register Xor 7891 instruct xorI_reg_reg(iRegI dst, iRegI src, flagsReg cr) %{ 7892 match(Set dst (XorI dst src)); 7893 effect(KILL cr); 7894 size(2); 7895 format %{ "XR $dst,$src" %} 7896 opcode(XR_ZOPC); 7897 ins_encode(z_rrform(dst, src)); 7898 ins_pipe(pipe_class_dummy); 7899 %} 7900 7901 instruct xorI_Reg_mem(iRegI dst, memory src, flagsReg cr)%{ 7902 match(Set dst (XorI dst (LoadI src))); 7903 effect(KILL cr); 7904 ins_cost(MEMORY_REF_COST); 7905 // TODO: s390 port size(VARIABLE_SIZE); 7906 format %{ "X(Y) $dst, $src\t # int" %} 7907 opcode(XY_ZOPC, X_ZOPC); 7908 ins_encode(z_form_rt_mem_opt(dst, src)); 7909 ins_pipe(pipe_class_dummy); 7910 %} 7911 7912 // Immediate Xor 7913 instruct xorI_reg_uimm32(iRegI dst, uimmI src, flagsReg cr) %{ 7914 match(Set dst (XorI dst src)); 7915 effect(KILL cr); 7916 ins_cost(DEFAULT_COST_HIGH); 7917 size(6); 7918 format %{ "XILF $dst,$src" %} 7919 opcode(XILF_ZOPC); 7920 ins_encode(z_rilform_unsigned(dst, src)); 7921 ins_pipe(pipe_class_dummy); 7922 %} 7923 7924 // Register Xor Long 7925 instruct xorL_reg_reg(iRegL dst, iRegL src, flagsReg cr) %{ 7926 match(Set dst (XorL dst src)); 7927 effect(KILL cr); 7928 ins_cost(DEFAULT_COST); 7929 size(4); 7930 format %{ "XGR $dst,$src\t # long" %} 7931 opcode(XGR_ZOPC); 7932 ins_encode(z_rreform(dst, src)); 7933 ins_pipe(pipe_class_dummy); 7934 %} 7935 7936 instruct xorL_Reg_mem(iRegL dst, memory src, flagsReg cr)%{ 7937 match(Set dst (XorL dst (LoadL src))); 7938 effect(KILL cr); 7939 ins_cost(MEMORY_REF_COST); 7940 size(Z_DISP3_SIZE); 7941 format %{ "XG $dst, $src\t # long" %} 7942 opcode(XG_ZOPC, XG_ZOPC); 7943 ins_encode(z_form_rt_mem_opt(dst, src)); 7944 ins_pipe(pipe_class_dummy); 7945 %} 7946 7947 // Immediate Xor Long 7948 instruct xorL_reg_uimm32(iRegL dst, uimmL32 con, flagsReg cr) %{ 7949 match(Set dst (XorL dst con)); 7950 effect(KILL cr); 7951 ins_cost(DEFAULT_COST_HIGH); 7952 size(6); 7953 format %{ "XILF $dst,$con\t # long" %} 7954 opcode(XILF_ZOPC); 7955 ins_encode(z_rilform_unsigned(dst,con)); 7956 ins_pipe(pipe_class_dummy); 7957 %} 7958 7959 //----------Convert to Boolean------------------------------------------------- 7960 7961 // Convert integer to boolean. 7962 instruct convI2B(iRegI dst, iRegI src, flagsReg cr) %{ 7963 match(Set dst (Conv2B src)); 7964 effect(KILL cr); 7965 ins_cost(3 * DEFAULT_COST); 7966 size(6); 7967 format %{ "convI2B $dst,$src" %} 7968 ins_encode %{ 7969 __ z_lnr($dst$$Register, $src$$Register); // Rdst := -|Rsrc|, i.e. Rdst == 0 <=> Rsrc == 0 7970 __ z_srl($dst$$Register, 31); // Rdst := sign(Rdest) 7971 %} 7972 ins_pipe(pipe_class_dummy); 7973 %} 7974 7975 instruct convP2B(iRegI dst, iRegP_N2P src, flagsReg cr) %{ 7976 match(Set dst (Conv2B src)); 7977 effect(KILL cr); 7978 ins_cost(3 * DEFAULT_COST); 7979 size(10); 7980 format %{ "convP2B $dst,$src" %} 7981 ins_encode %{ 7982 __ z_lngr($dst$$Register, $src$$Register); // Rdst := -|Rsrc| i.e. Rdst == 0 <=> Rsrc == 0 7983 __ z_srlg($dst$$Register, $dst$$Register, 63); // Rdst := sign(Rdest) 7984 %} 7985 ins_pipe(pipe_class_dummy); 7986 %} 7987 7988 instruct cmpLTMask_reg_reg(iRegI dst, iRegI src, flagsReg cr) %{ 7989 match(Set dst (CmpLTMask dst src)); 7990 effect(KILL cr); 7991 ins_cost(2 * DEFAULT_COST); 7992 size(18); 7993 format %{ "Set $dst CmpLTMask $dst,$src" %} 7994 ins_encode %{ 7995 // Avoid signed 32 bit overflow: Do sign extend and sub 64 bit. 7996 __ z_lgfr(Z_R0_scratch, $src$$Register); 7997 __ z_lgfr($dst$$Register, $dst$$Register); 7998 __ z_sgr($dst$$Register, Z_R0_scratch); 7999 __ z_srag($dst$$Register, $dst$$Register, 63); 8000 %} 8001 ins_pipe(pipe_class_dummy); 8002 %} 8003 8004 instruct cmpLTMask_reg_zero(iRegI dst, immI_0 zero, flagsReg cr) %{ 8005 match(Set dst (CmpLTMask dst zero)); 8006 effect(KILL cr); 8007 ins_cost(DEFAULT_COST); 8008 size(4); 8009 format %{ "Set $dst CmpLTMask $dst,$zero" %} 8010 ins_encode %{ __ z_sra($dst$$Register, 31); %} 8011 ins_pipe(pipe_class_dummy); 8012 %} 8013 8014 8015 //----------Arithmetic Conversion Instructions--------------------------------- 8016 // The conversions operations are all Alpha sorted. Please keep it that way! 8017 8018 instruct convD2F_reg(regF dst, regD src) %{ 8019 match(Set dst (ConvD2F src)); 8020 // CC remains unchanged. 8021 size(4); 8022 format %{ "LEDBR $dst,$src" %} 8023 opcode(LEDBR_ZOPC); 8024 ins_encode(z_rreform(dst, src)); 8025 ins_pipe(pipe_class_dummy); 8026 %} 8027 8028 instruct convF2I_reg(iRegI dst, regF src, flagsReg cr) %{ 8029 match(Set dst (ConvF2I src)); 8030 effect(KILL cr); 8031 ins_cost(2 * DEFAULT_COST + BRANCH_COST); 8032 size(16); 8033 format %{ "convF2I $dst,$src" %} 8034 ins_encode %{ 8035 Label done; 8036 __ clear_reg($dst$$Register, false, false); // Initialize with result for unordered: 0. 8037 __ z_cebr($src$$FloatRegister, $src$$FloatRegister); // Round. 8038 __ z_brno(done); // Result is zero if unordered argument. 8039 __ z_cfebr($dst$$Register, $src$$FloatRegister, Assembler::to_zero); 8040 __ bind(done); 8041 %} 8042 ins_pipe(pipe_class_dummy); 8043 %} 8044 8045 instruct convD2I_reg(iRegI dst, regD src, flagsReg cr) %{ 8046 match(Set dst (ConvD2I src)); 8047 effect(KILL cr); 8048 ins_cost(2 * DEFAULT_COST + BRANCH_COST); 8049 size(16); 8050 format %{ "convD2I $dst,$src" %} 8051 ins_encode %{ 8052 Label done; 8053 __ clear_reg($dst$$Register, false, false); // Initialize with result for unordered: 0. 8054 __ z_cdbr($src$$FloatRegister, $src$$FloatRegister); // Round. 8055 __ z_brno(done); // Result is zero if unordered argument. 8056 __ z_cfdbr($dst$$Register, $src$$FloatRegister, Assembler::to_zero); 8057 __ bind(done); 8058 %} 8059 ins_pipe(pipe_class_dummy); 8060 %} 8061 8062 instruct convF2L_reg(iRegL dst, regF src, flagsReg cr) %{ 8063 match(Set dst (ConvF2L src)); 8064 effect(KILL cr); 8065 ins_cost(2 * DEFAULT_COST + BRANCH_COST); 8066 size(16); 8067 format %{ "convF2L $dst,$src" %} 8068 ins_encode %{ 8069 Label done; 8070 __ clear_reg($dst$$Register, true, false); // Initialize with result for unordered: 0. 8071 __ z_cebr($src$$FloatRegister, $src$$FloatRegister); // Round. 8072 __ z_brno(done); // Result is zero if unordered argument. 8073 __ z_cgebr($dst$$Register, $src$$FloatRegister, Assembler::to_zero); 8074 __ bind(done); 8075 %} 8076 ins_pipe(pipe_class_dummy); 8077 %} 8078 8079 instruct convD2L_reg(iRegL dst, regD src, flagsReg cr) %{ 8080 match(Set dst (ConvD2L src)); 8081 effect(KILL cr); 8082 ins_cost(2 * DEFAULT_COST + BRANCH_COST); 8083 size(16); 8084 format %{ "convD2L $dst,$src" %} 8085 ins_encode %{ 8086 Label done; 8087 __ clear_reg($dst$$Register, true, false); // Initialize with result for unordered: 0. 8088 __ z_cdbr($src$$FloatRegister, $src$$FloatRegister); // Round. 8089 __ z_brno(done); // Result is zero if unordered argument. 8090 __ z_cgdbr($dst$$Register, $src$$FloatRegister, Assembler::to_zero); 8091 __ bind(done); 8092 %} 8093 ins_pipe(pipe_class_dummy); 8094 %} 8095 8096 instruct convF2D_reg(regD dst, regF src) %{ 8097 match(Set dst (ConvF2D src)); 8098 // CC remains unchanged. 8099 size(4); 8100 format %{ "LDEBR $dst,$src" %} 8101 opcode(LDEBR_ZOPC); 8102 ins_encode(z_rreform(dst, src)); 8103 ins_pipe(pipe_class_dummy); 8104 %} 8105 8106 instruct convF2D_mem(regD dst, memoryRX src) %{ 8107 match(Set dst (ConvF2D src)); 8108 // CC remains unchanged. 8109 size(6); 8110 format %{ "LDEB $dst,$src" %} 8111 opcode(LDEB_ZOPC); 8112 ins_encode(z_form_rt_memFP(dst, src)); 8113 ins_pipe(pipe_class_dummy); 8114 %} 8115 8116 instruct convI2D_reg(regD dst, iRegI src) %{ 8117 match(Set dst (ConvI2D src)); 8118 // CC remains unchanged. 8119 ins_cost(DEFAULT_COST); 8120 size(4); 8121 format %{ "CDFBR $dst,$src" %} 8122 opcode(CDFBR_ZOPC); 8123 ins_encode(z_rreform(dst, src)); 8124 ins_pipe(pipe_class_dummy); 8125 %} 8126 8127 // Optimization that saves up to two memory operations for each conversion. 8128 instruct convI2F_ireg(regF dst, iRegI src) %{ 8129 match(Set dst (ConvI2F src)); 8130 // CC remains unchanged. 8131 ins_cost(DEFAULT_COST); 8132 size(4); 8133 format %{ "CEFBR $dst,$src\t # convert int to float" %} 8134 opcode(CEFBR_ZOPC); 8135 ins_encode(z_rreform(dst, src)); 8136 ins_pipe(pipe_class_dummy); 8137 %} 8138 8139 instruct convI2L_reg(iRegL dst, iRegI src) %{ 8140 match(Set dst (ConvI2L src)); 8141 size(4); 8142 format %{ "LGFR $dst,$src\t # int->long" %} 8143 opcode(LGFR_ZOPC); 8144 ins_encode(z_rreform(dst, src)); 8145 ins_pipe(pipe_class_dummy); 8146 %} 8147 8148 // Zero-extend convert int to long. 8149 instruct convI2L_reg_zex(iRegL dst, iRegI src, immL_32bits mask) %{ 8150 match(Set dst (AndL (ConvI2L src) mask)); 8151 size(4); 8152 format %{ "LLGFR $dst, $src \t # zero-extend int to long" %} 8153 ins_encode %{ __ z_llgfr($dst$$Register, $src$$Register); %} 8154 ins_pipe(pipe_class_dummy); 8155 %} 8156 8157 // Zero-extend convert int to long. 8158 instruct convI2L_mem_zex(iRegL dst, memory src, immL_32bits mask) %{ 8159 match(Set dst (AndL (ConvI2L (LoadI src)) mask)); 8160 // Uses load_const_optmized, so size can vary. 8161 // TODO: s390 port size(VARIABLE_SIZE); 8162 format %{ "LLGF $dst, $src \t # zero-extend int to long" %} 8163 opcode(LLGF_ZOPC, LLGF_ZOPC); 8164 ins_encode(z_form_rt_mem_opt(dst, src)); 8165 ins_pipe(pipe_class_dummy); 8166 %} 8167 8168 // Zero-extend long 8169 instruct zeroExtend_long(iRegL dst, iRegL src, immL_32bits mask) %{ 8170 match(Set dst (AndL src mask)); 8171 size(4); 8172 format %{ "LLGFR $dst, $src \t # zero-extend long to long" %} 8173 ins_encode %{ __ z_llgfr($dst$$Register, $src$$Register); %} 8174 ins_pipe(pipe_class_dummy); 8175 %} 8176 8177 instruct rShiftI16_lShiftI16_reg(iRegI dst, iRegI src, immI_16 amount) %{ 8178 match(Set dst (RShiftI (LShiftI src amount) amount)); 8179 size(4); 8180 format %{ "LHR $dst,$src\t short->int" %} 8181 opcode(LHR_ZOPC); 8182 ins_encode(z_rreform(dst, src)); 8183 ins_pipe(pipe_class_dummy); 8184 %} 8185 8186 instruct rShiftI24_lShiftI24_reg(iRegI dst, iRegI src, immI_24 amount) %{ 8187 match(Set dst (RShiftI (LShiftI src amount) amount)); 8188 size(4); 8189 format %{ "LBR $dst,$src\t byte->int" %} 8190 opcode(LBR_ZOPC); 8191 ins_encode(z_rreform(dst, src)); 8192 ins_pipe(pipe_class_dummy); 8193 %} 8194 8195 instruct MoveF2I_stack_reg(iRegI dst, stackSlotF src) %{ 8196 match(Set dst (MoveF2I src)); 8197 ins_cost(MEMORY_REF_COST); 8198 size(4); 8199 format %{ "L $dst,$src\t # MoveF2I" %} 8200 opcode(L_ZOPC); 8201 ins_encode(z_form_rt_mem(dst, src)); 8202 ins_pipe(pipe_class_dummy); 8203 %} 8204 8205 // javax.imageio.stream.ImageInputStreamImpl.toFloats([B[FII) 8206 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{ 8207 match(Set dst (MoveI2F src)); 8208 ins_cost(MEMORY_REF_COST); 8209 // TODO: s390 port size(FIXED_SIZE); 8210 format %{ "LE $dst,$src\t # MoveI2F" %} 8211 opcode(LE_ZOPC); 8212 ins_encode(z_form_rt_mem(dst, src)); 8213 ins_pipe(pipe_class_dummy); 8214 %} 8215 8216 instruct MoveD2L_stack_reg(iRegL dst, stackSlotD src) %{ 8217 match(Set dst (MoveD2L src)); 8218 ins_cost(MEMORY_REF_COST); 8219 size(6); 8220 format %{ "LG $src,$dst\t # MoveD2L" %} 8221 opcode(LG_ZOPC); 8222 ins_encode(z_form_rt_mem(dst, src)); 8223 ins_pipe(pipe_class_dummy); 8224 %} 8225 8226 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{ 8227 match(Set dst (MoveL2D src)); 8228 ins_cost(MEMORY_REF_COST); 8229 size(4); 8230 format %{ "LD $dst,$src\t # MoveL2D" %} 8231 opcode(LD_ZOPC); 8232 ins_encode(z_form_rt_mem(dst, src)); 8233 ins_pipe(pipe_class_dummy); 8234 %} 8235 8236 instruct MoveI2F_reg_stack(stackSlotF dst, iRegI src) %{ 8237 match(Set dst (MoveI2F src)); 8238 ins_cost(MEMORY_REF_COST); 8239 size(4); 8240 format %{ "ST $src,$dst\t # MoveI2F" %} 8241 opcode(ST_ZOPC); 8242 ins_encode(z_form_rt_mem(src, dst)); 8243 ins_pipe(pipe_class_dummy); 8244 %} 8245 8246 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{ 8247 match(Set dst (MoveD2L src)); 8248 effect(DEF dst, USE src); 8249 ins_cost(MEMORY_REF_COST); 8250 size(4); 8251 format %{ "STD $src,$dst\t # MoveD2L" %} 8252 opcode(STD_ZOPC); 8253 ins_encode(z_form_rt_mem(src,dst)); 8254 ins_pipe(pipe_class_dummy); 8255 %} 8256 8257 instruct MoveL2D_reg_stack(stackSlotD dst, iRegL src) %{ 8258 match(Set dst (MoveL2D src)); 8259 ins_cost(MEMORY_REF_COST); 8260 size(6); 8261 format %{ "STG $src,$dst\t # MoveL2D" %} 8262 opcode(STG_ZOPC); 8263 ins_encode(z_form_rt_mem(src,dst)); 8264 ins_pipe(pipe_class_dummy); 8265 %} 8266 8267 instruct convL2F_reg(regF dst, iRegL src) %{ 8268 match(Set dst (ConvL2F src)); 8269 // CC remains unchanged. 8270 ins_cost(DEFAULT_COST); 8271 size(4); 8272 format %{ "CEGBR $dst,$src" %} 8273 opcode(CEGBR_ZOPC); 8274 ins_encode(z_rreform(dst, src)); 8275 ins_pipe(pipe_class_dummy); 8276 %} 8277 8278 instruct convL2D_reg(regD dst, iRegL src) %{ 8279 match(Set dst (ConvL2D src)); 8280 // CC remains unchanged. 8281 ins_cost(DEFAULT_COST); 8282 size(4); 8283 format %{ "CDGBR $dst,$src" %} 8284 opcode(CDGBR_ZOPC); 8285 ins_encode(z_rreform(dst, src)); 8286 ins_pipe(pipe_class_dummy); 8287 %} 8288 8289 instruct convL2I_reg(iRegI dst, iRegL src) %{ 8290 match(Set dst (ConvL2I src)); 8291 // TODO: s390 port size(VARIABLE_SIZE); 8292 format %{ "LR $dst,$src\t # long->int (if needed)" %} 8293 ins_encode %{ __ lr_if_needed($dst$$Register, $src$$Register); %} 8294 ins_pipe(pipe_class_dummy); 8295 %} 8296 8297 // Register Shift Right Immediate 8298 instruct shrL_reg_imm6_L2I(iRegI dst, iRegL src, immI_32_63 cnt, flagsReg cr) %{ 8299 match(Set dst (ConvL2I (RShiftL src cnt))); 8300 effect(KILL cr); 8301 size(6); 8302 format %{ "SRAG $dst,$src,$cnt" %} 8303 opcode(SRAG_ZOPC); 8304 ins_encode(z_rsyform_const(dst, src, cnt)); 8305 ins_pipe(pipe_class_dummy); 8306 %} 8307 8308 //----------TRAP based zero checks and range checks---------------------------- 8309 8310 // SIGTRAP based implicit range checks in compiled code. 8311 // A range check in the ideal world has one of the following shapes: 8312 // - (If le (CmpU length index)), (IfTrue throw exception) 8313 // - (If lt (CmpU index length)), (IfFalse throw exception) 8314 // 8315 // Match range check 'If le (CmpU length index)' 8316 instruct rangeCheck_iReg_uimmI16(cmpOpT cmp, iRegI length, uimmI16 index, label labl) %{ 8317 match(If cmp (CmpU length index)); 8318 effect(USE labl); 8319 predicate(TrapBasedRangeChecks && 8320 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le && 8321 PROB_UNLIKELY(_leaf->as_If ()->_prob) >= PROB_ALWAYS && 8322 Matcher::branches_to_uncommon_trap(_leaf)); 8323 ins_cost(1); 8324 // TODO: s390 port size(FIXED_SIZE); 8325 8326 ins_is_TrapBasedCheckNode(true); 8327 8328 format %{ "RangeCheck len=$length cmp=$cmp idx=$index => trap $labl" %} 8329 ins_encode %{ __ z_clfit($length$$Register, $index$$constant, $cmp$$cmpcode); %} 8330 ins_pipe(pipe_class_trap); 8331 %} 8332 8333 // Match range check 'If lt (CmpU index length)' 8334 instruct rangeCheck_iReg_iReg(cmpOpT cmp, iRegI index, iRegI length, label labl, flagsReg cr) %{ 8335 match(If cmp (CmpU index length)); 8336 effect(USE labl, KILL cr); 8337 predicate(TrapBasedRangeChecks && 8338 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt && 8339 _leaf->as_If ()->_prob >= PROB_ALWAYS && 8340 Matcher::branches_to_uncommon_trap(_leaf)); 8341 ins_cost(1); 8342 // TODO: s390 port size(FIXED_SIZE); 8343 8344 ins_is_TrapBasedCheckNode(true); 8345 8346 format %{ "RangeCheck idx=$index cmp=$cmp len=$length => trap $labl" %} 8347 ins_encode %{ __ z_clrt($index$$Register, $length$$Register, $cmp$$cmpcode); %} 8348 ins_pipe(pipe_class_trap); 8349 %} 8350 8351 // Match range check 'If lt (CmpU index length)' 8352 instruct rangeCheck_uimmI16_iReg(cmpOpT cmp, iRegI index, uimmI16 length, label labl) %{ 8353 match(If cmp (CmpU index length)); 8354 effect(USE labl); 8355 predicate(TrapBasedRangeChecks && 8356 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt && 8357 _leaf->as_If ()->_prob >= PROB_ALWAYS && 8358 Matcher::branches_to_uncommon_trap(_leaf)); 8359 ins_cost(1); 8360 // TODO: s390 port size(FIXED_SIZE); 8361 8362 ins_is_TrapBasedCheckNode(true); 8363 8364 format %{ "RangeCheck idx=$index cmp=$cmp len= $length => trap $labl" %} 8365 ins_encode %{ __ z_clfit($index$$Register, $length$$constant, $cmp$$cmpcode); %} 8366 ins_pipe(pipe_class_trap); 8367 %} 8368 8369 // Implicit zero checks (more implicit null checks). 8370 instruct zeroCheckP_iReg_imm0(cmpOpT cmp, iRegP_N2P value, immP0 zero, label labl) %{ 8371 match(If cmp (CmpP value zero)); 8372 effect(USE labl); 8373 predicate(TrapBasedNullChecks && 8374 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne && 8375 _leaf->as_If ()->_prob >= PROB_LIKELY_MAG(4) && 8376 Matcher::branches_to_uncommon_trap(_leaf)); 8377 size(6); 8378 8379 ins_is_TrapBasedCheckNode(true); 8380 8381 format %{ "ZeroCheckP value=$value cmp=$cmp zero=$zero => trap $labl" %} 8382 ins_encode %{ __ z_cgit($value$$Register, 0, $cmp$$cmpcode); %} 8383 ins_pipe(pipe_class_trap); 8384 %} 8385 8386 // Implicit zero checks (more implicit null checks). 8387 instruct zeroCheckN_iReg_imm0(cmpOpT cmp, iRegN_P2N value, immN0 zero, label labl) %{ 8388 match(If cmp (CmpN value zero)); 8389 effect(USE labl); 8390 predicate(TrapBasedNullChecks && 8391 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne && 8392 _leaf->as_If ()->_prob >= PROB_LIKELY_MAG(4) && 8393 Matcher::branches_to_uncommon_trap(_leaf)); 8394 size(6); 8395 8396 ins_is_TrapBasedCheckNode(true); 8397 8398 format %{ "ZeroCheckN value=$value cmp=$cmp zero=$zero => trap $labl" %} 8399 ins_encode %{ __ z_cit($value$$Register, 0, $cmp$$cmpcode); %} 8400 ins_pipe(pipe_class_trap); 8401 %} 8402 8403 //----------Compare instructions----------------------------------------------- 8404 8405 // INT signed 8406 8407 // Compare Integers 8408 instruct compI_reg_reg(flagsReg cr, iRegI op1, iRegI op2) %{ 8409 match(Set cr (CmpI op1 op2)); 8410 size(2); 8411 format %{ "CR $op1,$op2" %} 8412 opcode(CR_ZOPC); 8413 ins_encode(z_rrform(op1, op2)); 8414 ins_pipe(pipe_class_dummy); 8415 %} 8416 8417 instruct compI_reg_imm(flagsReg cr, iRegI op1, immI op2) %{ 8418 match(Set cr (CmpI op1 op2)); 8419 size(6); 8420 format %{ "CFI $op1,$op2" %} 8421 opcode(CFI_ZOPC); 8422 ins_encode(z_rilform_signed(op1, op2)); 8423 ins_pipe(pipe_class_dummy); 8424 %} 8425 8426 instruct compI_reg_imm16(flagsReg cr, iRegI op1, immI16 op2) %{ 8427 match(Set cr (CmpI op1 op2)); 8428 size(4); 8429 format %{ "CHI $op1,$op2" %} 8430 opcode(CHI_ZOPC); 8431 ins_encode(z_riform_signed(op1, op2)); 8432 ins_pipe(pipe_class_dummy); 8433 %} 8434 8435 instruct compI_reg_imm0(flagsReg cr, iRegI op1, immI_0 zero) %{ 8436 match(Set cr (CmpI op1 zero)); 8437 ins_cost(DEFAULT_COST_LOW); 8438 size(2); 8439 format %{ "LTR $op1,$op1" %} 8440 opcode(LTR_ZOPC); 8441 ins_encode(z_rrform(op1, op1)); 8442 ins_pipe(pipe_class_dummy); 8443 %} 8444 8445 instruct compI_reg_mem(flagsReg cr, iRegI op1, memory op2)%{ 8446 match(Set cr (CmpI op1 (LoadI op2))); 8447 ins_cost(MEMORY_REF_COST); 8448 // TODO: s390 port size(VARIABLE_SIZE); 8449 format %{ "C(Y) $op1, $op2\t # int" %} 8450 opcode(CY_ZOPC, C_ZOPC); 8451 ins_encode(z_form_rt_mem_opt(op1, op2)); 8452 ins_pipe(pipe_class_dummy); 8453 %} 8454 8455 // INT unsigned 8456 8457 instruct compU_reg_reg(flagsReg cr, iRegI op1, iRegI op2) %{ 8458 match(Set cr (CmpU op1 op2)); 8459 size(2); 8460 format %{ "CLR $op1,$op2\t # unsigned" %} 8461 opcode(CLR_ZOPC); 8462 ins_encode(z_rrform(op1, op2)); 8463 ins_pipe(pipe_class_dummy); 8464 %} 8465 8466 instruct compU_reg_uimm(flagsReg cr, iRegI op1, uimmI op2) %{ 8467 match(Set cr (CmpU op1 op2)); 8468 size(6); 8469 format %{ "CLFI $op1,$op2\t # unsigned" %} 8470 opcode(CLFI_ZOPC); 8471 ins_encode(z_rilform_unsigned(op1, op2)); 8472 ins_pipe(pipe_class_dummy); 8473 %} 8474 8475 instruct compU_reg_mem(flagsReg cr, iRegI op1, memory op2)%{ 8476 match(Set cr (CmpU op1 (LoadI op2))); 8477 ins_cost(MEMORY_REF_COST); 8478 // TODO: s390 port size(VARIABLE_SIZE); 8479 format %{ "CL(Y) $op1, $op2\t # unsigned" %} 8480 opcode(CLY_ZOPC, CL_ZOPC); 8481 ins_encode(z_form_rt_mem_opt(op1, op2)); 8482 ins_pipe(pipe_class_dummy); 8483 %} 8484 8485 // LONG signed 8486 8487 instruct compL_reg_reg(flagsReg cr, iRegL op1, iRegL op2) %{ 8488 match(Set cr (CmpL op1 op2)); 8489 size(4); 8490 format %{ "CGR $op1,$op2\t # long" %} 8491 opcode(CGR_ZOPC); 8492 ins_encode(z_rreform(op1, op2)); 8493 ins_pipe(pipe_class_dummy); 8494 %} 8495 8496 instruct compL_reg_regI(flagsReg cr, iRegL op1, iRegI op2) %{ 8497 match(Set cr (CmpL op1 (ConvI2L op2))); 8498 size(4); 8499 format %{ "CGFR $op1,$op2\t # long/int" %} 8500 opcode(CGFR_ZOPC); 8501 ins_encode(z_rreform(op1, op2)); 8502 ins_pipe(pipe_class_dummy); 8503 %} 8504 8505 instruct compL_reg_imm32(flagsReg cr, iRegL op1, immL32 con) %{ 8506 match(Set cr (CmpL op1 con)); 8507 size(6); 8508 format %{ "CGFI $op1,$con" %} 8509 opcode(CGFI_ZOPC); 8510 ins_encode(z_rilform_signed(op1, con)); 8511 ins_pipe(pipe_class_dummy); 8512 %} 8513 8514 instruct compL_reg_imm16(flagsReg cr, iRegL op1, immL16 con) %{ 8515 match(Set cr (CmpL op1 con)); 8516 size(4); 8517 format %{ "CGHI $op1,$con" %} 8518 opcode(CGHI_ZOPC); 8519 ins_encode(z_riform_signed(op1, con)); 8520 ins_pipe(pipe_class_dummy); 8521 %} 8522 8523 instruct compL_reg_imm0(flagsReg cr, iRegL op1, immL_0 con) %{ 8524 match(Set cr (CmpL op1 con)); 8525 ins_cost(DEFAULT_COST_LOW); 8526 size(4); 8527 format %{ "LTGR $op1,$op1" %} 8528 opcode(LTGR_ZOPC); 8529 ins_encode(z_rreform(op1, op1)); 8530 ins_pipe(pipe_class_dummy); 8531 %} 8532 8533 instruct compL_conv_reg_imm0(flagsReg cr, iRegI op1, immL_0 con) %{ 8534 match(Set cr (CmpL (ConvI2L op1) con)); 8535 ins_cost(DEFAULT_COST_LOW); 8536 size(4); 8537 format %{ "LTGFR $op1,$op1" %} 8538 opcode(LTGFR_ZOPC); 8539 ins_encode(z_rreform(op1, op1)); 8540 ins_pipe(pipe_class_dummy); 8541 %} 8542 8543 instruct compL_reg_mem(iRegL dst, memory src, flagsReg cr)%{ 8544 match(Set cr (CmpL dst (LoadL src))); 8545 ins_cost(MEMORY_REF_COST); 8546 size(Z_DISP3_SIZE); 8547 format %{ "CG $dst, $src\t # long" %} 8548 opcode(CG_ZOPC, CG_ZOPC); 8549 ins_encode(z_form_rt_mem_opt(dst, src)); 8550 ins_pipe(pipe_class_dummy); 8551 %} 8552 8553 instruct compL_reg_memI(iRegL dst, memory src, flagsReg cr)%{ 8554 match(Set cr (CmpL dst (ConvI2L (LoadI src)))); 8555 ins_cost(MEMORY_REF_COST); 8556 size(Z_DISP3_SIZE); 8557 format %{ "CGF $dst, $src\t # long/int" %} 8558 opcode(CGF_ZOPC, CGF_ZOPC); 8559 ins_encode(z_form_rt_mem_opt(dst, src)); 8560 ins_pipe(pipe_class_dummy); 8561 %} 8562 8563 // LONG unsigned 8564 // Added CmpUL for LoopPredicate. 8565 instruct compUL_reg_reg(flagsReg cr, iRegL op1, iRegL op2) %{ 8566 match(Set cr (CmpUL op1 op2)); 8567 size(4); 8568 format %{ "CLGR $op1,$op2\t # long" %} 8569 opcode(CLGR_ZOPC); 8570 ins_encode(z_rreform(op1, op2)); 8571 ins_pipe(pipe_class_dummy); 8572 %} 8573 8574 instruct compUL_reg_imm32(flagsReg cr, iRegL op1, uimmL32 con) %{ 8575 match(Set cr (CmpUL op1 con)); 8576 size(6); 8577 format %{ "CLGFI $op1,$con" %} 8578 opcode(CLGFI_ZOPC); 8579 ins_encode(z_rilform_unsigned(op1, con)); 8580 ins_pipe(pipe_class_dummy); 8581 %} 8582 8583 // PTR unsigned 8584 8585 instruct compP_reg_reg(flagsReg cr, iRegP_N2P op1, iRegP_N2P op2) %{ 8586 match(Set cr (CmpP op1 op2)); 8587 size(4); 8588 format %{ "CLGR $op1,$op2\t # ptr" %} 8589 opcode(CLGR_ZOPC); 8590 ins_encode(z_rreform(op1, op2)); 8591 ins_pipe(pipe_class_dummy); 8592 %} 8593 8594 instruct compP_reg_imm0(flagsReg cr, iRegP_N2P op1, immP0 op2) %{ 8595 match(Set cr (CmpP op1 op2)); 8596 ins_cost(DEFAULT_COST_LOW); 8597 size(4); 8598 format %{ "LTGR $op1, $op1\t # ptr" %} 8599 opcode(LTGR_ZOPC); 8600 ins_encode(z_rreform(op1, op1)); 8601 ins_pipe(pipe_class_dummy); 8602 %} 8603 8604 // Don't use LTGFR which performs sign extend. 8605 instruct compP_decode_reg_imm0(flagsReg cr, iRegN op1, immP0 op2) %{ 8606 match(Set cr (CmpP (DecodeN op1) op2)); 8607 predicate(CompressedOops::base() == NULL && CompressedOops::shift() == 0); 8608 ins_cost(DEFAULT_COST_LOW); 8609 size(2); 8610 format %{ "LTR $op1, $op1\t # ptr" %} 8611 opcode(LTR_ZOPC); 8612 ins_encode(z_rrform(op1, op1)); 8613 ins_pipe(pipe_class_dummy); 8614 %} 8615 8616 instruct compP_reg_mem(iRegP dst, memory src, flagsReg cr)%{ 8617 match(Set cr (CmpP dst (LoadP src))); 8618 ins_cost(MEMORY_REF_COST); 8619 size(Z_DISP3_SIZE); 8620 format %{ "CLG $dst, $src\t # ptr" %} 8621 opcode(CLG_ZOPC, CLG_ZOPC); 8622 ins_encode(z_form_rt_mem_opt(dst, src)); 8623 ins_pipe(pipe_class_dummy); 8624 %} 8625 8626 //----------Max and Min-------------------------------------------------------- 8627 8628 // Max Register with Register 8629 instruct z196_minI_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{ 8630 match(Set dst (MinI src1 src2)); 8631 effect(KILL cr); 8632 predicate(VM_Version::has_LoadStoreConditional()); 8633 ins_cost(3 * DEFAULT_COST); 8634 // TODO: s390 port size(VARIABLE_SIZE); 8635 format %{ "MinI $dst $src1,$src2\t MinI (z196 only)" %} 8636 ins_encode %{ 8637 Register Rdst = $dst$$Register; 8638 Register Rsrc1 = $src1$$Register; 8639 Register Rsrc2 = $src2$$Register; 8640 8641 if (Rsrc1 == Rsrc2) { 8642 if (Rdst != Rsrc1) { 8643 __ z_lgfr(Rdst, Rsrc1); 8644 } 8645 } else if (Rdst == Rsrc1) { // Rdst preset with src1. 8646 __ z_cr(Rsrc1, Rsrc2); // Move src2 only if src1 is NotLow. 8647 __ z_locr(Rdst, Rsrc2, Assembler::bcondNotLow); 8648 } else if (Rdst == Rsrc2) { // Rdst preset with src2. 8649 __ z_cr(Rsrc2, Rsrc1); // Move src1 only if src2 is NotLow. 8650 __ z_locr(Rdst, Rsrc1, Assembler::bcondNotLow); 8651 } else { 8652 // Rdst is disjoint from operands, move in either case. 8653 __ z_cr(Rsrc1, Rsrc2); 8654 __ z_locr(Rdst, Rsrc2, Assembler::bcondNotLow); 8655 __ z_locr(Rdst, Rsrc1, Assembler::bcondLow); 8656 } 8657 %} 8658 ins_pipe(pipe_class_dummy); 8659 %} 8660 8661 // Min Register with Register. 8662 instruct z10_minI_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{ 8663 match(Set dst (MinI src1 src2)); 8664 effect(KILL cr); 8665 predicate(VM_Version::has_CompareBranch()); 8666 ins_cost(2 * DEFAULT_COST + BRANCH_COST); 8667 // TODO: s390 port size(VARIABLE_SIZE); 8668 format %{ "MinI $dst $src1,$src2\t MinI (z10 only)" %} 8669 ins_encode %{ 8670 Register Rdst = $dst$$Register; 8671 Register Rsrc1 = $src1$$Register; 8672 Register Rsrc2 = $src2$$Register; 8673 Label done; 8674 8675 if (Rsrc1 == Rsrc2) { 8676 if (Rdst != Rsrc1) { 8677 __ z_lgfr(Rdst, Rsrc1); 8678 } 8679 } else if (Rdst == Rsrc1) { 8680 __ z_crj(Rsrc1, Rsrc2, Assembler::bcondLow, done); 8681 __ z_lgfr(Rdst, Rsrc2); 8682 } else if (Rdst == Rsrc2) { 8683 __ z_crj(Rsrc2, Rsrc1, Assembler::bcondLow, done); 8684 __ z_lgfr(Rdst, Rsrc1); 8685 } else { 8686 __ z_lgfr(Rdst, Rsrc1); 8687 __ z_crj(Rsrc1, Rsrc2, Assembler::bcondLow, done); 8688 __ z_lgfr(Rdst, Rsrc2); 8689 } 8690 __ bind(done); 8691 %} 8692 ins_pipe(pipe_class_dummy); 8693 %} 8694 8695 instruct minI_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{ 8696 match(Set dst (MinI src1 src2)); 8697 effect(KILL cr); 8698 predicate(!VM_Version::has_CompareBranch()); 8699 ins_cost(3 * DEFAULT_COST + BRANCH_COST); 8700 // TODO: s390 port size(VARIABLE_SIZE); 8701 format %{ "MinI $dst $src1,$src2\t MinI" %} 8702 ins_encode %{ 8703 Register Rdst = $dst$$Register; 8704 Register Rsrc1 = $src1$$Register; 8705 Register Rsrc2 = $src2$$Register; 8706 Label done; 8707 8708 if (Rsrc1 == Rsrc2) { 8709 if (Rdst != Rsrc1) { 8710 __ z_lgfr(Rdst, Rsrc1); 8711 } 8712 } else if (Rdst == Rsrc1) { 8713 __ z_cr(Rsrc1, Rsrc2); 8714 __ z_brl(done); 8715 __ z_lgfr(Rdst, Rsrc2); 8716 } else if (Rdst == Rsrc2) { 8717 __ z_cr(Rsrc2, Rsrc1); 8718 __ z_brl(done); 8719 __ z_lgfr(Rdst, Rsrc1); 8720 } else { 8721 __ z_lgfr(Rdst, Rsrc1); 8722 __ z_cr(Rsrc1, Rsrc2); 8723 __ z_brl(done); 8724 __ z_lgfr(Rdst, Rsrc2); 8725 } 8726 __ bind(done); 8727 %} 8728 ins_pipe(pipe_class_dummy); 8729 %} 8730 8731 instruct z196_minI_reg_imm32(iRegI dst, iRegI src1, immI src2, flagsReg cr) %{ 8732 match(Set dst (MinI src1 src2)); 8733 effect(KILL cr); 8734 predicate(VM_Version::has_LoadStoreConditional()); 8735 ins_cost(3 * DEFAULT_COST); 8736 // TODO: s390 port size(VARIABLE_SIZE); 8737 format %{ "MinI $dst $src1,$src2\t MinI const32 (z196 only)" %} 8738 ins_encode %{ 8739 Register Rdst = $dst$$Register; 8740 Register Rsrc1 = $src1$$Register; 8741 int Isrc2 = $src2$$constant; 8742 8743 if (Rdst == Rsrc1) { 8744 __ load_const_optimized(Z_R0_scratch, Isrc2); 8745 __ z_cfi(Rsrc1, Isrc2); 8746 __ z_locr(Rdst, Z_R0_scratch, Assembler::bcondNotLow); 8747 } else { 8748 __ load_const_optimized(Rdst, Isrc2); 8749 __ z_cfi(Rsrc1, Isrc2); 8750 __ z_locr(Rdst, Rsrc1, Assembler::bcondLow); 8751 } 8752 %} 8753 ins_pipe(pipe_class_dummy); 8754 %} 8755 8756 instruct minI_reg_imm32(iRegI dst, iRegI src1, immI src2, flagsReg cr) %{ 8757 match(Set dst (MinI src1 src2)); 8758 effect(KILL cr); 8759 ins_cost(2 * DEFAULT_COST + BRANCH_COST); 8760 // TODO: s390 port size(VARIABLE_SIZE); 8761 format %{ "MinI $dst $src1,$src2\t MinI const32" %} 8762 ins_encode %{ 8763 Label done; 8764 if ($dst$$Register != $src1$$Register) { 8765 __ z_lgfr($dst$$Register, $src1$$Register); 8766 } 8767 __ z_cfi($src1$$Register, $src2$$constant); 8768 __ z_brl(done); 8769 __ z_lgfi($dst$$Register, $src2$$constant); 8770 __ bind(done); 8771 %} 8772 ins_pipe(pipe_class_dummy); 8773 %} 8774 8775 instruct z196_minI_reg_imm16(iRegI dst, iRegI src1, immI16 src2, flagsReg cr) %{ 8776 match(Set dst (MinI src1 src2)); 8777 effect(KILL cr); 8778 predicate(VM_Version::has_LoadStoreConditional()); 8779 ins_cost(3 * DEFAULT_COST); 8780 // TODO: s390 port size(VARIABLE_SIZE); 8781 format %{ "MinI $dst $src1,$src2\t MinI const16 (z196 only)" %} 8782 ins_encode %{ 8783 Register Rdst = $dst$$Register; 8784 Register Rsrc1 = $src1$$Register; 8785 int Isrc2 = $src2$$constant; 8786 8787 if (Rdst == Rsrc1) { 8788 __ load_const_optimized(Z_R0_scratch, Isrc2); 8789 __ z_chi(Rsrc1, Isrc2); 8790 __ z_locr(Rdst, Z_R0_scratch, Assembler::bcondNotLow); 8791 } else { 8792 __ load_const_optimized(Rdst, Isrc2); 8793 __ z_chi(Rsrc1, Isrc2); 8794 __ z_locr(Rdst, Rsrc1, Assembler::bcondLow); 8795 } 8796 %} 8797 ins_pipe(pipe_class_dummy); 8798 %} 8799 8800 instruct minI_reg_imm16(iRegI dst, iRegI src1, immI16 src2, flagsReg cr) %{ 8801 match(Set dst (MinI src1 src2)); 8802 effect(KILL cr); 8803 ins_cost(2 * DEFAULT_COST + BRANCH_COST); 8804 // TODO: s390 port size(VARIABLE_SIZE); 8805 format %{ "MinI $dst $src1,$src2\t MinI const16" %} 8806 ins_encode %{ 8807 Label done; 8808 if ($dst$$Register != $src1$$Register) { 8809 __ z_lgfr($dst$$Register, $src1$$Register); 8810 } 8811 __ z_chi($src1$$Register, $src2$$constant); 8812 __ z_brl(done); 8813 __ z_lghi($dst$$Register, $src2$$constant); 8814 __ bind(done); 8815 %} 8816 ins_pipe(pipe_class_dummy); 8817 %} 8818 8819 instruct z10_minI_reg_imm8(iRegI dst, iRegI src1, immI8 src2, flagsReg cr) %{ 8820 match(Set dst (MinI src1 src2)); 8821 effect(KILL cr); 8822 predicate(VM_Version::has_CompareBranch()); 8823 ins_cost(DEFAULT_COST + BRANCH_COST); 8824 // TODO: s390 port size(VARIABLE_SIZE); 8825 format %{ "MinI $dst $src1,$src2\t MinI const8 (z10 only)" %} 8826 ins_encode %{ 8827 Label done; 8828 if ($dst$$Register != $src1$$Register) { 8829 __ z_lgfr($dst$$Register, $src1$$Register); 8830 } 8831 __ z_cij($src1$$Register, $src2$$constant, Assembler::bcondLow, done); 8832 __ z_lghi($dst$$Register, $src2$$constant); 8833 __ bind(done); 8834 %} 8835 ins_pipe(pipe_class_dummy); 8836 %} 8837 8838 // Max Register with Register 8839 instruct z196_maxI_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{ 8840 match(Set dst (MaxI src1 src2)); 8841 effect(KILL cr); 8842 predicate(VM_Version::has_LoadStoreConditional()); 8843 ins_cost(3 * DEFAULT_COST); 8844 // TODO: s390 port size(VARIABLE_SIZE); 8845 format %{ "MaxI $dst $src1,$src2\t MaxI (z196 only)" %} 8846 ins_encode %{ 8847 Register Rdst = $dst$$Register; 8848 Register Rsrc1 = $src1$$Register; 8849 Register Rsrc2 = $src2$$Register; 8850 8851 if (Rsrc1 == Rsrc2) { 8852 if (Rdst != Rsrc1) { 8853 __ z_lgfr(Rdst, Rsrc1); 8854 } 8855 } else if (Rdst == Rsrc1) { // Rdst preset with src1. 8856 __ z_cr(Rsrc1, Rsrc2); // Move src2 only if src1 is NotHigh. 8857 __ z_locr(Rdst, Rsrc2, Assembler::bcondNotHigh); 8858 } else if (Rdst == Rsrc2) { // Rdst preset with src2. 8859 __ z_cr(Rsrc2, Rsrc1); // Move src1 only if src2 is NotHigh. 8860 __ z_locr(Rdst, Rsrc1, Assembler::bcondNotHigh); 8861 } else { // Rdst is disjoint from operands, move in either case. 8862 __ z_cr(Rsrc1, Rsrc2); 8863 __ z_locr(Rdst, Rsrc2, Assembler::bcondNotHigh); 8864 __ z_locr(Rdst, Rsrc1, Assembler::bcondHigh); 8865 } 8866 %} 8867 ins_pipe(pipe_class_dummy); 8868 %} 8869 8870 // Max Register with Register 8871 instruct z10_maxI_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{ 8872 match(Set dst (MaxI src1 src2)); 8873 effect(KILL cr); 8874 predicate(VM_Version::has_CompareBranch()); 8875 ins_cost(2 * DEFAULT_COST + BRANCH_COST); 8876 // TODO: s390 port size(VARIABLE_SIZE); 8877 format %{ "MaxI $dst $src1,$src2\t MaxI (z10 only)" %} 8878 ins_encode %{ 8879 Register Rdst = $dst$$Register; 8880 Register Rsrc1 = $src1$$Register; 8881 Register Rsrc2 = $src2$$Register; 8882 Label done; 8883 8884 if (Rsrc1 == Rsrc2) { 8885 if (Rdst != Rsrc1) { 8886 __ z_lgfr(Rdst, Rsrc1); 8887 } 8888 } else if (Rdst == Rsrc1) { 8889 __ z_crj(Rsrc1, Rsrc2, Assembler::bcondHigh, done); 8890 __ z_lgfr(Rdst, Rsrc2); 8891 } else if (Rdst == Rsrc2) { 8892 __ z_crj(Rsrc2, Rsrc1, Assembler::bcondHigh, done); 8893 __ z_lgfr(Rdst, Rsrc1); 8894 } else { 8895 __ z_lgfr(Rdst, Rsrc1); 8896 __ z_crj(Rsrc1, Rsrc2, Assembler::bcondHigh, done); 8897 __ z_lgfr(Rdst, Rsrc2); 8898 } 8899 __ bind(done); 8900 %} 8901 ins_pipe(pipe_class_dummy); 8902 %} 8903 8904 instruct maxI_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{ 8905 match(Set dst (MaxI src1 src2)); 8906 effect(KILL cr); 8907 predicate(!VM_Version::has_CompareBranch()); 8908 ins_cost(3 * DEFAULT_COST + BRANCH_COST); 8909 // TODO: s390 port size(VARIABLE_SIZE); 8910 format %{ "MaxI $dst $src1,$src2\t MaxI" %} 8911 ins_encode %{ 8912 Register Rdst = $dst$$Register; 8913 Register Rsrc1 = $src1$$Register; 8914 Register Rsrc2 = $src2$$Register; 8915 Label done; 8916 8917 if (Rsrc1 == Rsrc2) { 8918 if (Rdst != Rsrc1) { 8919 __ z_lgfr(Rdst, Rsrc1); 8920 } 8921 } else if (Rdst == Rsrc1) { 8922 __ z_cr(Rsrc1, Rsrc2); 8923 __ z_brh(done); 8924 __ z_lgfr(Rdst, Rsrc2); 8925 } else if (Rdst == Rsrc2) { 8926 __ z_cr(Rsrc2, Rsrc1); 8927 __ z_brh(done); 8928 __ z_lgfr(Rdst, Rsrc1); 8929 } else { 8930 __ z_lgfr(Rdst, Rsrc1); 8931 __ z_cr(Rsrc1, Rsrc2); 8932 __ z_brh(done); 8933 __ z_lgfr(Rdst, Rsrc2); 8934 } 8935 8936 __ bind(done); 8937 %} 8938 8939 ins_pipe(pipe_class_dummy); 8940 %} 8941 8942 instruct z196_maxI_reg_imm32(iRegI dst, iRegI src1, immI src2, flagsReg cr) %{ 8943 match(Set dst (MaxI src1 src2)); 8944 effect(KILL cr); 8945 predicate(VM_Version::has_LoadStoreConditional()); 8946 ins_cost(3 * DEFAULT_COST); 8947 // TODO: s390 port size(VARIABLE_SIZE); 8948 format %{ "MaxI $dst $src1,$src2\t MaxI const32 (z196 only)" %} 8949 ins_encode %{ 8950 Register Rdst = $dst$$Register; 8951 Register Rsrc1 = $src1$$Register; 8952 int Isrc2 = $src2$$constant; 8953 8954 if (Rdst == Rsrc1) { 8955 __ load_const_optimized(Z_R0_scratch, Isrc2); 8956 __ z_cfi(Rsrc1, Isrc2); 8957 __ z_locr(Rdst, Z_R0_scratch, Assembler::bcondNotHigh); 8958 } else { 8959 __ load_const_optimized(Rdst, Isrc2); 8960 __ z_cfi(Rsrc1, Isrc2); 8961 __ z_locr(Rdst, Rsrc1, Assembler::bcondHigh); 8962 } 8963 %} 8964 ins_pipe(pipe_class_dummy); 8965 %} 8966 8967 instruct maxI_reg_imm32(iRegI dst, iRegI src1, immI src2, flagsReg cr) %{ 8968 match(Set dst (MaxI src1 src2)); 8969 effect(KILL cr); 8970 ins_cost(2 * DEFAULT_COST + BRANCH_COST); 8971 // TODO: s390 port size(VARIABLE_SIZE); 8972 format %{ "MaxI $dst $src1,$src2\t MaxI const32" %} 8973 ins_encode %{ 8974 Label done; 8975 if ($dst$$Register != $src1$$Register) { 8976 __ z_lgfr($dst$$Register, $src1$$Register); 8977 } 8978 __ z_cfi($src1$$Register, $src2$$constant); 8979 __ z_brh(done); 8980 __ z_lgfi($dst$$Register, $src2$$constant); 8981 __ bind(done); 8982 %} 8983 ins_pipe(pipe_class_dummy); 8984 %} 8985 8986 instruct z196_maxI_reg_imm16(iRegI dst, iRegI src1, immI16 src2, flagsReg cr) %{ 8987 match(Set dst (MaxI src1 src2)); 8988 effect(KILL cr); 8989 predicate(VM_Version::has_LoadStoreConditional()); 8990 ins_cost(3 * DEFAULT_COST); 8991 // TODO: s390 port size(VARIABLE_SIZE); 8992 format %{ "MaxI $dst $src1,$src2\t MaxI const16 (z196 only)" %} 8993 ins_encode %{ 8994 Register Rdst = $dst$$Register; 8995 Register Rsrc1 = $src1$$Register; 8996 int Isrc2 = $src2$$constant; 8997 if (Rdst == Rsrc1) { 8998 __ load_const_optimized(Z_R0_scratch, Isrc2); 8999 __ z_chi(Rsrc1, Isrc2); 9000 __ z_locr(Rdst, Z_R0_scratch, Assembler::bcondNotHigh); 9001 } else { 9002 __ load_const_optimized(Rdst, Isrc2); 9003 __ z_chi(Rsrc1, Isrc2); 9004 __ z_locr(Rdst, Rsrc1, Assembler::bcondHigh); 9005 } 9006 %} 9007 ins_pipe(pipe_class_dummy); 9008 %} 9009 9010 instruct maxI_reg_imm16(iRegI dst, iRegI src1, immI16 src2, flagsReg cr) %{ 9011 match(Set dst (MaxI src1 src2)); 9012 effect(KILL cr); 9013 ins_cost(2 * DEFAULT_COST + BRANCH_COST); 9014 // TODO: s390 port size(VARIABLE_SIZE); 9015 format %{ "MaxI $dst $src1,$src2\t MaxI const16" %} 9016 ins_encode %{ 9017 Label done; 9018 if ($dst$$Register != $src1$$Register) { 9019 __ z_lgfr($dst$$Register, $src1$$Register); 9020 } 9021 __ z_chi($src1$$Register, $src2$$constant); 9022 __ z_brh(done); 9023 __ z_lghi($dst$$Register, $src2$$constant); 9024 __ bind(done); 9025 %} 9026 ins_pipe(pipe_class_dummy); 9027 %} 9028 9029 instruct z10_maxI_reg_imm8(iRegI dst, iRegI src1, immI8 src2, flagsReg cr) %{ 9030 match(Set dst (MaxI src1 src2)); 9031 effect(KILL cr); 9032 predicate(VM_Version::has_CompareBranch()); 9033 ins_cost(DEFAULT_COST + BRANCH_COST); 9034 // TODO: s390 port size(VARIABLE_SIZE); 9035 format %{ "MaxI $dst $src1,$src2\t MaxI const8" %} 9036 ins_encode %{ 9037 Label done; 9038 if ($dst$$Register != $src1$$Register) { 9039 __ z_lgfr($dst$$Register, $src1$$Register); 9040 } 9041 __ z_cij($src1$$Register, $src2$$constant, Assembler::bcondHigh, done); 9042 __ z_lghi($dst$$Register, $src2$$constant); 9043 __ bind(done); 9044 %} 9045 ins_pipe(pipe_class_dummy); 9046 %} 9047 9048 //----------Abs--------------------------------------------------------------- 9049 9050 instruct absI_reg(iRegI dst, iRegI src, flagsReg cr) %{ 9051 match(Set dst (AbsI src)); 9052 effect(KILL cr); 9053 ins_cost(DEFAULT_COST_LOW); 9054 // TODO: s390 port size(FIXED_SIZE); 9055 format %{ "LPR $dst, $src" %} 9056 opcode(LPR_ZOPC); 9057 ins_encode(z_rrform(dst, src)); 9058 ins_pipe(pipe_class_dummy); 9059 %} 9060 9061 instruct absL_reg(iRegL dst, iRegL src, flagsReg cr) %{ 9062 match(Set dst (AbsL src)); 9063 effect(KILL cr); 9064 ins_cost(DEFAULT_COST_LOW); 9065 // TODO: s390 port size(FIXED_SIZE); 9066 format %{ "LPGR $dst, $src" %} 9067 opcode(LPGR_ZOPC); 9068 ins_encode(z_rreform(dst, src)); 9069 ins_pipe(pipe_class_dummy); 9070 %} 9071 9072 instruct negabsI_reg(iRegI dst, iRegI src, immI_0 zero, flagsReg cr) %{ 9073 match(Set dst (SubI zero (AbsI src))); 9074 effect(KILL cr); 9075 ins_cost(DEFAULT_COST_LOW); 9076 // TODO: s390 port size(FIXED_SIZE); 9077 format %{ "LNR $dst, $src" %} 9078 opcode(LNR_ZOPC); 9079 ins_encode(z_rrform(dst, src)); 9080 ins_pipe(pipe_class_dummy); 9081 %} 9082 9083 //----------Float Compares---------------------------------------------------- 9084 9085 // Compare floating, generate condition code. 9086 instruct cmpF_cc(flagsReg cr, regF src1, regF src2) %{ 9087 match(Set cr (CmpF src1 src2)); 9088 ins_cost(ALU_REG_COST); 9089 size(4); 9090 format %{ "FCMPcc $src1,$src2\t # float" %} 9091 ins_encode %{ __ z_cebr($src1$$FloatRegister, $src2$$FloatRegister); %} 9092 ins_pipe(pipe_class_dummy); 9093 %} 9094 9095 instruct cmpD_cc(flagsReg cr, regD src1, regD src2) %{ 9096 match(Set cr (CmpD src1 src2)); 9097 ins_cost(ALU_REG_COST); 9098 size(4); 9099 format %{ "FCMPcc $src1,$src2 \t # double" %} 9100 ins_encode %{ __ z_cdbr($src1$$FloatRegister, $src2$$FloatRegister); %} 9101 ins_pipe(pipe_class_dummy); 9102 %} 9103 9104 instruct cmpF_cc_mem(flagsReg cr, regF src1, memoryRX src2) %{ 9105 match(Set cr (CmpF src1 (LoadF src2))); 9106 ins_cost(ALU_MEMORY_COST); 9107 size(6); 9108 format %{ "FCMPcc_mem $src1,$src2\t # floatMemory" %} 9109 opcode(CEB_ZOPC); 9110 ins_encode(z_form_rt_memFP(src1, src2)); 9111 ins_pipe(pipe_class_dummy); 9112 %} 9113 9114 instruct cmpD_cc_mem(flagsReg cr, regD src1, memoryRX src2) %{ 9115 match(Set cr (CmpD src1 (LoadD src2))); 9116 ins_cost(ALU_MEMORY_COST); 9117 size(6); 9118 format %{ "DCMPcc_mem $src1,$src2\t # doubleMemory" %} 9119 opcode(CDB_ZOPC); 9120 ins_encode(z_form_rt_memFP(src1, src2)); 9121 ins_pipe(pipe_class_dummy); 9122 %} 9123 9124 // Compare floating, generate condition code 9125 instruct cmpF0_cc(flagsReg cr, regF src1, immFpm0 src2) %{ 9126 match(Set cr (CmpF src1 src2)); 9127 ins_cost(DEFAULT_COST); 9128 size(4); 9129 format %{ "LTEBR $src1,$src1\t # float" %} 9130 opcode(LTEBR_ZOPC); 9131 ins_encode(z_rreform(src1, src1)); 9132 ins_pipe(pipe_class_dummy); 9133 %} 9134 9135 instruct cmpD0_cc(flagsReg cr, regD src1, immDpm0 src2) %{ 9136 match(Set cr (CmpD src1 src2)); 9137 ins_cost(DEFAULT_COST); 9138 size(4); 9139 format %{ "LTDBR $src1,$src1 \t # double" %} 9140 opcode(LTDBR_ZOPC); 9141 ins_encode(z_rreform(src1, src1)); 9142 ins_pipe(pipe_class_dummy); 9143 %} 9144 9145 // Compare floating, generate -1,0,1 9146 instruct cmpF_reg(iRegI dst, regF src1, regF src2, flagsReg cr) %{ 9147 match(Set dst (CmpF3 src1 src2)); 9148 effect(KILL cr); 9149 ins_cost(DEFAULT_COST * 5 + BRANCH_COST); 9150 size(24); 9151 format %{ "CmpF3 $dst,$src1,$src2" %} 9152 ins_encode %{ 9153 // compare registers 9154 __ z_cebr($src1$$FloatRegister, $src2$$FloatRegister); 9155 // Convert condition code into -1,0,1, where 9156 // -1 means unordered or less 9157 // 0 means equal 9158 // 1 means greater. 9159 if (VM_Version::has_LoadStoreConditional()) { 9160 Register one = Z_R0_scratch; 9161 Register minus_one = Z_R1_scratch; 9162 __ z_lghi(minus_one, -1); 9163 __ z_lghi(one, 1); 9164 __ z_lghi( $dst$$Register, 0); 9165 __ z_locgr($dst$$Register, one, Assembler::bcondHigh); 9166 __ z_locgr($dst$$Register, minus_one, Assembler::bcondLowOrNotOrdered); 9167 } else { 9168 Label done; 9169 __ clear_reg($dst$$Register, true, false); 9170 __ z_bre(done); 9171 __ z_lhi($dst$$Register, 1); 9172 __ z_brh(done); 9173 __ z_lhi($dst$$Register, -1); 9174 __ bind(done); 9175 } 9176 %} 9177 ins_pipe(pipe_class_dummy); 9178 %} 9179 9180 instruct cmpD_reg(iRegI dst, regD src1, regD src2, flagsReg cr) %{ 9181 match(Set dst (CmpD3 src1 src2)); 9182 effect(KILL cr); 9183 ins_cost(DEFAULT_COST * 5 + BRANCH_COST); 9184 size(24); 9185 format %{ "CmpD3 $dst,$src1,$src2" %} 9186 ins_encode %{ 9187 // compare registers 9188 __ z_cdbr($src1$$FloatRegister, $src2$$FloatRegister); 9189 // Convert condition code into -1,0,1, where 9190 // -1 means unordered or less 9191 // 0 means equal 9192 // 1 means greater. 9193 if (VM_Version::has_LoadStoreConditional()) { 9194 Register one = Z_R0_scratch; 9195 Register minus_one = Z_R1_scratch; 9196 __ z_lghi(minus_one, -1); 9197 __ z_lghi(one, 1); 9198 __ z_lghi( $dst$$Register, 0); 9199 __ z_locgr($dst$$Register, one, Assembler::bcondHigh); 9200 __ z_locgr($dst$$Register, minus_one, Assembler::bcondLowOrNotOrdered); 9201 } else { 9202 Label done; 9203 // indicate unused result 9204 (void) __ clear_reg($dst$$Register, true, false); 9205 __ z_bre(done); 9206 __ z_lhi($dst$$Register, 1); 9207 __ z_brh(done); 9208 __ z_lhi($dst$$Register, -1); 9209 __ bind(done); 9210 } 9211 %} 9212 ins_pipe(pipe_class_dummy); 9213 %} 9214 9215 //----------Branches--------------------------------------------------------- 9216 // Jump 9217 9218 // Direct Branch. 9219 instruct branch(label labl) %{ 9220 match(Goto); 9221 effect(USE labl); 9222 ins_cost(BRANCH_COST); 9223 size(4); 9224 format %{ "BRU $labl" %} 9225 ins_encode(z_enc_bru(labl)); 9226 ins_pipe(pipe_class_dummy); 9227 // If set to 1 this indicates that the current instruction is a 9228 // short variant of a long branch. This avoids using this 9229 // instruction in first-pass matching. It will then only be used in 9230 // the `Shorten_branches' pass. 9231 ins_short_branch(1); 9232 %} 9233 9234 // Direct Branch. 9235 instruct branchFar(label labl) %{ 9236 match(Goto); 9237 effect(USE labl); 9238 ins_cost(BRANCH_COST); 9239 size(6); 9240 format %{ "BRUL $labl" %} 9241 ins_encode(z_enc_brul(labl)); 9242 ins_pipe(pipe_class_dummy); 9243 // This is not a short variant of a branch, but the long variant. 9244 ins_short_branch(0); 9245 %} 9246 9247 // Conditional Near Branch 9248 instruct branchCon(cmpOp cmp, flagsReg cr, label lbl) %{ 9249 // Same match rule as `branchConFar'. 9250 match(If cmp cr); 9251 effect(USE lbl); 9252 ins_cost(BRANCH_COST); 9253 size(4); 9254 format %{ "branch_con_short,$cmp $lbl" %} 9255 ins_encode(z_enc_branch_con_short(cmp, lbl)); 9256 ins_pipe(pipe_class_dummy); 9257 // If set to 1 this indicates that the current instruction is a 9258 // short variant of a long branch. This avoids using this 9259 // instruction in first-pass matching. It will then only be used in 9260 // the `Shorten_branches' pass. 9261 ins_short_branch(1); 9262 %} 9263 9264 // This is for cases when the z/Architecture conditional branch instruction 9265 // does not reach far enough. So we emit a far branch here, which is 9266 // more expensive. 9267 // 9268 // Conditional Far Branch 9269 instruct branchConFar(cmpOp cmp, flagsReg cr, label lbl) %{ 9270 // Same match rule as `branchCon'. 9271 match(If cmp cr); 9272 effect(USE cr, USE lbl); 9273 // Make more expensive to prefer compare_and_branch over separate instructions. 9274 ins_cost(2 * BRANCH_COST); 9275 size(6); 9276 format %{ "branch_con_far,$cmp $lbl" %} 9277 ins_encode(z_enc_branch_con_far(cmp, lbl)); 9278 ins_pipe(pipe_class_dummy); 9279 // This is not a short variant of a branch, but the long variant.. 9280 ins_short_branch(0); 9281 %} 9282 9283 instruct branchLoopEnd(cmpOp cmp, flagsReg cr, label labl) %{ 9284 match(CountedLoopEnd cmp cr); 9285 effect(USE labl); 9286 ins_cost(BRANCH_COST); 9287 size(4); 9288 format %{ "branch_con_short,$cmp $labl\t # counted loop end" %} 9289 ins_encode(z_enc_branch_con_short(cmp, labl)); 9290 ins_pipe(pipe_class_dummy); 9291 // If set to 1 this indicates that the current instruction is a 9292 // short variant of a long branch. This avoids using this 9293 // instruction in first-pass matching. It will then only be used in 9294 // the `Shorten_branches' pass. 9295 ins_short_branch(1); 9296 %} 9297 9298 instruct branchLoopEndFar(cmpOp cmp, flagsReg cr, label labl) %{ 9299 match(CountedLoopEnd cmp cr); 9300 effect(USE labl); 9301 ins_cost(BRANCH_COST); 9302 size(6); 9303 format %{ "branch_con_far,$cmp $labl\t # counted loop end" %} 9304 ins_encode(z_enc_branch_con_far(cmp, labl)); 9305 ins_pipe(pipe_class_dummy); 9306 // This is not a short variant of a branch, but the long variant. 9307 ins_short_branch(0); 9308 %} 9309 9310 //----------Compare and Branch (short distance)------------------------------ 9311 9312 // INT REG operands for loop counter processing. 9313 instruct testAndBranchLoopEnd_Reg(cmpOpT boolnode, iRegI src1, iRegI src2, label labl, flagsReg cr) %{ 9314 match(CountedLoopEnd boolnode (CmpI src1 src2)); 9315 effect(USE labl, KILL cr); 9316 predicate(VM_Version::has_CompareBranch()); 9317 ins_cost(BRANCH_COST); 9318 // TODO: s390 port size(FIXED_SIZE); 9319 format %{ "test_and_branch_loop_end,$boolnode $src1,$src2,$labl\t # counted loop end SHORT" %} 9320 opcode(CRJ_ZOPC); 9321 ins_encode(z_enc_cmpb_regreg(src1, src2, labl, boolnode)); 9322 ins_pipe(pipe_class_dummy); 9323 ins_short_branch(1); 9324 %} 9325 9326 // INT REG operands. 9327 instruct cmpb_RegI(cmpOpT boolnode, iRegI src1, iRegI src2, label labl, flagsReg cr) %{ 9328 match(If boolnode (CmpI src1 src2)); 9329 effect(USE labl, KILL cr); 9330 predicate(VM_Version::has_CompareBranch()); 9331 ins_cost(BRANCH_COST); 9332 // TODO: s390 port size(FIXED_SIZE); 9333 format %{ "CRJ,$boolnode $src1,$src2,$labl\t # SHORT" %} 9334 opcode(CRJ_ZOPC); 9335 ins_encode(z_enc_cmpb_regreg(src1, src2, labl, boolnode)); 9336 ins_pipe(pipe_class_dummy); 9337 ins_short_branch(1); 9338 %} 9339 9340 // Unsigned INT REG operands 9341 instruct cmpbU_RegI(cmpOpT boolnode, iRegI src1, iRegI src2, label labl, flagsReg cr) %{ 9342 match(If boolnode (CmpU src1 src2)); 9343 effect(USE labl, KILL cr); 9344 predicate(VM_Version::has_CompareBranch()); 9345 ins_cost(BRANCH_COST); 9346 // TODO: s390 port size(FIXED_SIZE); 9347 format %{ "CLRJ,$boolnode $src1,$src2,$labl\t # SHORT" %} 9348 opcode(CLRJ_ZOPC); 9349 ins_encode(z_enc_cmpb_regreg(src1, src2, labl, boolnode)); 9350 ins_pipe(pipe_class_dummy); 9351 ins_short_branch(1); 9352 %} 9353 9354 // LONG REG operands 9355 instruct cmpb_RegL(cmpOpT boolnode, iRegL src1, iRegL src2, label labl, flagsReg cr) %{ 9356 match(If boolnode (CmpL src1 src2)); 9357 effect(USE labl, KILL cr); 9358 predicate(VM_Version::has_CompareBranch()); 9359 ins_cost(BRANCH_COST); 9360 // TODO: s390 port size(FIXED_SIZE); 9361 format %{ "CGRJ,$boolnode $src1,$src2,$labl\t # SHORT" %} 9362 opcode(CGRJ_ZOPC); 9363 ins_encode(z_enc_cmpb_regreg(src1, src2, labl, boolnode)); 9364 ins_pipe(pipe_class_dummy); 9365 ins_short_branch(1); 9366 %} 9367 9368 // PTR REG operands 9369 9370 // Separate rules for regular and narrow oops. ADLC can't recognize 9371 // rules with polymorphic operands to be sisters -> shorten_branches 9372 // will not shorten. 9373 9374 instruct cmpb_RegPP(cmpOpT boolnode, iRegP src1, iRegP src2, label labl, flagsReg cr) %{ 9375 match(If boolnode (CmpP src1 src2)); 9376 effect(USE labl, KILL cr); 9377 predicate(VM_Version::has_CompareBranch()); 9378 ins_cost(BRANCH_COST); 9379 // TODO: s390 port size(FIXED_SIZE); 9380 format %{ "CLGRJ,$boolnode $src1,$src2,$labl\t # SHORT" %} 9381 opcode(CLGRJ_ZOPC); 9382 ins_encode(z_enc_cmpb_regreg(src1, src2, labl, boolnode)); 9383 ins_pipe(pipe_class_dummy); 9384 ins_short_branch(1); 9385 %} 9386 9387 instruct cmpb_RegNN(cmpOpT boolnode, iRegN src1, iRegN src2, label labl, flagsReg cr) %{ 9388 match(If boolnode (CmpP (DecodeN src1) (DecodeN src2))); 9389 effect(USE labl, KILL cr); 9390 predicate(VM_Version::has_CompareBranch()); 9391 ins_cost(BRANCH_COST); 9392 // TODO: s390 port size(FIXED_SIZE); 9393 format %{ "CLGRJ,$boolnode $src1,$src2,$labl\t # SHORT" %} 9394 opcode(CLGRJ_ZOPC); 9395 ins_encode(z_enc_cmpb_regreg(src1, src2, labl, boolnode)); 9396 ins_pipe(pipe_class_dummy); 9397 ins_short_branch(1); 9398 %} 9399 9400 // INT REG/IMM operands for loop counter processing 9401 instruct testAndBranchLoopEnd_Imm(cmpOpT boolnode, iRegI src1, immI8 src2, label labl, flagsReg cr) %{ 9402 match(CountedLoopEnd boolnode (CmpI src1 src2)); 9403 effect(USE labl, KILL cr); 9404 predicate(VM_Version::has_CompareBranch()); 9405 ins_cost(BRANCH_COST); 9406 // TODO: s390 port size(FIXED_SIZE); 9407 format %{ "test_and_branch_loop_end,$boolnode $src1,$src2,$labl\t # counted loop end SHORT" %} 9408 opcode(CIJ_ZOPC); 9409 ins_encode(z_enc_cmpb_regimm(src1, src2, labl, boolnode)); 9410 ins_pipe(pipe_class_dummy); 9411 ins_short_branch(1); 9412 %} 9413 9414 // INT REG/IMM operands 9415 instruct cmpb_RegI_imm(cmpOpT boolnode, iRegI src1, immI8 src2, label labl, flagsReg cr) %{ 9416 match(If boolnode (CmpI src1 src2)); 9417 effect(USE labl, KILL cr); 9418 predicate(VM_Version::has_CompareBranch()); 9419 ins_cost(BRANCH_COST); 9420 // TODO: s390 port size(FIXED_SIZE); 9421 format %{ "CIJ,$boolnode $src1,$src2,$labl\t # SHORT" %} 9422 opcode(CIJ_ZOPC); 9423 ins_encode(z_enc_cmpb_regimm(src1, src2, labl, boolnode)); 9424 ins_pipe(pipe_class_dummy); 9425 ins_short_branch(1); 9426 %} 9427 9428 // INT REG/IMM operands 9429 instruct cmpbU_RegI_imm(cmpOpT boolnode, iRegI src1, uimmI8 src2, label labl, flagsReg cr) %{ 9430 match(If boolnode (CmpU src1 src2)); 9431 effect(USE labl, KILL cr); 9432 predicate(VM_Version::has_CompareBranch()); 9433 ins_cost(BRANCH_COST); 9434 // TODO: s390 port size(FIXED_SIZE); 9435 format %{ "CLIJ,$boolnode $src1,$src2,$labl\t # SHORT" %} 9436 opcode(CLIJ_ZOPC); 9437 ins_encode(z_enc_cmpb_regimm(src1, src2, labl, boolnode)); 9438 ins_pipe(pipe_class_dummy); 9439 ins_short_branch(1); 9440 %} 9441 9442 // LONG REG/IMM operands 9443 instruct cmpb_RegL_imm(cmpOpT boolnode, iRegL src1, immL8 src2, label labl, flagsReg cr) %{ 9444 match(If boolnode (CmpL src1 src2)); 9445 effect(USE labl, KILL cr); 9446 predicate(VM_Version::has_CompareBranch()); 9447 ins_cost(BRANCH_COST); 9448 // TODO: s390 port size(FIXED_SIZE); 9449 format %{ "CGIJ,$boolnode $src1,$src2,$labl\t # SHORT" %} 9450 opcode(CGIJ_ZOPC); 9451 ins_encode(z_enc_cmpb_regimm(src1, src2, labl, boolnode)); 9452 ins_pipe(pipe_class_dummy); 9453 ins_short_branch(1); 9454 %} 9455 9456 // PTR REG-imm operands 9457 9458 // Separate rules for regular and narrow oops. ADLC can't recognize 9459 // rules with polymorphic operands to be sisters -> shorten_branches 9460 // will not shorten. 9461 9462 instruct cmpb_RegP_immP(cmpOpT boolnode, iRegP src1, immP8 src2, label labl, flagsReg cr) %{ 9463 match(If boolnode (CmpP src1 src2)); 9464 effect(USE labl, KILL cr); 9465 predicate(VM_Version::has_CompareBranch()); 9466 ins_cost(BRANCH_COST); 9467 // TODO: s390 port size(FIXED_SIZE); 9468 format %{ "CLGIJ,$boolnode $src1,$src2,$labl\t # SHORT" %} 9469 opcode(CLGIJ_ZOPC); 9470 ins_encode(z_enc_cmpb_regimm(src1, src2, labl, boolnode)); 9471 ins_pipe(pipe_class_dummy); 9472 ins_short_branch(1); 9473 %} 9474 9475 // Compare against zero only, do not mix N and P oops (encode/decode required). 9476 instruct cmpb_RegN_immP0(cmpOpT boolnode, iRegN src1, immP0 src2, label labl, flagsReg cr) %{ 9477 match(If boolnode (CmpP (DecodeN src1) src2)); 9478 effect(USE labl, KILL cr); 9479 predicate(VM_Version::has_CompareBranch()); 9480 ins_cost(BRANCH_COST); 9481 // TODO: s390 port size(FIXED_SIZE); 9482 format %{ "CLGIJ,$boolnode $src1,$src2,$labl\t # SHORT" %} 9483 opcode(CLGIJ_ZOPC); 9484 ins_encode(z_enc_cmpb_regimm(src1, src2, labl, boolnode)); 9485 ins_pipe(pipe_class_dummy); 9486 ins_short_branch(1); 9487 %} 9488 9489 instruct cmpb_RegN_imm(cmpOpT boolnode, iRegN src1, immN8 src2, label labl, flagsReg cr) %{ 9490 match(If boolnode (CmpP (DecodeN src1) (DecodeN src2))); 9491 effect(USE labl, KILL cr); 9492 predicate(VM_Version::has_CompareBranch()); 9493 ins_cost(BRANCH_COST); 9494 // TODO: s390 port size(FIXED_SIZE); 9495 format %{ "CLGIJ,$boolnode $src1,$src2,$labl\t # SHORT" %} 9496 opcode(CLGIJ_ZOPC); 9497 ins_encode(z_enc_cmpb_regimm(src1, src2, labl, boolnode)); 9498 ins_pipe(pipe_class_dummy); 9499 ins_short_branch(1); 9500 %} 9501 9502 9503 //----------Compare and Branch (far distance)------------------------------ 9504 9505 // INT REG operands for loop counter processing 9506 instruct testAndBranchLoopEnd_RegFar(cmpOpT boolnode, iRegI src1, iRegI src2, label labl, flagsReg cr) %{ 9507 match(CountedLoopEnd boolnode (CmpI src1 src2)); 9508 effect(USE labl, KILL cr); 9509 predicate(VM_Version::has_CompareBranch()); 9510 ins_cost(BRANCH_COST+DEFAULT_COST); 9511 // TODO: s390 port size(FIXED_SIZE); 9512 format %{ "test_and_branch_loop_end,$boolnode $src1,$src2,$labl\t # counted loop end FAR" %} 9513 opcode(CR_ZOPC, BRCL_ZOPC); 9514 ins_encode(z_enc_cmpb_regregFar(src1, src2, labl, boolnode)); 9515 ins_pipe(pipe_class_dummy); 9516 ins_short_branch(0); 9517 %} 9518 9519 // INT REG operands 9520 instruct cmpb_RegI_Far(cmpOpT boolnode, iRegI src1, iRegI src2, label labl, flagsReg cr) %{ 9521 match(If boolnode (CmpI src1 src2)); 9522 effect(USE labl, KILL cr); 9523 predicate(VM_Version::has_CompareBranch()); 9524 ins_cost(BRANCH_COST+DEFAULT_COST); 9525 // TODO: s390 port size(FIXED_SIZE); 9526 format %{ "CRJ,$boolnode $src1,$src2,$labl\t # FAR(substituted)" %} 9527 opcode(CR_ZOPC, BRCL_ZOPC); 9528 ins_encode(z_enc_cmpb_regregFar(src1, src2, labl, boolnode)); 9529 ins_pipe(pipe_class_dummy); 9530 ins_short_branch(0); 9531 %} 9532 9533 // INT REG operands 9534 instruct cmpbU_RegI_Far(cmpOpT boolnode, iRegI src1, iRegI src2, label labl, flagsReg cr) %{ 9535 match(If boolnode (CmpU src1 src2)); 9536 effect(USE labl, KILL cr); 9537 predicate(VM_Version::has_CompareBranch()); 9538 ins_cost(BRANCH_COST+DEFAULT_COST); 9539 // TODO: s390 port size(FIXED_SIZE); 9540 format %{ "CLRJ,$boolnode $src1,$src2,$labl\t # FAR(substituted)" %} 9541 opcode(CLR_ZOPC, BRCL_ZOPC); 9542 ins_encode(z_enc_cmpb_regregFar(src1, src2, labl, boolnode)); 9543 ins_pipe(pipe_class_dummy); 9544 ins_short_branch(0); 9545 %} 9546 9547 // LONG REG operands 9548 instruct cmpb_RegL_Far(cmpOpT boolnode, iRegL src1, iRegL src2, label labl, flagsReg cr) %{ 9549 match(If boolnode (CmpL src1 src2)); 9550 effect(USE labl, KILL cr); 9551 predicate(VM_Version::has_CompareBranch()); 9552 ins_cost(BRANCH_COST+DEFAULT_COST); 9553 // TODO: s390 port size(FIXED_SIZE); 9554 format %{ "CGRJ,$boolnode $src1,$src2,$labl\t # FAR(substituted)" %} 9555 opcode(CGR_ZOPC, BRCL_ZOPC); 9556 ins_encode(z_enc_cmpb_regregFar(src1, src2, labl, boolnode)); 9557 ins_pipe(pipe_class_dummy); 9558 ins_short_branch(0); 9559 %} 9560 9561 // PTR REG operands 9562 9563 // Separate rules for regular and narrow oops. ADLC can't recognize 9564 // rules with polymorphic operands to be sisters -> shorten_branches 9565 // will not shorten. 9566 9567 instruct cmpb_RegPP_Far(cmpOpT boolnode, iRegP src1, iRegP src2, label labl, flagsReg cr) %{ 9568 match(If boolnode (CmpP src1 src2)); 9569 effect(USE labl, KILL cr); 9570 predicate(VM_Version::has_CompareBranch()); 9571 ins_cost(BRANCH_COST+DEFAULT_COST); 9572 // TODO: s390 port size(FIXED_SIZE); 9573 format %{ "CLGRJ,$boolnode $src1,$src2,$labl\t # FAR(substituted)" %} 9574 opcode(CLGR_ZOPC, BRCL_ZOPC); 9575 ins_encode(z_enc_cmpb_regregFar(src1, src2, labl, boolnode)); 9576 ins_pipe(pipe_class_dummy); 9577 ins_short_branch(0); 9578 %} 9579 9580 instruct cmpb_RegNN_Far(cmpOpT boolnode, iRegN src1, iRegN src2, label labl, flagsReg cr) %{ 9581 match(If boolnode (CmpP (DecodeN src1) (DecodeN src2))); 9582 effect(USE labl, KILL cr); 9583 predicate(VM_Version::has_CompareBranch()); 9584 ins_cost(BRANCH_COST+DEFAULT_COST); 9585 // TODO: s390 port size(FIXED_SIZE); 9586 format %{ "CLGRJ,$boolnode $src1,$src2,$labl\t # FAR(substituted)" %} 9587 opcode(CLGR_ZOPC, BRCL_ZOPC); 9588 ins_encode(z_enc_cmpb_regregFar(src1, src2, labl, boolnode)); 9589 ins_pipe(pipe_class_dummy); 9590 ins_short_branch(0); 9591 %} 9592 9593 // INT REG/IMM operands for loop counter processing 9594 instruct testAndBranchLoopEnd_ImmFar(cmpOpT boolnode, iRegI src1, immI8 src2, label labl, flagsReg cr) %{ 9595 match(CountedLoopEnd boolnode (CmpI src1 src2)); 9596 effect(USE labl, KILL cr); 9597 predicate(VM_Version::has_CompareBranch()); 9598 ins_cost(BRANCH_COST+DEFAULT_COST); 9599 // TODO: s390 port size(FIXED_SIZE); 9600 format %{ "test_and_branch_loop_end,$boolnode $src1,$src2,$labl\t # counted loop end FAR" %} 9601 opcode(CHI_ZOPC, BRCL_ZOPC); 9602 ins_encode(z_enc_cmpb_regimmFar(src1, src2, labl, boolnode)); 9603 ins_pipe(pipe_class_dummy); 9604 ins_short_branch(0); 9605 %} 9606 9607 // INT REG/IMM operands 9608 instruct cmpb_RegI_imm_Far(cmpOpT boolnode, iRegI src1, immI8 src2, label labl, flagsReg cr) %{ 9609 match(If boolnode (CmpI src1 src2)); 9610 effect(USE labl, KILL cr); 9611 predicate(VM_Version::has_CompareBranch()); 9612 ins_cost(BRANCH_COST+DEFAULT_COST); 9613 // TODO: s390 port size(FIXED_SIZE); 9614 format %{ "CIJ,$boolnode $src1,$src2,$labl\t # FAR(substituted)" %} 9615 opcode(CHI_ZOPC, BRCL_ZOPC); 9616 ins_encode(z_enc_cmpb_regimmFar(src1, src2, labl, boolnode)); 9617 ins_pipe(pipe_class_dummy); 9618 ins_short_branch(0); 9619 %} 9620 9621 // INT REG/IMM operands 9622 instruct cmpbU_RegI_imm_Far(cmpOpT boolnode, iRegI src1, uimmI8 src2, label labl, flagsReg cr) %{ 9623 match(If boolnode (CmpU src1 src2)); 9624 effect(USE labl, KILL cr); 9625 predicate(VM_Version::has_CompareBranch()); 9626 ins_cost(BRANCH_COST+DEFAULT_COST); 9627 // TODO: s390 port size(FIXED_SIZE); 9628 format %{ "CLIJ,$boolnode $src1,$src2,$labl\t # FAR(substituted)" %} 9629 opcode(CLFI_ZOPC, BRCL_ZOPC); 9630 ins_encode(z_enc_cmpb_regimmFar(src1, src2, labl, boolnode)); 9631 ins_pipe(pipe_class_dummy); 9632 ins_short_branch(0); 9633 %} 9634 9635 // LONG REG/IMM operands 9636 instruct cmpb_RegL_imm_Far(cmpOpT boolnode, iRegL src1, immL8 src2, label labl, flagsReg cr) %{ 9637 match(If boolnode (CmpL src1 src2)); 9638 effect(USE labl, KILL cr); 9639 predicate(VM_Version::has_CompareBranch()); 9640 ins_cost(BRANCH_COST+DEFAULT_COST); 9641 // TODO: s390 port size(FIXED_SIZE); 9642 format %{ "CGIJ,$boolnode $src1,$src2,$labl\t # FAR(substituted)" %} 9643 opcode(CGHI_ZOPC, BRCL_ZOPC); 9644 ins_encode(z_enc_cmpb_regimmFar(src1, src2, labl, boolnode)); 9645 ins_pipe(pipe_class_dummy); 9646 ins_short_branch(0); 9647 %} 9648 9649 // PTR REG-imm operands 9650 9651 // Separate rules for regular and narrow oops. ADLC can't recognize 9652 // rules with polymorphic operands to be sisters -> shorten_branches 9653 // will not shorten. 9654 9655 instruct cmpb_RegP_immP_Far(cmpOpT boolnode, iRegP src1, immP8 src2, label labl, flagsReg cr) %{ 9656 match(If boolnode (CmpP src1 src2)); 9657 effect(USE labl, KILL cr); 9658 predicate(VM_Version::has_CompareBranch()); 9659 ins_cost(BRANCH_COST+DEFAULT_COST); 9660 // TODO: s390 port size(FIXED_SIZE); 9661 format %{ "CLGIJ,$boolnode $src1,$src2,$labl\t # FAR(substituted)" %} 9662 opcode(CLGFI_ZOPC, BRCL_ZOPC); 9663 ins_encode(z_enc_cmpb_regimmFar(src1, src2, labl, boolnode)); 9664 ins_pipe(pipe_class_dummy); 9665 ins_short_branch(0); 9666 %} 9667 9668 // Compare against zero only, do not mix N and P oops (encode/decode required). 9669 instruct cmpb_RegN_immP0_Far(cmpOpT boolnode, iRegN src1, immP0 src2, label labl, flagsReg cr) %{ 9670 match(If boolnode (CmpP (DecodeN src1) src2)); 9671 effect(USE labl, KILL cr); 9672 predicate(VM_Version::has_CompareBranch()); 9673 ins_cost(BRANCH_COST+DEFAULT_COST); 9674 // TODO: s390 port size(FIXED_SIZE); 9675 format %{ "CLGIJ,$boolnode $src1,$src2,$labl\t # FAR(substituted)" %} 9676 opcode(CLGFI_ZOPC, BRCL_ZOPC); 9677 ins_encode(z_enc_cmpb_regimmFar(src1, src2, labl, boolnode)); 9678 ins_pipe(pipe_class_dummy); 9679 ins_short_branch(0); 9680 %} 9681 9682 instruct cmpb_RegN_immN_Far(cmpOpT boolnode, iRegN src1, immN8 src2, label labl, flagsReg cr) %{ 9683 match(If boolnode (CmpP (DecodeN src1) (DecodeN src2))); 9684 effect(USE labl, KILL cr); 9685 predicate(VM_Version::has_CompareBranch()); 9686 ins_cost(BRANCH_COST+DEFAULT_COST); 9687 // TODO: s390 port size(FIXED_SIZE); 9688 format %{ "CLGIJ,$boolnode $src1,$src2,$labl\t # FAR(substituted)" %} 9689 opcode(CLGFI_ZOPC, BRCL_ZOPC); 9690 ins_encode(z_enc_cmpb_regimmFar(src1, src2, labl, boolnode)); 9691 ins_pipe(pipe_class_dummy); 9692 ins_short_branch(0); 9693 %} 9694 9695 // ============================================================================ 9696 // Long Compare 9697 9698 // Due to a shortcoming in the ADLC, it mixes up expressions like: 9699 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the 9700 // difference between 'Y' and '0L'. The tree-matches for the CmpI sections 9701 // are collapsed internally in the ADLC's dfa-gen code. The match for 9702 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the 9703 // foo match ends up with the wrong leaf. One fix is to not match both 9704 // reg-reg and reg-zero forms of long-compare. This is unfortunate because 9705 // both forms beat the trinary form of long-compare and both are very useful 9706 // on platforms which have few registers. 9707 9708 // Manifest a CmpL3 result in an integer register. Very painful. 9709 // This is the test to avoid. 9710 instruct cmpL3_reg_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg cr) %{ 9711 match(Set dst (CmpL3 src1 src2)); 9712 effect(KILL cr); 9713 ins_cost(DEFAULT_COST * 5 + BRANCH_COST); 9714 size(24); 9715 format %{ "CmpL3 $dst,$src1,$src2" %} 9716 ins_encode %{ 9717 Label done; 9718 // compare registers 9719 __ z_cgr($src1$$Register, $src2$$Register); 9720 // Convert condition code into -1,0,1, where 9721 // -1 means less 9722 // 0 means equal 9723 // 1 means greater. 9724 if (VM_Version::has_LoadStoreConditional()) { 9725 Register one = Z_R0_scratch; 9726 Register minus_one = Z_R1_scratch; 9727 __ z_lghi(minus_one, -1); 9728 __ z_lghi(one, 1); 9729 __ z_lghi( $dst$$Register, 0); 9730 __ z_locgr($dst$$Register, one, Assembler::bcondHigh); 9731 __ z_locgr($dst$$Register, minus_one, Assembler::bcondLow); 9732 } else { 9733 __ clear_reg($dst$$Register, true, false); 9734 __ z_bre(done); 9735 __ z_lhi($dst$$Register, 1); 9736 __ z_brh(done); 9737 __ z_lhi($dst$$Register, -1); 9738 } 9739 __ bind(done); 9740 %} 9741 ins_pipe(pipe_class_dummy); 9742 %} 9743 9744 // ============================================================================ 9745 // Safepoint Instruction 9746 9747 instruct safePoint() %{ 9748 match(SafePoint); 9749 predicate(false); 9750 // TODO: s390 port size(FIXED_SIZE); 9751 format %{ "UNIMPLEMENTED Safepoint_ " %} 9752 ins_encode(enc_unimplemented()); 9753 ins_pipe(pipe_class_dummy); 9754 %} 9755 9756 instruct safePoint_poll(iRegP poll, flagsReg cr) %{ 9757 match(SafePoint poll); 9758 effect(USE poll, KILL cr); // R0 is killed, too. 9759 // TODO: s390 port size(FIXED_SIZE); 9760 format %{ "TM #0[,$poll],#111\t # Safepoint: poll for GC" %} 9761 ins_encode %{ 9762 // Mark the code position where the load from the safepoint 9763 // polling page was emitted as relocInfo::poll_type. 9764 __ relocate(relocInfo::poll_type); 9765 __ load_from_polling_page($poll$$Register); 9766 %} 9767 ins_pipe(pipe_class_dummy); 9768 %} 9769 9770 // ============================================================================ 9771 9772 // Call Instructions 9773 9774 // Call Java Static Instruction 9775 instruct CallStaticJavaDirect_dynTOC(method meth) %{ 9776 match(CallStaticJava); 9777 effect(USE meth); 9778 ins_cost(CALL_COST); 9779 // TODO: s390 port size(VARIABLE_SIZE); 9780 format %{ "CALL,static dynTOC $meth; ==> " %} 9781 ins_encode( z_enc_java_static_call(meth) ); 9782 ins_pipe(pipe_class_dummy); 9783 ins_alignment(2); 9784 %} 9785 9786 // Call Java Dynamic Instruction 9787 instruct CallDynamicJavaDirect_dynTOC(method meth) %{ 9788 match(CallDynamicJava); 9789 effect(USE meth); 9790 ins_cost(CALL_COST); 9791 // TODO: s390 port size(VARIABLE_SIZE); 9792 format %{ "CALL,dynamic dynTOC $meth; ==> " %} 9793 ins_encode(z_enc_java_dynamic_call(meth)); 9794 ins_pipe(pipe_class_dummy); 9795 ins_alignment(2); 9796 %} 9797 9798 // Call Runtime Instruction 9799 instruct CallRuntimeDirect(method meth) %{ 9800 match(CallRuntime); 9801 effect(USE meth); 9802 ins_cost(CALL_COST); 9803 // TODO: s390 port size(VARIABLE_SIZE); 9804 ins_num_consts(1); 9805 ins_alignment(2); 9806 format %{ "CALL,runtime" %} 9807 ins_encode( z_enc_java_to_runtime_call(meth) ); 9808 ins_pipe(pipe_class_dummy); 9809 %} 9810 9811 // Call runtime without safepoint - same as CallRuntime 9812 instruct CallLeafDirect(method meth) %{ 9813 match(CallLeaf); 9814 effect(USE meth); 9815 ins_cost(CALL_COST); 9816 // TODO: s390 port size(VARIABLE_SIZE); 9817 ins_num_consts(1); 9818 ins_alignment(2); 9819 format %{ "CALL,runtime leaf $meth" %} 9820 ins_encode( z_enc_java_to_runtime_call(meth) ); 9821 ins_pipe(pipe_class_dummy); 9822 %} 9823 9824 // Call runtime without safepoint - same as CallLeaf 9825 instruct CallLeafNoFPDirect(method meth) %{ 9826 match(CallLeafNoFP); 9827 effect(USE meth); 9828 ins_cost(CALL_COST); 9829 // TODO: s390 port size(VARIABLE_SIZE); 9830 ins_num_consts(1); 9831 format %{ "CALL,runtime leaf nofp $meth" %} 9832 ins_encode( z_enc_java_to_runtime_call(meth) ); 9833 ins_pipe(pipe_class_dummy); 9834 ins_alignment(2); 9835 %} 9836 9837 // Tail Call; Jump from runtime stub to Java code. 9838 // Also known as an 'interprocedural jump'. 9839 // Target of jump will eventually return to caller. 9840 // TailJump below removes the return address. 9841 instruct TailCalljmpInd(iRegP jump_target, inline_cache_regP method_ptr) %{ 9842 match(TailCall jump_target method_ptr); 9843 ins_cost(CALL_COST); 9844 size(2); 9845 format %{ "Jmp $jump_target\t # $method_ptr holds method" %} 9846 ins_encode %{ __ z_br($jump_target$$Register); %} 9847 ins_pipe(pipe_class_dummy); 9848 %} 9849 9850 // Return Instruction 9851 instruct Ret() %{ 9852 match(Return); 9853 size(2); 9854 format %{ "BR(Z_R14) // branch to link register" %} 9855 ins_encode %{ __ z_br(Z_R14); %} 9856 ins_pipe(pipe_class_dummy); 9857 %} 9858 9859 // Tail Jump; remove the return address; jump to target. 9860 // TailCall above leaves the return address around. 9861 // TailJump is used in only one place, the rethrow_Java stub (fancy_jump=2). 9862 // ex_oop (Exception Oop) is needed in %o0 at the jump. As there would be a 9863 // "restore" before this instruction (in Epilogue), we need to materialize it 9864 // in %i0. 9865 instruct tailjmpInd(iRegP jump_target, rarg1RegP ex_oop) %{ 9866 match(TailJump jump_target ex_oop); 9867 ins_cost(CALL_COST); 9868 size(8); 9869 format %{ "TailJump $jump_target" %} 9870 ins_encode %{ 9871 __ z_lg(Z_ARG2/* issuing pc */, _z_abi(return_pc), Z_SP); 9872 __ z_br($jump_target$$Register); 9873 %} 9874 ins_pipe(pipe_class_dummy); 9875 %} 9876 9877 // Create exception oop: created by stack-crawling runtime code. 9878 // Created exception is now available to this handler, and is setup 9879 // just prior to jumping to this handler. No code emitted. 9880 instruct CreateException(rarg1RegP ex_oop) %{ 9881 match(Set ex_oop (CreateEx)); 9882 ins_cost(0); 9883 size(0); 9884 format %{ "# exception oop; no code emitted" %} 9885 ins_encode(/*empty*/); 9886 ins_pipe(pipe_class_dummy); 9887 %} 9888 9889 // Rethrow exception: The exception oop will come in the first 9890 // argument position. Then JUMP (not call) to the rethrow stub code. 9891 instruct RethrowException() %{ 9892 match(Rethrow); 9893 ins_cost(CALL_COST); 9894 // TODO: s390 port size(VARIABLE_SIZE); 9895 format %{ "Jmp rethrow_stub" %} 9896 ins_encode %{ 9897 cbuf.set_insts_mark(); 9898 __ load_const_optimized(Z_R1_scratch, (address)OptoRuntime::rethrow_stub()); 9899 __ z_br(Z_R1_scratch); 9900 %} 9901 ins_pipe(pipe_class_dummy); 9902 %} 9903 9904 // Die now. 9905 instruct ShouldNotReachHere() %{ 9906 match(Halt); 9907 ins_cost(CALL_COST); 9908 format %{ "ILLTRAP; ShouldNotReachHere" %} 9909 ins_encode %{ 9910 if (is_reachable()) { 9911 __ stop(_halt_reason); 9912 } 9913 %} 9914 ins_pipe(pipe_class_dummy); 9915 %} 9916 9917 // ============================================================================ 9918 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass 9919 // array for an instance of the superklass. Set a hidden internal cache on a 9920 // hit (cache is checked with exposed code in gen_subtype_check()). Return 9921 // not zero for a miss or zero for a hit. The encoding ALSO sets flags. 9922 instruct partialSubtypeCheck(rarg1RegP index, rarg2RegP sub, rarg3RegP super, flagsReg pcc, 9923 rarg4RegP scratch1, rarg5RegP scratch2) %{ 9924 match(Set index (PartialSubtypeCheck sub super)); 9925 effect(KILL pcc, KILL scratch1, KILL scratch2); 9926 ins_cost(10 * DEFAULT_COST); 9927 // TODO: s390 port size(FIXED_SIZE); 9928 format %{ " CALL PartialSubtypeCheck\n" %} 9929 ins_encode %{ 9930 AddressLiteral stub_address(StubRoutines::zarch::partial_subtype_check()); 9931 __ load_const_optimized(Z_ARG4, stub_address); 9932 __ z_basr(Z_R14, Z_ARG4); 9933 %} 9934 ins_pipe(pipe_class_dummy); 9935 %} 9936 9937 instruct partialSubtypeCheck_vs_zero(flagsReg pcc, rarg2RegP sub, rarg3RegP super, immP0 zero, 9938 rarg1RegP index, rarg4RegP scratch1, rarg5RegP scratch2) %{ 9939 match(Set pcc (CmpI (PartialSubtypeCheck sub super) zero)); 9940 effect(KILL scratch1, KILL scratch2, KILL index); 9941 ins_cost(10 * DEFAULT_COST); 9942 // TODO: s390 port size(FIXED_SIZE); 9943 format %{ "CALL PartialSubtypeCheck_vs_zero\n" %} 9944 ins_encode %{ 9945 AddressLiteral stub_address(StubRoutines::zarch::partial_subtype_check()); 9946 __ load_const_optimized(Z_ARG4, stub_address); 9947 __ z_basr(Z_R14, Z_ARG4); 9948 %} 9949 ins_pipe(pipe_class_dummy); 9950 %} 9951 9952 // ============================================================================ 9953 // inlined locking and unlocking 9954 9955 instruct cmpFastLock(flagsReg pcc, iRegP_N2P oop, iRegP_N2P box, iRegP tmp1, iRegP tmp2) %{ 9956 match(Set pcc (FastLock oop box)); 9957 effect(TEMP tmp1, TEMP tmp2); 9958 ins_cost(100); 9959 // TODO: s390 port size(VARIABLE_SIZE); // Uses load_const_optimized. 9960 format %{ "FASTLOCK $oop, $box; KILL Z_ARG4, Z_ARG5" %} 9961 ins_encode %{ __ compiler_fast_lock_object($oop$$Register, $box$$Register, $tmp1$$Register, $tmp2$$Register, 9962 UseBiasedLocking && !UseOptoBiasInlining); %} 9963 ins_pipe(pipe_class_dummy); 9964 %} 9965 9966 instruct cmpFastUnlock(flagsReg pcc, iRegP_N2P oop, iRegP_N2P box, iRegP tmp1, iRegP tmp2) %{ 9967 match(Set pcc (FastUnlock oop box)); 9968 effect(TEMP tmp1, TEMP tmp2); 9969 ins_cost(100); 9970 // TODO: s390 port size(FIXED_SIZE); // emitted code depends on UseBiasedLocking being on/off. 9971 format %{ "FASTUNLOCK $oop, $box; KILL Z_ARG4, Z_ARG5" %} 9972 ins_encode %{ __ compiler_fast_unlock_object($oop$$Register, $box$$Register, $tmp1$$Register, $tmp2$$Register, 9973 UseBiasedLocking && !UseOptoBiasInlining); %} 9974 ins_pipe(pipe_class_dummy); 9975 %} 9976 9977 instruct inlineCallClearArrayConst(SSlenDW cnt, iRegP_N2P base, Universe dummy, flagsReg cr) %{ 9978 match(Set dummy (ClearArray cnt base)); 9979 effect(KILL cr); 9980 ins_cost(100); 9981 // TODO: s390 port size(VARIABLE_SIZE); // Variable in size due to varying #instructions. 9982 format %{ "ClearArrayConst $cnt,$base" %} 9983 ins_encode %{ __ Clear_Array_Const($cnt$$constant, $base$$Register); %} 9984 ins_pipe(pipe_class_dummy); 9985 %} 9986 9987 instruct inlineCallClearArrayConstBig(immL cnt, iRegP_N2P base, Universe dummy, allRoddRegL tmpL, flagsReg cr) %{ 9988 match(Set dummy (ClearArray cnt base)); 9989 effect(TEMP tmpL, KILL cr); // R0, R1 are killed, too. 9990 ins_cost(200); 9991 // TODO: s390 port size(VARIABLE_SIZE); // Variable in size due to optimized constant loader. 9992 format %{ "ClearArrayConstBig $cnt,$base" %} 9993 ins_encode %{ __ Clear_Array_Const_Big($cnt$$constant, $base$$Register, $tmpL$$Register); %} 9994 ins_pipe(pipe_class_dummy); 9995 %} 9996 9997 instruct inlineCallClearArray(iRegL cnt, iRegP_N2P base, Universe dummy, allRoddRegL tmpL, flagsReg cr) %{ 9998 match(Set dummy (ClearArray cnt base)); 9999 effect(TEMP tmpL, KILL cr); // R0, R1 are killed, too. 10000 ins_cost(300); 10001 // TODO: s390 port size(FIXED_SIZE); // z/Architecture: emitted code depends on PreferLAoverADD being on/off. 10002 format %{ "ClearArrayVar $cnt,$base" %} 10003 ins_encode %{ __ Clear_Array($cnt$$Register, $base$$Register, $tmpL$$Register); %} 10004 ins_pipe(pipe_class_dummy); 10005 %} 10006 10007 // ============================================================================ 10008 // CompactStrings 10009 10010 // String equals 10011 instruct string_equalsL(iRegP str1, iRegP str2, iRegI cnt, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{ 10012 match(Set result (StrEquals (Binary str1 str2) cnt)); 10013 effect(TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too. 10014 predicate(((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::LL); 10015 ins_cost(300); 10016 format %{ "String Equals byte[] $str1,$str2,$cnt -> $result" %} 10017 ins_encode %{ 10018 __ array_equals(false, $str1$$Register, $str2$$Register, 10019 $cnt$$Register, $oddReg$$Register, $evenReg$$Register, 10020 $result$$Register, true /* byte */); 10021 %} 10022 ins_pipe(pipe_class_dummy); 10023 %} 10024 10025 instruct string_equalsU(iRegP str1, iRegP str2, iRegI cnt, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{ 10026 match(Set result (StrEquals (Binary str1 str2) cnt)); 10027 effect(TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too. 10028 predicate(((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::UU || ((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::none); 10029 ins_cost(300); 10030 format %{ "String Equals char[] $str1,$str2,$cnt -> $result" %} 10031 ins_encode %{ 10032 __ array_equals(false, $str1$$Register, $str2$$Register, 10033 $cnt$$Register, $oddReg$$Register, $evenReg$$Register, 10034 $result$$Register, false /* byte */); 10035 %} 10036 ins_pipe(pipe_class_dummy); 10037 %} 10038 10039 instruct string_equals_imm(iRegP str1, iRegP str2, uimmI8 cnt, iRegI result, flagsReg cr) %{ 10040 match(Set result (StrEquals (Binary str1 str2) cnt)); 10041 effect(KILL cr); // R0 is killed, too. 10042 predicate(((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::LL || ((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::UU); 10043 ins_cost(100); 10044 format %{ "String Equals byte[] $str1,$str2,$cnt -> $result" %} 10045 ins_encode %{ 10046 const int cnt_imm = $cnt$$constant; 10047 if (cnt_imm) { __ z_clc(0, cnt_imm - 1, $str1$$Register, 0, $str2$$Register); } 10048 __ z_lhi($result$$Register, 1); 10049 if (cnt_imm) { 10050 if (VM_Version::has_LoadStoreConditional()) { 10051 __ z_lhi(Z_R0_scratch, 0); 10052 __ z_locr($result$$Register, Z_R0_scratch, Assembler::bcondNotEqual); 10053 } else { 10054 Label Lskip; 10055 __ z_bre(Lskip); 10056 __ clear_reg($result$$Register); 10057 __ bind(Lskip); 10058 } 10059 } 10060 %} 10061 ins_pipe(pipe_class_dummy); 10062 %} 10063 10064 instruct string_equalsC_imm(iRegP str1, iRegP str2, immI8 cnt, iRegI result, flagsReg cr) %{ 10065 match(Set result (StrEquals (Binary str1 str2) cnt)); 10066 effect(KILL cr); // R0 is killed, too. 10067 predicate(((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::none); 10068 ins_cost(100); 10069 format %{ "String Equals $str1,$str2,$cnt -> $result" %} 10070 ins_encode %{ 10071 const int cnt_imm = $cnt$$constant; // positive immI8 (7 bits used) 10072 if (cnt_imm) { __ z_clc(0, (cnt_imm << 1) - 1, $str1$$Register, 0, $str2$$Register); } 10073 __ z_lhi($result$$Register, 1); 10074 if (cnt_imm) { 10075 if (VM_Version::has_LoadStoreConditional()) { 10076 __ z_lhi(Z_R0_scratch, 0); 10077 __ z_locr($result$$Register, Z_R0_scratch, Assembler::bcondNotEqual); 10078 } else { 10079 Label Lskip; 10080 __ z_bre(Lskip); 10081 __ clear_reg($result$$Register); 10082 __ bind(Lskip); 10083 } 10084 } 10085 %} 10086 ins_pipe(pipe_class_dummy); 10087 %} 10088 10089 // Array equals 10090 instruct array_equalsB(iRegP ary1, iRegP ary2, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{ 10091 match(Set result (AryEq ary1 ary2)); 10092 effect(TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too. 10093 predicate(((AryEqNode*)n)->encoding() == StrIntrinsicNode::LL); 10094 ins_cost(300); 10095 format %{ "Array Equals $ary1,$ary2 -> $result" %} 10096 ins_encode %{ 10097 __ array_equals(true, $ary1$$Register, $ary2$$Register, 10098 noreg, $oddReg$$Register, $evenReg$$Register, 10099 $result$$Register, true /* byte */); 10100 %} 10101 ins_pipe(pipe_class_dummy); 10102 %} 10103 10104 instruct array_equalsC(iRegP ary1, iRegP ary2, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{ 10105 match(Set result (AryEq ary1 ary2)); 10106 effect(TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too. 10107 predicate(((AryEqNode*)n)->encoding() == StrIntrinsicNode::UU); 10108 ins_cost(300); 10109 format %{ "Array Equals $ary1,$ary2 -> $result" %} 10110 ins_encode %{ 10111 __ array_equals(true, $ary1$$Register, $ary2$$Register, 10112 noreg, $oddReg$$Register, $evenReg$$Register, 10113 $result$$Register, false /* byte */); 10114 %} 10115 ins_pipe(pipe_class_dummy); 10116 %} 10117 10118 // String CompareTo 10119 instruct string_compareL(iRegP str1, iRegP str2, rarg2RegI cnt1, rarg5RegI cnt2, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{ 10120 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2))); 10121 effect(TEMP_DEF result, USE_KILL cnt1, USE_KILL cnt2, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too. 10122 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::LL); 10123 ins_cost(300); 10124 format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result" %} 10125 ins_encode %{ 10126 __ string_compare($str1$$Register, $str2$$Register, 10127 $cnt1$$Register, $cnt2$$Register, 10128 $oddReg$$Register, $evenReg$$Register, 10129 $result$$Register, StrIntrinsicNode::LL); 10130 %} 10131 ins_pipe(pipe_class_dummy); 10132 %} 10133 10134 instruct string_compareU(iRegP str1, iRegP str2, rarg2RegI cnt1, rarg5RegI cnt2, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{ 10135 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2))); 10136 effect(TEMP_DEF result, USE_KILL cnt1, USE_KILL cnt2, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too. 10137 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::UU || ((StrCompNode*)n)->encoding() == StrIntrinsicNode::none); 10138 ins_cost(300); 10139 format %{ "String Compare char[] $str1,$cnt1,$str2,$cnt2 -> $result" %} 10140 ins_encode %{ 10141 __ string_compare($str1$$Register, $str2$$Register, 10142 $cnt1$$Register, $cnt2$$Register, 10143 $oddReg$$Register, $evenReg$$Register, 10144 $result$$Register, StrIntrinsicNode::UU); 10145 %} 10146 ins_pipe(pipe_class_dummy); 10147 %} 10148 10149 instruct string_compareLU(iRegP str1, iRegP str2, rarg2RegI cnt1, rarg5RegI cnt2, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{ 10150 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2))); 10151 effect(TEMP_DEF result, USE_KILL cnt1, USE_KILL cnt2, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too. 10152 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::LU); 10153 ins_cost(300); 10154 format %{ "String Compare byte[],char[] $str1,$cnt1,$str2,$cnt2 -> $result" %} 10155 ins_encode %{ 10156 __ string_compare($str1$$Register, $str2$$Register, 10157 $cnt1$$Register, $cnt2$$Register, 10158 $oddReg$$Register, $evenReg$$Register, 10159 $result$$Register, StrIntrinsicNode::LU); 10160 %} 10161 ins_pipe(pipe_class_dummy); 10162 %} 10163 10164 instruct string_compareUL(iRegP str1, iRegP str2, rarg2RegI cnt1, rarg5RegI cnt2, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{ 10165 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2))); 10166 effect(TEMP_DEF result, USE_KILL cnt1, USE_KILL cnt2, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too. 10167 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::UL); 10168 ins_cost(300); 10169 format %{ "String Compare char[],byte[] $str1,$cnt1,$str2,$cnt2 -> $result" %} 10170 ins_encode %{ 10171 __ string_compare($str2$$Register, $str1$$Register, 10172 $cnt2$$Register, $cnt1$$Register, 10173 $oddReg$$Register, $evenReg$$Register, 10174 $result$$Register, StrIntrinsicNode::UL); 10175 %} 10176 ins_pipe(pipe_class_dummy); 10177 %} 10178 10179 // String IndexOfChar 10180 instruct indexOfChar_U(iRegP haystack, iRegI haycnt, iRegI ch, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{ 10181 match(Set result (StrIndexOfChar (Binary haystack haycnt) ch)); 10182 effect(TEMP_DEF result, TEMP evenReg, TEMP oddReg, KILL cr); // R0, R1 are killed, too. 10183 ins_cost(200); 10184 format %{ "String IndexOfChar [0..$haycnt]($haystack), $ch -> $result" %} 10185 ins_encode %{ 10186 __ string_indexof_char($result$$Register, 10187 $haystack$$Register, $haycnt$$Register, 10188 $ch$$Register, 0 /* unused, ch is in register */, 10189 $oddReg$$Register, $evenReg$$Register, false /*is_byte*/); 10190 %} 10191 ins_pipe(pipe_class_dummy); 10192 %} 10193 10194 instruct indexOf_imm1_U(iRegP haystack, iRegI haycnt, immP needle, immI_1 needlecnt, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{ 10195 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecnt))); 10196 effect(TEMP_DEF result, TEMP evenReg, TEMP oddReg, KILL cr); // R0, R1 are killed, too. 10197 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU || ((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::none); 10198 ins_cost(200); 10199 format %{ "String IndexOf UL [0..$haycnt]($haystack), [0]($needle) -> $result" %} 10200 ins_encode %{ 10201 immPOper *needleOper = (immPOper *)$needle; 10202 const TypeOopPtr *t = needleOper->type()->isa_oopptr(); 10203 ciTypeArray* needle_values = t->const_oop()->as_type_array(); // Pointer to live char * 10204 jchar chr; 10205 #ifdef VM_LITTLE_ENDIAN 10206 Unimplemented(); 10207 #else 10208 chr = (((jchar)(unsigned char)needle_values->element_value(0).as_byte()) << 8) | 10209 ((jchar)(unsigned char)needle_values->element_value(1).as_byte()); 10210 #endif 10211 __ string_indexof_char($result$$Register, 10212 $haystack$$Register, $haycnt$$Register, 10213 noreg, chr, 10214 $oddReg$$Register, $evenReg$$Register, false /*is_byte*/); 10215 %} 10216 ins_pipe(pipe_class_dummy); 10217 %} 10218 10219 instruct indexOf_imm1_L(iRegP haystack, iRegI haycnt, immP needle, immI_1 needlecnt, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{ 10220 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecnt))); 10221 effect(TEMP_DEF result, TEMP evenReg, TEMP oddReg, KILL cr); // R0, R1 are killed, too. 10222 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL); 10223 ins_cost(200); 10224 format %{ "String IndexOf L [0..$haycnt]($haystack), [0]($needle) -> $result" %} 10225 ins_encode %{ 10226 immPOper *needleOper = (immPOper *)$needle; 10227 const TypeOopPtr *t = needleOper->type()->isa_oopptr(); 10228 ciTypeArray* needle_values = t->const_oop()->as_type_array(); // Pointer to live char * 10229 jchar chr = (jchar)needle_values->element_value(0).as_byte(); 10230 __ string_indexof_char($result$$Register, 10231 $haystack$$Register, $haycnt$$Register, 10232 noreg, chr, 10233 $oddReg$$Register, $evenReg$$Register, true /*is_byte*/); 10234 %} 10235 ins_pipe(pipe_class_dummy); 10236 %} 10237 10238 instruct indexOf_imm1_UL(iRegP haystack, iRegI haycnt, immP needle, immI_1 needlecnt, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{ 10239 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecnt))); 10240 effect(TEMP_DEF result, TEMP evenReg, TEMP oddReg, KILL cr); // R0, R1 are killed, too. 10241 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL); 10242 ins_cost(200); 10243 format %{ "String IndexOf UL [0..$haycnt]($haystack), [0]($needle) -> $result" %} 10244 ins_encode %{ 10245 immPOper *needleOper = (immPOper *)$needle; 10246 const TypeOopPtr *t = needleOper->type()->isa_oopptr(); 10247 ciTypeArray* needle_values = t->const_oop()->as_type_array(); // Pointer to live char * 10248 jchar chr = (jchar)needle_values->element_value(0).as_byte(); 10249 __ string_indexof_char($result$$Register, 10250 $haystack$$Register, $haycnt$$Register, 10251 noreg, chr, 10252 $oddReg$$Register, $evenReg$$Register, false /*is_byte*/); 10253 %} 10254 ins_pipe(pipe_class_dummy); 10255 %} 10256 10257 // String IndexOf 10258 instruct indexOf_imm_U(iRegP haystack, rarg2RegI haycnt, iRegP needle, immI16 needlecntImm, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{ 10259 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecntImm))); 10260 effect(TEMP_DEF result, USE_KILL haycnt, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too. 10261 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU || ((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::none); 10262 ins_cost(250); 10263 format %{ "String IndexOf U [0..$needlecntImm]($needle) .in. [0..$haycnt]($haystack) -> $result" %} 10264 ins_encode %{ 10265 __ string_indexof($result$$Register, 10266 $haystack$$Register, $haycnt$$Register, 10267 $needle$$Register, noreg, $needlecntImm$$constant, 10268 $oddReg$$Register, $evenReg$$Register, StrIntrinsicNode::UU); 10269 %} 10270 ins_pipe(pipe_class_dummy); 10271 %} 10272 10273 instruct indexOf_imm_L(iRegP haystack, rarg2RegI haycnt, iRegP needle, immI16 needlecntImm, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{ 10274 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecntImm))); 10275 effect(TEMP_DEF result, USE_KILL haycnt, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too. 10276 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL); 10277 ins_cost(250); 10278 format %{ "String IndexOf L [0..$needlecntImm]($needle) .in. [0..$haycnt]($haystack) -> $result" %} 10279 ins_encode %{ 10280 __ string_indexof($result$$Register, 10281 $haystack$$Register, $haycnt$$Register, 10282 $needle$$Register, noreg, $needlecntImm$$constant, 10283 $oddReg$$Register, $evenReg$$Register, StrIntrinsicNode::LL); 10284 %} 10285 ins_pipe(pipe_class_dummy); 10286 %} 10287 10288 instruct indexOf_imm_UL(iRegP haystack, rarg2RegI haycnt, iRegP needle, immI16 needlecntImm, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{ 10289 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecntImm))); 10290 effect(TEMP_DEF result, USE_KILL haycnt, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too. 10291 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL); 10292 ins_cost(250); 10293 format %{ "String IndexOf UL [0..$needlecntImm]($needle) .in. [0..$haycnt]($haystack) -> $result" %} 10294 ins_encode %{ 10295 __ string_indexof($result$$Register, 10296 $haystack$$Register, $haycnt$$Register, 10297 $needle$$Register, noreg, $needlecntImm$$constant, 10298 $oddReg$$Register, $evenReg$$Register, StrIntrinsicNode::UL); 10299 %} 10300 ins_pipe(pipe_class_dummy); 10301 %} 10302 10303 instruct indexOf_U(iRegP haystack, rarg2RegI haycnt, iRegP needle, rarg5RegI needlecnt, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{ 10304 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecnt))); 10305 effect(TEMP_DEF result, USE_KILL haycnt, USE_KILL needlecnt, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too. 10306 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU || ((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::none); 10307 ins_cost(300); 10308 format %{ "String IndexOf U [0..$needlecnt]($needle) .in. [0..$haycnt]($haystack) -> $result" %} 10309 ins_encode %{ 10310 __ string_indexof($result$$Register, 10311 $haystack$$Register, $haycnt$$Register, 10312 $needle$$Register, $needlecnt$$Register, 0, 10313 $oddReg$$Register, $evenReg$$Register, StrIntrinsicNode::UU); 10314 %} 10315 ins_pipe(pipe_class_dummy); 10316 %} 10317 10318 instruct indexOf_L(iRegP haystack, rarg2RegI haycnt, iRegP needle, rarg5RegI needlecnt, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{ 10319 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecnt))); 10320 effect(TEMP_DEF result, USE_KILL haycnt, USE_KILL needlecnt, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too. 10321 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL); 10322 ins_cost(300); 10323 format %{ "String IndexOf L [0..$needlecnt]($needle) .in. [0..$haycnt]($haystack) -> $result" %} 10324 ins_encode %{ 10325 __ string_indexof($result$$Register, 10326 $haystack$$Register, $haycnt$$Register, 10327 $needle$$Register, $needlecnt$$Register, 0, 10328 $oddReg$$Register, $evenReg$$Register, StrIntrinsicNode::LL); 10329 %} 10330 ins_pipe(pipe_class_dummy); 10331 %} 10332 10333 instruct indexOf_UL(iRegP haystack, rarg2RegI haycnt, iRegP needle, rarg5RegI needlecnt, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{ 10334 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecnt))); 10335 effect(TEMP_DEF result, USE_KILL haycnt, USE_KILL needlecnt, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too. 10336 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL); 10337 ins_cost(300); 10338 format %{ "String IndexOf UL [0..$needlecnt]($needle) .in. [0..$haycnt]($haystack) -> $result" %} 10339 ins_encode %{ 10340 __ string_indexof($result$$Register, 10341 $haystack$$Register, $haycnt$$Register, 10342 $needle$$Register, $needlecnt$$Register, 0, 10343 $oddReg$$Register, $evenReg$$Register, StrIntrinsicNode::UL); 10344 %} 10345 ins_pipe(pipe_class_dummy); 10346 %} 10347 10348 // char[] to byte[] compression 10349 instruct string_compress(iRegP src, iRegP dst, iRegI result, iRegI len, iRegI tmp, flagsReg cr) %{ 10350 match(Set result (StrCompressedCopy src (Binary dst len))); 10351 effect(TEMP_DEF result, TEMP tmp, KILL cr); // R0, R1 are killed, too. 10352 ins_cost(300); 10353 format %{ "String Compress $src->$dst($len) -> $result" %} 10354 ins_encode %{ 10355 __ string_compress($result$$Register, $src$$Register, $dst$$Register, $len$$Register, 10356 $tmp$$Register, false); 10357 %} 10358 ins_pipe(pipe_class_dummy); 10359 %} 10360 10361 // byte[] to char[] inflation. trot implementation is shorter, but slower than the unrolled icm(h) loop. 10362 //instruct string_inflate_trot(Universe dummy, iRegP src, revenRegP dst, roddRegI len, iRegI tmp, flagsReg cr) %{ 10363 // match(Set dummy (StrInflatedCopy src (Binary dst len))); 10364 // effect(USE_KILL dst, USE_KILL len, TEMP tmp, KILL cr); // R0, R1 are killed, too. 10365 // predicate(VM_Version::has_ETF2Enhancements()); 10366 // ins_cost(300); 10367 // format %{ "String Inflate (trot) $dst,$src($len)" %} 10368 // ins_encode %{ 10369 // __ string_inflate_trot($src$$Register, $dst$$Register, $len$$Register, $tmp$$Register); 10370 // %} 10371 // ins_pipe(pipe_class_dummy); 10372 //%} 10373 10374 // byte[] to char[] inflation 10375 instruct string_inflate(Universe dummy, iRegP src, iRegP dst, iRegI len, iRegI tmp, flagsReg cr) %{ 10376 match(Set dummy (StrInflatedCopy src (Binary dst len))); 10377 effect(TEMP tmp, KILL cr); // R0, R1 are killed, too. 10378 ins_cost(300); 10379 format %{ "String Inflate $src->$dst($len)" %} 10380 ins_encode %{ 10381 __ string_inflate($src$$Register, $dst$$Register, $len$$Register, $tmp$$Register); 10382 %} 10383 ins_pipe(pipe_class_dummy); 10384 %} 10385 10386 // byte[] to char[] inflation 10387 instruct string_inflate_const(Universe dummy, iRegP src, iRegP dst, iRegI tmp, immI len, flagsReg cr) %{ 10388 match(Set dummy (StrInflatedCopy src (Binary dst len))); 10389 effect(TEMP tmp, KILL cr); // R0, R1 are killed, too. 10390 ins_cost(300); 10391 format %{ "String Inflate (constLen) $src->$dst($len)" %} 10392 ins_encode %{ 10393 __ string_inflate_const($src$$Register, $dst$$Register, $tmp$$Register, $len$$constant); 10394 %} 10395 ins_pipe(pipe_class_dummy); 10396 %} 10397 10398 // StringCoding.java intrinsics 10399 instruct has_negatives(rarg5RegP ary1, iRegI len, iRegI result, roddRegI oddReg, revenRegI evenReg, iRegI tmp, flagsReg cr) %{ 10400 match(Set result (HasNegatives ary1 len)); 10401 effect(TEMP_DEF result, USE_KILL ary1, TEMP oddReg, TEMP evenReg, TEMP tmp, KILL cr); // R0, R1 are killed, too. 10402 ins_cost(300); 10403 format %{ "has negatives byte[] $ary1($len) -> $result" %} 10404 ins_encode %{ 10405 __ has_negatives($result$$Register, $ary1$$Register, $len$$Register, 10406 $oddReg$$Register, $evenReg$$Register, $tmp$$Register); 10407 %} 10408 ins_pipe(pipe_class_dummy); 10409 %} 10410 10411 // encode char[] to byte[] in ISO_8859_1 10412 instruct encode_iso_array(iRegP src, iRegP dst, iRegI result, iRegI len, iRegI tmp, flagsReg cr) %{ 10413 match(Set result (EncodeISOArray src (Binary dst len))); 10414 effect(TEMP_DEF result, TEMP tmp, KILL cr); // R0, R1 are killed, too. 10415 ins_cost(300); 10416 format %{ "Encode array $src->$dst($len) -> $result" %} 10417 ins_encode %{ 10418 __ string_compress($result$$Register, $src$$Register, $dst$$Register, $len$$Register, 10419 $tmp$$Register, true); 10420 %} 10421 ins_pipe(pipe_class_dummy); 10422 %} 10423 10424 10425 //----------PEEPHOLE RULES----------------------------------------------------- 10426 // These must follow all instruction definitions as they use the names 10427 // defined in the instructions definitions. 10428 // 10429 // peepmatch (root_instr_name [preceeding_instruction]*); 10430 // 10431 // peepconstraint %{ 10432 // (instruction_number.operand_name relational_op instruction_number.operand_name 10433 // [, ...]); 10434 // // instruction numbers are zero-based using left to right order in peepmatch 10435 // 10436 // peepreplace (instr_name([instruction_number.operand_name]*)); 10437 // // provide an instruction_number.operand_name for each operand that appears 10438 // // in the replacement instruction's match rule 10439 // 10440 // ---------VM FLAGS--------------------------------------------------------- 10441 // 10442 // All peephole optimizations can be turned off using -XX:-OptoPeephole 10443 // 10444 // Each peephole rule is given an identifying number starting with zero and 10445 // increasing by one in the order seen by the parser. An individual peephole 10446 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=# 10447 // on the command-line. 10448 // 10449 // ---------CURRENT LIMITATIONS---------------------------------------------- 10450 // 10451 // Only match adjacent instructions in same basic block 10452 // Only equality constraints 10453 // Only constraints between operands, not (0.dest_reg == EAX_enc) 10454 // Only one replacement instruction 10455 // 10456 // ---------EXAMPLE---------------------------------------------------------- 10457 // 10458 // // pertinent parts of existing instructions in architecture description 10459 // instruct movI(eRegI dst, eRegI src) %{ 10460 // match(Set dst (CopyI src)); 10461 // %} 10462 // 10463 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{ 10464 // match(Set dst (AddI dst src)); 10465 // effect(KILL cr); 10466 // %} 10467 // 10468 // // Change (inc mov) to lea 10469 // peephole %{ 10470 // // increment preceeded by register-register move 10471 // peepmatch (incI_eReg movI); 10472 // // require that the destination register of the increment 10473 // // match the destination register of the move 10474 // peepconstraint (0.dst == 1.dst); 10475 // // construct a replacement instruction that sets 10476 // // the destination to (move's source register + one) 10477 // peepreplace (leaI_eReg_immI(0.dst 1.src 0.src)); 10478 // %} 10479 // 10480 // Implementation no longer uses movX instructions since 10481 // machine-independent system no longer uses CopyX nodes. 10482 // 10483 // peephole %{ 10484 // peepmatch (incI_eReg movI); 10485 // peepconstraint (0.dst == 1.dst); 10486 // peepreplace (leaI_eReg_immI(0.dst 1.src 0.src)); 10487 // %} 10488 // 10489 // peephole %{ 10490 // peepmatch (decI_eReg movI); 10491 // peepconstraint (0.dst == 1.dst); 10492 // peepreplace (leaI_eReg_immI(0.dst 1.src 0.src)); 10493 // %} 10494 // 10495 // peephole %{ 10496 // peepmatch (addI_eReg_imm movI); 10497 // peepconstraint (0.dst == 1.dst); 10498 // peepreplace (leaI_eReg_immI(0.dst 1.src 0.src)); 10499 // %} 10500 // 10501 // peephole %{ 10502 // peepmatch (addP_eReg_imm movP); 10503 // peepconstraint (0.dst == 1.dst); 10504 // peepreplace (leaP_eReg_immI(0.dst 1.src 0.src)); 10505 // %} 10506 10507 10508 // This peephole rule does not work, probably because ADLC can't handle two effects: 10509 // Effect 1 is defining 0.op1 and effect 2 is setting CC 10510 // condense a load from memory and subsequent test for zero 10511 // into a single, more efficient ICM instruction. 10512 // peephole %{ 10513 // peepmatch (compI_iReg_imm0 loadI); 10514 // peepconstraint (1.dst == 0.op1); 10515 // peepreplace (loadtest15_iReg_mem(0.op1 0.op1 1.mem)); 10516 // %} 10517 10518 // // Change load of spilled value to only a spill 10519 // instruct storeI(memory mem, eRegI src) %{ 10520 // match(Set mem (StoreI mem src)); 10521 // %} 10522 // 10523 // instruct loadI(eRegI dst, memory mem) %{ 10524 // match(Set dst (LoadI mem)); 10525 // %} 10526 // 10527 peephole %{ 10528 peepmatch (loadI storeI); 10529 peepconstraint (1.src == 0.dst, 1.mem == 0.mem); 10530 peepreplace (storeI(1.mem 1.mem 1.src)); 10531 %} 10532 10533 peephole %{ 10534 peepmatch (loadL storeL); 10535 peepconstraint (1.src == 0.dst, 1.mem == 0.mem); 10536 peepreplace (storeL(1.mem 1.mem 1.src)); 10537 %} 10538 10539 peephole %{ 10540 peepmatch (loadP storeP); 10541 peepconstraint (1.src == 0.dst, 1.dst == 0.mem); 10542 peepreplace (storeP(1.dst 1.dst 1.src)); 10543 %} 10544 10545 //----------SUPERWORD RULES--------------------------------------------------- 10546 10547 // Expand rules for special cases 10548 10549 instruct expand_storeF(stackSlotF mem, regF src) %{ 10550 // No match rule, false predicate, for expand only. 10551 effect(DEF mem, USE src); 10552 predicate(false); 10553 ins_cost(MEMORY_REF_COST); 10554 // TODO: s390 port size(FIXED_SIZE); 10555 format %{ "STE $src,$mem\t # replicate(float2stack)" %} 10556 opcode(STE_ZOPC, STE_ZOPC); 10557 ins_encode(z_form_rt_mem(src, mem)); 10558 ins_pipe(pipe_class_dummy); 10559 %} 10560 10561 instruct expand_LoadLogical_I2L(iRegL dst, stackSlotF mem) %{ 10562 // No match rule, false predicate, for expand only. 10563 effect(DEF dst, USE mem); 10564 predicate(false); 10565 ins_cost(MEMORY_REF_COST); 10566 // TODO: s390 port size(FIXED_SIZE); 10567 format %{ "LLGF $dst,$mem\t # replicate(stack2reg(unsigned))" %} 10568 opcode(LLGF_ZOPC, LLGF_ZOPC); 10569 ins_encode(z_form_rt_mem(dst, mem)); 10570 ins_pipe(pipe_class_dummy); 10571 %} 10572 10573 // Replicate scalar int to packed int values (8 Bytes) 10574 instruct expand_Repl2I_reg(iRegL dst, iRegL src) %{ 10575 // Dummy match rule, false predicate, for expand only. 10576 match(Set dst (ConvI2L src)); 10577 predicate(false); 10578 ins_cost(DEFAULT_COST); 10579 // TODO: s390 port size(FIXED_SIZE); 10580 format %{ "REPLIC2F $dst,$src\t # replicate(pack2F)" %} 10581 ins_encode %{ 10582 if ($dst$$Register == $src$$Register) { 10583 __ z_sllg(Z_R0_scratch, $src$$Register, 64-32); 10584 __ z_ogr($dst$$Register, Z_R0_scratch); 10585 } else { 10586 __ z_sllg($dst$$Register, $src$$Register, 64-32); 10587 __ z_ogr( $dst$$Register, $src$$Register); 10588 } 10589 %} 10590 ins_pipe(pipe_class_dummy); 10591 %} 10592 10593 // Replication 10594 10595 // Exploit rotate_then_insert, if available 10596 // Replicate scalar byte to packed byte values (8 Bytes). 10597 instruct Repl8B_reg_risbg(iRegL dst, iRegI src, flagsReg cr) %{ 10598 match(Set dst (ReplicateB src)); 10599 effect(KILL cr); 10600 predicate((n->as_Vector()->length() == 8)); 10601 format %{ "REPLIC8B $dst,$src\t # pack8B" %} 10602 ins_encode %{ 10603 if ($dst$$Register != $src$$Register) { 10604 __ z_lgr($dst$$Register, $src$$Register); 10605 } 10606 __ rotate_then_insert($dst$$Register, $dst$$Register, 48, 55, 8, false); 10607 __ rotate_then_insert($dst$$Register, $dst$$Register, 32, 47, 16, false); 10608 __ rotate_then_insert($dst$$Register, $dst$$Register, 0, 31, 32, false); 10609 %} 10610 ins_pipe(pipe_class_dummy); 10611 %} 10612 10613 // Replicate scalar byte to packed byte values (8 Bytes). 10614 instruct Repl8B_imm(iRegL dst, immB_n0m1 src) %{ 10615 match(Set dst (ReplicateB src)); 10616 predicate(n->as_Vector()->length() == 8); 10617 ins_should_rematerialize(true); 10618 format %{ "REPLIC8B $dst,$src\t # pack8B imm" %} 10619 ins_encode %{ 10620 int64_t Isrc8 = $src$$constant & 0x000000ff; 10621 int64_t Isrc16 = Isrc8 << 8 | Isrc8; 10622 int64_t Isrc32 = Isrc16 << 16 | Isrc16; 10623 assert(Isrc8 != 0x000000ff && Isrc8 != 0, "should be handled by other match rules."); 10624 10625 __ z_llilf($dst$$Register, Isrc32); 10626 __ z_iihf($dst$$Register, Isrc32); 10627 %} 10628 ins_pipe(pipe_class_dummy); 10629 %} 10630 10631 // Replicate scalar byte to packed byte values (8 Bytes). 10632 instruct Repl8B_imm0(iRegL dst, immI_0 src) %{ 10633 match(Set dst (ReplicateB src)); 10634 predicate(n->as_Vector()->length() == 8); 10635 ins_should_rematerialize(true); 10636 format %{ "REPLIC8B $dst,$src\t # pack8B imm0" %} 10637 ins_encode %{ __ z_laz($dst$$Register, 0, Z_R0); %} 10638 ins_pipe(pipe_class_dummy); 10639 %} 10640 10641 // Replicate scalar byte to packed byte values (8 Bytes). 10642 instruct Repl8B_immm1(iRegL dst, immB_minus1 src) %{ 10643 match(Set dst (ReplicateB src)); 10644 predicate(n->as_Vector()->length() == 8); 10645 ins_should_rematerialize(true); 10646 format %{ "REPLIC8B $dst,$src\t # pack8B immm1" %} 10647 ins_encode %{ __ z_lghi($dst$$Register, -1); %} 10648 ins_pipe(pipe_class_dummy); 10649 %} 10650 10651 // Exploit rotate_then_insert, if available 10652 // Replicate scalar short to packed short values (8 Bytes). 10653 instruct Repl4S_reg_risbg(iRegL dst, iRegI src, flagsReg cr) %{ 10654 match(Set dst (ReplicateS src)); 10655 effect(KILL cr); 10656 predicate((n->as_Vector()->length() == 4)); 10657 format %{ "REPLIC4S $dst,$src\t # pack4S" %} 10658 ins_encode %{ 10659 if ($dst$$Register != $src$$Register) { 10660 __ z_lgr($dst$$Register, $src$$Register); 10661 } 10662 __ rotate_then_insert($dst$$Register, $dst$$Register, 32, 47, 16, false); 10663 __ rotate_then_insert($dst$$Register, $dst$$Register, 0, 31, 32, false); 10664 %} 10665 ins_pipe(pipe_class_dummy); 10666 %} 10667 10668 // Replicate scalar short to packed short values (8 Bytes). 10669 instruct Repl4S_imm(iRegL dst, immS_n0m1 src) %{ 10670 match(Set dst (ReplicateS src)); 10671 predicate(n->as_Vector()->length() == 4); 10672 ins_should_rematerialize(true); 10673 format %{ "REPLIC4S $dst,$src\t # pack4S imm" %} 10674 ins_encode %{ 10675 int64_t Isrc16 = $src$$constant & 0x0000ffff; 10676 int64_t Isrc32 = Isrc16 << 16 | Isrc16; 10677 assert(Isrc16 != 0x0000ffff && Isrc16 != 0, "Repl4S_imm: (src == " INT64_FORMAT 10678 ") should be handled by other match rules.", $src$$constant); 10679 10680 __ z_llilf($dst$$Register, Isrc32); 10681 __ z_iihf($dst$$Register, Isrc32); 10682 %} 10683 ins_pipe(pipe_class_dummy); 10684 %} 10685 10686 // Replicate scalar short to packed short values (8 Bytes). 10687 instruct Repl4S_imm0(iRegL dst, immI_0 src) %{ 10688 match(Set dst (ReplicateS src)); 10689 predicate(n->as_Vector()->length() == 4); 10690 ins_should_rematerialize(true); 10691 format %{ "REPLIC4S $dst,$src\t # pack4S imm0" %} 10692 ins_encode %{ __ z_laz($dst$$Register, 0, Z_R0); %} 10693 ins_pipe(pipe_class_dummy); 10694 %} 10695 10696 // Replicate scalar short to packed short values (8 Bytes). 10697 instruct Repl4S_immm1(iRegL dst, immS_minus1 src) %{ 10698 match(Set dst (ReplicateS src)); 10699 predicate(n->as_Vector()->length() == 4); 10700 ins_should_rematerialize(true); 10701 format %{ "REPLIC4S $dst,$src\t # pack4S immm1" %} 10702 ins_encode %{ __ z_lghi($dst$$Register, -1); %} 10703 ins_pipe(pipe_class_dummy); 10704 %} 10705 10706 // Exploit rotate_then_insert, if available. 10707 // Replicate scalar int to packed int values (8 Bytes). 10708 instruct Repl2I_reg_risbg(iRegL dst, iRegI src, flagsReg cr) %{ 10709 match(Set dst (ReplicateI src)); 10710 effect(KILL cr); 10711 predicate((n->as_Vector()->length() == 2)); 10712 format %{ "REPLIC2I $dst,$src\t # pack2I" %} 10713 ins_encode %{ 10714 if ($dst$$Register != $src$$Register) { 10715 __ z_lgr($dst$$Register, $src$$Register); 10716 } 10717 __ rotate_then_insert($dst$$Register, $dst$$Register, 0, 31, 32, false); 10718 %} 10719 ins_pipe(pipe_class_dummy); 10720 %} 10721 10722 // Replicate scalar int to packed int values (8 Bytes). 10723 instruct Repl2I_imm(iRegL dst, immI_n0m1 src) %{ 10724 match(Set dst (ReplicateI src)); 10725 predicate(n->as_Vector()->length() == 2); 10726 ins_should_rematerialize(true); 10727 format %{ "REPLIC2I $dst,$src\t # pack2I imm" %} 10728 ins_encode %{ 10729 int64_t Isrc32 = $src$$constant; 10730 assert(Isrc32 != -1 && Isrc32 != 0, "should be handled by other match rules."); 10731 10732 __ z_llilf($dst$$Register, Isrc32); 10733 __ z_iihf($dst$$Register, Isrc32); 10734 %} 10735 ins_pipe(pipe_class_dummy); 10736 %} 10737 10738 // Replicate scalar int to packed int values (8 Bytes). 10739 instruct Repl2I_imm0(iRegL dst, immI_0 src) %{ 10740 match(Set dst (ReplicateI src)); 10741 predicate(n->as_Vector()->length() == 2); 10742 ins_should_rematerialize(true); 10743 format %{ "REPLIC2I $dst,$src\t # pack2I imm0" %} 10744 ins_encode %{ __ z_laz($dst$$Register, 0, Z_R0); %} 10745 ins_pipe(pipe_class_dummy); 10746 %} 10747 10748 // Replicate scalar int to packed int values (8 Bytes). 10749 instruct Repl2I_immm1(iRegL dst, immI_minus1 src) %{ 10750 match(Set dst (ReplicateI src)); 10751 predicate(n->as_Vector()->length() == 2); 10752 ins_should_rematerialize(true); 10753 format %{ "REPLIC2I $dst,$src\t # pack2I immm1" %} 10754 ins_encode %{ __ z_lghi($dst$$Register, -1); %} 10755 ins_pipe(pipe_class_dummy); 10756 %} 10757 10758 // 10759 10760 instruct Repl2F_reg_indirect(iRegL dst, regF src, flagsReg cr) %{ 10761 match(Set dst (ReplicateF src)); 10762 effect(KILL cr); 10763 predicate(!VM_Version::has_FPSupportEnhancements() && n->as_Vector()->length() == 2); 10764 format %{ "REPLIC2F $dst,$src\t # pack2F indirect" %} 10765 expand %{ 10766 stackSlotF tmp; 10767 iRegL tmp2; 10768 expand_storeF(tmp, src); 10769 expand_LoadLogical_I2L(tmp2, tmp); 10770 expand_Repl2I_reg(dst, tmp2); 10771 %} 10772 %} 10773 10774 // Replicate scalar float to packed float values in GREG (8 Bytes). 10775 instruct Repl2F_reg_direct(iRegL dst, regF src, flagsReg cr) %{ 10776 match(Set dst (ReplicateF src)); 10777 effect(KILL cr); 10778 predicate(VM_Version::has_FPSupportEnhancements() && n->as_Vector()->length() == 2); 10779 format %{ "REPLIC2F $dst,$src\t # pack2F direct" %} 10780 ins_encode %{ 10781 assert(VM_Version::has_FPSupportEnhancements(), "encoder should never be called on old H/W"); 10782 __ z_lgdr($dst$$Register, $src$$FloatRegister); 10783 10784 __ z_srlg(Z_R0_scratch, $dst$$Register, 32); // Floats are left-justified in 64bit reg. 10785 __ z_iilf($dst$$Register, 0); // Save a "result not ready" stall. 10786 __ z_ogr($dst$$Register, Z_R0_scratch); 10787 %} 10788 ins_pipe(pipe_class_dummy); 10789 %} 10790 10791 // Replicate scalar float immediate to packed float values in GREG (8 Bytes). 10792 instruct Repl2F_imm(iRegL dst, immF src) %{ 10793 match(Set dst (ReplicateF src)); 10794 predicate(n->as_Vector()->length() == 2); 10795 ins_should_rematerialize(true); 10796 format %{ "REPLIC2F $dst,$src\t # pack2F imm" %} 10797 ins_encode %{ 10798 union { 10799 int Isrc32; 10800 float Fsrc32; 10801 }; 10802 Fsrc32 = $src$$constant; 10803 __ z_llilf($dst$$Register, Isrc32); 10804 __ z_iihf($dst$$Register, Isrc32); 10805 %} 10806 ins_pipe(pipe_class_dummy); 10807 %} 10808 10809 // Replicate scalar float immediate zeroes to packed float values in GREG (8 Bytes). 10810 // Do this only for 'real' zeroes, especially don't loose sign of negative zeroes. 10811 instruct Repl2F_imm0(iRegL dst, immFp0 src) %{ 10812 match(Set dst (ReplicateF src)); 10813 predicate(n->as_Vector()->length() == 2); 10814 ins_should_rematerialize(true); 10815 format %{ "REPLIC2F $dst,$src\t # pack2F imm0" %} 10816 ins_encode %{ __ z_laz($dst$$Register, 0, Z_R0); %} 10817 ins_pipe(pipe_class_dummy); 10818 %} 10819 10820 // Store 10821 10822 // Store Aligned Packed Byte register to memory (8 Bytes). 10823 instruct storeA8B(memory mem, iRegL src) %{ 10824 match(Set mem (StoreVector mem src)); 10825 predicate(n->as_StoreVector()->memory_size() == 8); 10826 ins_cost(MEMORY_REF_COST); 10827 // TODO: s390 port size(VARIABLE_SIZE); 10828 format %{ "STG $src,$mem\t # ST(packed8B)" %} 10829 opcode(STG_ZOPC, STG_ZOPC); 10830 ins_encode(z_form_rt_mem_opt(src, mem)); 10831 ins_pipe(pipe_class_dummy); 10832 %} 10833 10834 // Load 10835 10836 instruct loadV8(iRegL dst, memory mem) %{ 10837 match(Set dst (LoadVector mem)); 10838 predicate(n->as_LoadVector()->memory_size() == 8); 10839 ins_cost(MEMORY_REF_COST); 10840 // TODO: s390 port size(VARIABLE_SIZE); 10841 format %{ "LG $dst,$mem\t # L(packed8B)" %} 10842 opcode(LG_ZOPC, LG_ZOPC); 10843 ins_encode(z_form_rt_mem_opt(dst, mem)); 10844 ins_pipe(pipe_class_dummy); 10845 %} 10846 10847 //----------POPULATION COUNT RULES-------------------------------------------- 10848 10849 // Byte reverse 10850 10851 instruct bytes_reverse_int(iRegI dst, iRegI src) %{ 10852 match(Set dst (ReverseBytesI src)); 10853 predicate(UseByteReverseInstruction); // See Matcher::match_rule_supported 10854 ins_cost(DEFAULT_COST); 10855 size(4); 10856 format %{ "LRVR $dst,$src\t # byte reverse int" %} 10857 opcode(LRVR_ZOPC); 10858 ins_encode(z_rreform(dst, src)); 10859 ins_pipe(pipe_class_dummy); 10860 %} 10861 10862 instruct bytes_reverse_long(iRegL dst, iRegL src) %{ 10863 match(Set dst (ReverseBytesL src)); 10864 predicate(UseByteReverseInstruction); // See Matcher::match_rule_supported 10865 ins_cost(DEFAULT_COST); 10866 // TODO: s390 port size(FIXED_SIZE); 10867 format %{ "LRVGR $dst,$src\t # byte reverse long" %} 10868 opcode(LRVGR_ZOPC); 10869 ins_encode(z_rreform(dst, src)); 10870 ins_pipe(pipe_class_dummy); 10871 %} 10872 10873 // Leading zeroes 10874 10875 // The instruction FLOGR (Find Leftmost One in Grande (64bit) Register) 10876 // returns the bit position of the leftmost 1 in the 64bit source register. 10877 // As the bits are numbered from left to right (0..63), the returned 10878 // position index is equivalent to the number of leading zeroes. 10879 // If no 1-bit is found (i.e. the regsiter contains zero), the instruction 10880 // returns position 64. That's exactly what we need. 10881 10882 instruct countLeadingZerosI(revenRegI dst, iRegI src, roddRegI tmp, flagsReg cr) %{ 10883 match(Set dst (CountLeadingZerosI src)); 10884 effect(KILL tmp, KILL cr); 10885 ins_cost(3 * DEFAULT_COST); 10886 size(14); 10887 format %{ "SLLG $dst,$src,32\t # no need to always count 32 zeroes first\n\t" 10888 "IILH $dst,0x8000 \t # insert \"stop bit\" to force result 32 for zero src.\n\t" 10889 "FLOGR $dst,$dst" 10890 %} 10891 ins_encode %{ 10892 // Performance experiments indicate that "FLOGR" is using some kind of 10893 // iteration to find the leftmost "1" bit. 10894 // 10895 // The prior implementation zero-extended the 32-bit argument to 64 bit, 10896 // thus forcing "FLOGR" to count 32 bits of which we know they are zero. 10897 // We could gain measurable speedup in micro benchmark: 10898 // 10899 // leading trailing 10900 // z10: int 2.04 1.68 10901 // long 1.00 1.02 10902 // z196: int 0.99 1.23 10903 // long 1.00 1.11 10904 // 10905 // By shifting the argument into the high-word instead of zero-extending it. 10906 // The add'l branch on condition (taken for a zero argument, very infrequent, 10907 // good prediction) is well compensated for by the savings. 10908 // 10909 // We leave the previous implementation in for some time in the future when 10910 // the "FLOGR" instruction may become less iterative. 10911 10912 // Version 2: shows 62%(z9), 204%(z10), -1%(z196) improvement over original 10913 __ z_sllg($dst$$Register, $src$$Register, 32); // No need to always count 32 zeroes first. 10914 __ z_iilh($dst$$Register, 0x8000); // Insert "stop bit" to force result 32 for zero src. 10915 __ z_flogr($dst$$Register, $dst$$Register); 10916 %} 10917 ins_pipe(pipe_class_dummy); 10918 %} 10919 10920 instruct countLeadingZerosL(revenRegI dst, iRegL src, roddRegI tmp, flagsReg cr) %{ 10921 match(Set dst (CountLeadingZerosL src)); 10922 effect(KILL tmp, KILL cr); 10923 ins_cost(DEFAULT_COST); 10924 size(4); 10925 format %{ "FLOGR $dst,$src \t # count leading zeros (long)\n\t" %} 10926 ins_encode %{ __ z_flogr($dst$$Register, $src$$Register); %} 10927 ins_pipe(pipe_class_dummy); 10928 %} 10929 10930 // trailing zeroes 10931 10932 // We transform the trailing zeroes problem to a leading zeroes problem 10933 // such that can use the FLOGR instruction to our advantage. 10934 10935 // With 10936 // tmp1 = src - 1 10937 // we flip all trailing zeroes to ones and the rightmost one to zero. 10938 // All other bits remain unchanged. 10939 // With the complement 10940 // tmp2 = ~src 10941 // we get all ones in the trailing zeroes positions. Thus, 10942 // tmp3 = tmp1 & tmp2 10943 // yields ones in the trailing zeroes positions and zeroes elsewhere. 10944 // Now we can apply FLOGR and get 64-(trailing zeroes). 10945 instruct countTrailingZerosI(revenRegI dst, iRegI src, roddRegI tmp, flagsReg cr) %{ 10946 match(Set dst (CountTrailingZerosI src)); 10947 effect(TEMP_DEF dst, TEMP tmp, KILL cr); 10948 ins_cost(8 * DEFAULT_COST); 10949 // TODO: s390 port size(FIXED_SIZE); // Emitted code depends on PreferLAoverADD being on/off. 10950 format %{ "LLGFR $dst,$src \t # clear upper 32 bits (we are dealing with int)\n\t" 10951 "LCGFR $tmp,$src \t # load 2's complement (32->64 bit)\n\t" 10952 "AGHI $dst,-1 \t # tmp1 = src-1\n\t" 10953 "AGHI $tmp,-1 \t # tmp2 = -src-1 = ~src\n\t" 10954 "NGR $dst,$tmp \t # tmp3 = tmp1&tmp2\n\t" 10955 "FLOGR $dst,$dst \t # count trailing zeros (int)\n\t" 10956 "AHI $dst,-64 \t # tmp4 = 64-(trailing zeroes)-64\n\t" 10957 "LCR $dst,$dst \t # res = -tmp4" 10958 %} 10959 ins_encode %{ 10960 Register Rdst = $dst$$Register; 10961 Register Rsrc = $src$$Register; 10962 // Rtmp only needed for for zero-argument shortcut. With kill effect in 10963 // match rule Rsrc = roddReg would be possible, saving one register. 10964 Register Rtmp = $tmp$$Register; 10965 10966 assert_different_registers(Rdst, Rsrc, Rtmp); 10967 10968 // Algorithm: 10969 // - Isolate the least significant (rightmost) set bit using (src & (-src)). 10970 // All other bits in the result are zero. 10971 // - Find the "leftmost one" bit position in the single-bit result from previous step. 10972 // - 63-("leftmost one" bit position) gives the # of trailing zeros. 10973 10974 // Version 2: shows 79%(z9), 68%(z10), 23%(z196) improvement over original. 10975 Label done; 10976 __ load_const_optimized(Rdst, 32); // Prepare for shortcut (zero argument), result will be 32. 10977 __ z_lcgfr(Rtmp, Rsrc); 10978 __ z_bre(done); // Taken very infrequently, good prediction, no BHT entry. 10979 10980 __ z_nr(Rtmp, Rsrc); // (src) & (-src) leaves nothing but least significant bit. 10981 __ z_ahi(Rtmp, -1); // Subtract one to fill all trailing zero positions with ones. 10982 // Use 32bit op to prevent borrow propagation (case Rdst = 0x80000000) 10983 // into upper half of reg. Not relevant with sllg below. 10984 __ z_sllg(Rdst, Rtmp, 32); // Shift interesting contents to upper half of register. 10985 __ z_bre(done); // Shortcut for argument = 1, result will be 0. 10986 // Depends on CC set by ahi above. 10987 // Taken very infrequently, good prediction, no BHT entry. 10988 // Branch delayed to have Rdst set correctly (Rtmp == 0(32bit) 10989 // after SLLG Rdst == 0(64bit)). 10990 __ z_flogr(Rdst, Rdst); // Kills tmp which is the oddReg for dst. 10991 __ add2reg(Rdst, -32); // 32-pos(leftmost1) is #trailing zeros 10992 __ z_lcgfr(Rdst, Rdst); // Provide 64bit result at no cost. 10993 __ bind(done); 10994 %} 10995 ins_pipe(pipe_class_dummy); 10996 %} 10997 10998 instruct countTrailingZerosL(revenRegI dst, iRegL src, roddRegL tmp, flagsReg cr) %{ 10999 match(Set dst (CountTrailingZerosL src)); 11000 effect(TEMP_DEF dst, KILL tmp, KILL cr); 11001 ins_cost(8 * DEFAULT_COST); 11002 // TODO: s390 port size(FIXED_SIZE); // Emitted code depends on PreferLAoverADD being on/off. 11003 format %{ "LCGR $dst,$src \t # preserve src\n\t" 11004 "NGR $dst,$src \t #\n\t" 11005 "AGHI $dst,-1 \t # tmp1 = src-1\n\t" 11006 "FLOGR $dst,$dst \t # count trailing zeros (long), kill $tmp\n\t" 11007 "AHI $dst,-64 \t # tmp4 = 64-(trailing zeroes)-64\n\t" 11008 "LCR $dst,$dst \t #" 11009 %} 11010 ins_encode %{ 11011 Register Rdst = $dst$$Register; 11012 Register Rsrc = $src$$Register; 11013 assert_different_registers(Rdst, Rsrc); // Rtmp == Rsrc allowed. 11014 11015 // New version: shows 5%(z9), 2%(z10), 11%(z196) improvement over original. 11016 __ z_lcgr(Rdst, Rsrc); 11017 __ z_ngr(Rdst, Rsrc); 11018 __ add2reg(Rdst, -1); 11019 __ z_flogr(Rdst, Rdst); // Kills tmp which is the oddReg for dst. 11020 __ add2reg(Rdst, -64); 11021 __ z_lcgfr(Rdst, Rdst); // Provide 64bit result at no cost. 11022 %} 11023 ins_pipe(pipe_class_dummy); 11024 %} 11025 11026 11027 // bit count 11028 11029 instruct popCountI(iRegI dst, iRegI src, iRegI tmp, flagsReg cr) %{ 11030 match(Set dst (PopCountI src)); 11031 effect(TEMP_DEF dst, TEMP tmp, KILL cr); 11032 predicate(UsePopCountInstruction && VM_Version::has_PopCount()); 11033 ins_cost(DEFAULT_COST); 11034 size(24); 11035 format %{ "POPCNT $dst,$src\t # pop count int" %} 11036 ins_encode %{ 11037 Register Rdst = $dst$$Register; 11038 Register Rsrc = $src$$Register; 11039 Register Rtmp = $tmp$$Register; 11040 11041 // Prefer compile-time assertion over run-time SIGILL. 11042 assert(VM_Version::has_PopCount(), "bad predicate for countLeadingZerosI"); 11043 assert_different_registers(Rdst, Rtmp); 11044 11045 // Version 2: shows 10%(z196) improvement over original. 11046 __ z_popcnt(Rdst, Rsrc); 11047 __ z_srlg(Rtmp, Rdst, 16); // calc byte4+byte6 and byte5+byte7 11048 __ z_alr(Rdst, Rtmp); // into byte6 and byte7 11049 __ z_srlg(Rtmp, Rdst, 8); // calc (byte4+byte6) + (byte5+byte7) 11050 __ z_alr(Rdst, Rtmp); // into byte7 11051 __ z_llgcr(Rdst, Rdst); // zero-extend sum 11052 %} 11053 ins_pipe(pipe_class_dummy); 11054 %} 11055 11056 instruct popCountL(iRegI dst, iRegL src, iRegL tmp, flagsReg cr) %{ 11057 match(Set dst (PopCountL src)); 11058 effect(TEMP_DEF dst, TEMP tmp, KILL cr); 11059 predicate(UsePopCountInstruction && VM_Version::has_PopCount()); 11060 ins_cost(DEFAULT_COST); 11061 // TODO: s390 port size(FIXED_SIZE); 11062 format %{ "POPCNT $dst,$src\t # pop count long" %} 11063 ins_encode %{ 11064 Register Rdst = $dst$$Register; 11065 Register Rsrc = $src$$Register; 11066 Register Rtmp = $tmp$$Register; 11067 11068 // Prefer compile-time assertion over run-time SIGILL. 11069 assert(VM_Version::has_PopCount(), "bad predicate for countLeadingZerosI"); 11070 assert_different_registers(Rdst, Rtmp); 11071 11072 // Original version. Using LA instead of algr seems to be a really bad idea (-35%). 11073 __ z_popcnt(Rdst, Rsrc); 11074 __ z_ahhlr(Rdst, Rdst, Rdst); 11075 __ z_sllg(Rtmp, Rdst, 16); 11076 __ z_algr(Rdst, Rtmp); 11077 __ z_sllg(Rtmp, Rdst, 8); 11078 __ z_algr(Rdst, Rtmp); 11079 __ z_srlg(Rdst, Rdst, 56); 11080 %} 11081 ins_pipe(pipe_class_dummy); 11082 %} 11083 11084 //----------SMARTSPILL RULES--------------------------------------------------- 11085 // These must follow all instruction definitions as they use the names 11086 // defined in the instructions definitions. 11087 11088 // ============================================================================ 11089 // TYPE PROFILING RULES