src/hotspot/cpu/aarch64/aarch64.ad

*** 92,13 ***
  reg_def R5_H    ( SOC, SOC, Op_RegI,  5, r5->as_VMReg()->next() );
  reg_def R6      ( SOC, SOC, Op_RegI,  6, r6->as_VMReg()         );
  reg_def R6_H    ( SOC, SOC, Op_RegI,  6, r6->as_VMReg()->next() );
  reg_def R7      ( SOC, SOC, Op_RegI,  7, r7->as_VMReg()         );
  reg_def R7_H    ( SOC, SOC, Op_RegI,  7, r7->as_VMReg()->next() );
! reg_def R8      ( NS,  SOC, Op_RegI,  8, r8->as_VMReg()         );
  reg_def R8_H    ( NS,  SOC, Op_RegI,  8, r8->as_VMReg()->next() );
! reg_def R9      ( NS,  SOC, Op_RegI,  9, r9->as_VMReg()         );
  reg_def R9_H    ( NS,  SOC, Op_RegI,  9, r9->as_VMReg()->next() );
  reg_def R10     ( SOC, SOC, Op_RegI, 10, r10->as_VMReg()        );
  reg_def R10_H   ( SOC, SOC, Op_RegI, 10, r10->as_VMReg()->next());
  reg_def R11     ( SOC, SOC, Op_RegI, 11, r11->as_VMReg()        );
  reg_def R11_H   ( SOC, SOC, Op_RegI, 11, r11->as_VMReg()->next());
--- 92,13 ---
  reg_def R5_H    ( SOC, SOC, Op_RegI,  5, r5->as_VMReg()->next() );
  reg_def R6      ( SOC, SOC, Op_RegI,  6, r6->as_VMReg()         );
  reg_def R6_H    ( SOC, SOC, Op_RegI,  6, r6->as_VMReg()->next() );
  reg_def R7      ( SOC, SOC, Op_RegI,  7, r7->as_VMReg()         );
  reg_def R7_H    ( SOC, SOC, Op_RegI,  7, r7->as_VMReg()->next() );
! reg_def R8      ( NS,  SOC, Op_RegI,  8, r8->as_VMReg()         ); // rscratch1, non-allocatable
  reg_def R8_H    ( NS,  SOC, Op_RegI,  8, r8->as_VMReg()->next() );
! reg_def R9      ( NS,  SOC, Op_RegI,  9, r9->as_VMReg()         ); // rscratch2, non-allocatable
  reg_def R9_H    ( NS,  SOC, Op_RegI,  9, r9->as_VMReg()->next() );
  reg_def R10     ( SOC, SOC, Op_RegI, 10, r10->as_VMReg()        );
  reg_def R10_H   ( SOC, SOC, Op_RegI, 10, r10->as_VMReg()->next());
  reg_def R11     ( SOC, SOC, Op_RegI, 11, r11->as_VMReg()        );
  reg_def R11_H   ( SOC, SOC, Op_RegI, 11, r11->as_VMReg()->next());

*** 166,14 ***
  // v16-v31 are SOC as per the platform spec
  
  // For SVE vector registers, we simply extend vector register size to 8
  // slots. A vector register with lower 4 slots, denotes a 128-bit vector
  // NEON vector register. While a vector register with whole 8 slots,
! // indicating an SVE vector register with vector size >= 128 bits
! // (128 ~ 2048 bits, multiple of 128 bits). A 128-bit SVE vector
  // register also has 8 slots, but the the actual size is 128 bits, the
! // same as a NEON vector register.
  
    reg_def V0   ( SOC, SOC, Op_RegF, 0, v0->as_VMReg()          );
    reg_def V0_H ( SOC, SOC, Op_RegF, 0, v0->as_VMReg()->next()  );
    reg_def V0_J ( SOC, SOC, Op_RegF, 0, v0->as_VMReg()->next(2) );
    reg_def V0_K ( SOC, SOC, Op_RegF, 0, v0->as_VMReg()->next(3) );
--- 166,17 ---
  // v16-v31 are SOC as per the platform spec
  
  // For SVE vector registers, we simply extend vector register size to 8
  // slots. A vector register with lower 4 slots, denotes a 128-bit vector
  // NEON vector register. While a vector register with whole 8 slots,
! // indicating an SVE scalable vector register with vector size >= 128
! // bits (128 ~ 2048 bits, multiple of 128 bits). A 128-bit SVE vector
  // register also has 8 slots, but the the actual size is 128 bits, the
! // same as a NEON vector register. Since during JIT compilation, the
+ // real SVE vector register size can be detected, so register allocator
+ // is able to do the right thing with the real register size, e.g. for
+ // spilling/unspilling.
  
    reg_def V0   ( SOC, SOC, Op_RegF, 0, v0->as_VMReg()          );
    reg_def V0_H ( SOC, SOC, Op_RegF, 0, v0->as_VMReg()->next()  );
    reg_def V0_J ( SOC, SOC, Op_RegF, 0, v0->as_VMReg()->next(2) );
    reg_def V0_K ( SOC, SOC, Op_RegF, 0, v0->as_VMReg()->next(3) );