1 /*
2 * Copyright (c) 1997, 2020, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2014, 2020 Red Hat Inc. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 */
24
25 #include <stdio.h>
26 #include <sys/types.h>
27
28 #include "precompiled.hpp"
29 #include "asm/assembler.hpp"
30 #include "asm/assembler.inline.hpp"
31 #include "interpreter/interpreter.hpp"
32
33 #ifndef PRODUCT
34 const uintptr_t Assembler::asm_bp = 0x00007fffee09ac88;
35 #endif
36
37 #include "compiler/disassembler.hpp"
38 #include "memory/resourceArea.hpp"
39 #include "runtime/interfaceSupport.inline.hpp"
40 #include "runtime/sharedRuntime.hpp"
41 #include "immediate_aarch64.hpp"
42
43 extern "C" void entry(CodeBuffer *cb);
44
45 #define __ _masm.
46 #ifdef PRODUCT
47 #define BLOCK_COMMENT(str) /* nothing */
48 #else
49 #define BLOCK_COMMENT(str) block_comment(str)
50 #endif
51
52 #define BIND(label) bind(label); __ BLOCK_COMMENT(#label ":")
53
54 static float unpack(unsigned value);
55
56 short Assembler::SIMD_Size_in_bytes[] = {
57 // T8B, T16B, T4H, T8H, T2S, T4S, T1D, T2D, T1Q
58 8, 16, 8, 16, 8, 16, 8, 16, 16
59 };
60
61 #ifdef ASSERT
62 static void asm_check(const unsigned int *insns, const unsigned int *insns1, size_t len) {
63 bool ok = true;
64 for (unsigned int i = 0; i < len; i++) {
65 if (insns[i] != insns1[i]) {
66 ok = false;
67 printf("Ours:\n");
68 Disassembler::decode((address)&insns1[i], (address)&insns1[i+1]);
69 printf("Theirs:\n");
70 Disassembler::decode((address)&insns[i], (address)&insns[i+1]);
71 printf("\n");
72 }
73 }
74 assert(ok, "Assembler smoke test failed");
75 }
76
77 void entry(CodeBuffer *cb) {
78
79 // {
80 // for (int i = 0; i < 256; i+=16)
81 // {
82 // printf("\"%20.20g\", ", unpack(i));
83 // printf("\"%20.20g\", ", unpack(i+1));
84 // }
85 // printf("\n");
86 // }
87
88 Assembler _masm(cb);
89 address entry = __ pc();
90
91 // Smoke test for assembler
92
93 // BEGIN Generated code -- do not edit
94 // Generated by aarch64-asmtest.py
95 Label back, forth;
96 __ bind(back);
97
98 // ArithOp
99 __ add(r26, r23, r13, Assembler::LSL, 32); // add x26, x23, x13, LSL #32
100 __ sub(r12, r24, r9, Assembler::LSR, 37); // sub x12, x24, x9, LSR #37
101 __ adds(r28, r15, r8, Assembler::ASR, 39); // adds x28, x15, x8, ASR #39
102 __ subs(r7, r28, r30, Assembler::ASR, 57); // subs x7, x28, x30, ASR #57
103 __ addw(r9, r22, r27, Assembler::ASR, 15); // add w9, w22, w27, ASR #15
104 __ subw(r3, r13, r18, Assembler::ASR, 30); // sub w3, w13, w18, ASR #30
105 __ addsw(r14, r26, r8, Assembler::ASR, 17); // adds w14, w26, w8, ASR #17
106 __ subsw(r0, r22, r12, Assembler::ASR, 21); // subs w0, w22, w12, ASR #21
107 __ andr(r0, r15, r26, Assembler::LSL, 20); // and x0, x15, x26, LSL #20
108 __ orr(r26, r5, r17, Assembler::LSL, 61); // orr x26, x5, x17, LSL #61
109 __ eor(r24, r13, r2, Assembler::LSL, 32); // eor x24, x13, x2, LSL #32
110 __ ands(r28, r3, r17, Assembler::ASR, 35); // ands x28, x3, x17, ASR #35
111 __ andw(r25, r16, r29, Assembler::LSR, 18); // and w25, w16, w29, LSR #18
112 __ orrw(r13, r18, r11, Assembler::LSR, 9); // orr w13, w18, w11, LSR #9
113 __ eorw(r5, r5, r18, Assembler::LSR, 15); // eor w5, w5, w18, LSR #15
114 __ andsw(r2, r23, r27, Assembler::ASR, 26); // ands w2, w23, w27, ASR #26
115 __ bic(r27, r28, r16, Assembler::LSR, 45); // bic x27, x28, x16, LSR #45
116 __ orn(r8, r25, r26, Assembler::ASR, 37); // orn x8, x25, x26, ASR #37
117 __ eon(r29, r17, r13, Assembler::LSR, 63); // eon x29, x17, x13, LSR #63
118 __ bics(r28, r24, r2, Assembler::LSR, 31); // bics x28, x24, x2, LSR #31
119 __ bicw(r19, r26, r7, Assembler::ASR, 3); // bic w19, w26, w7, ASR #3
120 __ ornw(r6, r24, r10, Assembler::ASR, 3); // orn w6, w24, w10, ASR #3
121 __ eonw(r4, r21, r1, Assembler::LSR, 29); // eon w4, w21, w1, LSR #29
122 __ bicsw(r16, r21, r0, Assembler::LSR, 19); // bics w16, w21, w0, LSR #19
123
124 // AddSubImmOp
125 __ addw(r17, r12, 379u); // add w17, w12, #379
126 __ addsw(r30, r1, 22u); // adds w30, w1, #22
127 __ subw(r29, r5, 126u); // sub w29, w5, #126
128 __ subsw(r6, r24, 960u); // subs w6, w24, #960
129 __ add(r0, r13, 104u); // add x0, x13, #104
130 __ adds(r8, r6, 663u); // adds x8, x6, #663
131 __ sub(r10, r5, 516u); // sub x10, x5, #516
132 __ subs(r1, r3, 1012u); // subs x1, x3, #1012
133
134 // LogicalImmOp
135 __ andw(r6, r11, 4294049777ull); // and w6, w11, #0xfff1fff1
136 __ orrw(r28, r5, 4294966791ull); // orr w28, w5, #0xfffffe07
137 __ eorw(r1, r20, 134217216ull); // eor w1, w20, #0x7fffe00
138 __ andsw(r7, r18, 1048576ull); // ands w7, w18, #0x100000
139 __ andr(r14, r12, 9223372036854775808ull); // and x14, x12, #0x8000000000000000
140 __ orr(r9, r11, 562675075514368ull); // orr x9, x11, #0x1ffc000000000
141 __ eor(r17, r0, 18014398509481728ull); // eor x17, x0, #0x3fffffffffff00
142 __ ands(r1, r8, 18446744073705357315ull); // ands x1, x8, #0xffffffffffc00003
143
144 // AbsOp
145 __ b(__ pc()); // b .
146 __ b(back); // b back
147 __ b(forth); // b forth
148 __ bl(__ pc()); // bl .
149 __ bl(back); // bl back
150 __ bl(forth); // bl forth
151
152 // RegAndAbsOp
153 __ cbzw(r10, __ pc()); // cbz w10, .
154 __ cbzw(r10, back); // cbz w10, back
155 __ cbzw(r10, forth); // cbz w10, forth
156 __ cbnzw(r8, __ pc()); // cbnz w8, .
157 __ cbnzw(r8, back); // cbnz w8, back
158 __ cbnzw(r8, forth); // cbnz w8, forth
159 __ cbz(r11, __ pc()); // cbz x11, .
160 __ cbz(r11, back); // cbz x11, back
161 __ cbz(r11, forth); // cbz x11, forth
162 __ cbnz(r29, __ pc()); // cbnz x29, .
163 __ cbnz(r29, back); // cbnz x29, back
164 __ cbnz(r29, forth); // cbnz x29, forth
165 __ adr(r19, __ pc()); // adr x19, .
166 __ adr(r19, back); // adr x19, back
167 __ adr(r19, forth); // adr x19, forth
168 __ _adrp(r19, __ pc()); // adrp x19, .
169
170 // RegImmAbsOp
171 __ tbz(r22, 6, __ pc()); // tbz x22, #6, .
172 __ tbz(r22, 6, back); // tbz x22, #6, back
173 __ tbz(r22, 6, forth); // tbz x22, #6, forth
174 __ tbnz(r12, 11, __ pc()); // tbnz x12, #11, .
175 __ tbnz(r12, 11, back); // tbnz x12, #11, back
176 __ tbnz(r12, 11, forth); // tbnz x12, #11, forth
177
178 // MoveWideImmOp
179 __ movnw(r0, 6301, 0); // movn w0, #6301, lsl 0
180 __ movzw(r7, 20886, 0); // movz w7, #20886, lsl 0
181 __ movkw(r27, 18617, 0); // movk w27, #18617, lsl 0
182 __ movn(r12, 22998, 16); // movn x12, #22998, lsl 16
183 __ movz(r20, 1532, 16); // movz x20, #1532, lsl 16
184 __ movk(r8, 5167, 32); // movk x8, #5167, lsl 32
185
186 // BitfieldOp
187 __ sbfm(r15, r17, 24, 28); // sbfm x15, x17, #24, #28
188 __ bfmw(r15, r9, 14, 25); // bfm w15, w9, #14, #25
189 __ ubfmw(r27, r25, 6, 31); // ubfm w27, w25, #6, #31
190 __ sbfm(r19, r2, 23, 31); // sbfm x19, x2, #23, #31
191 __ bfm(r12, r21, 10, 6); // bfm x12, x21, #10, #6
192 __ ubfm(r22, r0, 26, 16); // ubfm x22, x0, #26, #16
193
194 // ExtractOp
195 __ extrw(r3, r3, r20, 27); // extr w3, w3, w20, #27
196 __ extr(r8, r30, r3, 54); // extr x8, x30, x3, #54
197
198 // CondBranchOp
199 __ br(Assembler::EQ, __ pc()); // b.EQ .
200 __ br(Assembler::EQ, back); // b.EQ back
201 __ br(Assembler::EQ, forth); // b.EQ forth
202 __ br(Assembler::NE, __ pc()); // b.NE .
203 __ br(Assembler::NE, back); // b.NE back
204 __ br(Assembler::NE, forth); // b.NE forth
205 __ br(Assembler::HS, __ pc()); // b.HS .
206 __ br(Assembler::HS, back); // b.HS back
207 __ br(Assembler::HS, forth); // b.HS forth
208 __ br(Assembler::CS, __ pc()); // b.CS .
209 __ br(Assembler::CS, back); // b.CS back
210 __ br(Assembler::CS, forth); // b.CS forth
211 __ br(Assembler::LO, __ pc()); // b.LO .
212 __ br(Assembler::LO, back); // b.LO back
213 __ br(Assembler::LO, forth); // b.LO forth
214 __ br(Assembler::CC, __ pc()); // b.CC .
215 __ br(Assembler::CC, back); // b.CC back
216 __ br(Assembler::CC, forth); // b.CC forth
217 __ br(Assembler::MI, __ pc()); // b.MI .
218 __ br(Assembler::MI, back); // b.MI back
219 __ br(Assembler::MI, forth); // b.MI forth
220 __ br(Assembler::PL, __ pc()); // b.PL .
221 __ br(Assembler::PL, back); // b.PL back
222 __ br(Assembler::PL, forth); // b.PL forth
223 __ br(Assembler::VS, __ pc()); // b.VS .
224 __ br(Assembler::VS, back); // b.VS back
225 __ br(Assembler::VS, forth); // b.VS forth
226 __ br(Assembler::VC, __ pc()); // b.VC .
227 __ br(Assembler::VC, back); // b.VC back
228 __ br(Assembler::VC, forth); // b.VC forth
229 __ br(Assembler::HI, __ pc()); // b.HI .
230 __ br(Assembler::HI, back); // b.HI back
231 __ br(Assembler::HI, forth); // b.HI forth
232 __ br(Assembler::LS, __ pc()); // b.LS .
233 __ br(Assembler::LS, back); // b.LS back
234 __ br(Assembler::LS, forth); // b.LS forth
235 __ br(Assembler::GE, __ pc()); // b.GE .
236 __ br(Assembler::GE, back); // b.GE back
237 __ br(Assembler::GE, forth); // b.GE forth
238 __ br(Assembler::LT, __ pc()); // b.LT .
239 __ br(Assembler::LT, back); // b.LT back
240 __ br(Assembler::LT, forth); // b.LT forth
241 __ br(Assembler::GT, __ pc()); // b.GT .
242 __ br(Assembler::GT, back); // b.GT back
243 __ br(Assembler::GT, forth); // b.GT forth
244 __ br(Assembler::LE, __ pc()); // b.LE .
245 __ br(Assembler::LE, back); // b.LE back
246 __ br(Assembler::LE, forth); // b.LE forth
247 __ br(Assembler::AL, __ pc()); // b.AL .
248 __ br(Assembler::AL, back); // b.AL back
249 __ br(Assembler::AL, forth); // b.AL forth
250 __ br(Assembler::NV, __ pc()); // b.NV .
251 __ br(Assembler::NV, back); // b.NV back
252 __ br(Assembler::NV, forth); // b.NV forth
253
254 // ImmOp
255 __ svc(12999); // svc #12999
256 __ hvc(2665); // hvc #2665
257 __ smc(9002); // smc #9002
258 __ brk(14843); // brk #14843
259 __ hlt(25964); // hlt #25964
260
261 // Op
262 __ nop(); // nop
263 __ eret(); // eret
264 __ drps(); // drps
265 __ isb(); // isb
266
267 // SystemOp
268 __ dsb(Assembler::ST); // dsb ST
269 __ dmb(Assembler::OSHST); // dmb OSHST
270
271 // OneRegOp
272 __ br(r16); // br x16
273 __ blr(r20); // blr x20
274
275 // LoadStoreExclusiveOp
276 __ stxr(r10, r27, r8); // stxr w10, x27, [x8]
277 __ stlxr(r0, r1, r21); // stlxr w0, x1, [x21]
278 __ ldxr(r17, r29); // ldxr x17, [x29]
279 __ ldaxr(r29, r28); // ldaxr x29, [x28]
280 __ stlr(r1, r23); // stlr x1, [x23]
281 __ ldar(r21, r20); // ldar x21, [x20]
282
283 // LoadStoreExclusiveOp
284 __ stxrw(r22, r27, r19); // stxr w22, w27, [x19]
285 __ stlxrw(r11, r16, r6); // stlxr w11, w16, [x6]
286 __ ldxrw(r18, r0); // ldxr w18, [x0]
287 __ ldaxrw(r4, r10); // ldaxr w4, [x10]
288 __ stlrw(r24, r22); // stlr w24, [x22]
289 __ ldarw(r10, r19); // ldar w10, [x19]
290
291 // LoadStoreExclusiveOp
292 __ stxrh(r1, r5, r30); // stxrh w1, w5, [x30]
293 __ stlxrh(r8, r12, r17); // stlxrh w8, w12, [x17]
294 __ ldxrh(r9, r14); // ldxrh w9, [x14]
295 __ ldaxrh(r7, r1); // ldaxrh w7, [x1]
296 __ stlrh(r5, r16); // stlrh w5, [x16]
297 __ ldarh(r2, r12); // ldarh w2, [x12]
298
299 // LoadStoreExclusiveOp
300 __ stxrb(r10, r12, r3); // stxrb w10, w12, [x3]
301 __ stlxrb(r28, r14, r26); // stlxrb w28, w14, [x26]
302 __ ldxrb(r30, r10); // ldxrb w30, [x10]
303 __ ldaxrb(r14, r21); // ldaxrb w14, [x21]
304 __ stlrb(r13, r9); // stlrb w13, [x9]
305 __ ldarb(r22, r27); // ldarb w22, [x27]
306
307 // LoadStoreExclusiveOp
308 __ ldxp(r28, r19, r11); // ldxp x28, x19, [x11]
309 __ ldaxp(r30, r19, r2); // ldaxp x30, x19, [x2]
310 __ stxp(r2, r23, r1, r0); // stxp w2, x23, x1, [x0]
311 __ stlxp(r12, r16, r13, r15); // stlxp w12, x16, x13, [x15]
312
313 // LoadStoreExclusiveOp
314 __ ldxpw(r18, r21, r13); // ldxp w18, w21, [x13]
315 __ ldaxpw(r11, r30, r8); // ldaxp w11, w30, [x8]
316 __ stxpw(r24, r13, r11, r1); // stxp w24, w13, w11, [x1]
317 __ stlxpw(r26, r21, r27, r13); // stlxp w26, w21, w27, [x13]
318
319 // base_plus_unscaled_offset
320 // LoadStoreOp
321 __ str(r11, Address(r20, -103)); // str x11, [x20, -103]
322 __ strw(r28, Address(r16, 62)); // str w28, [x16, 62]
323 __ strb(r27, Address(r9, -9)); // strb w27, [x9, -9]
324 __ strh(r2, Address(r25, -50)); // strh w2, [x25, -50]
325 __ ldr(r4, Address(r2, -241)); // ldr x4, [x2, -241]
326 __ ldrw(r30, Address(r20, -31)); // ldr w30, [x20, -31]
327 __ ldrb(r18, Address(r23, -23)); // ldrb w18, [x23, -23]
328 __ ldrh(r29, Address(r26, -1)); // ldrh w29, [x26, -1]
329 __ ldrsb(r1, Address(r9, 6)); // ldrsb x1, [x9, 6]
330 __ ldrsh(r11, Address(r12, 19)); // ldrsh x11, [x12, 19]
331 __ ldrshw(r11, Address(r1, -50)); // ldrsh w11, [x1, -50]
332 __ ldrsw(r19, Address(r24, 41)); // ldrsw x19, [x24, 41]
333 __ ldrd(v24, Address(r24, 95)); // ldr d24, [x24, 95]
334 __ ldrs(v15, Address(r5, -43)); // ldr s15, [x5, -43]
335 __ strd(v21, Address(r27, 1)); // str d21, [x27, 1]
336 __ strs(v23, Address(r13, -107)); // str s23, [x13, -107]
337
338 // pre
339 // LoadStoreOp
340 __ str(r11, Address(__ pre(r0, 8))); // str x11, [x0, 8]!
341 __ strw(r3, Address(__ pre(r0, 29))); // str w3, [x0, 29]!
342 __ strb(r11, Address(__ pre(r14, 9))); // strb w11, [x14, 9]!
343 __ strh(r29, Address(__ pre(r24, -3))); // strh w29, [x24, -3]!
344 __ ldr(r13, Address(__ pre(r17, -144))); // ldr x13, [x17, -144]!
345 __ ldrw(r12, Address(__ pre(r22, -6))); // ldr w12, [x22, -6]!
346 __ ldrb(r13, Address(__ pre(r12, -10))); // ldrb w13, [x12, -10]!
347 __ ldrh(r0, Address(__ pre(r21, -21))); // ldrh w0, [x21, -21]!
348 __ ldrsb(r23, Address(__ pre(r7, 4))); // ldrsb x23, [x7, 4]!
349 __ ldrsh(r3, Address(__ pre(r7, -53))); // ldrsh x3, [x7, -53]!
350 __ ldrshw(r28, Address(__ pre(r5, -7))); // ldrsh w28, [x5, -7]!
351 __ ldrsw(r24, Address(__ pre(r9, -18))); // ldrsw x24, [x9, -18]!
352 __ ldrd(v14, Address(__ pre(r11, 12))); // ldr d14, [x11, 12]!
353 __ ldrs(v19, Address(__ pre(r12, -67))); // ldr s19, [x12, -67]!
354 __ strd(v20, Address(__ pre(r0, -253))); // str d20, [x0, -253]!
355 __ strs(v8, Address(__ pre(r0, 64))); // str s8, [x0, 64]!
356
357 // post
358 // LoadStoreOp
359 __ str(r4, Address(__ post(r28, -94))); // str x4, [x28], -94
360 __ strw(r12, Address(__ post(r7, -54))); // str w12, [x7], -54
361 __ strb(r27, Address(__ post(r10, -24))); // strb w27, [x10], -24
362 __ strh(r6, Address(__ post(r8, 27))); // strh w6, [x8], 27
363 __ ldr(r14, Address(__ post(r10, -202))); // ldr x14, [x10], -202
364 __ ldrw(r16, Address(__ post(r5, -41))); // ldr w16, [x5], -41
365 __ ldrb(r2, Address(__ post(r14, 9))); // ldrb w2, [x14], 9
366 __ ldrh(r28, Address(__ post(r13, -20))); // ldrh w28, [x13], -20
367 __ ldrsb(r9, Address(__ post(r13, -31))); // ldrsb x9, [x13], -31
368 __ ldrsh(r3, Address(__ post(r24, -36))); // ldrsh x3, [x24], -36
369 __ ldrshw(r20, Address(__ post(r3, 6))); // ldrsh w20, [x3], 6
370 __ ldrsw(r7, Address(__ post(r19, -1))); // ldrsw x7, [x19], -1
371 __ ldrd(v30, Address(__ post(r8, -130))); // ldr d30, [x8], -130
372 __ ldrs(v25, Address(__ post(r15, 21))); // ldr s25, [x15], 21
373 __ strd(v14, Address(__ post(r23, 90))); // str d14, [x23], 90
374 __ strs(v8, Address(__ post(r0, -33))); // str s8, [x0], -33
375
376 // base_plus_reg
377 // LoadStoreOp
378 __ str(r10, Address(r18, r21, Address::sxtw(3))); // str x10, [x18, w21, sxtw #3]
379 __ strw(r4, Address(r13, r22, Address::sxtw(2))); // str w4, [x13, w22, sxtw #2]
380 __ strb(r13, Address(r0, r19, Address::uxtw(0))); // strb w13, [x0, w19, uxtw #0]
381 __ strh(r12, Address(r27, r6, Address::sxtw(0))); // strh w12, [x27, w6, sxtw #0]
382 __ ldr(r0, Address(r8, r16, Address::lsl(0))); // ldr x0, [x8, x16, lsl #0]
383 __ ldrw(r0, Address(r4, r26, Address::sxtx(0))); // ldr w0, [x4, x26, sxtx #0]
384 __ ldrb(r14, Address(r25, r5, Address::sxtw(0))); // ldrb w14, [x25, w5, sxtw #0]
385 __ ldrh(r9, Address(r4, r18, Address::uxtw(0))); // ldrh w9, [x4, w18, uxtw #0]
386 __ ldrsb(r27, Address(r4, r7, Address::lsl(0))); // ldrsb x27, [x4, x7, lsl #0]
387 __ ldrsh(r15, Address(r17, r30, Address::sxtw(0))); // ldrsh x15, [x17, w30, sxtw #0]
388 __ ldrshw(r16, Address(r0, r22, Address::sxtw(0))); // ldrsh w16, [x0, w22, sxtw #0]
389 __ ldrsw(r22, Address(r10, r30, Address::sxtx(2))); // ldrsw x22, [x10, x30, sxtx #2]
390 __ ldrd(v29, Address(r21, r10, Address::sxtx(3))); // ldr d29, [x21, x10, sxtx #3]
391 __ ldrs(v3, Address(r11, r19, Address::uxtw(0))); // ldr s3, [x11, w19, uxtw #0]
392 __ strd(v13, Address(r28, r29, Address::uxtw(3))); // str d13, [x28, w29, uxtw #3]
393 __ strs(v23, Address(r29, r5, Address::sxtx(2))); // str s23, [x29, x5, sxtx #2]
394
395 // base_plus_scaled_offset
396 // LoadStoreOp
397 __ str(r5, Address(r8, 12600)); // str x5, [x8, 12600]
398 __ strw(r29, Address(r24, 7880)); // str w29, [x24, 7880]
399 __ strb(r19, Address(r17, 1566)); // strb w19, [x17, 1566]
400 __ strh(r13, Address(r19, 3984)); // strh w13, [x19, 3984]
401 __ ldr(r19, Address(r23, 13632)); // ldr x19, [x23, 13632]
402 __ ldrw(r23, Address(r29, 6264)); // ldr w23, [x29, 6264]
403 __ ldrb(r22, Address(r11, 2012)); // ldrb w22, [x11, 2012]
404 __ ldrh(r3, Address(r10, 3784)); // ldrh w3, [x10, 3784]
405 __ ldrsb(r8, Address(r16, 1951)); // ldrsb x8, [x16, 1951]
406 __ ldrsh(r23, Address(r20, 3346)); // ldrsh x23, [x20, 3346]
407 __ ldrshw(r2, Address(r1, 3994)); // ldrsh w2, [x1, 3994]
408 __ ldrsw(r4, Address(r17, 7204)); // ldrsw x4, [x17, 7204]
409 __ ldrd(v20, Address(r27, 14400)); // ldr d20, [x27, 14400]
410 __ ldrs(v25, Address(r14, 8096)); // ldr s25, [x14, 8096]
411 __ strd(v26, Address(r10, 15024)); // str d26, [x10, 15024]
412 __ strs(v9, Address(r3, 6936)); // str s9, [x3, 6936]
413
414 // pcrel
415 // LoadStoreOp
416 __ ldr(r27, forth); // ldr x27, forth
417 __ ldrw(r11, __ pc()); // ldr w11, .
418
419 // LoadStoreOp
420 __ prfm(Address(r3, -187)); // prfm PLDL1KEEP, [x3, -187]
421
422 // LoadStoreOp
423 __ prfm(__ pc()); // prfm PLDL1KEEP, .
424
425 // LoadStoreOp
426 __ prfm(Address(r29, r14, Address::lsl(0))); // prfm PLDL1KEEP, [x29, x14, lsl #0]
427
428 // LoadStoreOp
429 __ prfm(Address(r4, 13312)); // prfm PLDL1KEEP, [x4, 13312]
430
431 // AddSubCarryOp
432 __ adcw(r21, r1, r7); // adc w21, w1, w7
433 __ adcsw(r8, r5, r7); // adcs w8, w5, w7
434 __ sbcw(r7, r27, r14); // sbc w7, w27, w14
435 __ sbcsw(r27, r4, r17); // sbcs w27, w4, w17
436 __ adc(r0, r28, r0); // adc x0, x28, x0
437 __ adcs(r12, r24, r30); // adcs x12, x24, x30
438 __ sbc(r0, r25, r15); // sbc x0, x25, x15
439 __ sbcs(r1, r24, r3); // sbcs x1, x24, x3
440
441 // AddSubExtendedOp
442 __ addw(r18, r24, r20, ext::uxtb, 2); // add w18, w24, w20, uxtb #2
443 __ addsw(r13, r28, r10, ext::uxth, 1); // adds w13, w28, w10, uxth #1
444 __ sub(r15, r16, r2, ext::sxth, 2); // sub x15, x16, x2, sxth #2
445 __ subsw(r29, r13, r13, ext::uxth, 2); // subs w29, w13, w13, uxth #2
446 __ add(r12, r20, r12, ext::sxtw, 3); // add x12, x20, x12, sxtw #3
447 __ adds(r30, r27, r11, ext::sxtb, 1); // adds x30, x27, x11, sxtb #1
448 __ sub(r14, r7, r1, ext::sxtw, 2); // sub x14, x7, x1, sxtw #2
449 __ subs(r29, r3, r27, ext::sxth, 1); // subs x29, x3, x27, sxth #1
450
451 // ConditionalCompareOp
452 __ ccmnw(r0, r13, 14u, Assembler::MI); // ccmn w0, w13, #14, MI
453 __ ccmpw(r22, r18, 6u, Assembler::CC); // ccmp w22, w18, #6, CC
454 __ ccmn(r18, r30, 14u, Assembler::VS); // ccmn x18, x30, #14, VS
455 __ ccmp(r10, r19, 12u, Assembler::HI); // ccmp x10, x19, #12, HI
456
457 // ConditionalCompareImmedOp
458 __ ccmnw(r6, 18, 2, Assembler::LE); // ccmn w6, #18, #2, LE
459 __ ccmpw(r9, 13, 4, Assembler::HI); // ccmp w9, #13, #4, HI
460 __ ccmn(r21, 11, 11, Assembler::LO); // ccmn x21, #11, #11, LO
461 __ ccmp(r4, 13, 2, Assembler::VC); // ccmp x4, #13, #2, VC
462
463 // ConditionalSelectOp
464 __ cselw(r12, r2, r22, Assembler::HI); // csel w12, w2, w22, HI
465 __ csincw(r24, r16, r17, Assembler::HS); // csinc w24, w16, w17, HS
466 __ csinvw(r6, r7, r16, Assembler::LT); // csinv w6, w7, w16, LT
467 __ csnegw(r11, r27, r22, Assembler::LS); // csneg w11, w27, w22, LS
468 __ csel(r10, r3, r29, Assembler::LT); // csel x10, x3, x29, LT
469 __ csinc(r12, r26, r27, Assembler::CC); // csinc x12, x26, x27, CC
470 __ csinv(r15, r10, r21, Assembler::GT); // csinv x15, x10, x21, GT
471 __ csneg(r30, r23, r9, Assembler::GT); // csneg x30, x23, x9, GT
472
473 // TwoRegOp
474 __ rbitw(r30, r10); // rbit w30, w10
475 __ rev16w(r29, r15); // rev16 w29, w15
476 __ revw(r29, r30); // rev w29, w30
477 __ clzw(r25, r21); // clz w25, w21
478 __ clsw(r4, r0); // cls w4, w0
479 __ rbit(r18, r21); // rbit x18, x21
480 __ rev16(r29, r16); // rev16 x29, x16
481 __ rev32(r21, r20); // rev32 x21, x20
482 __ rev(r6, r19); // rev x6, x19
483 __ clz(r30, r3); // clz x30, x3
484 __ cls(r21, r19); // cls x21, x19
485
486 // ThreeRegOp
487 __ udivw(r11, r24, r0); // udiv w11, w24, w0
488 __ sdivw(r27, r25, r14); // sdiv w27, w25, w14
489 __ lslvw(r3, r14, r18); // lslv w3, w14, w18
490 __ lsrvw(r7, r15, r24); // lsrv w7, w15, w24
491 __ asrvw(r28, r17, r25); // asrv w28, w17, w25
492 __ rorvw(r2, r26, r28); // rorv w2, w26, w28
493 __ udiv(r5, r25, r26); // udiv x5, x25, x26
494 __ sdiv(r27, r16, r18); // sdiv x27, x16, x18
495 __ lslv(r6, r21, r12); // lslv x6, x21, x12
496 __ lsrv(r0, r4, r12); // lsrv x0, x4, x12
497 __ asrv(r27, r17, r28); // asrv x27, x17, x28
498 __ rorv(r28, r2, r18); // rorv x28, x2, x18
499 __ umulh(r10, r15, r14); // umulh x10, x15, x14
500 __ smulh(r14, r3, r25); // smulh x14, x3, x25
501
502 // FourRegMulOp
503 __ maddw(r15, r19, r14, r5); // madd w15, w19, w14, w5
504 __ msubw(r16, r4, r26, r25); // msub w16, w4, w26, w25
505 __ madd(r4, r2, r2, r12); // madd x4, x2, x2, x12
506 __ msub(r29, r17, r8, r7); // msub x29, x17, x8, x7
507 __ smaddl(r3, r4, r25, r4); // smaddl x3, w4, w25, x4
508 __ smsubl(r26, r25, r4, r17); // smsubl x26, w25, w4, x17
509 __ umaddl(r0, r26, r17, r23); // umaddl x0, w26, w17, x23
510 __ umsubl(r15, r21, r28, r17); // umsubl x15, w21, w28, x17
511
512 // ThreeRegFloatOp
513 __ fmuls(v27, v10, v3); // fmul s27, s10, s3
514 __ fdivs(v0, v7, v25); // fdiv s0, s7, s25
515 __ fadds(v9, v6, v15); // fadd s9, s6, s15
516 __ fsubs(v29, v15, v10); // fsub s29, s15, s10
517 __ fmuls(v2, v17, v7); // fmul s2, s17, s7
518 __ fmuld(v11, v11, v23); // fmul d11, d11, d23
519 __ fdivd(v7, v29, v23); // fdiv d7, d29, d23
520 __ faddd(v14, v27, v11); // fadd d14, d27, d11
521 __ fsubd(v11, v4, v24); // fsub d11, d4, d24
522 __ fmuld(v12, v15, v14); // fmul d12, d15, d14
523
524 // FourRegFloatOp
525 __ fmadds(v20, v11, v28, v13); // fmadd s20, s11, s28, s13
526 __ fmsubs(v11, v12, v23, v30); // fmsub s11, s12, s23, s30
527 __ fnmadds(v26, v14, v9, v13); // fnmadd s26, s14, s9, s13
528 __ fnmadds(v10, v7, v5, v29); // fnmadd s10, s7, s5, s29
529 __ fmaddd(v15, v3, v11, v12); // fmadd d15, d3, d11, d12
530 __ fmsubd(v15, v30, v30, v17); // fmsub d15, d30, d30, d17
531 __ fnmaddd(v19, v20, v15, v15); // fnmadd d19, d20, d15, d15
532 __ fnmaddd(v9, v21, v2, v9); // fnmadd d9, d21, d2, d9
533
534 // TwoRegFloatOp
535 __ fmovs(v27, v7); // fmov s27, s7
536 __ fabss(v29, v30); // fabs s29, s30
537 __ fnegs(v17, v1); // fneg s17, s1
538 __ fsqrts(v2, v6); // fsqrt s2, s6
539 __ fcvts(v10, v3); // fcvt d10, s3
540 __ fmovd(v24, v11); // fmov d24, d11
541 __ fabsd(v7, v1); // fabs d7, d1
542 __ fnegd(v11, v0); // fneg d11, d0
543 __ fsqrtd(v3, v18); // fsqrt d3, d18
544 __ fcvtd(v28, v6); // fcvt s28, d6
545
546 // FloatConvertOp
547 __ fcvtzsw(r22, v6); // fcvtzs w22, s6
548 __ fcvtzs(r0, v27); // fcvtzs x0, s27
549 __ fcvtzdw(r26, v2); // fcvtzs w26, d2
550 __ fcvtzd(r5, v7); // fcvtzs x5, d7
551 __ scvtfws(v28, r11); // scvtf s28, w11
552 __ scvtfs(v25, r13); // scvtf s25, x13
553 __ scvtfwd(v11, r23); // scvtf d11, w23
554 __ scvtfd(v19, r8); // scvtf d19, x8
555 __ fmovs(r18, v21); // fmov w18, s21
556 __ fmovd(r25, v20); // fmov x25, d20
557 __ fmovs(v19, r18); // fmov s19, w18
558 __ fmovd(v2, r29); // fmov d2, x29
559
560 // TwoRegFloatOp
561 __ fcmps(v22, v8); // fcmp s22, s8
562 __ fcmpd(v21, v19); // fcmp d21, d19
563 __ fcmps(v20, 0.0); // fcmp s20, #0.0
564 __ fcmpd(v11, 0.0); // fcmp d11, #0.0
565
566 // LoadStorePairOp
567 __ stpw(r20, r6, Address(r15, -32)); // stp w20, w6, [x15, #-32]
568 __ ldpw(r27, r14, Address(r3, -208)); // ldp w27, w14, [x3, #-208]
569 __ ldpsw(r17, r10, Address(r11, -80)); // ldpsw x17, x10, [x11, #-80]
570 __ stp(r7, r7, Address(r14, 64)); // stp x7, x7, [x14, #64]
571 __ ldp(r12, r23, Address(r0, 112)); // ldp x12, x23, [x0, #112]
572
573 // LoadStorePairOp
574 __ stpw(r13, r7, Address(__ pre(r6, -80))); // stp w13, w7, [x6, #-80]!
575 __ ldpw(r30, r16, Address(__ pre(r2, -144))); // ldp w30, w16, [x2, #-144]!
576 __ ldpsw(r4, r1, Address(__ pre(r26, -144))); // ldpsw x4, x1, [x26, #-144]!
577 __ stp(r23, r14, Address(__ pre(r11, 64))); // stp x23, x14, [x11, #64]!
578 __ ldp(r29, r27, Address(__ pre(r21, -192))); // ldp x29, x27, [x21, #-192]!
579
580 // LoadStorePairOp
581 __ stpw(r22, r5, Address(__ post(r21, -48))); // stp w22, w5, [x21], #-48
582 __ ldpw(r27, r17, Address(__ post(r6, -32))); // ldp w27, w17, [x6], #-32
583 __ ldpsw(r17, r6, Address(__ post(r1, -80))); // ldpsw x17, x6, [x1], #-80
584 __ stp(r13, r20, Address(__ post(r21, -208))); // stp x13, x20, [x21], #-208
585 __ ldp(r30, r27, Address(__ post(r10, 80))); // ldp x30, x27, [x10], #80
586
587 // LoadStorePairOp
588 __ stnpw(r5, r17, Address(r11, 16)); // stnp w5, w17, [x11, #16]
589 __ ldnpw(r14, r4, Address(r26, -96)); // ldnp w14, w4, [x26, #-96]
590 __ stnp(r23, r29, Address(r12, 32)); // stnp x23, x29, [x12, #32]
591 __ ldnp(r0, r6, Address(r21, -80)); // ldnp x0, x6, [x21, #-80]
592
593 // LdStSIMDOp
594 __ ld1(v15, __ T8B, Address(r26)); // ld1 {v15.8B}, [x26]
595 __ ld1(v23, v24, __ T16B, Address(__ post(r11, 32))); // ld1 {v23.16B, v24.16B}, [x11], 32
596 __ ld1(v8, v9, v10, __ T1D, Address(__ post(r23, r7))); // ld1 {v8.1D, v9.1D, v10.1D}, [x23], x7
597 __ ld1(v19, v20, v21, v22, __ T8H, Address(__ post(r25, 64))); // ld1 {v19.8H, v20.8H, v21.8H, v22.8H}, [x25], 64
598 __ ld1r(v29, __ T8B, Address(r17)); // ld1r {v29.8B}, [x17]
599 __ ld1r(v24, __ T4S, Address(__ post(r23, 4))); // ld1r {v24.4S}, [x23], 4
600 __ ld1r(v10, __ T1D, Address(__ post(r5, r25))); // ld1r {v10.1D}, [x5], x25
601 __ ld2(v18, v19, __ T2D, Address(r10)); // ld2 {v18.2D, v19.2D}, [x10]
602 __ ld2(v12, v13, __ T4H, Address(__ post(r15, 16))); // ld2 {v12.4H, v13.4H}, [x15], 16
603 __ ld2r(v25, v26, __ T16B, Address(r18)); // ld2r {v25.16B, v26.16B}, [x18]
604 __ ld2r(v1, v2, __ T2S, Address(__ post(r30, 8))); // ld2r {v1.2S, v2.2S}, [x30], 8
605 __ ld2r(v16, v17, __ T2D, Address(__ post(r18, r9))); // ld2r {v16.2D, v17.2D}, [x18], x9
606 __ ld3(v25, v26, v27, __ T4S, Address(__ post(r12, r2))); // ld3 {v25.4S, v26.4S, v27.4S}, [x12], x2
607 __ ld3(v26, v27, v28, __ T2S, Address(r19)); // ld3 {v26.2S, v27.2S, v28.2S}, [x19]
608 __ ld3r(v15, v16, v17, __ T8H, Address(r21)); // ld3r {v15.8H, v16.8H, v17.8H}, [x21]
609 __ ld3r(v25, v26, v27, __ T4S, Address(__ post(r13, 12))); // ld3r {v25.4S, v26.4S, v27.4S}, [x13], 12
610 __ ld3r(v14, v15, v16, __ T1D, Address(__ post(r28, r29))); // ld3r {v14.1D, v15.1D, v16.1D}, [x28], x29
611 __ ld4(v17, v18, v19, v20, __ T8H, Address(__ post(r29, 64))); // ld4 {v17.8H, v18.8H, v19.8H, v20.8H}, [x29], 64
612 __ ld4(v27, v28, v29, v30, __ T8B, Address(__ post(r7, r0))); // ld4 {v27.8B, v28.8B, v29.8B, v30.8B}, [x7], x0
613 __ ld4r(v24, v25, v26, v27, __ T8B, Address(r18)); // ld4r {v24.8B, v25.8B, v26.8B, v27.8B}, [x18]
614 __ ld4r(v0, v1, v2, v3, __ T4H, Address(__ post(r26, 8))); // ld4r {v0.4H, v1.4H, v2.4H, v3.4H}, [x26], 8
615 __ ld4r(v12, v13, v14, v15, __ T2S, Address(__ post(r25, r2))); // ld4r {v12.2S, v13.2S, v14.2S, v15.2S}, [x25], x2
616
617 // SHA512SIMDOp
618 __ sha512h(v22, __ T2D, v27, v4); // sha512h q22, q27, v4.2D
619 __ sha512h2(v7, __ T2D, v6, v1); // sha512h2 q7, q6, v1.2D
620 __ sha512su0(v26, __ T2D, v15); // sha512su0 v26.2D, v15.2D
621 __ sha512su1(v2, __ T2D, v13, v13); // sha512su1 v2.2D, v13.2D, v13.2D
622
623 // SpecialCases
624 __ ccmn(zr, zr, 3u, Assembler::LE); // ccmn xzr, xzr, #3, LE
625 __ ccmnw(zr, zr, 5u, Assembler::EQ); // ccmn wzr, wzr, #5, EQ
626 __ ccmp(zr, 1, 4u, Assembler::NE); // ccmp xzr, 1, #4, NE
627 __ ccmpw(zr, 2, 2, Assembler::GT); // ccmp wzr, 2, #2, GT
628 __ extr(zr, zr, zr, 0); // extr xzr, xzr, xzr, 0
629 __ stlxp(r0, zr, zr, sp); // stlxp w0, xzr, xzr, [sp]
630 __ stlxpw(r2, zr, zr, r3); // stlxp w2, wzr, wzr, [x3]
631 __ stxp(r4, zr, zr, r5); // stxp w4, xzr, xzr, [x5]
632 __ stxpw(r6, zr, zr, sp); // stxp w6, wzr, wzr, [sp]
633 __ dup(v0, __ T16B, zr); // dup v0.16b, wzr
634 __ mov(v1, __ T1D, 0, zr); // mov v1.d[0], xzr
635 __ mov(v1, __ T2S, 1, zr); // mov v1.s[1], wzr
636 __ mov(v1, __ T4H, 2, zr); // mov v1.h[2], wzr
637 __ mov(v1, __ T8B, 3, zr); // mov v1.b[3], wzr
638 __ ld1(v31, v0, __ T2D, Address(__ post(r1, r0))); // ld1 {v31.2d, v0.2d}, [x1], x0
639
640 // FloatImmediateOp
641 __ fmovd(v0, 2.0); // fmov d0, #2.0
642 __ fmovd(v0, 2.125); // fmov d0, #2.125
643 __ fmovd(v0, 4.0); // fmov d0, #4.0
644 __ fmovd(v0, 4.25); // fmov d0, #4.25
645 __ fmovd(v0, 8.0); // fmov d0, #8.0
646 __ fmovd(v0, 8.5); // fmov d0, #8.5
647 __ fmovd(v0, 16.0); // fmov d0, #16.0
648 __ fmovd(v0, 17.0); // fmov d0, #17.0
649 __ fmovd(v0, 0.125); // fmov d0, #0.125
650 __ fmovd(v0, 0.1328125); // fmov d0, #0.1328125
651 __ fmovd(v0, 0.25); // fmov d0, #0.25
652 __ fmovd(v0, 0.265625); // fmov d0, #0.265625
653 __ fmovd(v0, 0.5); // fmov d0, #0.5
654 __ fmovd(v0, 0.53125); // fmov d0, #0.53125
655 __ fmovd(v0, 1.0); // fmov d0, #1.0
656 __ fmovd(v0, 1.0625); // fmov d0, #1.0625
657 __ fmovd(v0, -2.0); // fmov d0, #-2.0
658 __ fmovd(v0, -2.125); // fmov d0, #-2.125
659 __ fmovd(v0, -4.0); // fmov d0, #-4.0
660 __ fmovd(v0, -4.25); // fmov d0, #-4.25
661 __ fmovd(v0, -8.0); // fmov d0, #-8.0
662 __ fmovd(v0, -8.5); // fmov d0, #-8.5
663 __ fmovd(v0, -16.0); // fmov d0, #-16.0
664 __ fmovd(v0, -17.0); // fmov d0, #-17.0
665 __ fmovd(v0, -0.125); // fmov d0, #-0.125
666 __ fmovd(v0, -0.1328125); // fmov d0, #-0.1328125
667 __ fmovd(v0, -0.25); // fmov d0, #-0.25
668 __ fmovd(v0, -0.265625); // fmov d0, #-0.265625
669 __ fmovd(v0, -0.5); // fmov d0, #-0.5
670 __ fmovd(v0, -0.53125); // fmov d0, #-0.53125
671 __ fmovd(v0, -1.0); // fmov d0, #-1.0
672 __ fmovd(v0, -1.0625); // fmov d0, #-1.0625
673
674 // LSEOp
675 __ swp(Assembler::xword, r24, r24, r4); // swp x24, x24, [x4]
676 __ ldadd(Assembler::xword, r20, r16, r0); // ldadd x20, x16, [x0]
677 __ ldbic(Assembler::xword, r4, r21, r11); // ldclr x4, x21, [x11]
678 __ ldeor(Assembler::xword, r30, r16, r22); // ldeor x30, x16, [x22]
679 __ ldorr(Assembler::xword, r4, r15, r23); // ldset x4, x15, [x23]
680 __ ldsmin(Assembler::xword, r26, r6, r12); // ldsmin x26, x6, [x12]
681 __ ldsmax(Assembler::xword, r15, r14, r15); // ldsmax x15, x14, [x15]
682 __ ldumin(Assembler::xword, r9, r25, r29); // ldumin x9, x25, [x29]
683 __ ldumax(Assembler::xword, r11, r20, r12); // ldumax x11, x20, [x12]
684
685 // LSEOp
686 __ swpa(Assembler::xword, r18, r22, r16); // swpa x18, x22, [x16]
687 __ ldadda(Assembler::xword, r21, r24, r26); // ldadda x21, x24, [x26]
688 __ ldbica(Assembler::xword, r6, r6, r16); // ldclra x6, x6, [x16]
689 __ ldeora(Assembler::xword, r16, r25, r16); // ldeora x16, x25, [x16]
690 __ ldorra(Assembler::xword, r28, r24, r16); // ldseta x28, x24, [x16]
691 __ ldsmina(Assembler::xword, r26, r15, r10); // ldsmina x26, x15, [x10]
692 __ ldsmaxa(Assembler::xword, r13, r14, r20); // ldsmaxa x13, x14, [x20]
693 __ ldumina(Assembler::xword, r1, r23, r30); // ldumina x1, x23, [x30]
694 __ ldumaxa(Assembler::xword, r14, r2, r6); // ldumaxa x14, x2, [x6]
695
696 // LSEOp
697 __ swpal(Assembler::xword, r3, r8, r25); // swpal x3, x8, [x25]
698 __ ldaddal(Assembler::xword, r0, r27, r30); // ldaddal x0, x27, [x30]
699 __ ldbical(Assembler::xword, r5, r5, r30); // ldclral x5, x5, [x30]
700 __ ldeoral(Assembler::xword, r11, r25, r0); // ldeoral x11, x25, [x0]
701 __ ldorral(Assembler::xword, zr, r0, r19); // ldsetal xzr, x0, [x19]
702 __ ldsminal(Assembler::xword, r29, r26, r9); // ldsminal x29, x26, [x9]
703 __ ldsmaxal(Assembler::xword, r26, r12, r15); // ldsmaxal x26, x12, [x15]
704 __ lduminal(Assembler::xword, r11, r11, r18); // lduminal x11, x11, [x18]
705 __ ldumaxal(Assembler::xword, r25, r22, r24); // ldumaxal x25, x22, [x24]
706
707 // LSEOp
708 __ swpl(Assembler::xword, r0, r17, r11); // swpl x0, x17, [x11]
709 __ ldaddl(Assembler::xword, r6, r29, r6); // ldaddl x6, x29, [x6]
710 __ ldbicl(Assembler::xword, r5, r5, r21); // ldclrl x5, x5, [x21]
711 __ ldeorl(Assembler::xword, r19, r16, r18); // ldeorl x19, x16, [x18]
712 __ ldorrl(Assembler::xword, r30, r27, r28); // ldsetl x30, x27, [x28]
713 __ ldsminl(Assembler::xword, r1, r28, r1); // ldsminl x1, x28, [x1]
714 __ ldsmaxl(Assembler::xword, r20, r29, r16); // ldsmaxl x20, x29, [x16]
715 __ lduminl(Assembler::xword, r13, r10, r29); // lduminl x13, x10, [x29]
716 __ ldumaxl(Assembler::xword, r29, r19, r22); // ldumaxl x29, x19, [x22]
717
718 // LSEOp
719 __ swp(Assembler::word, r10, r4, sp); // swp w10, w4, [sp]
720 __ ldadd(Assembler::word, r21, r8, sp); // ldadd w21, w8, [sp]
721 __ ldbic(Assembler::word, r19, r10, r28); // ldclr w19, w10, [x28]
722 __ ldeor(Assembler::word, r2, r25, r5); // ldeor w2, w25, [x5]
723 __ ldorr(Assembler::word, r3, r8, r22); // ldset w3, w8, [x22]
724 __ ldsmin(Assembler::word, r19, r13, r5); // ldsmin w19, w13, [x5]
725 __ ldsmax(Assembler::word, r29, r24, r21); // ldsmax w29, w24, [x21]
726 __ ldumin(Assembler::word, r26, r24, r3); // ldumin w26, w24, [x3]
727 __ ldumax(Assembler::word, r24, r26, r23); // ldumax w24, w26, [x23]
728
729 // LSEOp
730 __ swpa(Assembler::word, r15, r21, r3); // swpa w15, w21, [x3]
731 __ ldadda(Assembler::word, r24, r8, r25); // ldadda w24, w8, [x25]
732 __ ldbica(Assembler::word, r20, r16, r17); // ldclra w20, w16, [x17]
733 __ ldeora(Assembler::word, r2, r1, r0); // ldeora w2, w1, [x0]
734 __ ldorra(Assembler::word, r24, r4, r3); // ldseta w24, w4, [x3]
735 __ ldsmina(Assembler::word, r12, zr, r28); // ldsmina w12, wzr, [x28]
736 __ ldsmaxa(Assembler::word, r10, r26, r2); // ldsmaxa w10, w26, [x2]
737 __ ldumina(Assembler::word, r12, r18, sp); // ldumina w12, w18, [sp]
738 __ ldumaxa(Assembler::word, r1, r13, r29); // ldumaxa w1, w13, [x29]
739
740 // LSEOp
741 __ swpal(Assembler::word, r0, r19, r12); // swpal w0, w19, [x12]
742 __ ldaddal(Assembler::word, r17, r22, r13); // ldaddal w17, w22, [x13]
743 __ ldbical(Assembler::word, r28, r30, sp); // ldclral w28, w30, [sp]
744 __ ldeoral(Assembler::word, r1, r26, r28); // ldeoral w1, w26, [x28]
745 __ ldorral(Assembler::word, r4, r30, r4); // ldsetal w4, w30, [x4]
746 __ ldsminal(Assembler::word, r6, r30, r26); // ldsminal w6, w30, [x26]
747 __ ldsmaxal(Assembler::word, r18, r9, r8); // ldsmaxal w18, w9, [x8]
748 __ lduminal(Assembler::word, r12, r0, r20); // lduminal w12, w0, [x20]
749 __ ldumaxal(Assembler::word, r1, r24, r2); // ldumaxal w1, w24, [x2]
750
751 // LSEOp
752 __ swpl(Assembler::word, r0, r9, r24); // swpl w0, w9, [x24]
753 __ ldaddl(Assembler::word, r26, r16, r30); // ldaddl w26, w16, [x30]
754 __ ldbicl(Assembler::word, r3, r10, r23); // ldclrl w3, w10, [x23]
755 __ ldeorl(Assembler::word, r10, r4, r18); // ldeorl w10, w4, [x18]
756 __ ldorrl(Assembler::word, r2, r11, r8); // ldsetl w2, w11, [x8]
757 __ ldsminl(Assembler::word, r10, r15, r17); // ldsminl w10, w15, [x17]
758 __ ldsmaxl(Assembler::word, r2, r10, r12); // ldsmaxl w2, w10, [x12]
759 __ lduminl(Assembler::word, r12, r15, r13); // lduminl w12, w15, [x13]
760 __ ldumaxl(Assembler::word, r2, r7, r20); // ldumaxl w2, w7, [x20]
761
762 __ bind(forth);
763
764 /*
765 aarch64ops.o: file format elf64-littleaarch64
766
767
768 Disassembly of section .text:
769
770 0000000000000000 <back>:
771 0: 8b0d82fa add x26, x23, x13, lsl #32
772 4: cb49970c sub x12, x24, x9, lsr #37
773 8: ab889dfc adds x28, x15, x8, asr #39
774 c: eb9ee787 subs x7, x28, x30, asr #57
775 10: 0b9b3ec9 add w9, w22, w27, asr #15
776 14: 4b9279a3 sub w3, w13, w18, asr #30
777 18: 2b88474e adds w14, w26, w8, asr #17
778 1c: 6b8c56c0 subs w0, w22, w12, asr #21
779 20: 8a1a51e0 and x0, x15, x26, lsl #20
780 24: aa11f4ba orr x26, x5, x17, lsl #61
781 28: ca0281b8 eor x24, x13, x2, lsl #32
782 2c: ea918c7c ands x28, x3, x17, asr #35
783 30: 0a5d4a19 and w25, w16, w29, lsr #18
784 34: 2a4b264d orr w13, w18, w11, lsr #9
785 38: 4a523ca5 eor w5, w5, w18, lsr #15
786 3c: 6a9b6ae2 ands w2, w23, w27, asr #26
787 40: 8a70b79b bic x27, x28, x16, lsr #45
788 44: aaba9728 orn x8, x25, x26, asr #37
789 48: ca6dfe3d eon x29, x17, x13, lsr #63
790 4c: ea627f1c bics x28, x24, x2, lsr #31
791 50: 0aa70f53 bic w19, w26, w7, asr #3
792 54: 2aaa0f06 orn w6, w24, w10, asr #3
793 58: 4a6176a4 eon w4, w21, w1, lsr #29
794 5c: 6a604eb0 bics w16, w21, w0, lsr #19
795 60: 1105ed91 add w17, w12, #0x17b
796 64: 3100583e adds w30, w1, #0x16
797 68: 5101f8bd sub w29, w5, #0x7e
798 6c: 710f0306 subs w6, w24, #0x3c0
799 70: 9101a1a0 add x0, x13, #0x68
800 74: b10a5cc8 adds x8, x6, #0x297
801 78: d10810aa sub x10, x5, #0x204
802 7c: f10fd061 subs x1, x3, #0x3f4
803 80: 120cb166 and w6, w11, #0xfff1fff1
804 84: 321764bc orr w28, w5, #0xfffffe07
805 88: 52174681 eor w1, w20, #0x7fffe00
806 8c: 720c0247 ands w7, w18, #0x100000
807 90: 9241018e and x14, x12, #0x8000000000000000
808 94: b25a2969 orr x9, x11, #0x1ffc000000000
809 98: d278b411 eor x17, x0, #0x3fffffffffff00
810 9c: f26aad01 ands x1, x8, #0xffffffffffc00003
811 a0: 14000000 b a0 <back+0xa0>
812 a4: 17ffffd7 b 0 <back>
813 a8: 140001f2 b 870 <forth>
814 ac: 94000000 bl ac <back+0xac>
815 b0: 97ffffd4 bl 0 <back>
816 b4: 940001ef bl 870 <forth>
817 b8: 3400000a cbz w10, b8 <back+0xb8>
818 bc: 34fffa2a cbz w10, 0 <back>
819 c0: 34003d8a cbz w10, 870 <forth>
820 c4: 35000008 cbnz w8, c4 <back+0xc4>
821 c8: 35fff9c8 cbnz w8, 0 <back>
822 cc: 35003d28 cbnz w8, 870 <forth>
823 d0: b400000b cbz x11, d0 <back+0xd0>
824 d4: b4fff96b cbz x11, 0 <back>
825 d8: b4003ccb cbz x11, 870 <forth>
826 dc: b500001d cbnz x29, dc <back+0xdc>
827 e0: b5fff91d cbnz x29, 0 <back>
828 e4: b5003c7d cbnz x29, 870 <forth>
829 e8: 10000013 adr x19, e8 <back+0xe8>
830 ec: 10fff8b3 adr x19, 0 <back>
831 f0: 10003c13 adr x19, 870 <forth>
832 f4: 90000013 adrp x19, 0 <back>
833 f8: 36300016 tbz w22, #6, f8 <back+0xf8>
834 fc: 3637f836 tbz w22, #6, 0 <back>
835 100: 36303b96 tbz w22, #6, 870 <forth>
836 104: 3758000c tbnz w12, #11, 104 <back+0x104>
837 108: 375ff7cc tbnz w12, #11, 0 <back>
838 10c: 37583b2c tbnz w12, #11, 870 <forth>
839 110: 128313a0 mov w0, #0xffffe762 // #-6302
840 114: 528a32c7 mov w7, #0x5196 // #20886
841 118: 7289173b movk w27, #0x48b9
842 11c: 92ab3acc mov x12, #0xffffffffa629ffff // #-1507196929
843 120: d2a0bf94 mov x20, #0x5fc0000 // #100401152
844 124: f2c285e8 movk x8, #0x142f, lsl #32
845 128: 9358722f sbfx x15, x17, #24, #5
846 12c: 330e652f bfxil w15, w9, #14, #12
847 130: 53067f3b lsr w27, w25, #6
848 134: 93577c53 sbfx x19, x2, #23, #9
849 138: b34a1aac bfi x12, x21, #54, #7
850 13c: d35a4016 ubfiz x22, x0, #38, #17
851 140: 13946c63 extr w3, w3, w20, #27
852 144: 93c3dbc8 extr x8, x30, x3, #54
853 148: 54000000 b.eq 148 <back+0x148> // b.none
854 14c: 54fff5a0 b.eq 0 <back> // b.none
855 150: 54003900 b.eq 870 <forth> // b.none
856 154: 54000001 b.ne 154 <back+0x154> // b.any
857 158: 54fff541 b.ne 0 <back> // b.any
858 15c: 540038a1 b.ne 870 <forth> // b.any
859 160: 54000002 b.cs 160 <back+0x160> // b.hs, b.nlast
860 164: 54fff4e2 b.cs 0 <back> // b.hs, b.nlast
861 168: 54003842 b.cs 870 <forth> // b.hs, b.nlast
862 16c: 54000002 b.cs 16c <back+0x16c> // b.hs, b.nlast
863 170: 54fff482 b.cs 0 <back> // b.hs, b.nlast
864 174: 540037e2 b.cs 870 <forth> // b.hs, b.nlast
865 178: 54000003 b.cc 178 <back+0x178> // b.lo, b.ul, b.last
866 17c: 54fff423 b.cc 0 <back> // b.lo, b.ul, b.last
867 180: 54003783 b.cc 870 <forth> // b.lo, b.ul, b.last
868 184: 54000003 b.cc 184 <back+0x184> // b.lo, b.ul, b.last
869 188: 54fff3c3 b.cc 0 <back> // b.lo, b.ul, b.last
870 18c: 54003723 b.cc 870 <forth> // b.lo, b.ul, b.last
871 190: 54000004 b.mi 190 <back+0x190> // b.first
872 194: 54fff364 b.mi 0 <back> // b.first
873 198: 540036c4 b.mi 870 <forth> // b.first
874 19c: 54000005 b.pl 19c <back+0x19c> // b.nfrst
875 1a0: 54fff305 b.pl 0 <back> // b.nfrst
876 1a4: 54003665 b.pl 870 <forth> // b.nfrst
877 1a8: 54000006 b.vs 1a8 <back+0x1a8>
878 1ac: 54fff2a6 b.vs 0 <back>
879 1b0: 54003606 b.vs 870 <forth>
880 1b4: 54000007 b.vc 1b4 <back+0x1b4>
881 1b8: 54fff247 b.vc 0 <back>
882 1bc: 540035a7 b.vc 870 <forth>
883 1c0: 54000008 b.hi 1c0 <back+0x1c0> // b.pmore
884 1c4: 54fff1e8 b.hi 0 <back> // b.pmore
885 1c8: 54003548 b.hi 870 <forth> // b.pmore
886 1cc: 54000009 b.ls 1cc <back+0x1cc> // b.plast
887 1d0: 54fff189 b.ls 0 <back> // b.plast
888 1d4: 540034e9 b.ls 870 <forth> // b.plast
889 1d8: 5400000a b.ge 1d8 <back+0x1d8> // b.tcont
890 1dc: 54fff12a b.ge 0 <back> // b.tcont
891 1e0: 5400348a b.ge 870 <forth> // b.tcont
892 1e4: 5400000b b.lt 1e4 <back+0x1e4> // b.tstop
893 1e8: 54fff0cb b.lt 0 <back> // b.tstop
894 1ec: 5400342b b.lt 870 <forth> // b.tstop
895 1f0: 5400000c b.gt 1f0 <back+0x1f0>
896 1f4: 54fff06c b.gt 0 <back>
897 1f8: 540033cc b.gt 870 <forth>
898 1fc: 5400000d b.le 1fc <back+0x1fc>
899 200: 54fff00d b.le 0 <back>
900 204: 5400336d b.le 870 <forth>
901 208: 5400000e b.al 208 <back+0x208>
902 20c: 54ffefae b.al 0 <back>
903 210: 5400330e b.al 870 <forth>
904 214: 5400000f b.nv 214 <back+0x214>
905 218: 54ffef4f b.nv 0 <back>
906 21c: 540032af b.nv 870 <forth>
907 220: d40658e1 svc #0x32c7
908 224: d4014d22 hvc #0xa69
909 228: d4046543 smc #0x232a
910 22c: d4273f60 brk #0x39fb
911 230: d44cad80 hlt #0x656c
912 234: d503201f nop
913 238: d69f03e0 eret
914 23c: d6bf03e0 drps
915 240: d5033fdf isb
916 244: d5033e9f dsb st
917 248: d50332bf dmb oshst
918 24c: d61f0200 br x16
919 250: d63f0280 blr x20
920 254: c80a7d1b stxr w10, x27, [x8]
921 258: c800fea1 stlxr w0, x1, [x21]
922 25c: c85f7fb1 ldxr x17, [x29]
923 260: c85fff9d ldaxr x29, [x28]
924 264: c89ffee1 stlr x1, [x23]
925 268: c8dffe95 ldar x21, [x20]
926 26c: 88167e7b stxr w22, w27, [x19]
927 270: 880bfcd0 stlxr w11, w16, [x6]
928 274: 885f7c12 ldxr w18, [x0]
929 278: 885ffd44 ldaxr w4, [x10]
930 27c: 889ffed8 stlr w24, [x22]
931 280: 88dffe6a ldar w10, [x19]
932 284: 48017fc5 stxrh w1, w5, [x30]
933 288: 4808fe2c stlxrh w8, w12, [x17]
934 28c: 485f7dc9 ldxrh w9, [x14]
935 290: 485ffc27 ldaxrh w7, [x1]
936 294: 489ffe05 stlrh w5, [x16]
937 298: 48dffd82 ldarh w2, [x12]
938 29c: 080a7c6c stxrb w10, w12, [x3]
939 2a0: 081cff4e stlxrb w28, w14, [x26]
940 2a4: 085f7d5e ldxrb w30, [x10]
941 2a8: 085ffeae ldaxrb w14, [x21]
942 2ac: 089ffd2d stlrb w13, [x9]
943 2b0: 08dfff76 ldarb w22, [x27]
944 2b4: c87f4d7c ldxp x28, x19, [x11]
945 2b8: c87fcc5e ldaxp x30, x19, [x2]
946 2bc: c8220417 stxp w2, x23, x1, [x0]
947 2c0: c82cb5f0 stlxp w12, x16, x13, [x15]
948 2c4: 887f55b2 ldxp w18, w21, [x13]
949 2c8: 887ff90b ldaxp w11, w30, [x8]
950 2cc: 88382c2d stxp w24, w13, w11, [x1]
951 2d0: 883aedb5 stlxp w26, w21, w27, [x13]
952 2d4: f819928b stur x11, [x20, #-103]
953 2d8: b803e21c stur w28, [x16, #62]
954 2dc: 381f713b sturb w27, [x9, #-9]
955 2e0: 781ce322 sturh w2, [x25, #-50]
956 2e4: f850f044 ldur x4, [x2, #-241]
957 2e8: b85e129e ldur w30, [x20, #-31]
958 2ec: 385e92f2 ldurb w18, [x23, #-23]
959 2f0: 785ff35d ldurh w29, [x26, #-1]
960 2f4: 39801921 ldrsb x1, [x9, #6]
961 2f8: 7881318b ldursh x11, [x12, #19]
962 2fc: 78dce02b ldursh w11, [x1, #-50]
963 300: b8829313 ldursw x19, [x24, #41]
964 304: fc45f318 ldur d24, [x24, #95]
965 308: bc5d50af ldur s15, [x5, #-43]
966 30c: fc001375 stur d21, [x27, #1]
967 310: bc1951b7 stur s23, [x13, #-107]
968 314: f8008c0b str x11, [x0, #8]!
969 318: b801dc03 str w3, [x0, #29]!
970 31c: 38009dcb strb w11, [x14, #9]!
971 320: 781fdf1d strh w29, [x24, #-3]!
972 324: f8570e2d ldr x13, [x17, #-144]!
973 328: b85faecc ldr w12, [x22, #-6]!
974 32c: 385f6d8d ldrb w13, [x12, #-10]!
975 330: 785ebea0 ldrh w0, [x21, #-21]!
976 334: 38804cf7 ldrsb x23, [x7, #4]!
977 338: 789cbce3 ldrsh x3, [x7, #-53]!
978 33c: 78df9cbc ldrsh w28, [x5, #-7]!
979 340: b89eed38 ldrsw x24, [x9, #-18]!
980 344: fc40cd6e ldr d14, [x11, #12]!
981 348: bc5bdd93 ldr s19, [x12, #-67]!
982 34c: fc103c14 str d20, [x0, #-253]!
983 350: bc040c08 str s8, [x0, #64]!
984 354: f81a2784 str x4, [x28], #-94
985 358: b81ca4ec str w12, [x7], #-54
986 35c: 381e855b strb w27, [x10], #-24
987 360: 7801b506 strh w6, [x8], #27
988 364: f853654e ldr x14, [x10], #-202
989 368: b85d74b0 ldr w16, [x5], #-41
990 36c: 384095c2 ldrb w2, [x14], #9
991 370: 785ec5bc ldrh w28, [x13], #-20
992 374: 389e15a9 ldrsb x9, [x13], #-31
993 378: 789dc703 ldrsh x3, [x24], #-36
994 37c: 78c06474 ldrsh w20, [x3], #6
995 380: b89ff667 ldrsw x7, [x19], #-1
996 384: fc57e51e ldr d30, [x8], #-130
997 388: bc4155f9 ldr s25, [x15], #21
998 38c: fc05a6ee str d14, [x23], #90
999 390: bc1df408 str s8, [x0], #-33
1000 394: f835da4a str x10, [x18, w21, sxtw #3]
1001 398: b836d9a4 str w4, [x13, w22, sxtw #2]
1002 39c: 3833580d strb w13, [x0, w19, uxtw #0]
1003 3a0: 7826cb6c strh w12, [x27, w6, sxtw]
1004 3a4: f8706900 ldr x0, [x8, x16]
1005 3a8: b87ae880 ldr w0, [x4, x26, sxtx]
1006 3ac: 3865db2e ldrb w14, [x25, w5, sxtw #0]
1007 3b0: 78724889 ldrh w9, [x4, w18, uxtw]
1008 3b4: 38a7789b ldrsb x27, [x4, x7, lsl #0]
1009 3b8: 78beca2f ldrsh x15, [x17, w30, sxtw]
1010 3bc: 78f6c810 ldrsh w16, [x0, w22, sxtw]
1011 3c0: b8bef956 ldrsw x22, [x10, x30, sxtx #2]
1012 3c4: fc6afabd ldr d29, [x21, x10, sxtx #3]
1013 3c8: bc734963 ldr s3, [x11, w19, uxtw]
1014 3cc: fc3d5b8d str d13, [x28, w29, uxtw #3]
1015 3d0: bc25fbb7 str s23, [x29, x5, sxtx #2]
1016 3d4: f9189d05 str x5, [x8, #12600]
1017 3d8: b91ecb1d str w29, [x24, #7880]
1018 3dc: 39187a33 strb w19, [x17, #1566]
1019 3e0: 791f226d strh w13, [x19, #3984]
1020 3e4: f95aa2f3 ldr x19, [x23, #13632]
1021 3e8: b9587bb7 ldr w23, [x29, #6264]
1022 3ec: 395f7176 ldrb w22, [x11, #2012]
1023 3f0: 795d9143 ldrh w3, [x10, #3784]
1024 3f4: 399e7e08 ldrsb x8, [x16, #1951]
1025 3f8: 799a2697 ldrsh x23, [x20, #3346]
1026 3fc: 79df3422 ldrsh w2, [x1, #3994]
1027 400: b99c2624 ldrsw x4, [x17, #7204]
1028 404: fd5c2374 ldr d20, [x27, #14400]
1029 408: bd5fa1d9 ldr s25, [x14, #8096]
1030 40c: fd1d595a str d26, [x10, #15024]
1031 410: bd1b1869 str s9, [x3, #6936]
1032 414: 580022fb ldr x27, 870 <forth>
1033 418: 1800000b ldr w11, 418 <back+0x418>
1034 41c: f8945060 prfum pldl1keep, [x3, #-187]
1035 420: d8000000 prfm pldl1keep, 420 <back+0x420>
1036 424: f8ae6ba0 prfm pldl1keep, [x29, x14]
1037 428: f99a0080 prfm pldl1keep, [x4, #13312]
1038 42c: 1a070035 adc w21, w1, w7
1039 430: 3a0700a8 adcs w8, w5, w7
1040 434: 5a0e0367 sbc w7, w27, w14
1041 438: 7a11009b sbcs w27, w4, w17
1042 43c: 9a000380 adc x0, x28, x0
1043 440: ba1e030c adcs x12, x24, x30
1044 444: da0f0320 sbc x0, x25, x15
1045 448: fa030301 sbcs x1, x24, x3
1046 44c: 0b340b12 add w18, w24, w20, uxtb #2
1047 450: 2b2a278d adds w13, w28, w10, uxth #1
1048 454: cb22aa0f sub x15, x16, w2, sxth #2
1049 458: 6b2d29bd subs w29, w13, w13, uxth #2
1050 45c: 8b2cce8c add x12, x20, w12, sxtw #3
1051 460: ab2b877e adds x30, x27, w11, sxtb #1
1052 464: cb21c8ee sub x14, x7, w1, sxtw #2
1053 468: eb3ba47d subs x29, x3, w27, sxth #1
1054 46c: 3a4d400e ccmn w0, w13, #0xe, mi // mi = first
1055 470: 7a5232c6 ccmp w22, w18, #0x6, cc // cc = lo, ul, last
1056 474: ba5e624e ccmn x18, x30, #0xe, vs
1057 478: fa53814c ccmp x10, x19, #0xc, hi // hi = pmore
1058 47c: 3a52d8c2 ccmn w6, #0x12, #0x2, le
1059 480: 7a4d8924 ccmp w9, #0xd, #0x4, hi // hi = pmore
1060 484: ba4b3aab ccmn x21, #0xb, #0xb, cc // cc = lo, ul, last
1061 488: fa4d7882 ccmp x4, #0xd, #0x2, vc
1062 48c: 1a96804c csel w12, w2, w22, hi // hi = pmore
1063 490: 1a912618 csinc w24, w16, w17, cs // cs = hs, nlast
1064 494: 5a90b0e6 csinv w6, w7, w16, lt // lt = tstop
1065 498: 5a96976b csneg w11, w27, w22, ls // ls = plast
1066 49c: 9a9db06a csel x10, x3, x29, lt // lt = tstop
1067 4a0: 9a9b374c csinc x12, x26, x27, cc // cc = lo, ul, last
1068 4a4: da95c14f csinv x15, x10, x21, gt
1069 4a8: da89c6fe csneg x30, x23, x9, gt
1070 4ac: 5ac0015e rbit w30, w10
1071 4b0: 5ac005fd rev16 w29, w15
1072 4b4: 5ac00bdd rev w29, w30
1073 4b8: 5ac012b9 clz w25, w21
1074 4bc: 5ac01404 cls w4, w0
1075 4c0: dac002b2 rbit x18, x21
1076 4c4: dac0061d rev16 x29, x16
1077 4c8: dac00a95 rev32 x21, x20
1078 4cc: dac00e66 rev x6, x19
1079 4d0: dac0107e clz x30, x3
1080 4d4: dac01675 cls x21, x19
1081 4d8: 1ac00b0b udiv w11, w24, w0
1082 4dc: 1ace0f3b sdiv w27, w25, w14
1083 4e0: 1ad221c3 lsl w3, w14, w18
1084 4e4: 1ad825e7 lsr w7, w15, w24
1085 4e8: 1ad92a3c asr w28, w17, w25
1086 4ec: 1adc2f42 ror w2, w26, w28
1087 4f0: 9ada0b25 udiv x5, x25, x26
1088 4f4: 9ad20e1b sdiv x27, x16, x18
1089 4f8: 9acc22a6 lsl x6, x21, x12
1090 4fc: 9acc2480 lsr x0, x4, x12
1091 500: 9adc2a3b asr x27, x17, x28
1092 504: 9ad22c5c ror x28, x2, x18
1093 508: 9bce7dea umulh x10, x15, x14
1094 50c: 9b597c6e smulh x14, x3, x25
1095 510: 1b0e166f madd w15, w19, w14, w5
1096 514: 1b1ae490 msub w16, w4, w26, w25
1097 518: 9b023044 madd x4, x2, x2, x12
1098 51c: 9b089e3d msub x29, x17, x8, x7
1099 520: 9b391083 smaddl x3, w4, w25, x4
1100 524: 9b24c73a smsubl x26, w25, w4, x17
1101 528: 9bb15f40 umaddl x0, w26, w17, x23
1102 52c: 9bbcc6af umsubl x15, w21, w28, x17
1103 530: 1e23095b fmul s27, s10, s3
1104 534: 1e3918e0 fdiv s0, s7, s25
1105 538: 1e2f28c9 fadd s9, s6, s15
1106 53c: 1e2a39fd fsub s29, s15, s10
1107 540: 1e270a22 fmul s2, s17, s7
1108 544: 1e77096b fmul d11, d11, d23
1109 548: 1e771ba7 fdiv d7, d29, d23
1110 54c: 1e6b2b6e fadd d14, d27, d11
1111 550: 1e78388b fsub d11, d4, d24
1112 554: 1e6e09ec fmul d12, d15, d14
1113 558: 1f1c3574 fmadd s20, s11, s28, s13
1114 55c: 1f17f98b fmsub s11, s12, s23, s30
1115 560: 1f2935da fnmadd s26, s14, s9, s13
1116 564: 1f2574ea fnmadd s10, s7, s5, s29
1117 568: 1f4b306f fmadd d15, d3, d11, d12
1118 56c: 1f5ec7cf fmsub d15, d30, d30, d17
1119 570: 1f6f3e93 fnmadd d19, d20, d15, d15
1120 574: 1f6226a9 fnmadd d9, d21, d2, d9
1121 578: 1e2040fb fmov s27, s7
1122 57c: 1e20c3dd fabs s29, s30
1123 580: 1e214031 fneg s17, s1
1124 584: 1e21c0c2 fsqrt s2, s6
1125 588: 1e22c06a fcvt d10, s3
1126 58c: 1e604178 fmov d24, d11
1127 590: 1e60c027 fabs d7, d1
1128 594: 1e61400b fneg d11, d0
1129 598: 1e61c243 fsqrt d3, d18
1130 59c: 1e6240dc fcvt s28, d6
1131 5a0: 1e3800d6 fcvtzs w22, s6
1132 5a4: 9e380360 fcvtzs x0, s27
1133 5a8: 1e78005a fcvtzs w26, d2
1134 5ac: 9e7800e5 fcvtzs x5, d7
1135 5b0: 1e22017c scvtf s28, w11
1136 5b4: 9e2201b9 scvtf s25, x13
1137 5b8: 1e6202eb scvtf d11, w23
1138 5bc: 9e620113 scvtf d19, x8
1139 5c0: 1e2602b2 fmov w18, s21
1140 5c4: 9e660299 fmov x25, d20
1141 5c8: 1e270253 fmov s19, w18
1142 5cc: 9e6703a2 fmov d2, x29
1143 5d0: 1e2822c0 fcmp s22, s8
1144 5d4: 1e7322a0 fcmp d21, d19
1145 5d8: 1e202288 fcmp s20, #0.0
1146 5dc: 1e602168 fcmp d11, #0.0
1147 5e0: 293c19f4 stp w20, w6, [x15, #-32]
1148 5e4: 2966387b ldp w27, w14, [x3, #-208]
1149 5e8: 69762971 ldpsw x17, x10, [x11, #-80]
1150 5ec: a9041dc7 stp x7, x7, [x14, #64]
1151 5f0: a9475c0c ldp x12, x23, [x0, #112]
1152 5f4: 29b61ccd stp w13, w7, [x6, #-80]!
1153 5f8: 29ee405e ldp w30, w16, [x2, #-144]!
1154 5fc: 69ee0744 ldpsw x4, x1, [x26, #-144]!
1155 600: a9843977 stp x23, x14, [x11, #64]!
1156 604: a9f46ebd ldp x29, x27, [x21, #-192]!
1157 608: 28ba16b6 stp w22, w5, [x21], #-48
1158 60c: 28fc44db ldp w27, w17, [x6], #-32
1159 610: 68f61831 ldpsw x17, x6, [x1], #-80
1160 614: a8b352ad stp x13, x20, [x21], #-208
1161 618: a8c56d5e ldp x30, x27, [x10], #80
1162 61c: 28024565 stnp w5, w17, [x11, #16]
1163 620: 2874134e ldnp w14, w4, [x26, #-96]
1164 624: a8027597 stnp x23, x29, [x12, #32]
1165 628: a87b1aa0 ldnp x0, x6, [x21, #-80]
1166 62c: 0c40734f ld1 {v15.8b}, [x26]
1167 630: 4cdfa177 ld1 {v23.16b, v24.16b}, [x11], #32
1168 634: 0cc76ee8 ld1 {v8.1d-v10.1d}, [x23], x7
1169 638: 4cdf2733 ld1 {v19.8h-v22.8h}, [x25], #64
1170 63c: 0d40c23d ld1r {v29.8b}, [x17]
1171 640: 4ddfcaf8 ld1r {v24.4s}, [x23], #4
1172 644: 0dd9ccaa ld1r {v10.1d}, [x5], x25
1173 648: 4c408d52 ld2 {v18.2d, v19.2d}, [x10]
1174 64c: 0cdf85ec ld2 {v12.4h, v13.4h}, [x15], #16
1175 650: 4d60c259 ld2r {v25.16b, v26.16b}, [x18]
1176 654: 0dffcbc1 ld2r {v1.2s, v2.2s}, [x30], #8
1177 658: 4de9ce50 ld2r {v16.2d, v17.2d}, [x18], x9
1178 65c: 4cc24999 ld3 {v25.4s-v27.4s}, [x12], x2
1179 660: 0c404a7a ld3 {v26.2s-v28.2s}, [x19]
1180 664: 4d40e6af ld3r {v15.8h-v17.8h}, [x21]
1181 668: 4ddfe9b9 ld3r {v25.4s-v27.4s}, [x13], #12
1182 66c: 0dddef8e ld3r {v14.1d-v16.1d}, [x28], x29
1183 670: 4cdf07b1 ld4 {v17.8h-v20.8h}, [x29], #64
1184 674: 0cc000fb ld4 {v27.8b-v30.8b}, [x7], x0
1185 678: 0d60e258 ld4r {v24.8b-v27.8b}, [x18]
1186 67c: 0dffe740 ld4r {v0.4h-v3.4h}, [x26], #8
1187 680: 0de2eb2c ld4r {v12.2s-v15.2s}, [x25], x2
1188 684: ce648376 sha512h q22, q27, v4.2d
1189 688: ce6184c7 sha512h2 q7, q6, v1.2d
1190 68c: cec081fa sha512su0 v26.2d, v15.2d
1191 690: ce6d89a2 sha512su1 v2.2d, v13.2d, v13.2d
1192 694: ba5fd3e3 ccmn xzr, xzr, #0x3, le
1193 698: 3a5f03e5 ccmn wzr, wzr, #0x5, eq // eq = none
1194 69c: fa411be4 ccmp xzr, #0x1, #0x4, ne // ne = any
1195 6a0: 7a42cbe2 ccmp wzr, #0x2, #0x2, gt
1196 6a4: 93df03ff ror xzr, xzr, #0
1197 6a8: c820ffff stlxp w0, xzr, xzr, [sp]
1198 6ac: 8822fc7f stlxp w2, wzr, wzr, [x3]
1199 6b0: c8247cbf stxp w4, xzr, xzr, [x5]
1200 6b4: 88267fff stxp w6, wzr, wzr, [sp]
1201 6b8: 4e010fe0 dup v0.16b, wzr
1202 6bc: 4e081fe1 mov v1.d[0], xzr
1203 6c0: 4e0c1fe1 mov v1.s[1], wzr
1204 6c4: 4e0a1fe1 mov v1.h[2], wzr
1205 6c8: 4e071fe1 mov v1.b[3], wzr
1206 6cc: 4cc0ac3f ld1 {v31.2d, v0.2d}, [x1], x0
1207 6d0: 1e601000 fmov d0, #2.000000000000000000e+00
1208 6d4: 1e603000 fmov d0, #2.125000000000000000e+00
1209 6d8: 1e621000 fmov d0, #4.000000000000000000e+00
1210 6dc: 1e623000 fmov d0, #4.250000000000000000e+00
1211 6e0: 1e641000 fmov d0, #8.000000000000000000e+00
1212 6e4: 1e643000 fmov d0, #8.500000000000000000e+00
1213 6e8: 1e661000 fmov d0, #1.600000000000000000e+01
1214 6ec: 1e663000 fmov d0, #1.700000000000000000e+01
1215 6f0: 1e681000 fmov d0, #1.250000000000000000e-01
1216 6f4: 1e683000 fmov d0, #1.328125000000000000e-01
1217 6f8: 1e6a1000 fmov d0, #2.500000000000000000e-01
1218 6fc: 1e6a3000 fmov d0, #2.656250000000000000e-01
1219 700: 1e6c1000 fmov d0, #5.000000000000000000e-01
1220 704: 1e6c3000 fmov d0, #5.312500000000000000e-01
1221 708: 1e6e1000 fmov d0, #1.000000000000000000e+00
1222 70c: 1e6e3000 fmov d0, #1.062500000000000000e+00
1223 710: 1e701000 fmov d0, #-2.000000000000000000e+00
1224 714: 1e703000 fmov d0, #-2.125000000000000000e+00
1225 718: 1e721000 fmov d0, #-4.000000000000000000e+00
1226 71c: 1e723000 fmov d0, #-4.250000000000000000e+00
1227 720: 1e741000 fmov d0, #-8.000000000000000000e+00
1228 724: 1e743000 fmov d0, #-8.500000000000000000e+00
1229 728: 1e761000 fmov d0, #-1.600000000000000000e+01
1230 72c: 1e763000 fmov d0, #-1.700000000000000000e+01
1231 730: 1e781000 fmov d0, #-1.250000000000000000e-01
1232 734: 1e783000 fmov d0, #-1.328125000000000000e-01
1233 738: 1e7a1000 fmov d0, #-2.500000000000000000e-01
1234 73c: 1e7a3000 fmov d0, #-2.656250000000000000e-01
1235 740: 1e7c1000 fmov d0, #-5.000000000000000000e-01
1236 744: 1e7c3000 fmov d0, #-5.312500000000000000e-01
1237 748: 1e7e1000 fmov d0, #-1.000000000000000000e+00
1238 74c: 1e7e3000 fmov d0, #-1.062500000000000000e+00
1239 750: f8388098 swp x24, x24, [x4]
1240 754: f8340010 ldadd x20, x16, [x0]
1241 758: f8241175 ldclr x4, x21, [x11]
1242 75c: f83e22d0 ldeor x30, x16, [x22]
1243 760: f82432ef ldset x4, x15, [x23]
1244 764: f83a5186 ldsmin x26, x6, [x12]
1245 768: f82f41ee ldsmax x15, x14, [x15]
1246 76c: f82973b9 ldumin x9, x25, [x29]
1247 770: f82b6194 ldumax x11, x20, [x12]
1248 774: f8b28216 swpa x18, x22, [x16]
1249 778: f8b50358 ldadda x21, x24, [x26]
1250 77c: f8a61206 ldclra x6, x6, [x16]
1251 780: f8b02219 ldeora x16, x25, [x16]
1252 784: f8bc3218 ldseta x28, x24, [x16]
1253 788: f8ba514f ldsmina x26, x15, [x10]
1254 78c: f8ad428e ldsmaxa x13, x14, [x20]
1255 790: f8a173d7 ldumina x1, x23, [x30]
1256 794: f8ae60c2 ldumaxa x14, x2, [x6]
1257 798: f8e38328 swpal x3, x8, [x25]
1258 79c: f8e003db ldaddal x0, x27, [x30]
1259 7a0: f8e513c5 ldclral x5, x5, [x30]
1260 7a4: f8eb2019 ldeoral x11, x25, [x0]
1261 7a8: f8ff3260 ldsetal xzr, x0, [x19]
1262 7ac: f8fd513a ldsminal x29, x26, [x9]
1263 7b0: f8fa41ec ldsmaxal x26, x12, [x15]
1264 7b4: f8eb724b lduminal x11, x11, [x18]
1265 7b8: f8f96316 ldumaxal x25, x22, [x24]
1266 7bc: f8608171 swpl x0, x17, [x11]
1267 7c0: f86600dd ldaddl x6, x29, [x6]
1268 7c4: f86512a5 ldclrl x5, x5, [x21]
1269 7c8: f8732250 ldeorl x19, x16, [x18]
1270 7cc: f87e339b ldsetl x30, x27, [x28]
1271 7d0: f861503c ldsminl x1, x28, [x1]
1272 7d4: f874421d ldsmaxl x20, x29, [x16]
1273 7d8: f86d73aa lduminl x13, x10, [x29]
1274 7dc: f87d62d3 ldumaxl x29, x19, [x22]
1275 7e0: b82a83e4 swp w10, w4, [sp]
1276 7e4: b83503e8 ldadd w21, w8, [sp]
1277 7e8: b833138a ldclr w19, w10, [x28]
1278 7ec: b82220b9 ldeor w2, w25, [x5]
1279 7f0: b82332c8 ldset w3, w8, [x22]
1280 7f4: b83350ad ldsmin w19, w13, [x5]
1281 7f8: b83d42b8 ldsmax w29, w24, [x21]
1282 7fc: b83a7078 ldumin w26, w24, [x3]
1283 800: b83862fa ldumax w24, w26, [x23]
1284 804: b8af8075 swpa w15, w21, [x3]
1285 808: b8b80328 ldadda w24, w8, [x25]
1286 80c: b8b41230 ldclra w20, w16, [x17]
1287 810: b8a22001 ldeora w2, w1, [x0]
1288 814: b8b83064 ldseta w24, w4, [x3]
1289 818: b8ac539f ldsmina w12, wzr, [x28]
1290 81c: b8aa405a ldsmaxa w10, w26, [x2]
1291 820: b8ac73f2 ldumina w12, w18, [sp]
1292 824: b8a163ad ldumaxa w1, w13, [x29]
1293 828: b8e08193 swpal w0, w19, [x12]
1294 82c: b8f101b6 ldaddal w17, w22, [x13]
1295 830: b8fc13fe ldclral w28, w30, [sp]
1296 834: b8e1239a ldeoral w1, w26, [x28]
1297 838: b8e4309e ldsetal w4, w30, [x4]
1298 83c: b8e6535e ldsminal w6, w30, [x26]
1299 840: b8f24109 ldsmaxal w18, w9, [x8]
1300 844: b8ec7280 lduminal w12, w0, [x20]
1301 848: b8e16058 ldumaxal w1, w24, [x2]
1302 84c: b8608309 swpl w0, w9, [x24]
1303 850: b87a03d0 ldaddl w26, w16, [x30]
1304 854: b86312ea ldclrl w3, w10, [x23]
1305 858: b86a2244 ldeorl w10, w4, [x18]
1306 85c: b862310b ldsetl w2, w11, [x8]
1307 860: b86a522f ldsminl w10, w15, [x17]
1308 864: b862418a ldsmaxl w2, w10, [x12]
1309 868: b86c71af lduminl w12, w15, [x13]
1310 86c: b8626287 ldumaxl w2, w7, [x20]
1311 */
1312
1313 static const unsigned int insns[] =
1314 {
1315 0x8b0d82fa, 0xcb49970c, 0xab889dfc, 0xeb9ee787,
1316 0x0b9b3ec9, 0x4b9279a3, 0x2b88474e, 0x6b8c56c0,
1317 0x8a1a51e0, 0xaa11f4ba, 0xca0281b8, 0xea918c7c,
1318 0x0a5d4a19, 0x2a4b264d, 0x4a523ca5, 0x6a9b6ae2,
1319 0x8a70b79b, 0xaaba9728, 0xca6dfe3d, 0xea627f1c,
1320 0x0aa70f53, 0x2aaa0f06, 0x4a6176a4, 0x6a604eb0,
1321 0x1105ed91, 0x3100583e, 0x5101f8bd, 0x710f0306,
1322 0x9101a1a0, 0xb10a5cc8, 0xd10810aa, 0xf10fd061,
1323 0x120cb166, 0x321764bc, 0x52174681, 0x720c0247,
1324 0x9241018e, 0xb25a2969, 0xd278b411, 0xf26aad01,
1325 0x14000000, 0x17ffffd7, 0x140001f2, 0x94000000,
1326 0x97ffffd4, 0x940001ef, 0x3400000a, 0x34fffa2a,
1327 0x34003d8a, 0x35000008, 0x35fff9c8, 0x35003d28,
1328 0xb400000b, 0xb4fff96b, 0xb4003ccb, 0xb500001d,
1329 0xb5fff91d, 0xb5003c7d, 0x10000013, 0x10fff8b3,
1330 0x10003c13, 0x90000013, 0x36300016, 0x3637f836,
1331 0x36303b96, 0x3758000c, 0x375ff7cc, 0x37583b2c,
1332 0x128313a0, 0x528a32c7, 0x7289173b, 0x92ab3acc,
1333 0xd2a0bf94, 0xf2c285e8, 0x9358722f, 0x330e652f,
1334 0x53067f3b, 0x93577c53, 0xb34a1aac, 0xd35a4016,
1335 0x13946c63, 0x93c3dbc8, 0x54000000, 0x54fff5a0,
1336 0x54003900, 0x54000001, 0x54fff541, 0x540038a1,
1337 0x54000002, 0x54fff4e2, 0x54003842, 0x54000002,
1338 0x54fff482, 0x540037e2, 0x54000003, 0x54fff423,
1339 0x54003783, 0x54000003, 0x54fff3c3, 0x54003723,
1340 0x54000004, 0x54fff364, 0x540036c4, 0x54000005,
1341 0x54fff305, 0x54003665, 0x54000006, 0x54fff2a6,
1342 0x54003606, 0x54000007, 0x54fff247, 0x540035a7,
1343 0x54000008, 0x54fff1e8, 0x54003548, 0x54000009,
1344 0x54fff189, 0x540034e9, 0x5400000a, 0x54fff12a,
1345 0x5400348a, 0x5400000b, 0x54fff0cb, 0x5400342b,
1346 0x5400000c, 0x54fff06c, 0x540033cc, 0x5400000d,
1347 0x54fff00d, 0x5400336d, 0x5400000e, 0x54ffefae,
1348 0x5400330e, 0x5400000f, 0x54ffef4f, 0x540032af,
1349 0xd40658e1, 0xd4014d22, 0xd4046543, 0xd4273f60,
1350 0xd44cad80, 0xd503201f, 0xd69f03e0, 0xd6bf03e0,
1351 0xd5033fdf, 0xd5033e9f, 0xd50332bf, 0xd61f0200,
1352 0xd63f0280, 0xc80a7d1b, 0xc800fea1, 0xc85f7fb1,
1353 0xc85fff9d, 0xc89ffee1, 0xc8dffe95, 0x88167e7b,
1354 0x880bfcd0, 0x885f7c12, 0x885ffd44, 0x889ffed8,
1355 0x88dffe6a, 0x48017fc5, 0x4808fe2c, 0x485f7dc9,
1356 0x485ffc27, 0x489ffe05, 0x48dffd82, 0x080a7c6c,
1357 0x081cff4e, 0x085f7d5e, 0x085ffeae, 0x089ffd2d,
1358 0x08dfff76, 0xc87f4d7c, 0xc87fcc5e, 0xc8220417,
1359 0xc82cb5f0, 0x887f55b2, 0x887ff90b, 0x88382c2d,
1360 0x883aedb5, 0xf819928b, 0xb803e21c, 0x381f713b,
1361 0x781ce322, 0xf850f044, 0xb85e129e, 0x385e92f2,
1362 0x785ff35d, 0x39801921, 0x7881318b, 0x78dce02b,
1363 0xb8829313, 0xfc45f318, 0xbc5d50af, 0xfc001375,
1364 0xbc1951b7, 0xf8008c0b, 0xb801dc03, 0x38009dcb,
1365 0x781fdf1d, 0xf8570e2d, 0xb85faecc, 0x385f6d8d,
1366 0x785ebea0, 0x38804cf7, 0x789cbce3, 0x78df9cbc,
1367 0xb89eed38, 0xfc40cd6e, 0xbc5bdd93, 0xfc103c14,
1368 0xbc040c08, 0xf81a2784, 0xb81ca4ec, 0x381e855b,
1369 0x7801b506, 0xf853654e, 0xb85d74b0, 0x384095c2,
1370 0x785ec5bc, 0x389e15a9, 0x789dc703, 0x78c06474,
1371 0xb89ff667, 0xfc57e51e, 0xbc4155f9, 0xfc05a6ee,
1372 0xbc1df408, 0xf835da4a, 0xb836d9a4, 0x3833580d,
1373 0x7826cb6c, 0xf8706900, 0xb87ae880, 0x3865db2e,
1374 0x78724889, 0x38a7789b, 0x78beca2f, 0x78f6c810,
1375 0xb8bef956, 0xfc6afabd, 0xbc734963, 0xfc3d5b8d,
1376 0xbc25fbb7, 0xf9189d05, 0xb91ecb1d, 0x39187a33,
1377 0x791f226d, 0xf95aa2f3, 0xb9587bb7, 0x395f7176,
1378 0x795d9143, 0x399e7e08, 0x799a2697, 0x79df3422,
1379 0xb99c2624, 0xfd5c2374, 0xbd5fa1d9, 0xfd1d595a,
1380 0xbd1b1869, 0x580022fb, 0x1800000b, 0xf8945060,
1381 0xd8000000, 0xf8ae6ba0, 0xf99a0080, 0x1a070035,
1382 0x3a0700a8, 0x5a0e0367, 0x7a11009b, 0x9a000380,
1383 0xba1e030c, 0xda0f0320, 0xfa030301, 0x0b340b12,
1384 0x2b2a278d, 0xcb22aa0f, 0x6b2d29bd, 0x8b2cce8c,
1385 0xab2b877e, 0xcb21c8ee, 0xeb3ba47d, 0x3a4d400e,
1386 0x7a5232c6, 0xba5e624e, 0xfa53814c, 0x3a52d8c2,
1387 0x7a4d8924, 0xba4b3aab, 0xfa4d7882, 0x1a96804c,
1388 0x1a912618, 0x5a90b0e6, 0x5a96976b, 0x9a9db06a,
1389 0x9a9b374c, 0xda95c14f, 0xda89c6fe, 0x5ac0015e,
1390 0x5ac005fd, 0x5ac00bdd, 0x5ac012b9, 0x5ac01404,
1391 0xdac002b2, 0xdac0061d, 0xdac00a95, 0xdac00e66,
1392 0xdac0107e, 0xdac01675, 0x1ac00b0b, 0x1ace0f3b,
1393 0x1ad221c3, 0x1ad825e7, 0x1ad92a3c, 0x1adc2f42,
1394 0x9ada0b25, 0x9ad20e1b, 0x9acc22a6, 0x9acc2480,
1395 0x9adc2a3b, 0x9ad22c5c, 0x9bce7dea, 0x9b597c6e,
1396 0x1b0e166f, 0x1b1ae490, 0x9b023044, 0x9b089e3d,
1397 0x9b391083, 0x9b24c73a, 0x9bb15f40, 0x9bbcc6af,
1398 0x1e23095b, 0x1e3918e0, 0x1e2f28c9, 0x1e2a39fd,
1399 0x1e270a22, 0x1e77096b, 0x1e771ba7, 0x1e6b2b6e,
1400 0x1e78388b, 0x1e6e09ec, 0x1f1c3574, 0x1f17f98b,
1401 0x1f2935da, 0x1f2574ea, 0x1f4b306f, 0x1f5ec7cf,
1402 0x1f6f3e93, 0x1f6226a9, 0x1e2040fb, 0x1e20c3dd,
1403 0x1e214031, 0x1e21c0c2, 0x1e22c06a, 0x1e604178,
1404 0x1e60c027, 0x1e61400b, 0x1e61c243, 0x1e6240dc,
1405 0x1e3800d6, 0x9e380360, 0x1e78005a, 0x9e7800e5,
1406 0x1e22017c, 0x9e2201b9, 0x1e6202eb, 0x9e620113,
1407 0x1e2602b2, 0x9e660299, 0x1e270253, 0x9e6703a2,
1408 0x1e2822c0, 0x1e7322a0, 0x1e202288, 0x1e602168,
1409 0x293c19f4, 0x2966387b, 0x69762971, 0xa9041dc7,
1410 0xa9475c0c, 0x29b61ccd, 0x29ee405e, 0x69ee0744,
1411 0xa9843977, 0xa9f46ebd, 0x28ba16b6, 0x28fc44db,
1412 0x68f61831, 0xa8b352ad, 0xa8c56d5e, 0x28024565,
1413 0x2874134e, 0xa8027597, 0xa87b1aa0, 0x0c40734f,
1414 0x4cdfa177, 0x0cc76ee8, 0x4cdf2733, 0x0d40c23d,
1415 0x4ddfcaf8, 0x0dd9ccaa, 0x4c408d52, 0x0cdf85ec,
1416 0x4d60c259, 0x0dffcbc1, 0x4de9ce50, 0x4cc24999,
1417 0x0c404a7a, 0x4d40e6af, 0x4ddfe9b9, 0x0dddef8e,
1418 0x4cdf07b1, 0x0cc000fb, 0x0d60e258, 0x0dffe740,
1419 0x0de2eb2c, 0xce648376, 0xce6184c7, 0xcec081fa,
1420 0xce6d89a2, 0xba5fd3e3, 0x3a5f03e5, 0xfa411be4,
1421 0x7a42cbe2, 0x93df03ff, 0xc820ffff, 0x8822fc7f,
1422 0xc8247cbf, 0x88267fff, 0x4e010fe0, 0x4e081fe1,
1423 0x4e0c1fe1, 0x4e0a1fe1, 0x4e071fe1, 0x4cc0ac3f,
1424 0x1e601000, 0x1e603000, 0x1e621000, 0x1e623000,
1425 0x1e641000, 0x1e643000, 0x1e661000, 0x1e663000,
1426 0x1e681000, 0x1e683000, 0x1e6a1000, 0x1e6a3000,
1427 0x1e6c1000, 0x1e6c3000, 0x1e6e1000, 0x1e6e3000,
1428 0x1e701000, 0x1e703000, 0x1e721000, 0x1e723000,
1429 0x1e741000, 0x1e743000, 0x1e761000, 0x1e763000,
1430 0x1e781000, 0x1e783000, 0x1e7a1000, 0x1e7a3000,
1431 0x1e7c1000, 0x1e7c3000, 0x1e7e1000, 0x1e7e3000,
1432 0xf8388098, 0xf8340010, 0xf8241175, 0xf83e22d0,
1433 0xf82432ef, 0xf83a5186, 0xf82f41ee, 0xf82973b9,
1434 0xf82b6194, 0xf8b28216, 0xf8b50358, 0xf8a61206,
1435 0xf8b02219, 0xf8bc3218, 0xf8ba514f, 0xf8ad428e,
1436 0xf8a173d7, 0xf8ae60c2, 0xf8e38328, 0xf8e003db,
1437 0xf8e513c5, 0xf8eb2019, 0xf8ff3260, 0xf8fd513a,
1438 0xf8fa41ec, 0xf8eb724b, 0xf8f96316, 0xf8608171,
1439 0xf86600dd, 0xf86512a5, 0xf8732250, 0xf87e339b,
1440 0xf861503c, 0xf874421d, 0xf86d73aa, 0xf87d62d3,
1441 0xb82a83e4, 0xb83503e8, 0xb833138a, 0xb82220b9,
1442 0xb82332c8, 0xb83350ad, 0xb83d42b8, 0xb83a7078,
1443 0xb83862fa, 0xb8af8075, 0xb8b80328, 0xb8b41230,
1444 0xb8a22001, 0xb8b83064, 0xb8ac539f, 0xb8aa405a,
1445 0xb8ac73f2, 0xb8a163ad, 0xb8e08193, 0xb8f101b6,
1446 0xb8fc13fe, 0xb8e1239a, 0xb8e4309e, 0xb8e6535e,
1447 0xb8f24109, 0xb8ec7280, 0xb8e16058, 0xb8608309,
1448 0xb87a03d0, 0xb86312ea, 0xb86a2244, 0xb862310b,
1449 0xb86a522f, 0xb862418a, 0xb86c71af, 0xb8626287,
1450
1451 };
1452 // END Generated code -- do not edit
1453
1454 asm_check((unsigned int *)entry, insns, sizeof insns / sizeof insns[0]);
1455
1456 {
1457 address PC = __ pc();
1458 __ ld1(v0, __ T16B, Address(r16)); // No offset
1459 __ ld1(v0, __ T8H, __ post(r16, 16)); // Post-index
1460 __ ld2(v0, v1, __ T8H, __ post(r24, 16 * 2)); // Post-index
1461 __ ld1(v0, __ T16B, __ post(r16, r17)); // Register post-index
1462 static const unsigned int vector_insns[] = {
1463 0x4c407200, // ld1 {v0.16b}, [x16]
1464 0x4cdf7600, // ld1 {v0.8h}, [x16], #16
1465 0x4cdf8700, // ld2 {v0.8h, v1.8h}, [x24], #32
1466 0x4cd17200, // ld1 {v0.16b}, [x16], x17
1467 };
1468 asm_check((unsigned int *)PC, vector_insns,
1469 sizeof vector_insns / sizeof vector_insns[0]);
1470 }
1471 }
1472 #endif // ASSERT
1473
1474 #undef __
1475
1476 void Assembler::emit_data64(jlong data,
1477 relocInfo::relocType rtype,
1478 int format) {
1479 if (rtype == relocInfo::none) {
1480 emit_int64(data);
1481 } else {
1482 emit_data64(data, Relocation::spec_simple(rtype), format);
1483 }
1484 }
1485
1486 void Assembler::emit_data64(jlong data,
1487 RelocationHolder const& rspec,
1488 int format) {
1489
1490 assert(inst_mark() != NULL, "must be inside InstructionMark");
1491 // Do not use AbstractAssembler::relocate, which is not intended for
1492 // embedded words. Instead, relocate to the enclosing instruction.
1493 code_section()->relocate(inst_mark(), rspec, format);
1494 emit_int64(data);
1495 }
1496
1497 extern "C" {
1498 void das(uint64_t start, int len) {
1499 ResourceMark rm;
1500 len <<= 2;
1501 if (len < 0)
1502 Disassembler::decode((address)start + len, (address)start);
1503 else
1504 Disassembler::decode((address)start, (address)start + len);
1505 }
1506
1507 JNIEXPORT void das1(uintptr_t insn) {
1508 das(insn, 1);
1509 }
1510 }
1511
1512 #define gas_assert(ARG1) assert(ARG1, #ARG1)
1513
1514 #define __ as->
1515
1516 void Address::lea(MacroAssembler *as, Register r) const {
1517 Relocation* reloc = _rspec.reloc();
1518 relocInfo::relocType rtype = (relocInfo::relocType) reloc->type();
1519
1520 switch(_mode) {
1521 case base_plus_offset: {
1522 if (_offset == 0 && _base == r) // it's a nop
1523 break;
1524 if (_offset > 0)
1525 __ add(r, _base, _offset);
1526 else
1527 __ sub(r, _base, -_offset);
1528 break;
1529 }
1530 case base_plus_offset_reg: {
1531 __ add(r, _base, _index, _ext.op(), MAX2(_ext.shift(), 0));
1532 break;
1533 }
1534 case literal: {
1535 if (rtype == relocInfo::none)
1536 __ mov(r, target());
1537 else
1538 __ movptr(r, (uint64_t)target());
1539 break;
1540 }
1541 default:
1542 ShouldNotReachHere();
1543 }
1544 }
1545
1546 void Assembler::adrp(Register reg1, const Address &dest, uintptr_t &byte_offset) {
1547 ShouldNotReachHere();
1548 }
1549
1550 #undef __
1551
1552 #define starti Instruction_aarch64 do_not_use(this); set_current(&do_not_use)
1553
1554 void Assembler::adr(Register Rd, address adr) {
1555 intptr_t offset = adr - pc();
1556 int offset_lo = offset & 3;
1557 offset >>= 2;
1558 starti;
1559 f(0, 31), f(offset_lo, 30, 29), f(0b10000, 28, 24), sf(offset, 23, 5);
1560 rf(Rd, 0);
1561 }
1562
1563 void Assembler::_adrp(Register Rd, address adr) {
1564 uint64_t pc_page = (uint64_t)pc() >> 12;
1565 uint64_t adr_page = (uint64_t)adr >> 12;
1566 intptr_t offset = adr_page - pc_page;
1567 int offset_lo = offset & 3;
1568 offset >>= 2;
1569 starti;
1570 f(1, 31), f(offset_lo, 30, 29), f(0b10000, 28, 24), sf(offset, 23, 5);
1571 rf(Rd, 0);
1572 }
1573
1574 #undef starti
1575
1576 Address::Address(address target, relocInfo::relocType rtype) : _mode(literal){
1577 _is_lval = false;
1578 _target = target;
1579 switch (rtype) {
1580 case relocInfo::oop_type:
1581 case relocInfo::metadata_type:
1582 // Oops are a special case. Normally they would be their own section
1583 // but in cases like icBuffer they are literals in the code stream that
1584 // we don't have a section for. We use none so that we get a literal address
1585 // which is always patchable.
1586 break;
1587 case relocInfo::external_word_type:
1588 _rspec = external_word_Relocation::spec(target);
1589 break;
1590 case relocInfo::internal_word_type:
1591 _rspec = internal_word_Relocation::spec(target);
1592 break;
1593 case relocInfo::opt_virtual_call_type:
1594 _rspec = opt_virtual_call_Relocation::spec();
1595 break;
1596 case relocInfo::static_call_type:
1597 _rspec = static_call_Relocation::spec();
1598 break;
1599 case relocInfo::runtime_call_type:
1600 _rspec = runtime_call_Relocation::spec();
1601 break;
1602 case relocInfo::poll_type:
1603 case relocInfo::poll_return_type:
1604 _rspec = Relocation::spec_simple(rtype);
1605 break;
1606 case relocInfo::none:
1607 _rspec = RelocationHolder::none;
1608 break;
1609 default:
1610 ShouldNotReachHere();
1611 break;
1612 }
1613 }
1614
1615 void Assembler::b(const Address &dest) {
1616 code_section()->relocate(pc(), dest.rspec());
1617 b(dest.target());
1618 }
1619
1620 void Assembler::bl(const Address &dest) {
1621 code_section()->relocate(pc(), dest.rspec());
1622 bl(dest.target());
1623 }
1624
1625 void Assembler::adr(Register r, const Address &dest) {
1626 code_section()->relocate(pc(), dest.rspec());
1627 adr(r, dest.target());
1628 }
1629
1630 void Assembler::br(Condition cc, Label &L) {
1631 if (L.is_bound()) {
1632 br(cc, target(L));
1633 } else {
1634 L.add_patch_at(code(), locator());
1635 br(cc, pc());
1636 }
1637 }
1638
1639 void Assembler::wrap_label(Label &L,
1640 Assembler::uncond_branch_insn insn) {
1641 if (L.is_bound()) {
1642 (this->*insn)(target(L));
1643 } else {
1644 L.add_patch_at(code(), locator());
1645 (this->*insn)(pc());
1646 }
1647 }
1648
1649 void Assembler::wrap_label(Register r, Label &L,
1650 compare_and_branch_insn insn) {
1651 if (L.is_bound()) {
1652 (this->*insn)(r, target(L));
1653 } else {
1654 L.add_patch_at(code(), locator());
1655 (this->*insn)(r, pc());
1656 }
1657 }
1658
1659 void Assembler::wrap_label(Register r, int bitpos, Label &L,
1660 test_and_branch_insn insn) {
1661 if (L.is_bound()) {
1662 (this->*insn)(r, bitpos, target(L));
1663 } else {
1664 L.add_patch_at(code(), locator());
1665 (this->*insn)(r, bitpos, pc());
1666 }
1667 }
1668
1669 void Assembler::wrap_label(Label &L, prfop op, prefetch_insn insn) {
1670 if (L.is_bound()) {
1671 (this->*insn)(target(L), op);
1672 } else {
1673 L.add_patch_at(code(), locator());
1674 (this->*insn)(pc(), op);
1675 }
1676 }
1677
1678 // An "all-purpose" add/subtract immediate, per ARM documentation:
1679 // A "programmer-friendly" assembler may accept a negative immediate
1680 // between -(2^24 -1) and -1 inclusive, causing it to convert a
1681 // requested ADD operation to a SUB, or vice versa, and then encode
1682 // the absolute value of the immediate as for uimm24.
1683 void Assembler::add_sub_immediate(Register Rd, Register Rn, unsigned uimm, int op,
1684 int negated_op) {
1685 bool sets_flags = op & 1; // this op sets flags
1686 union {
1687 unsigned u;
1688 int imm;
1689 };
1690 u = uimm;
1691 bool shift = false;
1692 bool neg = imm < 0;
1693 if (neg) {
1694 imm = -imm;
1695 op = negated_op;
1696 }
1697 assert(Rd != sp || imm % 16 == 0, "misaligned stack");
1698 if (imm >= (1 << 11)
1699 && ((imm >> 12) << 12 == imm)) {
1700 imm >>= 12;
1701 shift = true;
1702 }
1703 f(op, 31, 29), f(0b10001, 28, 24), f(shift, 23, 22), f(imm, 21, 10);
1704
1705 // add/subtract immediate ops with the S bit set treat r31 as zr;
1706 // with S unset they use sp.
1707 if (sets_flags)
1708 zrf(Rd, 0);
1709 else
1710 srf(Rd, 0);
1711
1712 srf(Rn, 5);
1713 }
1714
1715 bool Assembler::operand_valid_for_add_sub_immediate(int64_t imm) {
1716 bool shift = false;
1717 uint64_t uimm = (uint64_t)uabs(imm);
1718 if (uimm < (1 << 12))
1719 return true;
1720 if (uimm < (1 << 24)
1721 && ((uimm >> 12) << 12 == uimm)) {
1722 return true;
1723 }
1724 return false;
1725 }
1726
1727 bool Assembler::operand_valid_for_logical_immediate(bool is32, uint64_t imm) {
1728 return encode_logical_immediate(is32, imm) != 0xffffffff;
1729 }
1730
1731 static uint64_t doubleTo64Bits(jdouble d) {
1732 union {
1733 jdouble double_value;
1734 uint64_t double_bits;
1735 };
1736
1737 double_value = d;
1738 return double_bits;
1739 }
1740
1741 bool Assembler::operand_valid_for_float_immediate(double imm) {
1742 // If imm is all zero bits we can use ZR as the source of a
1743 // floating-point value.
1744 if (doubleTo64Bits(imm) == 0)
1745 return true;
1746
1747 // Otherwise try to encode imm then convert the encoded value back
1748 // and make sure it's the exact same bit pattern.
1749 unsigned result = encoding_for_fp_immediate(imm);
1750 return doubleTo64Bits(imm) == fp_immediate_for_encoding(result, true);
1751 }
1752
1753 int AbstractAssembler::code_fill_byte() {
1754 return 0;
1755 }
1756
1757 // n.b. this is implemented in subclass MacroAssembler
1758 void Assembler::bang_stack_with_offset(int offset) { Unimplemented(); }
1759
1760
1761 // and now the routines called by the assembler which encapsulate the
1762 // above encode and decode functions
1763
1764 uint32_t
1765 asm_util::encode_logical_immediate(bool is32, uint64_t imm)
1766 {
1767 if (is32) {
1768 /* Allow all zeros or all ones in top 32-bits, so that
1769 constant expressions like ~1 are permitted. */
1770 if (imm >> 32 != 0 && imm >> 32 != 0xffffffff)
1771 return 0xffffffff;
1772 /* Replicate the 32 lower bits to the 32 upper bits. */
1773 imm &= 0xffffffff;
1774 imm |= imm << 32;
1775 }
1776
1777 return encoding_for_logical_immediate(imm);
1778 }
1779
1780 unsigned Assembler::pack(double value) {
1781 float val = (float)value;
1782 unsigned result = encoding_for_fp_immediate(val);
1783 guarantee(unpack(result) == value,
1784 "Invalid floating-point immediate operand");
1785 return result;
1786 }
1787
1788 // Packed operands for Floating-point Move (immediate)
1789
1790 static float unpack(unsigned value) {
1791 union {
1792 unsigned ival;
1793 float val;
1794 };
1795 ival = fp_immediate_for_encoding(value, 0);
1796 return val;
1797 }