src/hotspot/cpu/aarch64/assembler_aarch64.hpp

*** 2734,11 ***
  
  // SVE floating-point arithmetic - unpredicated
  #define INSN(NAME, opcode)                                                             \
    void NAME(FloatRegister Zd, SIMD_RegVariant T, FloatRegister Zn, FloatRegister Zm) { \
      starti;                                                                            \
!     assert(T != B && T != Q, "invalid register variant");                              \
      f(0b01100101, 31, 24), f(T, 23, 22), f(0, 21),                                     \
      rf(Zm, 16), f(0, 15, 13), f(opcode, 12, 10), rf(Zn, 5), rf(Zd, 0);                 \
    }
  
    INSN(sve_fadd, 0b000);
--- 2734,11 ---
  
  // SVE floating-point arithmetic - unpredicated
  #define INSN(NAME, opcode)                                                             \
    void NAME(FloatRegister Zd, SIMD_RegVariant T, FloatRegister Zn, FloatRegister Zm) { \
      starti;                                                                            \
!     assert(T == S || T == D, "invalid register variant");                              \
      f(0b01100101, 31, 24), f(T, 23, 22), f(0, 21),                                     \
      rf(Zm, 16), f(0, 15, 13), f(opcode, 12, 10), rf(Zn, 5), rf(Zd, 0);                 \
    }
  
    INSN(sve_fadd, 0b000);

*** 2766,10 ***
--- 2766,11 ---
  
    INSN(sve_abs,  0b00000100, 0b010110101); // vector abs, unary
    INSN(sve_add,  0b00000100, 0b000000000); // vector add
    INSN(sve_andv, 0b00000100, 0b011010001); // bitwise and reduction to scalar
    INSN(sve_asr,  0b00000100, 0b010000100); // vector arithmetic shift right
+   INSN(sve_cnt,  0b00000100, 0b011010101)  // count non-zero bits
    INSN(sve_cpy,  0b00000101, 0b100000100); // copy scalar to each active vector element
    INSN(sve_eorv, 0b00000100, 0b011001001); // bitwise xor reduction to scalar
    INSN(sve_lsl,  0b00000100, 0b010011100); // vector logical shift left
    INSN(sve_lsr,  0b00000100, 0b010001100); // vector logical shift right
    INSN(sve_mul,  0b00000100, 0b010000000); // vector mul

*** 2785,11 ***
  #undef INSN
  
  // SVE floating-point arithmetics - predicate
  #define INSN(NAME, op1, op2)                                                                          \
    void NAME(FloatRegister Zd_or_Zdn_or_Vd, SIMD_RegVariant T, PRegister Pg, FloatRegister Zn_or_Zm) { \
!     assert(T != Q && T != B, "invalid register variant");                                             \
      sve_predicate_reg_insn(op1, op2, Zd_or_Zdn_or_Vd, T, Pg, Zn_or_Zm);                               \
    }
  
    INSN(sve_fabs,    0b00000100, 0b011100101);
    INSN(sve_fadd,    0b01100101, 0b000000100);
--- 2786,11 ---
  #undef INSN
  
  // SVE floating-point arithmetics - predicate
  #define INSN(NAME, op1, op2)                                                                          \
    void NAME(FloatRegister Zd_or_Zdn_or_Vd, SIMD_RegVariant T, PRegister Pg, FloatRegister Zn_or_Zm) { \
!     assert(T == S || T == D, "invalid register variant");                                             \
      sve_predicate_reg_insn(op1, op2, Zd_or_Zdn_or_Vd, T, Pg, Zn_or_Zm);                               \
    }
  
    INSN(sve_fabs,    0b00000100, 0b011100101);
    INSN(sve_fadd,    0b01100101, 0b000000100);

*** 2964,18 ***
  
    INSN(sve_inc, 0);
    INSN(sve_dec, 1);
  #undef INSN
  
-   // SVE Count non-zero bits - predicated
-   void sve_cnt(FloatRegister Zd, SIMD_RegVariant T, PRegister Pg, FloatRegister Zn) {
-     starti;
-     assert(T != Q, "invalid size");
-     f(0b00000100, 31, 24), f(T, 23, 22), f(0b011010101, 21, 13);
-     pgrf(Pg, 10), rf(Zn, 5), rf(Zd, 0);
-   }
- 
    // SVE predicate count
    void sve_cntp(Register Xd, SIMD_RegVariant T, PRegister Pg, PRegister Pn) {
      starti;
      assert(T != Q, "invalid size");
      f(0b00100101, 31, 24), f(T, 23, 22), f(0b10000010, 21, 14);
--- 2965,10 ---