diff a/src/hotspot/share/opto/chaitin.cpp b/src/hotspot/share/opto/chaitin.cpp
--- a/src/hotspot/share/opto/chaitin.cpp
+++ b/src/hotspot/share/opto/chaitin.cpp
@@ -644,19 +644,15 @@
         if (!lrg._fat_proj) {   // Must be aligned adjacent register set
           // Live ranges record the highest register in their mask.
           // We want the low register for the AD file writer's convenience.
           OptoReg::Name hi = lrg.reg(); // Get hi register
           int num_regs = lrg.num_regs();
-          if (lrg._is_scalable && OptoReg::is_stack(hi)) {
-            if (lrg._is_vector) {
-              assert(num_regs == RegMask::SlotsPerVecA, "scalable vector register");
-            }
-            // For scalable registers, when they are allocated in physical registers,
-            // num_regs is
-            //   RegMask::SlotsPerVecA for reg mask of scalable vector;
-            // If they are allocated in stack, we need to get the actual num_regs,
-            // which reflects the physical length of scalable registers.
+          if (lrg.is_scalable() && OptoReg::is_stack(hi)) {
+            // For scalable vector registers, when they are allocated in physical
+            // registers, num_regs is RegMask::SlotsPerVecA for reg mask of scalable
+            // vector. If they are allocated on stack, we need to get the actual
+            // num_regs, which reflects the physical length of scalable registers.
             num_regs = lrg.scalable_reg_slots();
           }
           OptoReg::Name lo = OptoReg::add(hi, (1-num_regs)); // Find lo
           // We have to use pair [lo,lo+1] even for wide vectors because
           // the rest of code generation works only with pairs. It is safe
@@ -1338,19 +1334,18 @@
 
 static OptoReg::Name find_first_set(LRG &lrg, RegMask mask, int chunk) {
   int num_regs = lrg.num_regs();
   OptoReg::Name assigned = mask.find_first_set(lrg, num_regs);
 
-  if (lrg._is_scalable) {
+  if (lrg.is_scalable()) {
     // a physical register is found
     if (chunk == 0 && OptoReg::is_reg(assigned)) {
       return assigned;
     }
 
     // find available stack slots for scalable register
     if (lrg._is_vector) {
-      assert(num_regs == RegMask::SlotsPerVecA, "scalable vector register");
       num_regs = lrg.scalable_reg_slots();
       // if actual scalable vector register is exactly SlotsPerVecA * 32 bits
       if (num_regs == RegMask::SlotsPerVecA) {
         return assigned;
       }
@@ -1586,11 +1581,11 @@
         }
         lrg->Clear();           // Clear the mask
         lrg->Insert(reg);       // Set regmask to match selected reg
         // For vectors and pairs, also insert the low bit of the pair
         // We always choose the high bit, then mask the low bits by register size
-        if (lrg->_is_scalable && OptoReg::is_stack(lrg->reg())) { // stack
+        if (lrg->is_scalable() && OptoReg::is_stack(lrg->reg())) { // stack
           n_regs = lrg->scalable_reg_slots();
         }
         for (int i = 1; i < n_regs; i++) {
           lrg->Insert(OptoReg::add(reg,-i));
         }