1 /* 2 * Copyright (c) 1997, 2020, Oracle and/or its affiliates. All rights reserved. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 * 5 * This code is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 only, as 7 * published by the Free Software Foundation. 8 * 9 * This code is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * version 2 for more details (a copy is included in the LICENSE file that 13 * accompanied this code). 14 * 15 * You should have received a copy of the GNU General Public License version 16 * 2 along with this work; if not, write to the Free Software Foundation, 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 20 * or visit www.oracle.com if you need additional information or have any 21 * questions. 22 * 23 */ 24 25 #ifndef SHARE_OPTO_CHAITIN_HPP 26 #define SHARE_OPTO_CHAITIN_HPP 27 28 #include "code/vmreg.hpp" 29 #include "memory/resourceArea.hpp" 30 #include "opto/connode.hpp" 31 #include "opto/live.hpp" 32 #include "opto/machnode.hpp" 33 #include "opto/matcher.hpp" 34 #include "opto/phase.hpp" 35 #include "opto/regalloc.hpp" 36 #include "opto/regmask.hpp" 37 38 class Matcher; 39 class PhaseCFG; 40 class PhaseLive; 41 class PhaseRegAlloc; 42 class PhaseChaitin; 43 44 #define OPTO_DEBUG_SPLIT_FREQ BLOCK_FREQUENCY(0.001) 45 #define OPTO_LRG_HIGH_FREQ BLOCK_FREQUENCY(0.25) 46 47 //------------------------------LRG-------------------------------------------- 48 // Live-RanGe structure. 49 class LRG : public ResourceObj { 50 friend class VMStructs; 51 public: 52 static const uint AllStack_size = 0xFFFFF; // This mask size is used to tell that the mask of this LRG supports stack positions 53 enum { SPILL_REG=29999 }; // Register number of a spilled LRG 54 55 double _cost; // 2 for loads/1 for stores times block freq 56 double _area; // Sum of all simultaneously live values 57 double score() const; // Compute score from cost and area 58 double _maxfreq; // Maximum frequency of any def or use 59 60 Node *_def; // Check for multi-def live ranges 61 #ifndef PRODUCT 62 GrowableArray<Node*>* _defs; 63 #endif 64 65 uint _risk_bias; // Index of LRG which we want to avoid color 66 uint _copy_bias; // Index of LRG which we want to share color 67 68 uint _next; // Index of next LRG in linked list 69 uint _prev; // Index of prev LRG in linked list 70 private: 71 uint _reg; // Chosen register; undefined if mask is plural 72 public: 73 // Return chosen register for this LRG. Error if the LRG is not bound to 74 // a single register. 75 OptoReg::Name reg() const { return OptoReg::Name(_reg); } 76 void set_reg( OptoReg::Name r ) { _reg = r; } 77 78 private: 79 uint _eff_degree; // Effective degree: Sum of neighbors _num_regs 80 public: 81 int degree() const { assert( _degree_valid , "" ); return _eff_degree; } 82 // Degree starts not valid and any change to the IFG neighbor 83 // set makes it not valid. 84 void set_degree( uint degree ) { 85 _eff_degree = degree; 86 debug_only(_degree_valid = 1;) 87 assert(!_mask.is_AllStack() || (_mask.is_AllStack() && lo_degree()), "_eff_degree can't be bigger than AllStack_size - _num_regs if the mask supports stack registers"); 88 } 89 // Made a change that hammered degree 90 void invalid_degree() { debug_only(_degree_valid=0;) } 91 // Incrementally modify degree. If it was correct, it should remain correct 92 void inc_degree( uint mod ) { 93 _eff_degree += mod; 94 assert(!_mask.is_AllStack() || (_mask.is_AllStack() && lo_degree()), "_eff_degree can't be bigger than AllStack_size - _num_regs if the mask supports stack registers"); 95 } 96 // Compute the degree between 2 live ranges 97 int compute_degree( LRG &l ) const; 98 bool mask_is_nonempty_and_up() const { 99 return mask().is_UP() && mask_size(); 100 } 101 bool is_float_or_vector() const { 102 return _is_float || _is_vector; 103 } 104 105 private: 106 RegMask _mask; // Allowed registers for this LRG 107 uint _mask_size; // cache of _mask.Size(); 108 public: 109 int compute_mask_size() const { return _mask.is_AllStack() ? AllStack_size : _mask.Size(); } 110 void set_mask_size( int size ) { 111 assert((size == (int)AllStack_size) || (size == (int)_mask.Size()), ""); 112 _mask_size = size; 113 #ifdef ASSERT 114 _msize_valid=1; 115 if (_is_vector) { 116 assert(!_fat_proj, "sanity"); 117 if (!(_is_scalable && OptoReg::is_stack(_reg))) { 118 assert(_mask.is_aligned_sets(_num_regs), "mask is not aligned, adjacent sets"); 119 } 120 } else if (_num_regs == 2 && !_fat_proj) { 121 assert(_mask.is_aligned_pairs(), "mask is not aligned, adjacent pairs"); 122 } 123 #endif 124 } 125 void compute_set_mask_size() { set_mask_size(compute_mask_size()); } 126 int mask_size() const { assert( _msize_valid, "mask size not valid" ); 127 return _mask_size; } 128 // Get the last mask size computed, even if it does not match the 129 // count of bits in the current mask. 130 int get_invalid_mask_size() const { return _mask_size; } 131 const RegMask &mask() const { return _mask; } 132 void set_mask( const RegMask &rm ) { _mask = rm; debug_only(_msize_valid=0;)} 133 void AND( const RegMask &rm ) { _mask.AND(rm); debug_only(_msize_valid=0;)} 134 void SUBTRACT( const RegMask &rm ) { _mask.SUBTRACT(rm); debug_only(_msize_valid=0;)} 135 void Clear() { _mask.Clear() ; debug_only(_msize_valid=1); _mask_size = 0; } 136 void Set_All() { _mask.Set_All(); debug_only(_msize_valid=1); _mask_size = RegMask::CHUNK_SIZE; } 137 138 void Insert( OptoReg::Name reg ) { _mask.Insert(reg); debug_only(_msize_valid=0;) } 139 void Remove( OptoReg::Name reg ) { _mask.Remove(reg); debug_only(_msize_valid=0;) } 140 void clear_to_sets() { _mask.clear_to_sets(_num_regs); debug_only(_msize_valid=0;) } 141 142 private: 143 // Number of registers this live range uses when it colors 144 uint16_t _num_regs; // 2 for Longs and Doubles, 1 for all else 145 // except _num_regs is kill count for fat_proj 146 147 // For scalable register, num_regs may not be the actual physical register size. 148 // We need to get the actual physical length of scalable register when scalable 149 // register is spilled. The size of one slot is 32-bit. 150 uint _scalable_reg_slots; // Actual scalable register length of slots. 151 // Meaningful only when _is_scalable is true. 152 public: 153 int num_regs() const { return _num_regs; } 154 void set_num_regs( int reg ) { assert( _num_regs == reg || !_num_regs, "" ); _num_regs = reg; } 155 156 uint scalable_reg_slots() { return _scalable_reg_slots; } 157 void set_scalable_reg_slots(uint slots) { 158 assert(_is_scalable, "scalable register"); 159 assert(slots > 0, "slots of scalable register is not valid"); 160 _scalable_reg_slots = slots; 161 } 162 163 private: 164 // Number of physical registers this live range uses when it colors 165 // Architecture and register-set dependent 166 uint16_t _reg_pressure; 167 public: 168 void set_reg_pressure(int i) { _reg_pressure = i; } 169 int reg_pressure() const { return _reg_pressure; } 170 171 // How much 'wiggle room' does this live range have? 172 // How many color choices can it make (scaled by _num_regs)? 173 int degrees_of_freedom() const { return mask_size() - _num_regs; } 174 // Bound LRGs have ZERO degrees of freedom. We also count 175 // must_spill as bound. 176 bool is_bound () const { return _is_bound; } 177 // Negative degrees-of-freedom; even with no neighbors this 178 // live range must spill. 179 bool not_free() const { return degrees_of_freedom() < 0; } 180 // Is this live range of "low-degree"? Trivially colorable? 181 bool lo_degree () const { return degree() <= degrees_of_freedom(); } 182 // Is this live range just barely "low-degree"? Trivially colorable? 183 bool just_lo_degree () const { return degree() == degrees_of_freedom(); } 184 185 uint _is_oop:1, // Live-range holds an oop 186 _is_float:1, // True if in float registers 187 _is_vector:1, // True if in vector registers 188 _is_scalable:1, // True if register size is scalable 189 _was_spilled1:1, // True if prior spilling on def 190 _was_spilled2:1, // True if twice prior spilling on def 191 _is_bound:1, // live range starts life with no 192 // degrees of freedom. 193 _direct_conflict:1, // True if def and use registers in conflict 194 _must_spill:1, // live range has lost all degrees of freedom 195 // If _fat_proj is set, live range does NOT require aligned, adjacent 196 // registers and has NO interferences. 197 // If _fat_proj is clear, live range requires num_regs() to be a power of 198 // 2, and it requires registers to form an aligned, adjacent set. 199 _fat_proj:1, // 200 _was_lo:1, // Was lo-degree prior to coalesce 201 _msize_valid:1, // _mask_size cache valid 202 _degree_valid:1, // _degree cache valid 203 _has_copy:1, // Adjacent to some copy instruction 204 _at_risk:1; // Simplify says this guy is at risk to spill 205 206 207 // Alive if non-zero, dead if zero 208 bool alive() const { return _def != NULL; } 209 bool is_multidef() const { return _def == NodeSentinel; } 210 bool is_singledef() const { return _def != NodeSentinel; } 211 212 #ifndef PRODUCT 213 void dump( ) const; 214 #endif 215 }; 216 217 //------------------------------IFG-------------------------------------------- 218 // InterFerence Graph 219 // An undirected graph implementation. Created with a fixed number of 220 // vertices. Edges can be added & tested. Vertices can be removed, then 221 // added back later with all edges intact. Can add edges between one vertex 222 // and a list of other vertices. Can union vertices (and their edges) 223 // together. The IFG needs to be really really fast, and also fairly 224 // abstract! It needs abstraction so I can fiddle with the implementation to 225 // get even more speed. 226 class PhaseIFG : public Phase { 227 friend class VMStructs; 228 // Current implementation: a triangular adjacency list. 229 230 // Array of adjacency-lists, indexed by live-range number 231 IndexSet *_adjs; 232 233 // Assertion bit for proper use of Squaring 234 bool _is_square; 235 236 // Live range structure goes here 237 LRG *_lrgs; // Array of LRG structures 238 239 public: 240 // Largest live-range number 241 uint _maxlrg; 242 243 Arena *_arena; 244 245 // Keep track of inserted and deleted Nodes 246 VectorSet *_yanked; 247 248 PhaseIFG( Arena *arena ); 249 void init( uint maxlrg ); 250 251 // Add edge between a and b. Returns true if actually addded. 252 int add_edge( uint a, uint b ); 253 254 // Test for edge existance 255 int test_edge( uint a, uint b ) const; 256 257 // Square-up matrix for faster Union 258 void SquareUp(); 259 260 // Return number of LRG neighbors 261 uint neighbor_cnt( uint a ) const { return _adjs[a].count(); } 262 // Union edges of b into a on Squared-up matrix 263 void Union( uint a, uint b ); 264 // Test for edge in Squared-up matrix 265 int test_edge_sq( uint a, uint b ) const; 266 // Yank a Node and all connected edges from the IFG. Be prepared to 267 // re-insert the yanked Node in reverse order of yanking. Return a 268 // list of neighbors (edges) yanked. 269 IndexSet *remove_node( uint a ); 270 // Reinsert a yanked Node 271 void re_insert( uint a ); 272 // Return set of neighbors 273 IndexSet *neighbors( uint a ) const { return &_adjs[a]; } 274 275 #ifndef PRODUCT 276 // Dump the IFG 277 void dump() const; 278 void stats() const; 279 void verify( const PhaseChaitin * ) const; 280 #endif 281 282 //--------------- Live Range Accessors 283 LRG &lrgs(uint idx) const { assert(idx < _maxlrg, "oob"); return _lrgs[idx]; } 284 285 // Compute and set effective degree. Might be folded into SquareUp(). 286 void Compute_Effective_Degree(); 287 288 // Compute effective degree as the sum of neighbors' _sizes. 289 int effective_degree( uint lidx ) const; 290 }; 291 292 // The LiveRangeMap class is responsible for storing node to live range id mapping. 293 // Each node is mapped to a live range id (a virtual register). Nodes that are 294 // not considered for register allocation are given live range id 0. 295 class LiveRangeMap { 296 297 private: 298 299 uint _max_lrg_id; 300 301 // Union-find map. Declared as a short for speed. 302 // Indexed by live-range number, it returns the compacted live-range number 303 LRG_List _uf_map; 304 305 // Map from Nodes to live ranges 306 LRG_List _names; 307 308 // Straight out of Tarjan's union-find algorithm 309 uint find_compress(const Node *node) { 310 uint lrg_id = find_compress(_names.at(node->_idx)); 311 _names.at_put(node->_idx, lrg_id); 312 return lrg_id; 313 } 314 315 uint find_compress(uint lrg); 316 317 public: 318 319 const LRG_List& names() { 320 return _names; 321 } 322 323 uint max_lrg_id() const { 324 return _max_lrg_id; 325 } 326 327 void set_max_lrg_id(uint max_lrg_id) { 328 _max_lrg_id = max_lrg_id; 329 } 330 331 uint size() const { 332 return _names.length(); 333 } 334 335 uint live_range_id(uint idx) const { 336 return _names.at(idx); 337 } 338 339 uint live_range_id(const Node *node) const { 340 return _names.at(node->_idx); 341 } 342 343 uint uf_live_range_id(uint lrg_id) const { 344 return _uf_map.at(lrg_id); 345 } 346 347 void map(uint idx, uint lrg_id) { 348 _names.at_put(idx, lrg_id); 349 } 350 351 void uf_map(uint dst_lrg_id, uint src_lrg_id) { 352 _uf_map.at_put(dst_lrg_id, src_lrg_id); 353 } 354 355 void extend(uint idx, uint lrg_id) { 356 _names.at_put_grow(idx, lrg_id); 357 } 358 359 void uf_extend(uint dst_lrg_id, uint src_lrg_id) { 360 _uf_map.at_put_grow(dst_lrg_id, src_lrg_id); 361 } 362 363 LiveRangeMap(Arena* arena, uint unique) 364 : _max_lrg_id(0) 365 , _uf_map(arena, unique, unique, 0) 366 , _names(arena, unique, unique, 0) {} 367 368 uint find_id( const Node *n ) { 369 uint retval = live_range_id(n); 370 assert(retval == find(n),"Invalid node to lidx mapping"); 371 return retval; 372 } 373 374 // Reset the Union-Find map to identity 375 void reset_uf_map(uint max_lrg_id); 376 377 // Make all Nodes map directly to their final live range; no need for 378 // the Union-Find mapping after this call. 379 void compress_uf_map_for_nodes(); 380 381 uint find(uint lidx) { 382 uint uf_lidx = _uf_map.at(lidx); 383 return (uf_lidx == lidx) ? uf_lidx : find_compress(lidx); 384 } 385 386 // Convert a Node into a Live Range Index - a lidx 387 uint find(const Node *node) { 388 uint lidx = live_range_id(node); 389 uint uf_lidx = _uf_map.at(lidx); 390 return (uf_lidx == lidx) ? uf_lidx : find_compress(node); 391 } 392 393 // Like Find above, but no path compress, so bad asymptotic behavior 394 uint find_const(uint lrg) const; 395 396 // Like Find above, but no path compress, so bad asymptotic behavior 397 uint find_const(const Node *node) const { 398 if(node->_idx >= (uint)_names.length()) { 399 return 0; // not mapped, usual for debug dump 400 } 401 return find_const(_names.at(node->_idx)); 402 } 403 }; 404 405 //------------------------------Chaitin---------------------------------------- 406 // Briggs-Chaitin style allocation, mostly. 407 class PhaseChaitin : public PhaseRegAlloc { 408 friend class VMStructs; 409 410 int _trip_cnt; 411 int _alternate; 412 413 PhaseLive *_live; // Liveness, used in the interference graph 414 PhaseIFG *_ifg; // Interference graph (for original chunk) 415 VectorSet _spilled_once; // Nodes that have been spilled 416 VectorSet _spilled_twice; // Nodes that have been spilled twice 417 418 // Combine the Live Range Indices for these 2 Nodes into a single live 419 // range. Future requests for any Node in either live range will 420 // return the live range index for the combined live range. 421 void Union( const Node *src, const Node *dst ); 422 423 void new_lrg( const Node *x, uint lrg ); 424 425 // Compact live ranges, removing unused ones. Return new maxlrg. 426 void compact(); 427 428 uint _lo_degree; // Head of lo-degree LRGs list 429 uint _lo_stk_degree; // Head of lo-stk-degree LRGs list 430 uint _hi_degree; // Head of hi-degree LRGs list 431 uint _simplified; // Linked list head of simplified LRGs 432 433 // Helper functions for Split() 434 uint split_DEF(Node *def, Block *b, int loc, uint max, Node **Reachblock, Node **debug_defs, GrowableArray<uint> splits, int slidx ); 435 uint split_USE(MachSpillCopyNode::SpillType spill_type, Node *def, Block *b, Node *use, uint useidx, uint max, bool def_down, bool cisc_sp, GrowableArray<uint> splits, int slidx ); 436 437 //------------------------------clone_projs------------------------------------ 438 // After cloning some rematerialized instruction, clone any MachProj's that 439 // follow it. Example: Intel zero is XOR, kills flags. Sparc FP constants 440 // use G3 as an address temp. 441 int clone_projs(Block* b, uint idx, Node* orig, Node* copy, uint& max_lrg_id); 442 443 int clone_projs(Block* b, uint idx, Node* orig, Node* copy, LiveRangeMap& lrg_map) { 444 uint max_lrg_id = lrg_map.max_lrg_id(); 445 int found_projs = clone_projs(b, idx, orig, copy, max_lrg_id); 446 if (found_projs > 0) { 447 // max_lrg_id is updated during call above 448 lrg_map.set_max_lrg_id(max_lrg_id); 449 } 450 return found_projs; 451 } 452 453 Node *split_Rematerialize(Node *def, Block *b, uint insidx, uint &maxlrg, GrowableArray<uint> splits, 454 int slidx, uint *lrg2reach, Node **Reachblock, bool walkThru); 455 // True if lidx is used before any real register is def'd in the block 456 bool prompt_use( Block *b, uint lidx ); 457 Node *get_spillcopy_wide(MachSpillCopyNode::SpillType spill_type, Node *def, Node *use, uint uidx ); 458 // Insert the spill at chosen location. Skip over any intervening Proj's or 459 // Phis. Skip over a CatchNode and projs, inserting in the fall-through block 460 // instead. Update high-pressure indices. Create a new live range. 461 void insert_proj( Block *b, uint i, Node *spill, uint maxlrg ); 462 463 bool is_high_pressure( Block *b, LRG *lrg, uint insidx ); 464 465 uint _oldphi; // Node index which separates pre-allocation nodes 466 467 Block **_blks; // Array of blocks sorted by frequency for coalescing 468 469 float _high_frequency_lrg; // Frequency at which LRG will be spilled for debug info 470 471 #ifndef PRODUCT 472 bool _trace_spilling; 473 #endif 474 475 public: 476 PhaseChaitin(uint unique, PhaseCFG &cfg, Matcher &matcher, bool track_liveout_pressure); 477 ~PhaseChaitin() {} 478 479 LiveRangeMap _lrg_map; 480 481 LRG &lrgs(uint idx) const { return _ifg->lrgs(idx); } 482 483 // Do all the real work of allocate 484 void Register_Allocate(); 485 486 float high_frequency_lrg() const { return _high_frequency_lrg; } 487 488 // Used when scheduling info generated, not in general register allocation 489 bool _scheduling_info_generated; 490 491 void set_ifg(PhaseIFG &ifg) { _ifg = &ifg; } 492 void set_live(PhaseLive &live) { _live = &live; } 493 PhaseLive* get_live() { return _live; } 494 495 // Populate the live range maps with ssa info for scheduling 496 void mark_ssa(); 497 498 #ifndef PRODUCT 499 bool trace_spilling() const { return _trace_spilling; } 500 #endif 501 502 private: 503 // De-SSA the world. Assign registers to Nodes. Use the same register for 504 // all inputs to a PhiNode, effectively coalescing live ranges. Insert 505 // copies as needed. 506 void de_ssa(); 507 508 // Add edge between reg and everything in the vector. 509 // Use the RegMask information to trim the set of interferences. Return the 510 // count of edges added. 511 void interfere_with_live(uint lid, IndexSet* liveout); 512 #ifdef ASSERT 513 // Count register pressure for asserts 514 uint count_int_pressure(IndexSet* liveout); 515 uint count_float_pressure(IndexSet* liveout); 516 #endif 517 518 // Build the interference graph using virtual registers only. 519 // Used for aggressive coalescing. 520 void build_ifg_virtual( ); 521 522 // used when computing the register pressure for each block in the CFG. This 523 // is done during IFG creation. 524 class Pressure { 525 // keeps track of the register pressure at the current 526 // instruction (used when stepping backwards in the block) 527 uint _current_pressure; 528 529 // keeps track of the instruction index of the first low to high register pressure 530 // transition (starting from the top) in the block 531 // if high_pressure_index == 0 then the whole block is high pressure 532 // if high_pressure_index = b.end_idx() + 1 then the whole block is low pressure 533 uint _high_pressure_index; 534 535 // stores the highest pressure we find 536 uint _final_pressure; 537 538 // number of live ranges that constitute high register pressure 539 uint _high_pressure_limit; 540 541 // initial pressure observed 542 uint _start_pressure; 543 544 public: 545 546 // lower the register pressure and look for a low to high pressure 547 // transition 548 void lower(LRG& lrg, uint& location) { 549 _current_pressure -= lrg.reg_pressure(); 550 if (_current_pressure == _high_pressure_limit) { 551 _high_pressure_index = location; 552 } 553 } 554 555 // raise the pressure and store the pressure if it's the biggest 556 // pressure so far 557 void raise(LRG &lrg) { 558 _current_pressure += lrg.reg_pressure(); 559 if (_current_pressure > _final_pressure) { 560 _final_pressure = _current_pressure; 561 } 562 } 563 564 void init(int limit) { 565 _current_pressure = 0; 566 _high_pressure_index = 0; 567 _final_pressure = 0; 568 _high_pressure_limit = limit; 569 _start_pressure = 0; 570 } 571 572 uint high_pressure_index() const { 573 return _high_pressure_index; 574 } 575 576 uint final_pressure() const { 577 return _final_pressure; 578 } 579 580 uint start_pressure() const { 581 return _start_pressure; 582 } 583 584 uint current_pressure() const { 585 return _current_pressure; 586 } 587 588 uint high_pressure_limit() const { 589 return _high_pressure_limit; 590 } 591 592 void lower_high_pressure_index() { 593 _high_pressure_index--; 594 } 595 596 void set_high_pressure_index_to_block_start() { 597 _high_pressure_index = 0; 598 } 599 600 void set_start_pressure(int value) { 601 _start_pressure = value; 602 _final_pressure = value; 603 } 604 605 void set_current_pressure(int value) { 606 _current_pressure = value; 607 } 608 609 void check_pressure_at_fatproj(uint fatproj_location, RegMask& fatproj_mask) { 610 // this pressure is only valid at this instruction, i.e. we don't need to lower 611 // the register pressure since the fat proj was never live before (going backwards) 612 uint new_pressure = current_pressure() + fatproj_mask.Size(); 613 if (new_pressure > final_pressure()) { 614 _final_pressure = new_pressure; 615 } 616 617 // if we were at a low pressure and now and the fat proj is at high pressure, record the fat proj location 618 // as coming from a low to high (to low again) 619 if (current_pressure() <= high_pressure_limit() && new_pressure > high_pressure_limit()) { 620 _high_pressure_index = fatproj_location; 621 } 622 } 623 624 Pressure(uint high_pressure_index, uint high_pressure_limit) 625 : _current_pressure(0) 626 , _high_pressure_index(high_pressure_index) 627 , _final_pressure(0) 628 , _high_pressure_limit(high_pressure_limit) 629 , _start_pressure(0) {} 630 }; 631 632 void check_for_high_pressure_transition_at_fatproj(uint& block_reg_pressure, uint location, LRG& lrg, Pressure& pressure, const int op_regtype); 633 void add_input_to_liveout(Block* b, Node* n, IndexSet* liveout, double cost, Pressure& int_pressure, Pressure& float_pressure); 634 void compute_initial_block_pressure(Block* b, IndexSet* liveout, Pressure& int_pressure, Pressure& float_pressure, double cost); 635 bool remove_node_if_not_used(Block* b, uint location, Node* n, uint lid, IndexSet* liveout); 636 void assign_high_score_to_immediate_copies(Block* b, Node* n, LRG& lrg, uint next_inst, uint last_inst); 637 void remove_interference_from_copy(Block* b, uint location, uint lid_copy, IndexSet* liveout, double cost, Pressure& int_pressure, Pressure& float_pressure); 638 void remove_bound_register_from_interfering_live_ranges(LRG& lrg, IndexSet* liveout, uint& must_spill); 639 void check_for_high_pressure_block(Pressure& pressure); 640 void adjust_high_pressure_index(Block* b, uint& hrp_index, Pressure& pressure); 641 642 // Build the interference graph using physical registers when available. 643 // That is, if 2 live ranges are simultaneously alive but in their 644 // acceptable register sets do not overlap, then they do not interfere. 645 uint build_ifg_physical( ResourceArea *a ); 646 647 public: 648 // Gather LiveRanGe information, including register masks and base pointer/ 649 // derived pointer relationships. 650 void gather_lrg_masks( bool mod_cisc_masks ); 651 652 // user visible pressure variables for scheduling 653 Pressure _sched_int_pressure; 654 Pressure _sched_float_pressure; 655 Pressure _scratch_int_pressure; 656 Pressure _scratch_float_pressure; 657 658 // Pressure functions for user context 659 void lower_pressure(Block* b, uint location, LRG& lrg, IndexSet* liveout, Pressure& int_pressure, Pressure& float_pressure); 660 void raise_pressure(Block* b, LRG& lrg, Pressure& int_pressure, Pressure& float_pressure); 661 void compute_entry_block_pressure(Block* b); 662 void compute_exit_block_pressure(Block* b); 663 void print_pressure_info(Pressure& pressure, const char *str); 664 665 private: 666 // Force the bases of derived pointers to be alive at GC points. 667 bool stretch_base_pointer_live_ranges( ResourceArea *a ); 668 // Helper to stretch above; recursively discover the base Node for 669 // a given derived Node. Easy for AddP-related machine nodes, but 670 // needs to be recursive for derived Phis. 671 Node *find_base_for_derived( Node **derived_base_map, Node *derived, uint &maxlrg ); 672 673 // Set the was-lo-degree bit. Conservative coalescing should not change the 674 // colorability of the graph. If any live range was of low-degree before 675 // coalescing, it should Simplify. This call sets the was-lo-degree bit. 676 void set_was_low(); 677 678 // Init LRG caching of degree, numregs. Init lo_degree list. 679 void cache_lrg_info( ); 680 681 // Simplify the IFG by removing LRGs of low degree 682 void Simplify(); 683 684 // Select colors by re-inserting edges into the IFG. 685 // Return TRUE if any spills occurred. 686 uint Select( ); 687 // Helper function for select which allows biased coloring 688 OptoReg::Name choose_color( LRG &lrg, int chunk ); 689 // Helper function which implements biasing heuristic 690 OptoReg::Name bias_color( LRG &lrg, int chunk ); 691 692 // Split uncolorable live ranges 693 // Return new number of live ranges 694 uint Split(uint maxlrg, ResourceArea* split_arena); 695 696 // Set the 'spilled_once' or 'spilled_twice' flag on a node. 697 void set_was_spilled( Node *n ); 698 699 // Convert ideal spill-nodes into machine loads & stores 700 // Set C->failing when fixup spills could not complete, node limit exceeded. 701 void fixup_spills(); 702 703 // Post-Allocation peephole copy removal 704 void post_allocate_copy_removal(); 705 Node *skip_copies( Node *c ); 706 // Replace the old node with the current live version of that value 707 // and yank the old value if it's dead. 708 int replace_and_yank_if_dead( Node *old, OptoReg::Name nreg, 709 Block *current_block, Node_List& value, Node_List& regnd ) { 710 Node* v = regnd[nreg]; 711 assert(v->outcnt() != 0, "no dead values"); 712 old->replace_by(v); 713 return yank_if_dead(old, current_block, &value, ®nd); 714 } 715 716 int yank_if_dead( Node *old, Block *current_block, Node_List *value, Node_List *regnd ) { 717 return yank_if_dead_recurse(old, old, current_block, value, regnd); 718 } 719 int yank_if_dead_recurse(Node *old, Node *orig_old, Block *current_block, 720 Node_List *value, Node_List *regnd); 721 int yank( Node *old, Block *current_block, Node_List *value, Node_List *regnd ); 722 int elide_copy( Node *n, int k, Block *current_block, Node_List &value, Node_List ®nd, bool can_change_regs ); 723 int use_prior_register( Node *copy, uint idx, Node *def, Block *current_block, Node_List &value, Node_List ®nd ); 724 bool may_be_copy_of_callee( Node *def ) const; 725 726 // If nreg already contains the same constant as val then eliminate it 727 bool eliminate_copy_of_constant(Node* val, Node* n, 728 Block *current_block, Node_List& value, Node_List ®nd, 729 OptoReg::Name nreg, OptoReg::Name nreg2); 730 // Extend the node to LRG mapping 731 void add_reference( const Node *node, const Node *old_node); 732 733 // Record the first use of a def in the block for a register. 734 class RegDefUse { 735 Node* _def; 736 Node* _first_use; 737 public: 738 RegDefUse() : _def(NULL), _first_use(NULL) { } 739 Node* def() const { return _def; } 740 Node* first_use() const { return _first_use; } 741 742 void update(Node* def, Node* use) { 743 if (_def != def) { 744 _def = def; 745 _first_use = use; 746 } 747 } 748 void clear() { 749 _def = NULL; 750 _first_use = NULL; 751 } 752 }; 753 typedef GrowableArray<RegDefUse> RegToDefUseMap; 754 int possibly_merge_multidef(Node *n, uint k, Block *block, RegToDefUseMap& reg2defuse); 755 756 // Merge nodes that are a part of a multidef lrg and produce the same value within a block. 757 void merge_multidefs(); 758 759 private: 760 761 static int _final_loads, _final_stores, _final_copies, _final_memoves; 762 static double _final_load_cost, _final_store_cost, _final_copy_cost, _final_memove_cost; 763 static int _conserv_coalesce, _conserv_coalesce_pair; 764 static int _conserv_coalesce_trie, _conserv_coalesce_quad; 765 static int _post_alloc; 766 static int _lost_opp_pp_coalesce, _lost_opp_cflow_coalesce; 767 static int _used_cisc_instructions, _unused_cisc_instructions; 768 static int _allocator_attempts, _allocator_successes; 769 770 #ifdef ASSERT 771 // Verify that base pointers and derived pointers are still sane 772 void verify_base_ptrs(ResourceArea* a) const; 773 void verify(ResourceArea* a, bool verify_ifg = false) const; 774 #endif // ASSERT 775 776 #ifndef PRODUCT 777 static uint _high_pressure, _low_pressure; 778 779 void dump() const; 780 void dump(const Node* n) const; 781 void dump(const Block* b) const; 782 void dump_degree_lists() const; 783 void dump_simplified() const; 784 void dump_lrg(uint lidx, bool defs_only) const; 785 void dump_lrg(uint lidx) const { 786 // dump defs and uses by default 787 dump_lrg(lidx, false); 788 } 789 void dump_bb(uint pre_order) const; 790 void dump_for_spill_split_recycle() const; 791 792 public: 793 void dump_frame() const; 794 char *dump_register(const Node* n, char* buf) const; 795 private: 796 static void print_chaitin_statistics(); 797 #endif // not PRODUCT 798 friend class PhaseCoalesce; 799 friend class PhaseAggressiveCoalesce; 800 friend class PhaseConservativeCoalesce; 801 }; 802 803 #endif // SHARE_OPTO_CHAITIN_HPP