diff a/src/hotspot/share/opto/regmask.cpp b/src/hotspot/share/opto/regmask.cpp
--- a/src/hotspot/share/opto/regmask.cpp
+++ b/src/hotspot/share/opto/regmask.cpp
@@ -93,17 +93,13 @@
 
   // assigned is OptoReg which is selected by register allocator
   OptoReg::Name assigned = lrg.reg();
   assert(OptoReg::is_valid(assigned), "should be valid opto register");
 
-  if (lrg._is_scalable && OptoReg::is_stack(assigned)) {
-    if (lrg._is_vector) {
-      assert(ireg == Op_VecA, "scalable vector register");
-    }
+  if (lrg.is_scalable() && OptoReg::is_stack(assigned)) {
     n_regs = lrg.scalable_reg_slots();
   }
-
   return n_regs;
 }
 
 // Clear out partial bits; leave only bit pairs
 void RegMask::clear_to_pairs() {
@@ -195,11 +191,11 @@
 
 // Find the lowest-numbered register set in the mask.  Return the
 // HIGHEST register number in the set, or BAD if no sets.
 // Works also for size 1.
 OptoReg::Name RegMask::find_first_set(LRG &lrg, const int size) const {
-  if (lrg._is_scalable && lrg._is_vector) {
+  if (lrg.is_scalable()) {
     // For scalable vector register, regmask is SlotsPerVecA bits aligned.
     assert(is_aligned_sets(SlotsPerVecA), "mask is not aligned, adjacent sets");
   } else {
     assert(is_aligned_sets(size), "mask is not aligned, adjacent sets");
   }