1 /*
2 * Copyright (c) 1997, 2020, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
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11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
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23 */
24
25 #ifndef SHARE_OPTO_REGMASK_HPP
26 #define SHARE_OPTO_REGMASK_HPP
27
28 #include "code/vmreg.hpp"
29 #include "opto/optoreg.hpp"
30 #include "utilities/count_leading_zeros.hpp"
31 #include "utilities/count_trailing_zeros.hpp"
32
33 class LRG;
34
35 //-------------Non-zero bit search methods used by RegMask---------------------
36 // Find lowest 1, undefined if empty/0
37 static int find_lowest_bit(uint32_t mask) {
38 return count_trailing_zeros(mask);
39 }
40 // Find highest 1, undefined if empty/0
41 static int find_highest_bit(uint32_t mask) {
42 return count_leading_zeros(mask) ^ 31;
43 }
44
45 //------------------------------RegMask----------------------------------------
46 // The ADL file describes how to print the machine-specific registers, as well
47 // as any notion of register classes. We provide a register mask, which is
48 // just a collection of Register numbers.
49
50 // The ADLC defines 2 macros, RM_SIZE and FORALL_BODY.
51 // RM_SIZE is the size of a register mask in words.
52 // FORALL_BODY replicates a BODY macro once per word in the register mask.
53 // The usage is somewhat clumsy and limited to the regmask.[h,c]pp files.
54 // However, it means the ADLC can redefine the unroll macro and all loops
55 // over register masks will be unrolled by the correct amount.
56
57 class RegMask {
58 union {
59 double _dummy_force_double_alignment[RM_SIZE>>1];
60 // Array of Register Mask bits. This array is large enough to cover
61 // all the machine registers and all parameters that need to be passed
62 // on the stack (stack registers) up to some interesting limit. Methods
63 // that need more parameters will NOT be compiled. On Intel, the limit
64 // is something like 90+ parameters.
65 int _A[RM_SIZE];
66 };
67 // The low and high water marks represents the lowest and highest word
68 // that might contain set register mask bits, respectively. We guarantee
69 // that there are no bits in words outside this range, but any word at
70 // and between the two marks can still be 0.
71 int _lwm;
72 int _hwm;
73
74 enum {
75 _WordBits = BitsPerInt,
76 _LogWordBits = LogBitsPerInt,
77 _RM_SIZE = RM_SIZE // local constant, imported, then hidden by #undef
78 };
79
80 public:
81 enum { CHUNK_SIZE = RM_SIZE*_WordBits };
82
83 // SlotsPerLong is 2, since slots are 32 bits and longs are 64 bits.
84 // Also, consider the maximum alignment size for a normally allocated
85 // value. Since we allocate register pairs but not register quads (at
86 // present), this alignment is SlotsPerLong (== 2). A normally
87 // aligned allocated register is either a single register, or a pair
88 // of adjacent registers, the lower-numbered being even.
89 // See also is_aligned_Pairs() below, and the padding added before
90 // Matcher::_new_SP to keep allocated pairs aligned properly.
91 // If we ever go to quad-word allocations, SlotsPerQuad will become
92 // the controlling alignment constraint. Note that this alignment
93 // requirement is internal to the allocator, and independent of any
94 // particular platform.
95 enum { SlotsPerLong = 2,
96 SlotsPerVecA = 8,
97 SlotsPerVecS = 1,
98 SlotsPerVecD = 2,
99 SlotsPerVecX = 4,
100 SlotsPerVecY = 8,
101 SlotsPerVecZ = 16,
102 SlotsPerRegVmask = 1,
103 };
104
105 // A constructor only used by the ADLC output. All mask fields are filled
106 // in directly. Calls to this look something like RM(1,2,3,4);
107 RegMask(
108 # define BODY(I) int a##I,
109 FORALL_BODY
110 # undef BODY
111 int dummy = 0) {
112 # define BODY(I) _A[I] = a##I;
113 FORALL_BODY
114 # undef BODY
115 _lwm = 0;
116 _hwm = RM_SIZE - 1;
117 while (_hwm > 0 && _A[_hwm] == 0) _hwm--;
118 while ((_lwm < _hwm) && _A[_lwm] == 0) _lwm++;
119 assert(valid_watermarks(), "post-condition");
120 }
121
122 // Handy copying constructor
123 RegMask(RegMask *rm) {
124 _hwm = rm->_hwm;
125 _lwm = rm->_lwm;
126 for (int i = 0; i < RM_SIZE; i++) {
127 _A[i] = rm->_A[i];
128 }
129 assert(valid_watermarks(), "post-condition");
130 }
131
132 // Construct an empty mask
133 RegMask() {
134 Clear();
135 }
136
137 // Construct a mask with a single bit
138 RegMask(OptoReg::Name reg) {
139 Clear();
140 Insert(reg);
141 }
142
143 // Check for register being in mask
144 int Member(OptoReg::Name reg) const {
145 assert(reg < CHUNK_SIZE, "");
146 return _A[reg>>_LogWordBits] & (1<<(reg&(_WordBits-1)));
147 }
148
149 // The last bit in the register mask indicates that the mask should repeat
150 // indefinitely with ONE bits. Returns TRUE if mask is infinite or
151 // unbounded in size. Returns FALSE if mask is finite size.
152 int is_AllStack() const { return _A[RM_SIZE-1] >> (_WordBits-1); }
153
154 // Work around an -xO3 optimization problme in WS6U1. The old way:
155 // void set_AllStack() { _A[RM_SIZE-1] |= (1<<(_WordBits-1)); }
156 // will cause _A[RM_SIZE-1] to be clobbered, not updated when set_AllStack()
157 // follows an Insert() loop, like the one found in init_spill_mask(). Using
158 // Insert() instead works because the index into _A in computed instead of
159 // constant. See bug 4665841.
160 void set_AllStack() { Insert(OptoReg::Name(CHUNK_SIZE-1)); }
161
162 // Test for being a not-empty mask.
163 int is_NotEmpty() const {
164 assert(valid_watermarks(), "sanity");
165 int tmp = 0;
166 for (int i = _lwm; i <= _hwm; i++) {
167 tmp |= _A[i];
168 }
169 return tmp;
170 }
171
172 // Find lowest-numbered register from mask, or BAD if mask is empty.
173 OptoReg::Name find_first_elem() const {
174 assert(valid_watermarks(), "sanity");
175 for (int i = _lwm; i <= _hwm; i++) {
176 int bits = _A[i];
177 if (bits) {
178 return OptoReg::Name((i<<_LogWordBits) + find_lowest_bit(bits));
179 }
180 }
181 return OptoReg::Name(OptoReg::Bad);
182 }
183
184 // Get highest-numbered register from mask, or BAD if mask is empty.
185 OptoReg::Name find_last_elem() const {
186 assert(valid_watermarks(), "sanity");
187 for (int i = _hwm; i >= _lwm; i--) {
188 int bits = _A[i];
189 if (bits) {
190 return OptoReg::Name((i<<_LogWordBits) + find_highest_bit(bits));
191 }
192 }
193 return OptoReg::Name(OptoReg::Bad);
194 }
195
196 // Clear out partial bits; leave only aligned adjacent bit pairs.
197 void clear_to_pairs();
198
199 #ifdef ASSERT
200 // Verify watermarks are sane, i.e., within bounds and that no
201 // register words below or above the watermarks have bits set.
202 bool valid_watermarks() const {
203 assert(_hwm >= 0 && _hwm < RM_SIZE, "_hwm out of range: %d", _hwm);
204 assert(_lwm >= 0 && _lwm < RM_SIZE, "_lwm out of range: %d", _lwm);
205 for (int i = 0; i < _lwm; i++) {
206 assert(_A[i] == 0, "_lwm too high: %d regs at: %d", _lwm, i);
207 }
208 for (int i = _hwm + 1; i < RM_SIZE; i++) {
209 assert(_A[i] == 0, "_hwm too low: %d regs at: %d", _hwm, i);
210 }
211 return true;
212 }
213 #endif // !ASSERT
214
215 // Test that the mask contains only aligned adjacent bit pairs
216 bool is_aligned_pairs() const;
217
218 // mask is a pair of misaligned registers
219 bool is_misaligned_pair() const;
220 // Test for single register
221 bool is_bound1() const;
222 // Test for a single adjacent pair
223 bool is_bound_pair() const;
224 // Test for a single adjacent set of ideal register's size.
225 bool is_bound(uint ireg) const;
226
227 // Check that whether given reg number with size is valid
228 // for current regmask, where reg is the highest number.
229 bool is_valid_reg(OptoReg::Name reg, const int size) const;
230
231 // Find the lowest-numbered register set in the mask. Return the
232 // HIGHEST register number in the set, or BAD if no sets.
233 // Assert that the mask contains only bit sets.
234 OptoReg::Name find_first_set(LRG &lrg, const int size) const;
235
236 // Clear out partial bits; leave only aligned adjacent bit sets of size.
237 void clear_to_sets(const int size);
238 // Smear out partial bits to aligned adjacent bit sets.
239 void smear_to_sets(const int size);
240 // Test that the mask contains only aligned adjacent bit sets
241 bool is_aligned_sets(const int size) const;
242
243 // Test for a single adjacent set
244 int is_bound_set(const int size) const;
245
246 static bool is_vector(uint ireg);
247 static int num_registers(uint ireg);
248 static int num_registers(uint ireg, LRG &lrg);
249
250 // Fast overlap test. Non-zero if any registers in common.
251 int overlap(const RegMask &rm) const {
252 assert(valid_watermarks() && rm.valid_watermarks(), "sanity");
253 int hwm = MIN2(_hwm, rm._hwm);
254 int lwm = MAX2(_lwm, rm._lwm);
255 int result = 0;
256 for (int i = lwm; i <= hwm; i++) {
257 result |= _A[i] & rm._A[i];
258 }
259 return result;
260 }
261
262 // Special test for register pressure based splitting
263 // UP means register only, Register plus stack, or stack only is DOWN
264 bool is_UP() const;
265
266 // Clear a register mask
267 void Clear() {
268 _lwm = RM_SIZE - 1;
269 _hwm = 0;
270 memset(_A, 0, sizeof(int)*RM_SIZE);
271 assert(valid_watermarks(), "sanity");
272 }
273
274 // Fill a register mask with 1's
275 void Set_All() {
276 _lwm = 0;
277 _hwm = RM_SIZE - 1;
278 memset(_A, 0xFF, sizeof(int)*RM_SIZE);
279 assert(valid_watermarks(), "sanity");
280 }
281
282 // Insert register into mask
283 void Insert(OptoReg::Name reg) {
284 assert(reg < CHUNK_SIZE, "sanity");
285 assert(valid_watermarks(), "pre-condition");
286 int index = reg>>_LogWordBits;
287 if (index > _hwm) _hwm = index;
288 if (index < _lwm) _lwm = index;
289 _A[index] |= (1<<(reg&(_WordBits-1)));
290 assert(valid_watermarks(), "post-condition");
291 }
292
293 // Remove register from mask
294 void Remove(OptoReg::Name reg) {
295 assert(reg < CHUNK_SIZE, "");
296 _A[reg>>_LogWordBits] &= ~(1<<(reg&(_WordBits-1)));
297 }
298
299 // OR 'rm' into 'this'
300 void OR(const RegMask &rm) {
301 assert(valid_watermarks() && rm.valid_watermarks(), "sanity");
302 // OR widens the live range
303 if (_lwm > rm._lwm) _lwm = rm._lwm;
304 if (_hwm < rm._hwm) _hwm = rm._hwm;
305 for (int i = _lwm; i <= _hwm; i++) {
306 _A[i] |= rm._A[i];
307 }
308 assert(valid_watermarks(), "sanity");
309 }
310
311 // AND 'rm' into 'this'
312 void AND(const RegMask &rm) {
313 assert(valid_watermarks() && rm.valid_watermarks(), "sanity");
314 // Do not evaluate words outside the current watermark range, as they are
315 // already zero and an &= would not change that
316 for (int i = _lwm; i <= _hwm; i++) {
317 _A[i] &= rm._A[i];
318 }
319 // Narrow the watermarks if &rm spans a narrower range.
320 // Update after to ensure non-overlapping words are zeroed out.
321 if (_lwm < rm._lwm) _lwm = rm._lwm;
322 if (_hwm > rm._hwm) _hwm = rm._hwm;
323 }
324
325 // Subtract 'rm' from 'this'
326 void SUBTRACT(const RegMask &rm) {
327 assert(valid_watermarks() && rm.valid_watermarks(), "sanity");
328 int hwm = MIN2(_hwm, rm._hwm);
329 int lwm = MAX2(_lwm, rm._lwm);
330 for (int i = lwm; i <= hwm; i++) {
331 _A[i] &= ~rm._A[i];
332 }
333 }
334
335 // Compute size of register mask: number of bits
336 uint Size() const;
337
338 #ifndef PRODUCT
339 void print() const { dump(); }
340 void dump(outputStream *st = tty) const; // Print a mask
341 #endif
342
343 static const RegMask Empty; // Common empty mask
344
345 static bool can_represent(OptoReg::Name reg) {
346 // NOTE: -1 in computation reflects the usage of the last
347 // bit of the regmask as an infinite stack flag and
348 // -7 is to keep mask aligned for largest value (VecZ).
349 return (int)reg < (int)(CHUNK_SIZE-1);
350 }
351 static bool can_represent_arg(OptoReg::Name reg) {
352 // NOTE: -SlotsPerVecZ in computation reflects the need
353 // to keep mask aligned for largest value (VecZ).
354 return (int)reg < (int)(CHUNK_SIZE-SlotsPerVecZ);
355 }
356 };
357
358 // Do not use this constant directly in client code!
359 #undef RM_SIZE
360
361 #endif // SHARE_OPTO_REGMASK_HPP