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src/hotspot/cpu/aarch64/macroAssembler_aarch64.hpp

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rev 60615 : 8231441: Initial SVE backend support
Reviewed-by: adinn, pli
Contributed-by: joshua.zhu@arm.com, yang.zhang@arm.com, ningsheng.jian@arm.com

*** 886,897 **** // if heap base register is used - reinit it with the correct value void reinit_heapbase(); DEBUG_ONLY(void verify_heapbase(const char* msg);) ! void push_CPU_state(bool save_vectors = false); ! void pop_CPU_state(bool restore_vectors = false) ; // Round up to a power of two void round_to(Register reg, int modulus); // allocation --- 886,899 ---- // if heap base register is used - reinit it with the correct value void reinit_heapbase(); DEBUG_ONLY(void verify_heapbase(const char* msg);) ! void push_CPU_state(bool save_vectors = false, bool use_sve = false, ! int sve_vector_size_in_bytes = 0); ! void pop_CPU_state(bool restore_vectors = false, bool use_sve = false, ! int sve_vector_size_in_bytes = 0); // Round up to a power of two void round_to(Register reg, int modulus); // allocation
*** 967,976 **** --- 969,983 ---- Label* L_fast_path = NULL, Label* L_slow_path = NULL); Address argument_address(RegisterOrConstant arg_slot, int extra_slot_offset = 0); + void verify_sve_vector_length(); + void reinitialize_ptrue() { + sve_ptrue(ptrue, B); + } + void verify_ptrue(); // Debugging // only if +VerifyOops void verify_oop(Register reg, const char* s = "broken oop");
*** 1316,1325 **** --- 1323,1333 ---- private: // Returns an address on the stack which is reachable with a ldr/str of size // Uses rscratch2 if the address is not directly reachable Address spill_address(int size, int offset, Register tmp=rscratch2); + Address sve_spill_address(int sve_reg_size_in_bytes, int offset, Register tmp=rscratch2); bool merge_alignment_check(Register base, size_t size, int64_t cur_offset, int64_t prev_offset) const; // Check whether two loads/stores can be merged into ldp/stp. bool ldst_can_merge(Register rx, const Address &adr, size_t cur_size_in_bytes, bool is_store) const;
*** 1339,1358 **** --- 1347,1372 ---- } } void spill(FloatRegister Vx, SIMD_RegVariant T, int offset) { str(Vx, T, spill_address(1 << (int)T, offset)); } + void spill_sve_vector(FloatRegister Zx, int offset, int vector_reg_size_in_bytes) { + sve_str(Zx, sve_spill_address(vector_reg_size_in_bytes, offset)); + } void unspill(Register Rx, bool is64, int offset) { if (is64) { ldr(Rx, spill_address(8, offset)); } else { ldrw(Rx, spill_address(4, offset)); } } void unspill(FloatRegister Vx, SIMD_RegVariant T, int offset) { ldr(Vx, T, spill_address(1 << (int)T, offset)); } + void unspill_sve_vector(FloatRegister Zx, int offset, int vector_reg_size_in_bytes) { + sve_ldr(Zx, sve_spill_address(vector_reg_size_in_bytes, offset)); + } void spill_copy128(int src_offset, int dst_offset, Register tmp1=rscratch1, Register tmp2=rscratch2) { if (src_offset < 512 && (src_offset & 7) == 0 && dst_offset < 512 && (dst_offset & 7) == 0) { ldp(tmp1, tmp2, Address(sp, src_offset));
*** 1362,1372 **** spill(tmp1, true, dst_offset); unspill(tmp1, true, src_offset+8); spill(tmp1, true, dst_offset+8); } } ! void cache_wb(Address line); void cache_wbsync(bool is_pre); }; #ifdef ASSERT --- 1376,1394 ---- spill(tmp1, true, dst_offset); unspill(tmp1, true, src_offset+8); spill(tmp1, true, dst_offset+8); } } ! void spill_copy_sve_vector_stack_to_stack(int src_offset, int dst_offset, ! int sve_vec_reg_size_in_bytes) { ! assert(sve_vec_reg_size_in_bytes % 16 == 0, "unexpected sve vector reg size"); ! for (int i = 0; i < sve_vec_reg_size_in_bytes / 16; i++) { ! spill_copy128(src_offset, dst_offset); ! src_offset += 16; ! dst_offset += 16; ! } ! } void cache_wb(Address line); void cache_wbsync(bool is_pre); }; #ifdef ASSERT
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