src/hotspot/share/opto/opcodes.hpp

rev 60615 : 8231441: Initial SVE backend support
Reviewed-by: adinn, pli
Contributed-by: joshua.zhu@arm.com, yang.zhang@arm.com, ningsheng.jian@arm.com

*** 1,7 ****
  /*
!  * Copyright (c) 1997, 2019, Oracle and/or its affiliates. All rights reserved.
   * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   *
   * This code is free software; you can redistribute it and/or modify it
   * under the terms of the GNU General Public License version 2 only, as
   * published by the Free Software Foundation.
--- 1,7 ----
  /*
!  * Copyright (c) 1997, 2020, Oracle and/or its affiliates. All rights reserved.
   * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   *
   * This code is free software; you can redistribute it and/or modify it
   * under the terms of the GNU General Public License version 2 only, as
   * published by the Free Software Foundation.
*** 35,49 ****
--- 35,51 ----
    macro(RegI)                   // Machine integer register
    macro(RegP)                   // Machine pointer register
    macro(RegF)                   // Machine float   register
    macro(RegD)                   // Machine double  register
    macro(RegL)                   // Machine long    register
+   macro(VecA)                   // Machine vectora register
    macro(VecS)                   // Machine vectors register
    macro(VecD)                   // Machine vectord register
    macro(VecX)                   // Machine vectorx register
    macro(VecY)                   // Machine vectory register
    macro(VecZ)                   // Machine vectorz register
+   macro(RegVMask)               // Vector mask/predicate register
    macro(RegFlags)               // Machine flags   register
    _last_machine_leaf,           // Split between regular opcodes and machine
  #include "classes.hpp"
    _last_opcode
  };