1 /*
2 * Copyright (c) 1997, 2020, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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5 * This code is free software; you can redistribute it and/or modify it
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7 * published by the Free Software Foundation.
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11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
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23 */
24
25 #ifndef SHARE_OPTO_REGMASK_HPP
26 #define SHARE_OPTO_REGMASK_HPP
27
28 #include "code/vmreg.hpp"
29 #include "opto/optoreg.hpp"
30 #include "utilities/count_leading_zeros.hpp"
31 #include "utilities/count_trailing_zeros.hpp"
32
33 class LRG;
34
35 //-------------Non-zero bit search methods used by RegMask---------------------
36 // Find lowest 1, undefined if empty/0
37 static int find_lowest_bit(uint32_t mask) {
38 return count_trailing_zeros(mask);
39 }
40 // Find highest 1, undefined if empty/0
41 static int find_highest_bit(uint32_t mask) {
42 return count_leading_zeros(mask) ^ 31;
43 }
44
45 //------------------------------RegMask----------------------------------------
46 // The ADL file describes how to print the machine-specific registers, as well
47 // as any notion of register classes. We provide a register mask, which is
48 // just a collection of Register numbers.
49
50 // The ADLC defines 2 macros, RM_SIZE and FORALL_BODY.
51 // RM_SIZE is the size of a register mask in words.
52 // FORALL_BODY replicates a BODY macro once per word in the register mask.
53 // The usage is somewhat clumsy and limited to the regmask.[h,c]pp files.
54 // However, it means the ADLC can redefine the unroll macro and all loops
55 // over register masks will be unrolled by the correct amount.
56
57 class RegMask {
58 union {
59 double _dummy_force_double_alignment[RM_SIZE>>1];
60 // Array of Register Mask bits. This array is large enough to cover
61 // all the machine registers and all parameters that need to be passed
62 // on the stack (stack registers) up to some interesting limit. Methods
63 // that need more parameters will NOT be compiled. On Intel, the limit
64 // is something like 90+ parameters.
65 int _A[RM_SIZE];
66 };
67 // The low and high water marks represents the lowest and highest word
68 // that might contain set register mask bits, respectively. We guarantee
69 // that there are no bits in words outside this range, but any word at
70 // and between the two marks can still be 0.
71 int _lwm;
72 int _hwm;
73
74 enum {
75 _WordBits = BitsPerInt,
76 _LogWordBits = LogBitsPerInt,
77 _RM_SIZE = RM_SIZE // local constant, imported, then hidden by #undef
78 };
79
80 public:
81 enum { CHUNK_SIZE = RM_SIZE*_WordBits };
82
83 // SlotsPerLong is 2, since slots are 32 bits and longs are 64 bits.
84 // Also, consider the maximum alignment size for a normally allocated
85 // value. Since we allocate register pairs but not register quads (at
86 // present), this alignment is SlotsPerLong (== 2). A normally
87 // aligned allocated register is either a single register, or a pair
88 // of adjacent registers, the lower-numbered being even.
89 // See also is_aligned_Pairs() below, and the padding added before
90 // Matcher::_new_SP to keep allocated pairs aligned properly.
91 // If we ever go to quad-word allocations, SlotsPerQuad will become
92 // the controlling alignment constraint. Note that this alignment
93 // requirement is internal to the allocator, and independent of any
94 // particular platform.
95 enum { SlotsPerLong = 2,
96 SlotsPerVecA = 8,
97 SlotsPerVecS = 1,
98 SlotsPerVecD = 2,
99 SlotsPerVecX = 4,
100 SlotsPerVecY = 8,
101 SlotsPerVecZ = 16,
102 };
103
104 // A constructor only used by the ADLC output. All mask fields are filled
105 // in directly. Calls to this look something like RM(1,2,3,4);
106 RegMask(
107 # define BODY(I) int a##I,
108 FORALL_BODY
109 # undef BODY
110 int dummy = 0) {
111 # define BODY(I) _A[I] = a##I;
112 FORALL_BODY
113 # undef BODY
114 _lwm = 0;
115 _hwm = RM_SIZE - 1;
116 while (_hwm > 0 && _A[_hwm] == 0) _hwm--;
117 while ((_lwm < _hwm) && _A[_lwm] == 0) _lwm++;
118 assert(valid_watermarks(), "post-condition");
119 }
120
121 // Handy copying constructor
122 RegMask(RegMask *rm) {
123 _hwm = rm->_hwm;
124 _lwm = rm->_lwm;
125 for (int i = 0; i < RM_SIZE; i++) {
126 _A[i] = rm->_A[i];
127 }
128 assert(valid_watermarks(), "post-condition");
129 }
130
131 // Construct an empty mask
132 RegMask() {
133 Clear();
134 }
135
136 // Construct a mask with a single bit
137 RegMask(OptoReg::Name reg) {
138 Clear();
139 Insert(reg);
140 }
141
142 // Check for register being in mask
143 int Member(OptoReg::Name reg) const {
144 assert(reg < CHUNK_SIZE, "");
145 return _A[reg>>_LogWordBits] & (1<<(reg&(_WordBits-1)));
146 }
147
148 // The last bit in the register mask indicates that the mask should repeat
149 // indefinitely with ONE bits. Returns TRUE if mask is infinite or
150 // unbounded in size. Returns FALSE if mask is finite size.
151 int is_AllStack() const { return _A[RM_SIZE-1] >> (_WordBits-1); }
152
153 // Work around an -xO3 optimization problme in WS6U1. The old way:
154 // void set_AllStack() { _A[RM_SIZE-1] |= (1<<(_WordBits-1)); }
155 // will cause _A[RM_SIZE-1] to be clobbered, not updated when set_AllStack()
156 // follows an Insert() loop, like the one found in init_spill_mask(). Using
157 // Insert() instead works because the index into _A in computed instead of
158 // constant. See bug 4665841.
159 void set_AllStack() { Insert(OptoReg::Name(CHUNK_SIZE-1)); }
160
161 // Test for being a not-empty mask.
162 int is_NotEmpty() const {
163 assert(valid_watermarks(), "sanity");
164 int tmp = 0;
165 for (int i = _lwm; i <= _hwm; i++) {
166 tmp |= _A[i];
167 }
168 return tmp;
169 }
170
171 // Find lowest-numbered register from mask, or BAD if mask is empty.
172 OptoReg::Name find_first_elem() const {
173 assert(valid_watermarks(), "sanity");
174 for (int i = _lwm; i <= _hwm; i++) {
175 int bits = _A[i];
176 if (bits) {
177 return OptoReg::Name((i<<_LogWordBits) + find_lowest_bit(bits));
178 }
179 }
180 return OptoReg::Name(OptoReg::Bad);
181 }
182
183 // Get highest-numbered register from mask, or BAD if mask is empty.
184 OptoReg::Name find_last_elem() const {
185 assert(valid_watermarks(), "sanity");
186 for (int i = _hwm; i >= _lwm; i--) {
187 int bits = _A[i];
188 if (bits) {
189 return OptoReg::Name((i<<_LogWordBits) + find_highest_bit(bits));
190 }
191 }
192 return OptoReg::Name(OptoReg::Bad);
193 }
194
195 // Clear out partial bits; leave only aligned adjacent bit pairs.
196 void clear_to_pairs();
197
198 #ifdef ASSERT
199 // Verify watermarks are sane, i.e., within bounds and that no
200 // register words below or above the watermarks have bits set.
201 bool valid_watermarks() const {
202 assert(_hwm >= 0 && _hwm < RM_SIZE, "_hwm out of range: %d", _hwm);
203 assert(_lwm >= 0 && _lwm < RM_SIZE, "_lwm out of range: %d", _lwm);
204 for (int i = 0; i < _lwm; i++) {
205 assert(_A[i] == 0, "_lwm too high: %d regs at: %d", _lwm, i);
206 }
207 for (int i = _hwm + 1; i < RM_SIZE; i++) {
208 assert(_A[i] == 0, "_hwm too low: %d regs at: %d", _hwm, i);
209 }
210 return true;
211 }
212 #endif // !ASSERT
213
214 // Test that the mask contains only aligned adjacent bit pairs
215 bool is_aligned_pairs() const;
216
217 // mask is a pair of misaligned registers
218 bool is_misaligned_pair() const;
219 // Test for single register
220 bool is_bound1() const;
221 // Test for a single adjacent pair
222 bool is_bound_pair() const;
223 // Test for a single adjacent set of ideal register's size.
224 bool is_bound(uint ireg) const;
225
226 // Check that whether given reg number with size is valid
227 // for current regmask, where reg is the highest number.
228 bool is_valid_reg(OptoReg::Name reg, const int size) const;
229
230 // Find the lowest-numbered register set in the mask. Return the
231 // HIGHEST register number in the set, or BAD if no sets.
232 // Assert that the mask contains only bit sets.
233 OptoReg::Name find_first_set(LRG &lrg, const int size) const;
234
235 // Clear out partial bits; leave only aligned adjacent bit sets of size.
236 void clear_to_sets(const int size);
237 // Smear out partial bits to aligned adjacent bit sets.
238 void smear_to_sets(const int size);
239 // Test that the mask contains only aligned adjacent bit sets
240 bool is_aligned_sets(const int size) const;
241
242 // Test for a single adjacent set
243 int is_bound_set(const int size) const;
244
245 static bool is_vector(uint ireg);
246 static int num_registers(uint ireg);
247 static int num_registers(uint ireg, LRG &lrg);
248
249 // Fast overlap test. Non-zero if any registers in common.
250 int overlap(const RegMask &rm) const {
251 assert(valid_watermarks() && rm.valid_watermarks(), "sanity");
252 int hwm = MIN2(_hwm, rm._hwm);
253 int lwm = MAX2(_lwm, rm._lwm);
254 int result = 0;
255 for (int i = lwm; i <= hwm; i++) {
256 result |= _A[i] & rm._A[i];
257 }
258 return result;
259 }
260
261 // Special test for register pressure based splitting
262 // UP means register only, Register plus stack, or stack only is DOWN
263 bool is_UP() const;
264
265 // Clear a register mask
266 void Clear() {
267 _lwm = RM_SIZE - 1;
268 _hwm = 0;
269 memset(_A, 0, sizeof(int)*RM_SIZE);
270 assert(valid_watermarks(), "sanity");
271 }
272
273 // Fill a register mask with 1's
274 void Set_All() {
275 _lwm = 0;
276 _hwm = RM_SIZE - 1;
277 memset(_A, 0xFF, sizeof(int)*RM_SIZE);
278 assert(valid_watermarks(), "sanity");
279 }
280
281 // Insert register into mask
282 void Insert(OptoReg::Name reg) {
283 assert(reg < CHUNK_SIZE, "sanity");
284 assert(valid_watermarks(), "pre-condition");
285 int index = reg>>_LogWordBits;
286 if (index > _hwm) _hwm = index;
287 if (index < _lwm) _lwm = index;
288 _A[index] |= (1<<(reg&(_WordBits-1)));
289 assert(valid_watermarks(), "post-condition");
290 }
291
292 // Remove register from mask
293 void Remove(OptoReg::Name reg) {
294 assert(reg < CHUNK_SIZE, "");
295 _A[reg>>_LogWordBits] &= ~(1<<(reg&(_WordBits-1)));
296 }
297
298 // OR 'rm' into 'this'
299 void OR(const RegMask &rm) {
300 assert(valid_watermarks() && rm.valid_watermarks(), "sanity");
301 // OR widens the live range
302 if (_lwm > rm._lwm) _lwm = rm._lwm;
303 if (_hwm < rm._hwm) _hwm = rm._hwm;
304 for (int i = _lwm; i <= _hwm; i++) {
305 _A[i] |= rm._A[i];
306 }
307 assert(valid_watermarks(), "sanity");
308 }
309
310 // AND 'rm' into 'this'
311 void AND(const RegMask &rm) {
312 assert(valid_watermarks() && rm.valid_watermarks(), "sanity");
313 // Do not evaluate words outside the current watermark range, as they are
314 // already zero and an &= would not change that
315 for (int i = _lwm; i <= _hwm; i++) {
316 _A[i] &= rm._A[i];
317 }
318 // Narrow the watermarks if &rm spans a narrower range.
319 // Update after to ensure non-overlapping words are zeroed out.
320 if (_lwm < rm._lwm) _lwm = rm._lwm;
321 if (_hwm > rm._hwm) _hwm = rm._hwm;
322 }
323
324 // Subtract 'rm' from 'this'
325 void SUBTRACT(const RegMask &rm) {
326 assert(valid_watermarks() && rm.valid_watermarks(), "sanity");
327 int hwm = MIN2(_hwm, rm._hwm);
328 int lwm = MAX2(_lwm, rm._lwm);
329 for (int i = lwm; i <= hwm; i++) {
330 _A[i] &= ~rm._A[i];
331 }
332 }
333
334 // Compute size of register mask: number of bits
335 uint Size() const;
336
337 #ifndef PRODUCT
338 void print() const { dump(); }
339 void dump(outputStream *st = tty) const; // Print a mask
340 #endif
341
342 static const RegMask Empty; // Common empty mask
343
344 static bool can_represent(OptoReg::Name reg) {
345 // NOTE: -1 in computation reflects the usage of the last
346 // bit of the regmask as an infinite stack flag and
347 // -7 is to keep mask aligned for largest value (VecZ).
348 return (int)reg < (int)(CHUNK_SIZE-1);
349 }
350 static bool can_represent_arg(OptoReg::Name reg) {
351 // NOTE: -SlotsPerVecZ in computation reflects the need
352 // to keep mask aligned for largest value (VecZ).
353 return (int)reg < (int)(CHUNK_SIZE-SlotsPerVecZ);
354 }
355 };
356
357 // Do not use this constant directly in client code!
358 #undef RM_SIZE
359
360 #endif // SHARE_OPTO_REGMASK_HPP