232 CPU_MMX = (1 << 4),
233 CPU_3DNOW_PREFETCH = (1 << 5), // Processor supports 3dnow prefetch and prefetchw instructions
234 // may not necessarily support other 3dnow instructions
235 CPU_SSE = (1 << 6),
236 CPU_SSE2 = (1 << 7),
237 CPU_SSE3 = (1 << 8), // SSE3 comes from cpuid 1 (ECX)
238 CPU_SSSE3 = (1 << 9),
239 CPU_SSE4A = (1 << 10),
240 CPU_SSE4_1 = (1 << 11),
241 CPU_SSE4_2 = (1 << 12),
242 CPU_POPCNT = (1 << 13),
243 CPU_LZCNT = (1 << 14),
244 CPU_TSC = (1 << 15),
245 CPU_TSCINV = (1 << 16),
246 CPU_AVX = (1 << 17),
247 CPU_AVX2 = (1 << 18)
248 } cpuFeatureFlags;
249
250 enum {
251 // AMD
252 CPU_FAMILY_AMD_11H = 17,
253 // Intel
254 CPU_FAMILY_INTEL_CORE = 6,
255 CPU_MODEL_NEHALEM_EP = 26,
256 CPU_MODEL_WESTMERE_EP = 44,
257 // CPU_MODEL_IVYBRIDGE_EP = ??, TODO - get real value
258 CPU_MODEL_SANDYBRIDGE_EP = 45
259 } cpuExtendedFamily;
260
261 // cpuid information block. All info derived from executing cpuid with
262 // various function numbers is stored here. Intel and AMD info is
263 // merged in this block: accessor methods disentangle it.
264 //
265 // The info block is laid out in subblocks of 4 dwords corresponding to
266 // eax, ebx, ecx and edx, whether or not they contain anything useful.
267 struct CpuidInfo {
268 // cpuid function 0
269 uint32_t std_max_function;
270 uint32_t std_vendor_name_0;
271 uint32_t std_vendor_name_1;
272 uint32_t std_vendor_name_2;
273
274 // cpuid function 1
275 StdCpuid1Eax std_cpuid1_eax;
276 StdCpuid1Ebx std_cpuid1_ebx;
277 StdCpuid1Ecx std_cpuid1_ecx;
278 StdCpuid1Edx std_cpuid1_edx;
308 uint32_t tpl_cpuidB2_ecx; // unused currently
309 uint32_t tpl_cpuidB2_edx; // unused currently
310
311 // cpuid function 0x80000000 // example, unused
312 uint32_t ext_max_function;
313 uint32_t ext_vendor_name_0;
314 uint32_t ext_vendor_name_1;
315 uint32_t ext_vendor_name_2;
316
317 // cpuid function 0x80000001
318 uint32_t ext_cpuid1_eax; // reserved
319 uint32_t ext_cpuid1_ebx; // reserved
320 ExtCpuid1Ecx ext_cpuid1_ecx;
321 ExtCpuid1Edx ext_cpuid1_edx;
322
323 // cpuid functions 0x80000002 thru 0x80000004: example, unused
324 uint32_t proc_name_0, proc_name_1, proc_name_2, proc_name_3;
325 uint32_t proc_name_4, proc_name_5, proc_name_6, proc_name_7;
326 uint32_t proc_name_8, proc_name_9, proc_name_10,proc_name_11;
327
328 // cpuid function 0x80000005 //AMD L1, Intel reserved
329 uint32_t ext_cpuid5_eax; // unused currently
330 uint32_t ext_cpuid5_ebx; // reserved
331 ExtCpuid5Ex ext_cpuid5_ecx; // L1 data cache info (AMD)
332 ExtCpuid5Ex ext_cpuid5_edx; // L1 instruction cache info (AMD)
333
334 // cpuid function 0x80000007
335 uint32_t ext_cpuid7_eax; // reserved
336 uint32_t ext_cpuid7_ebx; // reserved
337 uint32_t ext_cpuid7_ecx; // reserved
338 ExtCpuid7Edx ext_cpuid7_edx; // tscinv
339
340 // cpuid function 0x80000008
341 uint32_t ext_cpuid8_eax; // unused currently
342 uint32_t ext_cpuid8_ebx; // reserved
343 ExtCpuid8Ecx ext_cpuid8_ecx;
344 uint32_t ext_cpuid8_edx; // reserved
345
346 // extended control register XCR0 (the XFEATURE_ENABLED_MASK register)
347 XemXcr0Eax xem_xcr0_eax;
348 uint32_t xem_xcr0_edx; // reserved
532 static bool supports_sse() { return (_cpuFeatures & CPU_SSE) != 0; }
533 static bool supports_sse2() { return (_cpuFeatures & CPU_SSE2) != 0; }
534 static bool supports_sse3() { return (_cpuFeatures & CPU_SSE3) != 0; }
535 static bool supports_ssse3() { return (_cpuFeatures & CPU_SSSE3)!= 0; }
536 static bool supports_sse4_1() { return (_cpuFeatures & CPU_SSE4_1) != 0; }
537 static bool supports_sse4_2() { return (_cpuFeatures & CPU_SSE4_2) != 0; }
538 static bool supports_popcnt() { return (_cpuFeatures & CPU_POPCNT) != 0; }
539 static bool supports_avx() { return (_cpuFeatures & CPU_AVX) != 0; }
540 static bool supports_avx2() { return (_cpuFeatures & CPU_AVX2) != 0; }
541 static bool supports_tsc() { return (_cpuFeatures & CPU_TSC) != 0; }
542
543 // Intel features
544 static bool is_intel_family_core() { return is_intel() &&
545 extended_cpu_family() == CPU_FAMILY_INTEL_CORE; }
546
547 static bool is_intel_tsc_synched_at_init() {
548 if (is_intel_family_core()) {
549 uint32_t ext_model = extended_cpu_model();
550 if (ext_model == CPU_MODEL_NEHALEM_EP ||
551 ext_model == CPU_MODEL_WESTMERE_EP ||
552 // TODO ext_model == CPU_MODEL_IVYBRIDGE_EP ||
553 ext_model == CPU_MODEL_SANDYBRIDGE_EP) {
554 // 2-socket invtsc support. EX versions with 4 sockets are not
555 // guaranteed to synchronize tscs at initialization via a double
556 // handshake. The tscs can be explicitly set in software. Code
557 // that uses tsc values must be prepared for them to arbitrarily
558 // jump backward or forward.
559 return true;
560 }
561 }
562 return false;
563 }
564
565 // AMD features
566 static bool supports_3dnow_prefetch() { return (_cpuFeatures & CPU_3DNOW_PREFETCH) != 0; }
567 static bool supports_mmx_ext() { return is_amd() && _cpuid_info.ext_cpuid1_edx.bits.mmx_amd != 0; }
568 static bool supports_lzcnt() { return (_cpuFeatures & CPU_LZCNT) != 0; }
569 static bool supports_sse4a() { return (_cpuFeatures & CPU_SSE4A) != 0; }
570
571 static bool is_amd_Barcelona() { return is_amd() &&
572 extended_cpu_family() == CPU_FAMILY_AMD_11H; }
573
574 // Intel and AMD newer cores support fast timestamps well
575 static bool supports_tscinv_bit() {
576 return (_cpuFeatures & CPU_TSCINV) != 0;
577 }
578 static bool supports_tscinv() {
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232 CPU_MMX = (1 << 4),
233 CPU_3DNOW_PREFETCH = (1 << 5), // Processor supports 3dnow prefetch and prefetchw instructions
234 // may not necessarily support other 3dnow instructions
235 CPU_SSE = (1 << 6),
236 CPU_SSE2 = (1 << 7),
237 CPU_SSE3 = (1 << 8), // SSE3 comes from cpuid 1 (ECX)
238 CPU_SSSE3 = (1 << 9),
239 CPU_SSE4A = (1 << 10),
240 CPU_SSE4_1 = (1 << 11),
241 CPU_SSE4_2 = (1 << 12),
242 CPU_POPCNT = (1 << 13),
243 CPU_LZCNT = (1 << 14),
244 CPU_TSC = (1 << 15),
245 CPU_TSCINV = (1 << 16),
246 CPU_AVX = (1 << 17),
247 CPU_AVX2 = (1 << 18)
248 } cpuFeatureFlags;
249
250 enum {
251 // AMD
252 CPU_FAMILY_AMD_11H = 0x11,
253 // Intel
254 CPU_FAMILY_INTEL_CORE = 6,
255 CPU_MODEL_NEHALEM_EP = 0x1a,
256 CPU_MODEL_NEHALEM_EX = 0x2e,
257 CPU_MODEL_WESTMERE_EP = 0x2c,
258 CPU_MODEL_WESTMERE_EX = 0x2f,
259 CPU_MODEL_SANDYBRIDGE_EP = 0x2a,
260 CPU_MODEL_IVYBRIDGE_EP = 0x3a
261 } cpuExtendedFamily;
262
263 // cpuid information block. All info derived from executing cpuid with
264 // various function numbers is stored here. Intel and AMD info is
265 // merged in this block: accessor methods disentangle it.
266 //
267 // The info block is laid out in subblocks of 4 dwords corresponding to
268 // eax, ebx, ecx and edx, whether or not they contain anything useful.
269 struct CpuidInfo {
270 // cpuid function 0
271 uint32_t std_max_function;
272 uint32_t std_vendor_name_0;
273 uint32_t std_vendor_name_1;
274 uint32_t std_vendor_name_2;
275
276 // cpuid function 1
277 StdCpuid1Eax std_cpuid1_eax;
278 StdCpuid1Ebx std_cpuid1_ebx;
279 StdCpuid1Ecx std_cpuid1_ecx;
280 StdCpuid1Edx std_cpuid1_edx;
310 uint32_t tpl_cpuidB2_ecx; // unused currently
311 uint32_t tpl_cpuidB2_edx; // unused currently
312
313 // cpuid function 0x80000000 // example, unused
314 uint32_t ext_max_function;
315 uint32_t ext_vendor_name_0;
316 uint32_t ext_vendor_name_1;
317 uint32_t ext_vendor_name_2;
318
319 // cpuid function 0x80000001
320 uint32_t ext_cpuid1_eax; // reserved
321 uint32_t ext_cpuid1_ebx; // reserved
322 ExtCpuid1Ecx ext_cpuid1_ecx;
323 ExtCpuid1Edx ext_cpuid1_edx;
324
325 // cpuid functions 0x80000002 thru 0x80000004: example, unused
326 uint32_t proc_name_0, proc_name_1, proc_name_2, proc_name_3;
327 uint32_t proc_name_4, proc_name_5, proc_name_6, proc_name_7;
328 uint32_t proc_name_8, proc_name_9, proc_name_10,proc_name_11;
329
330 // cpuid function 0x80000005 // AMD L1, Intel reserved
331 uint32_t ext_cpuid5_eax; // unused currently
332 uint32_t ext_cpuid5_ebx; // reserved
333 ExtCpuid5Ex ext_cpuid5_ecx; // L1 data cache info (AMD)
334 ExtCpuid5Ex ext_cpuid5_edx; // L1 instruction cache info (AMD)
335
336 // cpuid function 0x80000007
337 uint32_t ext_cpuid7_eax; // reserved
338 uint32_t ext_cpuid7_ebx; // reserved
339 uint32_t ext_cpuid7_ecx; // reserved
340 ExtCpuid7Edx ext_cpuid7_edx; // tscinv
341
342 // cpuid function 0x80000008
343 uint32_t ext_cpuid8_eax; // unused currently
344 uint32_t ext_cpuid8_ebx; // reserved
345 ExtCpuid8Ecx ext_cpuid8_ecx;
346 uint32_t ext_cpuid8_edx; // reserved
347
348 // extended control register XCR0 (the XFEATURE_ENABLED_MASK register)
349 XemXcr0Eax xem_xcr0_eax;
350 uint32_t xem_xcr0_edx; // reserved
534 static bool supports_sse() { return (_cpuFeatures & CPU_SSE) != 0; }
535 static bool supports_sse2() { return (_cpuFeatures & CPU_SSE2) != 0; }
536 static bool supports_sse3() { return (_cpuFeatures & CPU_SSE3) != 0; }
537 static bool supports_ssse3() { return (_cpuFeatures & CPU_SSSE3)!= 0; }
538 static bool supports_sse4_1() { return (_cpuFeatures & CPU_SSE4_1) != 0; }
539 static bool supports_sse4_2() { return (_cpuFeatures & CPU_SSE4_2) != 0; }
540 static bool supports_popcnt() { return (_cpuFeatures & CPU_POPCNT) != 0; }
541 static bool supports_avx() { return (_cpuFeatures & CPU_AVX) != 0; }
542 static bool supports_avx2() { return (_cpuFeatures & CPU_AVX2) != 0; }
543 static bool supports_tsc() { return (_cpuFeatures & CPU_TSC) != 0; }
544
545 // Intel features
546 static bool is_intel_family_core() { return is_intel() &&
547 extended_cpu_family() == CPU_FAMILY_INTEL_CORE; }
548
549 static bool is_intel_tsc_synched_at_init() {
550 if (is_intel_family_core()) {
551 uint32_t ext_model = extended_cpu_model();
552 if (ext_model == CPU_MODEL_NEHALEM_EP ||
553 ext_model == CPU_MODEL_WESTMERE_EP ||
554 ext_model == CPU_MODEL_SANDYBRIDGE_EP ||
555 ext_model == CPU_MODEL_IVYBRIDGE_EP) {
556 // 2-socket invariant tsc support. EX versions are usually used in
557 // > 2-socket systems and not guaranteed to synchronize tscs at
558 // initialization. Hotspot doesn't currently figure out the number
559 // of sockets, so we ignore EX versions and the possibility of
560 // 4-socket EP systems even though the latter can't have their tscs
561 // sync'ed at init time either.
562 // Code that uses tsc values must be prepared for them to arbitrarily
563 // jump forward or backward.
564 return true;
565 }
566 }
567 return false;
568 }
569
570 // AMD features
571 static bool supports_3dnow_prefetch() { return (_cpuFeatures & CPU_3DNOW_PREFETCH) != 0; }
572 static bool supports_mmx_ext() { return is_amd() && _cpuid_info.ext_cpuid1_edx.bits.mmx_amd != 0; }
573 static bool supports_lzcnt() { return (_cpuFeatures & CPU_LZCNT) != 0; }
574 static bool supports_sse4a() { return (_cpuFeatures & CPU_SSE4A) != 0; }
575
576 static bool is_amd_Barcelona() { return is_amd() &&
577 extended_cpu_family() == CPU_FAMILY_AMD_11H; }
578
579 // Intel and AMD newer cores support fast timestamps well
580 static bool supports_tscinv_bit() {
581 return (_cpuFeatures & CPU_TSCINV) != 0;
582 }
583 static bool supports_tscinv() {
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