1 /* 2 * Copyright (c) 1997, 2014, Oracle and/or its affiliates. All rights reserved. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 * 5 * This code is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 only, as 7 * published by the Free Software Foundation. 8 * 9 * This code is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * version 2 for more details (a copy is included in the LICENSE file that 13 * accompanied this code). 14 * 15 * You should have received a copy of the GNU General Public License version 16 * 2 along with this work; if not, write to the Free Software Foundation, 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 20 * or visit www.oracle.com if you need additional information or have any 21 * questions. 22 * 23 */ 24 25 #include "precompiled.hpp" 26 #include "asm/macroAssembler.inline.hpp" 27 #include "memory/resourceArea.hpp" 28 #include "runtime/java.hpp" 29 #include "runtime/stubCodeGenerator.hpp" 30 #include "vm_version_sparc.hpp" 31 #ifdef TARGET_OS_FAMILY_linux 32 # include "os_linux.inline.hpp" 33 #endif 34 #ifdef TARGET_OS_FAMILY_solaris 35 # include "os_solaris.inline.hpp" 36 #endif 37 38 int VM_Version::_features = VM_Version::unknown_m; 39 const char* VM_Version::_features_str = ""; 40 unsigned int VM_Version::_L2_data_cache_line_size = 0; 41 42 void VM_Version::initialize() { 43 44 assert(_features != VM_Version::unknown_m, "System pre-initialization is not complete."); 45 guarantee(VM_Version::has_v9(), "only SPARC v9 is supported"); 46 47 PrefetchCopyIntervalInBytes = prefetch_copy_interval_in_bytes(); 48 PrefetchScanIntervalInBytes = prefetch_scan_interval_in_bytes(); 49 PrefetchFieldsAhead = prefetch_fields_ahead(); 50 51 assert(0 <= AllocatePrefetchInstr && AllocatePrefetchInstr <= 1, "invalid value"); 52 if( AllocatePrefetchInstr < 0 ) AllocatePrefetchInstr = 0; 53 if( AllocatePrefetchInstr > 1 ) AllocatePrefetchInstr = 0; 54 55 // Allocation prefetch settings 56 intx cache_line_size = prefetch_data_size(); 57 if( cache_line_size > AllocatePrefetchStepSize ) 58 AllocatePrefetchStepSize = cache_line_size; 59 60 assert(AllocatePrefetchLines > 0, "invalid value"); 61 if( AllocatePrefetchLines < 1 ) // set valid value in product VM 62 AllocatePrefetchLines = 3; 63 assert(AllocateInstancePrefetchLines > 0, "invalid value"); 64 if( AllocateInstancePrefetchLines < 1 ) // set valid value in product VM 65 AllocateInstancePrefetchLines = 1; 66 67 AllocatePrefetchDistance = allocate_prefetch_distance(); 68 AllocatePrefetchStyle = allocate_prefetch_style(); 69 70 assert((AllocatePrefetchDistance % AllocatePrefetchStepSize) == 0 && 71 (AllocatePrefetchDistance > 0), "invalid value"); 72 if ((AllocatePrefetchDistance % AllocatePrefetchStepSize) != 0 || 73 (AllocatePrefetchDistance <= 0)) { 74 AllocatePrefetchDistance = AllocatePrefetchStepSize; 75 } 76 77 if (AllocatePrefetchStyle == 3 && !has_blk_init()) { 78 warning("BIS instructions are not available on this CPU"); 79 FLAG_SET_DEFAULT(AllocatePrefetchStyle, 1); 80 } 81 82 assert(ArraycopySrcPrefetchDistance < 4096, "invalid value"); 83 if (ArraycopySrcPrefetchDistance >= 4096) 84 ArraycopySrcPrefetchDistance = 4064; 85 assert(ArraycopyDstPrefetchDistance < 4096, "invalid value"); 86 if (ArraycopyDstPrefetchDistance >= 4096) 87 ArraycopyDstPrefetchDistance = 4064; 88 89 UseSSE = 0; // Only on x86 and x64 90 91 _supports_cx8 = has_v9(); 92 _supports_atomic_getset4 = true; // swap instruction 93 94 // There are Fujitsu Sparc64 CPUs which support blk_init as well so 95 // we have to take this check out of the 'is_niagara()' block below. 96 if (has_blk_init()) { 97 // When using CMS or G1, we cannot use memset() in BOT updates 98 // because the sun4v/CMT version in libc_psr uses BIS which 99 // exposes "phantom zeros" to concurrent readers. See 6948537. 100 if (FLAG_IS_DEFAULT(UseMemSetInBOT) && (UseConcMarkSweepGC || UseG1GC)) { 101 FLAG_SET_DEFAULT(UseMemSetInBOT, false); 102 } 103 // Issue a stern warning if the user has explicitly set 104 // UseMemSetInBOT (it is known to cause issues), but allow 105 // use for experimentation and debugging. 106 if (UseConcMarkSweepGC || UseG1GC) { 107 if (UseMemSetInBOT) { 108 assert(!FLAG_IS_DEFAULT(UseMemSetInBOT), "Error"); 109 warning("Experimental flag -XX:+UseMemSetInBOT is known to cause instability" 110 " on sun4v; please understand that you are using at your own risk!"); 111 } 112 } 113 } 114 115 if (is_niagara()) { 116 // Indirect branch is the same cost as direct 117 if (FLAG_IS_DEFAULT(UseInlineCaches)) { 118 FLAG_SET_DEFAULT(UseInlineCaches, false); 119 } 120 // Align loops on a single instruction boundary. 121 if (FLAG_IS_DEFAULT(OptoLoopAlignment)) { 122 FLAG_SET_DEFAULT(OptoLoopAlignment, 4); 123 } 124 #ifdef _LP64 125 // 32-bit oops don't make sense for the 64-bit VM on sparc 126 // since the 32-bit VM has the same registers and smaller objects. 127 Universe::set_narrow_oop_shift(LogMinObjAlignmentInBytes); 128 Universe::set_narrow_klass_shift(LogKlassAlignmentInBytes); 129 #endif // _LP64 130 #ifdef COMPILER2 131 // Indirect branch is the same cost as direct 132 if (FLAG_IS_DEFAULT(UseJumpTables)) { 133 FLAG_SET_DEFAULT(UseJumpTables, true); 134 } 135 // Single-issue, so entry and loop tops are 136 // aligned on a single instruction boundary 137 if (FLAG_IS_DEFAULT(InteriorEntryAlignment)) { 138 FLAG_SET_DEFAULT(InteriorEntryAlignment, 4); 139 } 140 if (is_niagara_plus()) { 141 if (has_blk_init() && UseTLAB && 142 FLAG_IS_DEFAULT(AllocatePrefetchInstr)) { 143 // Use BIS instruction for TLAB allocation prefetch. 144 FLAG_SET_ERGO(intx, AllocatePrefetchInstr, 1); 145 if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) { 146 FLAG_SET_ERGO(intx, AllocatePrefetchStyle, 3); 147 } 148 if (FLAG_IS_DEFAULT(AllocatePrefetchDistance)) { 149 // Use smaller prefetch distance with BIS 150 FLAG_SET_DEFAULT(AllocatePrefetchDistance, 64); 151 } 152 } 153 if (is_T4()) { 154 // Double number of prefetched cache lines on T4 155 // since L2 cache line size is smaller (32 bytes). 156 if (FLAG_IS_DEFAULT(AllocatePrefetchLines)) { 157 FLAG_SET_ERGO(intx, AllocatePrefetchLines, AllocatePrefetchLines*2); 158 } 159 if (FLAG_IS_DEFAULT(AllocateInstancePrefetchLines)) { 160 FLAG_SET_ERGO(intx, AllocateInstancePrefetchLines, AllocateInstancePrefetchLines*2); 161 } 162 } 163 if (AllocatePrefetchStyle != 3 && FLAG_IS_DEFAULT(AllocatePrefetchDistance)) { 164 // Use different prefetch distance without BIS 165 FLAG_SET_DEFAULT(AllocatePrefetchDistance, 256); 166 } 167 if (AllocatePrefetchInstr == 1) { 168 // Need a space at the end of TLAB for BIS since it 169 // will fault when accessing memory outside of heap. 170 171 // +1 for rounding up to next cache line, +1 to be safe 172 int lines = AllocatePrefetchLines + 2; 173 int step_size = AllocatePrefetchStepSize; 174 int distance = AllocatePrefetchDistance; 175 _reserve_for_allocation_prefetch = (distance + step_size*lines)/(int)HeapWordSize; 176 } 177 } 178 #endif 179 } 180 181 // Use hardware population count instruction if available. 182 if (has_hardware_popc()) { 183 if (FLAG_IS_DEFAULT(UsePopCountInstruction)) { 184 FLAG_SET_DEFAULT(UsePopCountInstruction, true); 185 } 186 } else if (UsePopCountInstruction) { 187 warning("POPC instruction is not available on this CPU"); 188 FLAG_SET_DEFAULT(UsePopCountInstruction, false); 189 } 190 191 // T4 and newer Sparc cpus have new compare and branch instruction. 192 if (has_cbcond()) { 193 if (FLAG_IS_DEFAULT(UseCBCond)) { 194 FLAG_SET_DEFAULT(UseCBCond, true); 195 } 196 } else if (UseCBCond) { 197 warning("CBCOND instruction is not available on this CPU"); 198 FLAG_SET_DEFAULT(UseCBCond, false); 199 } 200 201 assert(BlockZeroingLowLimit > 0, "invalid value"); 202 if (has_block_zeroing() && cache_line_size > 0) { 203 if (FLAG_IS_DEFAULT(UseBlockZeroing)) { 204 FLAG_SET_DEFAULT(UseBlockZeroing, true); 205 } 206 } else if (UseBlockZeroing) { 207 warning("BIS zeroing instructions are not available on this CPU"); 208 FLAG_SET_DEFAULT(UseBlockZeroing, false); 209 } 210 211 assert(BlockCopyLowLimit > 0, "invalid value"); 212 if (has_block_zeroing() && cache_line_size > 0) { // has_blk_init() && is_T4(): core's local L2 cache 213 if (FLAG_IS_DEFAULT(UseBlockCopy)) { 214 FLAG_SET_DEFAULT(UseBlockCopy, true); 215 } 216 } else if (UseBlockCopy) { 217 warning("BIS instructions are not available or expensive on this CPU"); 218 FLAG_SET_DEFAULT(UseBlockCopy, false); 219 } 220 221 #ifdef COMPILER2 222 // T4 and newer Sparc cpus have fast RDPC. 223 if (has_fast_rdpc() && FLAG_IS_DEFAULT(UseRDPCForConstantTableBase)) { 224 FLAG_SET_DEFAULT(UseRDPCForConstantTableBase, true); 225 } 226 227 // Currently not supported anywhere. 228 FLAG_SET_DEFAULT(UseFPUForSpilling, false); 229 230 MaxVectorSize = 8; 231 232 assert((InteriorEntryAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size"); 233 #endif 234 235 assert((CodeEntryAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size"); 236 assert((OptoLoopAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size"); 237 238 char buf[512]; 239 jio_snprintf(buf, sizeof(buf), "%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s", 240 (has_v9() ? ", v9" : (has_v8() ? ", v8" : "")), 241 (has_hardware_popc() ? ", popc" : ""), 242 (has_vis1() ? ", vis1" : ""), 243 (has_vis2() ? ", vis2" : ""), 244 (has_vis3() ? ", vis3" : ""), 245 (has_blk_init() ? ", blk_init" : ""), 246 (has_cbcond() ? ", cbcond" : ""), 247 (has_aes() ? ", aes" : ""), 248 (has_sha1() ? ", sha1" : ""), 249 (has_sha256() ? ", sha256" : ""), 250 (has_sha512() ? ", sha512" : ""), 251 (is_ultra3() ? ", ultra3" : ""), 252 (is_sun4v() ? ", sun4v" : ""), 253 (is_niagara_plus() ? ", niagara_plus" : (is_niagara() ? ", niagara" : "")), 254 (is_sparc64() ? ", sparc64" : ""), 255 (!has_hardware_mul32() ? ", no-mul32" : ""), 256 (!has_hardware_div32() ? ", no-div32" : ""), 257 (!has_hardware_fsmuld() ? ", no-fsmuld" : "")); 258 259 // buf is started with ", " or is empty 260 _features_str = strdup(strlen(buf) > 2 ? buf + 2 : buf); 261 262 // UseVIS is set to the smallest of what hardware supports and what 263 // the command line requires. I.e., you cannot set UseVIS to 3 on 264 // older UltraSparc which do not support it. 265 if (UseVIS > 3) UseVIS=3; 266 if (UseVIS < 0) UseVIS=0; 267 if (!has_vis3()) // Drop to 2 if no VIS3 support 268 UseVIS = MIN2((intx)2,UseVIS); 269 if (!has_vis2()) // Drop to 1 if no VIS2 support 270 UseVIS = MIN2((intx)1,UseVIS); 271 if (!has_vis1()) // Drop to 0 if no VIS1 support 272 UseVIS = 0; 273 274 // SPARC T4 and above should have support for AES instructions 275 if (has_aes()) { 276 if (UseVIS > 2) { // AES intrinsics use MOVxTOd/MOVdTOx which are VIS3 277 if (FLAG_IS_DEFAULT(UseAES)) { 278 FLAG_SET_DEFAULT(UseAES, true); 279 } 280 if (FLAG_IS_DEFAULT(UseAESIntrinsics)) { 281 FLAG_SET_DEFAULT(UseAESIntrinsics, true); 282 } 283 // we disable both the AES flags if either of them is disabled on the command line 284 if (!UseAES || !UseAESIntrinsics) { 285 FLAG_SET_DEFAULT(UseAES, false); 286 FLAG_SET_DEFAULT(UseAESIntrinsics, false); 287 } 288 } else { 289 if (UseAES || UseAESIntrinsics) { 290 warning("SPARC AES intrinsics require VIS3 instruction support. Intrinsics will be disabled."); 291 if (UseAES) { 292 FLAG_SET_DEFAULT(UseAES, false); 293 } 294 if (UseAESIntrinsics) { 295 FLAG_SET_DEFAULT(UseAESIntrinsics, false); 296 } 297 } 298 } 299 } else if (UseAES || UseAESIntrinsics) { 300 warning("AES instructions are not available on this CPU"); 301 if (UseAES) { 302 FLAG_SET_DEFAULT(UseAES, false); 303 } 304 if (UseAESIntrinsics) { 305 FLAG_SET_DEFAULT(UseAESIntrinsics, false); 306 } 307 } 308 309 // SHA1, SHA256, and SHA512 instructions were added to SPARC T-series at different times 310 if (has_sha1() || has_sha256() || has_sha512()) { 311 if (UseVIS > 0) { // SHA intrinsics use VIS1 instructions 312 if (FLAG_IS_DEFAULT(UseSHA)) { 313 FLAG_SET_DEFAULT(UseSHA, true); 314 } 315 } else { 316 if (UseSHA) { 317 warning("SPARC SHA intrinsics require VIS1 instruction support. Intrinsics will be disabled."); 318 FLAG_SET_DEFAULT(UseSHA, false); 319 } 320 } 321 } else if (UseSHA) { 322 warning("SHA instructions are not available on this CPU"); 323 FLAG_SET_DEFAULT(UseSHA, false); 324 } 325 326 if (!UseSHA) { 327 FLAG_SET_DEFAULT(UseSHA1Intrinsics, false); 328 FLAG_SET_DEFAULT(UseSHA256Intrinsics, false); 329 FLAG_SET_DEFAULT(UseSHA512Intrinsics, false); 330 } else { 331 if (has_sha1()) { 332 if (FLAG_IS_DEFAULT(UseSHA1Intrinsics)) { 333 FLAG_SET_DEFAULT(UseSHA1Intrinsics, true); 334 } 335 } else if (UseSHA1Intrinsics) { 336 warning("SHA1 instruction is not available on this CPU."); 337 FLAG_SET_DEFAULT(UseSHA1Intrinsics, false); 338 } 339 if (has_sha256()) { 340 if (FLAG_IS_DEFAULT(UseSHA256Intrinsics)) { 341 FLAG_SET_DEFAULT(UseSHA256Intrinsics, true); 342 } 343 } else if (UseSHA256Intrinsics) { 344 warning("SHA256 instruction (for SHA-224 and SHA-256) is not available on this CPU."); 345 FLAG_SET_DEFAULT(UseSHA256Intrinsics, false); 346 } 347 348 if (has_sha512()) { 349 if (FLAG_IS_DEFAULT(UseSHA512Intrinsics)) { 350 FLAG_SET_DEFAULT(UseSHA512Intrinsics, true); 351 } 352 } else if (UseSHA512Intrinsics) { 353 warning("SHA512 instruction (for SHA-384 and SHA-512) is not available on this CPU."); 354 FLAG_SET_DEFAULT(UseSHA512Intrinsics, false); 355 } 356 if (!(UseSHA1Intrinsics || UseSHA256Intrinsics || UseSHA512Intrinsics)) { 357 FLAG_SET_DEFAULT(UseSHA, false); 358 } 359 } 360 361 if (FLAG_IS_DEFAULT(ContendedPaddingWidth) && 362 (cache_line_size > ContendedPaddingWidth)) 363 ContendedPaddingWidth = cache_line_size; 364 365 #ifndef PRODUCT 366 if (PrintMiscellaneous && Verbose) { 367 tty->print_cr("L2 data cache line size: %u", L2_data_cache_line_size()); 368 tty->print("Allocation"); 369 if (AllocatePrefetchStyle <= 0) { 370 tty->print_cr(": no prefetching"); 371 } else { 372 tty->print(" prefetching: "); 373 if (AllocatePrefetchInstr == 0) { 374 tty->print("PREFETCH"); 375 } else if (AllocatePrefetchInstr == 1) { 376 tty->print("BIS"); 377 } 378 if (AllocatePrefetchLines > 1) { 379 tty->print_cr(" at distance %d, %d lines of %d bytes", (int) AllocatePrefetchDistance, (int) AllocatePrefetchLines, (int) AllocatePrefetchStepSize); 380 } else { 381 tty->print_cr(" at distance %d, one line of %d bytes", (int) AllocatePrefetchDistance, (int) AllocatePrefetchStepSize); 382 } 383 } 384 if (PrefetchCopyIntervalInBytes > 0) { 385 tty->print_cr("PrefetchCopyIntervalInBytes %d", (int) PrefetchCopyIntervalInBytes); 386 } 387 if (PrefetchScanIntervalInBytes > 0) { 388 tty->print_cr("PrefetchScanIntervalInBytes %d", (int) PrefetchScanIntervalInBytes); 389 } 390 if (PrefetchFieldsAhead > 0) { 391 tty->print_cr("PrefetchFieldsAhead %d", (int) PrefetchFieldsAhead); 392 } 393 if (ContendedPaddingWidth > 0) { 394 tty->print_cr("ContendedPaddingWidth %d", (int) ContendedPaddingWidth); 395 } 396 } 397 #endif // PRODUCT 398 } 399 400 void VM_Version::print_features() { 401 tty->print_cr("Version:%s", cpu_features()); 402 } 403 404 int VM_Version::determine_features() { 405 if (UseV8InstrsOnly) { 406 NOT_PRODUCT(if (PrintMiscellaneous && Verbose) tty->print_cr("Version is Forced-V8");) 407 return generic_v8_m; 408 } 409 410 int features = platform_features(unknown_m); // platform_features() is os_arch specific 411 412 if (features == unknown_m) { 413 features = generic_v9_m; 414 warning("Cannot recognize SPARC version. Default to V9"); 415 } 416 417 assert(is_T_family(features) == is_niagara(features), "Niagara should be T series"); 418 if (UseNiagaraInstrs) { // Force code generation for Niagara 419 if (is_T_family(features)) { 420 // Happy to accomodate... 421 } else { 422 NOT_PRODUCT(if (PrintMiscellaneous && Verbose) tty->print_cr("Version is Forced-Niagara");) 423 features |= T_family_m; 424 } 425 } else { 426 if (is_T_family(features) && !FLAG_IS_DEFAULT(UseNiagaraInstrs)) { 427 NOT_PRODUCT(if (PrintMiscellaneous && Verbose) tty->print_cr("Version is Forced-Not-Niagara");) 428 features &= ~(T_family_m | T1_model_m); 429 } else { 430 // Happy to accomodate... 431 } 432 } 433 434 return features; 435 } 436 437 static int saved_features = 0; 438 439 void VM_Version::allow_all() { 440 saved_features = _features; 441 _features = all_features_m; 442 } 443 444 void VM_Version::revert() { 445 _features = saved_features; 446 } 447 448 unsigned int VM_Version::calc_parallel_worker_threads() { 449 unsigned int result; 450 if (is_M_series()) { 451 // for now, use same gc thread calculation for M-series as for niagara-plus 452 // in future, we may want to tweak parameters for nof_parallel_worker_thread 453 result = nof_parallel_worker_threads(5, 16, 8); 454 } else if (is_niagara_plus()) { 455 result = nof_parallel_worker_threads(5, 16, 8); 456 } else { 457 result = nof_parallel_worker_threads(5, 8, 8); 458 } 459 return result; 460 }