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--- old/src/cpu/sparc/vm/vm_version_sparc.cpp
+++ new/src/cpu/sparc/vm/vm_version_sparc.cpp
1 1 /*
2 2 * Copyright (c) 1997, 2014, Oracle and/or its affiliates. All rights reserved.
3 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 4 *
5 5 * This code is free software; you can redistribute it and/or modify it
6 6 * under the terms of the GNU General Public License version 2 only, as
7 7 * published by the Free Software Foundation.
8 8 *
9 9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 12 * version 2 for more details (a copy is included in the LICENSE file that
13 13 * accompanied this code).
14 14 *
15 15 * You should have received a copy of the GNU General Public License version
16 16 * 2 along with this work; if not, write to the Free Software Foundation,
17 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 18 *
19 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 20 * or visit www.oracle.com if you need additional information or have any
21 21 * questions.
22 22 *
23 23 */
24 24
25 25 #include "precompiled.hpp"
26 26 #include "asm/macroAssembler.inline.hpp"
27 27 #include "memory/resourceArea.hpp"
28 28 #include "runtime/java.hpp"
29 29 #include "runtime/stubCodeGenerator.hpp"
30 30 #include "vm_version_sparc.hpp"
31 31 #ifdef TARGET_OS_FAMILY_linux
32 32 # include "os_linux.inline.hpp"
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33 33 #endif
34 34 #ifdef TARGET_OS_FAMILY_solaris
35 35 # include "os_solaris.inline.hpp"
36 36 #endif
37 37
38 38 int VM_Version::_features = VM_Version::unknown_m;
39 39 const char* VM_Version::_features_str = "";
40 40 unsigned int VM_Version::_L2_data_cache_line_size = 0;
41 41
42 42 void VM_Version::initialize() {
43 - _features = determine_features();
43 +
44 + assert(_features != VM_Version::unknown_m, "System pre-initialization is not complete.");
45 + guarantee(VM_Version::has_v9(), "only SPARC v9 is supported");
46 +
44 47 PrefetchCopyIntervalInBytes = prefetch_copy_interval_in_bytes();
45 48 PrefetchScanIntervalInBytes = prefetch_scan_interval_in_bytes();
46 49 PrefetchFieldsAhead = prefetch_fields_ahead();
47 50
48 51 assert(0 <= AllocatePrefetchInstr && AllocatePrefetchInstr <= 1, "invalid value");
49 52 if( AllocatePrefetchInstr < 0 ) AllocatePrefetchInstr = 0;
50 53 if( AllocatePrefetchInstr > 1 ) AllocatePrefetchInstr = 0;
51 54
52 55 // Allocation prefetch settings
53 56 intx cache_line_size = prefetch_data_size();
54 57 if( cache_line_size > AllocatePrefetchStepSize )
55 58 AllocatePrefetchStepSize = cache_line_size;
56 59
57 60 assert(AllocatePrefetchLines > 0, "invalid value");
58 61 if( AllocatePrefetchLines < 1 ) // set valid value in product VM
59 62 AllocatePrefetchLines = 3;
60 63 assert(AllocateInstancePrefetchLines > 0, "invalid value");
61 64 if( AllocateInstancePrefetchLines < 1 ) // set valid value in product VM
62 65 AllocateInstancePrefetchLines = 1;
63 66
64 67 AllocatePrefetchDistance = allocate_prefetch_distance();
65 68 AllocatePrefetchStyle = allocate_prefetch_style();
66 69
67 70 assert((AllocatePrefetchDistance % AllocatePrefetchStepSize) == 0 &&
68 71 (AllocatePrefetchDistance > 0), "invalid value");
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69 72 if ((AllocatePrefetchDistance % AllocatePrefetchStepSize) != 0 ||
70 73 (AllocatePrefetchDistance <= 0)) {
71 74 AllocatePrefetchDistance = AllocatePrefetchStepSize;
72 75 }
73 76
74 77 if (AllocatePrefetchStyle == 3 && !has_blk_init()) {
75 78 warning("BIS instructions are not available on this CPU");
76 79 FLAG_SET_DEFAULT(AllocatePrefetchStyle, 1);
77 80 }
78 81
79 - guarantee(VM_Version::has_v9(), "only SPARC v9 is supported");
80 -
81 82 assert(ArraycopySrcPrefetchDistance < 4096, "invalid value");
82 83 if (ArraycopySrcPrefetchDistance >= 4096)
83 84 ArraycopySrcPrefetchDistance = 4064;
84 85 assert(ArraycopyDstPrefetchDistance < 4096, "invalid value");
85 86 if (ArraycopyDstPrefetchDistance >= 4096)
86 87 ArraycopyDstPrefetchDistance = 4064;
87 88
88 89 UseSSE = 0; // Only on x86 and x64
89 90
90 91 _supports_cx8 = has_v9();
91 92 _supports_atomic_getset4 = true; // swap instruction
92 93
93 94 // There are Fujitsu Sparc64 CPUs which support blk_init as well so
94 95 // we have to take this check out of the 'is_niagara()' block below.
95 96 if (has_blk_init()) {
96 97 // When using CMS or G1, we cannot use memset() in BOT updates
97 98 // because the sun4v/CMT version in libc_psr uses BIS which
98 99 // exposes "phantom zeros" to concurrent readers. See 6948537.
99 100 if (FLAG_IS_DEFAULT(UseMemSetInBOT) && (UseConcMarkSweepGC || UseG1GC)) {
100 101 FLAG_SET_DEFAULT(UseMemSetInBOT, false);
101 102 }
102 103 // Issue a stern warning if the user has explicitly set
103 104 // UseMemSetInBOT (it is known to cause issues), but allow
104 105 // use for experimentation and debugging.
105 106 if (UseConcMarkSweepGC || UseG1GC) {
106 107 if (UseMemSetInBOT) {
107 108 assert(!FLAG_IS_DEFAULT(UseMemSetInBOT), "Error");
108 109 warning("Experimental flag -XX:+UseMemSetInBOT is known to cause instability"
109 110 " on sun4v; please understand that you are using at your own risk!");
110 111 }
111 112 }
112 113 }
113 114
114 115 if (is_niagara()) {
115 116 // Indirect branch is the same cost as direct
116 117 if (FLAG_IS_DEFAULT(UseInlineCaches)) {
117 118 FLAG_SET_DEFAULT(UseInlineCaches, false);
118 119 }
119 120 // Align loops on a single instruction boundary.
120 121 if (FLAG_IS_DEFAULT(OptoLoopAlignment)) {
121 122 FLAG_SET_DEFAULT(OptoLoopAlignment, 4);
122 123 }
123 124 #ifdef _LP64
124 125 // 32-bit oops don't make sense for the 64-bit VM on sparc
125 126 // since the 32-bit VM has the same registers and smaller objects.
126 127 Universe::set_narrow_oop_shift(LogMinObjAlignmentInBytes);
127 128 Universe::set_narrow_klass_shift(LogKlassAlignmentInBytes);
128 129 #endif // _LP64
129 130 #ifdef COMPILER2
130 131 // Indirect branch is the same cost as direct
131 132 if (FLAG_IS_DEFAULT(UseJumpTables)) {
132 133 FLAG_SET_DEFAULT(UseJumpTables, true);
133 134 }
134 135 // Single-issue, so entry and loop tops are
135 136 // aligned on a single instruction boundary
136 137 if (FLAG_IS_DEFAULT(InteriorEntryAlignment)) {
137 138 FLAG_SET_DEFAULT(InteriorEntryAlignment, 4);
138 139 }
139 140 if (is_niagara_plus()) {
140 141 if (has_blk_init() && UseTLAB &&
141 142 FLAG_IS_DEFAULT(AllocatePrefetchInstr)) {
142 143 // Use BIS instruction for TLAB allocation prefetch.
143 144 FLAG_SET_ERGO(intx, AllocatePrefetchInstr, 1);
144 145 if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) {
145 146 FLAG_SET_ERGO(intx, AllocatePrefetchStyle, 3);
146 147 }
147 148 if (FLAG_IS_DEFAULT(AllocatePrefetchDistance)) {
148 149 // Use smaller prefetch distance with BIS
149 150 FLAG_SET_DEFAULT(AllocatePrefetchDistance, 64);
150 151 }
151 152 }
152 153 if (is_T4()) {
153 154 // Double number of prefetched cache lines on T4
154 155 // since L2 cache line size is smaller (32 bytes).
155 156 if (FLAG_IS_DEFAULT(AllocatePrefetchLines)) {
156 157 FLAG_SET_ERGO(intx, AllocatePrefetchLines, AllocatePrefetchLines*2);
157 158 }
158 159 if (FLAG_IS_DEFAULT(AllocateInstancePrefetchLines)) {
159 160 FLAG_SET_ERGO(intx, AllocateInstancePrefetchLines, AllocateInstancePrefetchLines*2);
160 161 }
161 162 }
162 163 if (AllocatePrefetchStyle != 3 && FLAG_IS_DEFAULT(AllocatePrefetchDistance)) {
163 164 // Use different prefetch distance without BIS
164 165 FLAG_SET_DEFAULT(AllocatePrefetchDistance, 256);
165 166 }
166 167 if (AllocatePrefetchInstr == 1) {
167 168 // Need a space at the end of TLAB for BIS since it
168 169 // will fault when accessing memory outside of heap.
169 170
170 171 // +1 for rounding up to next cache line, +1 to be safe
171 172 int lines = AllocatePrefetchLines + 2;
172 173 int step_size = AllocatePrefetchStepSize;
173 174 int distance = AllocatePrefetchDistance;
174 175 _reserve_for_allocation_prefetch = (distance + step_size*lines)/(int)HeapWordSize;
175 176 }
176 177 }
177 178 #endif
178 179 }
179 180
180 181 // Use hardware population count instruction if available.
181 182 if (has_hardware_popc()) {
182 183 if (FLAG_IS_DEFAULT(UsePopCountInstruction)) {
183 184 FLAG_SET_DEFAULT(UsePopCountInstruction, true);
184 185 }
185 186 } else if (UsePopCountInstruction) {
186 187 warning("POPC instruction is not available on this CPU");
187 188 FLAG_SET_DEFAULT(UsePopCountInstruction, false);
188 189 }
189 190
190 191 // T4 and newer Sparc cpus have new compare and branch instruction.
191 192 if (has_cbcond()) {
192 193 if (FLAG_IS_DEFAULT(UseCBCond)) {
193 194 FLAG_SET_DEFAULT(UseCBCond, true);
194 195 }
195 196 } else if (UseCBCond) {
196 197 warning("CBCOND instruction is not available on this CPU");
197 198 FLAG_SET_DEFAULT(UseCBCond, false);
198 199 }
199 200
200 201 assert(BlockZeroingLowLimit > 0, "invalid value");
201 202 if (has_block_zeroing() && cache_line_size > 0) {
202 203 if (FLAG_IS_DEFAULT(UseBlockZeroing)) {
203 204 FLAG_SET_DEFAULT(UseBlockZeroing, true);
204 205 }
205 206 } else if (UseBlockZeroing) {
206 207 warning("BIS zeroing instructions are not available on this CPU");
207 208 FLAG_SET_DEFAULT(UseBlockZeroing, false);
208 209 }
209 210
210 211 assert(BlockCopyLowLimit > 0, "invalid value");
211 212 if (has_block_zeroing() && cache_line_size > 0) { // has_blk_init() && is_T4(): core's local L2 cache
212 213 if (FLAG_IS_DEFAULT(UseBlockCopy)) {
213 214 FLAG_SET_DEFAULT(UseBlockCopy, true);
214 215 }
215 216 } else if (UseBlockCopy) {
216 217 warning("BIS instructions are not available or expensive on this CPU");
217 218 FLAG_SET_DEFAULT(UseBlockCopy, false);
218 219 }
219 220
220 221 #ifdef COMPILER2
221 222 // T4 and newer Sparc cpus have fast RDPC.
222 223 if (has_fast_rdpc() && FLAG_IS_DEFAULT(UseRDPCForConstantTableBase)) {
223 224 FLAG_SET_DEFAULT(UseRDPCForConstantTableBase, true);
224 225 }
225 226
226 227 // Currently not supported anywhere.
227 228 FLAG_SET_DEFAULT(UseFPUForSpilling, false);
228 229
229 230 MaxVectorSize = 8;
230 231
231 232 assert((InteriorEntryAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size");
232 233 #endif
233 234
234 235 assert((CodeEntryAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size");
235 236 assert((OptoLoopAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size");
236 237
237 238 char buf[512];
238 239 jio_snprintf(buf, sizeof(buf), "%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
239 240 (has_v9() ? ", v9" : (has_v8() ? ", v8" : "")),
240 241 (has_hardware_popc() ? ", popc" : ""),
241 242 (has_vis1() ? ", vis1" : ""),
242 243 (has_vis2() ? ", vis2" : ""),
243 244 (has_vis3() ? ", vis3" : ""),
244 245 (has_blk_init() ? ", blk_init" : ""),
245 246 (has_cbcond() ? ", cbcond" : ""),
246 247 (has_aes() ? ", aes" : ""),
247 248 (has_sha1() ? ", sha1" : ""),
248 249 (has_sha256() ? ", sha256" : ""),
249 250 (has_sha512() ? ", sha512" : ""),
250 251 (is_ultra3() ? ", ultra3" : ""),
251 252 (is_sun4v() ? ", sun4v" : ""),
252 253 (is_niagara_plus() ? ", niagara_plus" : (is_niagara() ? ", niagara" : "")),
253 254 (is_sparc64() ? ", sparc64" : ""),
254 255 (!has_hardware_mul32() ? ", no-mul32" : ""),
255 256 (!has_hardware_div32() ? ", no-div32" : ""),
256 257 (!has_hardware_fsmuld() ? ", no-fsmuld" : ""));
257 258
258 259 // buf is started with ", " or is empty
259 260 _features_str = strdup(strlen(buf) > 2 ? buf + 2 : buf);
260 261
261 262 // UseVIS is set to the smallest of what hardware supports and what
262 263 // the command line requires. I.e., you cannot set UseVIS to 3 on
263 264 // older UltraSparc which do not support it.
264 265 if (UseVIS > 3) UseVIS=3;
265 266 if (UseVIS < 0) UseVIS=0;
266 267 if (!has_vis3()) // Drop to 2 if no VIS3 support
267 268 UseVIS = MIN2((intx)2,UseVIS);
268 269 if (!has_vis2()) // Drop to 1 if no VIS2 support
269 270 UseVIS = MIN2((intx)1,UseVIS);
270 271 if (!has_vis1()) // Drop to 0 if no VIS1 support
271 272 UseVIS = 0;
272 273
273 274 // SPARC T4 and above should have support for AES instructions
274 275 if (has_aes()) {
275 276 if (UseVIS > 2) { // AES intrinsics use MOVxTOd/MOVdTOx which are VIS3
276 277 if (FLAG_IS_DEFAULT(UseAES)) {
277 278 FLAG_SET_DEFAULT(UseAES, true);
278 279 }
279 280 if (FLAG_IS_DEFAULT(UseAESIntrinsics)) {
280 281 FLAG_SET_DEFAULT(UseAESIntrinsics, true);
281 282 }
282 283 // we disable both the AES flags if either of them is disabled on the command line
283 284 if (!UseAES || !UseAESIntrinsics) {
284 285 FLAG_SET_DEFAULT(UseAES, false);
285 286 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
286 287 }
287 288 } else {
288 289 if (UseAES || UseAESIntrinsics) {
289 290 warning("SPARC AES intrinsics require VIS3 instruction support. Intrinsics will be disabled.");
290 291 if (UseAES) {
291 292 FLAG_SET_DEFAULT(UseAES, false);
292 293 }
293 294 if (UseAESIntrinsics) {
294 295 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
295 296 }
296 297 }
297 298 }
298 299 } else if (UseAES || UseAESIntrinsics) {
299 300 warning("AES instructions are not available on this CPU");
300 301 if (UseAES) {
301 302 FLAG_SET_DEFAULT(UseAES, false);
302 303 }
303 304 if (UseAESIntrinsics) {
304 305 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
305 306 }
306 307 }
307 308
308 309 // SHA1, SHA256, and SHA512 instructions were added to SPARC T-series at different times
309 310 if (has_sha1() || has_sha256() || has_sha512()) {
310 311 if (UseVIS > 0) { // SHA intrinsics use VIS1 instructions
311 312 if (FLAG_IS_DEFAULT(UseSHA)) {
312 313 FLAG_SET_DEFAULT(UseSHA, true);
313 314 }
314 315 } else {
315 316 if (UseSHA) {
316 317 warning("SPARC SHA intrinsics require VIS1 instruction support. Intrinsics will be disabled.");
317 318 FLAG_SET_DEFAULT(UseSHA, false);
318 319 }
319 320 }
320 321 } else if (UseSHA) {
321 322 warning("SHA instructions are not available on this CPU");
322 323 FLAG_SET_DEFAULT(UseSHA, false);
323 324 }
324 325
325 326 if (!UseSHA) {
326 327 FLAG_SET_DEFAULT(UseSHA1Intrinsics, false);
327 328 FLAG_SET_DEFAULT(UseSHA256Intrinsics, false);
328 329 FLAG_SET_DEFAULT(UseSHA512Intrinsics, false);
329 330 } else {
330 331 if (has_sha1()) {
331 332 if (FLAG_IS_DEFAULT(UseSHA1Intrinsics)) {
332 333 FLAG_SET_DEFAULT(UseSHA1Intrinsics, true);
333 334 }
334 335 } else if (UseSHA1Intrinsics) {
335 336 warning("SHA1 instruction is not available on this CPU.");
336 337 FLAG_SET_DEFAULT(UseSHA1Intrinsics, false);
337 338 }
338 339 if (has_sha256()) {
339 340 if (FLAG_IS_DEFAULT(UseSHA256Intrinsics)) {
340 341 FLAG_SET_DEFAULT(UseSHA256Intrinsics, true);
341 342 }
342 343 } else if (UseSHA256Intrinsics) {
343 344 warning("SHA256 instruction (for SHA-224 and SHA-256) is not available on this CPU.");
344 345 FLAG_SET_DEFAULT(UseSHA256Intrinsics, false);
345 346 }
346 347
347 348 if (has_sha512()) {
348 349 if (FLAG_IS_DEFAULT(UseSHA512Intrinsics)) {
349 350 FLAG_SET_DEFAULT(UseSHA512Intrinsics, true);
350 351 }
351 352 } else if (UseSHA512Intrinsics) {
352 353 warning("SHA512 instruction (for SHA-384 and SHA-512) is not available on this CPU.");
353 354 FLAG_SET_DEFAULT(UseSHA512Intrinsics, false);
354 355 }
355 356 if (!(UseSHA1Intrinsics || UseSHA256Intrinsics || UseSHA512Intrinsics)) {
356 357 FLAG_SET_DEFAULT(UseSHA, false);
357 358 }
358 359 }
359 360
360 361 if (FLAG_IS_DEFAULT(ContendedPaddingWidth) &&
361 362 (cache_line_size > ContendedPaddingWidth))
362 363 ContendedPaddingWidth = cache_line_size;
363 364
364 365 #ifndef PRODUCT
365 366 if (PrintMiscellaneous && Verbose) {
366 367 tty->print_cr("L2 data cache line size: %u", L2_data_cache_line_size());
367 368 tty->print("Allocation");
368 369 if (AllocatePrefetchStyle <= 0) {
369 370 tty->print_cr(": no prefetching");
370 371 } else {
371 372 tty->print(" prefetching: ");
372 373 if (AllocatePrefetchInstr == 0) {
373 374 tty->print("PREFETCH");
374 375 } else if (AllocatePrefetchInstr == 1) {
375 376 tty->print("BIS");
376 377 }
377 378 if (AllocatePrefetchLines > 1) {
378 379 tty->print_cr(" at distance %d, %d lines of %d bytes", (int) AllocatePrefetchDistance, (int) AllocatePrefetchLines, (int) AllocatePrefetchStepSize);
379 380 } else {
380 381 tty->print_cr(" at distance %d, one line of %d bytes", (int) AllocatePrefetchDistance, (int) AllocatePrefetchStepSize);
381 382 }
382 383 }
383 384 if (PrefetchCopyIntervalInBytes > 0) {
384 385 tty->print_cr("PrefetchCopyIntervalInBytes %d", (int) PrefetchCopyIntervalInBytes);
385 386 }
386 387 if (PrefetchScanIntervalInBytes > 0) {
387 388 tty->print_cr("PrefetchScanIntervalInBytes %d", (int) PrefetchScanIntervalInBytes);
388 389 }
389 390 if (PrefetchFieldsAhead > 0) {
390 391 tty->print_cr("PrefetchFieldsAhead %d", (int) PrefetchFieldsAhead);
391 392 }
392 393 if (ContendedPaddingWidth > 0) {
393 394 tty->print_cr("ContendedPaddingWidth %d", (int) ContendedPaddingWidth);
394 395 }
395 396 }
396 397 #endif // PRODUCT
397 398 }
398 399
399 400 void VM_Version::print_features() {
400 401 tty->print_cr("Version:%s", cpu_features());
401 402 }
402 403
403 404 int VM_Version::determine_features() {
404 405 if (UseV8InstrsOnly) {
405 406 NOT_PRODUCT(if (PrintMiscellaneous && Verbose) tty->print_cr("Version is Forced-V8");)
406 407 return generic_v8_m;
407 408 }
408 409
409 410 int features = platform_features(unknown_m); // platform_features() is os_arch specific
410 411
411 412 if (features == unknown_m) {
412 413 features = generic_v9_m;
413 414 warning("Cannot recognize SPARC version. Default to V9");
414 415 }
415 416
416 417 assert(is_T_family(features) == is_niagara(features), "Niagara should be T series");
417 418 if (UseNiagaraInstrs) { // Force code generation for Niagara
418 419 if (is_T_family(features)) {
419 420 // Happy to accomodate...
420 421 } else {
421 422 NOT_PRODUCT(if (PrintMiscellaneous && Verbose) tty->print_cr("Version is Forced-Niagara");)
422 423 features |= T_family_m;
423 424 }
424 425 } else {
425 426 if (is_T_family(features) && !FLAG_IS_DEFAULT(UseNiagaraInstrs)) {
426 427 NOT_PRODUCT(if (PrintMiscellaneous && Verbose) tty->print_cr("Version is Forced-Not-Niagara");)
427 428 features &= ~(T_family_m | T1_model_m);
428 429 } else {
429 430 // Happy to accomodate...
430 431 }
431 432 }
432 433
433 434 return features;
434 435 }
435 436
436 437 static int saved_features = 0;
437 438
438 439 void VM_Version::allow_all() {
439 440 saved_features = _features;
440 441 _features = all_features_m;
441 442 }
442 443
443 444 void VM_Version::revert() {
444 445 _features = saved_features;
445 446 }
446 447
447 448 unsigned int VM_Version::calc_parallel_worker_threads() {
448 449 unsigned int result;
449 450 if (is_M_series()) {
450 451 // for now, use same gc thread calculation for M-series as for niagara-plus
451 452 // in future, we may want to tweak parameters for nof_parallel_worker_thread
452 453 result = nof_parallel_worker_threads(5, 16, 8);
453 454 } else if (is_niagara_plus()) {
454 455 result = nof_parallel_worker_threads(5, 16, 8);
455 456 } else {
456 457 result = nof_parallel_worker_threads(5, 8, 8);
457 458 }
458 459 return result;
459 460 }
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