diff a/src/hotspot/cpu/aarch64/aarch64.ad b/src/hotspot/cpu/aarch64/aarch64.ad --- a/src/hotspot/cpu/aarch64/aarch64.ad +++ b/src/hotspot/cpu/aarch64/aarch64.ad @@ -18349,39 +18349,10 @@ as_FloatRegister($src2$$reg)); %} ins_pipe(vmul128); %} -instruct vmul8B(vecD dst, vecD src1, vecD src2) -%{ - predicate(n->as_Vector()->length() == 4 || - n->as_Vector()->length() == 8); - match(Set dst (MulVB src1 src2)); - ins_cost(INSN_COST); - format %{ "mulv $dst,$src1,$src2\t# vector (8B)" %} - ins_encode %{ - __ mulv(as_FloatRegister($dst$$reg), __ T8B, - as_FloatRegister($src1$$reg), - as_FloatRegister($src2$$reg)); - %} - ins_pipe(vmul64); -%} - -instruct vmul16B(vecX dst, vecX src1, vecX src2) -%{ - predicate(n->as_Vector()->length() == 16); - match(Set dst (MulVB src1 src2)); - ins_cost(INSN_COST); - format %{ "mulv $dst,$src1,$src2\t# vector (16B)" %} - ins_encode %{ - __ mulv(as_FloatRegister($dst$$reg), __ T16B, - as_FloatRegister($src1$$reg), - as_FloatRegister($src2$$reg)); - %} - ins_pipe(vmul128); -%} - instruct vmul4S(vecD dst, vecD src1, vecD src2) %{ predicate(n->as_Vector()->length() == 2 || n->as_Vector()->length() == 4); match(Set dst (MulVS src1 src2)); @@ -18814,32 +18785,10 @@ as_FloatRegister($src$$reg)); %} ins_pipe(vsqrt_fp128); %} -instruct vsqrt2F(vecD dst, vecD src) -%{ - predicate(n->as_Vector()->length() == 2); - match(Set dst (SqrtVF src)); - format %{ "fsqrt $dst, $src\t# vector (2F)" %} - ins_encode %{ - __ fsqrt(as_FloatRegister($dst$$reg), __ T2S, as_FloatRegister($src$$reg)); - %} - ins_pipe(vunop_fp64); -%} - -instruct vsqrt4F(vecX dst, vecX src) -%{ - predicate(n->as_Vector()->length() == 4); - match(Set dst (SqrtVF src)); - format %{ "fsqrt $dst, $src\t# vector (4S)" %} - ins_encode %{ - __ fsqrt(as_FloatRegister($dst$$reg), __ T4S, as_FloatRegister($src$$reg)); - %} - ins_pipe(vsqrt_fp128); -%} - // --------------------------------- ABS -------------------------------------- instruct vabs8B(vecD dst, vecD src) %{ predicate(n->as_Vector()->length() == 8);