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src/hotspot/cpu/aarch64/aarch64.ad

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18334             as_FloatRegister($src1$$reg),
18335             as_FloatRegister($src2$$reg));
18336   %}
18337   ins_pipe(vmul64);
18338 %}
18339 
18340 instruct vmul16B(vecX dst, vecX src1, vecX src2)
18341 %{
18342   predicate(n->as_Vector()->length() == 16);
18343   match(Set dst (MulVB src1 src2));
18344   ins_cost(INSN_COST);
18345   format %{ "mulv  $dst,$src1,$src2\t# vector (16B)" %}
18346   ins_encode %{
18347     __ mulv(as_FloatRegister($dst$$reg), __ T16B,
18348             as_FloatRegister($src1$$reg),
18349             as_FloatRegister($src2$$reg));
18350   %}
18351   ins_pipe(vmul128);
18352 %}
18353 
18354 instruct vmul8B(vecD dst, vecD src1, vecD src2)
18355 %{
18356   predicate(n->as_Vector()->length() == 4 ||
18357             n->as_Vector()->length() == 8);
18358   match(Set dst (MulVB src1 src2));
18359   ins_cost(INSN_COST);
18360   format %{ "mulv  $dst,$src1,$src2\t# vector (8B)" %}
18361   ins_encode %{
18362     __ mulv(as_FloatRegister($dst$$reg), __ T8B,
18363             as_FloatRegister($src1$$reg),
18364             as_FloatRegister($src2$$reg));
18365   %}
18366   ins_pipe(vmul64);
18367 %}
18368 
18369 instruct vmul16B(vecX dst, vecX src1, vecX src2)
18370 %{
18371   predicate(n->as_Vector()->length() == 16);
18372   match(Set dst (MulVB src1 src2));
18373   ins_cost(INSN_COST);
18374   format %{ "mulv  $dst,$src1,$src2\t# vector (16B)" %}
18375   ins_encode %{
18376     __ mulv(as_FloatRegister($dst$$reg), __ T16B,
18377             as_FloatRegister($src1$$reg),
18378             as_FloatRegister($src2$$reg));
18379   %}
18380   ins_pipe(vmul128);
18381 %}
18382 
18383 instruct vmul4S(vecD dst, vecD src1, vecD src2)
18384 %{
18385   predicate(n->as_Vector()->length() == 2 ||
18386             n->as_Vector()->length() == 4);
18387   match(Set dst (MulVS src1 src2));
18388   ins_cost(INSN_COST);
18389   format %{ "mulv  $dst,$src1,$src2\t# vector (4H)" %}
18390   ins_encode %{
18391     __ mulv(as_FloatRegister($dst$$reg), __ T4H,
18392             as_FloatRegister($src1$$reg),
18393             as_FloatRegister($src2$$reg));
18394   %}
18395   ins_pipe(vmul64);
18396 %}
18397 
18398 instruct vmul8S(vecX dst, vecX src1, vecX src2)
18399 %{
18400   predicate(n->as_Vector()->length() == 8);
18401   match(Set dst (MulVS src1 src2));
18402   ins_cost(INSN_COST);

18799   match(Set dst (SqrtVF src));
18800   format %{ "fsqrt  $dst, $src\t# vector (4F)" %}
18801   ins_encode %{
18802     __ fsqrt(as_FloatRegister($dst$$reg), __ T4S, as_FloatRegister($src$$reg));
18803   %}
18804   ins_pipe(vsqrt_fp128);
18805 %}
18806 
18807 instruct vsqrt2D(vecX dst, vecX src)
18808 %{
18809   predicate(n->as_Vector()->length() == 2);
18810   match(Set dst (SqrtVD src));
18811   format %{ "fsqrt  $dst, $src\t# vector (2D)" %}
18812   ins_encode %{
18813     __ fsqrt(as_FloatRegister($dst$$reg), __ T2D,
18814              as_FloatRegister($src$$reg));
18815   %}
18816   ins_pipe(vsqrt_fp128);
18817 %}
18818 
18819 instruct vsqrt2F(vecD dst, vecD src)
18820 %{
18821   predicate(n->as_Vector()->length() == 2);
18822   match(Set dst (SqrtVF src));
18823   format %{ "fsqrt  $dst, $src\t# vector (2F)" %}
18824   ins_encode %{
18825     __ fsqrt(as_FloatRegister($dst$$reg), __ T2S, as_FloatRegister($src$$reg));
18826   %}
18827   ins_pipe(vunop_fp64);
18828 %}
18829 
18830 instruct vsqrt4F(vecX dst, vecX src)
18831 %{
18832   predicate(n->as_Vector()->length() == 4);
18833   match(Set dst (SqrtVF src));
18834   format %{ "fsqrt  $dst, $src\t# vector (4S)" %}
18835   ins_encode %{
18836     __ fsqrt(as_FloatRegister($dst$$reg), __ T4S, as_FloatRegister($src$$reg));
18837   %}
18838   ins_pipe(vsqrt_fp128);
18839 %}
18840 
18841 // --------------------------------- ABS --------------------------------------
18842 
18843 instruct vabs8B(vecD dst, vecD src)
18844 %{
18845   predicate(n->as_Vector()->length() == 8);
18846   match(Set dst (AbsVB src));
18847   ins_cost(INSN_COST);
18848   format %{ "abs  $dst,$src\t# vector (8B)" %}
18849   ins_encode %{
18850     __ absr(as_FloatRegister($dst$$reg), __ T8B, as_FloatRegister($src$$reg));
18851   %}
18852   ins_pipe(vlogical64);
18853 %}
18854 
18855 instruct vabs16B(vecX dst, vecX src)
18856 %{
18857   predicate(n->as_Vector()->length() == 16);
18858   match(Set dst (AbsVB src));
18859   ins_cost(INSN_COST);
18860   format %{ "abs  $dst,$src\t# vector (16B)" %}

18334             as_FloatRegister($src1$$reg),
18335             as_FloatRegister($src2$$reg));
18336   %}
18337   ins_pipe(vmul64);
18338 %}
18339 
18340 instruct vmul16B(vecX dst, vecX src1, vecX src2)
18341 %{
18342   predicate(n->as_Vector()->length() == 16);
18343   match(Set dst (MulVB src1 src2));
18344   ins_cost(INSN_COST);
18345   format %{ "mulv  $dst,$src1,$src2\t# vector (16B)" %}
18346   ins_encode %{
18347     __ mulv(as_FloatRegister($dst$$reg), __ T16B,
18348             as_FloatRegister($src1$$reg),
18349             as_FloatRegister($src2$$reg));
18350   %}
18351   ins_pipe(vmul128);
18352 %}
18353 





























18354 instruct vmul4S(vecD dst, vecD src1, vecD src2)
18355 %{
18356   predicate(n->as_Vector()->length() == 2 ||
18357             n->as_Vector()->length() == 4);
18358   match(Set dst (MulVS src1 src2));
18359   ins_cost(INSN_COST);
18360   format %{ "mulv  $dst,$src1,$src2\t# vector (4H)" %}
18361   ins_encode %{
18362     __ mulv(as_FloatRegister($dst$$reg), __ T4H,
18363             as_FloatRegister($src1$$reg),
18364             as_FloatRegister($src2$$reg));
18365   %}
18366   ins_pipe(vmul64);
18367 %}
18368 
18369 instruct vmul8S(vecX dst, vecX src1, vecX src2)
18370 %{
18371   predicate(n->as_Vector()->length() == 8);
18372   match(Set dst (MulVS src1 src2));
18373   ins_cost(INSN_COST);

18770   match(Set dst (SqrtVF src));
18771   format %{ "fsqrt  $dst, $src\t# vector (4F)" %}
18772   ins_encode %{
18773     __ fsqrt(as_FloatRegister($dst$$reg), __ T4S, as_FloatRegister($src$$reg));
18774   %}
18775   ins_pipe(vsqrt_fp128);
18776 %}
18777 
18778 instruct vsqrt2D(vecX dst, vecX src)
18779 %{
18780   predicate(n->as_Vector()->length() == 2);
18781   match(Set dst (SqrtVD src));
18782   format %{ "fsqrt  $dst, $src\t# vector (2D)" %}
18783   ins_encode %{
18784     __ fsqrt(as_FloatRegister($dst$$reg), __ T2D,
18785              as_FloatRegister($src$$reg));
18786   %}
18787   ins_pipe(vsqrt_fp128);
18788 %}
18789 






















18790 // --------------------------------- ABS --------------------------------------
18791 
18792 instruct vabs8B(vecD dst, vecD src)
18793 %{
18794   predicate(n->as_Vector()->length() == 8);
18795   match(Set dst (AbsVB src));
18796   ins_cost(INSN_COST);
18797   format %{ "abs  $dst,$src\t# vector (8B)" %}
18798   ins_encode %{
18799     __ absr(as_FloatRegister($dst$$reg), __ T8B, as_FloatRegister($src$$reg));
18800   %}
18801   ins_pipe(vlogical64);
18802 %}
18803 
18804 instruct vabs16B(vecX dst, vecX src)
18805 %{
18806   predicate(n->as_Vector()->length() == 16);
18807   match(Set dst (AbsVB src));
18808   ins_cost(INSN_COST);
18809   format %{ "abs  $dst,$src\t# vector (16B)" %}
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