739 uint input_edge_start =1; // Skip control most nodes
740 bool is_machine_node = false;
741 if (n->is_Mach()) {
742 is_machine_node = true;
743 input_edge_start = n->as_Mach()->oper_input_base();
744 }
745 uint idx = n->is_Copy();
746
747 // Get virtual register number, same as LiveRanGe index
748 uint vreg = _lrg_map.live_range_id(n);
749 LRG& lrg = lrgs(vreg);
750 if (vreg) { // No vreg means un-allocable (e.g. memory)
751
752 // Check for float-vs-int live range (used in register-pressure
753 // calculations)
754 const Type *n_type = n->bottom_type();
755 if (n_type->is_floatingpoint()) {
756 lrg._is_float = 1;
757 }
758
759 #ifndef PRODUCT
760 // Collect bits not used by product code, but which may be useful for
761 // debugging.
762
763 // Collect has-copy bit
764 if (idx) {
765 lrg._has_copy = 1;
766 uint clidx = _lrg_map.live_range_id(n->in(idx));
767 LRG& copy_src = lrgs(clidx);
768 copy_src._has_copy = 1;
769 }
770
771 // Check for twice prior spilling. Once prior spilling might have
772 // spilled 'soft', 2nd prior spill should have spilled 'hard' and
773 // further spilling is unlikely to make progress.
774 if (_spilled_once.test(n->_idx)) {
775 lrg._was_spilled1 = 1;
776 if (_spilled_twice.test(n->_idx)) {
777 lrg._was_spilled2 = 1;
778 }
779 }
780
781 if (trace_spilling() && lrg._def != NULL) {
782 // collect defs for MultiDef printing
783 if (lrg._defs == NULL) {
784 lrg._defs = new (_ifg->_arena) GrowableArray<Node*>(_ifg->_arena, 2, 0, NULL);
785 lrg._defs->append(lrg._def);
786 }
787 lrg._defs->append(n);
788 }
789 #endif
790
791 // Check for a single def LRG; these can spill nicely
792 // via rematerialization. Flag as NULL for no def found
793 // yet, or 'n' for single def or -1 for many defs.
794 lrg._def = lrg._def ? NodeSentinel : n;
795
796 // Limit result register mask to acceptable registers
797 const RegMask &rm = n->out_RegMask();
798 lrg.AND( rm );
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739 uint input_edge_start =1; // Skip control most nodes
740 bool is_machine_node = false;
741 if (n->is_Mach()) {
742 is_machine_node = true;
743 input_edge_start = n->as_Mach()->oper_input_base();
744 }
745 uint idx = n->is_Copy();
746
747 // Get virtual register number, same as LiveRanGe index
748 uint vreg = _lrg_map.live_range_id(n);
749 LRG& lrg = lrgs(vreg);
750 if (vreg) { // No vreg means un-allocable (e.g. memory)
751
752 // Check for float-vs-int live range (used in register-pressure
753 // calculations)
754 const Type *n_type = n->bottom_type();
755 if (n_type->is_floatingpoint()) {
756 lrg._is_float = 1;
757 }
758
759 // Check for twice prior spilling. Once prior spilling might have
760 // spilled 'soft', 2nd prior spill should have spilled 'hard' and
761 // further spilling is unlikely to make progress.
762 if (_spilled_once.test(n->_idx)) {
763 lrg._was_spilled1 = 1;
764 if (_spilled_twice.test(n->_idx)) {
765 lrg._was_spilled2 = 1;
766 }
767 }
768
769 #ifndef PRODUCT
770 // Collect bits not used by product code, but which may be useful for
771 // debugging.
772
773 // Collect has-copy bit
774 if (idx) {
775 lrg._has_copy = 1;
776 uint clidx = _lrg_map.live_range_id(n->in(idx));
777 LRG& copy_src = lrgs(clidx);
778 copy_src._has_copy = 1;
779 }
780
781 if (trace_spilling() && lrg._def != NULL) {
782 // collect defs for MultiDef printing
783 if (lrg._defs == NULL) {
784 lrg._defs = new (_ifg->_arena) GrowableArray<Node*>(_ifg->_arena, 2, 0, NULL);
785 lrg._defs->append(lrg._def);
786 }
787 lrg._defs->append(n);
788 }
789 #endif
790
791 // Check for a single def LRG; these can spill nicely
792 // via rematerialization. Flag as NULL for no def found
793 // yet, or 'n' for single def or -1 for many defs.
794 lrg._def = lrg._def ? NodeSentinel : n;
795
796 // Limit result register mask to acceptable registers
797 const RegMask &rm = n->out_RegMask();
798 lrg.AND( rm );
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