1 /*
   2  * Copyright (c) 1997, 2016, Oracle and/or its affiliates. All rights reserved.
   3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   4  *
   5  * This code is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 only, as
   7  * published by the Free Software Foundation.
   8  *
   9  * This code is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * version 2 for more details (a copy is included in the LICENSE file that
  13  * accompanied this code).
  14  *
  15  * You should have received a copy of the GNU General Public License version
  16  * 2 along with this work; if not, write to the Free Software Foundation,
  17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  18  *
  19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  20  * or visit www.oracle.com if you need additional information or have any
  21  * questions.
  22  *
  23  */
  24 
  25 #include "precompiled.hpp"
  26 #include "asm/assembler.hpp"
  27 #include "asm/assembler.inline.hpp"
  28 #include "compiler/disassembler.hpp"
  29 #include "gc/shared/cardTableModRefBS.hpp"
  30 #include "gc/shared/collectedHeap.inline.hpp"
  31 #include "interpreter/interpreter.hpp"
  32 #include "memory/resourceArea.hpp"
  33 #include "memory/universe.hpp"
  34 #include "oops/klass.inline.hpp"
  35 #include "prims/methodHandles.hpp"
  36 #include "runtime/biasedLocking.hpp"
  37 #include "runtime/interfaceSupport.hpp"
  38 #include "runtime/objectMonitor.hpp"
  39 #include "runtime/os.hpp"
  40 #include "runtime/sharedRuntime.hpp"
  41 #include "runtime/stubRoutines.hpp"
  42 #include "runtime/thread.hpp"
  43 #include "utilities/macros.hpp"
  44 #if INCLUDE_ALL_GCS
  45 #include "gc/g1/g1CollectedHeap.inline.hpp"
  46 #include "gc/g1/g1SATBCardTableModRefBS.hpp"
  47 #include "gc/g1/heapRegion.hpp"
  48 #endif // INCLUDE_ALL_GCS
  49 #include "crc32c.h"
  50 #ifdef COMPILER2
  51 #include "opto/intrinsicnode.hpp"
  52 #endif
  53 
  54 #ifdef PRODUCT
  55 #define BLOCK_COMMENT(str) /* nothing */
  56 #define STOP(error) stop(error)
  57 #else
  58 #define BLOCK_COMMENT(str) block_comment(str)
  59 #define STOP(error) block_comment(error); stop(error)
  60 #endif
  61 
  62 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
  63 
  64 #ifdef ASSERT
  65 bool AbstractAssembler::pd_check_instruction_mark() { return true; }
  66 #endif
  67 
  68 static Assembler::Condition reverse[] = {
  69     Assembler::noOverflow     /* overflow      = 0x0 */ ,
  70     Assembler::overflow       /* noOverflow    = 0x1 */ ,
  71     Assembler::aboveEqual     /* carrySet      = 0x2, below         = 0x2 */ ,
  72     Assembler::below          /* aboveEqual    = 0x3, carryClear    = 0x3 */ ,
  73     Assembler::notZero        /* zero          = 0x4, equal         = 0x4 */ ,
  74     Assembler::zero           /* notZero       = 0x5, notEqual      = 0x5 */ ,
  75     Assembler::above          /* belowEqual    = 0x6 */ ,
  76     Assembler::belowEqual     /* above         = 0x7 */ ,
  77     Assembler::positive       /* negative      = 0x8 */ ,
  78     Assembler::negative       /* positive      = 0x9 */ ,
  79     Assembler::noParity       /* parity        = 0xa */ ,
  80     Assembler::parity         /* noParity      = 0xb */ ,
  81     Assembler::greaterEqual   /* less          = 0xc */ ,
  82     Assembler::less           /* greaterEqual  = 0xd */ ,
  83     Assembler::greater        /* lessEqual     = 0xe */ ,
  84     Assembler::lessEqual      /* greater       = 0xf, */
  85 
  86 };
  87 
  88 
  89 // Implementation of MacroAssembler
  90 
  91 // First all the versions that have distinct versions depending on 32/64 bit
  92 // Unless the difference is trivial (1 line or so).
  93 
  94 #ifndef _LP64
  95 
  96 // 32bit versions
  97 
  98 Address MacroAssembler::as_Address(AddressLiteral adr) {
  99   return Address(adr.target(), adr.rspec());
 100 }
 101 
 102 Address MacroAssembler::as_Address(ArrayAddress adr) {
 103   return Address::make_array(adr);
 104 }
 105 
 106 void MacroAssembler::call_VM_leaf_base(address entry_point,
 107                                        int number_of_arguments) {
 108   call(RuntimeAddress(entry_point));
 109   increment(rsp, number_of_arguments * wordSize);
 110 }
 111 
 112 void MacroAssembler::cmpklass(Address src1, Metadata* obj) {
 113   cmp_literal32(src1, (int32_t)obj, metadata_Relocation::spec_for_immediate());
 114 }
 115 
 116 void MacroAssembler::cmpklass(Register src1, Metadata* obj) {
 117   cmp_literal32(src1, (int32_t)obj, metadata_Relocation::spec_for_immediate());
 118 }
 119 
 120 void MacroAssembler::cmpoop(Address src1, jobject obj) {
 121   cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate());
 122 }
 123 
 124 void MacroAssembler::cmpoop(Register src1, jobject obj) {
 125   cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate());
 126 }
 127 
 128 void MacroAssembler::extend_sign(Register hi, Register lo) {
 129   // According to Intel Doc. AP-526, "Integer Divide", p.18.
 130   if (VM_Version::is_P6() && hi == rdx && lo == rax) {
 131     cdql();
 132   } else {
 133     movl(hi, lo);
 134     sarl(hi, 31);
 135   }
 136 }
 137 
 138 void MacroAssembler::jC2(Register tmp, Label& L) {
 139   // set parity bit if FPU flag C2 is set (via rax)
 140   save_rax(tmp);
 141   fwait(); fnstsw_ax();
 142   sahf();
 143   restore_rax(tmp);
 144   // branch
 145   jcc(Assembler::parity, L);
 146 }
 147 
 148 void MacroAssembler::jnC2(Register tmp, Label& L) {
 149   // set parity bit if FPU flag C2 is set (via rax)
 150   save_rax(tmp);
 151   fwait(); fnstsw_ax();
 152   sahf();
 153   restore_rax(tmp);
 154   // branch
 155   jcc(Assembler::noParity, L);
 156 }
 157 
 158 // 32bit can do a case table jump in one instruction but we no longer allow the base
 159 // to be installed in the Address class
 160 void MacroAssembler::jump(ArrayAddress entry) {
 161   jmp(as_Address(entry));
 162 }
 163 
 164 // Note: y_lo will be destroyed
 165 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) {
 166   // Long compare for Java (semantics as described in JVM spec.)
 167   Label high, low, done;
 168 
 169   cmpl(x_hi, y_hi);
 170   jcc(Assembler::less, low);
 171   jcc(Assembler::greater, high);
 172   // x_hi is the return register
 173   xorl(x_hi, x_hi);
 174   cmpl(x_lo, y_lo);
 175   jcc(Assembler::below, low);
 176   jcc(Assembler::equal, done);
 177 
 178   bind(high);
 179   xorl(x_hi, x_hi);
 180   increment(x_hi);
 181   jmp(done);
 182 
 183   bind(low);
 184   xorl(x_hi, x_hi);
 185   decrementl(x_hi);
 186 
 187   bind(done);
 188 }
 189 
 190 void MacroAssembler::lea(Register dst, AddressLiteral src) {
 191     mov_literal32(dst, (int32_t)src.target(), src.rspec());
 192 }
 193 
 194 void MacroAssembler::lea(Address dst, AddressLiteral adr) {
 195   // leal(dst, as_Address(adr));
 196   // see note in movl as to why we must use a move
 197   mov_literal32(dst, (int32_t) adr.target(), adr.rspec());
 198 }
 199 
 200 void MacroAssembler::leave() {
 201   mov(rsp, rbp);
 202   pop(rbp);
 203 }
 204 
 205 void MacroAssembler::lmul(int x_rsp_offset, int y_rsp_offset) {
 206   // Multiplication of two Java long values stored on the stack
 207   // as illustrated below. Result is in rdx:rax.
 208   //
 209   // rsp ---> [  ??  ] \               \
 210   //            ....    | y_rsp_offset  |
 211   //          [ y_lo ] /  (in bytes)    | x_rsp_offset
 212   //          [ y_hi ]                  | (in bytes)
 213   //            ....                    |
 214   //          [ x_lo ]                 /
 215   //          [ x_hi ]
 216   //            ....
 217   //
 218   // Basic idea: lo(result) = lo(x_lo * y_lo)
 219   //             hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
 220   Address x_hi(rsp, x_rsp_offset + wordSize); Address x_lo(rsp, x_rsp_offset);
 221   Address y_hi(rsp, y_rsp_offset + wordSize); Address y_lo(rsp, y_rsp_offset);
 222   Label quick;
 223   // load x_hi, y_hi and check if quick
 224   // multiplication is possible
 225   movl(rbx, x_hi);
 226   movl(rcx, y_hi);
 227   movl(rax, rbx);
 228   orl(rbx, rcx);                                 // rbx, = 0 <=> x_hi = 0 and y_hi = 0
 229   jcc(Assembler::zero, quick);                   // if rbx, = 0 do quick multiply
 230   // do full multiplication
 231   // 1st step
 232   mull(y_lo);                                    // x_hi * y_lo
 233   movl(rbx, rax);                                // save lo(x_hi * y_lo) in rbx,
 234   // 2nd step
 235   movl(rax, x_lo);
 236   mull(rcx);                                     // x_lo * y_hi
 237   addl(rbx, rax);                                // add lo(x_lo * y_hi) to rbx,
 238   // 3rd step
 239   bind(quick);                                   // note: rbx, = 0 if quick multiply!
 240   movl(rax, x_lo);
 241   mull(y_lo);                                    // x_lo * y_lo
 242   addl(rdx, rbx);                                // correct hi(x_lo * y_lo)
 243 }
 244 
 245 void MacroAssembler::lneg(Register hi, Register lo) {
 246   negl(lo);
 247   adcl(hi, 0);
 248   negl(hi);
 249 }
 250 
 251 void MacroAssembler::lshl(Register hi, Register lo) {
 252   // Java shift left long support (semantics as described in JVM spec., p.305)
 253   // (basic idea for shift counts s >= n: x << s == (x << n) << (s - n))
 254   // shift value is in rcx !
 255   assert(hi != rcx, "must not use rcx");
 256   assert(lo != rcx, "must not use rcx");
 257   const Register s = rcx;                        // shift count
 258   const int      n = BitsPerWord;
 259   Label L;
 260   andl(s, 0x3f);                                 // s := s & 0x3f (s < 0x40)
 261   cmpl(s, n);                                    // if (s < n)
 262   jcc(Assembler::less, L);                       // else (s >= n)
 263   movl(hi, lo);                                  // x := x << n
 264   xorl(lo, lo);
 265   // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n!
 266   bind(L);                                       // s (mod n) < n
 267   shldl(hi, lo);                                 // x := x << s
 268   shll(lo);
 269 }
 270 
 271 
 272 void MacroAssembler::lshr(Register hi, Register lo, bool sign_extension) {
 273   // Java shift right long support (semantics as described in JVM spec., p.306 & p.310)
 274   // (basic idea for shift counts s >= n: x >> s == (x >> n) >> (s - n))
 275   assert(hi != rcx, "must not use rcx");
 276   assert(lo != rcx, "must not use rcx");
 277   const Register s = rcx;                        // shift count
 278   const int      n = BitsPerWord;
 279   Label L;
 280   andl(s, 0x3f);                                 // s := s & 0x3f (s < 0x40)
 281   cmpl(s, n);                                    // if (s < n)
 282   jcc(Assembler::less, L);                       // else (s >= n)
 283   movl(lo, hi);                                  // x := x >> n
 284   if (sign_extension) sarl(hi, 31);
 285   else                xorl(hi, hi);
 286   // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n!
 287   bind(L);                                       // s (mod n) < n
 288   shrdl(lo, hi);                                 // x := x >> s
 289   if (sign_extension) sarl(hi);
 290   else                shrl(hi);
 291 }
 292 
 293 void MacroAssembler::movoop(Register dst, jobject obj) {
 294   mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate());
 295 }
 296 
 297 void MacroAssembler::movoop(Address dst, jobject obj) {
 298   mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate());
 299 }
 300 
 301 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) {
 302   mov_literal32(dst, (int32_t)obj, metadata_Relocation::spec_for_immediate());
 303 }
 304 
 305 void MacroAssembler::mov_metadata(Address dst, Metadata* obj) {
 306   mov_literal32(dst, (int32_t)obj, metadata_Relocation::spec_for_immediate());
 307 }
 308 
 309 void MacroAssembler::movptr(Register dst, AddressLiteral src, Register scratch) {
 310   // scratch register is not used,
 311   // it is defined to match parameters of 64-bit version of this method.
 312   if (src.is_lval()) {
 313     mov_literal32(dst, (intptr_t)src.target(), src.rspec());
 314   } else {
 315     movl(dst, as_Address(src));
 316   }
 317 }
 318 
 319 void MacroAssembler::movptr(ArrayAddress dst, Register src) {
 320   movl(as_Address(dst), src);
 321 }
 322 
 323 void MacroAssembler::movptr(Register dst, ArrayAddress src) {
 324   movl(dst, as_Address(src));
 325 }
 326 
 327 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
 328 void MacroAssembler::movptr(Address dst, intptr_t src) {
 329   movl(dst, src);
 330 }
 331 
 332 
 333 void MacroAssembler::pop_callee_saved_registers() {
 334   pop(rcx);
 335   pop(rdx);
 336   pop(rdi);
 337   pop(rsi);
 338 }
 339 
 340 void MacroAssembler::pop_fTOS() {
 341   fld_d(Address(rsp, 0));
 342   addl(rsp, 2 * wordSize);
 343 }
 344 
 345 void MacroAssembler::push_callee_saved_registers() {
 346   push(rsi);
 347   push(rdi);
 348   push(rdx);
 349   push(rcx);
 350 }
 351 
 352 void MacroAssembler::push_fTOS() {
 353   subl(rsp, 2 * wordSize);
 354   fstp_d(Address(rsp, 0));
 355 }
 356 
 357 
 358 void MacroAssembler::pushoop(jobject obj) {
 359   push_literal32((int32_t)obj, oop_Relocation::spec_for_immediate());
 360 }
 361 
 362 void MacroAssembler::pushklass(Metadata* obj) {
 363   push_literal32((int32_t)obj, metadata_Relocation::spec_for_immediate());
 364 }
 365 
 366 void MacroAssembler::pushptr(AddressLiteral src) {
 367   if (src.is_lval()) {
 368     push_literal32((int32_t)src.target(), src.rspec());
 369   } else {
 370     pushl(as_Address(src));
 371   }
 372 }
 373 
 374 void MacroAssembler::set_word_if_not_zero(Register dst) {
 375   xorl(dst, dst);
 376   set_byte_if_not_zero(dst);
 377 }
 378 
 379 static void pass_arg0(MacroAssembler* masm, Register arg) {
 380   masm->push(arg);
 381 }
 382 
 383 static void pass_arg1(MacroAssembler* masm, Register arg) {
 384   masm->push(arg);
 385 }
 386 
 387 static void pass_arg2(MacroAssembler* masm, Register arg) {
 388   masm->push(arg);
 389 }
 390 
 391 static void pass_arg3(MacroAssembler* masm, Register arg) {
 392   masm->push(arg);
 393 }
 394 
 395 #ifndef PRODUCT
 396 extern "C" void findpc(intptr_t x);
 397 #endif
 398 
 399 void MacroAssembler::debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg) {
 400   // In order to get locks to work, we need to fake a in_VM state
 401   JavaThread* thread = JavaThread::current();
 402   JavaThreadState saved_state = thread->thread_state();
 403   thread->set_thread_state(_thread_in_vm);
 404   if (ShowMessageBoxOnError) {
 405     JavaThread* thread = JavaThread::current();
 406     JavaThreadState saved_state = thread->thread_state();
 407     thread->set_thread_state(_thread_in_vm);
 408     if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
 409       ttyLocker ttyl;
 410       BytecodeCounter::print();
 411     }
 412     // To see where a verify_oop failed, get $ebx+40/X for this frame.
 413     // This is the value of eip which points to where verify_oop will return.
 414     if (os::message_box(msg, "Execution stopped, print registers?")) {
 415       print_state32(rdi, rsi, rbp, rsp, rbx, rdx, rcx, rax, eip);
 416       BREAKPOINT;
 417     }
 418   } else {
 419     ttyLocker ttyl;
 420     ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n", msg);
 421   }
 422   // Don't assert holding the ttyLock
 423     assert(false, "DEBUG MESSAGE: %s", msg);
 424   ThreadStateTransition::transition(thread, _thread_in_vm, saved_state);
 425 }
 426 
 427 void MacroAssembler::print_state32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip) {
 428   ttyLocker ttyl;
 429   FlagSetting fs(Debugging, true);
 430   tty->print_cr("eip = 0x%08x", eip);
 431 #ifndef PRODUCT
 432   if ((WizardMode || Verbose) && PrintMiscellaneous) {
 433     tty->cr();
 434     findpc(eip);
 435     tty->cr();
 436   }
 437 #endif
 438 #define PRINT_REG(rax) \
 439   { tty->print("%s = ", #rax); os::print_location(tty, rax); }
 440   PRINT_REG(rax);
 441   PRINT_REG(rbx);
 442   PRINT_REG(rcx);
 443   PRINT_REG(rdx);
 444   PRINT_REG(rdi);
 445   PRINT_REG(rsi);
 446   PRINT_REG(rbp);
 447   PRINT_REG(rsp);
 448 #undef PRINT_REG
 449   // Print some words near top of staack.
 450   int* dump_sp = (int*) rsp;
 451   for (int col1 = 0; col1 < 8; col1++) {
 452     tty->print("(rsp+0x%03x) 0x%08x: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
 453     os::print_location(tty, *dump_sp++);
 454   }
 455   for (int row = 0; row < 16; row++) {
 456     tty->print("(rsp+0x%03x) 0x%08x: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
 457     for (int col = 0; col < 8; col++) {
 458       tty->print(" 0x%08x", *dump_sp++);
 459     }
 460     tty->cr();
 461   }
 462   // Print some instructions around pc:
 463   Disassembler::decode((address)eip-64, (address)eip);
 464   tty->print_cr("--------");
 465   Disassembler::decode((address)eip, (address)eip+32);
 466 }
 467 
 468 void MacroAssembler::stop(const char* msg) {
 469   ExternalAddress message((address)msg);
 470   // push address of message
 471   pushptr(message.addr());
 472   { Label L; call(L, relocInfo::none); bind(L); }     // push eip
 473   pusha();                                            // push registers
 474   call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug32)));
 475   hlt();
 476 }
 477 
 478 void MacroAssembler::warn(const char* msg) {
 479   push_CPU_state();
 480 
 481   ExternalAddress message((address) msg);
 482   // push address of message
 483   pushptr(message.addr());
 484 
 485   call(RuntimeAddress(CAST_FROM_FN_PTR(address, warning)));
 486   addl(rsp, wordSize);       // discard argument
 487   pop_CPU_state();
 488 }
 489 
 490 void MacroAssembler::print_state() {
 491   { Label L; call(L, relocInfo::none); bind(L); }     // push eip
 492   pusha();                                            // push registers
 493 
 494   push_CPU_state();
 495   call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::print_state32)));
 496   pop_CPU_state();
 497 
 498   popa();
 499   addl(rsp, wordSize);
 500 }
 501 
 502 #else // _LP64
 503 
 504 // 64 bit versions
 505 
 506 Address MacroAssembler::as_Address(AddressLiteral adr) {
 507   // amd64 always does this as a pc-rel
 508   // we can be absolute or disp based on the instruction type
 509   // jmp/call are displacements others are absolute
 510   assert(!adr.is_lval(), "must be rval");
 511   assert(reachable(adr), "must be");
 512   return Address((int32_t)(intptr_t)(adr.target() - pc()), adr.target(), adr.reloc());
 513 
 514 }
 515 
 516 Address MacroAssembler::as_Address(ArrayAddress adr) {
 517   AddressLiteral base = adr.base();
 518   lea(rscratch1, base);
 519   Address index = adr.index();
 520   assert(index._disp == 0, "must not have disp"); // maybe it can?
 521   Address array(rscratch1, index._index, index._scale, index._disp);
 522   return array;
 523 }
 524 
 525 void MacroAssembler::call_VM_leaf_base(address entry_point, int num_args) {
 526   Label L, E;
 527 
 528 #ifdef _WIN64
 529   // Windows always allocates space for it's register args
 530   assert(num_args <= 4, "only register arguments supported");
 531   subq(rsp,  frame::arg_reg_save_area_bytes);
 532 #endif
 533 
 534   // Align stack if necessary
 535   testl(rsp, 15);
 536   jcc(Assembler::zero, L);
 537 
 538   subq(rsp, 8);
 539   {
 540     call(RuntimeAddress(entry_point));
 541   }
 542   addq(rsp, 8);
 543   jmp(E);
 544 
 545   bind(L);
 546   {
 547     call(RuntimeAddress(entry_point));
 548   }
 549 
 550   bind(E);
 551 
 552 #ifdef _WIN64
 553   // restore stack pointer
 554   addq(rsp, frame::arg_reg_save_area_bytes);
 555 #endif
 556 
 557 }
 558 
 559 void MacroAssembler::cmp64(Register src1, AddressLiteral src2) {
 560   assert(!src2.is_lval(), "should use cmpptr");
 561 
 562   if (reachable(src2)) {
 563     cmpq(src1, as_Address(src2));
 564   } else {
 565     lea(rscratch1, src2);
 566     Assembler::cmpq(src1, Address(rscratch1, 0));
 567   }
 568 }
 569 
 570 int MacroAssembler::corrected_idivq(Register reg) {
 571   // Full implementation of Java ldiv and lrem; checks for special
 572   // case as described in JVM spec., p.243 & p.271.  The function
 573   // returns the (pc) offset of the idivl instruction - may be needed
 574   // for implicit exceptions.
 575   //
 576   //         normal case                           special case
 577   //
 578   // input : rax: dividend                         min_long
 579   //         reg: divisor   (may not be eax/edx)   -1
 580   //
 581   // output: rax: quotient  (= rax idiv reg)       min_long
 582   //         rdx: remainder (= rax irem reg)       0
 583   assert(reg != rax && reg != rdx, "reg cannot be rax or rdx register");
 584   static const int64_t min_long = 0x8000000000000000;
 585   Label normal_case, special_case;
 586 
 587   // check for special case
 588   cmp64(rax, ExternalAddress((address) &min_long));
 589   jcc(Assembler::notEqual, normal_case);
 590   xorl(rdx, rdx); // prepare rdx for possible special case (where
 591                   // remainder = 0)
 592   cmpq(reg, -1);
 593   jcc(Assembler::equal, special_case);
 594 
 595   // handle normal case
 596   bind(normal_case);
 597   cdqq();
 598   int idivq_offset = offset();
 599   idivq(reg);
 600 
 601   // normal and special case exit
 602   bind(special_case);
 603 
 604   return idivq_offset;
 605 }
 606 
 607 void MacroAssembler::decrementq(Register reg, int value) {
 608   if (value == min_jint) { subq(reg, value); return; }
 609   if (value <  0) { incrementq(reg, -value); return; }
 610   if (value == 0) {                        ; return; }
 611   if (value == 1 && UseIncDec) { decq(reg) ; return; }
 612   /* else */      { subq(reg, value)       ; return; }
 613 }
 614 
 615 void MacroAssembler::decrementq(Address dst, int value) {
 616   if (value == min_jint) { subq(dst, value); return; }
 617   if (value <  0) { incrementq(dst, -value); return; }
 618   if (value == 0) {                        ; return; }
 619   if (value == 1 && UseIncDec) { decq(dst) ; return; }
 620   /* else */      { subq(dst, value)       ; return; }
 621 }
 622 
 623 void MacroAssembler::incrementq(AddressLiteral dst) {
 624   if (reachable(dst)) {
 625     incrementq(as_Address(dst));
 626   } else {
 627     lea(rscratch1, dst);
 628     incrementq(Address(rscratch1, 0));
 629   }
 630 }
 631 
 632 void MacroAssembler::incrementq(Register reg, int value) {
 633   if (value == min_jint) { addq(reg, value); return; }
 634   if (value <  0) { decrementq(reg, -value); return; }
 635   if (value == 0) {                        ; return; }
 636   if (value == 1 && UseIncDec) { incq(reg) ; return; }
 637   /* else */      { addq(reg, value)       ; return; }
 638 }
 639 
 640 void MacroAssembler::incrementq(Address dst, int value) {
 641   if (value == min_jint) { addq(dst, value); return; }
 642   if (value <  0) { decrementq(dst, -value); return; }
 643   if (value == 0) {                        ; return; }
 644   if (value == 1 && UseIncDec) { incq(dst) ; return; }
 645   /* else */      { addq(dst, value)       ; return; }
 646 }
 647 
 648 // 32bit can do a case table jump in one instruction but we no longer allow the base
 649 // to be installed in the Address class
 650 void MacroAssembler::jump(ArrayAddress entry) {
 651   lea(rscratch1, entry.base());
 652   Address dispatch = entry.index();
 653   assert(dispatch._base == noreg, "must be");
 654   dispatch._base = rscratch1;
 655   jmp(dispatch);
 656 }
 657 
 658 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) {
 659   ShouldNotReachHere(); // 64bit doesn't use two regs
 660   cmpq(x_lo, y_lo);
 661 }
 662 
 663 void MacroAssembler::lea(Register dst, AddressLiteral src) {
 664     mov_literal64(dst, (intptr_t)src.target(), src.rspec());
 665 }
 666 
 667 void MacroAssembler::lea(Address dst, AddressLiteral adr) {
 668   mov_literal64(rscratch1, (intptr_t)adr.target(), adr.rspec());
 669   movptr(dst, rscratch1);
 670 }
 671 
 672 void MacroAssembler::leave() {
 673   // %%% is this really better? Why not on 32bit too?
 674   emit_int8((unsigned char)0xC9); // LEAVE
 675 }
 676 
 677 void MacroAssembler::lneg(Register hi, Register lo) {
 678   ShouldNotReachHere(); // 64bit doesn't use two regs
 679   negq(lo);
 680 }
 681 
 682 void MacroAssembler::movoop(Register dst, jobject obj) {
 683   mov_literal64(dst, (intptr_t)obj, oop_Relocation::spec_for_immediate());
 684 }
 685 
 686 void MacroAssembler::movoop(Address dst, jobject obj) {
 687   mov_literal64(rscratch1, (intptr_t)obj, oop_Relocation::spec_for_immediate());
 688   movq(dst, rscratch1);
 689 }
 690 
 691 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) {
 692   mov_literal64(dst, (intptr_t)obj, metadata_Relocation::spec_for_immediate());
 693 }
 694 
 695 void MacroAssembler::mov_metadata(Address dst, Metadata* obj) {
 696   mov_literal64(rscratch1, (intptr_t)obj, metadata_Relocation::spec_for_immediate());
 697   movq(dst, rscratch1);
 698 }
 699 
 700 void MacroAssembler::movptr(Register dst, AddressLiteral src, Register scratch) {
 701   if (src.is_lval()) {
 702     mov_literal64(dst, (intptr_t)src.target(), src.rspec());
 703   } else {
 704     if (reachable(src)) {
 705       movq(dst, as_Address(src));
 706     } else {
 707       lea(scratch, src);
 708       movq(dst, Address(scratch, 0));
 709     }
 710   }
 711 }
 712 
 713 void MacroAssembler::movptr(ArrayAddress dst, Register src) {
 714   movq(as_Address(dst), src);
 715 }
 716 
 717 void MacroAssembler::movptr(Register dst, ArrayAddress src) {
 718   movq(dst, as_Address(src));
 719 }
 720 
 721 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
 722 void MacroAssembler::movptr(Address dst, intptr_t src) {
 723   mov64(rscratch1, src);
 724   movq(dst, rscratch1);
 725 }
 726 
 727 // These are mostly for initializing NULL
 728 void MacroAssembler::movptr(Address dst, int32_t src) {
 729   movslq(dst, src);
 730 }
 731 
 732 void MacroAssembler::movptr(Register dst, int32_t src) {
 733   mov64(dst, (intptr_t)src);
 734 }
 735 
 736 void MacroAssembler::pushoop(jobject obj) {
 737   movoop(rscratch1, obj);
 738   push(rscratch1);
 739 }
 740 
 741 void MacroAssembler::pushklass(Metadata* obj) {
 742   mov_metadata(rscratch1, obj);
 743   push(rscratch1);
 744 }
 745 
 746 void MacroAssembler::pushptr(AddressLiteral src) {
 747   lea(rscratch1, src);
 748   if (src.is_lval()) {
 749     push(rscratch1);
 750   } else {
 751     pushq(Address(rscratch1, 0));
 752   }
 753 }
 754 
 755 void MacroAssembler::reset_last_Java_frame(bool clear_fp) {
 756   // we must set sp to zero to clear frame
 757   movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), NULL_WORD);
 758   // must clear fp, so that compiled frames are not confused; it is
 759   // possible that we need it only for debugging
 760   if (clear_fp) {
 761     movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()), NULL_WORD);
 762   }
 763 
 764   // Always clear the pc because it could have been set by make_walkable()
 765   movptr(Address(r15_thread, JavaThread::last_Java_pc_offset()), NULL_WORD);
 766 }
 767 
 768 void MacroAssembler::set_last_Java_frame(Register last_java_sp,
 769                                          Register last_java_fp,
 770                                          address  last_java_pc) {
 771   // determine last_java_sp register
 772   if (!last_java_sp->is_valid()) {
 773     last_java_sp = rsp;
 774   }
 775 
 776   // last_java_fp is optional
 777   if (last_java_fp->is_valid()) {
 778     movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()),
 779            last_java_fp);
 780   }
 781 
 782   // last_java_pc is optional
 783   if (last_java_pc != NULL) {
 784     Address java_pc(r15_thread,
 785                     JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset());
 786     lea(rscratch1, InternalAddress(last_java_pc));
 787     movptr(java_pc, rscratch1);
 788   }
 789 
 790   movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), last_java_sp);
 791 }
 792 
 793 static void pass_arg0(MacroAssembler* masm, Register arg) {
 794   if (c_rarg0 != arg ) {
 795     masm->mov(c_rarg0, arg);
 796   }
 797 }
 798 
 799 static void pass_arg1(MacroAssembler* masm, Register arg) {
 800   if (c_rarg1 != arg ) {
 801     masm->mov(c_rarg1, arg);
 802   }
 803 }
 804 
 805 static void pass_arg2(MacroAssembler* masm, Register arg) {
 806   if (c_rarg2 != arg ) {
 807     masm->mov(c_rarg2, arg);
 808   }
 809 }
 810 
 811 static void pass_arg3(MacroAssembler* masm, Register arg) {
 812   if (c_rarg3 != arg ) {
 813     masm->mov(c_rarg3, arg);
 814   }
 815 }
 816 
 817 void MacroAssembler::stop(const char* msg) {
 818   address rip = pc();
 819   pusha(); // get regs on stack
 820   lea(c_rarg0, ExternalAddress((address) msg));
 821   lea(c_rarg1, InternalAddress(rip));
 822   movq(c_rarg2, rsp); // pass pointer to regs array
 823   andq(rsp, -16); // align stack as required by ABI
 824   call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug64)));
 825   hlt();
 826 }
 827 
 828 void MacroAssembler::warn(const char* msg) {
 829   push(rbp);
 830   movq(rbp, rsp);
 831   andq(rsp, -16);     // align stack as required by push_CPU_state and call
 832   push_CPU_state();   // keeps alignment at 16 bytes
 833   lea(c_rarg0, ExternalAddress((address) msg));
 834   call_VM_leaf(CAST_FROM_FN_PTR(address, warning), c_rarg0);
 835   pop_CPU_state();
 836   mov(rsp, rbp);
 837   pop(rbp);
 838 }
 839 
 840 void MacroAssembler::print_state() {
 841   address rip = pc();
 842   pusha();            // get regs on stack
 843   push(rbp);
 844   movq(rbp, rsp);
 845   andq(rsp, -16);     // align stack as required by push_CPU_state and call
 846   push_CPU_state();   // keeps alignment at 16 bytes
 847 
 848   lea(c_rarg0, InternalAddress(rip));
 849   lea(c_rarg1, Address(rbp, wordSize)); // pass pointer to regs array
 850   call_VM_leaf(CAST_FROM_FN_PTR(address, MacroAssembler::print_state64), c_rarg0, c_rarg1);
 851 
 852   pop_CPU_state();
 853   mov(rsp, rbp);
 854   pop(rbp);
 855   popa();
 856 }
 857 
 858 #ifndef PRODUCT
 859 extern "C" void findpc(intptr_t x);
 860 #endif
 861 
 862 void MacroAssembler::debug64(char* msg, int64_t pc, int64_t regs[]) {
 863   // In order to get locks to work, we need to fake a in_VM state
 864   if (ShowMessageBoxOnError) {
 865     JavaThread* thread = JavaThread::current();
 866     JavaThreadState saved_state = thread->thread_state();
 867     thread->set_thread_state(_thread_in_vm);
 868 #ifndef PRODUCT
 869     if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
 870       ttyLocker ttyl;
 871       BytecodeCounter::print();
 872     }
 873 #endif
 874     // To see where a verify_oop failed, get $ebx+40/X for this frame.
 875     // XXX correct this offset for amd64
 876     // This is the value of eip which points to where verify_oop will return.
 877     if (os::message_box(msg, "Execution stopped, print registers?")) {
 878       print_state64(pc, regs);
 879       BREAKPOINT;
 880       assert(false, "start up GDB");
 881     }
 882     ThreadStateTransition::transition(thread, _thread_in_vm, saved_state);
 883   } else {
 884     ttyLocker ttyl;
 885     ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n",
 886                     msg);
 887     assert(false, "DEBUG MESSAGE: %s", msg);
 888   }
 889 }
 890 
 891 void MacroAssembler::print_state64(int64_t pc, int64_t regs[]) {
 892   ttyLocker ttyl;
 893   FlagSetting fs(Debugging, true);
 894   tty->print_cr("rip = 0x%016lx", pc);
 895 #ifndef PRODUCT
 896   tty->cr();
 897   findpc(pc);
 898   tty->cr();
 899 #endif
 900 #define PRINT_REG(rax, value) \
 901   { tty->print("%s = ", #rax); os::print_location(tty, value); }
 902   PRINT_REG(rax, regs[15]);
 903   PRINT_REG(rbx, regs[12]);
 904   PRINT_REG(rcx, regs[14]);
 905   PRINT_REG(rdx, regs[13]);
 906   PRINT_REG(rdi, regs[8]);
 907   PRINT_REG(rsi, regs[9]);
 908   PRINT_REG(rbp, regs[10]);
 909   PRINT_REG(rsp, regs[11]);
 910   PRINT_REG(r8 , regs[7]);
 911   PRINT_REG(r9 , regs[6]);
 912   PRINT_REG(r10, regs[5]);
 913   PRINT_REG(r11, regs[4]);
 914   PRINT_REG(r12, regs[3]);
 915   PRINT_REG(r13, regs[2]);
 916   PRINT_REG(r14, regs[1]);
 917   PRINT_REG(r15, regs[0]);
 918 #undef PRINT_REG
 919   // Print some words near top of staack.
 920   int64_t* rsp = (int64_t*) regs[11];
 921   int64_t* dump_sp = rsp;
 922   for (int col1 = 0; col1 < 8; col1++) {
 923     tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (int64_t)dump_sp);
 924     os::print_location(tty, *dump_sp++);
 925   }
 926   for (int row = 0; row < 25; row++) {
 927     tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (int64_t)dump_sp);
 928     for (int col = 0; col < 4; col++) {
 929       tty->print(" 0x%016lx", *dump_sp++);
 930     }
 931     tty->cr();
 932   }
 933   // Print some instructions around pc:
 934   Disassembler::decode((address)pc-64, (address)pc);
 935   tty->print_cr("--------");
 936   Disassembler::decode((address)pc, (address)pc+32);
 937 }
 938 
 939 #endif // _LP64
 940 
 941 // Now versions that are common to 32/64 bit
 942 
 943 void MacroAssembler::addptr(Register dst, int32_t imm32) {
 944   LP64_ONLY(addq(dst, imm32)) NOT_LP64(addl(dst, imm32));
 945 }
 946 
 947 void MacroAssembler::addptr(Register dst, Register src) {
 948   LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src));
 949 }
 950 
 951 void MacroAssembler::addptr(Address dst, Register src) {
 952   LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src));
 953 }
 954 
 955 void MacroAssembler::addsd(XMMRegister dst, AddressLiteral src) {
 956   if (reachable(src)) {
 957     Assembler::addsd(dst, as_Address(src));
 958   } else {
 959     lea(rscratch1, src);
 960     Assembler::addsd(dst, Address(rscratch1, 0));
 961   }
 962 }
 963 
 964 void MacroAssembler::addss(XMMRegister dst, AddressLiteral src) {
 965   if (reachable(src)) {
 966     addss(dst, as_Address(src));
 967   } else {
 968     lea(rscratch1, src);
 969     addss(dst, Address(rscratch1, 0));
 970   }
 971 }
 972 
 973 void MacroAssembler::addpd(XMMRegister dst, AddressLiteral src) {
 974   if (reachable(src)) {
 975     Assembler::addpd(dst, as_Address(src));
 976   } else {
 977     lea(rscratch1, src);
 978     Assembler::addpd(dst, Address(rscratch1, 0));
 979   }
 980 }
 981 
 982 void MacroAssembler::align(int modulus) {
 983   align(modulus, offset());
 984 }
 985 
 986 void MacroAssembler::align(int modulus, int target) {
 987   if (target % modulus != 0) {
 988     nop(modulus - (target % modulus));
 989   }
 990 }
 991 
 992 void MacroAssembler::andpd(XMMRegister dst, AddressLiteral src) {
 993   // Used in sign-masking with aligned address.
 994   assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
 995   if (reachable(src)) {
 996     Assembler::andpd(dst, as_Address(src));
 997   } else {
 998     lea(rscratch1, src);
 999     Assembler::andpd(dst, Address(rscratch1, 0));
1000   }
1001 }
1002 
1003 void MacroAssembler::andps(XMMRegister dst, AddressLiteral src) {
1004   // Used in sign-masking with aligned address.
1005   assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
1006   if (reachable(src)) {
1007     Assembler::andps(dst, as_Address(src));
1008   } else {
1009     lea(rscratch1, src);
1010     Assembler::andps(dst, Address(rscratch1, 0));
1011   }
1012 }
1013 
1014 void MacroAssembler::andptr(Register dst, int32_t imm32) {
1015   LP64_ONLY(andq(dst, imm32)) NOT_LP64(andl(dst, imm32));
1016 }
1017 
1018 void MacroAssembler::atomic_incl(Address counter_addr) {
1019   if (os::is_MP())
1020     lock();
1021   incrementl(counter_addr);
1022 }
1023 
1024 void MacroAssembler::atomic_incl(AddressLiteral counter_addr, Register scr) {
1025   if (reachable(counter_addr)) {
1026     atomic_incl(as_Address(counter_addr));
1027   } else {
1028     lea(scr, counter_addr);
1029     atomic_incl(Address(scr, 0));
1030   }
1031 }
1032 
1033 #ifdef _LP64
1034 void MacroAssembler::atomic_incq(Address counter_addr) {
1035   if (os::is_MP())
1036     lock();
1037   incrementq(counter_addr);
1038 }
1039 
1040 void MacroAssembler::atomic_incq(AddressLiteral counter_addr, Register scr) {
1041   if (reachable(counter_addr)) {
1042     atomic_incq(as_Address(counter_addr));
1043   } else {
1044     lea(scr, counter_addr);
1045     atomic_incq(Address(scr, 0));
1046   }
1047 }
1048 #endif
1049 
1050 // Writes to stack successive pages until offset reached to check for
1051 // stack overflow + shadow pages.  This clobbers tmp.
1052 void MacroAssembler::bang_stack_size(Register size, Register tmp) {
1053   movptr(tmp, rsp);
1054   // Bang stack for total size given plus shadow page size.
1055   // Bang one page at a time because large size can bang beyond yellow and
1056   // red zones.
1057   Label loop;
1058   bind(loop);
1059   movl(Address(tmp, (-os::vm_page_size())), size );
1060   subptr(tmp, os::vm_page_size());
1061   subl(size, os::vm_page_size());
1062   jcc(Assembler::greater, loop);
1063 
1064   // Bang down shadow pages too.
1065   // At this point, (tmp-0) is the last address touched, so don't
1066   // touch it again.  (It was touched as (tmp-pagesize) but then tmp
1067   // was post-decremented.)  Skip this address by starting at i=1, and
1068   // touch a few more pages below.  N.B.  It is important to touch all
1069   // the way down including all pages in the shadow zone.
1070   for (int i = 1; i < ((int)JavaThread::stack_shadow_zone_size() / os::vm_page_size()); i++) {
1071     // this could be any sized move but this is can be a debugging crumb
1072     // so the bigger the better.
1073     movptr(Address(tmp, (-i*os::vm_page_size())), size );
1074   }
1075 }
1076 
1077 void MacroAssembler::reserved_stack_check() {
1078     // testing if reserved zone needs to be enabled
1079     Label no_reserved_zone_enabling;
1080     Register thread = NOT_LP64(rsi) LP64_ONLY(r15_thread);
1081     NOT_LP64(get_thread(rsi);)
1082 
1083     cmpptr(rsp, Address(thread, JavaThread::reserved_stack_activation_offset()));
1084     jcc(Assembler::below, no_reserved_zone_enabling);
1085 
1086     call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::enable_stack_reserved_zone), thread);
1087     jump(RuntimeAddress(StubRoutines::throw_delayed_StackOverflowError_entry()));
1088     should_not_reach_here();
1089 
1090     bind(no_reserved_zone_enabling);
1091 }
1092 
1093 int MacroAssembler::biased_locking_enter(Register lock_reg,
1094                                          Register obj_reg,
1095                                          Register swap_reg,
1096                                          Register tmp_reg,
1097                                          bool swap_reg_contains_mark,
1098                                          Label& done,
1099                                          Label* slow_case,
1100                                          BiasedLockingCounters* counters) {
1101   assert(UseBiasedLocking, "why call this otherwise?");
1102   assert(swap_reg == rax, "swap_reg must be rax for cmpxchgq");
1103   assert(tmp_reg != noreg, "tmp_reg must be supplied");
1104   assert_different_registers(lock_reg, obj_reg, swap_reg, tmp_reg);
1105   assert(markOopDesc::age_shift == markOopDesc::lock_bits + markOopDesc::biased_lock_bits, "biased locking makes assumptions about bit layout");
1106   Address mark_addr      (obj_reg, oopDesc::mark_offset_in_bytes());
1107   NOT_LP64( Address saved_mark_addr(lock_reg, 0); )
1108 
1109   if (PrintBiasedLockingStatistics && counters == NULL) {
1110     counters = BiasedLocking::counters();
1111   }
1112   // Biased locking
1113   // See whether the lock is currently biased toward our thread and
1114   // whether the epoch is still valid
1115   // Note that the runtime guarantees sufficient alignment of JavaThread
1116   // pointers to allow age to be placed into low bits
1117   // First check to see whether biasing is even enabled for this object
1118   Label cas_label;
1119   int null_check_offset = -1;
1120   if (!swap_reg_contains_mark) {
1121     null_check_offset = offset();
1122     movptr(swap_reg, mark_addr);
1123   }
1124   movptr(tmp_reg, swap_reg);
1125   andptr(tmp_reg, markOopDesc::biased_lock_mask_in_place);
1126   cmpptr(tmp_reg, markOopDesc::biased_lock_pattern);
1127   jcc(Assembler::notEqual, cas_label);
1128   // The bias pattern is present in the object's header. Need to check
1129   // whether the bias owner and the epoch are both still current.
1130 #ifndef _LP64
1131   // Note that because there is no current thread register on x86_32 we
1132   // need to store off the mark word we read out of the object to
1133   // avoid reloading it and needing to recheck invariants below. This
1134   // store is unfortunate but it makes the overall code shorter and
1135   // simpler.
1136   movptr(saved_mark_addr, swap_reg);
1137 #endif
1138   if (swap_reg_contains_mark) {
1139     null_check_offset = offset();
1140   }
1141   load_prototype_header(tmp_reg, obj_reg);
1142 #ifdef _LP64
1143   orptr(tmp_reg, r15_thread);
1144   xorptr(tmp_reg, swap_reg);
1145   Register header_reg = tmp_reg;
1146 #else
1147   xorptr(tmp_reg, swap_reg);
1148   get_thread(swap_reg);
1149   xorptr(swap_reg, tmp_reg);
1150   Register header_reg = swap_reg;
1151 #endif
1152   andptr(header_reg, ~((int) markOopDesc::age_mask_in_place));
1153   if (counters != NULL) {
1154     cond_inc32(Assembler::zero,
1155                ExternalAddress((address) counters->biased_lock_entry_count_addr()));
1156   }
1157   jcc(Assembler::equal, done);
1158 
1159   Label try_revoke_bias;
1160   Label try_rebias;
1161 
1162   // At this point we know that the header has the bias pattern and
1163   // that we are not the bias owner in the current epoch. We need to
1164   // figure out more details about the state of the header in order to
1165   // know what operations can be legally performed on the object's
1166   // header.
1167 
1168   // If the low three bits in the xor result aren't clear, that means
1169   // the prototype header is no longer biased and we have to revoke
1170   // the bias on this object.
1171   testptr(header_reg, markOopDesc::biased_lock_mask_in_place);
1172   jccb(Assembler::notZero, try_revoke_bias);
1173 
1174   // Biasing is still enabled for this data type. See whether the
1175   // epoch of the current bias is still valid, meaning that the epoch
1176   // bits of the mark word are equal to the epoch bits of the
1177   // prototype header. (Note that the prototype header's epoch bits
1178   // only change at a safepoint.) If not, attempt to rebias the object
1179   // toward the current thread. Note that we must be absolutely sure
1180   // that the current epoch is invalid in order to do this because
1181   // otherwise the manipulations it performs on the mark word are
1182   // illegal.
1183   testptr(header_reg, markOopDesc::epoch_mask_in_place);
1184   jccb(Assembler::notZero, try_rebias);
1185 
1186   // The epoch of the current bias is still valid but we know nothing
1187   // about the owner; it might be set or it might be clear. Try to
1188   // acquire the bias of the object using an atomic operation. If this
1189   // fails we will go in to the runtime to revoke the object's bias.
1190   // Note that we first construct the presumed unbiased header so we
1191   // don't accidentally blow away another thread's valid bias.
1192   NOT_LP64( movptr(swap_reg, saved_mark_addr); )
1193   andptr(swap_reg,
1194          markOopDesc::biased_lock_mask_in_place | markOopDesc::age_mask_in_place | markOopDesc::epoch_mask_in_place);
1195 #ifdef _LP64
1196   movptr(tmp_reg, swap_reg);
1197   orptr(tmp_reg, r15_thread);
1198 #else
1199   get_thread(tmp_reg);
1200   orptr(tmp_reg, swap_reg);
1201 #endif
1202   if (os::is_MP()) {
1203     lock();
1204   }
1205   cmpxchgptr(tmp_reg, mark_addr); // compare tmp_reg and swap_reg
1206   // If the biasing toward our thread failed, this means that
1207   // another thread succeeded in biasing it toward itself and we
1208   // need to revoke that bias. The revocation will occur in the
1209   // interpreter runtime in the slow case.
1210   if (counters != NULL) {
1211     cond_inc32(Assembler::zero,
1212                ExternalAddress((address) counters->anonymously_biased_lock_entry_count_addr()));
1213   }
1214   if (slow_case != NULL) {
1215     jcc(Assembler::notZero, *slow_case);
1216   }
1217   jmp(done);
1218 
1219   bind(try_rebias);
1220   // At this point we know the epoch has expired, meaning that the
1221   // current "bias owner", if any, is actually invalid. Under these
1222   // circumstances _only_, we are allowed to use the current header's
1223   // value as the comparison value when doing the cas to acquire the
1224   // bias in the current epoch. In other words, we allow transfer of
1225   // the bias from one thread to another directly in this situation.
1226   //
1227   // FIXME: due to a lack of registers we currently blow away the age
1228   // bits in this situation. Should attempt to preserve them.
1229   load_prototype_header(tmp_reg, obj_reg);
1230 #ifdef _LP64
1231   orptr(tmp_reg, r15_thread);
1232 #else
1233   get_thread(swap_reg);
1234   orptr(tmp_reg, swap_reg);
1235   movptr(swap_reg, saved_mark_addr);
1236 #endif
1237   if (os::is_MP()) {
1238     lock();
1239   }
1240   cmpxchgptr(tmp_reg, mark_addr); // compare tmp_reg and swap_reg
1241   // If the biasing toward our thread failed, then another thread
1242   // succeeded in biasing it toward itself and we need to revoke that
1243   // bias. The revocation will occur in the runtime in the slow case.
1244   if (counters != NULL) {
1245     cond_inc32(Assembler::zero,
1246                ExternalAddress((address) counters->rebiased_lock_entry_count_addr()));
1247   }
1248   if (slow_case != NULL) {
1249     jcc(Assembler::notZero, *slow_case);
1250   }
1251   jmp(done);
1252 
1253   bind(try_revoke_bias);
1254   // The prototype mark in the klass doesn't have the bias bit set any
1255   // more, indicating that objects of this data type are not supposed
1256   // to be biased any more. We are going to try to reset the mark of
1257   // this object to the prototype value and fall through to the
1258   // CAS-based locking scheme. Note that if our CAS fails, it means
1259   // that another thread raced us for the privilege of revoking the
1260   // bias of this particular object, so it's okay to continue in the
1261   // normal locking code.
1262   //
1263   // FIXME: due to a lack of registers we currently blow away the age
1264   // bits in this situation. Should attempt to preserve them.
1265   NOT_LP64( movptr(swap_reg, saved_mark_addr); )
1266   load_prototype_header(tmp_reg, obj_reg);
1267   if (os::is_MP()) {
1268     lock();
1269   }
1270   cmpxchgptr(tmp_reg, mark_addr); // compare tmp_reg and swap_reg
1271   // Fall through to the normal CAS-based lock, because no matter what
1272   // the result of the above CAS, some thread must have succeeded in
1273   // removing the bias bit from the object's header.
1274   if (counters != NULL) {
1275     cond_inc32(Assembler::zero,
1276                ExternalAddress((address) counters->revoked_lock_entry_count_addr()));
1277   }
1278 
1279   bind(cas_label);
1280 
1281   return null_check_offset;
1282 }
1283 
1284 void MacroAssembler::biased_locking_exit(Register obj_reg, Register temp_reg, Label& done) {
1285   assert(UseBiasedLocking, "why call this otherwise?");
1286 
1287   // Check for biased locking unlock case, which is a no-op
1288   // Note: we do not have to check the thread ID for two reasons.
1289   // First, the interpreter checks for IllegalMonitorStateException at
1290   // a higher level. Second, if the bias was revoked while we held the
1291   // lock, the object could not be rebiased toward another thread, so
1292   // the bias bit would be clear.
1293   movptr(temp_reg, Address(obj_reg, oopDesc::mark_offset_in_bytes()));
1294   andptr(temp_reg, markOopDesc::biased_lock_mask_in_place);
1295   cmpptr(temp_reg, markOopDesc::biased_lock_pattern);
1296   jcc(Assembler::equal, done);
1297 }
1298 
1299 #ifdef COMPILER2
1300 
1301 #if INCLUDE_RTM_OPT
1302 
1303 // Update rtm_counters based on abort status
1304 // input: abort_status
1305 //        rtm_counters (RTMLockingCounters*)
1306 // flags are killed
1307 void MacroAssembler::rtm_counters_update(Register abort_status, Register rtm_counters) {
1308 
1309   atomic_incptr(Address(rtm_counters, RTMLockingCounters::abort_count_offset()));
1310   if (PrintPreciseRTMLockingStatistics) {
1311     for (int i = 0; i < RTMLockingCounters::ABORT_STATUS_LIMIT; i++) {
1312       Label check_abort;
1313       testl(abort_status, (1<<i));
1314       jccb(Assembler::equal, check_abort);
1315       atomic_incptr(Address(rtm_counters, RTMLockingCounters::abortX_count_offset() + (i * sizeof(uintx))));
1316       bind(check_abort);
1317     }
1318   }
1319 }
1320 
1321 // Branch if (random & (count-1) != 0), count is 2^n
1322 // tmp, scr and flags are killed
1323 void MacroAssembler::branch_on_random_using_rdtsc(Register tmp, Register scr, int count, Label& brLabel) {
1324   assert(tmp == rax, "");
1325   assert(scr == rdx, "");
1326   rdtsc(); // modifies EDX:EAX
1327   andptr(tmp, count-1);
1328   jccb(Assembler::notZero, brLabel);
1329 }
1330 
1331 // Perform abort ratio calculation, set no_rtm bit if high ratio
1332 // input:  rtm_counters_Reg (RTMLockingCounters* address)
1333 // tmpReg, rtm_counters_Reg and flags are killed
1334 void MacroAssembler::rtm_abort_ratio_calculation(Register tmpReg,
1335                                                  Register rtm_counters_Reg,
1336                                                  RTMLockingCounters* rtm_counters,
1337                                                  Metadata* method_data) {
1338   Label L_done, L_check_always_rtm1, L_check_always_rtm2;
1339 
1340   if (RTMLockingCalculationDelay > 0) {
1341     // Delay calculation
1342     movptr(tmpReg, ExternalAddress((address) RTMLockingCounters::rtm_calculation_flag_addr()), tmpReg);
1343     testptr(tmpReg, tmpReg);
1344     jccb(Assembler::equal, L_done);
1345   }
1346   // Abort ratio calculation only if abort_count > RTMAbortThreshold
1347   //   Aborted transactions = abort_count * 100
1348   //   All transactions = total_count *  RTMTotalCountIncrRate
1349   //   Set no_rtm bit if (Aborted transactions >= All transactions * RTMAbortRatio)
1350 
1351   movptr(tmpReg, Address(rtm_counters_Reg, RTMLockingCounters::abort_count_offset()));
1352   cmpptr(tmpReg, RTMAbortThreshold);
1353   jccb(Assembler::below, L_check_always_rtm2);
1354   imulptr(tmpReg, tmpReg, 100);
1355 
1356   Register scrReg = rtm_counters_Reg;
1357   movptr(scrReg, Address(rtm_counters_Reg, RTMLockingCounters::total_count_offset()));
1358   imulptr(scrReg, scrReg, RTMTotalCountIncrRate);
1359   imulptr(scrReg, scrReg, RTMAbortRatio);
1360   cmpptr(tmpReg, scrReg);
1361   jccb(Assembler::below, L_check_always_rtm1);
1362   if (method_data != NULL) {
1363     // set rtm_state to "no rtm" in MDO
1364     mov_metadata(tmpReg, method_data);
1365     if (os::is_MP()) {
1366       lock();
1367     }
1368     orl(Address(tmpReg, MethodData::rtm_state_offset_in_bytes()), NoRTM);
1369   }
1370   jmpb(L_done);
1371   bind(L_check_always_rtm1);
1372   // Reload RTMLockingCounters* address
1373   lea(rtm_counters_Reg, ExternalAddress((address)rtm_counters));
1374   bind(L_check_always_rtm2);
1375   movptr(tmpReg, Address(rtm_counters_Reg, RTMLockingCounters::total_count_offset()));
1376   cmpptr(tmpReg, RTMLockingThreshold / RTMTotalCountIncrRate);
1377   jccb(Assembler::below, L_done);
1378   if (method_data != NULL) {
1379     // set rtm_state to "always rtm" in MDO
1380     mov_metadata(tmpReg, method_data);
1381     if (os::is_MP()) {
1382       lock();
1383     }
1384     orl(Address(tmpReg, MethodData::rtm_state_offset_in_bytes()), UseRTM);
1385   }
1386   bind(L_done);
1387 }
1388 
1389 // Update counters and perform abort ratio calculation
1390 // input:  abort_status_Reg
1391 // rtm_counters_Reg, flags are killed
1392 void MacroAssembler::rtm_profiling(Register abort_status_Reg,
1393                                    Register rtm_counters_Reg,
1394                                    RTMLockingCounters* rtm_counters,
1395                                    Metadata* method_data,
1396                                    bool profile_rtm) {
1397 
1398   assert(rtm_counters != NULL, "should not be NULL when profiling RTM");
1399   // update rtm counters based on rax value at abort
1400   // reads abort_status_Reg, updates flags
1401   lea(rtm_counters_Reg, ExternalAddress((address)rtm_counters));
1402   rtm_counters_update(abort_status_Reg, rtm_counters_Reg);
1403   if (profile_rtm) {
1404     // Save abort status because abort_status_Reg is used by following code.
1405     if (RTMRetryCount > 0) {
1406       push(abort_status_Reg);
1407     }
1408     assert(rtm_counters != NULL, "should not be NULL when profiling RTM");
1409     rtm_abort_ratio_calculation(abort_status_Reg, rtm_counters_Reg, rtm_counters, method_data);
1410     // restore abort status
1411     if (RTMRetryCount > 0) {
1412       pop(abort_status_Reg);
1413     }
1414   }
1415 }
1416 
1417 // Retry on abort if abort's status is 0x6: can retry (0x2) | memory conflict (0x4)
1418 // inputs: retry_count_Reg
1419 //       : abort_status_Reg
1420 // output: retry_count_Reg decremented by 1
1421 // flags are killed
1422 void MacroAssembler::rtm_retry_lock_on_abort(Register retry_count_Reg, Register abort_status_Reg, Label& retryLabel) {
1423   Label doneRetry;
1424   assert(abort_status_Reg == rax, "");
1425   // The abort reason bits are in eax (see all states in rtmLocking.hpp)
1426   // 0x6 = conflict on which we can retry (0x2) | memory conflict (0x4)
1427   // if reason is in 0x6 and retry count != 0 then retry
1428   andptr(abort_status_Reg, 0x6);
1429   jccb(Assembler::zero, doneRetry);
1430   testl(retry_count_Reg, retry_count_Reg);
1431   jccb(Assembler::zero, doneRetry);
1432   pause();
1433   decrementl(retry_count_Reg);
1434   jmp(retryLabel);
1435   bind(doneRetry);
1436 }
1437 
1438 // Spin and retry if lock is busy,
1439 // inputs: box_Reg (monitor address)
1440 //       : retry_count_Reg
1441 // output: retry_count_Reg decremented by 1
1442 //       : clear z flag if retry count exceeded
1443 // tmp_Reg, scr_Reg, flags are killed
1444 void MacroAssembler::rtm_retry_lock_on_busy(Register retry_count_Reg, Register box_Reg,
1445                                             Register tmp_Reg, Register scr_Reg, Label& retryLabel) {
1446   Label SpinLoop, SpinExit, doneRetry;
1447   int owner_offset = OM_OFFSET_NO_MONITOR_VALUE_TAG(owner);
1448 
1449   testl(retry_count_Reg, retry_count_Reg);
1450   jccb(Assembler::zero, doneRetry);
1451   decrementl(retry_count_Reg);
1452   movptr(scr_Reg, RTMSpinLoopCount);
1453 
1454   bind(SpinLoop);
1455   pause();
1456   decrementl(scr_Reg);
1457   jccb(Assembler::lessEqual, SpinExit);
1458   movptr(tmp_Reg, Address(box_Reg, owner_offset));
1459   testptr(tmp_Reg, tmp_Reg);
1460   jccb(Assembler::notZero, SpinLoop);
1461 
1462   bind(SpinExit);
1463   jmp(retryLabel);
1464   bind(doneRetry);
1465   incrementl(retry_count_Reg); // clear z flag
1466 }
1467 
1468 // Use RTM for normal stack locks
1469 // Input: objReg (object to lock)
1470 void MacroAssembler::rtm_stack_locking(Register objReg, Register tmpReg, Register scrReg,
1471                                        Register retry_on_abort_count_Reg,
1472                                        RTMLockingCounters* stack_rtm_counters,
1473                                        Metadata* method_data, bool profile_rtm,
1474                                        Label& DONE_LABEL, Label& IsInflated) {
1475   assert(UseRTMForStackLocks, "why call this otherwise?");
1476   assert(!UseBiasedLocking, "Biased locking is not supported with RTM locking");
1477   assert(tmpReg == rax, "");
1478   assert(scrReg == rdx, "");
1479   Label L_rtm_retry, L_decrement_retry, L_on_abort;
1480 
1481   if (RTMRetryCount > 0) {
1482     movl(retry_on_abort_count_Reg, RTMRetryCount); // Retry on abort
1483     bind(L_rtm_retry);
1484   }
1485   movptr(tmpReg, Address(objReg, 0));
1486   testptr(tmpReg, markOopDesc::monitor_value);  // inflated vs stack-locked|neutral|biased
1487   jcc(Assembler::notZero, IsInflated);
1488 
1489   if (PrintPreciseRTMLockingStatistics || profile_rtm) {
1490     Label L_noincrement;
1491     if (RTMTotalCountIncrRate > 1) {
1492       // tmpReg, scrReg and flags are killed
1493       branch_on_random_using_rdtsc(tmpReg, scrReg, (int)RTMTotalCountIncrRate, L_noincrement);
1494     }
1495     assert(stack_rtm_counters != NULL, "should not be NULL when profiling RTM");
1496     atomic_incptr(ExternalAddress((address)stack_rtm_counters->total_count_addr()), scrReg);
1497     bind(L_noincrement);
1498   }
1499   xbegin(L_on_abort);
1500   movptr(tmpReg, Address(objReg, 0));       // fetch markword
1501   andptr(tmpReg, markOopDesc::biased_lock_mask_in_place); // look at 3 lock bits
1502   cmpptr(tmpReg, markOopDesc::unlocked_value);            // bits = 001 unlocked
1503   jcc(Assembler::equal, DONE_LABEL);        // all done if unlocked
1504 
1505   Register abort_status_Reg = tmpReg; // status of abort is stored in RAX
1506   if (UseRTMXendForLockBusy) {
1507     xend();
1508     movptr(abort_status_Reg, 0x2);   // Set the abort status to 2 (so we can retry)
1509     jmp(L_decrement_retry);
1510   }
1511   else {
1512     xabort(0);
1513   }
1514   bind(L_on_abort);
1515   if (PrintPreciseRTMLockingStatistics || profile_rtm) {
1516     rtm_profiling(abort_status_Reg, scrReg, stack_rtm_counters, method_data, profile_rtm);
1517   }
1518   bind(L_decrement_retry);
1519   if (RTMRetryCount > 0) {
1520     // retry on lock abort if abort status is 'can retry' (0x2) or 'memory conflict' (0x4)
1521     rtm_retry_lock_on_abort(retry_on_abort_count_Reg, abort_status_Reg, L_rtm_retry);
1522   }
1523 }
1524 
1525 // Use RTM for inflating locks
1526 // inputs: objReg (object to lock)
1527 //         boxReg (on-stack box address (displaced header location) - KILLED)
1528 //         tmpReg (ObjectMonitor address + markOopDesc::monitor_value)
1529 void MacroAssembler::rtm_inflated_locking(Register objReg, Register boxReg, Register tmpReg,
1530                                           Register scrReg, Register retry_on_busy_count_Reg,
1531                                           Register retry_on_abort_count_Reg,
1532                                           RTMLockingCounters* rtm_counters,
1533                                           Metadata* method_data, bool profile_rtm,
1534                                           Label& DONE_LABEL) {
1535   assert(UseRTMLocking, "why call this otherwise?");
1536   assert(tmpReg == rax, "");
1537   assert(scrReg == rdx, "");
1538   Label L_rtm_retry, L_decrement_retry, L_on_abort;
1539   int owner_offset = OM_OFFSET_NO_MONITOR_VALUE_TAG(owner);
1540 
1541   // Without cast to int32_t a movptr will destroy r10 which is typically obj
1542   movptr(Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark()));
1543   movptr(boxReg, tmpReg); // Save ObjectMonitor address
1544 
1545   if (RTMRetryCount > 0) {
1546     movl(retry_on_busy_count_Reg, RTMRetryCount);  // Retry on lock busy
1547     movl(retry_on_abort_count_Reg, RTMRetryCount); // Retry on abort
1548     bind(L_rtm_retry);
1549   }
1550   if (PrintPreciseRTMLockingStatistics || profile_rtm) {
1551     Label L_noincrement;
1552     if (RTMTotalCountIncrRate > 1) {
1553       // tmpReg, scrReg and flags are killed
1554       branch_on_random_using_rdtsc(tmpReg, scrReg, (int)RTMTotalCountIncrRate, L_noincrement);
1555     }
1556     assert(rtm_counters != NULL, "should not be NULL when profiling RTM");
1557     atomic_incptr(ExternalAddress((address)rtm_counters->total_count_addr()), scrReg);
1558     bind(L_noincrement);
1559   }
1560   xbegin(L_on_abort);
1561   movptr(tmpReg, Address(objReg, 0));
1562   movptr(tmpReg, Address(tmpReg, owner_offset));
1563   testptr(tmpReg, tmpReg);
1564   jcc(Assembler::zero, DONE_LABEL);
1565   if (UseRTMXendForLockBusy) {
1566     xend();
1567     jmp(L_decrement_retry);
1568   }
1569   else {
1570     xabort(0);
1571   }
1572   bind(L_on_abort);
1573   Register abort_status_Reg = tmpReg; // status of abort is stored in RAX
1574   if (PrintPreciseRTMLockingStatistics || profile_rtm) {
1575     rtm_profiling(abort_status_Reg, scrReg, rtm_counters, method_data, profile_rtm);
1576   }
1577   if (RTMRetryCount > 0) {
1578     // retry on lock abort if abort status is 'can retry' (0x2) or 'memory conflict' (0x4)
1579     rtm_retry_lock_on_abort(retry_on_abort_count_Reg, abort_status_Reg, L_rtm_retry);
1580   }
1581 
1582   movptr(tmpReg, Address(boxReg, owner_offset)) ;
1583   testptr(tmpReg, tmpReg) ;
1584   jccb(Assembler::notZero, L_decrement_retry) ;
1585 
1586   // Appears unlocked - try to swing _owner from null to non-null.
1587   // Invariant: tmpReg == 0.  tmpReg is EAX which is the implicit cmpxchg comparand.
1588 #ifdef _LP64
1589   Register threadReg = r15_thread;
1590 #else
1591   get_thread(scrReg);
1592   Register threadReg = scrReg;
1593 #endif
1594   if (os::is_MP()) {
1595     lock();
1596   }
1597   cmpxchgptr(threadReg, Address(boxReg, owner_offset)); // Updates tmpReg
1598 
1599   if (RTMRetryCount > 0) {
1600     // success done else retry
1601     jccb(Assembler::equal, DONE_LABEL) ;
1602     bind(L_decrement_retry);
1603     // Spin and retry if lock is busy.
1604     rtm_retry_lock_on_busy(retry_on_busy_count_Reg, boxReg, tmpReg, scrReg, L_rtm_retry);
1605   }
1606   else {
1607     bind(L_decrement_retry);
1608   }
1609 }
1610 
1611 #endif //  INCLUDE_RTM_OPT
1612 
1613 // Fast_Lock and Fast_Unlock used by C2
1614 
1615 // Because the transitions from emitted code to the runtime
1616 // monitorenter/exit helper stubs are so slow it's critical that
1617 // we inline both the stack-locking fast-path and the inflated fast path.
1618 //
1619 // See also: cmpFastLock and cmpFastUnlock.
1620 //
1621 // What follows is a specialized inline transliteration of the code
1622 // in slow_enter() and slow_exit().  If we're concerned about I$ bloat
1623 // another option would be to emit TrySlowEnter and TrySlowExit methods
1624 // at startup-time.  These methods would accept arguments as
1625 // (rax,=Obj, rbx=Self, rcx=box, rdx=Scratch) and return success-failure
1626 // indications in the icc.ZFlag.  Fast_Lock and Fast_Unlock would simply
1627 // marshal the arguments and emit calls to TrySlowEnter and TrySlowExit.
1628 // In practice, however, the # of lock sites is bounded and is usually small.
1629 // Besides the call overhead, TrySlowEnter and TrySlowExit might suffer
1630 // if the processor uses simple bimodal branch predictors keyed by EIP
1631 // Since the helper routines would be called from multiple synchronization
1632 // sites.
1633 //
1634 // An even better approach would be write "MonitorEnter()" and "MonitorExit()"
1635 // in java - using j.u.c and unsafe - and just bind the lock and unlock sites
1636 // to those specialized methods.  That'd give us a mostly platform-independent
1637 // implementation that the JITs could optimize and inline at their pleasure.
1638 // Done correctly, the only time we'd need to cross to native could would be
1639 // to park() or unpark() threads.  We'd also need a few more unsafe operators
1640 // to (a) prevent compiler-JIT reordering of non-volatile accesses, and
1641 // (b) explicit barriers or fence operations.
1642 //
1643 // TODO:
1644 //
1645 // *  Arrange for C2 to pass "Self" into Fast_Lock and Fast_Unlock in one of the registers (scr).
1646 //    This avoids manifesting the Self pointer in the Fast_Lock and Fast_Unlock terminals.
1647 //    Given TLAB allocation, Self is usually manifested in a register, so passing it into
1648 //    the lock operators would typically be faster than reifying Self.
1649 //
1650 // *  Ideally I'd define the primitives as:
1651 //       fast_lock   (nax Obj, nax box, EAX tmp, nax scr) where box, tmp and scr are KILLED.
1652 //       fast_unlock (nax Obj, EAX box, nax tmp) where box and tmp are KILLED
1653 //    Unfortunately ADLC bugs prevent us from expressing the ideal form.
1654 //    Instead, we're stuck with a rather awkward and brittle register assignments below.
1655 //    Furthermore the register assignments are overconstrained, possibly resulting in
1656 //    sub-optimal code near the synchronization site.
1657 //
1658 // *  Eliminate the sp-proximity tests and just use "== Self" tests instead.
1659 //    Alternately, use a better sp-proximity test.
1660 //
1661 // *  Currently ObjectMonitor._Owner can hold either an sp value or a (THREAD *) value.
1662 //    Either one is sufficient to uniquely identify a thread.
1663 //    TODO: eliminate use of sp in _owner and use get_thread(tr) instead.
1664 //
1665 // *  Intrinsify notify() and notifyAll() for the common cases where the
1666 //    object is locked by the calling thread but the waitlist is empty.
1667 //    avoid the expensive JNI call to JVM_Notify() and JVM_NotifyAll().
1668 //
1669 // *  use jccb and jmpb instead of jcc and jmp to improve code density.
1670 //    But beware of excessive branch density on AMD Opterons.
1671 //
1672 // *  Both Fast_Lock and Fast_Unlock set the ICC.ZF to indicate success
1673 //    or failure of the fast-path.  If the fast-path fails then we pass
1674 //    control to the slow-path, typically in C.  In Fast_Lock and
1675 //    Fast_Unlock we often branch to DONE_LABEL, just to find that C2
1676 //    will emit a conditional branch immediately after the node.
1677 //    So we have branches to branches and lots of ICC.ZF games.
1678 //    Instead, it might be better to have C2 pass a "FailureLabel"
1679 //    into Fast_Lock and Fast_Unlock.  In the case of success, control
1680 //    will drop through the node.  ICC.ZF is undefined at exit.
1681 //    In the case of failure, the node will branch directly to the
1682 //    FailureLabel
1683 
1684 
1685 // obj: object to lock
1686 // box: on-stack box address (displaced header location) - KILLED
1687 // rax,: tmp -- KILLED
1688 // scr: tmp -- KILLED
1689 void MacroAssembler::fast_lock(Register objReg, Register boxReg, Register tmpReg,
1690                                Register scrReg, Register cx1Reg, Register cx2Reg,
1691                                BiasedLockingCounters* counters,
1692                                RTMLockingCounters* rtm_counters,
1693                                RTMLockingCounters* stack_rtm_counters,
1694                                Metadata* method_data,
1695                                bool use_rtm, bool profile_rtm) {
1696   // Ensure the register assignments are disjoint
1697   assert(tmpReg == rax, "");
1698 
1699   if (use_rtm) {
1700     assert_different_registers(objReg, boxReg, tmpReg, scrReg, cx1Reg, cx2Reg);
1701   } else {
1702     assert(cx1Reg == noreg, "");
1703     assert(cx2Reg == noreg, "");
1704     assert_different_registers(objReg, boxReg, tmpReg, scrReg);
1705   }
1706 
1707   if (counters != NULL) {
1708     atomic_incl(ExternalAddress((address)counters->total_entry_count_addr()), scrReg);
1709   }
1710   if (EmitSync & 1) {
1711       // set box->dhw = markOopDesc::unused_mark()
1712       // Force all sync thru slow-path: slow_enter() and slow_exit()
1713       movptr (Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark()));
1714       cmpptr (rsp, (int32_t)NULL_WORD);
1715   } else {
1716     // Possible cases that we'll encounter in fast_lock
1717     // ------------------------------------------------
1718     // * Inflated
1719     //    -- unlocked
1720     //    -- Locked
1721     //       = by self
1722     //       = by other
1723     // * biased
1724     //    -- by Self
1725     //    -- by other
1726     // * neutral
1727     // * stack-locked
1728     //    -- by self
1729     //       = sp-proximity test hits
1730     //       = sp-proximity test generates false-negative
1731     //    -- by other
1732     //
1733 
1734     Label IsInflated, DONE_LABEL;
1735 
1736     // it's stack-locked, biased or neutral
1737     // TODO: optimize away redundant LDs of obj->mark and improve the markword triage
1738     // order to reduce the number of conditional branches in the most common cases.
1739     // Beware -- there's a subtle invariant that fetch of the markword
1740     // at [FETCH], below, will never observe a biased encoding (*101b).
1741     // If this invariant is not held we risk exclusion (safety) failure.
1742     if (UseBiasedLocking && !UseOptoBiasInlining) {
1743       biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, counters);
1744     }
1745 
1746 #if INCLUDE_RTM_OPT
1747     if (UseRTMForStackLocks && use_rtm) {
1748       rtm_stack_locking(objReg, tmpReg, scrReg, cx2Reg,
1749                         stack_rtm_counters, method_data, profile_rtm,
1750                         DONE_LABEL, IsInflated);
1751     }
1752 #endif // INCLUDE_RTM_OPT
1753 
1754     movptr(tmpReg, Address(objReg, 0));          // [FETCH]
1755     testptr(tmpReg, markOopDesc::monitor_value); // inflated vs stack-locked|neutral|biased
1756     jccb(Assembler::notZero, IsInflated);
1757 
1758     // Attempt stack-locking ...
1759     orptr (tmpReg, markOopDesc::unlocked_value);
1760     movptr(Address(boxReg, 0), tmpReg);          // Anticipate successful CAS
1761     if (os::is_MP()) {
1762       lock();
1763     }
1764     cmpxchgptr(boxReg, Address(objReg, 0));      // Updates tmpReg
1765     if (counters != NULL) {
1766       cond_inc32(Assembler::equal,
1767                  ExternalAddress((address)counters->fast_path_entry_count_addr()));
1768     }
1769     jcc(Assembler::equal, DONE_LABEL);           // Success
1770 
1771     // Recursive locking.
1772     // The object is stack-locked: markword contains stack pointer to BasicLock.
1773     // Locked by current thread if difference with current SP is less than one page.
1774     subptr(tmpReg, rsp);
1775     // Next instruction set ZFlag == 1 (Success) if difference is less then one page.
1776     andptr(tmpReg, (int32_t) (NOT_LP64(0xFFFFF003) LP64_ONLY(7 - os::vm_page_size())) );
1777     movptr(Address(boxReg, 0), tmpReg);
1778     if (counters != NULL) {
1779       cond_inc32(Assembler::equal,
1780                  ExternalAddress((address)counters->fast_path_entry_count_addr()));
1781     }
1782     jmp(DONE_LABEL);
1783 
1784     bind(IsInflated);
1785     // The object is inflated. tmpReg contains pointer to ObjectMonitor* + markOopDesc::monitor_value
1786 
1787 #if INCLUDE_RTM_OPT
1788     // Use the same RTM locking code in 32- and 64-bit VM.
1789     if (use_rtm) {
1790       rtm_inflated_locking(objReg, boxReg, tmpReg, scrReg, cx1Reg, cx2Reg,
1791                            rtm_counters, method_data, profile_rtm, DONE_LABEL);
1792     } else {
1793 #endif // INCLUDE_RTM_OPT
1794 
1795 #ifndef _LP64
1796     // The object is inflated.
1797 
1798     // boxReg refers to the on-stack BasicLock in the current frame.
1799     // We'd like to write:
1800     //   set box->_displaced_header = markOopDesc::unused_mark().  Any non-0 value suffices.
1801     // This is convenient but results a ST-before-CAS penalty.  The following CAS suffers
1802     // additional latency as we have another ST in the store buffer that must drain.
1803 
1804     if (EmitSync & 8192) {
1805        movptr(Address(boxReg, 0), 3);            // results in ST-before-CAS penalty
1806        get_thread (scrReg);
1807        movptr(boxReg, tmpReg);                    // consider: LEA box, [tmp-2]
1808        movptr(tmpReg, NULL_WORD);                 // consider: xor vs mov
1809        if (os::is_MP()) {
1810          lock();
1811        }
1812        cmpxchgptr(scrReg, Address(boxReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
1813     } else
1814     if ((EmitSync & 128) == 0) {                      // avoid ST-before-CAS
1815        // register juggle because we need tmpReg for cmpxchgptr below
1816        movptr(scrReg, boxReg);
1817        movptr(boxReg, tmpReg);                   // consider: LEA box, [tmp-2]
1818 
1819        // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes
1820        if ((EmitSync & 2048) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
1821           // prefetchw [eax + Offset(_owner)-2]
1822           prefetchw(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
1823        }
1824 
1825        if ((EmitSync & 64) == 0) {
1826          // Optimistic form: consider XORL tmpReg,tmpReg
1827          movptr(tmpReg, NULL_WORD);
1828        } else {
1829          // Can suffer RTS->RTO upgrades on shared or cold $ lines
1830          // Test-And-CAS instead of CAS
1831          movptr(tmpReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));   // rax, = m->_owner
1832          testptr(tmpReg, tmpReg);                   // Locked ?
1833          jccb  (Assembler::notZero, DONE_LABEL);
1834        }
1835 
1836        // Appears unlocked - try to swing _owner from null to non-null.
1837        // Ideally, I'd manifest "Self" with get_thread and then attempt
1838        // to CAS the register containing Self into m->Owner.
1839        // But we don't have enough registers, so instead we can either try to CAS
1840        // rsp or the address of the box (in scr) into &m->owner.  If the CAS succeeds
1841        // we later store "Self" into m->Owner.  Transiently storing a stack address
1842        // (rsp or the address of the box) into  m->owner is harmless.
1843        // Invariant: tmpReg == 0.  tmpReg is EAX which is the implicit cmpxchg comparand.
1844        if (os::is_MP()) {
1845          lock();
1846        }
1847        cmpxchgptr(scrReg, Address(boxReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
1848        movptr(Address(scrReg, 0), 3);          // box->_displaced_header = 3
1849        // If we weren't able to swing _owner from NULL to the BasicLock
1850        // then take the slow path.
1851        jccb  (Assembler::notZero, DONE_LABEL);
1852        // update _owner from BasicLock to thread
1853        get_thread (scrReg);                    // beware: clobbers ICCs
1854        movptr(Address(boxReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), scrReg);
1855        xorptr(boxReg, boxReg);                 // set icc.ZFlag = 1 to indicate success
1856 
1857        // If the CAS fails we can either retry or pass control to the slow-path.
1858        // We use the latter tactic.
1859        // Pass the CAS result in the icc.ZFlag into DONE_LABEL
1860        // If the CAS was successful ...
1861        //   Self has acquired the lock
1862        //   Invariant: m->_recursions should already be 0, so we don't need to explicitly set it.
1863        // Intentional fall-through into DONE_LABEL ...
1864     } else {
1865        movptr(Address(boxReg, 0), intptr_t(markOopDesc::unused_mark()));  // results in ST-before-CAS penalty
1866        movptr(boxReg, tmpReg);
1867 
1868        // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes
1869        if ((EmitSync & 2048) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
1870           // prefetchw [eax + Offset(_owner)-2]
1871           prefetchw(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
1872        }
1873 
1874        if ((EmitSync & 64) == 0) {
1875          // Optimistic form
1876          xorptr  (tmpReg, tmpReg);
1877        } else {
1878          // Can suffer RTS->RTO upgrades on shared or cold $ lines
1879          movptr(tmpReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));   // rax, = m->_owner
1880          testptr(tmpReg, tmpReg);                   // Locked ?
1881          jccb  (Assembler::notZero, DONE_LABEL);
1882        }
1883 
1884        // Appears unlocked - try to swing _owner from null to non-null.
1885        // Use either "Self" (in scr) or rsp as thread identity in _owner.
1886        // Invariant: tmpReg == 0.  tmpReg is EAX which is the implicit cmpxchg comparand.
1887        get_thread (scrReg);
1888        if (os::is_MP()) {
1889          lock();
1890        }
1891        cmpxchgptr(scrReg, Address(boxReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
1892 
1893        // If the CAS fails we can either retry or pass control to the slow-path.
1894        // We use the latter tactic.
1895        // Pass the CAS result in the icc.ZFlag into DONE_LABEL
1896        // If the CAS was successful ...
1897        //   Self has acquired the lock
1898        //   Invariant: m->_recursions should already be 0, so we don't need to explicitly set it.
1899        // Intentional fall-through into DONE_LABEL ...
1900     }
1901 #else // _LP64
1902     // It's inflated
1903     movq(scrReg, tmpReg);
1904     xorq(tmpReg, tmpReg);
1905 
1906     if (os::is_MP()) {
1907       lock();
1908     }
1909     cmpxchgptr(r15_thread, Address(scrReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
1910     // Unconditionally set box->_displaced_header = markOopDesc::unused_mark().
1911     // Without cast to int32_t movptr will destroy r10 which is typically obj.
1912     movptr(Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark()));
1913     // Intentional fall-through into DONE_LABEL ...
1914     // Propagate ICC.ZF from CAS above into DONE_LABEL.
1915 #endif // _LP64
1916 #if INCLUDE_RTM_OPT
1917     } // use_rtm()
1918 #endif
1919     // DONE_LABEL is a hot target - we'd really like to place it at the
1920     // start of cache line by padding with NOPs.
1921     // See the AMD and Intel software optimization manuals for the
1922     // most efficient "long" NOP encodings.
1923     // Unfortunately none of our alignment mechanisms suffice.
1924     bind(DONE_LABEL);
1925 
1926     // At DONE_LABEL the icc ZFlag is set as follows ...
1927     // Fast_Unlock uses the same protocol.
1928     // ZFlag == 1 -> Success
1929     // ZFlag == 0 -> Failure - force control through the slow-path
1930   }
1931 }
1932 
1933 // obj: object to unlock
1934 // box: box address (displaced header location), killed.  Must be EAX.
1935 // tmp: killed, cannot be obj nor box.
1936 //
1937 // Some commentary on balanced locking:
1938 //
1939 // Fast_Lock and Fast_Unlock are emitted only for provably balanced lock sites.
1940 // Methods that don't have provably balanced locking are forced to run in the
1941 // interpreter - such methods won't be compiled to use fast_lock and fast_unlock.
1942 // The interpreter provides two properties:
1943 // I1:  At return-time the interpreter automatically and quietly unlocks any
1944 //      objects acquired the current activation (frame).  Recall that the
1945 //      interpreter maintains an on-stack list of locks currently held by
1946 //      a frame.
1947 // I2:  If a method attempts to unlock an object that is not held by the
1948 //      the frame the interpreter throws IMSX.
1949 //
1950 // Lets say A(), which has provably balanced locking, acquires O and then calls B().
1951 // B() doesn't have provably balanced locking so it runs in the interpreter.
1952 // Control returns to A() and A() unlocks O.  By I1 and I2, above, we know that O
1953 // is still locked by A().
1954 //
1955 // The only other source of unbalanced locking would be JNI.  The "Java Native Interface:
1956 // Programmer's Guide and Specification" claims that an object locked by jni_monitorenter
1957 // should not be unlocked by "normal" java-level locking and vice-versa.  The specification
1958 // doesn't specify what will occur if a program engages in such mixed-mode locking, however.
1959 // Arguably given that the spec legislates the JNI case as undefined our implementation
1960 // could reasonably *avoid* checking owner in Fast_Unlock().
1961 // In the interest of performance we elide m->Owner==Self check in unlock.
1962 // A perfectly viable alternative is to elide the owner check except when
1963 // Xcheck:jni is enabled.
1964 
1965 void MacroAssembler::fast_unlock(Register objReg, Register boxReg, Register tmpReg, bool use_rtm) {
1966   assert(boxReg == rax, "");
1967   assert_different_registers(objReg, boxReg, tmpReg);
1968 
1969   if (EmitSync & 4) {
1970     // Disable - inhibit all inlining.  Force control through the slow-path
1971     cmpptr (rsp, 0);
1972   } else {
1973     Label DONE_LABEL, Stacked, CheckSucc;
1974 
1975     // Critically, the biased locking test must have precedence over
1976     // and appear before the (box->dhw == 0) recursive stack-lock test.
1977     if (UseBiasedLocking && !UseOptoBiasInlining) {
1978        biased_locking_exit(objReg, tmpReg, DONE_LABEL);
1979     }
1980 
1981 #if INCLUDE_RTM_OPT
1982     if (UseRTMForStackLocks && use_rtm) {
1983       assert(!UseBiasedLocking, "Biased locking is not supported with RTM locking");
1984       Label L_regular_unlock;
1985       movptr(tmpReg, Address(objReg, 0));           // fetch markword
1986       andptr(tmpReg, markOopDesc::biased_lock_mask_in_place); // look at 3 lock bits
1987       cmpptr(tmpReg, markOopDesc::unlocked_value);            // bits = 001 unlocked
1988       jccb(Assembler::notEqual, L_regular_unlock);  // if !HLE RegularLock
1989       xend();                                       // otherwise end...
1990       jmp(DONE_LABEL);                              // ... and we're done
1991       bind(L_regular_unlock);
1992     }
1993 #endif
1994 
1995     cmpptr(Address(boxReg, 0), (int32_t)NULL_WORD); // Examine the displaced header
1996     jcc   (Assembler::zero, DONE_LABEL);            // 0 indicates recursive stack-lock
1997     movptr(tmpReg, Address(objReg, 0));             // Examine the object's markword
1998     testptr(tmpReg, markOopDesc::monitor_value);    // Inflated?
1999     jccb  (Assembler::zero, Stacked);
2000 
2001     // It's inflated.
2002 #if INCLUDE_RTM_OPT
2003     if (use_rtm) {
2004       Label L_regular_inflated_unlock;
2005       int owner_offset = OM_OFFSET_NO_MONITOR_VALUE_TAG(owner);
2006       movptr(boxReg, Address(tmpReg, owner_offset));
2007       testptr(boxReg, boxReg);
2008       jccb(Assembler::notZero, L_regular_inflated_unlock);
2009       xend();
2010       jmpb(DONE_LABEL);
2011       bind(L_regular_inflated_unlock);
2012     }
2013 #endif
2014 
2015     // Despite our balanced locking property we still check that m->_owner == Self
2016     // as java routines or native JNI code called by this thread might
2017     // have released the lock.
2018     // Refer to the comments in synchronizer.cpp for how we might encode extra
2019     // state in _succ so we can avoid fetching EntryList|cxq.
2020     //
2021     // I'd like to add more cases in fast_lock() and fast_unlock() --
2022     // such as recursive enter and exit -- but we have to be wary of
2023     // I$ bloat, T$ effects and BP$ effects.
2024     //
2025     // If there's no contention try a 1-0 exit.  That is, exit without
2026     // a costly MEMBAR or CAS.  See synchronizer.cpp for details on how
2027     // we detect and recover from the race that the 1-0 exit admits.
2028     //
2029     // Conceptually Fast_Unlock() must execute a STST|LDST "release" barrier
2030     // before it STs null into _owner, releasing the lock.  Updates
2031     // to data protected by the critical section must be visible before
2032     // we drop the lock (and thus before any other thread could acquire
2033     // the lock and observe the fields protected by the lock).
2034     // IA32's memory-model is SPO, so STs are ordered with respect to
2035     // each other and there's no need for an explicit barrier (fence).
2036     // See also http://gee.cs.oswego.edu/dl/jmm/cookbook.html.
2037 #ifndef _LP64
2038     get_thread (boxReg);
2039     if ((EmitSync & 4096) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
2040       // prefetchw [ebx + Offset(_owner)-2]
2041       prefetchw(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
2042     }
2043 
2044     // Note that we could employ various encoding schemes to reduce
2045     // the number of loads below (currently 4) to just 2 or 3.
2046     // Refer to the comments in synchronizer.cpp.
2047     // In practice the chain of fetches doesn't seem to impact performance, however.
2048     xorptr(boxReg, boxReg);
2049     if ((EmitSync & 65536) == 0 && (EmitSync & 256)) {
2050        // Attempt to reduce branch density - AMD's branch predictor.
2051        orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(recursions)));
2052        orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(EntryList)));
2053        orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(cxq)));
2054        jccb  (Assembler::notZero, DONE_LABEL);
2055        movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), NULL_WORD);
2056        jmpb  (DONE_LABEL);
2057     } else {
2058        orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(recursions)));
2059        jccb  (Assembler::notZero, DONE_LABEL);
2060        movptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(EntryList)));
2061        orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(cxq)));
2062        jccb  (Assembler::notZero, CheckSucc);
2063        movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), NULL_WORD);
2064        jmpb  (DONE_LABEL);
2065     }
2066 
2067     // The Following code fragment (EmitSync & 65536) improves the performance of
2068     // contended applications and contended synchronization microbenchmarks.
2069     // Unfortunately the emission of the code - even though not executed - causes regressions
2070     // in scimark and jetstream, evidently because of $ effects.  Replacing the code
2071     // with an equal number of never-executed NOPs results in the same regression.
2072     // We leave it off by default.
2073 
2074     if ((EmitSync & 65536) != 0) {
2075        Label LSuccess, LGoSlowPath ;
2076 
2077        bind  (CheckSucc);
2078 
2079        // Optional pre-test ... it's safe to elide this
2080        cmpptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(succ)), (int32_t)NULL_WORD);
2081        jccb(Assembler::zero, LGoSlowPath);
2082 
2083        // We have a classic Dekker-style idiom:
2084        //    ST m->_owner = 0 ; MEMBAR; LD m->_succ
2085        // There are a number of ways to implement the barrier:
2086        // (1) lock:andl &m->_owner, 0
2087        //     is fast, but mask doesn't currently support the "ANDL M,IMM32" form.
2088        //     LOCK: ANDL [ebx+Offset(_Owner)-2], 0
2089        //     Encodes as 81 31 OFF32 IMM32 or 83 63 OFF8 IMM8
2090        // (2) If supported, an explicit MFENCE is appealing.
2091        //     In older IA32 processors MFENCE is slower than lock:add or xchg
2092        //     particularly if the write-buffer is full as might be the case if
2093        //     if stores closely precede the fence or fence-equivalent instruction.
2094        //     See https://blogs.oracle.com/dave/entry/instruction_selection_for_volatile_fences
2095        //     as the situation has changed with Nehalem and Shanghai.
2096        // (3) In lieu of an explicit fence, use lock:addl to the top-of-stack
2097        //     The $lines underlying the top-of-stack should be in M-state.
2098        //     The locked add instruction is serializing, of course.
2099        // (4) Use xchg, which is serializing
2100        //     mov boxReg, 0; xchgl boxReg, [tmpReg + Offset(_owner)-2] also works
2101        // (5) ST m->_owner = 0 and then execute lock:orl &m->_succ, 0.
2102        //     The integer condition codes will tell us if succ was 0.
2103        //     Since _succ and _owner should reside in the same $line and
2104        //     we just stored into _owner, it's likely that the $line
2105        //     remains in M-state for the lock:orl.
2106        //
2107        // We currently use (3), although it's likely that switching to (2)
2108        // is correct for the future.
2109 
2110        movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), NULL_WORD);
2111        if (os::is_MP()) {
2112          lock(); addptr(Address(rsp, 0), 0);
2113        }
2114        // Ratify _succ remains non-null
2115        cmpptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(succ)), 0);
2116        jccb  (Assembler::notZero, LSuccess);
2117 
2118        xorptr(boxReg, boxReg);                  // box is really EAX
2119        if (os::is_MP()) { lock(); }
2120        cmpxchgptr(rsp, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
2121        // There's no successor so we tried to regrab the lock with the
2122        // placeholder value. If that didn't work, then another thread
2123        // grabbed the lock so we're done (and exit was a success).
2124        jccb  (Assembler::notEqual, LSuccess);
2125        // Since we're low on registers we installed rsp as a placeholding in _owner.
2126        // Now install Self over rsp.  This is safe as we're transitioning from
2127        // non-null to non=null
2128        get_thread (boxReg);
2129        movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), boxReg);
2130        // Intentional fall-through into LGoSlowPath ...
2131 
2132        bind  (LGoSlowPath);
2133        orptr(boxReg, 1);                      // set ICC.ZF=0 to indicate failure
2134        jmpb  (DONE_LABEL);
2135 
2136        bind  (LSuccess);
2137        xorptr(boxReg, boxReg);                 // set ICC.ZF=1 to indicate success
2138        jmpb  (DONE_LABEL);
2139     }
2140 
2141     bind (Stacked);
2142     // It's not inflated and it's not recursively stack-locked and it's not biased.
2143     // It must be stack-locked.
2144     // Try to reset the header to displaced header.
2145     // The "box" value on the stack is stable, so we can reload
2146     // and be assured we observe the same value as above.
2147     movptr(tmpReg, Address(boxReg, 0));
2148     if (os::is_MP()) {
2149       lock();
2150     }
2151     cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses RAX which is box
2152     // Intention fall-thru into DONE_LABEL
2153 
2154     // DONE_LABEL is a hot target - we'd really like to place it at the
2155     // start of cache line by padding with NOPs.
2156     // See the AMD and Intel software optimization manuals for the
2157     // most efficient "long" NOP encodings.
2158     // Unfortunately none of our alignment mechanisms suffice.
2159     if ((EmitSync & 65536) == 0) {
2160        bind (CheckSucc);
2161     }
2162 #else // _LP64
2163     // It's inflated
2164     if (EmitSync & 1024) {
2165       // Emit code to check that _owner == Self
2166       // We could fold the _owner test into subsequent code more efficiently
2167       // than using a stand-alone check, but since _owner checking is off by
2168       // default we don't bother. We also might consider predicating the
2169       // _owner==Self check on Xcheck:jni or running on a debug build.
2170       movptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
2171       xorptr(boxReg, r15_thread);
2172     } else {
2173       xorptr(boxReg, boxReg);
2174     }
2175     orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(recursions)));
2176     jccb  (Assembler::notZero, DONE_LABEL);
2177     movptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(cxq)));
2178     orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(EntryList)));
2179     jccb  (Assembler::notZero, CheckSucc);
2180     movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), (int32_t)NULL_WORD);
2181     jmpb  (DONE_LABEL);
2182 
2183     if ((EmitSync & 65536) == 0) {
2184       // Try to avoid passing control into the slow_path ...
2185       Label LSuccess, LGoSlowPath ;
2186       bind  (CheckSucc);
2187 
2188       // The following optional optimization can be elided if necessary
2189       // Effectively: if (succ == null) goto SlowPath
2190       // The code reduces the window for a race, however,
2191       // and thus benefits performance.
2192       cmpptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(succ)), (int32_t)NULL_WORD);
2193       jccb  (Assembler::zero, LGoSlowPath);
2194 
2195       xorptr(boxReg, boxReg);
2196       if ((EmitSync & 16) && os::is_MP()) {
2197         xchgptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
2198       } else {
2199         movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), (int32_t)NULL_WORD);
2200         if (os::is_MP()) {
2201           // Memory barrier/fence
2202           // Dekker pivot point -- fulcrum : ST Owner; MEMBAR; LD Succ
2203           // Instead of MFENCE we use a dummy locked add of 0 to the top-of-stack.
2204           // This is faster on Nehalem and AMD Shanghai/Barcelona.
2205           // See https://blogs.oracle.com/dave/entry/instruction_selection_for_volatile_fences
2206           // We might also restructure (ST Owner=0;barrier;LD _Succ) to
2207           // (mov box,0; xchgq box, &m->Owner; LD _succ) .
2208           lock(); addl(Address(rsp, 0), 0);
2209         }
2210       }
2211       cmpptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(succ)), (int32_t)NULL_WORD);
2212       jccb  (Assembler::notZero, LSuccess);
2213 
2214       // Rare inopportune interleaving - race.
2215       // The successor vanished in the small window above.
2216       // The lock is contended -- (cxq|EntryList) != null -- and there's no apparent successor.
2217       // We need to ensure progress and succession.
2218       // Try to reacquire the lock.
2219       // If that fails then the new owner is responsible for succession and this
2220       // thread needs to take no further action and can exit via the fast path (success).
2221       // If the re-acquire succeeds then pass control into the slow path.
2222       // As implemented, this latter mode is horrible because we generated more
2223       // coherence traffic on the lock *and* artifically extended the critical section
2224       // length while by virtue of passing control into the slow path.
2225 
2226       // box is really RAX -- the following CMPXCHG depends on that binding
2227       // cmpxchg R,[M] is equivalent to rax = CAS(M,rax,R)
2228       if (os::is_MP()) { lock(); }
2229       cmpxchgptr(r15_thread, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
2230       // There's no successor so we tried to regrab the lock.
2231       // If that didn't work, then another thread grabbed the
2232       // lock so we're done (and exit was a success).
2233       jccb  (Assembler::notEqual, LSuccess);
2234       // Intentional fall-through into slow-path
2235 
2236       bind  (LGoSlowPath);
2237       orl   (boxReg, 1);                      // set ICC.ZF=0 to indicate failure
2238       jmpb  (DONE_LABEL);
2239 
2240       bind  (LSuccess);
2241       testl (boxReg, 0);                      // set ICC.ZF=1 to indicate success
2242       jmpb  (DONE_LABEL);
2243     }
2244 
2245     bind  (Stacked);
2246     movptr(tmpReg, Address (boxReg, 0));      // re-fetch
2247     if (os::is_MP()) { lock(); }
2248     cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses RAX which is box
2249 
2250     if (EmitSync & 65536) {
2251        bind (CheckSucc);
2252     }
2253 #endif
2254     bind(DONE_LABEL);
2255   }
2256 }
2257 #endif // COMPILER2
2258 
2259 void MacroAssembler::c2bool(Register x) {
2260   // implements x == 0 ? 0 : 1
2261   // note: must only look at least-significant byte of x
2262   //       since C-style booleans are stored in one byte
2263   //       only! (was bug)
2264   andl(x, 0xFF);
2265   setb(Assembler::notZero, x);
2266 }
2267 
2268 // Wouldn't need if AddressLiteral version had new name
2269 void MacroAssembler::call(Label& L, relocInfo::relocType rtype) {
2270   Assembler::call(L, rtype);
2271 }
2272 
2273 void MacroAssembler::call(Register entry) {
2274   Assembler::call(entry);
2275 }
2276 
2277 void MacroAssembler::call(AddressLiteral entry) {
2278   if (reachable(entry)) {
2279     Assembler::call_literal(entry.target(), entry.rspec());
2280   } else {
2281     lea(rscratch1, entry);
2282     Assembler::call(rscratch1);
2283   }
2284 }
2285 
2286 void MacroAssembler::ic_call(address entry, jint method_index) {
2287   RelocationHolder rh = virtual_call_Relocation::spec(pc(), method_index);
2288   movptr(rax, (intptr_t)Universe::non_oop_word());
2289   call(AddressLiteral(entry, rh));
2290 }
2291 
2292 // Implementation of call_VM versions
2293 
2294 void MacroAssembler::call_VM(Register oop_result,
2295                              address entry_point,
2296                              bool check_exceptions) {
2297   Label C, E;
2298   call(C, relocInfo::none);
2299   jmp(E);
2300 
2301   bind(C);
2302   call_VM_helper(oop_result, entry_point, 0, check_exceptions);
2303   ret(0);
2304 
2305   bind(E);
2306 }
2307 
2308 void MacroAssembler::call_VM(Register oop_result,
2309                              address entry_point,
2310                              Register arg_1,
2311                              bool check_exceptions) {
2312   Label C, E;
2313   call(C, relocInfo::none);
2314   jmp(E);
2315 
2316   bind(C);
2317   pass_arg1(this, arg_1);
2318   call_VM_helper(oop_result, entry_point, 1, check_exceptions);
2319   ret(0);
2320 
2321   bind(E);
2322 }
2323 
2324 void MacroAssembler::call_VM(Register oop_result,
2325                              address entry_point,
2326                              Register arg_1,
2327                              Register arg_2,
2328                              bool check_exceptions) {
2329   Label C, E;
2330   call(C, relocInfo::none);
2331   jmp(E);
2332 
2333   bind(C);
2334 
2335   LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2336 
2337   pass_arg2(this, arg_2);
2338   pass_arg1(this, arg_1);
2339   call_VM_helper(oop_result, entry_point, 2, check_exceptions);
2340   ret(0);
2341 
2342   bind(E);
2343 }
2344 
2345 void MacroAssembler::call_VM(Register oop_result,
2346                              address entry_point,
2347                              Register arg_1,
2348                              Register arg_2,
2349                              Register arg_3,
2350                              bool check_exceptions) {
2351   Label C, E;
2352   call(C, relocInfo::none);
2353   jmp(E);
2354 
2355   bind(C);
2356 
2357   LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
2358   LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
2359   pass_arg3(this, arg_3);
2360 
2361   LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2362   pass_arg2(this, arg_2);
2363 
2364   pass_arg1(this, arg_1);
2365   call_VM_helper(oop_result, entry_point, 3, check_exceptions);
2366   ret(0);
2367 
2368   bind(E);
2369 }
2370 
2371 void MacroAssembler::call_VM(Register oop_result,
2372                              Register last_java_sp,
2373                              address entry_point,
2374                              int number_of_arguments,
2375                              bool check_exceptions) {
2376   Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg);
2377   call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions);
2378 }
2379 
2380 void MacroAssembler::call_VM(Register oop_result,
2381                              Register last_java_sp,
2382                              address entry_point,
2383                              Register arg_1,
2384                              bool check_exceptions) {
2385   pass_arg1(this, arg_1);
2386   call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
2387 }
2388 
2389 void MacroAssembler::call_VM(Register oop_result,
2390                              Register last_java_sp,
2391                              address entry_point,
2392                              Register arg_1,
2393                              Register arg_2,
2394                              bool check_exceptions) {
2395 
2396   LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2397   pass_arg2(this, arg_2);
2398   pass_arg1(this, arg_1);
2399   call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
2400 }
2401 
2402 void MacroAssembler::call_VM(Register oop_result,
2403                              Register last_java_sp,
2404                              address entry_point,
2405                              Register arg_1,
2406                              Register arg_2,
2407                              Register arg_3,
2408                              bool check_exceptions) {
2409   LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
2410   LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
2411   pass_arg3(this, arg_3);
2412   LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2413   pass_arg2(this, arg_2);
2414   pass_arg1(this, arg_1);
2415   call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
2416 }
2417 
2418 void MacroAssembler::super_call_VM(Register oop_result,
2419                                    Register last_java_sp,
2420                                    address entry_point,
2421                                    int number_of_arguments,
2422                                    bool check_exceptions) {
2423   Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg);
2424   MacroAssembler::call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions);
2425 }
2426 
2427 void MacroAssembler::super_call_VM(Register oop_result,
2428                                    Register last_java_sp,
2429                                    address entry_point,
2430                                    Register arg_1,
2431                                    bool check_exceptions) {
2432   pass_arg1(this, arg_1);
2433   super_call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
2434 }
2435 
2436 void MacroAssembler::super_call_VM(Register oop_result,
2437                                    Register last_java_sp,
2438                                    address entry_point,
2439                                    Register arg_1,
2440                                    Register arg_2,
2441                                    bool check_exceptions) {
2442 
2443   LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2444   pass_arg2(this, arg_2);
2445   pass_arg1(this, arg_1);
2446   super_call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
2447 }
2448 
2449 void MacroAssembler::super_call_VM(Register oop_result,
2450                                    Register last_java_sp,
2451                                    address entry_point,
2452                                    Register arg_1,
2453                                    Register arg_2,
2454                                    Register arg_3,
2455                                    bool check_exceptions) {
2456   LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
2457   LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
2458   pass_arg3(this, arg_3);
2459   LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2460   pass_arg2(this, arg_2);
2461   pass_arg1(this, arg_1);
2462   super_call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
2463 }
2464 
2465 void MacroAssembler::call_VM_base(Register oop_result,
2466                                   Register java_thread,
2467                                   Register last_java_sp,
2468                                   address  entry_point,
2469                                   int      number_of_arguments,
2470                                   bool     check_exceptions) {
2471   // determine java_thread register
2472   if (!java_thread->is_valid()) {
2473 #ifdef _LP64
2474     java_thread = r15_thread;
2475 #else
2476     java_thread = rdi;
2477     get_thread(java_thread);
2478 #endif // LP64
2479   }
2480   // determine last_java_sp register
2481   if (!last_java_sp->is_valid()) {
2482     last_java_sp = rsp;
2483   }
2484   // debugging support
2485   assert(number_of_arguments >= 0   , "cannot have negative number of arguments");
2486   LP64_ONLY(assert(java_thread == r15_thread, "unexpected register"));
2487 #ifdef ASSERT
2488   // TraceBytecodes does not use r12 but saves it over the call, so don't verify
2489   // r12 is the heapbase.
2490   LP64_ONLY(if ((UseCompressedOops || UseCompressedClassPointers) && !TraceBytecodes) verify_heapbase("call_VM_base: heap base corrupted?");)
2491 #endif // ASSERT
2492 
2493   assert(java_thread != oop_result  , "cannot use the same register for java_thread & oop_result");
2494   assert(java_thread != last_java_sp, "cannot use the same register for java_thread & last_java_sp");
2495 
2496   // push java thread (becomes first argument of C function)
2497 
2498   NOT_LP64(push(java_thread); number_of_arguments++);
2499   LP64_ONLY(mov(c_rarg0, r15_thread));
2500 
2501   // set last Java frame before call
2502   assert(last_java_sp != rbp, "can't use ebp/rbp");
2503 
2504   // Only interpreter should have to set fp
2505   set_last_Java_frame(java_thread, last_java_sp, rbp, NULL);
2506 
2507   // do the call, remove parameters
2508   MacroAssembler::call_VM_leaf_base(entry_point, number_of_arguments);
2509 
2510   // restore the thread (cannot use the pushed argument since arguments
2511   // may be overwritten by C code generated by an optimizing compiler);
2512   // however can use the register value directly if it is callee saved.
2513   if (LP64_ONLY(true ||) java_thread == rdi || java_thread == rsi) {
2514     // rdi & rsi (also r15) are callee saved -> nothing to do
2515 #ifdef ASSERT
2516     guarantee(java_thread != rax, "change this code");
2517     push(rax);
2518     { Label L;
2519       get_thread(rax);
2520       cmpptr(java_thread, rax);
2521       jcc(Assembler::equal, L);
2522       STOP("MacroAssembler::call_VM_base: rdi not callee saved?");
2523       bind(L);
2524     }
2525     pop(rax);
2526 #endif
2527   } else {
2528     get_thread(java_thread);
2529   }
2530   // reset last Java frame
2531   // Only interpreter should have to clear fp
2532   reset_last_Java_frame(java_thread, true);
2533 
2534    // C++ interp handles this in the interpreter
2535   check_and_handle_popframe(java_thread);
2536   check_and_handle_earlyret(java_thread);
2537 
2538   if (check_exceptions) {
2539     // check for pending exceptions (java_thread is set upon return)
2540     cmpptr(Address(java_thread, Thread::pending_exception_offset()), (int32_t) NULL_WORD);
2541 #ifndef _LP64
2542     jump_cc(Assembler::notEqual,
2543             RuntimeAddress(StubRoutines::forward_exception_entry()));
2544 #else
2545     // This used to conditionally jump to forward_exception however it is
2546     // possible if we relocate that the branch will not reach. So we must jump
2547     // around so we can always reach
2548 
2549     Label ok;
2550     jcc(Assembler::equal, ok);
2551     jump(RuntimeAddress(StubRoutines::forward_exception_entry()));
2552     bind(ok);
2553 #endif // LP64
2554   }
2555 
2556   // get oop result if there is one and reset the value in the thread
2557   if (oop_result->is_valid()) {
2558     get_vm_result(oop_result, java_thread);
2559   }
2560 }
2561 
2562 void MacroAssembler::call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) {
2563 
2564   // Calculate the value for last_Java_sp
2565   // somewhat subtle. call_VM does an intermediate call
2566   // which places a return address on the stack just under the
2567   // stack pointer as the user finsihed with it. This allows
2568   // use to retrieve last_Java_pc from last_Java_sp[-1].
2569   // On 32bit we then have to push additional args on the stack to accomplish
2570   // the actual requested call. On 64bit call_VM only can use register args
2571   // so the only extra space is the return address that call_VM created.
2572   // This hopefully explains the calculations here.
2573 
2574 #ifdef _LP64
2575   // We've pushed one address, correct last_Java_sp
2576   lea(rax, Address(rsp, wordSize));
2577 #else
2578   lea(rax, Address(rsp, (1 + number_of_arguments) * wordSize));
2579 #endif // LP64
2580 
2581   call_VM_base(oop_result, noreg, rax, entry_point, number_of_arguments, check_exceptions);
2582 
2583 }
2584 
2585 // Use this method when MacroAssembler version of call_VM_leaf_base() should be called from Interpreter.
2586 void MacroAssembler::call_VM_leaf0(address entry_point) {
2587   MacroAssembler::call_VM_leaf_base(entry_point, 0);
2588 }
2589 
2590 void MacroAssembler::call_VM_leaf(address entry_point, int number_of_arguments) {
2591   call_VM_leaf_base(entry_point, number_of_arguments);
2592 }
2593 
2594 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0) {
2595   pass_arg0(this, arg_0);
2596   call_VM_leaf(entry_point, 1);
2597 }
2598 
2599 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
2600 
2601   LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2602   pass_arg1(this, arg_1);
2603   pass_arg0(this, arg_0);
2604   call_VM_leaf(entry_point, 2);
2605 }
2606 
2607 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
2608   LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg"));
2609   LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2610   pass_arg2(this, arg_2);
2611   LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2612   pass_arg1(this, arg_1);
2613   pass_arg0(this, arg_0);
2614   call_VM_leaf(entry_point, 3);
2615 }
2616 
2617 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0) {
2618   pass_arg0(this, arg_0);
2619   MacroAssembler::call_VM_leaf_base(entry_point, 1);
2620 }
2621 
2622 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
2623 
2624   LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2625   pass_arg1(this, arg_1);
2626   pass_arg0(this, arg_0);
2627   MacroAssembler::call_VM_leaf_base(entry_point, 2);
2628 }
2629 
2630 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
2631   LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg"));
2632   LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2633   pass_arg2(this, arg_2);
2634   LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2635   pass_arg1(this, arg_1);
2636   pass_arg0(this, arg_0);
2637   MacroAssembler::call_VM_leaf_base(entry_point, 3);
2638 }
2639 
2640 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2, Register arg_3) {
2641   LP64_ONLY(assert(arg_0 != c_rarg3, "smashed arg"));
2642   LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
2643   LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
2644   pass_arg3(this, arg_3);
2645   LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg"));
2646   LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2647   pass_arg2(this, arg_2);
2648   LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2649   pass_arg1(this, arg_1);
2650   pass_arg0(this, arg_0);
2651   MacroAssembler::call_VM_leaf_base(entry_point, 4);
2652 }
2653 
2654 void MacroAssembler::get_vm_result(Register oop_result, Register java_thread) {
2655   movptr(oop_result, Address(java_thread, JavaThread::vm_result_offset()));
2656   movptr(Address(java_thread, JavaThread::vm_result_offset()), NULL_WORD);
2657   verify_oop(oop_result, "broken oop in call_VM_base");
2658 }
2659 
2660 void MacroAssembler::get_vm_result_2(Register metadata_result, Register java_thread) {
2661   movptr(metadata_result, Address(java_thread, JavaThread::vm_result_2_offset()));
2662   movptr(Address(java_thread, JavaThread::vm_result_2_offset()), NULL_WORD);
2663 }
2664 
2665 void MacroAssembler::check_and_handle_earlyret(Register java_thread) {
2666 }
2667 
2668 void MacroAssembler::check_and_handle_popframe(Register java_thread) {
2669 }
2670 
2671 void MacroAssembler::cmp32(AddressLiteral src1, int32_t imm) {
2672   if (reachable(src1)) {
2673     cmpl(as_Address(src1), imm);
2674   } else {
2675     lea(rscratch1, src1);
2676     cmpl(Address(rscratch1, 0), imm);
2677   }
2678 }
2679 
2680 void MacroAssembler::cmp32(Register src1, AddressLiteral src2) {
2681   assert(!src2.is_lval(), "use cmpptr");
2682   if (reachable(src2)) {
2683     cmpl(src1, as_Address(src2));
2684   } else {
2685     lea(rscratch1, src2);
2686     cmpl(src1, Address(rscratch1, 0));
2687   }
2688 }
2689 
2690 void MacroAssembler::cmp32(Register src1, int32_t imm) {
2691   Assembler::cmpl(src1, imm);
2692 }
2693 
2694 void MacroAssembler::cmp32(Register src1, Address src2) {
2695   Assembler::cmpl(src1, src2);
2696 }
2697 
2698 void MacroAssembler::cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) {
2699   ucomisd(opr1, opr2);
2700 
2701   Label L;
2702   if (unordered_is_less) {
2703     movl(dst, -1);
2704     jcc(Assembler::parity, L);
2705     jcc(Assembler::below , L);
2706     movl(dst, 0);
2707     jcc(Assembler::equal , L);
2708     increment(dst);
2709   } else { // unordered is greater
2710     movl(dst, 1);
2711     jcc(Assembler::parity, L);
2712     jcc(Assembler::above , L);
2713     movl(dst, 0);
2714     jcc(Assembler::equal , L);
2715     decrementl(dst);
2716   }
2717   bind(L);
2718 }
2719 
2720 void MacroAssembler::cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) {
2721   ucomiss(opr1, opr2);
2722 
2723   Label L;
2724   if (unordered_is_less) {
2725     movl(dst, -1);
2726     jcc(Assembler::parity, L);
2727     jcc(Assembler::below , L);
2728     movl(dst, 0);
2729     jcc(Assembler::equal , L);
2730     increment(dst);
2731   } else { // unordered is greater
2732     movl(dst, 1);
2733     jcc(Assembler::parity, L);
2734     jcc(Assembler::above , L);
2735     movl(dst, 0);
2736     jcc(Assembler::equal , L);
2737     decrementl(dst);
2738   }
2739   bind(L);
2740 }
2741 
2742 
2743 void MacroAssembler::cmp8(AddressLiteral src1, int imm) {
2744   if (reachable(src1)) {
2745     cmpb(as_Address(src1), imm);
2746   } else {
2747     lea(rscratch1, src1);
2748     cmpb(Address(rscratch1, 0), imm);
2749   }
2750 }
2751 
2752 void MacroAssembler::cmpptr(Register src1, AddressLiteral src2) {
2753 #ifdef _LP64
2754   if (src2.is_lval()) {
2755     movptr(rscratch1, src2);
2756     Assembler::cmpq(src1, rscratch1);
2757   } else if (reachable(src2)) {
2758     cmpq(src1, as_Address(src2));
2759   } else {
2760     lea(rscratch1, src2);
2761     Assembler::cmpq(src1, Address(rscratch1, 0));
2762   }
2763 #else
2764   if (src2.is_lval()) {
2765     cmp_literal32(src1, (int32_t) src2.target(), src2.rspec());
2766   } else {
2767     cmpl(src1, as_Address(src2));
2768   }
2769 #endif // _LP64
2770 }
2771 
2772 void MacroAssembler::cmpptr(Address src1, AddressLiteral src2) {
2773   assert(src2.is_lval(), "not a mem-mem compare");
2774 #ifdef _LP64
2775   // moves src2's literal address
2776   movptr(rscratch1, src2);
2777   Assembler::cmpq(src1, rscratch1);
2778 #else
2779   cmp_literal32(src1, (int32_t) src2.target(), src2.rspec());
2780 #endif // _LP64
2781 }
2782 
2783 void MacroAssembler::locked_cmpxchgptr(Register reg, AddressLiteral adr) {
2784   if (reachable(adr)) {
2785     if (os::is_MP())
2786       lock();
2787     cmpxchgptr(reg, as_Address(adr));
2788   } else {
2789     lea(rscratch1, adr);
2790     if (os::is_MP())
2791       lock();
2792     cmpxchgptr(reg, Address(rscratch1, 0));
2793   }
2794 }
2795 
2796 void MacroAssembler::cmpxchgptr(Register reg, Address adr) {
2797   LP64_ONLY(cmpxchgq(reg, adr)) NOT_LP64(cmpxchgl(reg, adr));
2798 }
2799 
2800 void MacroAssembler::comisd(XMMRegister dst, AddressLiteral src) {
2801   if (reachable(src)) {
2802     Assembler::comisd(dst, as_Address(src));
2803   } else {
2804     lea(rscratch1, src);
2805     Assembler::comisd(dst, Address(rscratch1, 0));
2806   }
2807 }
2808 
2809 void MacroAssembler::comiss(XMMRegister dst, AddressLiteral src) {
2810   if (reachable(src)) {
2811     Assembler::comiss(dst, as_Address(src));
2812   } else {
2813     lea(rscratch1, src);
2814     Assembler::comiss(dst, Address(rscratch1, 0));
2815   }
2816 }
2817 
2818 
2819 void MacroAssembler::cond_inc32(Condition cond, AddressLiteral counter_addr) {
2820   Condition negated_cond = negate_condition(cond);
2821   Label L;
2822   jcc(negated_cond, L);
2823   pushf(); // Preserve flags
2824   atomic_incl(counter_addr);
2825   popf();
2826   bind(L);
2827 }
2828 
2829 int MacroAssembler::corrected_idivl(Register reg) {
2830   // Full implementation of Java idiv and irem; checks for
2831   // special case as described in JVM spec., p.243 & p.271.
2832   // The function returns the (pc) offset of the idivl
2833   // instruction - may be needed for implicit exceptions.
2834   //
2835   //         normal case                           special case
2836   //
2837   // input : rax,: dividend                         min_int
2838   //         reg: divisor   (may not be rax,/rdx)   -1
2839   //
2840   // output: rax,: quotient  (= rax, idiv reg)       min_int
2841   //         rdx: remainder (= rax, irem reg)       0
2842   assert(reg != rax && reg != rdx, "reg cannot be rax, or rdx register");
2843   const int min_int = 0x80000000;
2844   Label normal_case, special_case;
2845 
2846   // check for special case
2847   cmpl(rax, min_int);
2848   jcc(Assembler::notEqual, normal_case);
2849   xorl(rdx, rdx); // prepare rdx for possible special case (where remainder = 0)
2850   cmpl(reg, -1);
2851   jcc(Assembler::equal, special_case);
2852 
2853   // handle normal case
2854   bind(normal_case);
2855   cdql();
2856   int idivl_offset = offset();
2857   idivl(reg);
2858 
2859   // normal and special case exit
2860   bind(special_case);
2861 
2862   return idivl_offset;
2863 }
2864 
2865 
2866 
2867 void MacroAssembler::decrementl(Register reg, int value) {
2868   if (value == min_jint) {subl(reg, value) ; return; }
2869   if (value <  0) { incrementl(reg, -value); return; }
2870   if (value == 0) {                        ; return; }
2871   if (value == 1 && UseIncDec) { decl(reg) ; return; }
2872   /* else */      { subl(reg, value)       ; return; }
2873 }
2874 
2875 void MacroAssembler::decrementl(Address dst, int value) {
2876   if (value == min_jint) {subl(dst, value) ; return; }
2877   if (value <  0) { incrementl(dst, -value); return; }
2878   if (value == 0) {                        ; return; }
2879   if (value == 1 && UseIncDec) { decl(dst) ; return; }
2880   /* else */      { subl(dst, value)       ; return; }
2881 }
2882 
2883 void MacroAssembler::division_with_shift (Register reg, int shift_value) {
2884   assert (shift_value > 0, "illegal shift value");
2885   Label _is_positive;
2886   testl (reg, reg);
2887   jcc (Assembler::positive, _is_positive);
2888   int offset = (1 << shift_value) - 1 ;
2889 
2890   if (offset == 1) {
2891     incrementl(reg);
2892   } else {
2893     addl(reg, offset);
2894   }
2895 
2896   bind (_is_positive);
2897   sarl(reg, shift_value);
2898 }
2899 
2900 void MacroAssembler::divsd(XMMRegister dst, AddressLiteral src) {
2901   if (reachable(src)) {
2902     Assembler::divsd(dst, as_Address(src));
2903   } else {
2904     lea(rscratch1, src);
2905     Assembler::divsd(dst, Address(rscratch1, 0));
2906   }
2907 }
2908 
2909 void MacroAssembler::divss(XMMRegister dst, AddressLiteral src) {
2910   if (reachable(src)) {
2911     Assembler::divss(dst, as_Address(src));
2912   } else {
2913     lea(rscratch1, src);
2914     Assembler::divss(dst, Address(rscratch1, 0));
2915   }
2916 }
2917 
2918 // !defined(COMPILER2) is because of stupid core builds
2919 #if !defined(_LP64) || defined(COMPILER1) || !defined(COMPILER2) || INCLUDE_JVMCI
2920 void MacroAssembler::empty_FPU_stack() {
2921   if (VM_Version::supports_mmx()) {
2922     emms();
2923   } else {
2924     for (int i = 8; i-- > 0; ) ffree(i);
2925   }
2926 }
2927 #endif // !LP64 || C1 || !C2 || INCLUDE_JVMCI
2928 
2929 
2930 // Defines obj, preserves var_size_in_bytes
2931 void MacroAssembler::eden_allocate(Register obj,
2932                                    Register var_size_in_bytes,
2933                                    int con_size_in_bytes,
2934                                    Register t1,
2935                                    Label& slow_case) {
2936   assert(obj == rax, "obj must be in rax, for cmpxchg");
2937   assert_different_registers(obj, var_size_in_bytes, t1);
2938   if (!Universe::heap()->supports_inline_contig_alloc()) {
2939     jmp(slow_case);
2940   } else {
2941     Register end = t1;
2942     Label retry;
2943     bind(retry);
2944     ExternalAddress heap_top((address) Universe::heap()->top_addr());
2945     movptr(obj, heap_top);
2946     if (var_size_in_bytes == noreg) {
2947       lea(end, Address(obj, con_size_in_bytes));
2948     } else {
2949       lea(end, Address(obj, var_size_in_bytes, Address::times_1));
2950     }
2951     // if end < obj then we wrapped around => object too long => slow case
2952     cmpptr(end, obj);
2953     jcc(Assembler::below, slow_case);
2954     cmpptr(end, ExternalAddress((address) Universe::heap()->end_addr()));
2955     jcc(Assembler::above, slow_case);
2956     // Compare obj with the top addr, and if still equal, store the new top addr in
2957     // end at the address of the top addr pointer. Sets ZF if was equal, and clears
2958     // it otherwise. Use lock prefix for atomicity on MPs.
2959     locked_cmpxchgptr(end, heap_top);
2960     jcc(Assembler::notEqual, retry);
2961   }
2962 }
2963 
2964 void MacroAssembler::enter() {
2965   push(rbp);
2966   mov(rbp, rsp);
2967 }
2968 
2969 // A 5 byte nop that is safe for patching (see patch_verified_entry)
2970 void MacroAssembler::fat_nop() {
2971   if (UseAddressNop) {
2972     addr_nop_5();
2973   } else {
2974     emit_int8(0x26); // es:
2975     emit_int8(0x2e); // cs:
2976     emit_int8(0x64); // fs:
2977     emit_int8(0x65); // gs:
2978     emit_int8((unsigned char)0x90);
2979   }
2980 }
2981 
2982 void MacroAssembler::fcmp(Register tmp) {
2983   fcmp(tmp, 1, true, true);
2984 }
2985 
2986 void MacroAssembler::fcmp(Register tmp, int index, bool pop_left, bool pop_right) {
2987   assert(!pop_right || pop_left, "usage error");
2988   if (VM_Version::supports_cmov()) {
2989     assert(tmp == noreg, "unneeded temp");
2990     if (pop_left) {
2991       fucomip(index);
2992     } else {
2993       fucomi(index);
2994     }
2995     if (pop_right) {
2996       fpop();
2997     }
2998   } else {
2999     assert(tmp != noreg, "need temp");
3000     if (pop_left) {
3001       if (pop_right) {
3002         fcompp();
3003       } else {
3004         fcomp(index);
3005       }
3006     } else {
3007       fcom(index);
3008     }
3009     // convert FPU condition into eflags condition via rax,
3010     save_rax(tmp);
3011     fwait(); fnstsw_ax();
3012     sahf();
3013     restore_rax(tmp);
3014   }
3015   // condition codes set as follows:
3016   //
3017   // CF (corresponds to C0) if x < y
3018   // PF (corresponds to C2) if unordered
3019   // ZF (corresponds to C3) if x = y
3020 }
3021 
3022 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less) {
3023   fcmp2int(dst, unordered_is_less, 1, true, true);
3024 }
3025 
3026 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right) {
3027   fcmp(VM_Version::supports_cmov() ? noreg : dst, index, pop_left, pop_right);
3028   Label L;
3029   if (unordered_is_less) {
3030     movl(dst, -1);
3031     jcc(Assembler::parity, L);
3032     jcc(Assembler::below , L);
3033     movl(dst, 0);
3034     jcc(Assembler::equal , L);
3035     increment(dst);
3036   } else { // unordered is greater
3037     movl(dst, 1);
3038     jcc(Assembler::parity, L);
3039     jcc(Assembler::above , L);
3040     movl(dst, 0);
3041     jcc(Assembler::equal , L);
3042     decrementl(dst);
3043   }
3044   bind(L);
3045 }
3046 
3047 void MacroAssembler::fld_d(AddressLiteral src) {
3048   fld_d(as_Address(src));
3049 }
3050 
3051 void MacroAssembler::fld_s(AddressLiteral src) {
3052   fld_s(as_Address(src));
3053 }
3054 
3055 void MacroAssembler::fld_x(AddressLiteral src) {
3056   Assembler::fld_x(as_Address(src));
3057 }
3058 
3059 void MacroAssembler::fldcw(AddressLiteral src) {
3060   Assembler::fldcw(as_Address(src));
3061 }
3062 
3063 void MacroAssembler::mulpd(XMMRegister dst, AddressLiteral src) {
3064   if (reachable(src)) {
3065     Assembler::mulpd(dst, as_Address(src));
3066   } else {
3067     lea(rscratch1, src);
3068     Assembler::mulpd(dst, Address(rscratch1, 0));
3069   }
3070 }
3071 
3072 void MacroAssembler::increase_precision() {
3073   subptr(rsp, BytesPerWord);
3074   fnstcw(Address(rsp, 0));
3075   movl(rax, Address(rsp, 0));
3076   orl(rax, 0x300);
3077   push(rax);
3078   fldcw(Address(rsp, 0));
3079   pop(rax);
3080 }
3081 
3082 void MacroAssembler::restore_precision() {
3083   fldcw(Address(rsp, 0));
3084   addptr(rsp, BytesPerWord);
3085 }
3086 
3087 void MacroAssembler::fpop() {
3088   ffree();
3089   fincstp();
3090 }
3091 
3092 void MacroAssembler::load_float(Address src) {
3093   if (UseSSE >= 1) {
3094     movflt(xmm0, src);
3095   } else {
3096     LP64_ONLY(ShouldNotReachHere());
3097     NOT_LP64(fld_s(src));
3098   }
3099 }
3100 
3101 void MacroAssembler::store_float(Address dst) {
3102   if (UseSSE >= 1) {
3103     movflt(dst, xmm0);
3104   } else {
3105     LP64_ONLY(ShouldNotReachHere());
3106     NOT_LP64(fstp_s(dst));
3107   }
3108 }
3109 
3110 void MacroAssembler::load_double(Address src) {
3111   if (UseSSE >= 2) {
3112     movdbl(xmm0, src);
3113   } else {
3114     LP64_ONLY(ShouldNotReachHere());
3115     NOT_LP64(fld_d(src));
3116   }
3117 }
3118 
3119 void MacroAssembler::store_double(Address dst) {
3120   if (UseSSE >= 2) {
3121     movdbl(dst, xmm0);
3122   } else {
3123     LP64_ONLY(ShouldNotReachHere());
3124     NOT_LP64(fstp_d(dst));
3125   }
3126 }
3127 
3128 void MacroAssembler::fremr(Register tmp) {
3129   save_rax(tmp);
3130   { Label L;
3131     bind(L);
3132     fprem();
3133     fwait(); fnstsw_ax();
3134 #ifdef _LP64
3135     testl(rax, 0x400);
3136     jcc(Assembler::notEqual, L);
3137 #else
3138     sahf();
3139     jcc(Assembler::parity, L);
3140 #endif // _LP64
3141   }
3142   restore_rax(tmp);
3143   // Result is in ST0.
3144   // Note: fxch & fpop to get rid of ST1
3145   // (otherwise FPU stack could overflow eventually)
3146   fxch(1);
3147   fpop();
3148 }
3149 
3150 // dst = c = a * b + c
3151 void MacroAssembler::fmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c) {
3152   Assembler::vfmadd231sd(c, a, b);
3153   if (dst != c) {
3154     movdbl(dst, c);
3155   }
3156 }
3157 
3158 // dst = c = a * b + c
3159 void MacroAssembler::fmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c) {
3160   Assembler::vfmadd231ss(c, a, b);
3161   if (dst != c) {
3162     movflt(dst, c);
3163   }
3164 }
3165 
3166 
3167 
3168 
3169 void MacroAssembler::incrementl(AddressLiteral dst) {
3170   if (reachable(dst)) {
3171     incrementl(as_Address(dst));
3172   } else {
3173     lea(rscratch1, dst);
3174     incrementl(Address(rscratch1, 0));
3175   }
3176 }
3177 
3178 void MacroAssembler::incrementl(ArrayAddress dst) {
3179   incrementl(as_Address(dst));
3180 }
3181 
3182 void MacroAssembler::incrementl(Register reg, int value) {
3183   if (value == min_jint) {addl(reg, value) ; return; }
3184   if (value <  0) { decrementl(reg, -value); return; }
3185   if (value == 0) {                        ; return; }
3186   if (value == 1 && UseIncDec) { incl(reg) ; return; }
3187   /* else */      { addl(reg, value)       ; return; }
3188 }
3189 
3190 void MacroAssembler::incrementl(Address dst, int value) {
3191   if (value == min_jint) {addl(dst, value) ; return; }
3192   if (value <  0) { decrementl(dst, -value); return; }
3193   if (value == 0) {                        ; return; }
3194   if (value == 1 && UseIncDec) { incl(dst) ; return; }
3195   /* else */      { addl(dst, value)       ; return; }
3196 }
3197 
3198 void MacroAssembler::jump(AddressLiteral dst) {
3199   if (reachable(dst)) {
3200     jmp_literal(dst.target(), dst.rspec());
3201   } else {
3202     lea(rscratch1, dst);
3203     jmp(rscratch1);
3204   }
3205 }
3206 
3207 void MacroAssembler::jump_cc(Condition cc, AddressLiteral dst) {
3208   if (reachable(dst)) {
3209     InstructionMark im(this);
3210     relocate(dst.reloc());
3211     const int short_size = 2;
3212     const int long_size = 6;
3213     int offs = (intptr_t)dst.target() - ((intptr_t)pc());
3214     if (dst.reloc() == relocInfo::none && is8bit(offs - short_size)) {
3215       // 0111 tttn #8-bit disp
3216       emit_int8(0x70 | cc);
3217       emit_int8((offs - short_size) & 0xFF);
3218     } else {
3219       // 0000 1111 1000 tttn #32-bit disp
3220       emit_int8(0x0F);
3221       emit_int8((unsigned char)(0x80 | cc));
3222       emit_int32(offs - long_size);
3223     }
3224   } else {
3225 #ifdef ASSERT
3226     warning("reversing conditional branch");
3227 #endif /* ASSERT */
3228     Label skip;
3229     jccb(reverse[cc], skip);
3230     lea(rscratch1, dst);
3231     Assembler::jmp(rscratch1);
3232     bind(skip);
3233   }
3234 }
3235 
3236 void MacroAssembler::ldmxcsr(AddressLiteral src) {
3237   if (reachable(src)) {
3238     Assembler::ldmxcsr(as_Address(src));
3239   } else {
3240     lea(rscratch1, src);
3241     Assembler::ldmxcsr(Address(rscratch1, 0));
3242   }
3243 }
3244 
3245 int MacroAssembler::load_signed_byte(Register dst, Address src) {
3246   int off;
3247   if (LP64_ONLY(true ||) VM_Version::is_P6()) {
3248     off = offset();
3249     movsbl(dst, src); // movsxb
3250   } else {
3251     off = load_unsigned_byte(dst, src);
3252     shll(dst, 24);
3253     sarl(dst, 24);
3254   }
3255   return off;
3256 }
3257 
3258 // Note: load_signed_short used to be called load_signed_word.
3259 // Although the 'w' in x86 opcodes refers to the term "word" in the assembler
3260 // manual, which means 16 bits, that usage is found nowhere in HotSpot code.
3261 // The term "word" in HotSpot means a 32- or 64-bit machine word.
3262 int MacroAssembler::load_signed_short(Register dst, Address src) {
3263   int off;
3264   if (LP64_ONLY(true ||) VM_Version::is_P6()) {
3265     // This is dubious to me since it seems safe to do a signed 16 => 64 bit
3266     // version but this is what 64bit has always done. This seems to imply
3267     // that users are only using 32bits worth.
3268     off = offset();
3269     movswl(dst, src); // movsxw
3270   } else {
3271     off = load_unsigned_short(dst, src);
3272     shll(dst, 16);
3273     sarl(dst, 16);
3274   }
3275   return off;
3276 }
3277 
3278 int MacroAssembler::load_unsigned_byte(Register dst, Address src) {
3279   // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16,
3280   // and "3.9 Partial Register Penalties", p. 22).
3281   int off;
3282   if (LP64_ONLY(true || ) VM_Version::is_P6() || src.uses(dst)) {
3283     off = offset();
3284     movzbl(dst, src); // movzxb
3285   } else {
3286     xorl(dst, dst);
3287     off = offset();
3288     movb(dst, src);
3289   }
3290   return off;
3291 }
3292 
3293 // Note: load_unsigned_short used to be called load_unsigned_word.
3294 int MacroAssembler::load_unsigned_short(Register dst, Address src) {
3295   // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16,
3296   // and "3.9 Partial Register Penalties", p. 22).
3297   int off;
3298   if (LP64_ONLY(true ||) VM_Version::is_P6() || src.uses(dst)) {
3299     off = offset();
3300     movzwl(dst, src); // movzxw
3301   } else {
3302     xorl(dst, dst);
3303     off = offset();
3304     movw(dst, src);
3305   }
3306   return off;
3307 }
3308 
3309 void MacroAssembler::load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2) {
3310   switch (size_in_bytes) {
3311 #ifndef _LP64
3312   case  8:
3313     assert(dst2 != noreg, "second dest register required");
3314     movl(dst,  src);
3315     movl(dst2, src.plus_disp(BytesPerInt));
3316     break;
3317 #else
3318   case  8:  movq(dst, src); break;
3319 #endif
3320   case  4:  movl(dst, src); break;
3321   case  2:  is_signed ? load_signed_short(dst, src) : load_unsigned_short(dst, src); break;
3322   case  1:  is_signed ? load_signed_byte( dst, src) : load_unsigned_byte( dst, src); break;
3323   default:  ShouldNotReachHere();
3324   }
3325 }
3326 
3327 void MacroAssembler::store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2) {
3328   switch (size_in_bytes) {
3329 #ifndef _LP64
3330   case  8:
3331     assert(src2 != noreg, "second source register required");
3332     movl(dst,                        src);
3333     movl(dst.plus_disp(BytesPerInt), src2);
3334     break;
3335 #else
3336   case  8:  movq(dst, src); break;
3337 #endif
3338   case  4:  movl(dst, src); break;
3339   case  2:  movw(dst, src); break;
3340   case  1:  movb(dst, src); break;
3341   default:  ShouldNotReachHere();
3342   }
3343 }
3344 
3345 void MacroAssembler::mov32(AddressLiteral dst, Register src) {
3346   if (reachable(dst)) {
3347     movl(as_Address(dst), src);
3348   } else {
3349     lea(rscratch1, dst);
3350     movl(Address(rscratch1, 0), src);
3351   }
3352 }
3353 
3354 void MacroAssembler::mov32(Register dst, AddressLiteral src) {
3355   if (reachable(src)) {
3356     movl(dst, as_Address(src));
3357   } else {
3358     lea(rscratch1, src);
3359     movl(dst, Address(rscratch1, 0));
3360   }
3361 }
3362 
3363 // C++ bool manipulation
3364 
3365 void MacroAssembler::movbool(Register dst, Address src) {
3366   if(sizeof(bool) == 1)
3367     movb(dst, src);
3368   else if(sizeof(bool) == 2)
3369     movw(dst, src);
3370   else if(sizeof(bool) == 4)
3371     movl(dst, src);
3372   else
3373     // unsupported
3374     ShouldNotReachHere();
3375 }
3376 
3377 void MacroAssembler::movbool(Address dst, bool boolconst) {
3378   if(sizeof(bool) == 1)
3379     movb(dst, (int) boolconst);
3380   else if(sizeof(bool) == 2)
3381     movw(dst, (int) boolconst);
3382   else if(sizeof(bool) == 4)
3383     movl(dst, (int) boolconst);
3384   else
3385     // unsupported
3386     ShouldNotReachHere();
3387 }
3388 
3389 void MacroAssembler::movbool(Address dst, Register src) {
3390   if(sizeof(bool) == 1)
3391     movb(dst, src);
3392   else if(sizeof(bool) == 2)
3393     movw(dst, src);
3394   else if(sizeof(bool) == 4)
3395     movl(dst, src);
3396   else
3397     // unsupported
3398     ShouldNotReachHere();
3399 }
3400 
3401 void MacroAssembler::movbyte(ArrayAddress dst, int src) {
3402   movb(as_Address(dst), src);
3403 }
3404 
3405 void MacroAssembler::movdl(XMMRegister dst, AddressLiteral src) {
3406   if (reachable(src)) {
3407     movdl(dst, as_Address(src));
3408   } else {
3409     lea(rscratch1, src);
3410     movdl(dst, Address(rscratch1, 0));
3411   }
3412 }
3413 
3414 void MacroAssembler::movq(XMMRegister dst, AddressLiteral src) {
3415   if (reachable(src)) {
3416     movq(dst, as_Address(src));
3417   } else {
3418     lea(rscratch1, src);
3419     movq(dst, Address(rscratch1, 0));
3420   }
3421 }
3422 
3423 void MacroAssembler::setvectmask(Register dst, Register src) {
3424   Assembler::movl(dst, 1);
3425   Assembler::shlxl(dst, dst, src);
3426   Assembler::decl(dst);
3427   Assembler::kmovdl(k1, dst);
3428   Assembler::movl(dst, src);
3429 }
3430 
3431 void MacroAssembler::restorevectmask() {
3432   Assembler::knotwl(k1, k0);
3433 }
3434 
3435 void MacroAssembler::movdbl(XMMRegister dst, AddressLiteral src) {
3436   if (reachable(src)) {
3437     if (UseXmmLoadAndClearUpper) {
3438       movsd (dst, as_Address(src));
3439     } else {
3440       movlpd(dst, as_Address(src));
3441     }
3442   } else {
3443     lea(rscratch1, src);
3444     if (UseXmmLoadAndClearUpper) {
3445       movsd (dst, Address(rscratch1, 0));
3446     } else {
3447       movlpd(dst, Address(rscratch1, 0));
3448     }
3449   }
3450 }
3451 
3452 void MacroAssembler::movflt(XMMRegister dst, AddressLiteral src) {
3453   if (reachable(src)) {
3454     movss(dst, as_Address(src));
3455   } else {
3456     lea(rscratch1, src);
3457     movss(dst, Address(rscratch1, 0));
3458   }
3459 }
3460 
3461 void MacroAssembler::movptr(Register dst, Register src) {
3462   LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
3463 }
3464 
3465 void MacroAssembler::movptr(Register dst, Address src) {
3466   LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
3467 }
3468 
3469 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
3470 void MacroAssembler::movptr(Register dst, intptr_t src) {
3471   LP64_ONLY(mov64(dst, src)) NOT_LP64(movl(dst, src));
3472 }
3473 
3474 void MacroAssembler::movptr(Address dst, Register src) {
3475   LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
3476 }
3477 
3478 void MacroAssembler::movdqu(Address dst, XMMRegister src) {
3479   if (UseAVX > 2 && !VM_Version::supports_avx512vl() && (src->encoding() > 15)) {
3480     Assembler::vextractf32x4(dst, src, 0);
3481   } else {
3482     Assembler::movdqu(dst, src);
3483   }
3484 }
3485 
3486 void MacroAssembler::movdqu(XMMRegister dst, Address src) {
3487   if (UseAVX > 2 && !VM_Version::supports_avx512vl() && (dst->encoding() > 15)) {
3488     Assembler::vinsertf32x4(dst, dst, src, 0);
3489   } else {
3490     Assembler::movdqu(dst, src);
3491   }
3492 }
3493 
3494 void MacroAssembler::movdqu(XMMRegister dst, XMMRegister src) {
3495   if (UseAVX > 2 && !VM_Version::supports_avx512vl()) {
3496     Assembler::evmovdqul(dst, src, Assembler::AVX_512bit);
3497   } else {
3498     Assembler::movdqu(dst, src);
3499   }
3500 }
3501 
3502 void MacroAssembler::movdqu(XMMRegister dst, AddressLiteral src) {
3503   if (reachable(src)) {
3504     movdqu(dst, as_Address(src));
3505   } else {
3506     lea(rscratch1, src);
3507     movdqu(dst, Address(rscratch1, 0));
3508   }
3509 }
3510 
3511 void MacroAssembler::vmovdqu(Address dst, XMMRegister src) {
3512   if (UseAVX > 2 && !VM_Version::supports_avx512vl() && (src->encoding() > 15)) {
3513     vextractf64x4_low(dst, src);
3514   } else {
3515     Assembler::vmovdqu(dst, src);
3516   }
3517 }
3518 
3519 void MacroAssembler::vmovdqu(XMMRegister dst, Address src) {
3520   if (UseAVX > 2 && !VM_Version::supports_avx512vl() && (dst->encoding() > 15)) {
3521     vinsertf64x4_low(dst, src);
3522   } else {
3523     Assembler::vmovdqu(dst, src);
3524   }
3525 }
3526 
3527 void MacroAssembler::vmovdqu(XMMRegister dst, XMMRegister src) {
3528   if (UseAVX > 2 && !VM_Version::supports_avx512vl()) {
3529     Assembler::evmovdqul(dst, src, Assembler::AVX_512bit);
3530   }
3531   else {
3532     Assembler::vmovdqu(dst, src);
3533   }
3534 }
3535 
3536 void MacroAssembler::vmovdqu(XMMRegister dst, AddressLiteral src) {
3537   if (reachable(src)) {
3538     vmovdqu(dst, as_Address(src));
3539   }
3540   else {
3541     lea(rscratch1, src);
3542     vmovdqu(dst, Address(rscratch1, 0));
3543   }
3544 }
3545 
3546 void MacroAssembler::movdqa(XMMRegister dst, AddressLiteral src) {
3547   if (reachable(src)) {
3548     Assembler::movdqa(dst, as_Address(src));
3549   } else {
3550     lea(rscratch1, src);
3551     Assembler::movdqa(dst, Address(rscratch1, 0));
3552   }
3553 }
3554 
3555 void MacroAssembler::movsd(XMMRegister dst, AddressLiteral src) {
3556   if (reachable(src)) {
3557     Assembler::movsd(dst, as_Address(src));
3558   } else {
3559     lea(rscratch1, src);
3560     Assembler::movsd(dst, Address(rscratch1, 0));
3561   }
3562 }
3563 
3564 void MacroAssembler::movss(XMMRegister dst, AddressLiteral src) {
3565   if (reachable(src)) {
3566     Assembler::movss(dst, as_Address(src));
3567   } else {
3568     lea(rscratch1, src);
3569     Assembler::movss(dst, Address(rscratch1, 0));
3570   }
3571 }
3572 
3573 void MacroAssembler::mulsd(XMMRegister dst, AddressLiteral src) {
3574   if (reachable(src)) {
3575     Assembler::mulsd(dst, as_Address(src));
3576   } else {
3577     lea(rscratch1, src);
3578     Assembler::mulsd(dst, Address(rscratch1, 0));
3579   }
3580 }
3581 
3582 void MacroAssembler::mulss(XMMRegister dst, AddressLiteral src) {
3583   if (reachable(src)) {
3584     Assembler::mulss(dst, as_Address(src));
3585   } else {
3586     lea(rscratch1, src);
3587     Assembler::mulss(dst, Address(rscratch1, 0));
3588   }
3589 }
3590 
3591 void MacroAssembler::null_check(Register reg, int offset) {
3592   if (needs_explicit_null_check(offset)) {
3593     // provoke OS NULL exception if reg = NULL by
3594     // accessing M[reg] w/o changing any (non-CC) registers
3595     // NOTE: cmpl is plenty here to provoke a segv
3596     cmpptr(rax, Address(reg, 0));
3597     // Note: should probably use testl(rax, Address(reg, 0));
3598     //       may be shorter code (however, this version of
3599     //       testl needs to be implemented first)
3600   } else {
3601     // nothing to do, (later) access of M[reg + offset]
3602     // will provoke OS NULL exception if reg = NULL
3603   }
3604 }
3605 
3606 void MacroAssembler::os_breakpoint() {
3607   // instead of directly emitting a breakpoint, call os:breakpoint for better debugability
3608   // (e.g., MSVC can't call ps() otherwise)
3609   call(RuntimeAddress(CAST_FROM_FN_PTR(address, os::breakpoint)));
3610 }
3611 
3612 #ifdef _LP64
3613 #define XSTATE_BV 0x200
3614 #endif
3615 
3616 void MacroAssembler::pop_CPU_state() {
3617   pop_FPU_state();
3618   pop_IU_state();
3619 }
3620 
3621 void MacroAssembler::pop_FPU_state() {
3622 #ifndef _LP64
3623   frstor(Address(rsp, 0));
3624 #else
3625   fxrstor(Address(rsp, 0));
3626 #endif
3627   addptr(rsp, FPUStateSizeInWords * wordSize);
3628 }
3629 
3630 void MacroAssembler::pop_IU_state() {
3631   popa();
3632   LP64_ONLY(addq(rsp, 8));
3633   popf();
3634 }
3635 
3636 // Save Integer and Float state
3637 // Warning: Stack must be 16 byte aligned (64bit)
3638 void MacroAssembler::push_CPU_state() {
3639   push_IU_state();
3640   push_FPU_state();
3641 }
3642 
3643 void MacroAssembler::push_FPU_state() {
3644   subptr(rsp, FPUStateSizeInWords * wordSize);
3645 #ifndef _LP64
3646   fnsave(Address(rsp, 0));
3647   fwait();
3648 #else
3649   fxsave(Address(rsp, 0));
3650 #endif // LP64
3651 }
3652 
3653 void MacroAssembler::push_IU_state() {
3654   // Push flags first because pusha kills them
3655   pushf();
3656   // Make sure rsp stays 16-byte aligned
3657   LP64_ONLY(subq(rsp, 8));
3658   pusha();
3659 }
3660 
3661 void MacroAssembler::reset_last_Java_frame(Register java_thread, bool clear_fp) { // determine java_thread register
3662   if (!java_thread->is_valid()) {
3663     java_thread = rdi;
3664     get_thread(java_thread);
3665   }
3666   // we must set sp to zero to clear frame
3667   movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), NULL_WORD);
3668   if (clear_fp) {
3669     movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), NULL_WORD);
3670   }
3671 
3672   // Always clear the pc because it could have been set by make_walkable()
3673   movptr(Address(java_thread, JavaThread::last_Java_pc_offset()), NULL_WORD);
3674 
3675 }
3676 
3677 void MacroAssembler::restore_rax(Register tmp) {
3678   if (tmp == noreg) pop(rax);
3679   else if (tmp != rax) mov(rax, tmp);
3680 }
3681 
3682 void MacroAssembler::round_to(Register reg, int modulus) {
3683   addptr(reg, modulus - 1);
3684   andptr(reg, -modulus);
3685 }
3686 
3687 void MacroAssembler::save_rax(Register tmp) {
3688   if (tmp == noreg) push(rax);
3689   else if (tmp != rax) mov(tmp, rax);
3690 }
3691 
3692 // Write serialization page so VM thread can do a pseudo remote membar.
3693 // We use the current thread pointer to calculate a thread specific
3694 // offset to write to within the page. This minimizes bus traffic
3695 // due to cache line collision.
3696 void MacroAssembler::serialize_memory(Register thread, Register tmp) {
3697   movl(tmp, thread);
3698   shrl(tmp, os::get_serialize_page_shift_count());
3699   andl(tmp, (os::vm_page_size() - sizeof(int)));
3700 
3701   Address index(noreg, tmp, Address::times_1);
3702   ExternalAddress page(os::get_memory_serialize_page());
3703 
3704   // Size of store must match masking code above
3705   movl(as_Address(ArrayAddress(page, index)), tmp);
3706 }
3707 
3708 // Calls to C land
3709 //
3710 // When entering C land, the rbp, & rsp of the last Java frame have to be recorded
3711 // in the (thread-local) JavaThread object. When leaving C land, the last Java fp
3712 // has to be reset to 0. This is required to allow proper stack traversal.
3713 void MacroAssembler::set_last_Java_frame(Register java_thread,
3714                                          Register last_java_sp,
3715                                          Register last_java_fp,
3716                                          address  last_java_pc) {
3717   // determine java_thread register
3718   if (!java_thread->is_valid()) {
3719     java_thread = rdi;
3720     get_thread(java_thread);
3721   }
3722   // determine last_java_sp register
3723   if (!last_java_sp->is_valid()) {
3724     last_java_sp = rsp;
3725   }
3726 
3727   // last_java_fp is optional
3728 
3729   if (last_java_fp->is_valid()) {
3730     movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), last_java_fp);
3731   }
3732 
3733   // last_java_pc is optional
3734 
3735   if (last_java_pc != NULL) {
3736     lea(Address(java_thread,
3737                  JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset()),
3738         InternalAddress(last_java_pc));
3739 
3740   }
3741   movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), last_java_sp);
3742 }
3743 
3744 void MacroAssembler::shlptr(Register dst, int imm8) {
3745   LP64_ONLY(shlq(dst, imm8)) NOT_LP64(shll(dst, imm8));
3746 }
3747 
3748 void MacroAssembler::shrptr(Register dst, int imm8) {
3749   LP64_ONLY(shrq(dst, imm8)) NOT_LP64(shrl(dst, imm8));
3750 }
3751 
3752 void MacroAssembler::sign_extend_byte(Register reg) {
3753   if (LP64_ONLY(true ||) (VM_Version::is_P6() && reg->has_byte_register())) {
3754     movsbl(reg, reg); // movsxb
3755   } else {
3756     shll(reg, 24);
3757     sarl(reg, 24);
3758   }
3759 }
3760 
3761 void MacroAssembler::sign_extend_short(Register reg) {
3762   if (LP64_ONLY(true ||) VM_Version::is_P6()) {
3763     movswl(reg, reg); // movsxw
3764   } else {
3765     shll(reg, 16);
3766     sarl(reg, 16);
3767   }
3768 }
3769 
3770 void MacroAssembler::testl(Register dst, AddressLiteral src) {
3771   assert(reachable(src), "Address should be reachable");
3772   testl(dst, as_Address(src));
3773 }
3774 
3775 void MacroAssembler::pcmpeqb(XMMRegister dst, XMMRegister src) {
3776   int dst_enc = dst->encoding();
3777   int src_enc = src->encoding();
3778   if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
3779     Assembler::pcmpeqb(dst, src);
3780   } else if ((dst_enc < 16) && (src_enc < 16)) {
3781     Assembler::pcmpeqb(dst, src);
3782   } else if (src_enc < 16) {
3783     subptr(rsp, 64);
3784     evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3785     evmovdqul(xmm0, dst, Assembler::AVX_512bit);
3786     Assembler::pcmpeqb(xmm0, src);
3787     movdqu(dst, xmm0);
3788     evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3789     addptr(rsp, 64);
3790   } else if (dst_enc < 16) {
3791     subptr(rsp, 64);
3792     evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3793     evmovdqul(xmm0, src, Assembler::AVX_512bit);
3794     Assembler::pcmpeqb(dst, xmm0);
3795     evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3796     addptr(rsp, 64);
3797   } else {
3798     subptr(rsp, 64);
3799     evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3800     subptr(rsp, 64);
3801     evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
3802     movdqu(xmm0, src);
3803     movdqu(xmm1, dst);
3804     Assembler::pcmpeqb(xmm1, xmm0);
3805     movdqu(dst, xmm1);
3806     evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
3807     addptr(rsp, 64);
3808     evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3809     addptr(rsp, 64);
3810   }
3811 }
3812 
3813 void MacroAssembler::pcmpeqw(XMMRegister dst, XMMRegister src) {
3814   int dst_enc = dst->encoding();
3815   int src_enc = src->encoding();
3816   if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
3817     Assembler::pcmpeqw(dst, src);
3818   } else if ((dst_enc < 16) && (src_enc < 16)) {
3819     Assembler::pcmpeqw(dst, src);
3820   } else if (src_enc < 16) {
3821     subptr(rsp, 64);
3822     evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3823     evmovdqul(xmm0, dst, Assembler::AVX_512bit);
3824     Assembler::pcmpeqw(xmm0, src);
3825     movdqu(dst, xmm0);
3826     evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3827     addptr(rsp, 64);
3828   } else if (dst_enc < 16) {
3829     subptr(rsp, 64);
3830     evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3831     evmovdqul(xmm0, src, Assembler::AVX_512bit);
3832     Assembler::pcmpeqw(dst, xmm0);
3833     evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3834     addptr(rsp, 64);
3835   } else {
3836     subptr(rsp, 64);
3837     evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3838     subptr(rsp, 64);
3839     evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
3840     movdqu(xmm0, src);
3841     movdqu(xmm1, dst);
3842     Assembler::pcmpeqw(xmm1, xmm0);
3843     movdqu(dst, xmm1);
3844     evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
3845     addptr(rsp, 64);
3846     evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3847     addptr(rsp, 64);
3848   }
3849 }
3850 
3851 void MacroAssembler::pcmpestri(XMMRegister dst, Address src, int imm8) {
3852   int dst_enc = dst->encoding();
3853   if (dst_enc < 16) {
3854     Assembler::pcmpestri(dst, src, imm8);
3855   } else {
3856     subptr(rsp, 64);
3857     evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3858     evmovdqul(xmm0, dst, Assembler::AVX_512bit);
3859     Assembler::pcmpestri(xmm0, src, imm8);
3860     movdqu(dst, xmm0);
3861     evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3862     addptr(rsp, 64);
3863   }
3864 }
3865 
3866 void MacroAssembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) {
3867   int dst_enc = dst->encoding();
3868   int src_enc = src->encoding();
3869   if ((dst_enc < 16) && (src_enc < 16)) {
3870     Assembler::pcmpestri(dst, src, imm8);
3871   } else if (src_enc < 16) {
3872     subptr(rsp, 64);
3873     evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3874     evmovdqul(xmm0, dst, Assembler::AVX_512bit);
3875     Assembler::pcmpestri(xmm0, src, imm8);
3876     movdqu(dst, xmm0);
3877     evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3878     addptr(rsp, 64);
3879   } else if (dst_enc < 16) {
3880     subptr(rsp, 64);
3881     evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3882     evmovdqul(xmm0, src, Assembler::AVX_512bit);
3883     Assembler::pcmpestri(dst, xmm0, imm8);
3884     evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3885     addptr(rsp, 64);
3886   } else {
3887     subptr(rsp, 64);
3888     evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3889     subptr(rsp, 64);
3890     evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
3891     movdqu(xmm0, src);
3892     movdqu(xmm1, dst);
3893     Assembler::pcmpestri(xmm1, xmm0, imm8);
3894     movdqu(dst, xmm1);
3895     evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
3896     addptr(rsp, 64);
3897     evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3898     addptr(rsp, 64);
3899   }
3900 }
3901 
3902 void MacroAssembler::pmovzxbw(XMMRegister dst, XMMRegister src) {
3903   int dst_enc = dst->encoding();
3904   int src_enc = src->encoding();
3905   if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
3906     Assembler::pmovzxbw(dst, src);
3907   } else if ((dst_enc < 16) && (src_enc < 16)) {
3908     Assembler::pmovzxbw(dst, src);
3909   } else if (src_enc < 16) {
3910     subptr(rsp, 64);
3911     evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3912     evmovdqul(xmm0, dst, Assembler::AVX_512bit);
3913     Assembler::pmovzxbw(xmm0, src);
3914     movdqu(dst, xmm0);
3915     evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3916     addptr(rsp, 64);
3917   } else if (dst_enc < 16) {
3918     subptr(rsp, 64);
3919     evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3920     evmovdqul(xmm0, src, Assembler::AVX_512bit);
3921     Assembler::pmovzxbw(dst, xmm0);
3922     evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3923     addptr(rsp, 64);
3924   } else {
3925     subptr(rsp, 64);
3926     evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3927     subptr(rsp, 64);
3928     evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
3929     movdqu(xmm0, src);
3930     movdqu(xmm1, dst);
3931     Assembler::pmovzxbw(xmm1, xmm0);
3932     movdqu(dst, xmm1);
3933     evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
3934     addptr(rsp, 64);
3935     evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3936     addptr(rsp, 64);
3937   }
3938 }
3939 
3940 void MacroAssembler::pmovzxbw(XMMRegister dst, Address src) {
3941   int dst_enc = dst->encoding();
3942   if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
3943     Assembler::pmovzxbw(dst, src);
3944   } else if (dst_enc < 16) {
3945     Assembler::pmovzxbw(dst, src);
3946   } else {
3947     subptr(rsp, 64);
3948     evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3949     evmovdqul(xmm0, dst, Assembler::AVX_512bit);
3950     Assembler::pmovzxbw(xmm0, src);
3951     movdqu(dst, xmm0);
3952     evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3953     addptr(rsp, 64);
3954   }
3955 }
3956 
3957 void MacroAssembler::pmovmskb(Register dst, XMMRegister src) {
3958   int src_enc = src->encoding();
3959   if (src_enc < 16) {
3960     Assembler::pmovmskb(dst, src);
3961   } else {
3962     subptr(rsp, 64);
3963     evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3964     evmovdqul(xmm0, src, Assembler::AVX_512bit);
3965     Assembler::pmovmskb(dst, xmm0);
3966     evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3967     addptr(rsp, 64);
3968   }
3969 }
3970 
3971 void MacroAssembler::ptest(XMMRegister dst, XMMRegister src) {
3972   int dst_enc = dst->encoding();
3973   int src_enc = src->encoding();
3974   if ((dst_enc < 16) && (src_enc < 16)) {
3975     Assembler::ptest(dst, src);
3976   } else if (src_enc < 16) {
3977     subptr(rsp, 64);
3978     evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3979     evmovdqul(xmm0, dst, Assembler::AVX_512bit);
3980     Assembler::ptest(xmm0, src);
3981     evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3982     addptr(rsp, 64);
3983   } else if (dst_enc < 16) {
3984     subptr(rsp, 64);
3985     evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3986     evmovdqul(xmm0, src, Assembler::AVX_512bit);
3987     Assembler::ptest(dst, xmm0);
3988     evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3989     addptr(rsp, 64);
3990   } else {
3991     subptr(rsp, 64);
3992     evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3993     subptr(rsp, 64);
3994     evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
3995     movdqu(xmm0, src);
3996     movdqu(xmm1, dst);
3997     Assembler::ptest(xmm1, xmm0);
3998     evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
3999     addptr(rsp, 64);
4000     evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4001     addptr(rsp, 64);
4002   }
4003 }
4004 
4005 void MacroAssembler::sqrtsd(XMMRegister dst, AddressLiteral src) {
4006   if (reachable(src)) {
4007     Assembler::sqrtsd(dst, as_Address(src));
4008   } else {
4009     lea(rscratch1, src);
4010     Assembler::sqrtsd(dst, Address(rscratch1, 0));
4011   }
4012 }
4013 
4014 void MacroAssembler::sqrtss(XMMRegister dst, AddressLiteral src) {
4015   if (reachable(src)) {
4016     Assembler::sqrtss(dst, as_Address(src));
4017   } else {
4018     lea(rscratch1, src);
4019     Assembler::sqrtss(dst, Address(rscratch1, 0));
4020   }
4021 }
4022 
4023 void MacroAssembler::subsd(XMMRegister dst, AddressLiteral src) {
4024   if (reachable(src)) {
4025     Assembler::subsd(dst, as_Address(src));
4026   } else {
4027     lea(rscratch1, src);
4028     Assembler::subsd(dst, Address(rscratch1, 0));
4029   }
4030 }
4031 
4032 void MacroAssembler::subss(XMMRegister dst, AddressLiteral src) {
4033   if (reachable(src)) {
4034     Assembler::subss(dst, as_Address(src));
4035   } else {
4036     lea(rscratch1, src);
4037     Assembler::subss(dst, Address(rscratch1, 0));
4038   }
4039 }
4040 
4041 void MacroAssembler::ucomisd(XMMRegister dst, AddressLiteral src) {
4042   if (reachable(src)) {
4043     Assembler::ucomisd(dst, as_Address(src));
4044   } else {
4045     lea(rscratch1, src);
4046     Assembler::ucomisd(dst, Address(rscratch1, 0));
4047   }
4048 }
4049 
4050 void MacroAssembler::ucomiss(XMMRegister dst, AddressLiteral src) {
4051   if (reachable(src)) {
4052     Assembler::ucomiss(dst, as_Address(src));
4053   } else {
4054     lea(rscratch1, src);
4055     Assembler::ucomiss(dst, Address(rscratch1, 0));
4056   }
4057 }
4058 
4059 void MacroAssembler::xorpd(XMMRegister dst, AddressLiteral src) {
4060   // Used in sign-bit flipping with aligned address.
4061   assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
4062   if (reachable(src)) {
4063     Assembler::xorpd(dst, as_Address(src));
4064   } else {
4065     lea(rscratch1, src);
4066     Assembler::xorpd(dst, Address(rscratch1, 0));
4067   }
4068 }
4069 
4070 void MacroAssembler::xorpd(XMMRegister dst, XMMRegister src) {
4071   if (UseAVX > 2 && !VM_Version::supports_avx512dq() && (dst->encoding() == src->encoding())) {
4072     Assembler::vpxor(dst, dst, src, Assembler::AVX_512bit);
4073   }
4074   else {
4075     Assembler::xorpd(dst, src);
4076   }
4077 }
4078 
4079 void MacroAssembler::xorps(XMMRegister dst, XMMRegister src) {
4080   if (UseAVX > 2 && !VM_Version::supports_avx512dq() && (dst->encoding() == src->encoding())) {
4081     Assembler::vpxor(dst, dst, src, Assembler::AVX_512bit);
4082   } else {
4083     Assembler::xorps(dst, src);
4084   }
4085 }
4086 
4087 void MacroAssembler::xorps(XMMRegister dst, AddressLiteral src) {
4088   // Used in sign-bit flipping with aligned address.
4089   assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
4090   if (reachable(src)) {
4091     Assembler::xorps(dst, as_Address(src));
4092   } else {
4093     lea(rscratch1, src);
4094     Assembler::xorps(dst, Address(rscratch1, 0));
4095   }
4096 }
4097 
4098 void MacroAssembler::pshufb(XMMRegister dst, AddressLiteral src) {
4099   // Used in sign-bit flipping with aligned address.
4100   bool aligned_adr = (((intptr_t)src.target() & 15) == 0);
4101   assert((UseAVX > 0) || aligned_adr, "SSE mode requires address alignment 16 bytes");
4102   if (reachable(src)) {
4103     Assembler::pshufb(dst, as_Address(src));
4104   } else {
4105     lea(rscratch1, src);
4106     Assembler::pshufb(dst, Address(rscratch1, 0));
4107   }
4108 }
4109 
4110 // AVX 3-operands instructions
4111 
4112 void MacroAssembler::vaddsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
4113   if (reachable(src)) {
4114     vaddsd(dst, nds, as_Address(src));
4115   } else {
4116     lea(rscratch1, src);
4117     vaddsd(dst, nds, Address(rscratch1, 0));
4118   }
4119 }
4120 
4121 void MacroAssembler::vaddss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
4122   if (reachable(src)) {
4123     vaddss(dst, nds, as_Address(src));
4124   } else {
4125     lea(rscratch1, src);
4126     vaddss(dst, nds, Address(rscratch1, 0));
4127   }
4128 }
4129 
4130 void MacroAssembler::vabsss(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len) {
4131   int dst_enc = dst->encoding();
4132   int nds_enc = nds->encoding();
4133   int src_enc = src->encoding();
4134   if ((dst_enc < 16) && (nds_enc < 16)) {
4135     vandps(dst, nds, negate_field, vector_len);
4136   } else if ((src_enc < 16) && (dst_enc < 16)) {
4137     movss(src, nds);
4138     vandps(dst, src, negate_field, vector_len);
4139   } else if (src_enc < 16) {
4140     movss(src, nds);
4141     vandps(src, src, negate_field, vector_len);
4142     movss(dst, src);
4143   } else if (dst_enc < 16) {
4144     movdqu(src, xmm0);
4145     movss(xmm0, nds);
4146     vandps(dst, xmm0, negate_field, vector_len);
4147     movdqu(xmm0, src);
4148   } else if (nds_enc < 16) {
4149     movdqu(src, xmm0);
4150     vandps(xmm0, nds, negate_field, vector_len);
4151     movss(dst, xmm0);
4152     movdqu(xmm0, src);
4153   } else {
4154     movdqu(src, xmm0);
4155     movss(xmm0, nds);
4156     vandps(xmm0, xmm0, negate_field, vector_len);
4157     movss(dst, xmm0);
4158     movdqu(xmm0, src);
4159   }
4160 }
4161 
4162 void MacroAssembler::vabssd(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len) {
4163   int dst_enc = dst->encoding();
4164   int nds_enc = nds->encoding();
4165   int src_enc = src->encoding();
4166   if ((dst_enc < 16) && (nds_enc < 16)) {
4167     vandpd(dst, nds, negate_field, vector_len);
4168   } else if ((src_enc < 16) && (dst_enc < 16)) {
4169     movsd(src, nds);
4170     vandpd(dst, src, negate_field, vector_len);
4171   } else if (src_enc < 16) {
4172     movsd(src, nds);
4173     vandpd(src, src, negate_field, vector_len);
4174     movsd(dst, src);
4175   } else if (dst_enc < 16) {
4176     movdqu(src, xmm0);
4177     movsd(xmm0, nds);
4178     vandpd(dst, xmm0, negate_field, vector_len);
4179     movdqu(xmm0, src);
4180   } else if (nds_enc < 16) {
4181     movdqu(src, xmm0);
4182     vandpd(xmm0, nds, negate_field, vector_len);
4183     movsd(dst, xmm0);
4184     movdqu(xmm0, src);
4185   } else {
4186     movdqu(src, xmm0);
4187     movsd(xmm0, nds);
4188     vandpd(xmm0, xmm0, negate_field, vector_len);
4189     movsd(dst, xmm0);
4190     movdqu(xmm0, src);
4191   }
4192 }
4193 
4194 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4195   int dst_enc = dst->encoding();
4196   int nds_enc = nds->encoding();
4197   int src_enc = src->encoding();
4198   if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4199     Assembler::vpaddb(dst, nds, src, vector_len);
4200   } else if ((dst_enc < 16) && (src_enc < 16)) {
4201     Assembler::vpaddb(dst, dst, src, vector_len);
4202   } else if ((dst_enc < 16) && (nds_enc < 16)) {
4203     // use nds as scratch for src
4204     evmovdqul(nds, src, Assembler::AVX_512bit);
4205     Assembler::vpaddb(dst, dst, nds, vector_len);
4206   } else if ((src_enc < 16) && (nds_enc < 16)) {
4207     // use nds as scratch for dst
4208     evmovdqul(nds, dst, Assembler::AVX_512bit);
4209     Assembler::vpaddb(nds, nds, src, vector_len);
4210     evmovdqul(dst, nds, Assembler::AVX_512bit);
4211   } else if (dst_enc < 16) {
4212     // use nds as scatch for xmm0 to hold src
4213     evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4214     evmovdqul(xmm0, src, Assembler::AVX_512bit);
4215     Assembler::vpaddb(dst, dst, xmm0, vector_len);
4216     evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4217   } else {
4218     // worse case scenario, all regs are in the upper bank
4219     subptr(rsp, 64);
4220     evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4221     evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4222     evmovdqul(xmm1, src, Assembler::AVX_512bit);
4223     evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4224     Assembler::vpaddb(xmm0, xmm0, xmm1, vector_len);
4225     evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4226     evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4227     evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4228     addptr(rsp, 64);
4229   }
4230 }
4231 
4232 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4233   int dst_enc = dst->encoding();
4234   int nds_enc = nds->encoding();
4235   if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4236     Assembler::vpaddb(dst, nds, src, vector_len);
4237   } else if (dst_enc < 16) {
4238     Assembler::vpaddb(dst, dst, src, vector_len);
4239   } else if (nds_enc < 16) {
4240     // implies dst_enc in upper bank with src as scratch
4241     evmovdqul(nds, dst, Assembler::AVX_512bit);
4242     Assembler::vpaddb(nds, nds, src, vector_len);
4243     evmovdqul(dst, nds, Assembler::AVX_512bit);
4244   } else {
4245     // worse case scenario, all regs in upper bank
4246     evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4247     evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4248     Assembler::vpaddb(xmm0, xmm0, src, vector_len);
4249     evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4250   }
4251 }
4252 
4253 void MacroAssembler::vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4254   int dst_enc = dst->encoding();
4255   int nds_enc = nds->encoding();
4256   int src_enc = src->encoding();
4257   if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4258     Assembler::vpaddw(dst, nds, src, vector_len);
4259   } else if ((dst_enc < 16) && (src_enc < 16)) {
4260     Assembler::vpaddw(dst, dst, src, vector_len);
4261   } else if ((dst_enc < 16) && (nds_enc < 16)) {
4262     // use nds as scratch for src
4263     evmovdqul(nds, src, Assembler::AVX_512bit);
4264     Assembler::vpaddw(dst, dst, nds, vector_len);
4265   } else if ((src_enc < 16) && (nds_enc < 16)) {
4266     // use nds as scratch for dst
4267     evmovdqul(nds, dst, Assembler::AVX_512bit);
4268     Assembler::vpaddw(nds, nds, src, vector_len);
4269     evmovdqul(dst, nds, Assembler::AVX_512bit);
4270   } else if (dst_enc < 16) {
4271     // use nds as scatch for xmm0 to hold src
4272     evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4273     evmovdqul(xmm0, src, Assembler::AVX_512bit);
4274     Assembler::vpaddw(dst, dst, xmm0, vector_len);
4275     evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4276   } else {
4277     // worse case scenario, all regs are in the upper bank
4278     subptr(rsp, 64);
4279     evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4280     evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4281     evmovdqul(xmm1, src, Assembler::AVX_512bit);
4282     evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4283     Assembler::vpaddw(xmm0, xmm0, xmm1, vector_len);
4284     evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4285     evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4286     evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4287     addptr(rsp, 64);
4288   }
4289 }
4290 
4291 void MacroAssembler::vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4292   int dst_enc = dst->encoding();
4293   int nds_enc = nds->encoding();
4294   if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4295     Assembler::vpaddw(dst, nds, src, vector_len);
4296   } else if (dst_enc < 16) {
4297     Assembler::vpaddw(dst, dst, src, vector_len);
4298   } else if (nds_enc < 16) {
4299     // implies dst_enc in upper bank with src as scratch
4300     evmovdqul(nds, dst, Assembler::AVX_512bit);
4301     Assembler::vpaddw(nds, nds, src, vector_len);
4302     evmovdqul(dst, nds, Assembler::AVX_512bit);
4303   } else {
4304     // worse case scenario, all regs in upper bank
4305     evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4306     evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4307     Assembler::vpaddw(xmm0, xmm0, src, vector_len);
4308     evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4309   }
4310 }
4311 
4312 void MacroAssembler::vpand(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len) {
4313   if (reachable(src)) {
4314     Assembler::vpand(dst, nds, as_Address(src), vector_len);
4315   } else {
4316     lea(rscratch1, src);
4317     Assembler::vpand(dst, nds, Address(rscratch1, 0), vector_len);
4318   }
4319 }
4320 
4321 void MacroAssembler::vpbroadcastw(XMMRegister dst, XMMRegister src) {
4322   int dst_enc = dst->encoding();
4323   int src_enc = src->encoding();
4324   if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4325     Assembler::vpbroadcastw(dst, src);
4326   } else if ((dst_enc < 16) && (src_enc < 16)) {
4327     Assembler::vpbroadcastw(dst, src);
4328   } else if (src_enc < 16) {
4329     subptr(rsp, 64);
4330     evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4331     evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4332     Assembler::vpbroadcastw(xmm0, src);
4333     movdqu(dst, xmm0);
4334     evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4335     addptr(rsp, 64);
4336   } else if (dst_enc < 16) {
4337     subptr(rsp, 64);
4338     evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4339     evmovdqul(xmm0, src, Assembler::AVX_512bit);
4340     Assembler::vpbroadcastw(dst, xmm0);
4341     evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4342     addptr(rsp, 64);
4343   } else {
4344     subptr(rsp, 64);
4345     evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4346     subptr(rsp, 64);
4347     evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4348     movdqu(xmm0, src);
4349     movdqu(xmm1, dst);
4350     Assembler::vpbroadcastw(xmm1, xmm0);
4351     movdqu(dst, xmm1);
4352     evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4353     addptr(rsp, 64);
4354     evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4355     addptr(rsp, 64);
4356   }
4357 }
4358 
4359 void MacroAssembler::vpcmpeqb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4360   int dst_enc = dst->encoding();
4361   int nds_enc = nds->encoding();
4362   int src_enc = src->encoding();
4363   assert(dst_enc == nds_enc, "");
4364   if ((dst_enc < 16) && (src_enc < 16)) {
4365     Assembler::vpcmpeqb(dst, nds, src, vector_len);
4366   } else if (src_enc < 16) {
4367     subptr(rsp, 64);
4368     evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4369     evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4370     Assembler::vpcmpeqb(xmm0, xmm0, src, vector_len);
4371     movdqu(dst, xmm0);
4372     evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4373     addptr(rsp, 64);
4374   } else if (dst_enc < 16) {
4375     subptr(rsp, 64);
4376     evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4377     evmovdqul(xmm0, src, Assembler::AVX_512bit);
4378     Assembler::vpcmpeqb(dst, dst, xmm0, vector_len);
4379     evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4380     addptr(rsp, 64);
4381   } else {
4382     subptr(rsp, 64);
4383     evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4384     subptr(rsp, 64);
4385     evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4386     movdqu(xmm0, src);
4387     movdqu(xmm1, dst);
4388     Assembler::vpcmpeqb(xmm1, xmm1, xmm0, vector_len);
4389     movdqu(dst, xmm1);
4390     evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4391     addptr(rsp, 64);
4392     evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4393     addptr(rsp, 64);
4394   }
4395 }
4396 
4397 void MacroAssembler::vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4398   int dst_enc = dst->encoding();
4399   int nds_enc = nds->encoding();
4400   int src_enc = src->encoding();
4401   assert(dst_enc == nds_enc, "");
4402   if ((dst_enc < 16) && (src_enc < 16)) {
4403     Assembler::vpcmpeqw(dst, nds, src, vector_len);
4404   } else if (src_enc < 16) {
4405     subptr(rsp, 64);
4406     evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4407     evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4408     Assembler::vpcmpeqw(xmm0, xmm0, src, vector_len);
4409     movdqu(dst, xmm0);
4410     evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4411     addptr(rsp, 64);
4412   } else if (dst_enc < 16) {
4413     subptr(rsp, 64);
4414     evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4415     evmovdqul(xmm0, src, Assembler::AVX_512bit);
4416     Assembler::vpcmpeqw(dst, dst, xmm0, vector_len);
4417     evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4418     addptr(rsp, 64);
4419   } else {
4420     subptr(rsp, 64);
4421     evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4422     subptr(rsp, 64);
4423     evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4424     movdqu(xmm0, src);
4425     movdqu(xmm1, dst);
4426     Assembler::vpcmpeqw(xmm1, xmm1, xmm0, vector_len);
4427     movdqu(dst, xmm1);
4428     evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4429     addptr(rsp, 64);
4430     evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4431     addptr(rsp, 64);
4432   }
4433 }
4434 
4435 void MacroAssembler::vpmovzxbw(XMMRegister dst, Address src, int vector_len) {
4436   int dst_enc = dst->encoding();
4437   if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4438     Assembler::vpmovzxbw(dst, src, vector_len);
4439   } else if (dst_enc < 16) {
4440     Assembler::vpmovzxbw(dst, src, vector_len);
4441   } else {
4442     subptr(rsp, 64);
4443     evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4444     evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4445     Assembler::vpmovzxbw(xmm0, src, vector_len);
4446     movdqu(dst, xmm0);
4447     evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4448     addptr(rsp, 64);
4449   }
4450 }
4451 
4452 void MacroAssembler::vpmovmskb(Register dst, XMMRegister src) {
4453   int src_enc = src->encoding();
4454   if (src_enc < 16) {
4455     Assembler::vpmovmskb(dst, src);
4456   } else {
4457     subptr(rsp, 64);
4458     evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4459     evmovdqul(xmm0, src, Assembler::AVX_512bit);
4460     Assembler::vpmovmskb(dst, xmm0);
4461     evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4462     addptr(rsp, 64);
4463   }
4464 }
4465 
4466 void MacroAssembler::vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4467   int dst_enc = dst->encoding();
4468   int nds_enc = nds->encoding();
4469   int src_enc = src->encoding();
4470   if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4471     Assembler::vpmullw(dst, nds, src, vector_len);
4472   } else if ((dst_enc < 16) && (src_enc < 16)) {
4473     Assembler::vpmullw(dst, dst, src, vector_len);
4474   } else if ((dst_enc < 16) && (nds_enc < 16)) {
4475     // use nds as scratch for src
4476     evmovdqul(nds, src, Assembler::AVX_512bit);
4477     Assembler::vpmullw(dst, dst, nds, vector_len);
4478   } else if ((src_enc < 16) && (nds_enc < 16)) {
4479     // use nds as scratch for dst
4480     evmovdqul(nds, dst, Assembler::AVX_512bit);
4481     Assembler::vpmullw(nds, nds, src, vector_len);
4482     evmovdqul(dst, nds, Assembler::AVX_512bit);
4483   } else if (dst_enc < 16) {
4484     // use nds as scatch for xmm0 to hold src
4485     evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4486     evmovdqul(xmm0, src, Assembler::AVX_512bit);
4487     Assembler::vpmullw(dst, dst, xmm0, vector_len);
4488     evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4489   } else {
4490     // worse case scenario, all regs are in the upper bank
4491     subptr(rsp, 64);
4492     evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4493     evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4494     evmovdqul(xmm1, src, Assembler::AVX_512bit);
4495     evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4496     Assembler::vpmullw(xmm0, xmm0, xmm1, vector_len);
4497     evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4498     evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4499     evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4500     addptr(rsp, 64);
4501   }
4502 }
4503 
4504 void MacroAssembler::vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4505   int dst_enc = dst->encoding();
4506   int nds_enc = nds->encoding();
4507   if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4508     Assembler::vpmullw(dst, nds, src, vector_len);
4509   } else if (dst_enc < 16) {
4510     Assembler::vpmullw(dst, dst, src, vector_len);
4511   } else if (nds_enc < 16) {
4512     // implies dst_enc in upper bank with src as scratch
4513     evmovdqul(nds, dst, Assembler::AVX_512bit);
4514     Assembler::vpmullw(nds, nds, src, vector_len);
4515     evmovdqul(dst, nds, Assembler::AVX_512bit);
4516   } else {
4517     // worse case scenario, all regs in upper bank
4518     evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4519     evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4520     Assembler::vpmullw(xmm0, xmm0, src, vector_len);
4521     evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4522   }
4523 }
4524 
4525 void MacroAssembler::vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4526   int dst_enc = dst->encoding();
4527   int nds_enc = nds->encoding();
4528   int src_enc = src->encoding();
4529   if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4530     Assembler::vpsubb(dst, nds, src, vector_len);
4531   } else if ((dst_enc < 16) && (src_enc < 16)) {
4532     Assembler::vpsubb(dst, dst, src, vector_len);
4533   } else if ((dst_enc < 16) && (nds_enc < 16)) {
4534     // use nds as scratch for src
4535     evmovdqul(nds, src, Assembler::AVX_512bit);
4536     Assembler::vpsubb(dst, dst, nds, vector_len);
4537   } else if ((src_enc < 16) && (nds_enc < 16)) {
4538     // use nds as scratch for dst
4539     evmovdqul(nds, dst, Assembler::AVX_512bit);
4540     Assembler::vpsubb(nds, nds, src, vector_len);
4541     evmovdqul(dst, nds, Assembler::AVX_512bit);
4542   } else if (dst_enc < 16) {
4543     // use nds as scatch for xmm0 to hold src
4544     evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4545     evmovdqul(xmm0, src, Assembler::AVX_512bit);
4546     Assembler::vpsubb(dst, dst, xmm0, vector_len);
4547     evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4548   } else {
4549     // worse case scenario, all regs are in the upper bank
4550     subptr(rsp, 64);
4551     evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4552     evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4553     evmovdqul(xmm1, src, Assembler::AVX_512bit);
4554     evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4555     Assembler::vpsubb(xmm0, xmm0, xmm1, vector_len);
4556     evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4557     evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4558     evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4559     addptr(rsp, 64);
4560   }
4561 }
4562 
4563 void MacroAssembler::vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4564   int dst_enc = dst->encoding();
4565   int nds_enc = nds->encoding();
4566   if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4567     Assembler::vpsubb(dst, nds, src, vector_len);
4568   } else if (dst_enc < 16) {
4569     Assembler::vpsubb(dst, dst, src, vector_len);
4570   } else if (nds_enc < 16) {
4571     // implies dst_enc in upper bank with src as scratch
4572     evmovdqul(nds, dst, Assembler::AVX_512bit);
4573     Assembler::vpsubb(nds, nds, src, vector_len);
4574     evmovdqul(dst, nds, Assembler::AVX_512bit);
4575   } else {
4576     // worse case scenario, all regs in upper bank
4577     evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4578     evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4579     Assembler::vpsubw(xmm0, xmm0, src, vector_len);
4580     evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4581   }
4582 }
4583 
4584 void MacroAssembler::vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4585   int dst_enc = dst->encoding();
4586   int nds_enc = nds->encoding();
4587   int src_enc = src->encoding();
4588   if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4589     Assembler::vpsubw(dst, nds, src, vector_len);
4590   } else if ((dst_enc < 16) && (src_enc < 16)) {
4591     Assembler::vpsubw(dst, dst, src, vector_len);
4592   } else if ((dst_enc < 16) && (nds_enc < 16)) {
4593     // use nds as scratch for src
4594     evmovdqul(nds, src, Assembler::AVX_512bit);
4595     Assembler::vpsubw(dst, dst, nds, vector_len);
4596   } else if ((src_enc < 16) && (nds_enc < 16)) {
4597     // use nds as scratch for dst
4598     evmovdqul(nds, dst, Assembler::AVX_512bit);
4599     Assembler::vpsubw(nds, nds, src, vector_len);
4600     evmovdqul(dst, nds, Assembler::AVX_512bit);
4601   } else if (dst_enc < 16) {
4602     // use nds as scatch for xmm0 to hold src
4603     evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4604     evmovdqul(xmm0, src, Assembler::AVX_512bit);
4605     Assembler::vpsubw(dst, dst, xmm0, vector_len);
4606     evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4607   } else {
4608     // worse case scenario, all regs are in the upper bank
4609     subptr(rsp, 64);
4610     evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4611     evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4612     evmovdqul(xmm1, src, Assembler::AVX_512bit);
4613     evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4614     Assembler::vpsubw(xmm0, xmm0, xmm1, vector_len);
4615     evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4616     evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4617     evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4618     addptr(rsp, 64);
4619   }
4620 }
4621 
4622 void MacroAssembler::vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4623   int dst_enc = dst->encoding();
4624   int nds_enc = nds->encoding();
4625   if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4626     Assembler::vpsubw(dst, nds, src, vector_len);
4627   } else if (dst_enc < 16) {
4628     Assembler::vpsubw(dst, dst, src, vector_len);
4629   } else if (nds_enc < 16) {
4630     // implies dst_enc in upper bank with src as scratch
4631     evmovdqul(nds, dst, Assembler::AVX_512bit);
4632     Assembler::vpsubw(nds, nds, src, vector_len);
4633     evmovdqul(dst, nds, Assembler::AVX_512bit);
4634   } else {
4635     // worse case scenario, all regs in upper bank
4636     evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4637     evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4638     Assembler::vpsubw(xmm0, xmm0, src, vector_len);
4639     evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4640   }
4641 }
4642 
4643 void MacroAssembler::vpsraw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
4644   int dst_enc = dst->encoding();
4645   int nds_enc = nds->encoding();
4646   int shift_enc = shift->encoding();
4647   if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4648     Assembler::vpsraw(dst, nds, shift, vector_len);
4649   } else if ((dst_enc < 16) && (shift_enc < 16)) {
4650     Assembler::vpsraw(dst, dst, shift, vector_len);
4651   } else if ((dst_enc < 16) && (nds_enc < 16)) {
4652     // use nds_enc as scratch with shift
4653     evmovdqul(nds, shift, Assembler::AVX_512bit);
4654     Assembler::vpsraw(dst, dst, nds, vector_len);
4655   } else if ((shift_enc < 16) && (nds_enc < 16)) {
4656     // use nds as scratch with dst
4657     evmovdqul(nds, dst, Assembler::AVX_512bit);
4658     Assembler::vpsraw(nds, nds, shift, vector_len);
4659     evmovdqul(dst, nds, Assembler::AVX_512bit);
4660   } else if (dst_enc < 16) {
4661     // use nds to save a copy of xmm0 and hold shift
4662     evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4663     evmovdqul(xmm0, shift, Assembler::AVX_512bit);
4664     Assembler::vpsraw(dst, dst, xmm0, vector_len);
4665     evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4666   } else if (nds_enc < 16) {
4667     // use nds as dest as temps
4668     evmovdqul(nds, dst, Assembler::AVX_512bit);
4669     evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4670     evmovdqul(xmm0, shift, Assembler::AVX_512bit);
4671     Assembler::vpsraw(nds, nds, xmm0, vector_len);
4672     evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4673     evmovdqul(dst, nds, Assembler::AVX_512bit);
4674   } else {
4675     // worse case scenario, all regs are in the upper bank
4676     subptr(rsp, 64);
4677     evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4678     evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4679     evmovdqul(xmm1, shift, Assembler::AVX_512bit);
4680     evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4681     Assembler::vpsllw(xmm0, xmm0, xmm1, vector_len);
4682     evmovdqul(xmm1, dst, Assembler::AVX_512bit);
4683     evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4684     evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4685     evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4686     addptr(rsp, 64);
4687   }
4688 }
4689 
4690 void MacroAssembler::vpsraw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
4691   int dst_enc = dst->encoding();
4692   int nds_enc = nds->encoding();
4693   if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4694     Assembler::vpsraw(dst, nds, shift, vector_len);
4695   } else if (dst_enc < 16) {
4696     Assembler::vpsraw(dst, dst, shift, vector_len);
4697   } else if (nds_enc < 16) {
4698     // use nds as scratch
4699     evmovdqul(nds, dst, Assembler::AVX_512bit);
4700     Assembler::vpsraw(nds, nds, shift, vector_len);
4701     evmovdqul(dst, nds, Assembler::AVX_512bit);
4702   } else {
4703     // use nds as scratch for xmm0
4704     evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4705     evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4706     Assembler::vpsraw(xmm0, xmm0, shift, vector_len);
4707     evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4708   }
4709 }
4710 
4711 void MacroAssembler::vpsrlw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
4712   int dst_enc = dst->encoding();
4713   int nds_enc = nds->encoding();
4714   int shift_enc = shift->encoding();
4715   if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4716     Assembler::vpsrlw(dst, nds, shift, vector_len);
4717   } else if ((dst_enc < 16) && (shift_enc < 16)) {
4718     Assembler::vpsrlw(dst, dst, shift, vector_len);
4719   } else if ((dst_enc < 16) && (nds_enc < 16)) {
4720     // use nds_enc as scratch with shift
4721     evmovdqul(nds, shift, Assembler::AVX_512bit);
4722     Assembler::vpsrlw(dst, dst, nds, vector_len);
4723   } else if ((shift_enc < 16) && (nds_enc < 16)) {
4724     // use nds as scratch with dst
4725     evmovdqul(nds, dst, Assembler::AVX_512bit);
4726     Assembler::vpsrlw(nds, nds, shift, vector_len);
4727     evmovdqul(dst, nds, Assembler::AVX_512bit);
4728   } else if (dst_enc < 16) {
4729     // use nds to save a copy of xmm0 and hold shift
4730     evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4731     evmovdqul(xmm0, shift, Assembler::AVX_512bit);
4732     Assembler::vpsrlw(dst, dst, xmm0, vector_len);
4733     evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4734   } else if (nds_enc < 16) {
4735     // use nds as dest as temps
4736     evmovdqul(nds, dst, Assembler::AVX_512bit);
4737     evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4738     evmovdqul(xmm0, shift, Assembler::AVX_512bit);
4739     Assembler::vpsrlw(nds, nds, xmm0, vector_len);
4740     evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4741     evmovdqul(dst, nds, Assembler::AVX_512bit);
4742   } else {
4743     // worse case scenario, all regs are in the upper bank
4744     subptr(rsp, 64);
4745     evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4746     evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4747     evmovdqul(xmm1, shift, Assembler::AVX_512bit);
4748     evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4749     Assembler::vpsllw(xmm0, xmm0, xmm1, vector_len);
4750     evmovdqul(xmm1, dst, Assembler::AVX_512bit);
4751     evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4752     evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4753     evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4754     addptr(rsp, 64);
4755   }
4756 }
4757 
4758 void MacroAssembler::vpsrlw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
4759   int dst_enc = dst->encoding();
4760   int nds_enc = nds->encoding();
4761   if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4762     Assembler::vpsrlw(dst, nds, shift, vector_len);
4763   } else if (dst_enc < 16) {
4764     Assembler::vpsrlw(dst, dst, shift, vector_len);
4765   } else if (nds_enc < 16) {
4766     // use nds as scratch
4767     evmovdqul(nds, dst, Assembler::AVX_512bit);
4768     Assembler::vpsrlw(nds, nds, shift, vector_len);
4769     evmovdqul(dst, nds, Assembler::AVX_512bit);
4770   } else {
4771     // use nds as scratch for xmm0
4772     evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4773     evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4774     Assembler::vpsrlw(xmm0, xmm0, shift, vector_len);
4775     evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4776   }
4777 }
4778 
4779 void MacroAssembler::vpsllw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
4780   int dst_enc = dst->encoding();
4781   int nds_enc = nds->encoding();
4782   int shift_enc = shift->encoding();
4783   if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4784     Assembler::vpsllw(dst, nds, shift, vector_len);
4785   } else if ((dst_enc < 16) && (shift_enc < 16)) {
4786     Assembler::vpsllw(dst, dst, shift, vector_len);
4787   } else if ((dst_enc < 16) && (nds_enc < 16)) {
4788     // use nds_enc as scratch with shift
4789     evmovdqul(nds, shift, Assembler::AVX_512bit);
4790     Assembler::vpsllw(dst, dst, nds, vector_len);
4791   } else if ((shift_enc < 16) && (nds_enc < 16)) {
4792     // use nds as scratch with dst
4793     evmovdqul(nds, dst, Assembler::AVX_512bit);
4794     Assembler::vpsllw(nds, nds, shift, vector_len);
4795     evmovdqul(dst, nds, Assembler::AVX_512bit);
4796   } else if (dst_enc < 16) {
4797     // use nds to save a copy of xmm0 and hold shift
4798     evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4799     evmovdqul(xmm0, shift, Assembler::AVX_512bit);
4800     Assembler::vpsllw(dst, dst, xmm0, vector_len);
4801     evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4802   } else if (nds_enc < 16) {
4803     // use nds as dest as temps
4804     evmovdqul(nds, dst, Assembler::AVX_512bit);
4805     evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4806     evmovdqul(xmm0, shift, Assembler::AVX_512bit);
4807     Assembler::vpsllw(nds, nds, xmm0, vector_len);
4808     evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4809     evmovdqul(dst, nds, Assembler::AVX_512bit);
4810   } else {
4811     // worse case scenario, all regs are in the upper bank
4812     subptr(rsp, 64);
4813     evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4814     evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4815     evmovdqul(xmm1, shift, Assembler::AVX_512bit);
4816     evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4817     Assembler::vpsllw(xmm0, xmm0, xmm1, vector_len);
4818     evmovdqul(xmm1, dst, Assembler::AVX_512bit);
4819     evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4820     evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4821     evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4822     addptr(rsp, 64);
4823   }
4824 }
4825 
4826 void MacroAssembler::vpsllw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
4827   int dst_enc = dst->encoding();
4828   int nds_enc = nds->encoding();
4829   if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4830     Assembler::vpsllw(dst, nds, shift, vector_len);
4831   } else if (dst_enc < 16) {
4832     Assembler::vpsllw(dst, dst, shift, vector_len);
4833   } else if (nds_enc < 16) {
4834     // use nds as scratch
4835     evmovdqul(nds, dst, Assembler::AVX_512bit);
4836     Assembler::vpsllw(nds, nds, shift, vector_len);
4837     evmovdqul(dst, nds, Assembler::AVX_512bit);
4838   } else {
4839     // use nds as scratch for xmm0
4840     evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4841     evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4842     Assembler::vpsllw(xmm0, xmm0, shift, vector_len);
4843     evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4844   }
4845 }
4846 
4847 void MacroAssembler::vptest(XMMRegister dst, XMMRegister src) {
4848   int dst_enc = dst->encoding();
4849   int src_enc = src->encoding();
4850   if ((dst_enc < 16) && (src_enc < 16)) {
4851     Assembler::vptest(dst, src);
4852   } else if (src_enc < 16) {
4853     subptr(rsp, 64);
4854     evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4855     evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4856     Assembler::vptest(xmm0, src);
4857     evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4858     addptr(rsp, 64);
4859   } else if (dst_enc < 16) {
4860     subptr(rsp, 64);
4861     evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4862     evmovdqul(xmm0, src, Assembler::AVX_512bit);
4863     Assembler::vptest(dst, xmm0);
4864     evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4865     addptr(rsp, 64);
4866   } else {
4867     subptr(rsp, 64);
4868     evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4869     subptr(rsp, 64);
4870     evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4871     movdqu(xmm0, src);
4872     movdqu(xmm1, dst);
4873     Assembler::vptest(xmm1, xmm0);
4874     evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4875     addptr(rsp, 64);
4876     evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4877     addptr(rsp, 64);
4878   }
4879 }
4880 
4881 // This instruction exists within macros, ergo we cannot control its input
4882 // when emitted through those patterns.
4883 void MacroAssembler::punpcklbw(XMMRegister dst, XMMRegister src) {
4884   if (VM_Version::supports_avx512nobw()) {
4885     int dst_enc = dst->encoding();
4886     int src_enc = src->encoding();
4887     if (dst_enc == src_enc) {
4888       if (dst_enc < 16) {
4889         Assembler::punpcklbw(dst, src);
4890       } else {
4891         subptr(rsp, 64);
4892         evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4893         evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4894         Assembler::punpcklbw(xmm0, xmm0);
4895         evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4896         evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4897         addptr(rsp, 64);
4898       }
4899     } else {
4900       if ((src_enc < 16) && (dst_enc < 16)) {
4901         Assembler::punpcklbw(dst, src);
4902       } else if (src_enc < 16) {
4903         subptr(rsp, 64);
4904         evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4905         evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4906         Assembler::punpcklbw(xmm0, src);
4907         evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4908         evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4909         addptr(rsp, 64);
4910       } else if (dst_enc < 16) {
4911         subptr(rsp, 64);
4912         evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4913         evmovdqul(xmm0, src, Assembler::AVX_512bit);
4914         Assembler::punpcklbw(dst, xmm0);
4915         evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4916         addptr(rsp, 64);
4917       } else {
4918         subptr(rsp, 64);
4919         evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4920         subptr(rsp, 64);
4921         evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4922         evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4923         evmovdqul(xmm1, src, Assembler::AVX_512bit);
4924         Assembler::punpcklbw(xmm0, xmm1);
4925         evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4926         evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4927         addptr(rsp, 64);
4928         evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4929         addptr(rsp, 64);
4930       }
4931     }
4932   } else {
4933     Assembler::punpcklbw(dst, src);
4934   }
4935 }
4936 
4937 // This instruction exists within macros, ergo we cannot control its input
4938 // when emitted through those patterns.
4939 void MacroAssembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) {
4940   if (VM_Version::supports_avx512nobw()) {
4941     int dst_enc = dst->encoding();
4942     int src_enc = src->encoding();
4943     if (dst_enc == src_enc) {
4944       if (dst_enc < 16) {
4945         Assembler::pshuflw(dst, src, mode);
4946       } else {
4947         subptr(rsp, 64);
4948         evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4949         evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4950         Assembler::pshuflw(xmm0, xmm0, mode);
4951         evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4952         evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4953         addptr(rsp, 64);
4954       }
4955     } else {
4956       if ((src_enc < 16) && (dst_enc < 16)) {
4957         Assembler::pshuflw(dst, src, mode);
4958       } else if (src_enc < 16) {
4959         subptr(rsp, 64);
4960         evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4961         evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4962         Assembler::pshuflw(xmm0, src, mode);
4963         evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4964         evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4965         addptr(rsp, 64);
4966       } else if (dst_enc < 16) {
4967         subptr(rsp, 64);
4968         evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4969         evmovdqul(xmm0, src, Assembler::AVX_512bit);
4970         Assembler::pshuflw(dst, xmm0, mode);
4971         evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4972         addptr(rsp, 64);
4973       } else {
4974         subptr(rsp, 64);
4975         evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4976         subptr(rsp, 64);
4977         evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4978         evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4979         evmovdqul(xmm1, src, Assembler::AVX_512bit);
4980         Assembler::pshuflw(xmm0, xmm1, mode);
4981         evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4982         evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4983         addptr(rsp, 64);
4984         evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4985         addptr(rsp, 64);
4986       }
4987     }
4988   } else {
4989     Assembler::pshuflw(dst, src, mode);
4990   }
4991 }
4992 
4993 void MacroAssembler::vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len) {
4994   if (reachable(src)) {
4995     vandpd(dst, nds, as_Address(src), vector_len);
4996   } else {
4997     lea(rscratch1, src);
4998     vandpd(dst, nds, Address(rscratch1, 0), vector_len);
4999   }
5000 }
5001 
5002 void MacroAssembler::vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len) {
5003   if (reachable(src)) {
5004     vandps(dst, nds, as_Address(src), vector_len);
5005   } else {
5006     lea(rscratch1, src);
5007     vandps(dst, nds, Address(rscratch1, 0), vector_len);
5008   }
5009 }
5010 
5011 void MacroAssembler::vdivsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
5012   if (reachable(src)) {
5013     vdivsd(dst, nds, as_Address(src));
5014   } else {
5015     lea(rscratch1, src);
5016     vdivsd(dst, nds, Address(rscratch1, 0));
5017   }
5018 }
5019 
5020 void MacroAssembler::vdivss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
5021   if (reachable(src)) {
5022     vdivss(dst, nds, as_Address(src));
5023   } else {
5024     lea(rscratch1, src);
5025     vdivss(dst, nds, Address(rscratch1, 0));
5026   }
5027 }
5028 
5029 void MacroAssembler::vmulsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
5030   if (reachable(src)) {
5031     vmulsd(dst, nds, as_Address(src));
5032   } else {
5033     lea(rscratch1, src);
5034     vmulsd(dst, nds, Address(rscratch1, 0));
5035   }
5036 }
5037 
5038 void MacroAssembler::vmulss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
5039   if (reachable(src)) {
5040     vmulss(dst, nds, as_Address(src));
5041   } else {
5042     lea(rscratch1, src);
5043     vmulss(dst, nds, Address(rscratch1, 0));
5044   }
5045 }
5046 
5047 void MacroAssembler::vsubsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
5048   if (reachable(src)) {
5049     vsubsd(dst, nds, as_Address(src));
5050   } else {
5051     lea(rscratch1, src);
5052     vsubsd(dst, nds, Address(rscratch1, 0));
5053   }
5054 }
5055 
5056 void MacroAssembler::vsubss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
5057   if (reachable(src)) {
5058     vsubss(dst, nds, as_Address(src));
5059   } else {
5060     lea(rscratch1, src);
5061     vsubss(dst, nds, Address(rscratch1, 0));
5062   }
5063 }
5064 
5065 void MacroAssembler::vnegatess(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
5066   int nds_enc = nds->encoding();
5067   int dst_enc = dst->encoding();
5068   bool dst_upper_bank = (dst_enc > 15);
5069   bool nds_upper_bank = (nds_enc > 15);
5070   if (VM_Version::supports_avx512novl() &&
5071       (nds_upper_bank || dst_upper_bank)) {
5072     if (dst_upper_bank) {
5073       subptr(rsp, 64);
5074       evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
5075       movflt(xmm0, nds);
5076       vxorps(xmm0, xmm0, src, Assembler::AVX_128bit);
5077       movflt(dst, xmm0);
5078       evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
5079       addptr(rsp, 64);
5080     } else {
5081       movflt(dst, nds);
5082       vxorps(dst, dst, src, Assembler::AVX_128bit);
5083     }
5084   } else {
5085     vxorps(dst, nds, src, Assembler::AVX_128bit);
5086   }
5087 }
5088 
5089 void MacroAssembler::vnegatesd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
5090   int nds_enc = nds->encoding();
5091   int dst_enc = dst->encoding();
5092   bool dst_upper_bank = (dst_enc > 15);
5093   bool nds_upper_bank = (nds_enc > 15);
5094   if (VM_Version::supports_avx512novl() &&
5095       (nds_upper_bank || dst_upper_bank)) {
5096     if (dst_upper_bank) {
5097       subptr(rsp, 64);
5098       evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
5099       movdbl(xmm0, nds);
5100       vxorpd(xmm0, xmm0, src, Assembler::AVX_128bit);
5101       movdbl(dst, xmm0);
5102       evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
5103       addptr(rsp, 64);
5104     } else {
5105       movdbl(dst, nds);
5106       vxorpd(dst, dst, src, Assembler::AVX_128bit);
5107     }
5108   } else {
5109     vxorpd(dst, nds, src, Assembler::AVX_128bit);
5110   }
5111 }
5112 
5113 void MacroAssembler::vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len) {
5114   if (reachable(src)) {
5115     vxorpd(dst, nds, as_Address(src), vector_len);
5116   } else {
5117     lea(rscratch1, src);
5118     vxorpd(dst, nds, Address(rscratch1, 0), vector_len);
5119   }
5120 }
5121 
5122 void MacroAssembler::vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len) {
5123   if (reachable(src)) {
5124     vxorps(dst, nds, as_Address(src), vector_len);
5125   } else {
5126     lea(rscratch1, src);
5127     vxorps(dst, nds, Address(rscratch1, 0), vector_len);
5128   }
5129 }
5130 
5131 
5132 //////////////////////////////////////////////////////////////////////////////////
5133 #if INCLUDE_ALL_GCS
5134 
5135 void MacroAssembler::g1_write_barrier_pre(Register obj,
5136                                           Register pre_val,
5137                                           Register thread,
5138                                           Register tmp,
5139                                           bool tosca_live,
5140                                           bool expand_call) {
5141 
5142   // If expand_call is true then we expand the call_VM_leaf macro
5143   // directly to skip generating the check by
5144   // InterpreterMacroAssembler::call_VM_leaf_base that checks _last_sp.
5145 
5146 #ifdef _LP64
5147   assert(thread == r15_thread, "must be");
5148 #endif // _LP64
5149 
5150   Label done;
5151   Label runtime;
5152 
5153   assert(pre_val != noreg, "check this code");
5154 
5155   if (obj != noreg) {
5156     assert_different_registers(obj, pre_val, tmp);
5157     assert(pre_val != rax, "check this code");
5158   }
5159 
5160   Address in_progress(thread, in_bytes(JavaThread::satb_mark_queue_offset() +
5161                                        SATBMarkQueue::byte_offset_of_active()));
5162   Address index(thread, in_bytes(JavaThread::satb_mark_queue_offset() +
5163                                        SATBMarkQueue::byte_offset_of_index()));
5164   Address buffer(thread, in_bytes(JavaThread::satb_mark_queue_offset() +
5165                                        SATBMarkQueue::byte_offset_of_buf()));
5166 
5167 
5168   // Is marking active?
5169   if (in_bytes(SATBMarkQueue::byte_width_of_active()) == 4) {
5170     cmpl(in_progress, 0);
5171   } else {
5172     assert(in_bytes(SATBMarkQueue::byte_width_of_active()) == 1, "Assumption");
5173     cmpb(in_progress, 0);
5174   }
5175   jcc(Assembler::equal, done);
5176 
5177   // Do we need to load the previous value?
5178   if (obj != noreg) {
5179     load_heap_oop(pre_val, Address(obj, 0));
5180   }
5181 
5182   // Is the previous value null?
5183   cmpptr(pre_val, (int32_t) NULL_WORD);
5184   jcc(Assembler::equal, done);
5185 
5186   // Can we store original value in the thread's buffer?
5187   // Is index == 0?
5188   // (The index field is typed as size_t.)
5189 
5190   movptr(tmp, index);                   // tmp := *index_adr
5191   cmpptr(tmp, 0);                       // tmp == 0?
5192   jcc(Assembler::equal, runtime);       // If yes, goto runtime
5193 
5194   subptr(tmp, wordSize);                // tmp := tmp - wordSize
5195   movptr(index, tmp);                   // *index_adr := tmp
5196   addptr(tmp, buffer);                  // tmp := tmp + *buffer_adr
5197 
5198   // Record the previous value
5199   movptr(Address(tmp, 0), pre_val);
5200   jmp(done);
5201 
5202   bind(runtime);
5203   // save the live input values
5204   if(tosca_live) push(rax);
5205 
5206   if (obj != noreg && obj != rax)
5207     push(obj);
5208 
5209   if (pre_val != rax)
5210     push(pre_val);
5211 
5212   // Calling the runtime using the regular call_VM_leaf mechanism generates
5213   // code (generated by InterpreterMacroAssember::call_VM_leaf_base)
5214   // that checks that the *(ebp+frame::interpreter_frame_last_sp) == NULL.
5215   //
5216   // If we care generating the pre-barrier without a frame (e.g. in the
5217   // intrinsified Reference.get() routine) then ebp might be pointing to
5218   // the caller frame and so this check will most likely fail at runtime.
5219   //
5220   // Expanding the call directly bypasses the generation of the check.
5221   // So when we do not have have a full interpreter frame on the stack
5222   // expand_call should be passed true.
5223 
5224   NOT_LP64( push(thread); )
5225 
5226   if (expand_call) {
5227     LP64_ONLY( assert(pre_val != c_rarg1, "smashed arg"); )
5228     pass_arg1(this, thread);
5229     pass_arg0(this, pre_val);
5230     MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_pre), 2);
5231   } else {
5232     call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_pre), pre_val, thread);
5233   }
5234 
5235   NOT_LP64( pop(thread); )
5236 
5237   // save the live input values
5238   if (pre_val != rax)
5239     pop(pre_val);
5240 
5241   if (obj != noreg && obj != rax)
5242     pop(obj);
5243 
5244   if(tosca_live) pop(rax);
5245 
5246   bind(done);
5247 }
5248 
5249 void MacroAssembler::g1_write_barrier_post(Register store_addr,
5250                                            Register new_val,
5251                                            Register thread,
5252                                            Register tmp,
5253                                            Register tmp2) {
5254 #ifdef _LP64
5255   assert(thread == r15_thread, "must be");
5256 #endif // _LP64
5257 
5258   Address queue_index(thread, in_bytes(JavaThread::dirty_card_queue_offset() +
5259                                        DirtyCardQueue::byte_offset_of_index()));
5260   Address buffer(thread, in_bytes(JavaThread::dirty_card_queue_offset() +
5261                                        DirtyCardQueue::byte_offset_of_buf()));
5262 
5263   CardTableModRefBS* ct =
5264     barrier_set_cast<CardTableModRefBS>(Universe::heap()->barrier_set());
5265   assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code");
5266 
5267   Label done;
5268   Label runtime;
5269 
5270   // Does store cross heap regions?
5271 
5272   movptr(tmp, store_addr);
5273   xorptr(tmp, new_val);
5274   shrptr(tmp, HeapRegion::LogOfHRGrainBytes);
5275   jcc(Assembler::equal, done);
5276 
5277   // crosses regions, storing NULL?
5278 
5279   cmpptr(new_val, (int32_t) NULL_WORD);
5280   jcc(Assembler::equal, done);
5281 
5282   // storing region crossing non-NULL, is card already dirty?
5283 
5284   const Register card_addr = tmp;
5285   const Register cardtable = tmp2;
5286 
5287   movptr(card_addr, store_addr);
5288   shrptr(card_addr, CardTableModRefBS::card_shift);
5289   // Do not use ExternalAddress to load 'byte_map_base', since 'byte_map_base' is NOT
5290   // a valid address and therefore is not properly handled by the relocation code.
5291   movptr(cardtable, (intptr_t)ct->byte_map_base);
5292   addptr(card_addr, cardtable);
5293 
5294   cmpb(Address(card_addr, 0), (int)G1SATBCardTableModRefBS::g1_young_card_val());
5295   jcc(Assembler::equal, done);
5296 
5297   membar(Assembler::Membar_mask_bits(Assembler::StoreLoad));
5298   cmpb(Address(card_addr, 0), (int)CardTableModRefBS::dirty_card_val());
5299   jcc(Assembler::equal, done);
5300 
5301 
5302   // storing a region crossing, non-NULL oop, card is clean.
5303   // dirty card and log.
5304 
5305   movb(Address(card_addr, 0), (int)CardTableModRefBS::dirty_card_val());
5306 
5307   cmpl(queue_index, 0);
5308   jcc(Assembler::equal, runtime);
5309   subl(queue_index, wordSize);
5310   movptr(tmp2, buffer);
5311 #ifdef _LP64
5312   movslq(rscratch1, queue_index);
5313   addq(tmp2, rscratch1);
5314   movq(Address(tmp2, 0), card_addr);
5315 #else
5316   addl(tmp2, queue_index);
5317   movl(Address(tmp2, 0), card_addr);
5318 #endif
5319   jmp(done);
5320 
5321   bind(runtime);
5322   // save the live input values
5323   push(store_addr);
5324   push(new_val);
5325 #ifdef _LP64
5326   call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_post), card_addr, r15_thread);
5327 #else
5328   push(thread);
5329   call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_post), card_addr, thread);
5330   pop(thread);
5331 #endif
5332   pop(new_val);
5333   pop(store_addr);
5334 
5335   bind(done);
5336 }
5337 
5338 #endif // INCLUDE_ALL_GCS
5339 //////////////////////////////////////////////////////////////////////////////////
5340 
5341 
5342 void MacroAssembler::store_check(Register obj, Address dst) {
5343   store_check(obj);
5344 }
5345 
5346 void MacroAssembler::store_check(Register obj) {
5347   // Does a store check for the oop in register obj. The content of
5348   // register obj is destroyed afterwards.
5349   BarrierSet* bs = Universe::heap()->barrier_set();
5350   assert(bs->kind() == BarrierSet::CardTableForRS ||
5351          bs->kind() == BarrierSet::CardTableExtension,
5352          "Wrong barrier set kind");
5353 
5354   CardTableModRefBS* ct = barrier_set_cast<CardTableModRefBS>(bs);
5355   assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code");
5356 
5357   shrptr(obj, CardTableModRefBS::card_shift);
5358 
5359   Address card_addr;
5360 
5361   // The calculation for byte_map_base is as follows:
5362   // byte_map_base = _byte_map - (uintptr_t(low_bound) >> card_shift);
5363   // So this essentially converts an address to a displacement and it will
5364   // never need to be relocated. On 64bit however the value may be too
5365   // large for a 32bit displacement.
5366   intptr_t disp = (intptr_t) ct->byte_map_base;
5367   if (is_simm32(disp)) {
5368     card_addr = Address(noreg, obj, Address::times_1, disp);
5369   } else {
5370     // By doing it as an ExternalAddress 'disp' could be converted to a rip-relative
5371     // displacement and done in a single instruction given favorable mapping and a
5372     // smarter version of as_Address. However, 'ExternalAddress' generates a relocation
5373     // entry and that entry is not properly handled by the relocation code.
5374     AddressLiteral cardtable((address)ct->byte_map_base, relocInfo::none);
5375     Address index(noreg, obj, Address::times_1);
5376     card_addr = as_Address(ArrayAddress(cardtable, index));
5377   }
5378 
5379   int dirty = CardTableModRefBS::dirty_card_val();
5380   if (UseCondCardMark) {
5381     Label L_already_dirty;
5382     if (UseConcMarkSweepGC) {
5383       membar(Assembler::StoreLoad);
5384     }
5385     cmpb(card_addr, dirty);
5386     jcc(Assembler::equal, L_already_dirty);
5387     movb(card_addr, dirty);
5388     bind(L_already_dirty);
5389   } else {
5390     movb(card_addr, dirty);
5391   }
5392 }
5393 
5394 void MacroAssembler::subptr(Register dst, int32_t imm32) {
5395   LP64_ONLY(subq(dst, imm32)) NOT_LP64(subl(dst, imm32));
5396 }
5397 
5398 // Force generation of a 4 byte immediate value even if it fits into 8bit
5399 void MacroAssembler::subptr_imm32(Register dst, int32_t imm32) {
5400   LP64_ONLY(subq_imm32(dst, imm32)) NOT_LP64(subl_imm32(dst, imm32));
5401 }
5402 
5403 void MacroAssembler::subptr(Register dst, Register src) {
5404   LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src));
5405 }
5406 
5407 // C++ bool manipulation
5408 void MacroAssembler::testbool(Register dst) {
5409   if(sizeof(bool) == 1)
5410     testb(dst, 0xff);
5411   else if(sizeof(bool) == 2) {
5412     // testw implementation needed for two byte bools
5413     ShouldNotReachHere();
5414   } else if(sizeof(bool) == 4)
5415     testl(dst, dst);
5416   else
5417     // unsupported
5418     ShouldNotReachHere();
5419 }
5420 
5421 void MacroAssembler::testptr(Register dst, Register src) {
5422   LP64_ONLY(testq(dst, src)) NOT_LP64(testl(dst, src));
5423 }
5424 
5425 // Defines obj, preserves var_size_in_bytes, okay for t2 == var_size_in_bytes.
5426 void MacroAssembler::tlab_allocate(Register obj,
5427                                    Register var_size_in_bytes,
5428                                    int con_size_in_bytes,
5429                                    Register t1,
5430                                    Register t2,
5431                                    Label& slow_case) {
5432   assert_different_registers(obj, t1, t2);
5433   assert_different_registers(obj, var_size_in_bytes, t1);
5434   Register end = t2;
5435   Register thread = NOT_LP64(t1) LP64_ONLY(r15_thread);
5436 
5437   verify_tlab();
5438 
5439   NOT_LP64(get_thread(thread));
5440 
5441   movptr(obj, Address(thread, JavaThread::tlab_top_offset()));
5442   if (var_size_in_bytes == noreg) {
5443     lea(end, Address(obj, con_size_in_bytes));
5444   } else {
5445     lea(end, Address(obj, var_size_in_bytes, Address::times_1));
5446   }
5447   cmpptr(end, Address(thread, JavaThread::tlab_end_offset()));
5448   jcc(Assembler::above, slow_case);
5449 
5450   // update the tlab top pointer
5451   movptr(Address(thread, JavaThread::tlab_top_offset()), end);
5452 
5453   // recover var_size_in_bytes if necessary
5454   if (var_size_in_bytes == end) {
5455     subptr(var_size_in_bytes, obj);
5456   }
5457   verify_tlab();
5458 }
5459 
5460 // Preserves rbx, and rdx.
5461 Register MacroAssembler::tlab_refill(Label& retry,
5462                                      Label& try_eden,
5463                                      Label& slow_case) {
5464   Register top = rax;
5465   Register t1  = rcx; // object size
5466   Register t2  = rsi;
5467   Register thread_reg = NOT_LP64(rdi) LP64_ONLY(r15_thread);
5468   assert_different_registers(top, thread_reg, t1, t2, /* preserve: */ rbx, rdx);
5469   Label do_refill, discard_tlab;
5470 
5471   if (!Universe::heap()->supports_inline_contig_alloc()) {
5472     // No allocation in the shared eden.
5473     jmp(slow_case);
5474   }
5475 
5476   NOT_LP64(get_thread(thread_reg));
5477 
5478   movptr(top, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
5479   movptr(t1,  Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())));
5480 
5481   // calculate amount of free space
5482   subptr(t1, top);
5483   shrptr(t1, LogHeapWordSize);
5484 
5485   // Retain tlab and allocate object in shared space if
5486   // the amount free in the tlab is too large to discard.
5487   cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_refill_waste_limit_offset())));
5488   jcc(Assembler::lessEqual, discard_tlab);
5489 
5490   // Retain
5491   // %%% yuck as movptr...
5492   movptr(t2, (int32_t) ThreadLocalAllocBuffer::refill_waste_limit_increment());
5493   addptr(Address(thread_reg, in_bytes(JavaThread::tlab_refill_waste_limit_offset())), t2);
5494   if (TLABStats) {
5495     // increment number of slow_allocations
5496     addl(Address(thread_reg, in_bytes(JavaThread::tlab_slow_allocations_offset())), 1);
5497   }
5498   jmp(try_eden);
5499 
5500   bind(discard_tlab);
5501   if (TLABStats) {
5502     // increment number of refills
5503     addl(Address(thread_reg, in_bytes(JavaThread::tlab_number_of_refills_offset())), 1);
5504     // accumulate wastage -- t1 is amount free in tlab
5505     addl(Address(thread_reg, in_bytes(JavaThread::tlab_fast_refill_waste_offset())), t1);
5506   }
5507 
5508   // if tlab is currently allocated (top or end != null) then
5509   // fill [top, end + alignment_reserve) with array object
5510   testptr(top, top);
5511   jcc(Assembler::zero, do_refill);
5512 
5513   // set up the mark word
5514   movptr(Address(top, oopDesc::mark_offset_in_bytes()), (intptr_t)markOopDesc::prototype()->copy_set_hash(0x2));
5515   // set the length to the remaining space
5516   subptr(t1, typeArrayOopDesc::header_size(T_INT));
5517   addptr(t1, (int32_t)ThreadLocalAllocBuffer::alignment_reserve());
5518   shlptr(t1, log2_intptr(HeapWordSize/sizeof(jint)));
5519   movl(Address(top, arrayOopDesc::length_offset_in_bytes()), t1);
5520   // set klass to intArrayKlass
5521   // dubious reloc why not an oop reloc?
5522   movptr(t1, ExternalAddress((address)Universe::intArrayKlassObj_addr()));
5523   // store klass last.  concurrent gcs assumes klass length is valid if
5524   // klass field is not null.
5525   store_klass(top, t1);
5526 
5527   movptr(t1, top);
5528   subptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())));
5529   incr_allocated_bytes(thread_reg, t1, 0);
5530 
5531   // refill the tlab with an eden allocation
5532   bind(do_refill);
5533   movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_size_offset())));
5534   shlptr(t1, LogHeapWordSize);
5535   // allocate new tlab, address returned in top
5536   eden_allocate(top, t1, 0, t2, slow_case);
5537 
5538   // Check that t1 was preserved in eden_allocate.
5539 #ifdef ASSERT
5540   if (UseTLAB) {
5541     Label ok;
5542     Register tsize = rsi;
5543     assert_different_registers(tsize, thread_reg, t1);
5544     push(tsize);
5545     movptr(tsize, Address(thread_reg, in_bytes(JavaThread::tlab_size_offset())));
5546     shlptr(tsize, LogHeapWordSize);
5547     cmpptr(t1, tsize);
5548     jcc(Assembler::equal, ok);
5549     STOP("assert(t1 != tlab size)");
5550     should_not_reach_here();
5551 
5552     bind(ok);
5553     pop(tsize);
5554   }
5555 #endif
5556   movptr(Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())), top);
5557   movptr(Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())), top);
5558   addptr(top, t1);
5559   subptr(top, (int32_t)ThreadLocalAllocBuffer::alignment_reserve_in_bytes());
5560   movptr(Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())), top);
5561 
5562   if (ZeroTLAB) {
5563     // This is a fast TLAB refill, therefore the GC is not notified of it.
5564     // So compiled code must fill the new TLAB with zeroes.
5565     movptr(top, Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())));
5566     zero_memory(top, t1, 0, t2);
5567   }
5568 
5569   verify_tlab();
5570   jmp(retry);
5571 
5572   return thread_reg; // for use by caller
5573 }
5574 
5575 // Preserves the contents of address, destroys the contents length_in_bytes and temp.
5576 void MacroAssembler::zero_memory(Register address, Register length_in_bytes, int offset_in_bytes, Register temp) {
5577   assert(address != length_in_bytes && address != temp && temp != length_in_bytes, "registers must be different");
5578   assert((offset_in_bytes & (BytesPerWord - 1)) == 0, "offset must be a multiple of BytesPerWord");
5579   Label done;
5580 
5581   testptr(length_in_bytes, length_in_bytes);
5582   jcc(Assembler::zero, done);
5583 
5584   // initialize topmost word, divide index by 2, check if odd and test if zero
5585   // note: for the remaining code to work, index must be a multiple of BytesPerWord
5586 #ifdef ASSERT
5587   {
5588     Label L;
5589     testptr(length_in_bytes, BytesPerWord - 1);
5590     jcc(Assembler::zero, L);
5591     stop("length must be a multiple of BytesPerWord");
5592     bind(L);
5593   }
5594 #endif
5595   Register index = length_in_bytes;
5596   xorptr(temp, temp);    // use _zero reg to clear memory (shorter code)
5597   if (UseIncDec) {
5598     shrptr(index, 3);  // divide by 8/16 and set carry flag if bit 2 was set
5599   } else {
5600     shrptr(index, 2);  // use 2 instructions to avoid partial flag stall
5601     shrptr(index, 1);
5602   }
5603 #ifndef _LP64
5604   // index could have not been a multiple of 8 (i.e., bit 2 was set)
5605   {
5606     Label even;
5607     // note: if index was a multiple of 8, then it cannot
5608     //       be 0 now otherwise it must have been 0 before
5609     //       => if it is even, we don't need to check for 0 again
5610     jcc(Assembler::carryClear, even);
5611     // clear topmost word (no jump would be needed if conditional assignment worked here)
5612     movptr(Address(address, index, Address::times_8, offset_in_bytes - 0*BytesPerWord), temp);
5613     // index could be 0 now, must check again
5614     jcc(Assembler::zero, done);
5615     bind(even);
5616   }
5617 #endif // !_LP64
5618   // initialize remaining object fields: index is a multiple of 2 now
5619   {
5620     Label loop;
5621     bind(loop);
5622     movptr(Address(address, index, Address::times_8, offset_in_bytes - 1*BytesPerWord), temp);
5623     NOT_LP64(movptr(Address(address, index, Address::times_8, offset_in_bytes - 2*BytesPerWord), temp);)
5624     decrement(index);
5625     jcc(Assembler::notZero, loop);
5626   }
5627 
5628   bind(done);
5629 }
5630 
5631 void MacroAssembler::incr_allocated_bytes(Register thread,
5632                                           Register var_size_in_bytes,
5633                                           int con_size_in_bytes,
5634                                           Register t1) {
5635   if (!thread->is_valid()) {
5636 #ifdef _LP64
5637     thread = r15_thread;
5638 #else
5639     assert(t1->is_valid(), "need temp reg");
5640     thread = t1;
5641     get_thread(thread);
5642 #endif
5643   }
5644 
5645 #ifdef _LP64
5646   if (var_size_in_bytes->is_valid()) {
5647     addq(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), var_size_in_bytes);
5648   } else {
5649     addq(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), con_size_in_bytes);
5650   }
5651 #else
5652   if (var_size_in_bytes->is_valid()) {
5653     addl(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), var_size_in_bytes);
5654   } else {
5655     addl(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), con_size_in_bytes);
5656   }
5657   adcl(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())+4), 0);
5658 #endif
5659 }
5660 
5661 // Look up the method for a megamorphic invokeinterface call.
5662 // The target method is determined by <intf_klass, itable_index>.
5663 // The receiver klass is in recv_klass.
5664 // On success, the result will be in method_result, and execution falls through.
5665 // On failure, execution transfers to the given label.
5666 void MacroAssembler::lookup_interface_method(Register recv_klass,
5667                                              Register intf_klass,
5668                                              RegisterOrConstant itable_index,
5669                                              Register method_result,
5670                                              Register scan_temp,
5671                                              Label& L_no_such_interface) {
5672   assert_different_registers(recv_klass, intf_klass, method_result, scan_temp);
5673   assert(itable_index.is_constant() || itable_index.as_register() == method_result,
5674          "caller must use same register for non-constant itable index as for method");
5675 
5676   // Compute start of first itableOffsetEntry (which is at the end of the vtable)
5677   int vtable_base = in_bytes(Klass::vtable_start_offset());
5678   int itentry_off = itableMethodEntry::method_offset_in_bytes();
5679   int scan_step   = itableOffsetEntry::size() * wordSize;
5680   int vte_size    = vtableEntry::size_in_bytes();
5681   Address::ScaleFactor times_vte_scale = Address::times_ptr;
5682   assert(vte_size == wordSize, "else adjust times_vte_scale");
5683 
5684   movl(scan_temp, Address(recv_klass, Klass::vtable_length_offset()));
5685 
5686   // %%% Could store the aligned, prescaled offset in the klassoop.
5687   lea(scan_temp, Address(recv_klass, scan_temp, times_vte_scale, vtable_base));
5688 
5689   // Adjust recv_klass by scaled itable_index, so we can free itable_index.
5690   assert(itableMethodEntry::size() * wordSize == wordSize, "adjust the scaling in the code below");
5691   lea(recv_klass, Address(recv_klass, itable_index, Address::times_ptr, itentry_off));
5692 
5693   // for (scan = klass->itable(); scan->interface() != NULL; scan += scan_step) {
5694   //   if (scan->interface() == intf) {
5695   //     result = (klass + scan->offset() + itable_index);
5696   //   }
5697   // }
5698   Label search, found_method;
5699 
5700   for (int peel = 1; peel >= 0; peel--) {
5701     movptr(method_result, Address(scan_temp, itableOffsetEntry::interface_offset_in_bytes()));
5702     cmpptr(intf_klass, method_result);
5703 
5704     if (peel) {
5705       jccb(Assembler::equal, found_method);
5706     } else {
5707       jccb(Assembler::notEqual, search);
5708       // (invert the test to fall through to found_method...)
5709     }
5710 
5711     if (!peel)  break;
5712 
5713     bind(search);
5714 
5715     // Check that the previous entry is non-null.  A null entry means that
5716     // the receiver class doesn't implement the interface, and wasn't the
5717     // same as when the caller was compiled.
5718     testptr(method_result, method_result);
5719     jcc(Assembler::zero, L_no_such_interface);
5720     addptr(scan_temp, scan_step);
5721   }
5722 
5723   bind(found_method);
5724 
5725   // Got a hit.
5726   movl(scan_temp, Address(scan_temp, itableOffsetEntry::offset_offset_in_bytes()));
5727   movptr(method_result, Address(recv_klass, scan_temp, Address::times_1));
5728 }
5729 
5730 
5731 // virtual method calling
5732 void MacroAssembler::lookup_virtual_method(Register recv_klass,
5733                                            RegisterOrConstant vtable_index,
5734                                            Register method_result) {
5735   const int base = in_bytes(Klass::vtable_start_offset());
5736   assert(vtableEntry::size() * wordSize == wordSize, "else adjust the scaling in the code below");
5737   Address vtable_entry_addr(recv_klass,
5738                             vtable_index, Address::times_ptr,
5739                             base + vtableEntry::method_offset_in_bytes());
5740   movptr(method_result, vtable_entry_addr);
5741 }
5742 
5743 
5744 void MacroAssembler::check_klass_subtype(Register sub_klass,
5745                            Register super_klass,
5746                            Register temp_reg,
5747                            Label& L_success) {
5748   Label L_failure;
5749   check_klass_subtype_fast_path(sub_klass, super_klass, temp_reg,        &L_success, &L_failure, NULL);
5750   check_klass_subtype_slow_path(sub_klass, super_klass, temp_reg, noreg, &L_success, NULL);
5751   bind(L_failure);
5752 }
5753 
5754 
5755 void MacroAssembler::check_klass_subtype_fast_path(Register sub_klass,
5756                                                    Register super_klass,
5757                                                    Register temp_reg,
5758                                                    Label* L_success,
5759                                                    Label* L_failure,
5760                                                    Label* L_slow_path,
5761                                         RegisterOrConstant super_check_offset) {
5762   assert_different_registers(sub_klass, super_klass, temp_reg);
5763   bool must_load_sco = (super_check_offset.constant_or_zero() == -1);
5764   if (super_check_offset.is_register()) {
5765     assert_different_registers(sub_klass, super_klass,
5766                                super_check_offset.as_register());
5767   } else if (must_load_sco) {
5768     assert(temp_reg != noreg, "supply either a temp or a register offset");
5769   }
5770 
5771   Label L_fallthrough;
5772   int label_nulls = 0;
5773   if (L_success == NULL)   { L_success   = &L_fallthrough; label_nulls++; }
5774   if (L_failure == NULL)   { L_failure   = &L_fallthrough; label_nulls++; }
5775   if (L_slow_path == NULL) { L_slow_path = &L_fallthrough; label_nulls++; }
5776   assert(label_nulls <= 1, "at most one NULL in the batch");
5777 
5778   int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
5779   int sco_offset = in_bytes(Klass::super_check_offset_offset());
5780   Address super_check_offset_addr(super_klass, sco_offset);
5781 
5782   // Hacked jcc, which "knows" that L_fallthrough, at least, is in
5783   // range of a jccb.  If this routine grows larger, reconsider at
5784   // least some of these.
5785 #define local_jcc(assembler_cond, label)                                \
5786   if (&(label) == &L_fallthrough)  jccb(assembler_cond, label);         \
5787   else                             jcc( assembler_cond, label) /*omit semi*/
5788 
5789   // Hacked jmp, which may only be used just before L_fallthrough.
5790 #define final_jmp(label)                                                \
5791   if (&(label) == &L_fallthrough) { /*do nothing*/ }                    \
5792   else                            jmp(label)                /*omit semi*/
5793 
5794   // If the pointers are equal, we are done (e.g., String[] elements).
5795   // This self-check enables sharing of secondary supertype arrays among
5796   // non-primary types such as array-of-interface.  Otherwise, each such
5797   // type would need its own customized SSA.
5798   // We move this check to the front of the fast path because many
5799   // type checks are in fact trivially successful in this manner,
5800   // so we get a nicely predicted branch right at the start of the check.
5801   cmpptr(sub_klass, super_klass);
5802   local_jcc(Assembler::equal, *L_success);
5803 
5804   // Check the supertype display:
5805   if (must_load_sco) {
5806     // Positive movl does right thing on LP64.
5807     movl(temp_reg, super_check_offset_addr);
5808     super_check_offset = RegisterOrConstant(temp_reg);
5809   }
5810   Address super_check_addr(sub_klass, super_check_offset, Address::times_1, 0);
5811   cmpptr(super_klass, super_check_addr); // load displayed supertype
5812 
5813   // This check has worked decisively for primary supers.
5814   // Secondary supers are sought in the super_cache ('super_cache_addr').
5815   // (Secondary supers are interfaces and very deeply nested subtypes.)
5816   // This works in the same check above because of a tricky aliasing
5817   // between the super_cache and the primary super display elements.
5818   // (The 'super_check_addr' can address either, as the case requires.)
5819   // Note that the cache is updated below if it does not help us find
5820   // what we need immediately.
5821   // So if it was a primary super, we can just fail immediately.
5822   // Otherwise, it's the slow path for us (no success at this point).
5823 
5824   if (super_check_offset.is_register()) {
5825     local_jcc(Assembler::equal, *L_success);
5826     cmpl(super_check_offset.as_register(), sc_offset);
5827     if (L_failure == &L_fallthrough) {
5828       local_jcc(Assembler::equal, *L_slow_path);
5829     } else {
5830       local_jcc(Assembler::notEqual, *L_failure);
5831       final_jmp(*L_slow_path);
5832     }
5833   } else if (super_check_offset.as_constant() == sc_offset) {
5834     // Need a slow path; fast failure is impossible.
5835     if (L_slow_path == &L_fallthrough) {
5836       local_jcc(Assembler::equal, *L_success);
5837     } else {
5838       local_jcc(Assembler::notEqual, *L_slow_path);
5839       final_jmp(*L_success);
5840     }
5841   } else {
5842     // No slow path; it's a fast decision.
5843     if (L_failure == &L_fallthrough) {
5844       local_jcc(Assembler::equal, *L_success);
5845     } else {
5846       local_jcc(Assembler::notEqual, *L_failure);
5847       final_jmp(*L_success);
5848     }
5849   }
5850 
5851   bind(L_fallthrough);
5852 
5853 #undef local_jcc
5854 #undef final_jmp
5855 }
5856 
5857 
5858 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass,
5859                                                    Register super_klass,
5860                                                    Register temp_reg,
5861                                                    Register temp2_reg,
5862                                                    Label* L_success,
5863                                                    Label* L_failure,
5864                                                    bool set_cond_codes) {
5865   assert_different_registers(sub_klass, super_klass, temp_reg);
5866   if (temp2_reg != noreg)
5867     assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg);
5868 #define IS_A_TEMP(reg) ((reg) == temp_reg || (reg) == temp2_reg)
5869 
5870   Label L_fallthrough;
5871   int label_nulls = 0;
5872   if (L_success == NULL)   { L_success   = &L_fallthrough; label_nulls++; }
5873   if (L_failure == NULL)   { L_failure   = &L_fallthrough; label_nulls++; }
5874   assert(label_nulls <= 1, "at most one NULL in the batch");
5875 
5876   // a couple of useful fields in sub_klass:
5877   int ss_offset = in_bytes(Klass::secondary_supers_offset());
5878   int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
5879   Address secondary_supers_addr(sub_klass, ss_offset);
5880   Address super_cache_addr(     sub_klass, sc_offset);
5881 
5882   // Do a linear scan of the secondary super-klass chain.
5883   // This code is rarely used, so simplicity is a virtue here.
5884   // The repne_scan instruction uses fixed registers, which we must spill.
5885   // Don't worry too much about pre-existing connections with the input regs.
5886 
5887   assert(sub_klass != rax, "killed reg"); // killed by mov(rax, super)
5888   assert(sub_klass != rcx, "killed reg"); // killed by lea(rcx, &pst_counter)
5889 
5890   // Get super_klass value into rax (even if it was in rdi or rcx).
5891   bool pushed_rax = false, pushed_rcx = false, pushed_rdi = false;
5892   if (super_klass != rax || UseCompressedOops) {
5893     if (!IS_A_TEMP(rax)) { push(rax); pushed_rax = true; }
5894     mov(rax, super_klass);
5895   }
5896   if (!IS_A_TEMP(rcx)) { push(rcx); pushed_rcx = true; }
5897   if (!IS_A_TEMP(rdi)) { push(rdi); pushed_rdi = true; }
5898 
5899 #ifndef PRODUCT
5900   int* pst_counter = &SharedRuntime::_partial_subtype_ctr;
5901   ExternalAddress pst_counter_addr((address) pst_counter);
5902   NOT_LP64(  incrementl(pst_counter_addr) );
5903   LP64_ONLY( lea(rcx, pst_counter_addr) );
5904   LP64_ONLY( incrementl(Address(rcx, 0)) );
5905 #endif //PRODUCT
5906 
5907   // We will consult the secondary-super array.
5908   movptr(rdi, secondary_supers_addr);
5909   // Load the array length.  (Positive movl does right thing on LP64.)
5910   movl(rcx, Address(rdi, Array<Klass*>::length_offset_in_bytes()));
5911   // Skip to start of data.
5912   addptr(rdi, Array<Klass*>::base_offset_in_bytes());
5913 
5914   // Scan RCX words at [RDI] for an occurrence of RAX.
5915   // Set NZ/Z based on last compare.
5916   // Z flag value will not be set by 'repne' if RCX == 0 since 'repne' does
5917   // not change flags (only scas instruction which is repeated sets flags).
5918   // Set Z = 0 (not equal) before 'repne' to indicate that class was not found.
5919 
5920     testptr(rax,rax); // Set Z = 0
5921     repne_scan();
5922 
5923   // Unspill the temp. registers:
5924   if (pushed_rdi)  pop(rdi);
5925   if (pushed_rcx)  pop(rcx);
5926   if (pushed_rax)  pop(rax);
5927 
5928   if (set_cond_codes) {
5929     // Special hack for the AD files:  rdi is guaranteed non-zero.
5930     assert(!pushed_rdi, "rdi must be left non-NULL");
5931     // Also, the condition codes are properly set Z/NZ on succeed/failure.
5932   }
5933 
5934   if (L_failure == &L_fallthrough)
5935         jccb(Assembler::notEqual, *L_failure);
5936   else  jcc(Assembler::notEqual, *L_failure);
5937 
5938   // Success.  Cache the super we found and proceed in triumph.
5939   movptr(super_cache_addr, super_klass);
5940 
5941   if (L_success != &L_fallthrough) {
5942     jmp(*L_success);
5943   }
5944 
5945 #undef IS_A_TEMP
5946 
5947   bind(L_fallthrough);
5948 }
5949 
5950 
5951 void MacroAssembler::cmov32(Condition cc, Register dst, Address src) {
5952   if (VM_Version::supports_cmov()) {
5953     cmovl(cc, dst, src);
5954   } else {
5955     Label L;
5956     jccb(negate_condition(cc), L);
5957     movl(dst, src);
5958     bind(L);
5959   }
5960 }
5961 
5962 void MacroAssembler::cmov32(Condition cc, Register dst, Register src) {
5963   if (VM_Version::supports_cmov()) {
5964     cmovl(cc, dst, src);
5965   } else {
5966     Label L;
5967     jccb(negate_condition(cc), L);
5968     movl(dst, src);
5969     bind(L);
5970   }
5971 }
5972 
5973 void MacroAssembler::verify_oop(Register reg, const char* s) {
5974   if (!VerifyOops) return;
5975 
5976   // Pass register number to verify_oop_subroutine
5977   const char* b = NULL;
5978   {
5979     ResourceMark rm;
5980     stringStream ss;
5981     ss.print("verify_oop: %s: %s", reg->name(), s);
5982     b = code_string(ss.as_string());
5983   }
5984   BLOCK_COMMENT("verify_oop {");
5985 #ifdef _LP64
5986   push(rscratch1);                    // save r10, trashed by movptr()
5987 #endif
5988   push(rax);                          // save rax,
5989   push(reg);                          // pass register argument
5990   ExternalAddress buffer((address) b);
5991   // avoid using pushptr, as it modifies scratch registers
5992   // and our contract is not to modify anything
5993   movptr(rax, buffer.addr());
5994   push(rax);
5995   // call indirectly to solve generation ordering problem
5996   movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
5997   call(rax);
5998   // Caller pops the arguments (oop, message) and restores rax, r10
5999   BLOCK_COMMENT("} verify_oop");
6000 }
6001 
6002 
6003 RegisterOrConstant MacroAssembler::delayed_value_impl(intptr_t* delayed_value_addr,
6004                                                       Register tmp,
6005                                                       int offset) {
6006   intptr_t value = *delayed_value_addr;
6007   if (value != 0)
6008     return RegisterOrConstant(value + offset);
6009 
6010   // load indirectly to solve generation ordering problem
6011   movptr(tmp, ExternalAddress((address) delayed_value_addr));
6012 
6013 #ifdef ASSERT
6014   { Label L;
6015     testptr(tmp, tmp);
6016     if (WizardMode) {
6017       const char* buf = NULL;
6018       {
6019         ResourceMark rm;
6020         stringStream ss;
6021         ss.print("DelayedValue=" INTPTR_FORMAT, delayed_value_addr[1]);
6022         buf = code_string(ss.as_string());
6023       }
6024       jcc(Assembler::notZero, L);
6025       STOP(buf);
6026     } else {
6027       jccb(Assembler::notZero, L);
6028       hlt();
6029     }
6030     bind(L);
6031   }
6032 #endif
6033 
6034   if (offset != 0)
6035     addptr(tmp, offset);
6036 
6037   return RegisterOrConstant(tmp);
6038 }
6039 
6040 
6041 Address MacroAssembler::argument_address(RegisterOrConstant arg_slot,
6042                                          int extra_slot_offset) {
6043   // cf. TemplateTable::prepare_invoke(), if (load_receiver).
6044   int stackElementSize = Interpreter::stackElementSize;
6045   int offset = Interpreter::expr_offset_in_bytes(extra_slot_offset+0);
6046 #ifdef ASSERT
6047   int offset1 = Interpreter::expr_offset_in_bytes(extra_slot_offset+1);
6048   assert(offset1 - offset == stackElementSize, "correct arithmetic");
6049 #endif
6050   Register             scale_reg    = noreg;
6051   Address::ScaleFactor scale_factor = Address::no_scale;
6052   if (arg_slot.is_constant()) {
6053     offset += arg_slot.as_constant() * stackElementSize;
6054   } else {
6055     scale_reg    = arg_slot.as_register();
6056     scale_factor = Address::times(stackElementSize);
6057   }
6058   offset += wordSize;           // return PC is on stack
6059   return Address(rsp, scale_reg, scale_factor, offset);
6060 }
6061 
6062 
6063 void MacroAssembler::verify_oop_addr(Address addr, const char* s) {
6064   if (!VerifyOops) return;
6065 
6066   // Address adjust(addr.base(), addr.index(), addr.scale(), addr.disp() + BytesPerWord);
6067   // Pass register number to verify_oop_subroutine
6068   const char* b = NULL;
6069   {
6070     ResourceMark rm;
6071     stringStream ss;
6072     ss.print("verify_oop_addr: %s", s);
6073     b = code_string(ss.as_string());
6074   }
6075 #ifdef _LP64
6076   push(rscratch1);                    // save r10, trashed by movptr()
6077 #endif
6078   push(rax);                          // save rax,
6079   // addr may contain rsp so we will have to adjust it based on the push
6080   // we just did (and on 64 bit we do two pushes)
6081   // NOTE: 64bit seemed to have had a bug in that it did movq(addr, rax); which
6082   // stores rax into addr which is backwards of what was intended.
6083   if (addr.uses(rsp)) {
6084     lea(rax, addr);
6085     pushptr(Address(rax, LP64_ONLY(2 *) BytesPerWord));
6086   } else {
6087     pushptr(addr);
6088   }
6089 
6090   ExternalAddress buffer((address) b);
6091   // pass msg argument
6092   // avoid using pushptr, as it modifies scratch registers
6093   // and our contract is not to modify anything
6094   movptr(rax, buffer.addr());
6095   push(rax);
6096 
6097   // call indirectly to solve generation ordering problem
6098   movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
6099   call(rax);
6100   // Caller pops the arguments (addr, message) and restores rax, r10.
6101 }
6102 
6103 void MacroAssembler::verify_tlab() {
6104 #ifdef ASSERT
6105   if (UseTLAB && VerifyOops) {
6106     Label next, ok;
6107     Register t1 = rsi;
6108     Register thread_reg = NOT_LP64(rbx) LP64_ONLY(r15_thread);
6109 
6110     push(t1);
6111     NOT_LP64(push(thread_reg));
6112     NOT_LP64(get_thread(thread_reg));
6113 
6114     movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
6115     cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())));
6116     jcc(Assembler::aboveEqual, next);
6117     STOP("assert(top >= start)");
6118     should_not_reach_here();
6119 
6120     bind(next);
6121     movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())));
6122     cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
6123     jcc(Assembler::aboveEqual, ok);
6124     STOP("assert(top <= end)");
6125     should_not_reach_here();
6126 
6127     bind(ok);
6128     NOT_LP64(pop(thread_reg));
6129     pop(t1);
6130   }
6131 #endif
6132 }
6133 
6134 class ControlWord {
6135  public:
6136   int32_t _value;
6137 
6138   int  rounding_control() const        { return  (_value >> 10) & 3      ; }
6139   int  precision_control() const       { return  (_value >>  8) & 3      ; }
6140   bool precision() const               { return ((_value >>  5) & 1) != 0; }
6141   bool underflow() const               { return ((_value >>  4) & 1) != 0; }
6142   bool overflow() const                { return ((_value >>  3) & 1) != 0; }
6143   bool zero_divide() const             { return ((_value >>  2) & 1) != 0; }
6144   bool denormalized() const            { return ((_value >>  1) & 1) != 0; }
6145   bool invalid() const                 { return ((_value >>  0) & 1) != 0; }
6146 
6147   void print() const {
6148     // rounding control
6149     const char* rc;
6150     switch (rounding_control()) {
6151       case 0: rc = "round near"; break;
6152       case 1: rc = "round down"; break;
6153       case 2: rc = "round up  "; break;
6154       case 3: rc = "chop      "; break;
6155     };
6156     // precision control
6157     const char* pc;
6158     switch (precision_control()) {
6159       case 0: pc = "24 bits "; break;
6160       case 1: pc = "reserved"; break;
6161       case 2: pc = "53 bits "; break;
6162       case 3: pc = "64 bits "; break;
6163     };
6164     // flags
6165     char f[9];
6166     f[0] = ' ';
6167     f[1] = ' ';
6168     f[2] = (precision   ()) ? 'P' : 'p';
6169     f[3] = (underflow   ()) ? 'U' : 'u';
6170     f[4] = (overflow    ()) ? 'O' : 'o';
6171     f[5] = (zero_divide ()) ? 'Z' : 'z';
6172     f[6] = (denormalized()) ? 'D' : 'd';
6173     f[7] = (invalid     ()) ? 'I' : 'i';
6174     f[8] = '\x0';
6175     // output
6176     printf("%04x  masks = %s, %s, %s", _value & 0xFFFF, f, rc, pc);
6177   }
6178 
6179 };
6180 
6181 class StatusWord {
6182  public:
6183   int32_t _value;
6184 
6185   bool busy() const                    { return ((_value >> 15) & 1) != 0; }
6186   bool C3() const                      { return ((_value >> 14) & 1) != 0; }
6187   bool C2() const                      { return ((_value >> 10) & 1) != 0; }
6188   bool C1() const                      { return ((_value >>  9) & 1) != 0; }
6189   bool C0() const                      { return ((_value >>  8) & 1) != 0; }
6190   int  top() const                     { return  (_value >> 11) & 7      ; }
6191   bool error_status() const            { return ((_value >>  7) & 1) != 0; }
6192   bool stack_fault() const             { return ((_value >>  6) & 1) != 0; }
6193   bool precision() const               { return ((_value >>  5) & 1) != 0; }
6194   bool underflow() const               { return ((_value >>  4) & 1) != 0; }
6195   bool overflow() const                { return ((_value >>  3) & 1) != 0; }
6196   bool zero_divide() const             { return ((_value >>  2) & 1) != 0; }
6197   bool denormalized() const            { return ((_value >>  1) & 1) != 0; }
6198   bool invalid() const                 { return ((_value >>  0) & 1) != 0; }
6199 
6200   void print() const {
6201     // condition codes
6202     char c[5];
6203     c[0] = (C3()) ? '3' : '-';
6204     c[1] = (C2()) ? '2' : '-';
6205     c[2] = (C1()) ? '1' : '-';
6206     c[3] = (C0()) ? '0' : '-';
6207     c[4] = '\x0';
6208     // flags
6209     char f[9];
6210     f[0] = (error_status()) ? 'E' : '-';
6211     f[1] = (stack_fault ()) ? 'S' : '-';
6212     f[2] = (precision   ()) ? 'P' : '-';
6213     f[3] = (underflow   ()) ? 'U' : '-';
6214     f[4] = (overflow    ()) ? 'O' : '-';
6215     f[5] = (zero_divide ()) ? 'Z' : '-';
6216     f[6] = (denormalized()) ? 'D' : '-';
6217     f[7] = (invalid     ()) ? 'I' : '-';
6218     f[8] = '\x0';
6219     // output
6220     printf("%04x  flags = %s, cc =  %s, top = %d", _value & 0xFFFF, f, c, top());
6221   }
6222 
6223 };
6224 
6225 class TagWord {
6226  public:
6227   int32_t _value;
6228 
6229   int tag_at(int i) const              { return (_value >> (i*2)) & 3; }
6230 
6231   void print() const {
6232     printf("%04x", _value & 0xFFFF);
6233   }
6234 
6235 };
6236 
6237 class FPU_Register {
6238  public:
6239   int32_t _m0;
6240   int32_t _m1;
6241   int16_t _ex;
6242 
6243   bool is_indefinite() const           {
6244     return _ex == -1 && _m1 == (int32_t)0xC0000000 && _m0 == 0;
6245   }
6246 
6247   void print() const {
6248     char  sign = (_ex < 0) ? '-' : '+';
6249     const char* kind = (_ex == 0x7FFF || _ex == (int16_t)-1) ? "NaN" : "   ";
6250     printf("%c%04hx.%08x%08x  %s", sign, _ex, _m1, _m0, kind);
6251   };
6252 
6253 };
6254 
6255 class FPU_State {
6256  public:
6257   enum {
6258     register_size       = 10,
6259     number_of_registers =  8,
6260     register_mask       =  7
6261   };
6262 
6263   ControlWord  _control_word;
6264   StatusWord   _status_word;
6265   TagWord      _tag_word;
6266   int32_t      _error_offset;
6267   int32_t      _error_selector;
6268   int32_t      _data_offset;
6269   int32_t      _data_selector;
6270   int8_t       _register[register_size * number_of_registers];
6271 
6272   int tag_for_st(int i) const          { return _tag_word.tag_at((_status_word.top() + i) & register_mask); }
6273   FPU_Register* st(int i) const        { return (FPU_Register*)&_register[register_size * i]; }
6274 
6275   const char* tag_as_string(int tag) const {
6276     switch (tag) {
6277       case 0: return "valid";
6278       case 1: return "zero";
6279       case 2: return "special";
6280       case 3: return "empty";
6281     }
6282     ShouldNotReachHere();
6283     return NULL;
6284   }
6285 
6286   void print() const {
6287     // print computation registers
6288     { int t = _status_word.top();
6289       for (int i = 0; i < number_of_registers; i++) {
6290         int j = (i - t) & register_mask;
6291         printf("%c r%d = ST%d = ", (j == 0 ? '*' : ' '), i, j);
6292         st(j)->print();
6293         printf(" %s\n", tag_as_string(_tag_word.tag_at(i)));
6294       }
6295     }
6296     printf("\n");
6297     // print control registers
6298     printf("ctrl = "); _control_word.print(); printf("\n");
6299     printf("stat = "); _status_word .print(); printf("\n");
6300     printf("tags = "); _tag_word    .print(); printf("\n");
6301   }
6302 
6303 };
6304 
6305 class Flag_Register {
6306  public:
6307   int32_t _value;
6308 
6309   bool overflow() const                { return ((_value >> 11) & 1) != 0; }
6310   bool direction() const               { return ((_value >> 10) & 1) != 0; }
6311   bool sign() const                    { return ((_value >>  7) & 1) != 0; }
6312   bool zero() const                    { return ((_value >>  6) & 1) != 0; }
6313   bool auxiliary_carry() const         { return ((_value >>  4) & 1) != 0; }
6314   bool parity() const                  { return ((_value >>  2) & 1) != 0; }
6315   bool carry() const                   { return ((_value >>  0) & 1) != 0; }
6316 
6317   void print() const {
6318     // flags
6319     char f[8];
6320     f[0] = (overflow       ()) ? 'O' : '-';
6321     f[1] = (direction      ()) ? 'D' : '-';
6322     f[2] = (sign           ()) ? 'S' : '-';
6323     f[3] = (zero           ()) ? 'Z' : '-';
6324     f[4] = (auxiliary_carry()) ? 'A' : '-';
6325     f[5] = (parity         ()) ? 'P' : '-';
6326     f[6] = (carry          ()) ? 'C' : '-';
6327     f[7] = '\x0';
6328     // output
6329     printf("%08x  flags = %s", _value, f);
6330   }
6331 
6332 };
6333 
6334 class IU_Register {
6335  public:
6336   int32_t _value;
6337 
6338   void print() const {
6339     printf("%08x  %11d", _value, _value);
6340   }
6341 
6342 };
6343 
6344 class IU_State {
6345  public:
6346   Flag_Register _eflags;
6347   IU_Register   _rdi;
6348   IU_Register   _rsi;
6349   IU_Register   _rbp;
6350   IU_Register   _rsp;
6351   IU_Register   _rbx;
6352   IU_Register   _rdx;
6353   IU_Register   _rcx;
6354   IU_Register   _rax;
6355 
6356   void print() const {
6357     // computation registers
6358     printf("rax,  = "); _rax.print(); printf("\n");
6359     printf("rbx,  = "); _rbx.print(); printf("\n");
6360     printf("rcx  = "); _rcx.print(); printf("\n");
6361     printf("rdx  = "); _rdx.print(); printf("\n");
6362     printf("rdi  = "); _rdi.print(); printf("\n");
6363     printf("rsi  = "); _rsi.print(); printf("\n");
6364     printf("rbp,  = "); _rbp.print(); printf("\n");
6365     printf("rsp  = "); _rsp.print(); printf("\n");
6366     printf("\n");
6367     // control registers
6368     printf("flgs = "); _eflags.print(); printf("\n");
6369   }
6370 };
6371 
6372 
6373 class CPU_State {
6374  public:
6375   FPU_State _fpu_state;
6376   IU_State  _iu_state;
6377 
6378   void print() const {
6379     printf("--------------------------------------------------\n");
6380     _iu_state .print();
6381     printf("\n");
6382     _fpu_state.print();
6383     printf("--------------------------------------------------\n");
6384   }
6385 
6386 };
6387 
6388 
6389 static void _print_CPU_state(CPU_State* state) {
6390   state->print();
6391 };
6392 
6393 
6394 void MacroAssembler::print_CPU_state() {
6395   push_CPU_state();
6396   push(rsp);                // pass CPU state
6397   call(RuntimeAddress(CAST_FROM_FN_PTR(address, _print_CPU_state)));
6398   addptr(rsp, wordSize);       // discard argument
6399   pop_CPU_state();
6400 }
6401 
6402 
6403 static bool _verify_FPU(int stack_depth, char* s, CPU_State* state) {
6404   static int counter = 0;
6405   FPU_State* fs = &state->_fpu_state;
6406   counter++;
6407   // For leaf calls, only verify that the top few elements remain empty.
6408   // We only need 1 empty at the top for C2 code.
6409   if( stack_depth < 0 ) {
6410     if( fs->tag_for_st(7) != 3 ) {
6411       printf("FPR7 not empty\n");
6412       state->print();
6413       assert(false, "error");
6414       return false;
6415     }
6416     return true;                // All other stack states do not matter
6417   }
6418 
6419   assert((fs->_control_word._value & 0xffff) == StubRoutines::_fpu_cntrl_wrd_std,
6420          "bad FPU control word");
6421 
6422   // compute stack depth
6423   int i = 0;
6424   while (i < FPU_State::number_of_registers && fs->tag_for_st(i)  < 3) i++;
6425   int d = i;
6426   while (i < FPU_State::number_of_registers && fs->tag_for_st(i) == 3) i++;
6427   // verify findings
6428   if (i != FPU_State::number_of_registers) {
6429     // stack not contiguous
6430     printf("%s: stack not contiguous at ST%d\n", s, i);
6431     state->print();
6432     assert(false, "error");
6433     return false;
6434   }
6435   // check if computed stack depth corresponds to expected stack depth
6436   if (stack_depth < 0) {
6437     // expected stack depth is -stack_depth or less
6438     if (d > -stack_depth) {
6439       // too many elements on the stack
6440       printf("%s: <= %d stack elements expected but found %d\n", s, -stack_depth, d);
6441       state->print();
6442       assert(false, "error");
6443       return false;
6444     }
6445   } else {
6446     // expected stack depth is stack_depth
6447     if (d != stack_depth) {
6448       // wrong stack depth
6449       printf("%s: %d stack elements expected but found %d\n", s, stack_depth, d);
6450       state->print();
6451       assert(false, "error");
6452       return false;
6453     }
6454   }
6455   // everything is cool
6456   return true;
6457 }
6458 
6459 
6460 void MacroAssembler::verify_FPU(int stack_depth, const char* s) {
6461   if (!VerifyFPU) return;
6462   push_CPU_state();
6463   push(rsp);                // pass CPU state
6464   ExternalAddress msg((address) s);
6465   // pass message string s
6466   pushptr(msg.addr());
6467   push(stack_depth);        // pass stack depth
6468   call(RuntimeAddress(CAST_FROM_FN_PTR(address, _verify_FPU)));
6469   addptr(rsp, 3 * wordSize);   // discard arguments
6470   // check for error
6471   { Label L;
6472     testl(rax, rax);
6473     jcc(Assembler::notZero, L);
6474     int3();                  // break if error condition
6475     bind(L);
6476   }
6477   pop_CPU_state();
6478 }
6479 
6480 void MacroAssembler::restore_cpu_control_state_after_jni() {
6481   // Either restore the MXCSR register after returning from the JNI Call
6482   // or verify that it wasn't changed (with -Xcheck:jni flag).
6483   if (VM_Version::supports_sse()) {
6484     if (RestoreMXCSROnJNICalls) {
6485       ldmxcsr(ExternalAddress(StubRoutines::addr_mxcsr_std()));
6486     } else if (CheckJNICalls) {
6487       call(RuntimeAddress(StubRoutines::x86::verify_mxcsr_entry()));
6488     }
6489   }
6490   if (VM_Version::supports_avx()) {
6491     // Clear upper bits of YMM registers to avoid SSE <-> AVX transition penalty.
6492     vzeroupper();
6493   }
6494 
6495 #ifndef _LP64
6496   // Either restore the x87 floating pointer control word after returning
6497   // from the JNI call or verify that it wasn't changed.
6498   if (CheckJNICalls) {
6499     call(RuntimeAddress(StubRoutines::x86::verify_fpu_cntrl_wrd_entry()));
6500   }
6501 #endif // _LP64
6502 }
6503 
6504 void MacroAssembler::load_mirror(Register mirror, Register method) {
6505   // get mirror
6506   const int mirror_offset = in_bytes(Klass::java_mirror_offset());
6507   movptr(mirror, Address(method, Method::const_offset()));
6508   movptr(mirror, Address(mirror, ConstMethod::constants_offset()));
6509   movptr(mirror, Address(mirror, ConstantPool::pool_holder_offset_in_bytes()));
6510   movptr(mirror, Address(mirror, mirror_offset));
6511 }
6512 
6513 void MacroAssembler::load_klass(Register dst, Register src) {
6514 #ifdef _LP64
6515   if (UseCompressedClassPointers) {
6516     movl(dst, Address(src, oopDesc::klass_offset_in_bytes()));
6517     decode_klass_not_null(dst);
6518   } else
6519 #endif
6520     movptr(dst, Address(src, oopDesc::klass_offset_in_bytes()));
6521 }
6522 
6523 void MacroAssembler::load_prototype_header(Register dst, Register src) {
6524   load_klass(dst, src);
6525   movptr(dst, Address(dst, Klass::prototype_header_offset()));
6526 }
6527 
6528 void MacroAssembler::store_klass(Register dst, Register src) {
6529 #ifdef _LP64
6530   if (UseCompressedClassPointers) {
6531     encode_klass_not_null(src);
6532     movl(Address(dst, oopDesc::klass_offset_in_bytes()), src);
6533   } else
6534 #endif
6535     movptr(Address(dst, oopDesc::klass_offset_in_bytes()), src);
6536 }
6537 
6538 void MacroAssembler::load_heap_oop(Register dst, Address src) {
6539 #ifdef _LP64
6540   // FIXME: Must change all places where we try to load the klass.
6541   if (UseCompressedOops) {
6542     movl(dst, src);
6543     decode_heap_oop(dst);
6544   } else
6545 #endif
6546     movptr(dst, src);
6547 }
6548 
6549 // Doesn't do verfication, generates fixed size code
6550 void MacroAssembler::load_heap_oop_not_null(Register dst, Address src) {
6551 #ifdef _LP64
6552   if (UseCompressedOops) {
6553     movl(dst, src);
6554     decode_heap_oop_not_null(dst);
6555   } else
6556 #endif
6557     movptr(dst, src);
6558 }
6559 
6560 void MacroAssembler::store_heap_oop(Address dst, Register src) {
6561 #ifdef _LP64
6562   if (UseCompressedOops) {
6563     assert(!dst.uses(src), "not enough registers");
6564     encode_heap_oop(src);
6565     movl(dst, src);
6566   } else
6567 #endif
6568     movptr(dst, src);
6569 }
6570 
6571 void MacroAssembler::cmp_heap_oop(Register src1, Address src2, Register tmp) {
6572   assert_different_registers(src1, tmp);
6573 #ifdef _LP64
6574   if (UseCompressedOops) {
6575     bool did_push = false;
6576     if (tmp == noreg) {
6577       tmp = rax;
6578       push(tmp);
6579       did_push = true;
6580       assert(!src2.uses(rsp), "can't push");
6581     }
6582     load_heap_oop(tmp, src2);
6583     cmpptr(src1, tmp);
6584     if (did_push)  pop(tmp);
6585   } else
6586 #endif
6587     cmpptr(src1, src2);
6588 }
6589 
6590 // Used for storing NULLs.
6591 void MacroAssembler::store_heap_oop_null(Address dst) {
6592 #ifdef _LP64
6593   if (UseCompressedOops) {
6594     movl(dst, (int32_t)NULL_WORD);
6595   } else {
6596     movslq(dst, (int32_t)NULL_WORD);
6597   }
6598 #else
6599   movl(dst, (int32_t)NULL_WORD);
6600 #endif
6601 }
6602 
6603 #ifdef _LP64
6604 void MacroAssembler::store_klass_gap(Register dst, Register src) {
6605   if (UseCompressedClassPointers) {
6606     // Store to klass gap in destination
6607     movl(Address(dst, oopDesc::klass_gap_offset_in_bytes()), src);
6608   }
6609 }
6610 
6611 #ifdef ASSERT
6612 void MacroAssembler::verify_heapbase(const char* msg) {
6613   assert (UseCompressedOops, "should be compressed");
6614   assert (Universe::heap() != NULL, "java heap should be initialized");
6615   if (CheckCompressedOops) {
6616     Label ok;
6617     push(rscratch1); // cmpptr trashes rscratch1
6618     cmpptr(r12_heapbase, ExternalAddress((address)Universe::narrow_ptrs_base_addr()));
6619     jcc(Assembler::equal, ok);
6620     STOP(msg);
6621     bind(ok);
6622     pop(rscratch1);
6623   }
6624 }
6625 #endif
6626 
6627 // Algorithm must match oop.inline.hpp encode_heap_oop.
6628 void MacroAssembler::encode_heap_oop(Register r) {
6629 #ifdef ASSERT
6630   verify_heapbase("MacroAssembler::encode_heap_oop: heap base corrupted?");
6631 #endif
6632   verify_oop(r, "broken oop in encode_heap_oop");
6633   if (Universe::narrow_oop_base() == NULL) {
6634     if (Universe::narrow_oop_shift() != 0) {
6635       assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
6636       shrq(r, LogMinObjAlignmentInBytes);
6637     }
6638     return;
6639   }
6640   testq(r, r);
6641   cmovq(Assembler::equal, r, r12_heapbase);
6642   subq(r, r12_heapbase);
6643   shrq(r, LogMinObjAlignmentInBytes);
6644 }
6645 
6646 void MacroAssembler::encode_heap_oop_not_null(Register r) {
6647 #ifdef ASSERT
6648   verify_heapbase("MacroAssembler::encode_heap_oop_not_null: heap base corrupted?");
6649   if (CheckCompressedOops) {
6650     Label ok;
6651     testq(r, r);
6652     jcc(Assembler::notEqual, ok);
6653     STOP("null oop passed to encode_heap_oop_not_null");
6654     bind(ok);
6655   }
6656 #endif
6657   verify_oop(r, "broken oop in encode_heap_oop_not_null");
6658   if (Universe::narrow_oop_base() != NULL) {
6659     subq(r, r12_heapbase);
6660   }
6661   if (Universe::narrow_oop_shift() != 0) {
6662     assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
6663     shrq(r, LogMinObjAlignmentInBytes);
6664   }
6665 }
6666 
6667 void MacroAssembler::encode_heap_oop_not_null(Register dst, Register src) {
6668 #ifdef ASSERT
6669   verify_heapbase("MacroAssembler::encode_heap_oop_not_null2: heap base corrupted?");
6670   if (CheckCompressedOops) {
6671     Label ok;
6672     testq(src, src);
6673     jcc(Assembler::notEqual, ok);
6674     STOP("null oop passed to encode_heap_oop_not_null2");
6675     bind(ok);
6676   }
6677 #endif
6678   verify_oop(src, "broken oop in encode_heap_oop_not_null2");
6679   if (dst != src) {
6680     movq(dst, src);
6681   }
6682   if (Universe::narrow_oop_base() != NULL) {
6683     subq(dst, r12_heapbase);
6684   }
6685   if (Universe::narrow_oop_shift() != 0) {
6686     assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
6687     shrq(dst, LogMinObjAlignmentInBytes);
6688   }
6689 }
6690 
6691 void  MacroAssembler::decode_heap_oop(Register r) {
6692 #ifdef ASSERT
6693   verify_heapbase("MacroAssembler::decode_heap_oop: heap base corrupted?");
6694 #endif
6695   if (Universe::narrow_oop_base() == NULL) {
6696     if (Universe::narrow_oop_shift() != 0) {
6697       assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
6698       shlq(r, LogMinObjAlignmentInBytes);
6699     }
6700   } else {
6701     Label done;
6702     shlq(r, LogMinObjAlignmentInBytes);
6703     jccb(Assembler::equal, done);
6704     addq(r, r12_heapbase);
6705     bind(done);
6706   }
6707   verify_oop(r, "broken oop in decode_heap_oop");
6708 }
6709 
6710 void  MacroAssembler::decode_heap_oop_not_null(Register r) {
6711   // Note: it will change flags
6712   assert (UseCompressedOops, "should only be used for compressed headers");
6713   assert (Universe::heap() != NULL, "java heap should be initialized");
6714   // Cannot assert, unverified entry point counts instructions (see .ad file)
6715   // vtableStubs also counts instructions in pd_code_size_limit.
6716   // Also do not verify_oop as this is called by verify_oop.
6717   if (Universe::narrow_oop_shift() != 0) {
6718     assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
6719     shlq(r, LogMinObjAlignmentInBytes);
6720     if (Universe::narrow_oop_base() != NULL) {
6721       addq(r, r12_heapbase);
6722     }
6723   } else {
6724     assert (Universe::narrow_oop_base() == NULL, "sanity");
6725   }
6726 }
6727 
6728 void  MacroAssembler::decode_heap_oop_not_null(Register dst, Register src) {
6729   // Note: it will change flags
6730   assert (UseCompressedOops, "should only be used for compressed headers");
6731   assert (Universe::heap() != NULL, "java heap should be initialized");
6732   // Cannot assert, unverified entry point counts instructions (see .ad file)
6733   // vtableStubs also counts instructions in pd_code_size_limit.
6734   // Also do not verify_oop as this is called by verify_oop.
6735   if (Universe::narrow_oop_shift() != 0) {
6736     assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
6737     if (LogMinObjAlignmentInBytes == Address::times_8) {
6738       leaq(dst, Address(r12_heapbase, src, Address::times_8, 0));
6739     } else {
6740       if (dst != src) {
6741         movq(dst, src);
6742       }
6743       shlq(dst, LogMinObjAlignmentInBytes);
6744       if (Universe::narrow_oop_base() != NULL) {
6745         addq(dst, r12_heapbase);
6746       }
6747     }
6748   } else {
6749     assert (Universe::narrow_oop_base() == NULL, "sanity");
6750     if (dst != src) {
6751       movq(dst, src);
6752     }
6753   }
6754 }
6755 
6756 void MacroAssembler::encode_klass_not_null(Register r) {
6757   if (Universe::narrow_klass_base() != NULL) {
6758     // Use r12 as a scratch register in which to temporarily load the narrow_klass_base.
6759     assert(r != r12_heapbase, "Encoding a klass in r12");
6760     mov64(r12_heapbase, (int64_t)Universe::narrow_klass_base());
6761     subq(r, r12_heapbase);
6762   }
6763   if (Universe::narrow_klass_shift() != 0) {
6764     assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
6765     shrq(r, LogKlassAlignmentInBytes);
6766   }
6767   if (Universe::narrow_klass_base() != NULL) {
6768     reinit_heapbase();
6769   }
6770 }
6771 
6772 void MacroAssembler::encode_klass_not_null(Register dst, Register src) {
6773   if (dst == src) {
6774     encode_klass_not_null(src);
6775   } else {
6776     if (Universe::narrow_klass_base() != NULL) {
6777       mov64(dst, (int64_t)Universe::narrow_klass_base());
6778       negq(dst);
6779       addq(dst, src);
6780     } else {
6781       movptr(dst, src);
6782     }
6783     if (Universe::narrow_klass_shift() != 0) {
6784       assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
6785       shrq(dst, LogKlassAlignmentInBytes);
6786     }
6787   }
6788 }
6789 
6790 // Function instr_size_for_decode_klass_not_null() counts the instructions
6791 // generated by decode_klass_not_null(register r) and reinit_heapbase(),
6792 // when (Universe::heap() != NULL).  Hence, if the instructions they
6793 // generate change, then this method needs to be updated.
6794 int MacroAssembler::instr_size_for_decode_klass_not_null() {
6795   assert (UseCompressedClassPointers, "only for compressed klass ptrs");
6796   if (Universe::narrow_klass_base() != NULL) {
6797     // mov64 + addq + shlq? + mov64  (for reinit_heapbase()).
6798     return (Universe::narrow_klass_shift() == 0 ? 20 : 24);
6799   } else {
6800     // longest load decode klass function, mov64, leaq
6801     return 16;
6802   }
6803 }
6804 
6805 // !!! If the instructions that get generated here change then function
6806 // instr_size_for_decode_klass_not_null() needs to get updated.
6807 void  MacroAssembler::decode_klass_not_null(Register r) {
6808   // Note: it will change flags
6809   assert (UseCompressedClassPointers, "should only be used for compressed headers");
6810   assert(r != r12_heapbase, "Decoding a klass in r12");
6811   // Cannot assert, unverified entry point counts instructions (see .ad file)
6812   // vtableStubs also counts instructions in pd_code_size_limit.
6813   // Also do not verify_oop as this is called by verify_oop.
6814   if (Universe::narrow_klass_shift() != 0) {
6815     assert(LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
6816     shlq(r, LogKlassAlignmentInBytes);
6817   }
6818   // Use r12 as a scratch register in which to temporarily load the narrow_klass_base.
6819   if (Universe::narrow_klass_base() != NULL) {
6820     mov64(r12_heapbase, (int64_t)Universe::narrow_klass_base());
6821     addq(r, r12_heapbase);
6822     reinit_heapbase();
6823   }
6824 }
6825 
6826 void  MacroAssembler::decode_klass_not_null(Register dst, Register src) {
6827   // Note: it will change flags
6828   assert (UseCompressedClassPointers, "should only be used for compressed headers");
6829   if (dst == src) {
6830     decode_klass_not_null(dst);
6831   } else {
6832     // Cannot assert, unverified entry point counts instructions (see .ad file)
6833     // vtableStubs also counts instructions in pd_code_size_limit.
6834     // Also do not verify_oop as this is called by verify_oop.
6835     mov64(dst, (int64_t)Universe::narrow_klass_base());
6836     if (Universe::narrow_klass_shift() != 0) {
6837       assert(LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
6838       assert(LogKlassAlignmentInBytes == Address::times_8, "klass not aligned on 64bits?");
6839       leaq(dst, Address(dst, src, Address::times_8, 0));
6840     } else {
6841       addq(dst, src);
6842     }
6843   }
6844 }
6845 
6846 void  MacroAssembler::set_narrow_oop(Register dst, jobject obj) {
6847   assert (UseCompressedOops, "should only be used for compressed headers");
6848   assert (Universe::heap() != NULL, "java heap should be initialized");
6849   assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6850   int oop_index = oop_recorder()->find_index(obj);
6851   RelocationHolder rspec = oop_Relocation::spec(oop_index);
6852   mov_narrow_oop(dst, oop_index, rspec);
6853 }
6854 
6855 void  MacroAssembler::set_narrow_oop(Address dst, jobject obj) {
6856   assert (UseCompressedOops, "should only be used for compressed headers");
6857   assert (Universe::heap() != NULL, "java heap should be initialized");
6858   assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6859   int oop_index = oop_recorder()->find_index(obj);
6860   RelocationHolder rspec = oop_Relocation::spec(oop_index);
6861   mov_narrow_oop(dst, oop_index, rspec);
6862 }
6863 
6864 void  MacroAssembler::set_narrow_klass(Register dst, Klass* k) {
6865   assert (UseCompressedClassPointers, "should only be used for compressed headers");
6866   assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6867   int klass_index = oop_recorder()->find_index(k);
6868   RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6869   mov_narrow_oop(dst, Klass::encode_klass(k), rspec);
6870 }
6871 
6872 void  MacroAssembler::set_narrow_klass(Address dst, Klass* k) {
6873   assert (UseCompressedClassPointers, "should only be used for compressed headers");
6874   assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6875   int klass_index = oop_recorder()->find_index(k);
6876   RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6877   mov_narrow_oop(dst, Klass::encode_klass(k), rspec);
6878 }
6879 
6880 void  MacroAssembler::cmp_narrow_oop(Register dst, jobject obj) {
6881   assert (UseCompressedOops, "should only be used for compressed headers");
6882   assert (Universe::heap() != NULL, "java heap should be initialized");
6883   assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6884   int oop_index = oop_recorder()->find_index(obj);
6885   RelocationHolder rspec = oop_Relocation::spec(oop_index);
6886   Assembler::cmp_narrow_oop(dst, oop_index, rspec);
6887 }
6888 
6889 void  MacroAssembler::cmp_narrow_oop(Address dst, jobject obj) {
6890   assert (UseCompressedOops, "should only be used for compressed headers");
6891   assert (Universe::heap() != NULL, "java heap should be initialized");
6892   assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6893   int oop_index = oop_recorder()->find_index(obj);
6894   RelocationHolder rspec = oop_Relocation::spec(oop_index);
6895   Assembler::cmp_narrow_oop(dst, oop_index, rspec);
6896 }
6897 
6898 void  MacroAssembler::cmp_narrow_klass(Register dst, Klass* k) {
6899   assert (UseCompressedClassPointers, "should only be used for compressed headers");
6900   assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6901   int klass_index = oop_recorder()->find_index(k);
6902   RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6903   Assembler::cmp_narrow_oop(dst, Klass::encode_klass(k), rspec);
6904 }
6905 
6906 void  MacroAssembler::cmp_narrow_klass(Address dst, Klass* k) {
6907   assert (UseCompressedClassPointers, "should only be used for compressed headers");
6908   assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6909   int klass_index = oop_recorder()->find_index(k);
6910   RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6911   Assembler::cmp_narrow_oop(dst, Klass::encode_klass(k), rspec);
6912 }
6913 
6914 void MacroAssembler::reinit_heapbase() {
6915   if (UseCompressedOops || UseCompressedClassPointers) {
6916     if (Universe::heap() != NULL) {
6917       if (Universe::narrow_oop_base() == NULL) {
6918         MacroAssembler::xorptr(r12_heapbase, r12_heapbase);
6919       } else {
6920         mov64(r12_heapbase, (int64_t)Universe::narrow_ptrs_base());
6921       }
6922     } else {
6923       movptr(r12_heapbase, ExternalAddress((address)Universe::narrow_ptrs_base_addr()));
6924     }
6925   }
6926 }
6927 
6928 #endif // _LP64
6929 
6930 
6931 // C2 compiled method's prolog code.
6932 void MacroAssembler::verified_entry(int framesize, int stack_bang_size, bool fp_mode_24b) {
6933 
6934   // WARNING: Initial instruction MUST be 5 bytes or longer so that
6935   // NativeJump::patch_verified_entry will be able to patch out the entry
6936   // code safely. The push to verify stack depth is ok at 5 bytes,
6937   // the frame allocation can be either 3 or 6 bytes. So if we don't do
6938   // stack bang then we must use the 6 byte frame allocation even if
6939   // we have no frame. :-(
6940   assert(stack_bang_size >= framesize || stack_bang_size <= 0, "stack bang size incorrect");
6941 
6942   assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
6943   // Remove word for return addr
6944   framesize -= wordSize;
6945   stack_bang_size -= wordSize;
6946 
6947   // Calls to C2R adapters often do not accept exceptional returns.
6948   // We require that their callers must bang for them.  But be careful, because
6949   // some VM calls (such as call site linkage) can use several kilobytes of
6950   // stack.  But the stack safety zone should account for that.
6951   // See bugs 4446381, 4468289, 4497237.
6952   if (stack_bang_size > 0) {
6953     generate_stack_overflow_check(stack_bang_size);
6954 
6955     // We always push rbp, so that on return to interpreter rbp, will be
6956     // restored correctly and we can correct the stack.
6957     push(rbp);
6958     // Save caller's stack pointer into RBP if the frame pointer is preserved.
6959     if (PreserveFramePointer) {
6960       mov(rbp, rsp);
6961     }
6962     // Remove word for ebp
6963     framesize -= wordSize;
6964 
6965     // Create frame
6966     if (framesize) {
6967       subptr(rsp, framesize);
6968     }
6969   } else {
6970     // Create frame (force generation of a 4 byte immediate value)
6971     subptr_imm32(rsp, framesize);
6972 
6973     // Save RBP register now.
6974     framesize -= wordSize;
6975     movptr(Address(rsp, framesize), rbp);
6976     // Save caller's stack pointer into RBP if the frame pointer is preserved.
6977     if (PreserveFramePointer) {
6978       movptr(rbp, rsp);
6979       if (framesize > 0) {
6980         addptr(rbp, framesize);
6981       }
6982     }
6983   }
6984 
6985   if (VerifyStackAtCalls) { // Majik cookie to verify stack depth
6986     framesize -= wordSize;
6987     movptr(Address(rsp, framesize), (int32_t)0xbadb100d);
6988   }
6989 
6990 #ifndef _LP64
6991   // If method sets FPU control word do it now
6992   if (fp_mode_24b) {
6993     fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
6994   }
6995   if (UseSSE >= 2 && VerifyFPU) {
6996     verify_FPU(0, "FPU stack must be clean on entry");
6997   }
6998 #endif
6999 
7000 #ifdef ASSERT
7001   if (VerifyStackAtCalls) {
7002     Label L;
7003     push(rax);
7004     mov(rax, rsp);
7005     andptr(rax, StackAlignmentInBytes-1);
7006     cmpptr(rax, StackAlignmentInBytes-wordSize);
7007     pop(rax);
7008     jcc(Assembler::equal, L);
7009     STOP("Stack is not properly aligned!");
7010     bind(L);
7011   }
7012 #endif
7013 
7014 }
7015 
7016 void MacroAssembler::clear_mem(Register base, Register cnt, Register tmp, bool is_large) {
7017   // cnt - number of qwords (8-byte words).
7018   // base - start address, qword aligned.
7019   // is_large - if optimizers know cnt is larger than InitArrayShortSize
7020   assert(base==rdi, "base register must be edi for rep stos");
7021   assert(tmp==rax,   "tmp register must be eax for rep stos");
7022   assert(cnt==rcx,   "cnt register must be ecx for rep stos");
7023   assert(InitArrayShortSize % BytesPerLong == 0,
7024     "InitArrayShortSize should be the multiple of BytesPerLong");
7025 
7026   Label DONE;
7027 
7028   xorptr(tmp, tmp);
7029 
7030   if (!is_large) {
7031     Label LOOP, LONG;
7032     cmpptr(cnt, InitArrayShortSize/BytesPerLong);
7033     jccb(Assembler::greater, LONG);
7034 
7035     NOT_LP64(shlptr(cnt, 1);) // convert to number of 32-bit words for 32-bit VM
7036 
7037     decrement(cnt);
7038     jccb(Assembler::negative, DONE); // Zero length
7039 
7040     // Use individual pointer-sized stores for small counts:
7041     BIND(LOOP);
7042     movptr(Address(base, cnt, Address::times_ptr), tmp);
7043     decrement(cnt);
7044     jccb(Assembler::greaterEqual, LOOP);
7045     jmpb(DONE);
7046 
7047     BIND(LONG);
7048   }
7049 
7050   // Use longer rep-prefixed ops for non-small counts:
7051   if (UseFastStosb) {
7052     shlptr(cnt, 3); // convert to number of bytes
7053     rep_stosb();
7054   } else {
7055     NOT_LP64(shlptr(cnt, 1);) // convert to number of 32-bit words for 32-bit VM
7056     rep_stos();
7057   }
7058 
7059   BIND(DONE);
7060 }
7061 
7062 #ifdef COMPILER2
7063 
7064 // IndexOf for constant substrings with size >= 8 chars
7065 // which don't need to be loaded through stack.
7066 void MacroAssembler::string_indexofC8(Register str1, Register str2,
7067                                       Register cnt1, Register cnt2,
7068                                       int int_cnt2,  Register result,
7069                                       XMMRegister vec, Register tmp,
7070                                       int ae) {
7071   ShortBranchVerifier sbv(this);
7072   assert(UseSSE42Intrinsics, "SSE4.2 intrinsics are required");
7073   assert(ae != StrIntrinsicNode::LU, "Invalid encoding");
7074 
7075   // This method uses the pcmpestri instruction with bound registers
7076   //   inputs:
7077   //     xmm - substring
7078   //     rax - substring length (elements count)
7079   //     mem - scanned string
7080   //     rdx - string length (elements count)
7081   //     0xd - mode: 1100 (substring search) + 01 (unsigned shorts)
7082   //     0xc - mode: 1100 (substring search) + 00 (unsigned bytes)
7083   //   outputs:
7084   //     rcx - matched index in string
7085   assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri");
7086   int mode   = (ae == StrIntrinsicNode::LL) ? 0x0c : 0x0d; // bytes or shorts
7087   int stride = (ae == StrIntrinsicNode::LL) ? 16 : 8; //UU, UL -> 8
7088   Address::ScaleFactor scale1 = (ae == StrIntrinsicNode::LL) ? Address::times_1 : Address::times_2;
7089   Address::ScaleFactor scale2 = (ae == StrIntrinsicNode::UL) ? Address::times_1 : scale1;
7090 
7091   Label RELOAD_SUBSTR, SCAN_TO_SUBSTR, SCAN_SUBSTR,
7092         RET_FOUND, RET_NOT_FOUND, EXIT, FOUND_SUBSTR,
7093         MATCH_SUBSTR_HEAD, RELOAD_STR, FOUND_CANDIDATE;
7094 
7095   // Note, inline_string_indexOf() generates checks:
7096   // if (substr.count > string.count) return -1;
7097   // if (substr.count == 0) return 0;
7098   assert(int_cnt2 >= stride, "this code is used only for cnt2 >= 8 chars");
7099 
7100   // Load substring.
7101   if (ae == StrIntrinsicNode::UL) {
7102     pmovzxbw(vec, Address(str2, 0));
7103   } else {
7104     movdqu(vec, Address(str2, 0));
7105   }
7106   movl(cnt2, int_cnt2);
7107   movptr(result, str1); // string addr
7108 
7109   if (int_cnt2 > stride) {
7110     jmpb(SCAN_TO_SUBSTR);
7111 
7112     // Reload substr for rescan, this code
7113     // is executed only for large substrings (> 8 chars)
7114     bind(RELOAD_SUBSTR);
7115     if (ae == StrIntrinsicNode::UL) {
7116       pmovzxbw(vec, Address(str2, 0));
7117     } else {
7118       movdqu(vec, Address(str2, 0));
7119     }
7120     negptr(cnt2); // Jumped here with negative cnt2, convert to positive
7121 
7122     bind(RELOAD_STR);
7123     // We came here after the beginning of the substring was
7124     // matched but the rest of it was not so we need to search
7125     // again. Start from the next element after the previous match.
7126 
7127     // cnt2 is number of substring reminding elements and
7128     // cnt1 is number of string reminding elements when cmp failed.
7129     // Restored cnt1 = cnt1 - cnt2 + int_cnt2
7130     subl(cnt1, cnt2);
7131     addl(cnt1, int_cnt2);
7132     movl(cnt2, int_cnt2); // Now restore cnt2
7133 
7134     decrementl(cnt1);     // Shift to next element
7135     cmpl(cnt1, cnt2);
7136     jcc(Assembler::negative, RET_NOT_FOUND);  // Left less then substring
7137 
7138     addptr(result, (1<<scale1));
7139 
7140   } // (int_cnt2 > 8)
7141 
7142   // Scan string for start of substr in 16-byte vectors
7143   bind(SCAN_TO_SUBSTR);
7144   pcmpestri(vec, Address(result, 0), mode);
7145   jccb(Assembler::below, FOUND_CANDIDATE);   // CF == 1
7146   subl(cnt1, stride);
7147   jccb(Assembler::lessEqual, RET_NOT_FOUND); // Scanned full string
7148   cmpl(cnt1, cnt2);
7149   jccb(Assembler::negative, RET_NOT_FOUND);  // Left less then substring
7150   addptr(result, 16);
7151   jmpb(SCAN_TO_SUBSTR);
7152 
7153   // Found a potential substr
7154   bind(FOUND_CANDIDATE);
7155   // Matched whole vector if first element matched (tmp(rcx) == 0).
7156   if (int_cnt2 == stride) {
7157     jccb(Assembler::overflow, RET_FOUND);    // OF == 1
7158   } else { // int_cnt2 > 8
7159     jccb(Assembler::overflow, FOUND_SUBSTR);
7160   }
7161   // After pcmpestri tmp(rcx) contains matched element index
7162   // Compute start addr of substr
7163   lea(result, Address(result, tmp, scale1));
7164 
7165   // Make sure string is still long enough
7166   subl(cnt1, tmp);
7167   cmpl(cnt1, cnt2);
7168   if (int_cnt2 == stride) {
7169     jccb(Assembler::greaterEqual, SCAN_TO_SUBSTR);
7170   } else { // int_cnt2 > 8
7171     jccb(Assembler::greaterEqual, MATCH_SUBSTR_HEAD);
7172   }
7173   // Left less then substring.
7174 
7175   bind(RET_NOT_FOUND);
7176   movl(result, -1);
7177   jmp(EXIT);
7178 
7179   if (int_cnt2 > stride) {
7180     // This code is optimized for the case when whole substring
7181     // is matched if its head is matched.
7182     bind(MATCH_SUBSTR_HEAD);
7183     pcmpestri(vec, Address(result, 0), mode);
7184     // Reload only string if does not match
7185     jcc(Assembler::noOverflow, RELOAD_STR); // OF == 0
7186 
7187     Label CONT_SCAN_SUBSTR;
7188     // Compare the rest of substring (> 8 chars).
7189     bind(FOUND_SUBSTR);
7190     // First 8 chars are already matched.
7191     negptr(cnt2);
7192     addptr(cnt2, stride);
7193 
7194     bind(SCAN_SUBSTR);
7195     subl(cnt1, stride);
7196     cmpl(cnt2, -stride); // Do not read beyond substring
7197     jccb(Assembler::lessEqual, CONT_SCAN_SUBSTR);
7198     // Back-up strings to avoid reading beyond substring:
7199     // cnt1 = cnt1 - cnt2 + 8
7200     addl(cnt1, cnt2); // cnt2 is negative
7201     addl(cnt1, stride);
7202     movl(cnt2, stride); negptr(cnt2);
7203     bind(CONT_SCAN_SUBSTR);
7204     if (int_cnt2 < (int)G) {
7205       int tail_off1 = int_cnt2<<scale1;
7206       int tail_off2 = int_cnt2<<scale2;
7207       if (ae == StrIntrinsicNode::UL) {
7208         pmovzxbw(vec, Address(str2, cnt2, scale2, tail_off2));
7209       } else {
7210         movdqu(vec, Address(str2, cnt2, scale2, tail_off2));
7211       }
7212       pcmpestri(vec, Address(result, cnt2, scale1, tail_off1), mode);
7213     } else {
7214       // calculate index in register to avoid integer overflow (int_cnt2*2)
7215       movl(tmp, int_cnt2);
7216       addptr(tmp, cnt2);
7217       if (ae == StrIntrinsicNode::UL) {
7218         pmovzxbw(vec, Address(str2, tmp, scale2, 0));
7219       } else {
7220         movdqu(vec, Address(str2, tmp, scale2, 0));
7221       }
7222       pcmpestri(vec, Address(result, tmp, scale1, 0), mode);
7223     }
7224     // Need to reload strings pointers if not matched whole vector
7225     jcc(Assembler::noOverflow, RELOAD_SUBSTR); // OF == 0
7226     addptr(cnt2, stride);
7227     jcc(Assembler::negative, SCAN_SUBSTR);
7228     // Fall through if found full substring
7229 
7230   } // (int_cnt2 > 8)
7231 
7232   bind(RET_FOUND);
7233   // Found result if we matched full small substring.
7234   // Compute substr offset
7235   subptr(result, str1);
7236   if (ae == StrIntrinsicNode::UU || ae == StrIntrinsicNode::UL) {
7237     shrl(result, 1); // index
7238   }
7239   bind(EXIT);
7240 
7241 } // string_indexofC8
7242 
7243 // Small strings are loaded through stack if they cross page boundary.
7244 void MacroAssembler::string_indexof(Register str1, Register str2,
7245                                     Register cnt1, Register cnt2,
7246                                     int int_cnt2,  Register result,
7247                                     XMMRegister vec, Register tmp,
7248                                     int ae) {
7249   ShortBranchVerifier sbv(this);
7250   assert(UseSSE42Intrinsics, "SSE4.2 intrinsics are required");
7251   assert(ae != StrIntrinsicNode::LU, "Invalid encoding");
7252 
7253   //
7254   // int_cnt2 is length of small (< 8 chars) constant substring
7255   // or (-1) for non constant substring in which case its length
7256   // is in cnt2 register.
7257   //
7258   // Note, inline_string_indexOf() generates checks:
7259   // if (substr.count > string.count) return -1;
7260   // if (substr.count == 0) return 0;
7261   //
7262   int stride = (ae == StrIntrinsicNode::LL) ? 16 : 8; //UU, UL -> 8
7263   assert(int_cnt2 == -1 || (0 < int_cnt2 && int_cnt2 < stride), "should be != 0");
7264   // This method uses the pcmpestri instruction with bound registers
7265   //   inputs:
7266   //     xmm - substring
7267   //     rax - substring length (elements count)
7268   //     mem - scanned string
7269   //     rdx - string length (elements count)
7270   //     0xd - mode: 1100 (substring search) + 01 (unsigned shorts)
7271   //     0xc - mode: 1100 (substring search) + 00 (unsigned bytes)
7272   //   outputs:
7273   //     rcx - matched index in string
7274   assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri");
7275   int mode = (ae == StrIntrinsicNode::LL) ? 0x0c : 0x0d; // bytes or shorts
7276   Address::ScaleFactor scale1 = (ae == StrIntrinsicNode::LL) ? Address::times_1 : Address::times_2;
7277   Address::ScaleFactor scale2 = (ae == StrIntrinsicNode::UL) ? Address::times_1 : scale1;
7278 
7279   Label RELOAD_SUBSTR, SCAN_TO_SUBSTR, SCAN_SUBSTR, ADJUST_STR,
7280         RET_FOUND, RET_NOT_FOUND, CLEANUP, FOUND_SUBSTR,
7281         FOUND_CANDIDATE;
7282 
7283   { //========================================================
7284     // We don't know where these strings are located
7285     // and we can't read beyond them. Load them through stack.
7286     Label BIG_STRINGS, CHECK_STR, COPY_SUBSTR, COPY_STR;
7287 
7288     movptr(tmp, rsp); // save old SP
7289 
7290     if (int_cnt2 > 0) {     // small (< 8 chars) constant substring
7291       if (int_cnt2 == (1>>scale2)) { // One byte
7292         assert((ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UL), "Only possible for latin1 encoding");
7293         load_unsigned_byte(result, Address(str2, 0));
7294         movdl(vec, result); // move 32 bits
7295       } else if (ae == StrIntrinsicNode::LL && int_cnt2 == 3) {  // Three bytes
7296         // Not enough header space in 32-bit VM: 12+3 = 15.
7297         movl(result, Address(str2, -1));
7298         shrl(result, 8);
7299         movdl(vec, result); // move 32 bits
7300       } else if (ae != StrIntrinsicNode::UL && int_cnt2 == (2>>scale2)) {  // One char
7301         load_unsigned_short(result, Address(str2, 0));
7302         movdl(vec, result); // move 32 bits
7303       } else if (ae != StrIntrinsicNode::UL && int_cnt2 == (4>>scale2)) { // Two chars
7304         movdl(vec, Address(str2, 0)); // move 32 bits
7305       } else if (ae != StrIntrinsicNode::UL && int_cnt2 == (8>>scale2)) { // Four chars
7306         movq(vec, Address(str2, 0));  // move 64 bits
7307       } else { // cnt2 = { 3, 5, 6, 7 } || (ae == StrIntrinsicNode::UL && cnt2 ={2, ..., 7})
7308         // Array header size is 12 bytes in 32-bit VM
7309         // + 6 bytes for 3 chars == 18 bytes,
7310         // enough space to load vec and shift.
7311         assert(HeapWordSize*TypeArrayKlass::header_size() >= 12,"sanity");
7312         if (ae == StrIntrinsicNode::UL) {
7313           int tail_off = int_cnt2-8;
7314           pmovzxbw(vec, Address(str2, tail_off));
7315           psrldq(vec, -2*tail_off);
7316         }
7317         else {
7318           int tail_off = int_cnt2*(1<<scale2);
7319           movdqu(vec, Address(str2, tail_off-16));
7320           psrldq(vec, 16-tail_off);
7321         }
7322       }
7323     } else { // not constant substring
7324       cmpl(cnt2, stride);
7325       jccb(Assembler::aboveEqual, BIG_STRINGS); // Both strings are big enough
7326 
7327       // We can read beyond string if srt+16 does not cross page boundary
7328       // since heaps are aligned and mapped by pages.
7329       assert(os::vm_page_size() < (int)G, "default page should be small");
7330       movl(result, str2); // We need only low 32 bits
7331       andl(result, (os::vm_page_size()-1));
7332       cmpl(result, (os::vm_page_size()-16));
7333       jccb(Assembler::belowEqual, CHECK_STR);
7334 
7335       // Move small strings to stack to allow load 16 bytes into vec.
7336       subptr(rsp, 16);
7337       int stk_offset = wordSize-(1<<scale2);
7338       push(cnt2);
7339 
7340       bind(COPY_SUBSTR);
7341       if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UL) {
7342         load_unsigned_byte(result, Address(str2, cnt2, scale2, -1));
7343         movb(Address(rsp, cnt2, scale2, stk_offset), result);
7344       } else if (ae == StrIntrinsicNode::UU) {
7345         load_unsigned_short(result, Address(str2, cnt2, scale2, -2));
7346         movw(Address(rsp, cnt2, scale2, stk_offset), result);
7347       }
7348       decrement(cnt2);
7349       jccb(Assembler::notZero, COPY_SUBSTR);
7350 
7351       pop(cnt2);
7352       movptr(str2, rsp);  // New substring address
7353     } // non constant
7354 
7355     bind(CHECK_STR);
7356     cmpl(cnt1, stride);
7357     jccb(Assembler::aboveEqual, BIG_STRINGS);
7358 
7359     // Check cross page boundary.
7360     movl(result, str1); // We need only low 32 bits
7361     andl(result, (os::vm_page_size()-1));
7362     cmpl(result, (os::vm_page_size()-16));
7363     jccb(Assembler::belowEqual, BIG_STRINGS);
7364 
7365     subptr(rsp, 16);
7366     int stk_offset = -(1<<scale1);
7367     if (int_cnt2 < 0) { // not constant
7368       push(cnt2);
7369       stk_offset += wordSize;
7370     }
7371     movl(cnt2, cnt1);
7372 
7373     bind(COPY_STR);
7374     if (ae == StrIntrinsicNode::LL) {
7375       load_unsigned_byte(result, Address(str1, cnt2, scale1, -1));
7376       movb(Address(rsp, cnt2, scale1, stk_offset), result);
7377     } else {
7378       load_unsigned_short(result, Address(str1, cnt2, scale1, -2));
7379       movw(Address(rsp, cnt2, scale1, stk_offset), result);
7380     }
7381     decrement(cnt2);
7382     jccb(Assembler::notZero, COPY_STR);
7383 
7384     if (int_cnt2 < 0) { // not constant
7385       pop(cnt2);
7386     }
7387     movptr(str1, rsp);  // New string address
7388 
7389     bind(BIG_STRINGS);
7390     // Load substring.
7391     if (int_cnt2 < 0) { // -1
7392       if (ae == StrIntrinsicNode::UL) {
7393         pmovzxbw(vec, Address(str2, 0));
7394       } else {
7395         movdqu(vec, Address(str2, 0));
7396       }
7397       push(cnt2);       // substr count
7398       push(str2);       // substr addr
7399       push(str1);       // string addr
7400     } else {
7401       // Small (< 8 chars) constant substrings are loaded already.
7402       movl(cnt2, int_cnt2);
7403     }
7404     push(tmp);  // original SP
7405 
7406   } // Finished loading
7407 
7408   //========================================================
7409   // Start search
7410   //
7411 
7412   movptr(result, str1); // string addr
7413 
7414   if (int_cnt2  < 0) {  // Only for non constant substring
7415     jmpb(SCAN_TO_SUBSTR);
7416 
7417     // SP saved at sp+0
7418     // String saved at sp+1*wordSize
7419     // Substr saved at sp+2*wordSize
7420     // Substr count saved at sp+3*wordSize
7421 
7422     // Reload substr for rescan, this code
7423     // is executed only for large substrings (> 8 chars)
7424     bind(RELOAD_SUBSTR);
7425     movptr(str2, Address(rsp, 2*wordSize));
7426     movl(cnt2, Address(rsp, 3*wordSize));
7427     if (ae == StrIntrinsicNode::UL) {
7428       pmovzxbw(vec, Address(str2, 0));
7429     } else {
7430       movdqu(vec, Address(str2, 0));
7431     }
7432     // We came here after the beginning of the substring was
7433     // matched but the rest of it was not so we need to search
7434     // again. Start from the next element after the previous match.
7435     subptr(str1, result); // Restore counter
7436     if (ae == StrIntrinsicNode::UU || ae == StrIntrinsicNode::UL) {
7437       shrl(str1, 1);
7438     }
7439     addl(cnt1, str1);
7440     decrementl(cnt1);   // Shift to next element
7441     cmpl(cnt1, cnt2);
7442     jcc(Assembler::negative, RET_NOT_FOUND);  // Left less then substring
7443 
7444     addptr(result, (1<<scale1));
7445   } // non constant
7446 
7447   // Scan string for start of substr in 16-byte vectors
7448   bind(SCAN_TO_SUBSTR);
7449   assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri");
7450   pcmpestri(vec, Address(result, 0), mode);
7451   jccb(Assembler::below, FOUND_CANDIDATE);   // CF == 1
7452   subl(cnt1, stride);
7453   jccb(Assembler::lessEqual, RET_NOT_FOUND); // Scanned full string
7454   cmpl(cnt1, cnt2);
7455   jccb(Assembler::negative, RET_NOT_FOUND);  // Left less then substring
7456   addptr(result, 16);
7457 
7458   bind(ADJUST_STR);
7459   cmpl(cnt1, stride); // Do not read beyond string
7460   jccb(Assembler::greaterEqual, SCAN_TO_SUBSTR);
7461   // Back-up string to avoid reading beyond string.
7462   lea(result, Address(result, cnt1, scale1, -16));
7463   movl(cnt1, stride);
7464   jmpb(SCAN_TO_SUBSTR);
7465 
7466   // Found a potential substr
7467   bind(FOUND_CANDIDATE);
7468   // After pcmpestri tmp(rcx) contains matched element index
7469 
7470   // Make sure string is still long enough
7471   subl(cnt1, tmp);
7472   cmpl(cnt1, cnt2);
7473   jccb(Assembler::greaterEqual, FOUND_SUBSTR);
7474   // Left less then substring.
7475 
7476   bind(RET_NOT_FOUND);
7477   movl(result, -1);
7478   jmpb(CLEANUP);
7479 
7480   bind(FOUND_SUBSTR);
7481   // Compute start addr of substr
7482   lea(result, Address(result, tmp, scale1));
7483   if (int_cnt2 > 0) { // Constant substring
7484     // Repeat search for small substring (< 8 chars)
7485     // from new point without reloading substring.
7486     // Have to check that we don't read beyond string.
7487     cmpl(tmp, stride-int_cnt2);
7488     jccb(Assembler::greater, ADJUST_STR);
7489     // Fall through if matched whole substring.
7490   } else { // non constant
7491     assert(int_cnt2 == -1, "should be != 0");
7492 
7493     addl(tmp, cnt2);
7494     // Found result if we matched whole substring.
7495     cmpl(tmp, stride);
7496     jccb(Assembler::lessEqual, RET_FOUND);
7497 
7498     // Repeat search for small substring (<= 8 chars)
7499     // from new point 'str1' without reloading substring.
7500     cmpl(cnt2, stride);
7501     // Have to check that we don't read beyond string.
7502     jccb(Assembler::lessEqual, ADJUST_STR);
7503 
7504     Label CHECK_NEXT, CONT_SCAN_SUBSTR, RET_FOUND_LONG;
7505     // Compare the rest of substring (> 8 chars).
7506     movptr(str1, result);
7507 
7508     cmpl(tmp, cnt2);
7509     // First 8 chars are already matched.
7510     jccb(Assembler::equal, CHECK_NEXT);
7511 
7512     bind(SCAN_SUBSTR);
7513     pcmpestri(vec, Address(str1, 0), mode);
7514     // Need to reload strings pointers if not matched whole vector
7515     jcc(Assembler::noOverflow, RELOAD_SUBSTR); // OF == 0
7516 
7517     bind(CHECK_NEXT);
7518     subl(cnt2, stride);
7519     jccb(Assembler::lessEqual, RET_FOUND_LONG); // Found full substring
7520     addptr(str1, 16);
7521     if (ae == StrIntrinsicNode::UL) {
7522       addptr(str2, 8);
7523     } else {
7524       addptr(str2, 16);
7525     }
7526     subl(cnt1, stride);
7527     cmpl(cnt2, stride); // Do not read beyond substring
7528     jccb(Assembler::greaterEqual, CONT_SCAN_SUBSTR);
7529     // Back-up strings to avoid reading beyond substring.
7530 
7531     if (ae == StrIntrinsicNode::UL) {
7532       lea(str2, Address(str2, cnt2, scale2, -8));
7533       lea(str1, Address(str1, cnt2, scale1, -16));
7534     } else {
7535       lea(str2, Address(str2, cnt2, scale2, -16));
7536       lea(str1, Address(str1, cnt2, scale1, -16));
7537     }
7538     subl(cnt1, cnt2);
7539     movl(cnt2, stride);
7540     addl(cnt1, stride);
7541     bind(CONT_SCAN_SUBSTR);
7542     if (ae == StrIntrinsicNode::UL) {
7543       pmovzxbw(vec, Address(str2, 0));
7544     } else {
7545       movdqu(vec, Address(str2, 0));
7546     }
7547     jmp(SCAN_SUBSTR);
7548 
7549     bind(RET_FOUND_LONG);
7550     movptr(str1, Address(rsp, wordSize));
7551   } // non constant
7552 
7553   bind(RET_FOUND);
7554   // Compute substr offset
7555   subptr(result, str1);
7556   if (ae == StrIntrinsicNode::UU || ae == StrIntrinsicNode::UL) {
7557     shrl(result, 1); // index
7558   }
7559   bind(CLEANUP);
7560   pop(rsp); // restore SP
7561 
7562 } // string_indexof
7563 
7564 void MacroAssembler::string_indexof_char(Register str1, Register cnt1, Register ch, Register result,
7565                                          XMMRegister vec1, XMMRegister vec2, XMMRegister vec3, Register tmp) {
7566   ShortBranchVerifier sbv(this);
7567   assert(UseSSE42Intrinsics, "SSE4.2 intrinsics are required");
7568 
7569   int stride = 8;
7570 
7571   Label FOUND_CHAR, SCAN_TO_CHAR, SCAN_TO_CHAR_LOOP,
7572         SCAN_TO_8_CHAR, SCAN_TO_8_CHAR_LOOP, SCAN_TO_16_CHAR_LOOP,
7573         RET_NOT_FOUND, SCAN_TO_8_CHAR_INIT,
7574         FOUND_SEQ_CHAR, DONE_LABEL;
7575 
7576   movptr(result, str1);
7577   if (UseAVX >= 2) {
7578     cmpl(cnt1, stride);
7579     jcc(Assembler::less, SCAN_TO_CHAR_LOOP);
7580     cmpl(cnt1, 2*stride);
7581     jcc(Assembler::less, SCAN_TO_8_CHAR_INIT);
7582     movdl(vec1, ch);
7583     vpbroadcastw(vec1, vec1);
7584     vpxor(vec2, vec2);
7585     movl(tmp, cnt1);
7586     andl(tmp, 0xFFFFFFF0);  //vector count (in chars)
7587     andl(cnt1,0x0000000F);  //tail count (in chars)
7588 
7589     bind(SCAN_TO_16_CHAR_LOOP);
7590     vmovdqu(vec3, Address(result, 0));
7591     vpcmpeqw(vec3, vec3, vec1, 1);
7592     vptest(vec2, vec3);
7593     jcc(Assembler::carryClear, FOUND_CHAR);
7594     addptr(result, 32);
7595     subl(tmp, 2*stride);
7596     jccb(Assembler::notZero, SCAN_TO_16_CHAR_LOOP);
7597     jmp(SCAN_TO_8_CHAR);
7598     bind(SCAN_TO_8_CHAR_INIT);
7599     movdl(vec1, ch);
7600     pshuflw(vec1, vec1, 0x00);
7601     pshufd(vec1, vec1, 0);
7602     pxor(vec2, vec2);
7603   }
7604   bind(SCAN_TO_8_CHAR);
7605   cmpl(cnt1, stride);
7606   if (UseAVX >= 2) {
7607     jcc(Assembler::less, SCAN_TO_CHAR);
7608   } else {
7609     jcc(Assembler::less, SCAN_TO_CHAR_LOOP);
7610     movdl(vec1, ch);
7611     pshuflw(vec1, vec1, 0x00);
7612     pshufd(vec1, vec1, 0);
7613     pxor(vec2, vec2);
7614   }
7615   movl(tmp, cnt1);
7616   andl(tmp, 0xFFFFFFF8);  //vector count (in chars)
7617   andl(cnt1,0x00000007);  //tail count (in chars)
7618 
7619   bind(SCAN_TO_8_CHAR_LOOP);
7620   movdqu(vec3, Address(result, 0));
7621   pcmpeqw(vec3, vec1);
7622   ptest(vec2, vec3);
7623   jcc(Assembler::carryClear, FOUND_CHAR);
7624   addptr(result, 16);
7625   subl(tmp, stride);
7626   jccb(Assembler::notZero, SCAN_TO_8_CHAR_LOOP);
7627   bind(SCAN_TO_CHAR);
7628   testl(cnt1, cnt1);
7629   jcc(Assembler::zero, RET_NOT_FOUND);
7630   bind(SCAN_TO_CHAR_LOOP);
7631   load_unsigned_short(tmp, Address(result, 0));
7632   cmpl(ch, tmp);
7633   jccb(Assembler::equal, FOUND_SEQ_CHAR);
7634   addptr(result, 2);
7635   subl(cnt1, 1);
7636   jccb(Assembler::zero, RET_NOT_FOUND);
7637   jmp(SCAN_TO_CHAR_LOOP);
7638 
7639   bind(RET_NOT_FOUND);
7640   movl(result, -1);
7641   jmpb(DONE_LABEL);
7642 
7643   bind(FOUND_CHAR);
7644   if (UseAVX >= 2) {
7645     vpmovmskb(tmp, vec3);
7646   } else {
7647     pmovmskb(tmp, vec3);
7648   }
7649   bsfl(ch, tmp);
7650   addl(result, ch);
7651 
7652   bind(FOUND_SEQ_CHAR);
7653   subptr(result, str1);
7654   shrl(result, 1);
7655 
7656   bind(DONE_LABEL);
7657 } // string_indexof_char
7658 
7659 // helper function for string_compare
7660 void MacroAssembler::load_next_elements(Register elem1, Register elem2, Register str1, Register str2,
7661                                         Address::ScaleFactor scale, Address::ScaleFactor scale1,
7662                                         Address::ScaleFactor scale2, Register index, int ae) {
7663   if (ae == StrIntrinsicNode::LL) {
7664     load_unsigned_byte(elem1, Address(str1, index, scale, 0));
7665     load_unsigned_byte(elem2, Address(str2, index, scale, 0));
7666   } else if (ae == StrIntrinsicNode::UU) {
7667     load_unsigned_short(elem1, Address(str1, index, scale, 0));
7668     load_unsigned_short(elem2, Address(str2, index, scale, 0));
7669   } else {
7670     load_unsigned_byte(elem1, Address(str1, index, scale1, 0));
7671     load_unsigned_short(elem2, Address(str2, index, scale2, 0));
7672   }
7673 }
7674 
7675 // Compare strings, used for char[] and byte[].
7676 void MacroAssembler::string_compare(Register str1, Register str2,
7677                                     Register cnt1, Register cnt2, Register result,
7678                                     XMMRegister vec1, int ae) {
7679   ShortBranchVerifier sbv(this);
7680   Label LENGTH_DIFF_LABEL, POP_LABEL, DONE_LABEL, WHILE_HEAD_LABEL;
7681   Label COMPARE_WIDE_VECTORS_LOOP_FAILED;  // used only _LP64 && AVX3
7682   int stride, stride2, adr_stride, adr_stride1, adr_stride2;
7683   int stride2x2 = 0x40;
7684   Address::ScaleFactor scale = Address::no_scale;
7685   Address::ScaleFactor scale1 = Address::no_scale;
7686   Address::ScaleFactor scale2 = Address::no_scale;
7687 
7688   if (ae != StrIntrinsicNode::LL) {
7689     stride2x2 = 0x20;
7690   }
7691 
7692   if (ae == StrIntrinsicNode::LU || ae == StrIntrinsicNode::UL) {
7693     shrl(cnt2, 1);
7694   }
7695   // Compute the minimum of the string lengths and the
7696   // difference of the string lengths (stack).
7697   // Do the conditional move stuff
7698   movl(result, cnt1);
7699   subl(cnt1, cnt2);
7700   push(cnt1);
7701   cmov32(Assembler::lessEqual, cnt2, result);    // cnt2 = min(cnt1, cnt2)
7702 
7703   // Is the minimum length zero?
7704   testl(cnt2, cnt2);
7705   jcc(Assembler::zero, LENGTH_DIFF_LABEL);
7706   if (ae == StrIntrinsicNode::LL) {
7707     // Load first bytes
7708     load_unsigned_byte(result, Address(str1, 0));  // result = str1[0]
7709     load_unsigned_byte(cnt1, Address(str2, 0));    // cnt1   = str2[0]
7710   } else if (ae == StrIntrinsicNode::UU) {
7711     // Load first characters
7712     load_unsigned_short(result, Address(str1, 0));
7713     load_unsigned_short(cnt1, Address(str2, 0));
7714   } else {
7715     load_unsigned_byte(result, Address(str1, 0));
7716     load_unsigned_short(cnt1, Address(str2, 0));
7717   }
7718   subl(result, cnt1);
7719   jcc(Assembler::notZero,  POP_LABEL);
7720 
7721   if (ae == StrIntrinsicNode::UU) {
7722     // Divide length by 2 to get number of chars
7723     shrl(cnt2, 1);
7724   }
7725   cmpl(cnt2, 1);
7726   jcc(Assembler::equal, LENGTH_DIFF_LABEL);
7727 
7728   // Check if the strings start at the same location and setup scale and stride
7729   if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7730     cmpptr(str1, str2);
7731     jcc(Assembler::equal, LENGTH_DIFF_LABEL);
7732     if (ae == StrIntrinsicNode::LL) {
7733       scale = Address::times_1;
7734       stride = 16;
7735     } else {
7736       scale = Address::times_2;
7737       stride = 8;
7738     }
7739   } else {
7740     scale1 = Address::times_1;
7741     scale2 = Address::times_2;
7742     // scale not used
7743     stride = 8;
7744   }
7745 
7746   if (UseAVX >= 2 && UseSSE42Intrinsics) {
7747     Label COMPARE_WIDE_VECTORS, VECTOR_NOT_EQUAL, COMPARE_WIDE_TAIL, COMPARE_SMALL_STR;
7748     Label COMPARE_WIDE_VECTORS_LOOP, COMPARE_16_CHARS, COMPARE_INDEX_CHAR;
7749     Label COMPARE_WIDE_VECTORS_LOOP_AVX2;
7750     Label COMPARE_TAIL_LONG;
7751     Label COMPARE_WIDE_VECTORS_LOOP_AVX3;  // used only _LP64 && AVX3
7752 
7753     int pcmpmask = 0x19;
7754     if (ae == StrIntrinsicNode::LL) {
7755       pcmpmask &= ~0x01;
7756     }
7757 
7758     // Setup to compare 16-chars (32-bytes) vectors,
7759     // start from first character again because it has aligned address.
7760     if (ae == StrIntrinsicNode::LL) {
7761       stride2 = 32;
7762     } else {
7763       stride2 = 16;
7764     }
7765     if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7766       adr_stride = stride << scale;
7767     } else {
7768       adr_stride1 = 8;  //stride << scale1;
7769       adr_stride2 = 16; //stride << scale2;
7770     }
7771 
7772     assert(result == rax && cnt2 == rdx && cnt1 == rcx, "pcmpestri");
7773     // rax and rdx are used by pcmpestri as elements counters
7774     movl(result, cnt2);
7775     andl(cnt2, ~(stride2-1));   // cnt2 holds the vector count
7776     jcc(Assembler::zero, COMPARE_TAIL_LONG);
7777 
7778     // fast path : compare first 2 8-char vectors.
7779     bind(COMPARE_16_CHARS);
7780     if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7781       movdqu(vec1, Address(str1, 0));
7782     } else {
7783       pmovzxbw(vec1, Address(str1, 0));
7784     }
7785     pcmpestri(vec1, Address(str2, 0), pcmpmask);
7786     jccb(Assembler::below, COMPARE_INDEX_CHAR);
7787 
7788     if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7789       movdqu(vec1, Address(str1, adr_stride));
7790       pcmpestri(vec1, Address(str2, adr_stride), pcmpmask);
7791     } else {
7792       pmovzxbw(vec1, Address(str1, adr_stride1));
7793       pcmpestri(vec1, Address(str2, adr_stride2), pcmpmask);
7794     }
7795     jccb(Assembler::aboveEqual, COMPARE_WIDE_VECTORS);
7796     addl(cnt1, stride);
7797 
7798     // Compare the characters at index in cnt1
7799     bind(COMPARE_INDEX_CHAR); // cnt1 has the offset of the mismatching character
7800     load_next_elements(result, cnt2, str1, str2, scale, scale1, scale2, cnt1, ae);
7801     subl(result, cnt2);
7802     jmp(POP_LABEL);
7803 
7804     // Setup the registers to start vector comparison loop
7805     bind(COMPARE_WIDE_VECTORS);
7806     if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7807       lea(str1, Address(str1, result, scale));
7808       lea(str2, Address(str2, result, scale));
7809     } else {
7810       lea(str1, Address(str1, result, scale1));
7811       lea(str2, Address(str2, result, scale2));
7812     }
7813     subl(result, stride2);
7814     subl(cnt2, stride2);
7815     jcc(Assembler::zero, COMPARE_WIDE_TAIL);
7816     negptr(result);
7817 
7818     //  In a loop, compare 16-chars (32-bytes) at once using (vpxor+vptest)
7819     bind(COMPARE_WIDE_VECTORS_LOOP);
7820 
7821 #ifdef _LP64
7822     if (VM_Version::supports_avx512vlbw()) { // trying 64 bytes fast loop
7823       cmpl(cnt2, stride2x2);
7824       jccb(Assembler::below, COMPARE_WIDE_VECTORS_LOOP_AVX2);
7825       testl(cnt2, stride2x2-1);   // cnt2 holds the vector count
7826       jccb(Assembler::notZero, COMPARE_WIDE_VECTORS_LOOP_AVX2);   // means we cannot subtract by 0x40
7827 
7828       bind(COMPARE_WIDE_VECTORS_LOOP_AVX3); // the hottest loop
7829       if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7830         evmovdquq(vec1, Address(str1, result, scale), Assembler::AVX_512bit);
7831         evpcmpeqb(k7, vec1, Address(str2, result, scale), Assembler::AVX_512bit); // k7 == 11..11, if operands equal, otherwise k7 has some 0
7832       } else {
7833         vpmovzxbw(vec1, Address(str1, result, scale1), Assembler::AVX_512bit);
7834         evpcmpeqb(k7, vec1, Address(str2, result, scale2), Assembler::AVX_512bit); // k7 == 11..11, if operands equal, otherwise k7 has some 0
7835       }
7836       kortestql(k7, k7);
7837       jcc(Assembler::aboveEqual, COMPARE_WIDE_VECTORS_LOOP_FAILED);     // miscompare
7838       addptr(result, stride2x2);  // update since we already compared at this addr
7839       subl(cnt2, stride2x2);      // and sub the size too
7840       jccb(Assembler::notZero, COMPARE_WIDE_VECTORS_LOOP_AVX3);
7841 
7842       vpxor(vec1, vec1);
7843       jmpb(COMPARE_WIDE_TAIL);
7844     }//if (VM_Version::supports_avx512vlbw())
7845 #endif // _LP64
7846 
7847 
7848     bind(COMPARE_WIDE_VECTORS_LOOP_AVX2);
7849     if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7850       vmovdqu(vec1, Address(str1, result, scale));
7851       vpxor(vec1, Address(str2, result, scale));
7852     } else {
7853       vpmovzxbw(vec1, Address(str1, result, scale1), Assembler::AVX_256bit);
7854       vpxor(vec1, Address(str2, result, scale2));
7855     }
7856     vptest(vec1, vec1);
7857     jcc(Assembler::notZero, VECTOR_NOT_EQUAL);
7858     addptr(result, stride2);
7859     subl(cnt2, stride2);
7860     jcc(Assembler::notZero, COMPARE_WIDE_VECTORS_LOOP);
7861     // clean upper bits of YMM registers
7862     vpxor(vec1, vec1);
7863 
7864     // compare wide vectors tail
7865     bind(COMPARE_WIDE_TAIL);
7866     testptr(result, result);
7867     jcc(Assembler::zero, LENGTH_DIFF_LABEL);
7868 
7869     movl(result, stride2);
7870     movl(cnt2, result);
7871     negptr(result);
7872     jmp(COMPARE_WIDE_VECTORS_LOOP_AVX2);
7873 
7874     // Identifies the mismatching (higher or lower)16-bytes in the 32-byte vectors.
7875     bind(VECTOR_NOT_EQUAL);
7876     // clean upper bits of YMM registers
7877     vpxor(vec1, vec1);
7878     if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7879       lea(str1, Address(str1, result, scale));
7880       lea(str2, Address(str2, result, scale));
7881     } else {
7882       lea(str1, Address(str1, result, scale1));
7883       lea(str2, Address(str2, result, scale2));
7884     }
7885     jmp(COMPARE_16_CHARS);
7886 
7887     // Compare tail chars, length between 1 to 15 chars
7888     bind(COMPARE_TAIL_LONG);
7889     movl(cnt2, result);
7890     cmpl(cnt2, stride);
7891     jcc(Assembler::less, COMPARE_SMALL_STR);
7892 
7893     if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7894       movdqu(vec1, Address(str1, 0));
7895     } else {
7896       pmovzxbw(vec1, Address(str1, 0));
7897     }
7898     pcmpestri(vec1, Address(str2, 0), pcmpmask);
7899     jcc(Assembler::below, COMPARE_INDEX_CHAR);
7900     subptr(cnt2, stride);
7901     jcc(Assembler::zero, LENGTH_DIFF_LABEL);
7902     if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7903       lea(str1, Address(str1, result, scale));
7904       lea(str2, Address(str2, result, scale));
7905     } else {
7906       lea(str1, Address(str1, result, scale1));
7907       lea(str2, Address(str2, result, scale2));
7908     }
7909     negptr(cnt2);
7910     jmpb(WHILE_HEAD_LABEL);
7911 
7912     bind(COMPARE_SMALL_STR);
7913   } else if (UseSSE42Intrinsics) {
7914     Label COMPARE_WIDE_VECTORS, VECTOR_NOT_EQUAL, COMPARE_TAIL;
7915     int pcmpmask = 0x19;
7916     // Setup to compare 8-char (16-byte) vectors,
7917     // start from first character again because it has aligned address.
7918     movl(result, cnt2);
7919     andl(cnt2, ~(stride - 1));   // cnt2 holds the vector count
7920     if (ae == StrIntrinsicNode::LL) {
7921       pcmpmask &= ~0x01;
7922     }
7923     jcc(Assembler::zero, COMPARE_TAIL);
7924     if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7925       lea(str1, Address(str1, result, scale));
7926       lea(str2, Address(str2, result, scale));
7927     } else {
7928       lea(str1, Address(str1, result, scale1));
7929       lea(str2, Address(str2, result, scale2));
7930     }
7931     negptr(result);
7932 
7933     // pcmpestri
7934     //   inputs:
7935     //     vec1- substring
7936     //     rax - negative string length (elements count)
7937     //     mem - scanned string
7938     //     rdx - string length (elements count)
7939     //     pcmpmask - cmp mode: 11000 (string compare with negated result)
7940     //               + 00 (unsigned bytes) or  + 01 (unsigned shorts)
7941     //   outputs:
7942     //     rcx - first mismatched element index
7943     assert(result == rax && cnt2 == rdx && cnt1 == rcx, "pcmpestri");
7944 
7945     bind(COMPARE_WIDE_VECTORS);
7946     if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7947       movdqu(vec1, Address(str1, result, scale));
7948       pcmpestri(vec1, Address(str2, result, scale), pcmpmask);
7949     } else {
7950       pmovzxbw(vec1, Address(str1, result, scale1));
7951       pcmpestri(vec1, Address(str2, result, scale2), pcmpmask);
7952     }
7953     // After pcmpestri cnt1(rcx) contains mismatched element index
7954 
7955     jccb(Assembler::below, VECTOR_NOT_EQUAL);  // CF==1
7956     addptr(result, stride);
7957     subptr(cnt2, stride);
7958     jccb(Assembler::notZero, COMPARE_WIDE_VECTORS);
7959 
7960     // compare wide vectors tail
7961     testptr(result, result);
7962     jcc(Assembler::zero, LENGTH_DIFF_LABEL);
7963 
7964     movl(cnt2, stride);
7965     movl(result, stride);
7966     negptr(result);
7967     if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7968       movdqu(vec1, Address(str1, result, scale));
7969       pcmpestri(vec1, Address(str2, result, scale), pcmpmask);
7970     } else {
7971       pmovzxbw(vec1, Address(str1, result, scale1));
7972       pcmpestri(vec1, Address(str2, result, scale2), pcmpmask);
7973     }
7974     jccb(Assembler::aboveEqual, LENGTH_DIFF_LABEL);
7975 
7976     // Mismatched characters in the vectors
7977     bind(VECTOR_NOT_EQUAL);
7978     addptr(cnt1, result);
7979     load_next_elements(result, cnt2, str1, str2, scale, scale1, scale2, cnt1, ae);
7980     subl(result, cnt2);
7981     jmpb(POP_LABEL);
7982 
7983     bind(COMPARE_TAIL); // limit is zero
7984     movl(cnt2, result);
7985     // Fallthru to tail compare
7986   }
7987   // Shift str2 and str1 to the end of the arrays, negate min
7988   if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7989     lea(str1, Address(str1, cnt2, scale));
7990     lea(str2, Address(str2, cnt2, scale));
7991   } else {
7992     lea(str1, Address(str1, cnt2, scale1));
7993     lea(str2, Address(str2, cnt2, scale2));
7994   }
7995   decrementl(cnt2);  // first character was compared already
7996   negptr(cnt2);
7997 
7998   // Compare the rest of the elements
7999   bind(WHILE_HEAD_LABEL);
8000   load_next_elements(result, cnt1, str1, str2, scale, scale1, scale2, cnt2, ae);
8001   subl(result, cnt1);
8002   jccb(Assembler::notZero, POP_LABEL);
8003   increment(cnt2);
8004   jccb(Assembler::notZero, WHILE_HEAD_LABEL);
8005 
8006   // Strings are equal up to min length.  Return the length difference.
8007   bind(LENGTH_DIFF_LABEL);
8008   pop(result);
8009   if (ae == StrIntrinsicNode::UU) {
8010     // Divide diff by 2 to get number of chars
8011     sarl(result, 1);
8012   }
8013   jmpb(DONE_LABEL);
8014 
8015 #ifdef _LP64
8016   if (VM_Version::supports_avx512vlbw()) {
8017 
8018     bind(COMPARE_WIDE_VECTORS_LOOP_FAILED);
8019 
8020     kmovql(cnt1, k7);
8021     notq(cnt1);
8022     bsfq(cnt2, cnt1);
8023     if (ae != StrIntrinsicNode::LL) {
8024       // Divide diff by 2 to get number of chars
8025       sarl(cnt2, 1);
8026     }
8027     addq(result, cnt2);
8028     if (ae == StrIntrinsicNode::LL) {
8029       load_unsigned_byte(cnt1, Address(str2, result));
8030       load_unsigned_byte(result, Address(str1, result));
8031     } else if (ae == StrIntrinsicNode::UU) {
8032       load_unsigned_short(cnt1, Address(str2, result, scale));
8033       load_unsigned_short(result, Address(str1, result, scale));
8034     } else {
8035       load_unsigned_short(cnt1, Address(str2, result, scale2));
8036       load_unsigned_byte(result, Address(str1, result, scale1));
8037     }
8038     subl(result, cnt1);
8039     jmpb(POP_LABEL);
8040   }//if (VM_Version::supports_avx512vlbw())
8041 #endif // _LP64
8042 
8043   // Discard the stored length difference
8044   bind(POP_LABEL);
8045   pop(cnt1);
8046 
8047   // That's it
8048   bind(DONE_LABEL);
8049   if(ae == StrIntrinsicNode::UL) {
8050     negl(result);
8051   }
8052 
8053 }
8054 
8055 // Search for Non-ASCII character (Negative byte value) in a byte array,
8056 // return true if it has any and false otherwise.
8057 //   ..\jdk\src\java.base\share\classes\java\lang\StringCoding.java
8058 //   @HotSpotIntrinsicCandidate
8059 //   private static boolean hasNegatives(byte[] ba, int off, int len) {
8060 //     for (int i = off; i < off + len; i++) {
8061 //       if (ba[i] < 0) {
8062 //         return true;
8063 //       }
8064 //     }
8065 //     return false;
8066 //   }
8067 void MacroAssembler::has_negatives(Register ary1, Register len,
8068   Register result, Register tmp1,
8069   XMMRegister vec1, XMMRegister vec2) {
8070   // rsi: byte array
8071   // rcx: len
8072   // rax: result
8073   ShortBranchVerifier sbv(this);
8074   assert_different_registers(ary1, len, result, tmp1);
8075   assert_different_registers(vec1, vec2);
8076   Label TRUE_LABEL, FALSE_LABEL, DONE, COMPARE_CHAR, COMPARE_VECTORS, COMPARE_BYTE;
8077 
8078   // len == 0
8079   testl(len, len);
8080   jcc(Assembler::zero, FALSE_LABEL);
8081 
8082   if ((UseAVX > 2) && // AVX512
8083     VM_Version::supports_avx512vlbw() &&
8084     VM_Version::supports_bmi2()) {
8085 
8086     set_vector_masking();  // opening of the stub context for programming mask registers
8087 
8088     Label test_64_loop, test_tail;
8089     Register tmp3_aliased = len;
8090 
8091     movl(tmp1, len);
8092     vpxor(vec2, vec2, vec2, Assembler::AVX_512bit);
8093 
8094     andl(tmp1, 64 - 1);   // tail count (in chars) 0x3F
8095     andl(len, ~(64 - 1));    // vector count (in chars)
8096     jccb(Assembler::zero, test_tail);
8097 
8098     lea(ary1, Address(ary1, len, Address::times_1));
8099     negptr(len);
8100 
8101     bind(test_64_loop);
8102     // Check whether our 64 elements of size byte contain negatives
8103     evpcmpgtb(k2, vec2, Address(ary1, len, Address::times_1), Assembler::AVX_512bit);
8104     kortestql(k2, k2);
8105     jcc(Assembler::notZero, TRUE_LABEL);
8106 
8107     addptr(len, 64);
8108     jccb(Assembler::notZero, test_64_loop);
8109 
8110 
8111     bind(test_tail);
8112     // bail out when there is nothing to be done
8113     testl(tmp1, -1);
8114     jcc(Assembler::zero, FALSE_LABEL);
8115 
8116     // Save k1
8117     kmovql(k3, k1);
8118 
8119     // ~(~0 << len) applied up to two times (for 32-bit scenario)
8120 #ifdef _LP64
8121     mov64(tmp3_aliased, 0xFFFFFFFFFFFFFFFF);
8122     shlxq(tmp3_aliased, tmp3_aliased, tmp1);
8123     notq(tmp3_aliased);
8124     kmovql(k1, tmp3_aliased);
8125 #else
8126     Label k_init;
8127     jmp(k_init);
8128 
8129     // We could not read 64-bits from a general purpose register thus we move
8130     // data required to compose 64 1's to the instruction stream
8131     // We emit 64 byte wide series of elements from 0..63 which later on would
8132     // be used as a compare targets with tail count contained in tmp1 register.
8133     // Result would be a k1 register having tmp1 consecutive number or 1
8134     // counting from least significant bit.
8135     address tmp = pc();
8136     emit_int64(0x0706050403020100);
8137     emit_int64(0x0F0E0D0C0B0A0908);
8138     emit_int64(0x1716151413121110);
8139     emit_int64(0x1F1E1D1C1B1A1918);
8140     emit_int64(0x2726252423222120);
8141     emit_int64(0x2F2E2D2C2B2A2928);
8142     emit_int64(0x3736353433323130);
8143     emit_int64(0x3F3E3D3C3B3A3938);
8144 
8145     bind(k_init);
8146     lea(len, InternalAddress(tmp));
8147     // create mask to test for negative byte inside a vector
8148     evpbroadcastb(vec1, tmp1, Assembler::AVX_512bit);
8149     evpcmpgtb(k1, vec1, Address(len, 0), Assembler::AVX_512bit);
8150 
8151 #endif
8152     evpcmpgtb(k2, k1, vec2, Address(ary1, 0), Assembler::AVX_512bit);
8153     ktestq(k2, k1);
8154     // Restore k1
8155     kmovql(k1, k3);
8156     jcc(Assembler::notZero, TRUE_LABEL);
8157 
8158     jmp(FALSE_LABEL);
8159 
8160     clear_vector_masking();   // closing of the stub context for programming mask registers
8161   } else {
8162     movl(result, len); // copy
8163 
8164     if (UseAVX == 2 && UseSSE >= 2) {
8165       // With AVX2, use 32-byte vector compare
8166       Label COMPARE_WIDE_VECTORS, COMPARE_TAIL;
8167 
8168       // Compare 32-byte vectors
8169       andl(result, 0x0000001f);  //   tail count (in bytes)
8170       andl(len, 0xffffffe0);   // vector count (in bytes)
8171       jccb(Assembler::zero, COMPARE_TAIL);
8172 
8173       lea(ary1, Address(ary1, len, Address::times_1));
8174       negptr(len);
8175 
8176       movl(tmp1, 0x80808080);   // create mask to test for Unicode chars in vector
8177       movdl(vec2, tmp1);
8178       vpbroadcastd(vec2, vec2);
8179 
8180       bind(COMPARE_WIDE_VECTORS);
8181       vmovdqu(vec1, Address(ary1, len, Address::times_1));
8182       vptest(vec1, vec2);
8183       jccb(Assembler::notZero, TRUE_LABEL);
8184       addptr(len, 32);
8185       jcc(Assembler::notZero, COMPARE_WIDE_VECTORS);
8186 
8187       testl(result, result);
8188       jccb(Assembler::zero, FALSE_LABEL);
8189 
8190       vmovdqu(vec1, Address(ary1, result, Address::times_1, -32));
8191       vptest(vec1, vec2);
8192       jccb(Assembler::notZero, TRUE_LABEL);
8193       jmpb(FALSE_LABEL);
8194 
8195       bind(COMPARE_TAIL); // len is zero
8196       movl(len, result);
8197       // Fallthru to tail compare
8198     } else if (UseSSE42Intrinsics) {
8199       // With SSE4.2, use double quad vector compare
8200       Label COMPARE_WIDE_VECTORS, COMPARE_TAIL;
8201 
8202       // Compare 16-byte vectors
8203       andl(result, 0x0000000f);  //   tail count (in bytes)
8204       andl(len, 0xfffffff0);   // vector count (in bytes)
8205       jccb(Assembler::zero, COMPARE_TAIL);
8206 
8207       lea(ary1, Address(ary1, len, Address::times_1));
8208       negptr(len);
8209 
8210       movl(tmp1, 0x80808080);
8211       movdl(vec2, tmp1);
8212       pshufd(vec2, vec2, 0);
8213 
8214       bind(COMPARE_WIDE_VECTORS);
8215       movdqu(vec1, Address(ary1, len, Address::times_1));
8216       ptest(vec1, vec2);
8217       jccb(Assembler::notZero, TRUE_LABEL);
8218       addptr(len, 16);
8219       jcc(Assembler::notZero, COMPARE_WIDE_VECTORS);
8220 
8221       testl(result, result);
8222       jccb(Assembler::zero, FALSE_LABEL);
8223 
8224       movdqu(vec1, Address(ary1, result, Address::times_1, -16));
8225       ptest(vec1, vec2);
8226       jccb(Assembler::notZero, TRUE_LABEL);
8227       jmpb(FALSE_LABEL);
8228 
8229       bind(COMPARE_TAIL); // len is zero
8230       movl(len, result);
8231       // Fallthru to tail compare
8232     }
8233   }
8234   // Compare 4-byte vectors
8235   andl(len, 0xfffffffc); // vector count (in bytes)
8236   jccb(Assembler::zero, COMPARE_CHAR);
8237 
8238   lea(ary1, Address(ary1, len, Address::times_1));
8239   negptr(len);
8240 
8241   bind(COMPARE_VECTORS);
8242   movl(tmp1, Address(ary1, len, Address::times_1));
8243   andl(tmp1, 0x80808080);
8244   jccb(Assembler::notZero, TRUE_LABEL);
8245   addptr(len, 4);
8246   jcc(Assembler::notZero, COMPARE_VECTORS);
8247 
8248   // Compare trailing char (final 2 bytes), if any
8249   bind(COMPARE_CHAR);
8250   testl(result, 0x2);   // tail  char
8251   jccb(Assembler::zero, COMPARE_BYTE);
8252   load_unsigned_short(tmp1, Address(ary1, 0));
8253   andl(tmp1, 0x00008080);
8254   jccb(Assembler::notZero, TRUE_LABEL);
8255   subptr(result, 2);
8256   lea(ary1, Address(ary1, 2));
8257 
8258   bind(COMPARE_BYTE);
8259   testl(result, 0x1);   // tail  byte
8260   jccb(Assembler::zero, FALSE_LABEL);
8261   load_unsigned_byte(tmp1, Address(ary1, 0));
8262   andl(tmp1, 0x00000080);
8263   jccb(Assembler::notEqual, TRUE_LABEL);
8264   jmpb(FALSE_LABEL);
8265 
8266   bind(TRUE_LABEL);
8267   movl(result, 1);   // return true
8268   jmpb(DONE);
8269 
8270   bind(FALSE_LABEL);
8271   xorl(result, result); // return false
8272 
8273   // That's it
8274   bind(DONE);
8275   if (UseAVX >= 2 && UseSSE >= 2) {
8276     // clean upper bits of YMM registers
8277     vpxor(vec1, vec1);
8278     vpxor(vec2, vec2);
8279   }
8280 }
8281 // Compare char[] or byte[] arrays aligned to 4 bytes or substrings.
8282 void MacroAssembler::arrays_equals(bool is_array_equ, Register ary1, Register ary2,
8283                                    Register limit, Register result, Register chr,
8284                                    XMMRegister vec1, XMMRegister vec2, bool is_char) {
8285   ShortBranchVerifier sbv(this);
8286   Label TRUE_LABEL, FALSE_LABEL, DONE, COMPARE_VECTORS, COMPARE_CHAR, COMPARE_BYTE;
8287 
8288   int length_offset  = arrayOopDesc::length_offset_in_bytes();
8289   int base_offset    = arrayOopDesc::base_offset_in_bytes(is_char ? T_CHAR : T_BYTE);
8290 
8291   if (is_array_equ) {
8292     // Check the input args
8293     cmpptr(ary1, ary2);
8294     jcc(Assembler::equal, TRUE_LABEL);
8295 
8296     // Need additional checks for arrays_equals.
8297     testptr(ary1, ary1);
8298     jcc(Assembler::zero, FALSE_LABEL);
8299     testptr(ary2, ary2);
8300     jcc(Assembler::zero, FALSE_LABEL);
8301 
8302     // Check the lengths
8303     movl(limit, Address(ary1, length_offset));
8304     cmpl(limit, Address(ary2, length_offset));
8305     jcc(Assembler::notEqual, FALSE_LABEL);
8306   }
8307 
8308   // count == 0
8309   testl(limit, limit);
8310   jcc(Assembler::zero, TRUE_LABEL);
8311 
8312   if (is_array_equ) {
8313     // Load array address
8314     lea(ary1, Address(ary1, base_offset));
8315     lea(ary2, Address(ary2, base_offset));
8316   }
8317 
8318   if (is_array_equ && is_char) {
8319     // arrays_equals when used for char[].
8320     shll(limit, 1);      // byte count != 0
8321   }
8322   movl(result, limit); // copy
8323 
8324   if (UseAVX >= 2) {
8325     // With AVX2, use 32-byte vector compare
8326     Label COMPARE_WIDE_VECTORS, COMPARE_TAIL;
8327 
8328     // Compare 32-byte vectors
8329     andl(result, 0x0000001f);  //   tail count (in bytes)
8330     andl(limit, 0xffffffe0);   // vector count (in bytes)
8331     jcc(Assembler::zero, COMPARE_TAIL);
8332 
8333     lea(ary1, Address(ary1, limit, Address::times_1));
8334     lea(ary2, Address(ary2, limit, Address::times_1));
8335     negptr(limit);
8336 
8337     bind(COMPARE_WIDE_VECTORS);
8338 
8339 #ifdef _LP64
8340     if (VM_Version::supports_avx512vlbw()) { // trying 64 bytes fast loop
8341       Label COMPARE_WIDE_VECTORS_LOOP_AVX2, COMPARE_WIDE_VECTORS_LOOP_AVX3;
8342 
8343       cmpl(limit, -64);
8344       jccb(Assembler::greater, COMPARE_WIDE_VECTORS_LOOP_AVX2);
8345 
8346       bind(COMPARE_WIDE_VECTORS_LOOP_AVX3); // the hottest loop
8347 
8348       evmovdquq(vec1, Address(ary1, limit, Address::times_1), Assembler::AVX_512bit);
8349       evpcmpeqb(k7, vec1, Address(ary2, limit, Address::times_1), Assembler::AVX_512bit);
8350       kortestql(k7, k7);
8351       jcc(Assembler::aboveEqual, FALSE_LABEL);     // miscompare
8352       addptr(limit, 64);  // update since we already compared at this addr
8353       cmpl(limit, -64);
8354       jccb(Assembler::lessEqual, COMPARE_WIDE_VECTORS_LOOP_AVX3);
8355 
8356       // At this point we may still need to compare -limit+result bytes.
8357       // We could execute the next two instruction and just continue via non-wide path:
8358       //  cmpl(limit, 0);
8359       //  jcc(Assembler::equal, COMPARE_TAIL);  // true
8360       // But since we stopped at the points ary{1,2}+limit which are
8361       // not farther than 64 bytes from the ends of arrays ary{1,2}+result
8362       // (|limit| <= 32 and result < 32),
8363       // we may just compare the last 64 bytes.
8364       //
8365       addptr(result, -64);   // it is safe, bc we just came from this area
8366       evmovdquq(vec1, Address(ary1, result, Address::times_1), Assembler::AVX_512bit);
8367       evpcmpeqb(k7, vec1, Address(ary2, result, Address::times_1), Assembler::AVX_512bit);
8368       kortestql(k7, k7);
8369       jcc(Assembler::aboveEqual, FALSE_LABEL);     // miscompare
8370 
8371       jmp(TRUE_LABEL);
8372 
8373       bind(COMPARE_WIDE_VECTORS_LOOP_AVX2);
8374 
8375     }//if (VM_Version::supports_avx512vlbw())
8376 #endif //_LP64
8377 
8378     vmovdqu(vec1, Address(ary1, limit, Address::times_1));
8379     vmovdqu(vec2, Address(ary2, limit, Address::times_1));
8380     vpxor(vec1, vec2);
8381 
8382     vptest(vec1, vec1);
8383     jcc(Assembler::notZero, FALSE_LABEL);
8384     addptr(limit, 32);
8385     jcc(Assembler::notZero, COMPARE_WIDE_VECTORS);
8386 
8387     testl(result, result);
8388     jcc(Assembler::zero, TRUE_LABEL);
8389 
8390     vmovdqu(vec1, Address(ary1, result, Address::times_1, -32));
8391     vmovdqu(vec2, Address(ary2, result, Address::times_1, -32));
8392     vpxor(vec1, vec2);
8393 
8394     vptest(vec1, vec1);
8395     jccb(Assembler::notZero, FALSE_LABEL);
8396     jmpb(TRUE_LABEL);
8397 
8398     bind(COMPARE_TAIL); // limit is zero
8399     movl(limit, result);
8400     // Fallthru to tail compare
8401   } else if (UseSSE42Intrinsics) {
8402     // With SSE4.2, use double quad vector compare
8403     Label COMPARE_WIDE_VECTORS, COMPARE_TAIL;
8404 
8405     // Compare 16-byte vectors
8406     andl(result, 0x0000000f);  //   tail count (in bytes)
8407     andl(limit, 0xfffffff0);   // vector count (in bytes)
8408     jcc(Assembler::zero, COMPARE_TAIL);
8409 
8410     lea(ary1, Address(ary1, limit, Address::times_1));
8411     lea(ary2, Address(ary2, limit, Address::times_1));
8412     negptr(limit);
8413 
8414     bind(COMPARE_WIDE_VECTORS);
8415     movdqu(vec1, Address(ary1, limit, Address::times_1));
8416     movdqu(vec2, Address(ary2, limit, Address::times_1));
8417     pxor(vec1, vec2);
8418 
8419     ptest(vec1, vec1);
8420     jcc(Assembler::notZero, FALSE_LABEL);
8421     addptr(limit, 16);
8422     jcc(Assembler::notZero, COMPARE_WIDE_VECTORS);
8423 
8424     testl(result, result);
8425     jcc(Assembler::zero, TRUE_LABEL);
8426 
8427     movdqu(vec1, Address(ary1, result, Address::times_1, -16));
8428     movdqu(vec2, Address(ary2, result, Address::times_1, -16));
8429     pxor(vec1, vec2);
8430 
8431     ptest(vec1, vec1);
8432     jccb(Assembler::notZero, FALSE_LABEL);
8433     jmpb(TRUE_LABEL);
8434 
8435     bind(COMPARE_TAIL); // limit is zero
8436     movl(limit, result);
8437     // Fallthru to tail compare
8438   }
8439 
8440   // Compare 4-byte vectors
8441   andl(limit, 0xfffffffc); // vector count (in bytes)
8442   jccb(Assembler::zero, COMPARE_CHAR);
8443 
8444   lea(ary1, Address(ary1, limit, Address::times_1));
8445   lea(ary2, Address(ary2, limit, Address::times_1));
8446   negptr(limit);
8447 
8448   bind(COMPARE_VECTORS);
8449   movl(chr, Address(ary1, limit, Address::times_1));
8450   cmpl(chr, Address(ary2, limit, Address::times_1));
8451   jccb(Assembler::notEqual, FALSE_LABEL);
8452   addptr(limit, 4);
8453   jcc(Assembler::notZero, COMPARE_VECTORS);
8454 
8455   // Compare trailing char (final 2 bytes), if any
8456   bind(COMPARE_CHAR);
8457   testl(result, 0x2);   // tail  char
8458   jccb(Assembler::zero, COMPARE_BYTE);
8459   load_unsigned_short(chr, Address(ary1, 0));
8460   load_unsigned_short(limit, Address(ary2, 0));
8461   cmpl(chr, limit);
8462   jccb(Assembler::notEqual, FALSE_LABEL);
8463 
8464   if (is_array_equ && is_char) {
8465     bind(COMPARE_BYTE);
8466   } else {
8467     lea(ary1, Address(ary1, 2));
8468     lea(ary2, Address(ary2, 2));
8469 
8470     bind(COMPARE_BYTE);
8471     testl(result, 0x1);   // tail  byte
8472     jccb(Assembler::zero, TRUE_LABEL);
8473     load_unsigned_byte(chr, Address(ary1, 0));
8474     load_unsigned_byte(limit, Address(ary2, 0));
8475     cmpl(chr, limit);
8476     jccb(Assembler::notEqual, FALSE_LABEL);
8477   }
8478   bind(TRUE_LABEL);
8479   movl(result, 1);   // return true
8480   jmpb(DONE);
8481 
8482   bind(FALSE_LABEL);
8483   xorl(result, result); // return false
8484 
8485   // That's it
8486   bind(DONE);
8487   if (UseAVX >= 2) {
8488     // clean upper bits of YMM registers
8489     vpxor(vec1, vec1);
8490     vpxor(vec2, vec2);
8491   }
8492 }
8493 
8494 #endif
8495 
8496 void MacroAssembler::generate_fill(BasicType t, bool aligned,
8497                                    Register to, Register value, Register count,
8498                                    Register rtmp, XMMRegister xtmp) {
8499   ShortBranchVerifier sbv(this);
8500   assert_different_registers(to, value, count, rtmp);
8501   Label L_exit, L_skip_align1, L_skip_align2, L_fill_byte;
8502   Label L_fill_2_bytes, L_fill_4_bytes;
8503 
8504   int shift = -1;
8505   switch (t) {
8506     case T_BYTE:
8507       shift = 2;
8508       break;
8509     case T_SHORT:
8510       shift = 1;
8511       break;
8512     case T_INT:
8513       shift = 0;
8514       break;
8515     default: ShouldNotReachHere();
8516   }
8517 
8518   if (t == T_BYTE) {
8519     andl(value, 0xff);
8520     movl(rtmp, value);
8521     shll(rtmp, 8);
8522     orl(value, rtmp);
8523   }
8524   if (t == T_SHORT) {
8525     andl(value, 0xffff);
8526   }
8527   if (t == T_BYTE || t == T_SHORT) {
8528     movl(rtmp, value);
8529     shll(rtmp, 16);
8530     orl(value, rtmp);
8531   }
8532 
8533   cmpl(count, 2<<shift); // Short arrays (< 8 bytes) fill by element
8534   jcc(Assembler::below, L_fill_4_bytes); // use unsigned cmp
8535   if (!UseUnalignedLoadStores && !aligned && (t == T_BYTE || t == T_SHORT)) {
8536     // align source address at 4 bytes address boundary
8537     if (t == T_BYTE) {
8538       // One byte misalignment happens only for byte arrays
8539       testptr(to, 1);
8540       jccb(Assembler::zero, L_skip_align1);
8541       movb(Address(to, 0), value);
8542       increment(to);
8543       decrement(count);
8544       BIND(L_skip_align1);
8545     }
8546     // Two bytes misalignment happens only for byte and short (char) arrays
8547     testptr(to, 2);
8548     jccb(Assembler::zero, L_skip_align2);
8549     movw(Address(to, 0), value);
8550     addptr(to, 2);
8551     subl(count, 1<<(shift-1));
8552     BIND(L_skip_align2);
8553   }
8554   if (UseSSE < 2) {
8555     Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes;
8556     // Fill 32-byte chunks
8557     subl(count, 8 << shift);
8558     jcc(Assembler::less, L_check_fill_8_bytes);
8559     align(16);
8560 
8561     BIND(L_fill_32_bytes_loop);
8562 
8563     for (int i = 0; i < 32; i += 4) {
8564       movl(Address(to, i), value);
8565     }
8566 
8567     addptr(to, 32);
8568     subl(count, 8 << shift);
8569     jcc(Assembler::greaterEqual, L_fill_32_bytes_loop);
8570     BIND(L_check_fill_8_bytes);
8571     addl(count, 8 << shift);
8572     jccb(Assembler::zero, L_exit);
8573     jmpb(L_fill_8_bytes);
8574 
8575     //
8576     // length is too short, just fill qwords
8577     //
8578     BIND(L_fill_8_bytes_loop);
8579     movl(Address(to, 0), value);
8580     movl(Address(to, 4), value);
8581     addptr(to, 8);
8582     BIND(L_fill_8_bytes);
8583     subl(count, 1 << (shift + 1));
8584     jcc(Assembler::greaterEqual, L_fill_8_bytes_loop);
8585     // fall through to fill 4 bytes
8586   } else {
8587     Label L_fill_32_bytes;
8588     if (!UseUnalignedLoadStores) {
8589       // align to 8 bytes, we know we are 4 byte aligned to start
8590       testptr(to, 4);
8591       jccb(Assembler::zero, L_fill_32_bytes);
8592       movl(Address(to, 0), value);
8593       addptr(to, 4);
8594       subl(count, 1<<shift);
8595     }
8596     BIND(L_fill_32_bytes);
8597     {
8598       assert( UseSSE >= 2, "supported cpu only" );
8599       Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes;
8600       if (UseAVX > 2) {
8601         movl(rtmp, 0xffff);
8602         kmovwl(k1, rtmp);
8603       }
8604       movdl(xtmp, value);
8605       if (UseAVX > 2 && UseUnalignedLoadStores) {
8606         // Fill 64-byte chunks
8607         Label L_fill_64_bytes_loop, L_check_fill_32_bytes;
8608         evpbroadcastd(xtmp, xtmp, Assembler::AVX_512bit);
8609 
8610         subl(count, 16 << shift);
8611         jcc(Assembler::less, L_check_fill_32_bytes);
8612         align(16);
8613 
8614         BIND(L_fill_64_bytes_loop);
8615         evmovdqul(Address(to, 0), xtmp, Assembler::AVX_512bit);
8616         addptr(to, 64);
8617         subl(count, 16 << shift);
8618         jcc(Assembler::greaterEqual, L_fill_64_bytes_loop);
8619 
8620         BIND(L_check_fill_32_bytes);
8621         addl(count, 8 << shift);
8622         jccb(Assembler::less, L_check_fill_8_bytes);
8623         vmovdqu(Address(to, 0), xtmp);
8624         addptr(to, 32);
8625         subl(count, 8 << shift);
8626 
8627         BIND(L_check_fill_8_bytes);
8628       } else if (UseAVX == 2 && UseUnalignedLoadStores) {
8629         // Fill 64-byte chunks
8630         Label L_fill_64_bytes_loop, L_check_fill_32_bytes;
8631         vpbroadcastd(xtmp, xtmp);
8632 
8633         subl(count, 16 << shift);
8634         jcc(Assembler::less, L_check_fill_32_bytes);
8635         align(16);
8636 
8637         BIND(L_fill_64_bytes_loop);
8638         vmovdqu(Address(to, 0), xtmp);
8639         vmovdqu(Address(to, 32), xtmp);
8640         addptr(to, 64);
8641         subl(count, 16 << shift);
8642         jcc(Assembler::greaterEqual, L_fill_64_bytes_loop);
8643 
8644         BIND(L_check_fill_32_bytes);
8645         addl(count, 8 << shift);
8646         jccb(Assembler::less, L_check_fill_8_bytes);
8647         vmovdqu(Address(to, 0), xtmp);
8648         addptr(to, 32);
8649         subl(count, 8 << shift);
8650 
8651         BIND(L_check_fill_8_bytes);
8652         // clean upper bits of YMM registers
8653         movdl(xtmp, value);
8654         pshufd(xtmp, xtmp, 0);
8655       } else {
8656         // Fill 32-byte chunks
8657         pshufd(xtmp, xtmp, 0);
8658 
8659         subl(count, 8 << shift);
8660         jcc(Assembler::less, L_check_fill_8_bytes);
8661         align(16);
8662 
8663         BIND(L_fill_32_bytes_loop);
8664 
8665         if (UseUnalignedLoadStores) {
8666           movdqu(Address(to, 0), xtmp);
8667           movdqu(Address(to, 16), xtmp);
8668         } else {
8669           movq(Address(to, 0), xtmp);
8670           movq(Address(to, 8), xtmp);
8671           movq(Address(to, 16), xtmp);
8672           movq(Address(to, 24), xtmp);
8673         }
8674 
8675         addptr(to, 32);
8676         subl(count, 8 << shift);
8677         jcc(Assembler::greaterEqual, L_fill_32_bytes_loop);
8678 
8679         BIND(L_check_fill_8_bytes);
8680       }
8681       addl(count, 8 << shift);
8682       jccb(Assembler::zero, L_exit);
8683       jmpb(L_fill_8_bytes);
8684 
8685       //
8686       // length is too short, just fill qwords
8687       //
8688       BIND(L_fill_8_bytes_loop);
8689       movq(Address(to, 0), xtmp);
8690       addptr(to, 8);
8691       BIND(L_fill_8_bytes);
8692       subl(count, 1 << (shift + 1));
8693       jcc(Assembler::greaterEqual, L_fill_8_bytes_loop);
8694     }
8695   }
8696   // fill trailing 4 bytes
8697   BIND(L_fill_4_bytes);
8698   testl(count, 1<<shift);
8699   jccb(Assembler::zero, L_fill_2_bytes);
8700   movl(Address(to, 0), value);
8701   if (t == T_BYTE || t == T_SHORT) {
8702     addptr(to, 4);
8703     BIND(L_fill_2_bytes);
8704     // fill trailing 2 bytes
8705     testl(count, 1<<(shift-1));
8706     jccb(Assembler::zero, L_fill_byte);
8707     movw(Address(to, 0), value);
8708     if (t == T_BYTE) {
8709       addptr(to, 2);
8710       BIND(L_fill_byte);
8711       // fill trailing byte
8712       testl(count, 1);
8713       jccb(Assembler::zero, L_exit);
8714       movb(Address(to, 0), value);
8715     } else {
8716       BIND(L_fill_byte);
8717     }
8718   } else {
8719     BIND(L_fill_2_bytes);
8720   }
8721   BIND(L_exit);
8722 }
8723 
8724 // encode char[] to byte[] in ISO_8859_1
8725    //@HotSpotIntrinsicCandidate
8726    //private static int implEncodeISOArray(byte[] sa, int sp,
8727    //byte[] da, int dp, int len) {
8728    //  int i = 0;
8729    //  for (; i < len; i++) {
8730    //    char c = StringUTF16.getChar(sa, sp++);
8731    //    if (c > '\u00FF')
8732    //      break;
8733    //    da[dp++] = (byte)c;
8734    //  }
8735    //  return i;
8736    //}
8737 void MacroAssembler::encode_iso_array(Register src, Register dst, Register len,
8738   XMMRegister tmp1Reg, XMMRegister tmp2Reg,
8739   XMMRegister tmp3Reg, XMMRegister tmp4Reg,
8740   Register tmp5, Register result) {
8741 
8742   // rsi: src
8743   // rdi: dst
8744   // rdx: len
8745   // rcx: tmp5
8746   // rax: result
8747   ShortBranchVerifier sbv(this);
8748   assert_different_registers(src, dst, len, tmp5, result);
8749   Label L_done, L_copy_1_char, L_copy_1_char_exit;
8750 
8751   // set result
8752   xorl(result, result);
8753   // check for zero length
8754   testl(len, len);
8755   jcc(Assembler::zero, L_done);
8756 
8757   movl(result, len);
8758 
8759   // Setup pointers
8760   lea(src, Address(src, len, Address::times_2)); // char[]
8761   lea(dst, Address(dst, len, Address::times_1)); // byte[]
8762   negptr(len);
8763 
8764   if (UseSSE42Intrinsics || UseAVX >= 2) {
8765     Label L_chars_8_check, L_copy_8_chars, L_copy_8_chars_exit;
8766     Label L_chars_16_check, L_copy_16_chars, L_copy_16_chars_exit;
8767 
8768     if (UseAVX >= 2) {
8769       Label L_chars_32_check, L_copy_32_chars, L_copy_32_chars_exit;
8770       movl(tmp5, 0xff00ff00);   // create mask to test for Unicode chars in vector
8771       movdl(tmp1Reg, tmp5);
8772       vpbroadcastd(tmp1Reg, tmp1Reg);
8773       jmp(L_chars_32_check);
8774 
8775       bind(L_copy_32_chars);
8776       vmovdqu(tmp3Reg, Address(src, len, Address::times_2, -64));
8777       vmovdqu(tmp4Reg, Address(src, len, Address::times_2, -32));
8778       vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector_len */ 1);
8779       vptest(tmp2Reg, tmp1Reg);       // check for Unicode chars in  vector
8780       jccb(Assembler::notZero, L_copy_32_chars_exit);
8781       vpackuswb(tmp3Reg, tmp3Reg, tmp4Reg, /* vector_len */ 1);
8782       vpermq(tmp4Reg, tmp3Reg, 0xD8, /* vector_len */ 1);
8783       vmovdqu(Address(dst, len, Address::times_1, -32), tmp4Reg);
8784 
8785       bind(L_chars_32_check);
8786       addptr(len, 32);
8787       jcc(Assembler::lessEqual, L_copy_32_chars);
8788 
8789       bind(L_copy_32_chars_exit);
8790       subptr(len, 16);
8791       jccb(Assembler::greater, L_copy_16_chars_exit);
8792 
8793     } else if (UseSSE42Intrinsics) {
8794       movl(tmp5, 0xff00ff00);   // create mask to test for Unicode chars in vector
8795       movdl(tmp1Reg, tmp5);
8796       pshufd(tmp1Reg, tmp1Reg, 0);
8797       jmpb(L_chars_16_check);
8798     }
8799 
8800     bind(L_copy_16_chars);
8801     if (UseAVX >= 2) {
8802       vmovdqu(tmp2Reg, Address(src, len, Address::times_2, -32));
8803       vptest(tmp2Reg, tmp1Reg);
8804       jcc(Assembler::notZero, L_copy_16_chars_exit);
8805       vpackuswb(tmp2Reg, tmp2Reg, tmp1Reg, /* vector_len */ 1);
8806       vpermq(tmp3Reg, tmp2Reg, 0xD8, /* vector_len */ 1);
8807     } else {
8808       if (UseAVX > 0) {
8809         movdqu(tmp3Reg, Address(src, len, Address::times_2, -32));
8810         movdqu(tmp4Reg, Address(src, len, Address::times_2, -16));
8811         vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector_len */ 0);
8812       } else {
8813         movdqu(tmp3Reg, Address(src, len, Address::times_2, -32));
8814         por(tmp2Reg, tmp3Reg);
8815         movdqu(tmp4Reg, Address(src, len, Address::times_2, -16));
8816         por(tmp2Reg, tmp4Reg);
8817       }
8818       ptest(tmp2Reg, tmp1Reg);       // check for Unicode chars in  vector
8819       jccb(Assembler::notZero, L_copy_16_chars_exit);
8820       packuswb(tmp3Reg, tmp4Reg);
8821     }
8822     movdqu(Address(dst, len, Address::times_1, -16), tmp3Reg);
8823 
8824     bind(L_chars_16_check);
8825     addptr(len, 16);
8826     jcc(Assembler::lessEqual, L_copy_16_chars);
8827 
8828     bind(L_copy_16_chars_exit);
8829     if (UseAVX >= 2) {
8830       // clean upper bits of YMM registers
8831       vpxor(tmp2Reg, tmp2Reg);
8832       vpxor(tmp3Reg, tmp3Reg);
8833       vpxor(tmp4Reg, tmp4Reg);
8834       movdl(tmp1Reg, tmp5);
8835       pshufd(tmp1Reg, tmp1Reg, 0);
8836     }
8837     subptr(len, 8);
8838     jccb(Assembler::greater, L_copy_8_chars_exit);
8839 
8840     bind(L_copy_8_chars);
8841     movdqu(tmp3Reg, Address(src, len, Address::times_2, -16));
8842     ptest(tmp3Reg, tmp1Reg);
8843     jccb(Assembler::notZero, L_copy_8_chars_exit);
8844     packuswb(tmp3Reg, tmp1Reg);
8845     movq(Address(dst, len, Address::times_1, -8), tmp3Reg);
8846     addptr(len, 8);
8847     jccb(Assembler::lessEqual, L_copy_8_chars);
8848 
8849     bind(L_copy_8_chars_exit);
8850     subptr(len, 8);
8851     jccb(Assembler::zero, L_done);
8852   }
8853 
8854   bind(L_copy_1_char);
8855   load_unsigned_short(tmp5, Address(src, len, Address::times_2, 0));
8856   testl(tmp5, 0xff00);      // check if Unicode char
8857   jccb(Assembler::notZero, L_copy_1_char_exit);
8858   movb(Address(dst, len, Address::times_1, 0), tmp5);
8859   addptr(len, 1);
8860   jccb(Assembler::less, L_copy_1_char);
8861 
8862   bind(L_copy_1_char_exit);
8863   addptr(result, len); // len is negative count of not processed elements
8864 
8865   bind(L_done);
8866 }
8867 
8868 #ifdef _LP64
8869 /**
8870  * Helper for multiply_to_len().
8871  */
8872 void MacroAssembler::add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2) {
8873   addq(dest_lo, src1);
8874   adcq(dest_hi, 0);
8875   addq(dest_lo, src2);
8876   adcq(dest_hi, 0);
8877 }
8878 
8879 /**
8880  * Multiply 64 bit by 64 bit first loop.
8881  */
8882 void MacroAssembler::multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
8883                                            Register y, Register y_idx, Register z,
8884                                            Register carry, Register product,
8885                                            Register idx, Register kdx) {
8886   //
8887   //  jlong carry, x[], y[], z[];
8888   //  for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
8889   //    huge_128 product = y[idx] * x[xstart] + carry;
8890   //    z[kdx] = (jlong)product;
8891   //    carry  = (jlong)(product >>> 64);
8892   //  }
8893   //  z[xstart] = carry;
8894   //
8895 
8896   Label L_first_loop, L_first_loop_exit;
8897   Label L_one_x, L_one_y, L_multiply;
8898 
8899   decrementl(xstart);
8900   jcc(Assembler::negative, L_one_x);
8901 
8902   movq(x_xstart, Address(x, xstart, Address::times_4,  0));
8903   rorq(x_xstart, 32); // convert big-endian to little-endian
8904 
8905   bind(L_first_loop);
8906   decrementl(idx);
8907   jcc(Assembler::negative, L_first_loop_exit);
8908   decrementl(idx);
8909   jcc(Assembler::negative, L_one_y);
8910   movq(y_idx, Address(y, idx, Address::times_4,  0));
8911   rorq(y_idx, 32); // convert big-endian to little-endian
8912   bind(L_multiply);
8913   movq(product, x_xstart);
8914   mulq(y_idx); // product(rax) * y_idx -> rdx:rax
8915   addq(product, carry);
8916   adcq(rdx, 0);
8917   subl(kdx, 2);
8918   movl(Address(z, kdx, Address::times_4,  4), product);
8919   shrq(product, 32);
8920   movl(Address(z, kdx, Address::times_4,  0), product);
8921   movq(carry, rdx);
8922   jmp(L_first_loop);
8923 
8924   bind(L_one_y);
8925   movl(y_idx, Address(y,  0));
8926   jmp(L_multiply);
8927 
8928   bind(L_one_x);
8929   movl(x_xstart, Address(x,  0));
8930   jmp(L_first_loop);
8931 
8932   bind(L_first_loop_exit);
8933 }
8934 
8935 /**
8936  * Multiply 64 bit by 64 bit and add 128 bit.
8937  */
8938 void MacroAssembler::multiply_add_128_x_128(Register x_xstart, Register y, Register z,
8939                                             Register yz_idx, Register idx,
8940                                             Register carry, Register product, int offset) {
8941   //     huge_128 product = (y[idx] * x_xstart) + z[kdx] + carry;
8942   //     z[kdx] = (jlong)product;
8943 
8944   movq(yz_idx, Address(y, idx, Address::times_4,  offset));
8945   rorq(yz_idx, 32); // convert big-endian to little-endian
8946   movq(product, x_xstart);
8947   mulq(yz_idx);     // product(rax) * yz_idx -> rdx:product(rax)
8948   movq(yz_idx, Address(z, idx, Address::times_4,  offset));
8949   rorq(yz_idx, 32); // convert big-endian to little-endian
8950 
8951   add2_with_carry(rdx, product, carry, yz_idx);
8952 
8953   movl(Address(z, idx, Address::times_4,  offset+4), product);
8954   shrq(product, 32);
8955   movl(Address(z, idx, Address::times_4,  offset), product);
8956 
8957 }
8958 
8959 /**
8960  * Multiply 128 bit by 128 bit. Unrolled inner loop.
8961  */
8962 void MacroAssembler::multiply_128_x_128_loop(Register x_xstart, Register y, Register z,
8963                                              Register yz_idx, Register idx, Register jdx,
8964                                              Register carry, Register product,
8965                                              Register carry2) {
8966   //   jlong carry, x[], y[], z[];
8967   //   int kdx = ystart+1;
8968   //   for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop
8969   //     huge_128 product = (y[idx+1] * x_xstart) + z[kdx+idx+1] + carry;
8970   //     z[kdx+idx+1] = (jlong)product;
8971   //     jlong carry2  = (jlong)(product >>> 64);
8972   //     product = (y[idx] * x_xstart) + z[kdx+idx] + carry2;
8973   //     z[kdx+idx] = (jlong)product;
8974   //     carry  = (jlong)(product >>> 64);
8975   //   }
8976   //   idx += 2;
8977   //   if (idx > 0) {
8978   //     product = (y[idx] * x_xstart) + z[kdx+idx] + carry;
8979   //     z[kdx+idx] = (jlong)product;
8980   //     carry  = (jlong)(product >>> 64);
8981   //   }
8982   //
8983 
8984   Label L_third_loop, L_third_loop_exit, L_post_third_loop_done;
8985 
8986   movl(jdx, idx);
8987   andl(jdx, 0xFFFFFFFC);
8988   shrl(jdx, 2);
8989 
8990   bind(L_third_loop);
8991   subl(jdx, 1);
8992   jcc(Assembler::negative, L_third_loop_exit);
8993   subl(idx, 4);
8994 
8995   multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry, product, 8);
8996   movq(carry2, rdx);
8997 
8998   multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry2, product, 0);
8999   movq(carry, rdx);
9000   jmp(L_third_loop);
9001 
9002   bind (L_third_loop_exit);
9003 
9004   andl (idx, 0x3);
9005   jcc(Assembler::zero, L_post_third_loop_done);
9006 
9007   Label L_check_1;
9008   subl(idx, 2);
9009   jcc(Assembler::negative, L_check_1);
9010 
9011   multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry, product, 0);
9012   movq(carry, rdx);
9013 
9014   bind (L_check_1);
9015   addl (idx, 0x2);
9016   andl (idx, 0x1);
9017   subl(idx, 1);
9018   jcc(Assembler::negative, L_post_third_loop_done);
9019 
9020   movl(yz_idx, Address(y, idx, Address::times_4,  0));
9021   movq(product, x_xstart);
9022   mulq(yz_idx); // product(rax) * yz_idx -> rdx:product(rax)
9023   movl(yz_idx, Address(z, idx, Address::times_4,  0));
9024 
9025   add2_with_carry(rdx, product, yz_idx, carry);
9026 
9027   movl(Address(z, idx, Address::times_4,  0), product);
9028   shrq(product, 32);
9029 
9030   shlq(rdx, 32);
9031   orq(product, rdx);
9032   movq(carry, product);
9033 
9034   bind(L_post_third_loop_done);
9035 }
9036 
9037 /**
9038  * Multiply 128 bit by 128 bit using BMI2. Unrolled inner loop.
9039  *
9040  */
9041 void MacroAssembler::multiply_128_x_128_bmi2_loop(Register y, Register z,
9042                                                   Register carry, Register carry2,
9043                                                   Register idx, Register jdx,
9044                                                   Register yz_idx1, Register yz_idx2,
9045                                                   Register tmp, Register tmp3, Register tmp4) {
9046   assert(UseBMI2Instructions, "should be used only when BMI2 is available");
9047 
9048   //   jlong carry, x[], y[], z[];
9049   //   int kdx = ystart+1;
9050   //   for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop
9051   //     huge_128 tmp3 = (y[idx+1] * rdx) + z[kdx+idx+1] + carry;
9052   //     jlong carry2  = (jlong)(tmp3 >>> 64);
9053   //     huge_128 tmp4 = (y[idx]   * rdx) + z[kdx+idx] + carry2;
9054   //     carry  = (jlong)(tmp4 >>> 64);
9055   //     z[kdx+idx+1] = (jlong)tmp3;
9056   //     z[kdx+idx] = (jlong)tmp4;
9057   //   }
9058   //   idx += 2;
9059   //   if (idx > 0) {
9060   //     yz_idx1 = (y[idx] * rdx) + z[kdx+idx] + carry;
9061   //     z[kdx+idx] = (jlong)yz_idx1;
9062   //     carry  = (jlong)(yz_idx1 >>> 64);
9063   //   }
9064   //
9065 
9066   Label L_third_loop, L_third_loop_exit, L_post_third_loop_done;
9067 
9068   movl(jdx, idx);
9069   andl(jdx, 0xFFFFFFFC);
9070   shrl(jdx, 2);
9071 
9072   bind(L_third_loop);
9073   subl(jdx, 1);
9074   jcc(Assembler::negative, L_third_loop_exit);
9075   subl(idx, 4);
9076 
9077   movq(yz_idx1,  Address(y, idx, Address::times_4,  8));
9078   rorxq(yz_idx1, yz_idx1, 32); // convert big-endian to little-endian
9079   movq(yz_idx2, Address(y, idx, Address::times_4,  0));
9080   rorxq(yz_idx2, yz_idx2, 32);
9081 
9082   mulxq(tmp4, tmp3, yz_idx1);  //  yz_idx1 * rdx -> tmp4:tmp3
9083   mulxq(carry2, tmp, yz_idx2); //  yz_idx2 * rdx -> carry2:tmp
9084 
9085   movq(yz_idx1,  Address(z, idx, Address::times_4,  8));
9086   rorxq(yz_idx1, yz_idx1, 32);
9087   movq(yz_idx2, Address(z, idx, Address::times_4,  0));
9088   rorxq(yz_idx2, yz_idx2, 32);
9089 
9090   if (VM_Version::supports_adx()) {
9091     adcxq(tmp3, carry);
9092     adoxq(tmp3, yz_idx1);
9093 
9094     adcxq(tmp4, tmp);
9095     adoxq(tmp4, yz_idx2);
9096 
9097     movl(carry, 0); // does not affect flags
9098     adcxq(carry2, carry);
9099     adoxq(carry2, carry);
9100   } else {
9101     add2_with_carry(tmp4, tmp3, carry, yz_idx1);
9102     add2_with_carry(carry2, tmp4, tmp, yz_idx2);
9103   }
9104   movq(carry, carry2);
9105 
9106   movl(Address(z, idx, Address::times_4, 12), tmp3);
9107   shrq(tmp3, 32);
9108   movl(Address(z, idx, Address::times_4,  8), tmp3);
9109 
9110   movl(Address(z, idx, Address::times_4,  4), tmp4);
9111   shrq(tmp4, 32);
9112   movl(Address(z, idx, Address::times_4,  0), tmp4);
9113 
9114   jmp(L_third_loop);
9115 
9116   bind (L_third_loop_exit);
9117 
9118   andl (idx, 0x3);
9119   jcc(Assembler::zero, L_post_third_loop_done);
9120 
9121   Label L_check_1;
9122   subl(idx, 2);
9123   jcc(Assembler::negative, L_check_1);
9124 
9125   movq(yz_idx1, Address(y, idx, Address::times_4,  0));
9126   rorxq(yz_idx1, yz_idx1, 32);
9127   mulxq(tmp4, tmp3, yz_idx1); //  yz_idx1 * rdx -> tmp4:tmp3
9128   movq(yz_idx2, Address(z, idx, Address::times_4,  0));
9129   rorxq(yz_idx2, yz_idx2, 32);
9130 
9131   add2_with_carry(tmp4, tmp3, carry, yz_idx2);
9132 
9133   movl(Address(z, idx, Address::times_4,  4), tmp3);
9134   shrq(tmp3, 32);
9135   movl(Address(z, idx, Address::times_4,  0), tmp3);
9136   movq(carry, tmp4);
9137 
9138   bind (L_check_1);
9139   addl (idx, 0x2);
9140   andl (idx, 0x1);
9141   subl(idx, 1);
9142   jcc(Assembler::negative, L_post_third_loop_done);
9143   movl(tmp4, Address(y, idx, Address::times_4,  0));
9144   mulxq(carry2, tmp3, tmp4);  //  tmp4 * rdx -> carry2:tmp3
9145   movl(tmp4, Address(z, idx, Address::times_4,  0));
9146 
9147   add2_with_carry(carry2, tmp3, tmp4, carry);
9148 
9149   movl(Address(z, idx, Address::times_4,  0), tmp3);
9150   shrq(tmp3, 32);
9151 
9152   shlq(carry2, 32);
9153   orq(tmp3, carry2);
9154   movq(carry, tmp3);
9155 
9156   bind(L_post_third_loop_done);
9157 }
9158 
9159 /**
9160  * Code for BigInteger::multiplyToLen() instrinsic.
9161  *
9162  * rdi: x
9163  * rax: xlen
9164  * rsi: y
9165  * rcx: ylen
9166  * r8:  z
9167  * r11: zlen
9168  * r12: tmp1
9169  * r13: tmp2
9170  * r14: tmp3
9171  * r15: tmp4
9172  * rbx: tmp5
9173  *
9174  */
9175 void MacroAssembler::multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z, Register zlen,
9176                                      Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5) {
9177   ShortBranchVerifier sbv(this);
9178   assert_different_registers(x, xlen, y, ylen, z, zlen, tmp1, tmp2, tmp3, tmp4, tmp5, rdx);
9179 
9180   push(tmp1);
9181   push(tmp2);
9182   push(tmp3);
9183   push(tmp4);
9184   push(tmp5);
9185 
9186   push(xlen);
9187   push(zlen);
9188 
9189   const Register idx = tmp1;
9190   const Register kdx = tmp2;
9191   const Register xstart = tmp3;
9192 
9193   const Register y_idx = tmp4;
9194   const Register carry = tmp5;
9195   const Register product  = xlen;
9196   const Register x_xstart = zlen;  // reuse register
9197 
9198   // First Loop.
9199   //
9200   //  final static long LONG_MASK = 0xffffffffL;
9201   //  int xstart = xlen - 1;
9202   //  int ystart = ylen - 1;
9203   //  long carry = 0;
9204   //  for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
9205   //    long product = (y[idx] & LONG_MASK) * (x[xstart] & LONG_MASK) + carry;
9206   //    z[kdx] = (int)product;
9207   //    carry = product >>> 32;
9208   //  }
9209   //  z[xstart] = (int)carry;
9210   //
9211 
9212   movl(idx, ylen);      // idx = ylen;
9213   movl(kdx, zlen);      // kdx = xlen+ylen;
9214   xorq(carry, carry);   // carry = 0;
9215 
9216   Label L_done;
9217 
9218   movl(xstart, xlen);
9219   decrementl(xstart);
9220   jcc(Assembler::negative, L_done);
9221 
9222   multiply_64_x_64_loop(x, xstart, x_xstart, y, y_idx, z, carry, product, idx, kdx);
9223 
9224   Label L_second_loop;
9225   testl(kdx, kdx);
9226   jcc(Assembler::zero, L_second_loop);
9227 
9228   Label L_carry;
9229   subl(kdx, 1);
9230   jcc(Assembler::zero, L_carry);
9231 
9232   movl(Address(z, kdx, Address::times_4,  0), carry);
9233   shrq(carry, 32);
9234   subl(kdx, 1);
9235 
9236   bind(L_carry);
9237   movl(Address(z, kdx, Address::times_4,  0), carry);
9238 
9239   // Second and third (nested) loops.
9240   //
9241   // for (int i = xstart-1; i >= 0; i--) { // Second loop
9242   //   carry = 0;
9243   //   for (int jdx=ystart, k=ystart+1+i; jdx >= 0; jdx--, k--) { // Third loop
9244   //     long product = (y[jdx] & LONG_MASK) * (x[i] & LONG_MASK) +
9245   //                    (z[k] & LONG_MASK) + carry;
9246   //     z[k] = (int)product;
9247   //     carry = product >>> 32;
9248   //   }
9249   //   z[i] = (int)carry;
9250   // }
9251   //
9252   // i = xlen, j = tmp1, k = tmp2, carry = tmp5, x[i] = rdx
9253 
9254   const Register jdx = tmp1;
9255 
9256   bind(L_second_loop);
9257   xorl(carry, carry);    // carry = 0;
9258   movl(jdx, ylen);       // j = ystart+1
9259 
9260   subl(xstart, 1);       // i = xstart-1;
9261   jcc(Assembler::negative, L_done);
9262 
9263   push (z);
9264 
9265   Label L_last_x;
9266   lea(z, Address(z, xstart, Address::times_4, 4)); // z = z + k - j
9267   subl(xstart, 1);       // i = xstart-1;
9268   jcc(Assembler::negative, L_last_x);
9269 
9270   if (UseBMI2Instructions) {
9271     movq(rdx,  Address(x, xstart, Address::times_4,  0));
9272     rorxq(rdx, rdx, 32); // convert big-endian to little-endian
9273   } else {
9274     movq(x_xstart, Address(x, xstart, Address::times_4,  0));
9275     rorq(x_xstart, 32);  // convert big-endian to little-endian
9276   }
9277 
9278   Label L_third_loop_prologue;
9279   bind(L_third_loop_prologue);
9280 
9281   push (x);
9282   push (xstart);
9283   push (ylen);
9284 
9285 
9286   if (UseBMI2Instructions) {
9287     multiply_128_x_128_bmi2_loop(y, z, carry, x, jdx, ylen, product, tmp2, x_xstart, tmp3, tmp4);
9288   } else { // !UseBMI2Instructions
9289     multiply_128_x_128_loop(x_xstart, y, z, y_idx, jdx, ylen, carry, product, x);
9290   }
9291 
9292   pop(ylen);
9293   pop(xlen);
9294   pop(x);
9295   pop(z);
9296 
9297   movl(tmp3, xlen);
9298   addl(tmp3, 1);
9299   movl(Address(z, tmp3, Address::times_4,  0), carry);
9300   subl(tmp3, 1);
9301   jccb(Assembler::negative, L_done);
9302 
9303   shrq(carry, 32);
9304   movl(Address(z, tmp3, Address::times_4,  0), carry);
9305   jmp(L_second_loop);
9306 
9307   // Next infrequent code is moved outside loops.
9308   bind(L_last_x);
9309   if (UseBMI2Instructions) {
9310     movl(rdx, Address(x,  0));
9311   } else {
9312     movl(x_xstart, Address(x,  0));
9313   }
9314   jmp(L_third_loop_prologue);
9315 
9316   bind(L_done);
9317 
9318   pop(zlen);
9319   pop(xlen);
9320 
9321   pop(tmp5);
9322   pop(tmp4);
9323   pop(tmp3);
9324   pop(tmp2);
9325   pop(tmp1);
9326 }
9327 
9328 void MacroAssembler::vectorized_mismatch(Register obja, Register objb, Register length, Register log2_array_indxscale,
9329   Register result, Register tmp1, Register tmp2, XMMRegister rymm0, XMMRegister rymm1, XMMRegister rymm2){
9330   assert(UseSSE42Intrinsics, "SSE4.2 must be enabled.");
9331   Label VECTOR64_LOOP, VECTOR64_TAIL, VECTOR64_NOT_EQUAL, VECTOR32_TAIL;
9332   Label VECTOR32_LOOP, VECTOR16_LOOP, VECTOR8_LOOP, VECTOR4_LOOP;
9333   Label VECTOR16_TAIL, VECTOR8_TAIL, VECTOR4_TAIL;
9334   Label VECTOR32_NOT_EQUAL, VECTOR16_NOT_EQUAL, VECTOR8_NOT_EQUAL, VECTOR4_NOT_EQUAL;
9335   Label SAME_TILL_END, DONE;
9336   Label BYTES_LOOP, BYTES_TAIL, BYTES_NOT_EQUAL;
9337 
9338   //scale is in rcx in both Win64 and Unix
9339   ShortBranchVerifier sbv(this);
9340 
9341   shlq(length);
9342   xorq(result, result);
9343 
9344   if ((UseAVX > 2) &&
9345       VM_Version::supports_avx512vlbw()) {
9346     set_vector_masking();  // opening of the stub context for programming mask registers
9347     cmpq(length, 64);
9348     jcc(Assembler::less, VECTOR32_TAIL);
9349     movq(tmp1, length);
9350     andq(tmp1, 0x3F);      // tail count
9351     andq(length, ~(0x3F)); //vector count
9352 
9353     bind(VECTOR64_LOOP);
9354     // AVX512 code to compare 64 byte vectors.
9355     evmovdqub(rymm0, Address(obja, result), Assembler::AVX_512bit);
9356     evpcmpeqb(k7, rymm0, Address(objb, result), Assembler::AVX_512bit);
9357     kortestql(k7, k7);
9358     jcc(Assembler::aboveEqual, VECTOR64_NOT_EQUAL);     // mismatch
9359     addq(result, 64);
9360     subq(length, 64);
9361     jccb(Assembler::notZero, VECTOR64_LOOP);
9362 
9363     //bind(VECTOR64_TAIL);
9364     testq(tmp1, tmp1);
9365     jcc(Assembler::zero, SAME_TILL_END);
9366 
9367     bind(VECTOR64_TAIL);
9368     // AVX512 code to compare upto 63 byte vectors.
9369     // Save k1
9370     kmovql(k3, k1);
9371     mov64(tmp2, 0xFFFFFFFFFFFFFFFF);
9372     shlxq(tmp2, tmp2, tmp1);
9373     notq(tmp2);
9374     kmovql(k1, tmp2);
9375 
9376     evmovdqub(rymm0, k1, Address(obja, result), Assembler::AVX_512bit);
9377     evpcmpeqb(k7, k1, rymm0, Address(objb, result), Assembler::AVX_512bit);
9378 
9379     ktestql(k7, k1);
9380     // Restore k1
9381     kmovql(k1, k3);
9382     jcc(Assembler::below, SAME_TILL_END);     // not mismatch
9383 
9384     bind(VECTOR64_NOT_EQUAL);
9385     kmovql(tmp1, k7);
9386     notq(tmp1);
9387     tzcntq(tmp1, tmp1);
9388     addq(result, tmp1);
9389     shrq(result);
9390     jmp(DONE);
9391     bind(VECTOR32_TAIL);
9392     clear_vector_masking();   // closing of the stub context for programming mask registers
9393   }
9394 
9395   cmpq(length, 8);
9396   jcc(Assembler::equal, VECTOR8_LOOP);
9397   jcc(Assembler::less, VECTOR4_TAIL);
9398 
9399   if (UseAVX >= 2) {
9400 
9401     cmpq(length, 16);
9402     jcc(Assembler::equal, VECTOR16_LOOP);
9403     jcc(Assembler::less, VECTOR8_LOOP);
9404 
9405     cmpq(length, 32);
9406     jccb(Assembler::less, VECTOR16_TAIL);
9407 
9408     subq(length, 32);
9409     bind(VECTOR32_LOOP);
9410     vmovdqu(rymm0, Address(obja, result));
9411     vmovdqu(rymm1, Address(objb, result));
9412     vpxor(rymm2, rymm0, rymm1, Assembler::AVX_256bit);
9413     vptest(rymm2, rymm2);
9414     jcc(Assembler::notZero, VECTOR32_NOT_EQUAL);//mismatch found
9415     addq(result, 32);
9416     subq(length, 32);
9417     jccb(Assembler::greaterEqual, VECTOR32_LOOP);
9418     addq(length, 32);
9419     jcc(Assembler::equal, SAME_TILL_END);
9420     //falling through if less than 32 bytes left //close the branch here.
9421 
9422     bind(VECTOR16_TAIL);
9423     cmpq(length, 16);
9424     jccb(Assembler::less, VECTOR8_TAIL);
9425     bind(VECTOR16_LOOP);
9426     movdqu(rymm0, Address(obja, result));
9427     movdqu(rymm1, Address(objb, result));
9428     vpxor(rymm2, rymm0, rymm1, Assembler::AVX_128bit);
9429     ptest(rymm2, rymm2);
9430     jcc(Assembler::notZero, VECTOR16_NOT_EQUAL);//mismatch found
9431     addq(result, 16);
9432     subq(length, 16);
9433     jcc(Assembler::equal, SAME_TILL_END);
9434     //falling through if less than 16 bytes left
9435   } else {//regular intrinsics
9436 
9437     cmpq(length, 16);
9438     jccb(Assembler::less, VECTOR8_TAIL);
9439 
9440     subq(length, 16);
9441     bind(VECTOR16_LOOP);
9442     movdqu(rymm0, Address(obja, result));
9443     movdqu(rymm1, Address(objb, result));
9444     pxor(rymm0, rymm1);
9445     ptest(rymm0, rymm0);
9446     jcc(Assembler::notZero, VECTOR16_NOT_EQUAL);//mismatch found
9447     addq(result, 16);
9448     subq(length, 16);
9449     jccb(Assembler::greaterEqual, VECTOR16_LOOP);
9450     addq(length, 16);
9451     jcc(Assembler::equal, SAME_TILL_END);
9452     //falling through if less than 16 bytes left
9453   }
9454 
9455   bind(VECTOR8_TAIL);
9456   cmpq(length, 8);
9457   jccb(Assembler::less, VECTOR4_TAIL);
9458   bind(VECTOR8_LOOP);
9459   movq(tmp1, Address(obja, result));
9460   movq(tmp2, Address(objb, result));
9461   xorq(tmp1, tmp2);
9462   testq(tmp1, tmp1);
9463   jcc(Assembler::notZero, VECTOR8_NOT_EQUAL);//mismatch found
9464   addq(result, 8);
9465   subq(length, 8);
9466   jcc(Assembler::equal, SAME_TILL_END);
9467   //falling through if less than 8 bytes left
9468 
9469   bind(VECTOR4_TAIL);
9470   cmpq(length, 4);
9471   jccb(Assembler::less, BYTES_TAIL);
9472   bind(VECTOR4_LOOP);
9473   movl(tmp1, Address(obja, result));
9474   xorl(tmp1, Address(objb, result));
9475   testl(tmp1, tmp1);
9476   jcc(Assembler::notZero, VECTOR4_NOT_EQUAL);//mismatch found
9477   addq(result, 4);
9478   subq(length, 4);
9479   jcc(Assembler::equal, SAME_TILL_END);
9480   //falling through if less than 4 bytes left
9481 
9482   bind(BYTES_TAIL);
9483   bind(BYTES_LOOP);
9484   load_unsigned_byte(tmp1, Address(obja, result));
9485   load_unsigned_byte(tmp2, Address(objb, result));
9486   xorl(tmp1, tmp2);
9487   testl(tmp1, tmp1);
9488   jccb(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found
9489   decq(length);
9490   jccb(Assembler::zero, SAME_TILL_END);
9491   incq(result);
9492   load_unsigned_byte(tmp1, Address(obja, result));
9493   load_unsigned_byte(tmp2, Address(objb, result));
9494   xorl(tmp1, tmp2);
9495   testl(tmp1, tmp1);
9496   jccb(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found
9497   decq(length);
9498   jccb(Assembler::zero, SAME_TILL_END);
9499   incq(result);
9500   load_unsigned_byte(tmp1, Address(obja, result));
9501   load_unsigned_byte(tmp2, Address(objb, result));
9502   xorl(tmp1, tmp2);
9503   testl(tmp1, tmp1);
9504   jccb(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found
9505   jmpb(SAME_TILL_END);
9506 
9507   if (UseAVX >= 2) {
9508     bind(VECTOR32_NOT_EQUAL);
9509     vpcmpeqb(rymm2, rymm2, rymm2, Assembler::AVX_256bit);
9510     vpcmpeqb(rymm0, rymm0, rymm1, Assembler::AVX_256bit);
9511     vpxor(rymm0, rymm0, rymm2, Assembler::AVX_256bit);
9512     vpmovmskb(tmp1, rymm0);
9513     bsfq(tmp1, tmp1);
9514     addq(result, tmp1);
9515     shrq(result);
9516     jmpb(DONE);
9517   }
9518 
9519   bind(VECTOR16_NOT_EQUAL);
9520   if (UseAVX >= 2) {
9521     vpcmpeqb(rymm2, rymm2, rymm2, Assembler::AVX_128bit);
9522     vpcmpeqb(rymm0, rymm0, rymm1, Assembler::AVX_128bit);
9523     pxor(rymm0, rymm2);
9524   } else {
9525     pcmpeqb(rymm2, rymm2);
9526     pxor(rymm0, rymm1);
9527     pcmpeqb(rymm0, rymm1);
9528     pxor(rymm0, rymm2);
9529   }
9530   pmovmskb(tmp1, rymm0);
9531   bsfq(tmp1, tmp1);
9532   addq(result, tmp1);
9533   shrq(result);
9534   jmpb(DONE);
9535 
9536   bind(VECTOR8_NOT_EQUAL);
9537   bind(VECTOR4_NOT_EQUAL);
9538   bsfq(tmp1, tmp1);
9539   shrq(tmp1, 3);
9540   addq(result, tmp1);
9541   bind(BYTES_NOT_EQUAL);
9542   shrq(result);
9543   jmpb(DONE);
9544 
9545   bind(SAME_TILL_END);
9546   mov64(result, -1);
9547 
9548   bind(DONE);
9549 }
9550 
9551 //Helper functions for square_to_len()
9552 
9553 /**
9554  * Store the squares of x[], right shifted one bit (divided by 2) into z[]
9555  * Preserves x and z and modifies rest of the registers.
9556  */
9557 void MacroAssembler::square_rshift(Register x, Register xlen, Register z, Register tmp1, Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
9558   // Perform square and right shift by 1
9559   // Handle odd xlen case first, then for even xlen do the following
9560   // jlong carry = 0;
9561   // for (int j=0, i=0; j < xlen; j+=2, i+=4) {
9562   //     huge_128 product = x[j:j+1] * x[j:j+1];
9563   //     z[i:i+1] = (carry << 63) | (jlong)(product >>> 65);
9564   //     z[i+2:i+3] = (jlong)(product >>> 1);
9565   //     carry = (jlong)product;
9566   // }
9567 
9568   xorq(tmp5, tmp5);     // carry
9569   xorq(rdxReg, rdxReg);
9570   xorl(tmp1, tmp1);     // index for x
9571   xorl(tmp4, tmp4);     // index for z
9572 
9573   Label L_first_loop, L_first_loop_exit;
9574 
9575   testl(xlen, 1);
9576   jccb(Assembler::zero, L_first_loop); //jump if xlen is even
9577 
9578   // Square and right shift by 1 the odd element using 32 bit multiply
9579   movl(raxReg, Address(x, tmp1, Address::times_4, 0));
9580   imulq(raxReg, raxReg);
9581   shrq(raxReg, 1);
9582   adcq(tmp5, 0);
9583   movq(Address(z, tmp4, Address::times_4, 0), raxReg);
9584   incrementl(tmp1);
9585   addl(tmp4, 2);
9586 
9587   // Square and  right shift by 1 the rest using 64 bit multiply
9588   bind(L_first_loop);
9589   cmpptr(tmp1, xlen);
9590   jccb(Assembler::equal, L_first_loop_exit);
9591 
9592   // Square
9593   movq(raxReg, Address(x, tmp1, Address::times_4,  0));
9594   rorq(raxReg, 32);    // convert big-endian to little-endian
9595   mulq(raxReg);        // 64-bit multiply rax * rax -> rdx:rax
9596 
9597   // Right shift by 1 and save carry
9598   shrq(tmp5, 1);       // rdx:rax:tmp5 = (tmp5:rdx:rax) >>> 1
9599   rcrq(rdxReg, 1);
9600   rcrq(raxReg, 1);
9601   adcq(tmp5, 0);
9602 
9603   // Store result in z
9604   movq(Address(z, tmp4, Address::times_4, 0), rdxReg);
9605   movq(Address(z, tmp4, Address::times_4, 8), raxReg);
9606 
9607   // Update indices for x and z
9608   addl(tmp1, 2);
9609   addl(tmp4, 4);
9610   jmp(L_first_loop);
9611 
9612   bind(L_first_loop_exit);
9613 }
9614 
9615 
9616 /**
9617  * Perform the following multiply add operation using BMI2 instructions
9618  * carry:sum = sum + op1*op2 + carry
9619  * op2 should be in rdx
9620  * op2 is preserved, all other registers are modified
9621  */
9622 void MacroAssembler::multiply_add_64_bmi2(Register sum, Register op1, Register op2, Register carry, Register tmp2) {
9623   // assert op2 is rdx
9624   mulxq(tmp2, op1, op1);  //  op1 * op2 -> tmp2:op1
9625   addq(sum, carry);
9626   adcq(tmp2, 0);
9627   addq(sum, op1);
9628   adcq(tmp2, 0);
9629   movq(carry, tmp2);
9630 }
9631 
9632 /**
9633  * Perform the following multiply add operation:
9634  * carry:sum = sum + op1*op2 + carry
9635  * Preserves op1, op2 and modifies rest of registers
9636  */
9637 void MacroAssembler::multiply_add_64(Register sum, Register op1, Register op2, Register carry, Register rdxReg, Register raxReg) {
9638   // rdx:rax = op1 * op2
9639   movq(raxReg, op2);
9640   mulq(op1);
9641 
9642   //  rdx:rax = sum + carry + rdx:rax
9643   addq(sum, carry);
9644   adcq(rdxReg, 0);
9645   addq(sum, raxReg);
9646   adcq(rdxReg, 0);
9647 
9648   // carry:sum = rdx:sum
9649   movq(carry, rdxReg);
9650 }
9651 
9652 /**
9653  * Add 64 bit long carry into z[] with carry propogation.
9654  * Preserves z and carry register values and modifies rest of registers.
9655  *
9656  */
9657 void MacroAssembler::add_one_64(Register z, Register zlen, Register carry, Register tmp1) {
9658   Label L_fourth_loop, L_fourth_loop_exit;
9659 
9660   movl(tmp1, 1);
9661   subl(zlen, 2);
9662   addq(Address(z, zlen, Address::times_4, 0), carry);
9663 
9664   bind(L_fourth_loop);
9665   jccb(Assembler::carryClear, L_fourth_loop_exit);
9666   subl(zlen, 2);
9667   jccb(Assembler::negative, L_fourth_loop_exit);
9668   addq(Address(z, zlen, Address::times_4, 0), tmp1);
9669   jmp(L_fourth_loop);
9670   bind(L_fourth_loop_exit);
9671 }
9672 
9673 /**
9674  * Shift z[] left by 1 bit.
9675  * Preserves x, len, z and zlen registers and modifies rest of the registers.
9676  *
9677  */
9678 void MacroAssembler::lshift_by_1(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2, Register tmp3, Register tmp4) {
9679 
9680   Label L_fifth_loop, L_fifth_loop_exit;
9681 
9682   // Fifth loop
9683   // Perform primitiveLeftShift(z, zlen, 1)
9684 
9685   const Register prev_carry = tmp1;
9686   const Register new_carry = tmp4;
9687   const Register value = tmp2;
9688   const Register zidx = tmp3;
9689 
9690   // int zidx, carry;
9691   // long value;
9692   // carry = 0;
9693   // for (zidx = zlen-2; zidx >=0; zidx -= 2) {
9694   //    (carry:value)  = (z[i] << 1) | carry ;
9695   //    z[i] = value;
9696   // }
9697 
9698   movl(zidx, zlen);
9699   xorl(prev_carry, prev_carry); // clear carry flag and prev_carry register
9700 
9701   bind(L_fifth_loop);
9702   decl(zidx);  // Use decl to preserve carry flag
9703   decl(zidx);
9704   jccb(Assembler::negative, L_fifth_loop_exit);
9705 
9706   if (UseBMI2Instructions) {
9707      movq(value, Address(z, zidx, Address::times_4, 0));
9708      rclq(value, 1);
9709      rorxq(value, value, 32);
9710      movq(Address(z, zidx, Address::times_4,  0), value);  // Store back in big endian form
9711   }
9712   else {
9713     // clear new_carry
9714     xorl(new_carry, new_carry);
9715 
9716     // Shift z[i] by 1, or in previous carry and save new carry
9717     movq(value, Address(z, zidx, Address::times_4, 0));
9718     shlq(value, 1);
9719     adcl(new_carry, 0);
9720 
9721     orq(value, prev_carry);
9722     rorq(value, 0x20);
9723     movq(Address(z, zidx, Address::times_4,  0), value);  // Store back in big endian form
9724 
9725     // Set previous carry = new carry
9726     movl(prev_carry, new_carry);
9727   }
9728   jmp(L_fifth_loop);
9729 
9730   bind(L_fifth_loop_exit);
9731 }
9732 
9733 
9734 /**
9735  * Code for BigInteger::squareToLen() intrinsic
9736  *
9737  * rdi: x
9738  * rsi: len
9739  * r8:  z
9740  * rcx: zlen
9741  * r12: tmp1
9742  * r13: tmp2
9743  * r14: tmp3
9744  * r15: tmp4
9745  * rbx: tmp5
9746  *
9747  */
9748 void MacroAssembler::square_to_len(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
9749 
9750   Label L_second_loop, L_second_loop_exit, L_third_loop, L_third_loop_exit, fifth_loop, fifth_loop_exit, L_last_x, L_multiply;
9751   push(tmp1);
9752   push(tmp2);
9753   push(tmp3);
9754   push(tmp4);
9755   push(tmp5);
9756 
9757   // First loop
9758   // Store the squares, right shifted one bit (i.e., divided by 2).
9759   square_rshift(x, len, z, tmp1, tmp3, tmp4, tmp5, rdxReg, raxReg);
9760 
9761   // Add in off-diagonal sums.
9762   //
9763   // Second, third (nested) and fourth loops.
9764   // zlen +=2;
9765   // for (int xidx=len-2,zidx=zlen-4; xidx > 0; xidx-=2,zidx-=4) {
9766   //    carry = 0;
9767   //    long op2 = x[xidx:xidx+1];
9768   //    for (int j=xidx-2,k=zidx; j >= 0; j-=2) {
9769   //       k -= 2;
9770   //       long op1 = x[j:j+1];
9771   //       long sum = z[k:k+1];
9772   //       carry:sum = multiply_add_64(sum, op1, op2, carry, tmp_regs);
9773   //       z[k:k+1] = sum;
9774   //    }
9775   //    add_one_64(z, k, carry, tmp_regs);
9776   // }
9777 
9778   const Register carry = tmp5;
9779   const Register sum = tmp3;
9780   const Register op1 = tmp4;
9781   Register op2 = tmp2;
9782 
9783   push(zlen);
9784   push(len);
9785   addl(zlen,2);
9786   bind(L_second_loop);
9787   xorq(carry, carry);
9788   subl(zlen, 4);
9789   subl(len, 2);
9790   push(zlen);
9791   push(len);
9792   cmpl(len, 0);
9793   jccb(Assembler::lessEqual, L_second_loop_exit);
9794 
9795   // Multiply an array by one 64 bit long.
9796   if (UseBMI2Instructions) {
9797     op2 = rdxReg;
9798     movq(op2, Address(x, len, Address::times_4,  0));
9799     rorxq(op2, op2, 32);
9800   }
9801   else {
9802     movq(op2, Address(x, len, Address::times_4,  0));
9803     rorq(op2, 32);
9804   }
9805 
9806   bind(L_third_loop);
9807   decrementl(len);
9808   jccb(Assembler::negative, L_third_loop_exit);
9809   decrementl(len);
9810   jccb(Assembler::negative, L_last_x);
9811 
9812   movq(op1, Address(x, len, Address::times_4,  0));
9813   rorq(op1, 32);
9814 
9815   bind(L_multiply);
9816   subl(zlen, 2);
9817   movq(sum, Address(z, zlen, Address::times_4,  0));
9818 
9819   // Multiply 64 bit by 64 bit and add 64 bits lower half and upper 64 bits as carry.
9820   if (UseBMI2Instructions) {
9821     multiply_add_64_bmi2(sum, op1, op2, carry, tmp2);
9822   }
9823   else {
9824     multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
9825   }
9826 
9827   movq(Address(z, zlen, Address::times_4, 0), sum);
9828 
9829   jmp(L_third_loop);
9830   bind(L_third_loop_exit);
9831 
9832   // Fourth loop
9833   // Add 64 bit long carry into z with carry propogation.
9834   // Uses offsetted zlen.
9835   add_one_64(z, zlen, carry, tmp1);
9836 
9837   pop(len);
9838   pop(zlen);
9839   jmp(L_second_loop);
9840 
9841   // Next infrequent code is moved outside loops.
9842   bind(L_last_x);
9843   movl(op1, Address(x, 0));
9844   jmp(L_multiply);
9845 
9846   bind(L_second_loop_exit);
9847   pop(len);
9848   pop(zlen);
9849   pop(len);
9850   pop(zlen);
9851 
9852   // Fifth loop
9853   // Shift z left 1 bit.
9854   lshift_by_1(x, len, z, zlen, tmp1, tmp2, tmp3, tmp4);
9855 
9856   // z[zlen-1] |= x[len-1] & 1;
9857   movl(tmp3, Address(x, len, Address::times_4, -4));
9858   andl(tmp3, 1);
9859   orl(Address(z, zlen, Address::times_4,  -4), tmp3);
9860 
9861   pop(tmp5);
9862   pop(tmp4);
9863   pop(tmp3);
9864   pop(tmp2);
9865   pop(tmp1);
9866 }
9867 
9868 /**
9869  * Helper function for mul_add()
9870  * Multiply the in[] by int k and add to out[] starting at offset offs using
9871  * 128 bit by 32 bit multiply and return the carry in tmp5.
9872  * Only quad int aligned length of in[] is operated on in this function.
9873  * k is in rdxReg for BMI2Instructions, for others it is in tmp2.
9874  * This function preserves out, in and k registers.
9875  * len and offset point to the appropriate index in "in" & "out" correspondingly
9876  * tmp5 has the carry.
9877  * other registers are temporary and are modified.
9878  *
9879  */
9880 void MacroAssembler::mul_add_128_x_32_loop(Register out, Register in,
9881   Register offset, Register len, Register tmp1, Register tmp2, Register tmp3,
9882   Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
9883 
9884   Label L_first_loop, L_first_loop_exit;
9885 
9886   movl(tmp1, len);
9887   shrl(tmp1, 2);
9888 
9889   bind(L_first_loop);
9890   subl(tmp1, 1);
9891   jccb(Assembler::negative, L_first_loop_exit);
9892 
9893   subl(len, 4);
9894   subl(offset, 4);
9895 
9896   Register op2 = tmp2;
9897   const Register sum = tmp3;
9898   const Register op1 = tmp4;
9899   const Register carry = tmp5;
9900 
9901   if (UseBMI2Instructions) {
9902     op2 = rdxReg;
9903   }
9904 
9905   movq(op1, Address(in, len, Address::times_4,  8));
9906   rorq(op1, 32);
9907   movq(sum, Address(out, offset, Address::times_4,  8));
9908   rorq(sum, 32);
9909   if (UseBMI2Instructions) {
9910     multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
9911   }
9912   else {
9913     multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
9914   }
9915   // Store back in big endian from little endian
9916   rorq(sum, 0x20);
9917   movq(Address(out, offset, Address::times_4,  8), sum);
9918 
9919   movq(op1, Address(in, len, Address::times_4,  0));
9920   rorq(op1, 32);
9921   movq(sum, Address(out, offset, Address::times_4,  0));
9922   rorq(sum, 32);
9923   if (UseBMI2Instructions) {
9924     multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
9925   }
9926   else {
9927     multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
9928   }
9929   // Store back in big endian from little endian
9930   rorq(sum, 0x20);
9931   movq(Address(out, offset, Address::times_4,  0), sum);
9932 
9933   jmp(L_first_loop);
9934   bind(L_first_loop_exit);
9935 }
9936 
9937 /**
9938  * Code for BigInteger::mulAdd() intrinsic
9939  *
9940  * rdi: out
9941  * rsi: in
9942  * r11: offs (out.length - offset)
9943  * rcx: len
9944  * r8:  k
9945  * r12: tmp1
9946  * r13: tmp2
9947  * r14: tmp3
9948  * r15: tmp4
9949  * rbx: tmp5
9950  * Multiply the in[] by word k and add to out[], return the carry in rax
9951  */
9952 void MacroAssembler::mul_add(Register out, Register in, Register offs,
9953    Register len, Register k, Register tmp1, Register tmp2, Register tmp3,
9954    Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
9955 
9956   Label L_carry, L_last_in, L_done;
9957 
9958 // carry = 0;
9959 // for (int j=len-1; j >= 0; j--) {
9960 //    long product = (in[j] & LONG_MASK) * kLong +
9961 //                   (out[offs] & LONG_MASK) + carry;
9962 //    out[offs--] = (int)product;
9963 //    carry = product >>> 32;
9964 // }
9965 //
9966   push(tmp1);
9967   push(tmp2);
9968   push(tmp3);
9969   push(tmp4);
9970   push(tmp5);
9971 
9972   Register op2 = tmp2;
9973   const Register sum = tmp3;
9974   const Register op1 = tmp4;
9975   const Register carry =  tmp5;
9976 
9977   if (UseBMI2Instructions) {
9978     op2 = rdxReg;
9979     movl(op2, k);
9980   }
9981   else {
9982     movl(op2, k);
9983   }
9984 
9985   xorq(carry, carry);
9986 
9987   //First loop
9988 
9989   //Multiply in[] by k in a 4 way unrolled loop using 128 bit by 32 bit multiply
9990   //The carry is in tmp5
9991   mul_add_128_x_32_loop(out, in, offs, len, tmp1, tmp2, tmp3, tmp4, tmp5, rdxReg, raxReg);
9992 
9993   //Multiply the trailing in[] entry using 64 bit by 32 bit, if any
9994   decrementl(len);
9995   jccb(Assembler::negative, L_carry);
9996   decrementl(len);
9997   jccb(Assembler::negative, L_last_in);
9998 
9999   movq(op1, Address(in, len, Address::times_4,  0));
10000   rorq(op1, 32);
10001 
10002   subl(offs, 2);
10003   movq(sum, Address(out, offs, Address::times_4,  0));
10004   rorq(sum, 32);
10005 
10006   if (UseBMI2Instructions) {
10007     multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
10008   }
10009   else {
10010     multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
10011   }
10012 
10013   // Store back in big endian from little endian
10014   rorq(sum, 0x20);
10015   movq(Address(out, offs, Address::times_4,  0), sum);
10016 
10017   testl(len, len);
10018   jccb(Assembler::zero, L_carry);
10019 
10020   //Multiply the last in[] entry, if any
10021   bind(L_last_in);
10022   movl(op1, Address(in, 0));
10023   movl(sum, Address(out, offs, Address::times_4,  -4));
10024 
10025   movl(raxReg, k);
10026   mull(op1); //tmp4 * eax -> edx:eax
10027   addl(sum, carry);
10028   adcl(rdxReg, 0);
10029   addl(sum, raxReg);
10030   adcl(rdxReg, 0);
10031   movl(carry, rdxReg);
10032 
10033   movl(Address(out, offs, Address::times_4,  -4), sum);
10034 
10035   bind(L_carry);
10036   //return tmp5/carry as carry in rax
10037   movl(rax, carry);
10038 
10039   bind(L_done);
10040   pop(tmp5);
10041   pop(tmp4);
10042   pop(tmp3);
10043   pop(tmp2);
10044   pop(tmp1);
10045 }
10046 #endif
10047 
10048 /**
10049  * Emits code to update CRC-32 with a byte value according to constants in table
10050  *
10051  * @param [in,out]crc   Register containing the crc.
10052  * @param [in]val       Register containing the byte to fold into the CRC.
10053  * @param [in]table     Register containing the table of crc constants.
10054  *
10055  * uint32_t crc;
10056  * val = crc_table[(val ^ crc) & 0xFF];
10057  * crc = val ^ (crc >> 8);
10058  *
10059  */
10060 void MacroAssembler::update_byte_crc32(Register crc, Register val, Register table) {
10061   xorl(val, crc);
10062   andl(val, 0xFF);
10063   shrl(crc, 8); // unsigned shift
10064   xorl(crc, Address(table, val, Address::times_4, 0));
10065 }
10066 
10067 /**
10068  * Fold 128-bit data chunk
10069  */
10070 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset) {
10071   if (UseAVX > 0) {
10072     vpclmulhdq(xtmp, xK, xcrc); // [123:64]
10073     vpclmulldq(xcrc, xK, xcrc); // [63:0]
10074     vpxor(xcrc, xcrc, Address(buf, offset), 0 /* vector_len */);
10075     pxor(xcrc, xtmp);
10076   } else {
10077     movdqa(xtmp, xcrc);
10078     pclmulhdq(xtmp, xK);   // [123:64]
10079     pclmulldq(xcrc, xK);   // [63:0]
10080     pxor(xcrc, xtmp);
10081     movdqu(xtmp, Address(buf, offset));
10082     pxor(xcrc, xtmp);
10083   }
10084 }
10085 
10086 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, XMMRegister xbuf) {
10087   if (UseAVX > 0) {
10088     vpclmulhdq(xtmp, xK, xcrc);
10089     vpclmulldq(xcrc, xK, xcrc);
10090     pxor(xcrc, xbuf);
10091     pxor(xcrc, xtmp);
10092   } else {
10093     movdqa(xtmp, xcrc);
10094     pclmulhdq(xtmp, xK);
10095     pclmulldq(xcrc, xK);
10096     pxor(xcrc, xbuf);
10097     pxor(xcrc, xtmp);
10098   }
10099 }
10100 
10101 /**
10102  * 8-bit folds to compute 32-bit CRC
10103  *
10104  * uint64_t xcrc;
10105  * timesXtoThe32[xcrc & 0xFF] ^ (xcrc >> 8);
10106  */
10107 void MacroAssembler::fold_8bit_crc32(XMMRegister xcrc, Register table, XMMRegister xtmp, Register tmp) {
10108   movdl(tmp, xcrc);
10109   andl(tmp, 0xFF);
10110   movdl(xtmp, Address(table, tmp, Address::times_4, 0));
10111   psrldq(xcrc, 1); // unsigned shift one byte
10112   pxor(xcrc, xtmp);
10113 }
10114 
10115 /**
10116  * uint32_t crc;
10117  * timesXtoThe32[crc & 0xFF] ^ (crc >> 8);
10118  */
10119 void MacroAssembler::fold_8bit_crc32(Register crc, Register table, Register tmp) {
10120   movl(tmp, crc);
10121   andl(tmp, 0xFF);
10122   shrl(crc, 8);
10123   xorl(crc, Address(table, tmp, Address::times_4, 0));
10124 }
10125 
10126 /**
10127  * @param crc   register containing existing CRC (32-bit)
10128  * @param buf   register pointing to input byte buffer (byte*)
10129  * @param len   register containing number of bytes
10130  * @param table register that will contain address of CRC table
10131  * @param tmp   scratch register
10132  */
10133 void MacroAssembler::kernel_crc32(Register crc, Register buf, Register len, Register table, Register tmp) {
10134   assert_different_registers(crc, buf, len, table, tmp, rax);
10135 
10136   Label L_tail, L_tail_restore, L_tail_loop, L_exit, L_align_loop, L_aligned;
10137   Label L_fold_tail, L_fold_128b, L_fold_512b, L_fold_512b_loop, L_fold_tail_loop;
10138 
10139   // For EVEX with VL and BW, provide a standard mask, VL = 128 will guide the merge
10140   // context for the registers used, where all instructions below are using 128-bit mode
10141   // On EVEX without VL and BW, these instructions will all be AVX.
10142   if (VM_Version::supports_avx512vlbw()) {
10143     movl(tmp, 0xffff);
10144     kmovwl(k1, tmp);
10145   }
10146 
10147   lea(table, ExternalAddress(StubRoutines::crc_table_addr()));
10148   notl(crc); // ~crc
10149   cmpl(len, 16);
10150   jcc(Assembler::less, L_tail);
10151 
10152   // Align buffer to 16 bytes
10153   movl(tmp, buf);
10154   andl(tmp, 0xF);
10155   jccb(Assembler::zero, L_aligned);
10156   subl(tmp,  16);
10157   addl(len, tmp);
10158 
10159   align(4);
10160   BIND(L_align_loop);
10161   movsbl(rax, Address(buf, 0)); // load byte with sign extension
10162   update_byte_crc32(crc, rax, table);
10163   increment(buf);
10164   incrementl(tmp);
10165   jccb(Assembler::less, L_align_loop);
10166 
10167   BIND(L_aligned);
10168   movl(tmp, len); // save
10169   shrl(len, 4);
10170   jcc(Assembler::zero, L_tail_restore);
10171 
10172   // Fold crc into first bytes of vector
10173   movdqa(xmm1, Address(buf, 0));
10174   movdl(rax, xmm1);
10175   xorl(crc, rax);
10176   if (VM_Version::supports_sse4_1()) {
10177     pinsrd(xmm1, crc, 0);
10178   } else {
10179     pinsrw(xmm1, crc, 0);
10180     shrl(crc, 16);
10181     pinsrw(xmm1, crc, 1);
10182   }
10183   addptr(buf, 16);
10184   subl(len, 4); // len > 0
10185   jcc(Assembler::less, L_fold_tail);
10186 
10187   movdqa(xmm2, Address(buf,  0));
10188   movdqa(xmm3, Address(buf, 16));
10189   movdqa(xmm4, Address(buf, 32));
10190   addptr(buf, 48);
10191   subl(len, 3);
10192   jcc(Assembler::lessEqual, L_fold_512b);
10193 
10194   // Fold total 512 bits of polynomial on each iteration,
10195   // 128 bits per each of 4 parallel streams.
10196   movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 32));
10197 
10198   align(32);
10199   BIND(L_fold_512b_loop);
10200   fold_128bit_crc32(xmm1, xmm0, xmm5, buf,  0);
10201   fold_128bit_crc32(xmm2, xmm0, xmm5, buf, 16);
10202   fold_128bit_crc32(xmm3, xmm0, xmm5, buf, 32);
10203   fold_128bit_crc32(xmm4, xmm0, xmm5, buf, 48);
10204   addptr(buf, 64);
10205   subl(len, 4);
10206   jcc(Assembler::greater, L_fold_512b_loop);
10207 
10208   // Fold 512 bits to 128 bits.
10209   BIND(L_fold_512b);
10210   movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16));
10211   fold_128bit_crc32(xmm1, xmm0, xmm5, xmm2);
10212   fold_128bit_crc32(xmm1, xmm0, xmm5, xmm3);
10213   fold_128bit_crc32(xmm1, xmm0, xmm5, xmm4);
10214 
10215   // Fold the rest of 128 bits data chunks
10216   BIND(L_fold_tail);
10217   addl(len, 3);
10218   jccb(Assembler::lessEqual, L_fold_128b);
10219   movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16));
10220 
10221   BIND(L_fold_tail_loop);
10222   fold_128bit_crc32(xmm1, xmm0, xmm5, buf,  0);
10223   addptr(buf, 16);
10224   decrementl(len);
10225   jccb(Assembler::greater, L_fold_tail_loop);
10226 
10227   // Fold 128 bits in xmm1 down into 32 bits in crc register.
10228   BIND(L_fold_128b);
10229   movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr()));
10230   if (UseAVX > 0) {
10231     vpclmulqdq(xmm2, xmm0, xmm1, 0x1);
10232     vpand(xmm3, xmm0, xmm2, 0 /* vector_len */);
10233     vpclmulqdq(xmm0, xmm0, xmm3, 0x1);
10234   } else {
10235     movdqa(xmm2, xmm0);
10236     pclmulqdq(xmm2, xmm1, 0x1);
10237     movdqa(xmm3, xmm0);
10238     pand(xmm3, xmm2);
10239     pclmulqdq(xmm0, xmm3, 0x1);
10240   }
10241   psrldq(xmm1, 8);
10242   psrldq(xmm2, 4);
10243   pxor(xmm0, xmm1);
10244   pxor(xmm0, xmm2);
10245 
10246   // 8 8-bit folds to compute 32-bit CRC.
10247   for (int j = 0; j < 4; j++) {
10248     fold_8bit_crc32(xmm0, table, xmm1, rax);
10249   }
10250   movdl(crc, xmm0); // mov 32 bits to general register
10251   for (int j = 0; j < 4; j++) {
10252     fold_8bit_crc32(crc, table, rax);
10253   }
10254 
10255   BIND(L_tail_restore);
10256   movl(len, tmp); // restore
10257   BIND(L_tail);
10258   andl(len, 0xf);
10259   jccb(Assembler::zero, L_exit);
10260 
10261   // Fold the rest of bytes
10262   align(4);
10263   BIND(L_tail_loop);
10264   movsbl(rax, Address(buf, 0)); // load byte with sign extension
10265   update_byte_crc32(crc, rax, table);
10266   increment(buf);
10267   decrementl(len);
10268   jccb(Assembler::greater, L_tail_loop);
10269 
10270   BIND(L_exit);
10271   notl(crc); // ~c
10272 }
10273 
10274 #ifdef _LP64
10275 // S. Gueron / Information Processing Letters 112 (2012) 184
10276 // Algorithm 4: Computing carry-less multiplication using a precomputed lookup table.
10277 // Input: A 32 bit value B = [byte3, byte2, byte1, byte0].
10278 // Output: the 64-bit carry-less product of B * CONST
10279 void MacroAssembler::crc32c_ipl_alg4(Register in, uint32_t n,
10280                                      Register tmp1, Register tmp2, Register tmp3) {
10281   lea(tmp3, ExternalAddress(StubRoutines::crc32c_table_addr()));
10282   if (n > 0) {
10283     addq(tmp3, n * 256 * 8);
10284   }
10285   //    Q1 = TABLEExt[n][B & 0xFF];
10286   movl(tmp1, in);
10287   andl(tmp1, 0x000000FF);
10288   shll(tmp1, 3);
10289   addq(tmp1, tmp3);
10290   movq(tmp1, Address(tmp1, 0));
10291 
10292   //    Q2 = TABLEExt[n][B >> 8 & 0xFF];
10293   movl(tmp2, in);
10294   shrl(tmp2, 8);
10295   andl(tmp2, 0x000000FF);
10296   shll(tmp2, 3);
10297   addq(tmp2, tmp3);
10298   movq(tmp2, Address(tmp2, 0));
10299 
10300   shlq(tmp2, 8);
10301   xorq(tmp1, tmp2);
10302 
10303   //    Q3 = TABLEExt[n][B >> 16 & 0xFF];
10304   movl(tmp2, in);
10305   shrl(tmp2, 16);
10306   andl(tmp2, 0x000000FF);
10307   shll(tmp2, 3);
10308   addq(tmp2, tmp3);
10309   movq(tmp2, Address(tmp2, 0));
10310 
10311   shlq(tmp2, 16);
10312   xorq(tmp1, tmp2);
10313 
10314   //    Q4 = TABLEExt[n][B >> 24 & 0xFF];
10315   shrl(in, 24);
10316   andl(in, 0x000000FF);
10317   shll(in, 3);
10318   addq(in, tmp3);
10319   movq(in, Address(in, 0));
10320 
10321   shlq(in, 24);
10322   xorq(in, tmp1);
10323   //    return Q1 ^ Q2 << 8 ^ Q3 << 16 ^ Q4 << 24;
10324 }
10325 
10326 void MacroAssembler::crc32c_pclmulqdq(XMMRegister w_xtmp1,
10327                                       Register in_out,
10328                                       uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported,
10329                                       XMMRegister w_xtmp2,
10330                                       Register tmp1,
10331                                       Register n_tmp2, Register n_tmp3) {
10332   if (is_pclmulqdq_supported) {
10333     movdl(w_xtmp1, in_out); // modified blindly
10334 
10335     movl(tmp1, const_or_pre_comp_const_index);
10336     movdl(w_xtmp2, tmp1);
10337     pclmulqdq(w_xtmp1, w_xtmp2, 0);
10338 
10339     movdq(in_out, w_xtmp1);
10340   } else {
10341     crc32c_ipl_alg4(in_out, const_or_pre_comp_const_index, tmp1, n_tmp2, n_tmp3);
10342   }
10343 }
10344 
10345 // Recombination Alternative 2: No bit-reflections
10346 // T1 = (CRC_A * U1) << 1
10347 // T2 = (CRC_B * U2) << 1
10348 // C1 = T1 >> 32
10349 // C2 = T2 >> 32
10350 // T1 = T1 & 0xFFFFFFFF
10351 // T2 = T2 & 0xFFFFFFFF
10352 // T1 = CRC32(0, T1)
10353 // T2 = CRC32(0, T2)
10354 // C1 = C1 ^ T1
10355 // C2 = C2 ^ T2
10356 // CRC = C1 ^ C2 ^ CRC_C
10357 void MacroAssembler::crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2,
10358                                      XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
10359                                      Register tmp1, Register tmp2,
10360                                      Register n_tmp3) {
10361   crc32c_pclmulqdq(w_xtmp1, in_out, const_or_pre_comp_const_index_u1, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
10362   crc32c_pclmulqdq(w_xtmp2, in1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
10363   shlq(in_out, 1);
10364   movl(tmp1, in_out);
10365   shrq(in_out, 32);
10366   xorl(tmp2, tmp2);
10367   crc32(tmp2, tmp1, 4);
10368   xorl(in_out, tmp2); // we don't care about upper 32 bit contents here
10369   shlq(in1, 1);
10370   movl(tmp1, in1);
10371   shrq(in1, 32);
10372   xorl(tmp2, tmp2);
10373   crc32(tmp2, tmp1, 4);
10374   xorl(in1, tmp2);
10375   xorl(in_out, in1);
10376   xorl(in_out, in2);
10377 }
10378 
10379 // Set N to predefined value
10380 // Subtract from a lenght of a buffer
10381 // execute in a loop:
10382 // CRC_A = 0xFFFFFFFF, CRC_B = 0, CRC_C = 0
10383 // for i = 1 to N do
10384 //  CRC_A = CRC32(CRC_A, A[i])
10385 //  CRC_B = CRC32(CRC_B, B[i])
10386 //  CRC_C = CRC32(CRC_C, C[i])
10387 // end for
10388 // Recombine
10389 void MacroAssembler::crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported,
10390                                        Register in_out1, Register in_out2, Register in_out3,
10391                                        Register tmp1, Register tmp2, Register tmp3,
10392                                        XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
10393                                        Register tmp4, Register tmp5,
10394                                        Register n_tmp6) {
10395   Label L_processPartitions;
10396   Label L_processPartition;
10397   Label L_exit;
10398 
10399   bind(L_processPartitions);
10400   cmpl(in_out1, 3 * size);
10401   jcc(Assembler::less, L_exit);
10402     xorl(tmp1, tmp1);
10403     xorl(tmp2, tmp2);
10404     movq(tmp3, in_out2);
10405     addq(tmp3, size);
10406 
10407     bind(L_processPartition);
10408       crc32(in_out3, Address(in_out2, 0), 8);
10409       crc32(tmp1, Address(in_out2, size), 8);
10410       crc32(tmp2, Address(in_out2, size * 2), 8);
10411       addq(in_out2, 8);
10412       cmpq(in_out2, tmp3);
10413       jcc(Assembler::less, L_processPartition);
10414     crc32c_rec_alt2(const_or_pre_comp_const_index_u1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, in_out3, tmp1, tmp2,
10415             w_xtmp1, w_xtmp2, w_xtmp3,
10416             tmp4, tmp5,
10417             n_tmp6);
10418     addq(in_out2, 2 * size);
10419     subl(in_out1, 3 * size);
10420     jmp(L_processPartitions);
10421 
10422   bind(L_exit);
10423 }
10424 #else
10425 void MacroAssembler::crc32c_ipl_alg4(Register in_out, uint32_t n,
10426                                      Register tmp1, Register tmp2, Register tmp3,
10427                                      XMMRegister xtmp1, XMMRegister xtmp2) {
10428   lea(tmp3, ExternalAddress(StubRoutines::crc32c_table_addr()));
10429   if (n > 0) {
10430     addl(tmp3, n * 256 * 8);
10431   }
10432   //    Q1 = TABLEExt[n][B & 0xFF];
10433   movl(tmp1, in_out);
10434   andl(tmp1, 0x000000FF);
10435   shll(tmp1, 3);
10436   addl(tmp1, tmp3);
10437   movq(xtmp1, Address(tmp1, 0));
10438 
10439   //    Q2 = TABLEExt[n][B >> 8 & 0xFF];
10440   movl(tmp2, in_out);
10441   shrl(tmp2, 8);
10442   andl(tmp2, 0x000000FF);
10443   shll(tmp2, 3);
10444   addl(tmp2, tmp3);
10445   movq(xtmp2, Address(tmp2, 0));
10446 
10447   psllq(xtmp2, 8);
10448   pxor(xtmp1, xtmp2);
10449 
10450   //    Q3 = TABLEExt[n][B >> 16 & 0xFF];
10451   movl(tmp2, in_out);
10452   shrl(tmp2, 16);
10453   andl(tmp2, 0x000000FF);
10454   shll(tmp2, 3);
10455   addl(tmp2, tmp3);
10456   movq(xtmp2, Address(tmp2, 0));
10457 
10458   psllq(xtmp2, 16);
10459   pxor(xtmp1, xtmp2);
10460 
10461   //    Q4 = TABLEExt[n][B >> 24 & 0xFF];
10462   shrl(in_out, 24);
10463   andl(in_out, 0x000000FF);
10464   shll(in_out, 3);
10465   addl(in_out, tmp3);
10466   movq(xtmp2, Address(in_out, 0));
10467 
10468   psllq(xtmp2, 24);
10469   pxor(xtmp1, xtmp2); // Result in CXMM
10470   //    return Q1 ^ Q2 << 8 ^ Q3 << 16 ^ Q4 << 24;
10471 }
10472 
10473 void MacroAssembler::crc32c_pclmulqdq(XMMRegister w_xtmp1,
10474                                       Register in_out,
10475                                       uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported,
10476                                       XMMRegister w_xtmp2,
10477                                       Register tmp1,
10478                                       Register n_tmp2, Register n_tmp3) {
10479   if (is_pclmulqdq_supported) {
10480     movdl(w_xtmp1, in_out);
10481 
10482     movl(tmp1, const_or_pre_comp_const_index);
10483     movdl(w_xtmp2, tmp1);
10484     pclmulqdq(w_xtmp1, w_xtmp2, 0);
10485     // Keep result in XMM since GPR is 32 bit in length
10486   } else {
10487     crc32c_ipl_alg4(in_out, const_or_pre_comp_const_index, tmp1, n_tmp2, n_tmp3, w_xtmp1, w_xtmp2);
10488   }
10489 }
10490 
10491 void MacroAssembler::crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2,
10492                                      XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
10493                                      Register tmp1, Register tmp2,
10494                                      Register n_tmp3) {
10495   crc32c_pclmulqdq(w_xtmp1, in_out, const_or_pre_comp_const_index_u1, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
10496   crc32c_pclmulqdq(w_xtmp2, in1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
10497 
10498   psllq(w_xtmp1, 1);
10499   movdl(tmp1, w_xtmp1);
10500   psrlq(w_xtmp1, 32);
10501   movdl(in_out, w_xtmp1);
10502 
10503   xorl(tmp2, tmp2);
10504   crc32(tmp2, tmp1, 4);
10505   xorl(in_out, tmp2);
10506 
10507   psllq(w_xtmp2, 1);
10508   movdl(tmp1, w_xtmp2);
10509   psrlq(w_xtmp2, 32);
10510   movdl(in1, w_xtmp2);
10511 
10512   xorl(tmp2, tmp2);
10513   crc32(tmp2, tmp1, 4);
10514   xorl(in1, tmp2);
10515   xorl(in_out, in1);
10516   xorl(in_out, in2);
10517 }
10518 
10519 void MacroAssembler::crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported,
10520                                        Register in_out1, Register in_out2, Register in_out3,
10521                                        Register tmp1, Register tmp2, Register tmp3,
10522                                        XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
10523                                        Register tmp4, Register tmp5,
10524                                        Register n_tmp6) {
10525   Label L_processPartitions;
10526   Label L_processPartition;
10527   Label L_exit;
10528 
10529   bind(L_processPartitions);
10530   cmpl(in_out1, 3 * size);
10531   jcc(Assembler::less, L_exit);
10532     xorl(tmp1, tmp1);
10533     xorl(tmp2, tmp2);
10534     movl(tmp3, in_out2);
10535     addl(tmp3, size);
10536 
10537     bind(L_processPartition);
10538       crc32(in_out3, Address(in_out2, 0), 4);
10539       crc32(tmp1, Address(in_out2, size), 4);
10540       crc32(tmp2, Address(in_out2, size*2), 4);
10541       crc32(in_out3, Address(in_out2, 0+4), 4);
10542       crc32(tmp1, Address(in_out2, size+4), 4);
10543       crc32(tmp2, Address(in_out2, size*2+4), 4);
10544       addl(in_out2, 8);
10545       cmpl(in_out2, tmp3);
10546       jcc(Assembler::less, L_processPartition);
10547 
10548         push(tmp3);
10549         push(in_out1);
10550         push(in_out2);
10551         tmp4 = tmp3;
10552         tmp5 = in_out1;
10553         n_tmp6 = in_out2;
10554 
10555       crc32c_rec_alt2(const_or_pre_comp_const_index_u1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, in_out3, tmp1, tmp2,
10556             w_xtmp1, w_xtmp2, w_xtmp3,
10557             tmp4, tmp5,
10558             n_tmp6);
10559 
10560         pop(in_out2);
10561         pop(in_out1);
10562         pop(tmp3);
10563 
10564     addl(in_out2, 2 * size);
10565     subl(in_out1, 3 * size);
10566     jmp(L_processPartitions);
10567 
10568   bind(L_exit);
10569 }
10570 #endif //LP64
10571 
10572 #ifdef _LP64
10573 // Algorithm 2: Pipelined usage of the CRC32 instruction.
10574 // Input: A buffer I of L bytes.
10575 // Output: the CRC32C value of the buffer.
10576 // Notations:
10577 // Write L = 24N + r, with N = floor (L/24).
10578 // r = L mod 24 (0 <= r < 24).
10579 // Consider I as the concatenation of A|B|C|R, where A, B, C, each,
10580 // N quadwords, and R consists of r bytes.
10581 // A[j] = I [8j+7:8j], j= 0, 1, ..., N-1
10582 // B[j] = I [N + 8j+7:N + 8j], j= 0, 1, ..., N-1
10583 // C[j] = I [2N + 8j+7:2N + 8j], j= 0, 1, ..., N-1
10584 // if r > 0 R[j] = I [3N +j], j= 0, 1, ...,r-1
10585 void MacroAssembler::crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2,
10586                                           Register tmp1, Register tmp2, Register tmp3,
10587                                           Register tmp4, Register tmp5, Register tmp6,
10588                                           XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
10589                                           bool is_pclmulqdq_supported) {
10590   uint32_t const_or_pre_comp_const_index[CRC32C_NUM_PRECOMPUTED_CONSTANTS];
10591   Label L_wordByWord;
10592   Label L_byteByByteProlog;
10593   Label L_byteByByte;
10594   Label L_exit;
10595 
10596   if (is_pclmulqdq_supported ) {
10597     const_or_pre_comp_const_index[1] = *(uint32_t *)StubRoutines::_crc32c_table_addr;
10598     const_or_pre_comp_const_index[0] = *((uint32_t *)StubRoutines::_crc32c_table_addr+1);
10599 
10600     const_or_pre_comp_const_index[3] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 2);
10601     const_or_pre_comp_const_index[2] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 3);
10602 
10603     const_or_pre_comp_const_index[5] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 4);
10604     const_or_pre_comp_const_index[4] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 5);
10605     assert((CRC32C_NUM_PRECOMPUTED_CONSTANTS - 1 ) == 5, "Checking whether you declared all of the constants based on the number of \"chunks\"");
10606   } else {
10607     const_or_pre_comp_const_index[0] = 1;
10608     const_or_pre_comp_const_index[1] = 0;
10609 
10610     const_or_pre_comp_const_index[2] = 3;
10611     const_or_pre_comp_const_index[3] = 2;
10612 
10613     const_or_pre_comp_const_index[4] = 5;
10614     const_or_pre_comp_const_index[5] = 4;
10615    }
10616   crc32c_proc_chunk(CRC32C_HIGH, const_or_pre_comp_const_index[0], const_or_pre_comp_const_index[1], is_pclmulqdq_supported,
10617                     in2, in1, in_out,
10618                     tmp1, tmp2, tmp3,
10619                     w_xtmp1, w_xtmp2, w_xtmp3,
10620                     tmp4, tmp5,
10621                     tmp6);
10622   crc32c_proc_chunk(CRC32C_MIDDLE, const_or_pre_comp_const_index[2], const_or_pre_comp_const_index[3], is_pclmulqdq_supported,
10623                     in2, in1, in_out,
10624                     tmp1, tmp2, tmp3,
10625                     w_xtmp1, w_xtmp2, w_xtmp3,
10626                     tmp4, tmp5,
10627                     tmp6);
10628   crc32c_proc_chunk(CRC32C_LOW, const_or_pre_comp_const_index[4], const_or_pre_comp_const_index[5], is_pclmulqdq_supported,
10629                     in2, in1, in_out,
10630                     tmp1, tmp2, tmp3,
10631                     w_xtmp1, w_xtmp2, w_xtmp3,
10632                     tmp4, tmp5,
10633                     tmp6);
10634   movl(tmp1, in2);
10635   andl(tmp1, 0x00000007);
10636   negl(tmp1);
10637   addl(tmp1, in2);
10638   addq(tmp1, in1);
10639 
10640   BIND(L_wordByWord);
10641   cmpq(in1, tmp1);
10642   jcc(Assembler::greaterEqual, L_byteByByteProlog);
10643     crc32(in_out, Address(in1, 0), 4);
10644     addq(in1, 4);
10645     jmp(L_wordByWord);
10646 
10647   BIND(L_byteByByteProlog);
10648   andl(in2, 0x00000007);
10649   movl(tmp2, 1);
10650 
10651   BIND(L_byteByByte);
10652   cmpl(tmp2, in2);
10653   jccb(Assembler::greater, L_exit);
10654     crc32(in_out, Address(in1, 0), 1);
10655     incq(in1);
10656     incl(tmp2);
10657     jmp(L_byteByByte);
10658 
10659   BIND(L_exit);
10660 }
10661 #else
10662 void MacroAssembler::crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2,
10663                                           Register tmp1, Register  tmp2, Register tmp3,
10664                                           Register tmp4, Register  tmp5, Register tmp6,
10665                                           XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
10666                                           bool is_pclmulqdq_supported) {
10667   uint32_t const_or_pre_comp_const_index[CRC32C_NUM_PRECOMPUTED_CONSTANTS];
10668   Label L_wordByWord;
10669   Label L_byteByByteProlog;
10670   Label L_byteByByte;
10671   Label L_exit;
10672 
10673   if (is_pclmulqdq_supported) {
10674     const_or_pre_comp_const_index[1] = *(uint32_t *)StubRoutines::_crc32c_table_addr;
10675     const_or_pre_comp_const_index[0] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 1);
10676 
10677     const_or_pre_comp_const_index[3] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 2);
10678     const_or_pre_comp_const_index[2] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 3);
10679 
10680     const_or_pre_comp_const_index[5] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 4);
10681     const_or_pre_comp_const_index[4] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 5);
10682   } else {
10683     const_or_pre_comp_const_index[0] = 1;
10684     const_or_pre_comp_const_index[1] = 0;
10685 
10686     const_or_pre_comp_const_index[2] = 3;
10687     const_or_pre_comp_const_index[3] = 2;
10688 
10689     const_or_pre_comp_const_index[4] = 5;
10690     const_or_pre_comp_const_index[5] = 4;
10691   }
10692   crc32c_proc_chunk(CRC32C_HIGH, const_or_pre_comp_const_index[0], const_or_pre_comp_const_index[1], is_pclmulqdq_supported,
10693                     in2, in1, in_out,
10694                     tmp1, tmp2, tmp3,
10695                     w_xtmp1, w_xtmp2, w_xtmp3,
10696                     tmp4, tmp5,
10697                     tmp6);
10698   crc32c_proc_chunk(CRC32C_MIDDLE, const_or_pre_comp_const_index[2], const_or_pre_comp_const_index[3], is_pclmulqdq_supported,
10699                     in2, in1, in_out,
10700                     tmp1, tmp2, tmp3,
10701                     w_xtmp1, w_xtmp2, w_xtmp3,
10702                     tmp4, tmp5,
10703                     tmp6);
10704   crc32c_proc_chunk(CRC32C_LOW, const_or_pre_comp_const_index[4], const_or_pre_comp_const_index[5], is_pclmulqdq_supported,
10705                     in2, in1, in_out,
10706                     tmp1, tmp2, tmp3,
10707                     w_xtmp1, w_xtmp2, w_xtmp3,
10708                     tmp4, tmp5,
10709                     tmp6);
10710   movl(tmp1, in2);
10711   andl(tmp1, 0x00000007);
10712   negl(tmp1);
10713   addl(tmp1, in2);
10714   addl(tmp1, in1);
10715 
10716   BIND(L_wordByWord);
10717   cmpl(in1, tmp1);
10718   jcc(Assembler::greaterEqual, L_byteByByteProlog);
10719     crc32(in_out, Address(in1,0), 4);
10720     addl(in1, 4);
10721     jmp(L_wordByWord);
10722 
10723   BIND(L_byteByByteProlog);
10724   andl(in2, 0x00000007);
10725   movl(tmp2, 1);
10726 
10727   BIND(L_byteByByte);
10728   cmpl(tmp2, in2);
10729   jccb(Assembler::greater, L_exit);
10730     movb(tmp1, Address(in1, 0));
10731     crc32(in_out, tmp1, 1);
10732     incl(in1);
10733     incl(tmp2);
10734     jmp(L_byteByByte);
10735 
10736   BIND(L_exit);
10737 }
10738 #endif // LP64
10739 #undef BIND
10740 #undef BLOCK_COMMENT
10741 
10742 // Compress char[] array to byte[].
10743 //   ..\jdk\src\java.base\share\classes\java\lang\StringUTF16.java
10744 //   @HotSpotIntrinsicCandidate
10745 //   private static int compress(char[] src, int srcOff, byte[] dst, int dstOff, int len) {
10746 //     for (int i = 0; i < len; i++) {
10747 //       int c = src[srcOff++];
10748 //       if (c >>> 8 != 0) {
10749 //         return 0;
10750 //       }
10751 //       dst[dstOff++] = (byte)c;
10752 //     }
10753 //     return len;
10754 //   }
10755 void MacroAssembler::char_array_compress(Register src, Register dst, Register len,
10756   XMMRegister tmp1Reg, XMMRegister tmp2Reg,
10757   XMMRegister tmp3Reg, XMMRegister tmp4Reg,
10758   Register tmp5, Register result) {
10759   Label copy_chars_loop, return_length, return_zero, done, below_threshold;
10760 
10761   // rsi: src
10762   // rdi: dst
10763   // rdx: len
10764   // rcx: tmp5
10765   // rax: result
10766 
10767   // rsi holds start addr of source char[] to be compressed
10768   // rdi holds start addr of destination byte[]
10769   // rdx holds length
10770 
10771   assert(len != result, "");
10772 
10773   // save length for return
10774   push(len);
10775 
10776   // 8165287: EVEX version disabled for now, needs to be refactored as
10777   // it is returning incorrect results.
10778   if ((UseAVX > 2) && // AVX512
10779     0 &&
10780     VM_Version::supports_avx512vlbw() &&
10781     VM_Version::supports_bmi2()) {
10782 
10783     set_vector_masking();  // opening of the stub context for programming mask registers
10784 
10785     Label copy_32_loop, copy_loop_tail, copy_just_portion_of_candidates;
10786 
10787     // alignement
10788     Label post_alignement;
10789 
10790     // if length of the string is less than 16, handle it in an old fashioned
10791     // way
10792     testl(len, -32);
10793     jcc(Assembler::zero, below_threshold);
10794 
10795     // First check whether a character is compressable ( <= 0xFF).
10796     // Create mask to test for Unicode chars inside zmm vector
10797     movl(result, 0x00FF);
10798     evpbroadcastw(tmp2Reg, result, Assembler::AVX_512bit);
10799 
10800     testl(len, -64);
10801     jcc(Assembler::zero, post_alignement);
10802 
10803     // Save k1
10804     kmovql(k3, k1);
10805 
10806     movl(tmp5, dst);
10807     andl(tmp5, (64 - 1));
10808     negl(tmp5);
10809     andl(tmp5, (64 - 1));
10810 
10811     // bail out when there is nothing to be done
10812     testl(tmp5, 0xFFFFFFFF);
10813     jcc(Assembler::zero, post_alignement);
10814 
10815     // ~(~0 << len), where len is the # of remaining elements to process
10816     movl(result, 0xFFFFFFFF);
10817     shlxl(result, result, tmp5);
10818     notl(result);
10819 
10820     kmovdl(k1, result);
10821 
10822     evmovdquw(tmp1Reg, k1, Address(src, 0), Assembler::AVX_512bit);
10823     evpcmpuw(k2, k1, tmp1Reg, tmp2Reg, Assembler::le, Assembler::AVX_512bit);
10824     ktestd(k2, k1);
10825     jcc(Assembler::carryClear, copy_just_portion_of_candidates);
10826 
10827     evpmovwb(Address(dst, 0), k1, tmp1Reg, Assembler::AVX_512bit);
10828 
10829     addptr(src, tmp5);
10830     addptr(src, tmp5);
10831     addptr(dst, tmp5);
10832     subl(len, tmp5);
10833 
10834     bind(post_alignement);
10835     // end of alignement
10836 
10837     movl(tmp5, len);
10838     andl(tmp5, (32 - 1));   // tail count (in chars)
10839     andl(len, ~(32 - 1));    // vector count (in chars)
10840     jcc(Assembler::zero, copy_loop_tail);
10841 
10842     lea(src, Address(src, len, Address::times_2));
10843     lea(dst, Address(dst, len, Address::times_1));
10844     negptr(len);
10845 
10846     bind(copy_32_loop);
10847     evmovdquw(tmp1Reg, Address(src, len, Address::times_2), Assembler::AVX_512bit);
10848     evpcmpuw(k2, tmp1Reg, tmp2Reg, Assembler::le, Assembler::AVX_512bit);
10849     kortestdl(k2, k2);
10850     jcc(Assembler::carryClear, copy_just_portion_of_candidates);
10851 
10852     // All elements in current processed chunk are valid candidates for
10853     // compression. Write a truncated byte elements to the memory.
10854     evpmovwb(Address(dst, len, Address::times_1), tmp1Reg, Assembler::AVX_512bit);
10855     addptr(len, 32);
10856     jcc(Assembler::notZero, copy_32_loop);
10857 
10858     bind(copy_loop_tail);
10859     // bail out when there is nothing to be done
10860     testl(tmp5, 0xFFFFFFFF);
10861     jcc(Assembler::zero, return_length);
10862 
10863     // Save k1
10864     kmovql(k3, k1);
10865 
10866     movl(len, tmp5);
10867 
10868     // ~(~0 << len), where len is the # of remaining elements to process
10869     movl(result, 0xFFFFFFFF);
10870     shlxl(result, result, len);
10871     notl(result);
10872 
10873     kmovdl(k1, result);
10874 
10875     evmovdquw(tmp1Reg, k1, Address(src, 0), Assembler::AVX_512bit);
10876     evpcmpuw(k2, k1, tmp1Reg, tmp2Reg, Assembler::le, Assembler::AVX_512bit);
10877     ktestd(k2, k1);
10878     jcc(Assembler::carryClear, copy_just_portion_of_candidates);
10879 
10880     evpmovwb(Address(dst, 0), k1, tmp1Reg, Assembler::AVX_512bit);
10881     // Restore k1
10882     kmovql(k1, k3);
10883 
10884     jmp(return_length);
10885 
10886     bind(copy_just_portion_of_candidates);
10887     kmovdl(tmp5, k2);
10888     tzcntl(tmp5, tmp5);
10889 
10890     // ~(~0 << tmp5), where tmp5 is a number of elements in an array from the
10891     // result to the first element larger than 0xFF
10892     movl(result, 0xFFFFFFFF);
10893     shlxl(result, result, tmp5);
10894     notl(result);
10895 
10896     kmovdl(k1, result);
10897 
10898     evpmovwb(Address(dst, 0), k1, tmp1Reg, Assembler::AVX_512bit);
10899     // Restore k1
10900     kmovql(k1, k3);
10901 
10902     jmp(return_zero);
10903 
10904     clear_vector_masking();   // closing of the stub context for programming mask registers
10905   }
10906   if (UseSSE42Intrinsics) {
10907     Label copy_32_loop, copy_16, copy_tail;
10908 
10909     bind(below_threshold);
10910 
10911     movl(result, len);
10912 
10913     movl(tmp5, 0xff00ff00);   // create mask to test for Unicode chars in vectors
10914 
10915     // vectored compression
10916     andl(len, 0xfffffff0);    // vector count (in chars)
10917     andl(result, 0x0000000f);    // tail count (in chars)
10918     testl(len, len);
10919     jccb(Assembler::zero, copy_16);
10920 
10921     // compress 16 chars per iter
10922     movdl(tmp1Reg, tmp5);
10923     pshufd(tmp1Reg, tmp1Reg, 0);   // store Unicode mask in tmp1Reg
10924     pxor(tmp4Reg, tmp4Reg);
10925 
10926     lea(src, Address(src, len, Address::times_2));
10927     lea(dst, Address(dst, len, Address::times_1));
10928     negptr(len);
10929 
10930     bind(copy_32_loop);
10931     movdqu(tmp2Reg, Address(src, len, Address::times_2));     // load 1st 8 characters
10932     por(tmp4Reg, tmp2Reg);
10933     movdqu(tmp3Reg, Address(src, len, Address::times_2, 16)); // load next 8 characters
10934     por(tmp4Reg, tmp3Reg);
10935     ptest(tmp4Reg, tmp1Reg);       // check for Unicode chars in next vector
10936     jcc(Assembler::notZero, return_zero);
10937     packuswb(tmp2Reg, tmp3Reg);    // only ASCII chars; compress each to 1 byte
10938     movdqu(Address(dst, len, Address::times_1), tmp2Reg);
10939     addptr(len, 16);
10940     jcc(Assembler::notZero, copy_32_loop);
10941 
10942     // compress next vector of 8 chars (if any)
10943     bind(copy_16);
10944     movl(len, result);
10945     andl(len, 0xfffffff8);    // vector count (in chars)
10946     andl(result, 0x00000007);    // tail count (in chars)
10947     testl(len, len);
10948     jccb(Assembler::zero, copy_tail);
10949 
10950     movdl(tmp1Reg, tmp5);
10951     pshufd(tmp1Reg, tmp1Reg, 0);   // store Unicode mask in tmp1Reg
10952     pxor(tmp3Reg, tmp3Reg);
10953 
10954     movdqu(tmp2Reg, Address(src, 0));
10955     ptest(tmp2Reg, tmp1Reg);       // check for Unicode chars in vector
10956     jccb(Assembler::notZero, return_zero);
10957     packuswb(tmp2Reg, tmp3Reg);    // only LATIN1 chars; compress each to 1 byte
10958     movq(Address(dst, 0), tmp2Reg);
10959     addptr(src, 16);
10960     addptr(dst, 8);
10961 
10962     bind(copy_tail);
10963     movl(len, result);
10964   }
10965   // compress 1 char per iter
10966   testl(len, len);
10967   jccb(Assembler::zero, return_length);
10968   lea(src, Address(src, len, Address::times_2));
10969   lea(dst, Address(dst, len, Address::times_1));
10970   negptr(len);
10971 
10972   bind(copy_chars_loop);
10973   load_unsigned_short(result, Address(src, len, Address::times_2));
10974   testl(result, 0xff00);      // check if Unicode char
10975   jccb(Assembler::notZero, return_zero);
10976   movb(Address(dst, len, Address::times_1), result);  // ASCII char; compress to 1 byte
10977   increment(len);
10978   jcc(Assembler::notZero, copy_chars_loop);
10979 
10980   // if compression succeeded, return length
10981   bind(return_length);
10982   pop(result);
10983   jmpb(done);
10984 
10985   // if compression failed, return 0
10986   bind(return_zero);
10987   xorl(result, result);
10988   addptr(rsp, wordSize);
10989 
10990   bind(done);
10991 }
10992 
10993 // Inflate byte[] array to char[].
10994 //   ..\jdk\src\java.base\share\classes\java\lang\StringLatin1.java
10995 //   @HotSpotIntrinsicCandidate
10996 //   private static void inflate(byte[] src, int srcOff, char[] dst, int dstOff, int len) {
10997 //     for (int i = 0; i < len; i++) {
10998 //       dst[dstOff++] = (char)(src[srcOff++] & 0xff);
10999 //     }
11000 //   }
11001 void MacroAssembler::byte_array_inflate(Register src, Register dst, Register len,
11002   XMMRegister tmp1, Register tmp2) {
11003   Label copy_chars_loop, done, below_threshold;
11004   // rsi: src
11005   // rdi: dst
11006   // rdx: len
11007   // rcx: tmp2
11008 
11009   // rsi holds start addr of source byte[] to be inflated
11010   // rdi holds start addr of destination char[]
11011   // rdx holds length
11012   assert_different_registers(src, dst, len, tmp2);
11013 
11014   if ((UseAVX > 2) && // AVX512
11015     VM_Version::supports_avx512vlbw() &&
11016     VM_Version::supports_bmi2()) {
11017 
11018     set_vector_masking();  // opening of the stub context for programming mask registers
11019 
11020     Label copy_32_loop, copy_tail;
11021     Register tmp3_aliased = len;
11022 
11023     // if length of the string is less than 16, handle it in an old fashioned
11024     // way
11025     testl(len, -16);
11026     jcc(Assembler::zero, below_threshold);
11027 
11028     // In order to use only one arithmetic operation for the main loop we use
11029     // this pre-calculation
11030     movl(tmp2, len);
11031     andl(tmp2, (32 - 1)); // tail count (in chars), 32 element wide loop
11032     andl(len, -32);     // vector count
11033     jccb(Assembler::zero, copy_tail);
11034 
11035     lea(src, Address(src, len, Address::times_1));
11036     lea(dst, Address(dst, len, Address::times_2));
11037     negptr(len);
11038 
11039 
11040     // inflate 32 chars per iter
11041     bind(copy_32_loop);
11042     vpmovzxbw(tmp1, Address(src, len, Address::times_1), Assembler::AVX_512bit);
11043     evmovdquw(Address(dst, len, Address::times_2), tmp1, Assembler::AVX_512bit);
11044     addptr(len, 32);
11045     jcc(Assembler::notZero, copy_32_loop);
11046 
11047     bind(copy_tail);
11048     // bail out when there is nothing to be done
11049     testl(tmp2, -1); // we don't destroy the contents of tmp2 here
11050     jcc(Assembler::zero, done);
11051 
11052     // Save k1
11053     kmovql(k2, k1);
11054 
11055     // ~(~0 << length), where length is the # of remaining elements to process
11056     movl(tmp3_aliased, -1);
11057     shlxl(tmp3_aliased, tmp3_aliased, tmp2);
11058     notl(tmp3_aliased);
11059     kmovdl(k1, tmp3_aliased);
11060     evpmovzxbw(tmp1, k1, Address(src, 0), Assembler::AVX_512bit);
11061     evmovdquw(Address(dst, 0), k1, tmp1, Assembler::AVX_512bit);
11062 
11063     // Restore k1
11064     kmovql(k1, k2);
11065     jmp(done);
11066 
11067     clear_vector_masking();   // closing of the stub context for programming mask registers
11068   }
11069   if (UseSSE42Intrinsics) {
11070     Label copy_16_loop, copy_8_loop, copy_bytes, copy_new_tail, copy_tail;
11071 
11072     movl(tmp2, len);
11073 
11074     if (UseAVX > 1) {
11075       andl(tmp2, (16 - 1));
11076       andl(len, -16);
11077       jccb(Assembler::zero, copy_new_tail);
11078     } else {
11079       andl(tmp2, 0x00000007);   // tail count (in chars)
11080       andl(len, 0xfffffff8);    // vector count (in chars)
11081       jccb(Assembler::zero, copy_tail);
11082     }
11083 
11084     // vectored inflation
11085     lea(src, Address(src, len, Address::times_1));
11086     lea(dst, Address(dst, len, Address::times_2));
11087     negptr(len);
11088 
11089     if (UseAVX > 1) {
11090       bind(copy_16_loop);
11091       vpmovzxbw(tmp1, Address(src, len, Address::times_1), Assembler::AVX_256bit);
11092       vmovdqu(Address(dst, len, Address::times_2), tmp1);
11093       addptr(len, 16);
11094       jcc(Assembler::notZero, copy_16_loop);
11095 
11096       bind(below_threshold);
11097       bind(copy_new_tail);
11098       if ((UseAVX > 2) &&
11099         VM_Version::supports_avx512vlbw() &&
11100         VM_Version::supports_bmi2()) {
11101         movl(tmp2, len);
11102       } else {
11103         movl(len, tmp2);
11104       }
11105       andl(tmp2, 0x00000007);
11106       andl(len, 0xFFFFFFF8);
11107       jccb(Assembler::zero, copy_tail);
11108 
11109       pmovzxbw(tmp1, Address(src, 0));
11110       movdqu(Address(dst, 0), tmp1);
11111       addptr(src, 8);
11112       addptr(dst, 2 * 8);
11113 
11114       jmp(copy_tail, true);
11115     }
11116 
11117     // inflate 8 chars per iter
11118     bind(copy_8_loop);
11119     pmovzxbw(tmp1, Address(src, len, Address::times_1));  // unpack to 8 words
11120     movdqu(Address(dst, len, Address::times_2), tmp1);
11121     addptr(len, 8);
11122     jcc(Assembler::notZero, copy_8_loop);
11123 
11124     bind(copy_tail);
11125     movl(len, tmp2);
11126 
11127     cmpl(len, 4);
11128     jccb(Assembler::less, copy_bytes);
11129 
11130     movdl(tmp1, Address(src, 0));  // load 4 byte chars
11131     pmovzxbw(tmp1, tmp1);
11132     movq(Address(dst, 0), tmp1);
11133     subptr(len, 4);
11134     addptr(src, 4);
11135     addptr(dst, 8);
11136 
11137     bind(copy_bytes);
11138   }
11139   testl(len, len);
11140   jccb(Assembler::zero, done);
11141   lea(src, Address(src, len, Address::times_1));
11142   lea(dst, Address(dst, len, Address::times_2));
11143   negptr(len);
11144 
11145   // inflate 1 char per iter
11146   bind(copy_chars_loop);
11147   load_unsigned_byte(tmp2, Address(src, len, Address::times_1));  // load byte char
11148   movw(Address(dst, len, Address::times_2), tmp2);  // inflate byte char to word
11149   increment(len);
11150   jcc(Assembler::notZero, copy_chars_loop);
11151 
11152   bind(done);
11153 }
11154 
11155 Assembler::Condition MacroAssembler::negate_condition(Assembler::Condition cond) {
11156   switch (cond) {
11157     // Note some conditions are synonyms for others
11158     case Assembler::zero:         return Assembler::notZero;
11159     case Assembler::notZero:      return Assembler::zero;
11160     case Assembler::less:         return Assembler::greaterEqual;
11161     case Assembler::lessEqual:    return Assembler::greater;
11162     case Assembler::greater:      return Assembler::lessEqual;
11163     case Assembler::greaterEqual: return Assembler::less;
11164     case Assembler::below:        return Assembler::aboveEqual;
11165     case Assembler::belowEqual:   return Assembler::above;
11166     case Assembler::above:        return Assembler::belowEqual;
11167     case Assembler::aboveEqual:   return Assembler::below;
11168     case Assembler::overflow:     return Assembler::noOverflow;
11169     case Assembler::noOverflow:   return Assembler::overflow;
11170     case Assembler::negative:     return Assembler::positive;
11171     case Assembler::positive:     return Assembler::negative;
11172     case Assembler::parity:       return Assembler::noParity;
11173     case Assembler::noParity:     return Assembler::parity;
11174   }
11175   ShouldNotReachHere(); return Assembler::overflow;
11176 }
11177 
11178 SkipIfEqual::SkipIfEqual(
11179     MacroAssembler* masm, const bool* flag_addr, bool value) {
11180   _masm = masm;
11181   _masm->cmp8(ExternalAddress((address)flag_addr), value);
11182   _masm->jcc(Assembler::equal, _label);
11183 }
11184 
11185 SkipIfEqual::~SkipIfEqual() {
11186   _masm->bind(_label);
11187 }
11188 
11189 // 32-bit Windows has its own fast-path implementation
11190 // of get_thread
11191 #if !defined(WIN32) || defined(_LP64)
11192 
11193 // This is simply a call to Thread::current()
11194 void MacroAssembler::get_thread(Register thread) {
11195   if (thread != rax) {
11196     push(rax);
11197   }
11198   LP64_ONLY(push(rdi);)
11199   LP64_ONLY(push(rsi);)
11200   push(rdx);
11201   push(rcx);
11202 #ifdef _LP64
11203   push(r8);
11204   push(r9);
11205   push(r10);
11206   push(r11);
11207 #endif
11208 
11209   MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, Thread::current), 0);
11210 
11211 #ifdef _LP64
11212   pop(r11);
11213   pop(r10);
11214   pop(r9);
11215   pop(r8);
11216 #endif
11217   pop(rcx);
11218   pop(rdx);
11219   LP64_ONLY(pop(rsi);)
11220   LP64_ONLY(pop(rdi);)
11221   if (thread != rax) {
11222     mov(thread, rax);
11223     pop(rax);
11224   }
11225 }
11226 
11227 #endif