1 //
2 // Copyright (c) 2003, 2015, Oracle and/or its affiliates. All rights reserved.
3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 //
5 // This code is free software; you can redistribute it and/or modify it
6 // under the terms of the GNU General Public License version 2 only, as
7 // published by the Free Software Foundation.
8 //
9 // This code is distributed in the hope that it will be useful, but WITHOUT
10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 // version 2 for more details (a copy is included in the LICENSE file that
13 // accompanied this code).
14 //
15 // You should have received a copy of the GNU General Public License version
16 // 2 along with this work; if not, write to the Free Software Foundation,
17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 //
19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 // or visit www.oracle.com if you need additional information or have any
21 // questions.
22 //
23 //
24
25 // AMD64 Architecture Description File
26
27 //----------REGISTER DEFINITION BLOCK------------------------------------------
28 // This information is used by the matcher and the register allocator to
29 // describe individual registers and classes of registers within the target
30 // archtecture.
31
32 register %{
33 //----------Architecture Description Register Definitions----------------------
34 // General Registers
35 // "reg_def" name ( register save type, C convention save type,
36 // ideal register type, encoding );
37 // Register Save Types:
38 //
39 // NS = No-Save: The register allocator assumes that these registers
40 // can be used without saving upon entry to the method, &
41 // that they do not need to be saved at call sites.
42 //
43 // SOC = Save-On-Call: The register allocator assumes that these registers
44 // can be used without saving upon entry to the method,
45 // but that they must be saved at call sites.
46 //
47 // SOE = Save-On-Entry: The register allocator assumes that these registers
48 // must be saved before using them upon entry to the
49 // method, but they do not need to be saved at call
50 // sites.
51 //
52 // AS = Always-Save: The register allocator assumes that these registers
53 // must be saved before using them upon entry to the
54 // method, & that they must be saved at call sites.
55 //
56 // Ideal Register Type is used to determine how to save & restore a
57 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
58 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
59 //
60 // The encoding number is the actual bit-pattern placed into the opcodes.
61
62 // General Registers
63 // R8-R15 must be encoded with REX. (RSP, RBP, RSI, RDI need REX when
64 // used as byte registers)
65
66 // Previously set RBX, RSI, and RDI as save-on-entry for java code
67 // Turn off SOE in java-code due to frequent use of uncommon-traps.
68 // Now that allocator is better, turn on RSI and RDI as SOE registers.
69
70 reg_def RAX (SOC, SOC, Op_RegI, 0, rax->as_VMReg());
71 reg_def RAX_H(SOC, SOC, Op_RegI, 0, rax->as_VMReg()->next());
72
73 reg_def RCX (SOC, SOC, Op_RegI, 1, rcx->as_VMReg());
74 reg_def RCX_H(SOC, SOC, Op_RegI, 1, rcx->as_VMReg()->next());
75
76 reg_def RDX (SOC, SOC, Op_RegI, 2, rdx->as_VMReg());
77 reg_def RDX_H(SOC, SOC, Op_RegI, 2, rdx->as_VMReg()->next());
78
79 reg_def RBX (SOC, SOE, Op_RegI, 3, rbx->as_VMReg());
80 reg_def RBX_H(SOC, SOE, Op_RegI, 3, rbx->as_VMReg()->next());
81
82 reg_def RSP (NS, NS, Op_RegI, 4, rsp->as_VMReg());
83 reg_def RSP_H(NS, NS, Op_RegI, 4, rsp->as_VMReg()->next());
84
85 // now that adapter frames are gone RBP is always saved and restored by the prolog/epilog code
86 reg_def RBP (NS, SOE, Op_RegI, 5, rbp->as_VMReg());
87 reg_def RBP_H(NS, SOE, Op_RegI, 5, rbp->as_VMReg()->next());
88
89 #ifdef _WIN64
90
91 reg_def RSI (SOC, SOE, Op_RegI, 6, rsi->as_VMReg());
92 reg_def RSI_H(SOC, SOE, Op_RegI, 6, rsi->as_VMReg()->next());
93
94 reg_def RDI (SOC, SOE, Op_RegI, 7, rdi->as_VMReg());
95 reg_def RDI_H(SOC, SOE, Op_RegI, 7, rdi->as_VMReg()->next());
96
97 #else
98
99 reg_def RSI (SOC, SOC, Op_RegI, 6, rsi->as_VMReg());
100 reg_def RSI_H(SOC, SOC, Op_RegI, 6, rsi->as_VMReg()->next());
101
102 reg_def RDI (SOC, SOC, Op_RegI, 7, rdi->as_VMReg());
103 reg_def RDI_H(SOC, SOC, Op_RegI, 7, rdi->as_VMReg()->next());
104
105 #endif
106
107 reg_def R8 (SOC, SOC, Op_RegI, 8, r8->as_VMReg());
108 reg_def R8_H (SOC, SOC, Op_RegI, 8, r8->as_VMReg()->next());
109
110 reg_def R9 (SOC, SOC, Op_RegI, 9, r9->as_VMReg());
111 reg_def R9_H (SOC, SOC, Op_RegI, 9, r9->as_VMReg()->next());
112
113 reg_def R10 (SOC, SOC, Op_RegI, 10, r10->as_VMReg());
114 reg_def R10_H(SOC, SOC, Op_RegI, 10, r10->as_VMReg()->next());
115
116 reg_def R11 (SOC, SOC, Op_RegI, 11, r11->as_VMReg());
117 reg_def R11_H(SOC, SOC, Op_RegI, 11, r11->as_VMReg()->next());
118
119 reg_def R12 (SOC, SOE, Op_RegI, 12, r12->as_VMReg());
120 reg_def R12_H(SOC, SOE, Op_RegI, 12, r12->as_VMReg()->next());
121
122 reg_def R13 (SOC, SOE, Op_RegI, 13, r13->as_VMReg());
123 reg_def R13_H(SOC, SOE, Op_RegI, 13, r13->as_VMReg()->next());
124
125 reg_def R14 (SOC, SOE, Op_RegI, 14, r14->as_VMReg());
126 reg_def R14_H(SOC, SOE, Op_RegI, 14, r14->as_VMReg()->next());
127
128 reg_def R15 (SOC, SOE, Op_RegI, 15, r15->as_VMReg());
129 reg_def R15_H(SOC, SOE, Op_RegI, 15, r15->as_VMReg()->next());
130
131
132 // Floating Point Registers
133
134 // Specify priority of register selection within phases of register
135 // allocation. Highest priority is first. A useful heuristic is to
136 // give registers a low priority when they are required by machine
137 // instructions, like EAX and EDX on I486, and choose no-save registers
138 // before save-on-call, & save-on-call before save-on-entry. Registers
139 // which participate in fixed calling sequences should come last.
140 // Registers which are used as pairs must fall on an even boundary.
141
142 alloc_class chunk0(R10, R10_H,
143 R11, R11_H,
144 R8, R8_H,
145 R9, R9_H,
146 R12, R12_H,
147 RCX, RCX_H,
148 RBX, RBX_H,
149 RDI, RDI_H,
150 RDX, RDX_H,
151 RSI, RSI_H,
152 RAX, RAX_H,
153 RBP, RBP_H,
154 R13, R13_H,
155 R14, R14_H,
156 R15, R15_H,
157 RSP, RSP_H);
158
159
160 //----------Architecture Description Register Classes--------------------------
161 // Several register classes are automatically defined based upon information in
162 // this architecture description.
163 // 1) reg_class inline_cache_reg ( /* as def'd in frame section */ )
164 // 2) reg_class compiler_method_oop_reg ( /* as def'd in frame section */ )
165 // 2) reg_class interpreter_method_oop_reg ( /* as def'd in frame section */ )
166 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
167 //
168
169 // Empty register class.
170 reg_class no_reg();
171
172 // Class for all pointer registers (including RSP and RBP)
173 reg_class any_reg_with_rbp(RAX, RAX_H,
174 RDX, RDX_H,
175 RBP, RBP_H,
176 RDI, RDI_H,
177 RSI, RSI_H,
178 RCX, RCX_H,
179 RBX, RBX_H,
180 RSP, RSP_H,
181 R8, R8_H,
182 R9, R9_H,
183 R10, R10_H,
184 R11, R11_H,
185 R12, R12_H,
186 R13, R13_H,
187 R14, R14_H,
188 R15, R15_H);
189
190 // Class for all pointer registers (including RSP, but excluding RBP)
191 reg_class any_reg_no_rbp(RAX, RAX_H,
192 RDX, RDX_H,
193 RDI, RDI_H,
194 RSI, RSI_H,
195 RCX, RCX_H,
196 RBX, RBX_H,
197 RSP, RSP_H,
198 R8, R8_H,
199 R9, R9_H,
200 R10, R10_H,
201 R11, R11_H,
202 R12, R12_H,
203 R13, R13_H,
204 R14, R14_H,
205 R15, R15_H);
206
207 // Dynamic register class that selects at runtime between register classes
208 // any_reg_no_rbp and any_reg_with_rbp (depending on the value of the flag PreserveFramePointer).
209 // Equivalent to: return PreserveFramePointer ? any_reg_no_rbp : any_reg_with_rbp;
210 reg_class_dynamic any_reg(any_reg_no_rbp, any_reg_with_rbp, %{ PreserveFramePointer %});
211
212 // Class for all pointer registers (excluding RSP)
213 reg_class ptr_reg_with_rbp(RAX, RAX_H,
214 RDX, RDX_H,
215 RBP, RBP_H,
216 RDI, RDI_H,
217 RSI, RSI_H,
218 RCX, RCX_H,
219 RBX, RBX_H,
220 R8, R8_H,
221 R9, R9_H,
222 R10, R10_H,
223 R11, R11_H,
224 R13, R13_H,
225 R14, R14_H);
226
227 // Class for all pointer registers (excluding RSP and RBP)
228 reg_class ptr_reg_no_rbp(RAX, RAX_H,
229 RDX, RDX_H,
230 RDI, RDI_H,
231 RSI, RSI_H,
232 RCX, RCX_H,
233 RBX, RBX_H,
234 R8, R8_H,
235 R9, R9_H,
236 R10, R10_H,
237 R11, R11_H,
238 R13, R13_H,
239 R14, R14_H);
240
241 // Dynamic register class that selects between ptr_reg_no_rbp and ptr_reg_with_rbp.
242 reg_class_dynamic ptr_reg(ptr_reg_no_rbp, ptr_reg_with_rbp, %{ PreserveFramePointer %});
243
244 // Class for all pointer registers (excluding RAX and RSP)
245 reg_class ptr_no_rax_reg_with_rbp(RDX, RDX_H,
246 RBP, RBP_H,
247 RDI, RDI_H,
248 RSI, RSI_H,
249 RCX, RCX_H,
250 RBX, RBX_H,
251 R8, R8_H,
252 R9, R9_H,
253 R10, R10_H,
254 R11, R11_H,
255 R13, R13_H,
256 R14, R14_H);
257
258 // Class for all pointer registers (excluding RAX, RSP, and RBP)
259 reg_class ptr_no_rax_reg_no_rbp(RDX, RDX_H,
260 RDI, RDI_H,
261 RSI, RSI_H,
262 RCX, RCX_H,
263 RBX, RBX_H,
264 R8, R8_H,
265 R9, R9_H,
266 R10, R10_H,
267 R11, R11_H,
268 R13, R13_H,
269 R14, R14_H);
270
271 // Dynamic register class that selects between ptr_no_rax_reg_no_rbp and ptr_no_rax_reg_with_rbp.
272 reg_class_dynamic ptr_no_rax_reg(ptr_no_rax_reg_no_rbp, ptr_no_rax_reg_with_rbp, %{ PreserveFramePointer %});
273
274 // Class for all pointer registers (excluding RAX, RBX, and RSP)
275 reg_class ptr_no_rax_rbx_reg_with_rbp(RDX, RDX_H,
276 RBP, RBP_H,
277 RDI, RDI_H,
278 RSI, RSI_H,
279 RCX, RCX_H,
280 R8, R8_H,
281 R9, R9_H,
282 R10, R10_H,
283 R11, R11_H,
284 R13, R13_H,
285 R14, R14_H);
286
287 // Class for all pointer registers (excluding RAX, RBX, RSP, and RBP)
288 reg_class ptr_no_rax_rbx_reg_no_rbp(RDX, RDX_H,
289 RDI, RDI_H,
290 RSI, RSI_H,
291 RCX, RCX_H,
292 R8, R8_H,
293 R9, R9_H,
294 R10, R10_H,
295 R11, R11_H,
296 R13, R13_H,
297 R14, R14_H);
298
299 // Dynamic register class that selects between ptr_no_rax_rbx_reg_no_rbp and ptr_no_rax_rbx_reg_with_rbp.
300 reg_class_dynamic ptr_no_rax_rbx_reg(ptr_no_rax_rbx_reg_no_rbp, ptr_no_rax_rbx_reg_with_rbp, %{ PreserveFramePointer %});
301
302 // Singleton class for RAX pointer register
303 reg_class ptr_rax_reg(RAX, RAX_H);
304
305 // Singleton class for RBX pointer register
306 reg_class ptr_rbx_reg(RBX, RBX_H);
307
308 // Singleton class for RSI pointer register
309 reg_class ptr_rsi_reg(RSI, RSI_H);
310
311 // Singleton class for RDI pointer register
312 reg_class ptr_rdi_reg(RDI, RDI_H);
313
314 // Singleton class for stack pointer
315 reg_class ptr_rsp_reg(RSP, RSP_H);
316
317 // Singleton class for TLS pointer
318 reg_class ptr_r15_reg(R15, R15_H);
319
320 // Class for all long registers (excluding RSP)
321 reg_class long_reg_with_rbp(RAX, RAX_H,
322 RDX, RDX_H,
323 RBP, RBP_H,
324 RDI, RDI_H,
325 RSI, RSI_H,
326 RCX, RCX_H,
327 RBX, RBX_H,
328 R8, R8_H,
329 R9, R9_H,
330 R10, R10_H,
331 R11, R11_H,
332 R13, R13_H,
333 R14, R14_H);
334
335 // Class for all long registers (excluding RSP and RBP)
336 reg_class long_reg_no_rbp(RAX, RAX_H,
337 RDX, RDX_H,
338 RDI, RDI_H,
339 RSI, RSI_H,
340 RCX, RCX_H,
341 RBX, RBX_H,
342 R8, R8_H,
343 R9, R9_H,
344 R10, R10_H,
345 R11, R11_H,
346 R13, R13_H,
347 R14, R14_H);
348
349 // Dynamic register class that selects between long_reg_no_rbp and long_reg_with_rbp.
350 reg_class_dynamic long_reg(long_reg_no_rbp, long_reg_with_rbp, %{ PreserveFramePointer %});
351
352 // Class for all long registers (excluding RAX, RDX and RSP)
353 reg_class long_no_rax_rdx_reg_with_rbp(RBP, RBP_H,
354 RDI, RDI_H,
355 RSI, RSI_H,
356 RCX, RCX_H,
357 RBX, RBX_H,
358 R8, R8_H,
359 R9, R9_H,
360 R10, R10_H,
361 R11, R11_H,
362 R13, R13_H,
363 R14, R14_H);
364
365 // Class for all long registers (excluding RAX, RDX, RSP, and RBP)
366 reg_class long_no_rax_rdx_reg_no_rbp(RDI, RDI_H,
367 RSI, RSI_H,
368 RCX, RCX_H,
369 RBX, RBX_H,
370 R8, R8_H,
371 R9, R9_H,
372 R10, R10_H,
373 R11, R11_H,
374 R13, R13_H,
375 R14, R14_H);
376
377 // Dynamic register class that selects between long_no_rax_rdx_reg_no_rbp and long_no_rax_rdx_reg_with_rbp.
378 reg_class_dynamic long_no_rax_rdx_reg(long_no_rax_rdx_reg_no_rbp, long_no_rax_rdx_reg_with_rbp, %{ PreserveFramePointer %});
379
380 // Class for all long registers (excluding RCX and RSP)
381 reg_class long_no_rcx_reg_with_rbp(RBP, RBP_H,
382 RDI, RDI_H,
383 RSI, RSI_H,
384 RAX, RAX_H,
385 RDX, RDX_H,
386 RBX, RBX_H,
387 R8, R8_H,
388 R9, R9_H,
389 R10, R10_H,
390 R11, R11_H,
391 R13, R13_H,
392 R14, R14_H);
393
394 // Class for all long registers (excluding RCX, RSP, and RBP)
395 reg_class long_no_rcx_reg_no_rbp(RDI, RDI_H,
396 RSI, RSI_H,
397 RAX, RAX_H,
398 RDX, RDX_H,
399 RBX, RBX_H,
400 R8, R8_H,
401 R9, R9_H,
402 R10, R10_H,
403 R11, R11_H,
404 R13, R13_H,
405 R14, R14_H);
406
407 // Dynamic register class that selects between long_no_rcx_reg_no_rbp and long_no_rcx_reg_with_rbp.
408 reg_class_dynamic long_no_rcx_reg(long_no_rcx_reg_no_rbp, long_no_rcx_reg_with_rbp, %{ PreserveFramePointer %});
409
410 // Singleton class for RAX long register
411 reg_class long_rax_reg(RAX, RAX_H);
412
413 // Singleton class for RCX long register
414 reg_class long_rcx_reg(RCX, RCX_H);
415
416 // Singleton class for RDX long register
417 reg_class long_rdx_reg(RDX, RDX_H);
418
419 // Class for all int registers (excluding RSP)
420 reg_class int_reg_with_rbp(RAX,
421 RDX,
422 RBP,
423 RDI,
424 RSI,
425 RCX,
426 RBX,
427 R8,
428 R9,
429 R10,
430 R11,
431 R13,
432 R14);
433
434 // Class for all int registers (excluding RSP and RBP)
435 reg_class int_reg_no_rbp(RAX,
436 RDX,
437 RDI,
438 RSI,
439 RCX,
440 RBX,
441 R8,
442 R9,
443 R10,
444 R11,
445 R13,
446 R14);
447
448 // Dynamic register class that selects between int_reg_no_rbp and int_reg_with_rbp.
449 reg_class_dynamic int_reg(int_reg_no_rbp, int_reg_with_rbp, %{ PreserveFramePointer %});
450
451 // Class for all int registers (excluding RCX and RSP)
452 reg_class int_no_rcx_reg_with_rbp(RAX,
453 RDX,
454 RBP,
455 RDI,
456 RSI,
457 RBX,
458 R8,
459 R9,
460 R10,
461 R11,
462 R13,
463 R14);
464
465 // Class for all int registers (excluding RCX, RSP, and RBP)
466 reg_class int_no_rcx_reg_no_rbp(RAX,
467 RDX,
468 RDI,
469 RSI,
470 RBX,
471 R8,
472 R9,
473 R10,
474 R11,
475 R13,
476 R14);
477
478 // Dynamic register class that selects between int_no_rcx_reg_no_rbp and int_no_rcx_reg_with_rbp.
479 reg_class_dynamic int_no_rcx_reg(int_no_rcx_reg_no_rbp, int_no_rcx_reg_with_rbp, %{ PreserveFramePointer %});
480
481 // Class for all int registers (excluding RAX, RDX, and RSP)
482 reg_class int_no_rax_rdx_reg_with_rbp(RBP,
483 RDI,
484 RSI,
485 RCX,
486 RBX,
487 R8,
488 R9,
489 R10,
490 R11,
491 R13,
492 R14);
493
494 // Class for all int registers (excluding RAX, RDX, RSP, and RBP)
495 reg_class int_no_rax_rdx_reg_no_rbp(RDI,
496 RSI,
497 RCX,
498 RBX,
499 R8,
500 R9,
501 R10,
502 R11,
503 R13,
504 R14);
505
506 // Dynamic register class that selects between int_no_rax_rdx_reg_no_rbp and int_no_rax_rdx_reg_with_rbp.
507 reg_class_dynamic int_no_rax_rdx_reg(int_no_rax_rdx_reg_no_rbp, int_no_rax_rdx_reg_with_rbp, %{ PreserveFramePointer %});
508
509 // Singleton class for RAX int register
510 reg_class int_rax_reg(RAX);
511
512 // Singleton class for RBX int register
513 reg_class int_rbx_reg(RBX);
514
515 // Singleton class for RCX int register
516 reg_class int_rcx_reg(RCX);
517
518 // Singleton class for RCX int register
519 reg_class int_rdx_reg(RDX);
520
521 // Singleton class for RCX int register
522 reg_class int_rdi_reg(RDI);
523
524 // Singleton class for instruction pointer
525 // reg_class ip_reg(RIP);
526
527 %}
528
529 //----------SOURCE BLOCK-------------------------------------------------------
530 // This is a block of C++ code which provides values, functions, and
531 // definitions necessary in the rest of the architecture description
532 source %{
533 #define RELOC_IMM64 Assembler::imm_operand
534 #define RELOC_DISP32 Assembler::disp32_operand
535
536 #define __ _masm.
537
538 static int clear_avx_size() {
539 return (Compile::current()->max_vector_size() > 16) ? 3 : 0; // vzeroupper
540 }
541
542 // !!!!! Special hack to get all types of calls to specify the byte offset
543 // from the start of the call to the point where the return address
544 // will point.
545 int MachCallStaticJavaNode::ret_addr_offset()
546 {
547 int offset = 5; // 5 bytes from start of call to where return address points
548 offset += clear_avx_size();
549 return offset;
550 }
551
552 int MachCallDynamicJavaNode::ret_addr_offset()
553 {
554 int offset = 15; // 15 bytes from start of call to where return address points
555 offset += clear_avx_size();
556 return offset;
557 }
558
559 int MachCallRuntimeNode::ret_addr_offset() {
560 int offset = 13; // movq r10,#addr; callq (r10)
561 offset += clear_avx_size();
562 return offset;
563 }
564
565 // Indicate if the safepoint node needs the polling page as an input,
566 // it does if the polling page is more than disp32 away.
567 bool SafePointNode::needs_polling_address_input()
568 {
569 return Assembler::is_polling_page_far();
570 }
571
572 //
573 // Compute padding required for nodes which need alignment
574 //
575
576 // The address of the call instruction needs to be 4-byte aligned to
577 // ensure that it does not span a cache line so that it can be patched.
578 int CallStaticJavaDirectNode::compute_padding(int current_offset) const
579 {
580 current_offset += clear_avx_size(); // skip vzeroupper
581 current_offset += 1; // skip call opcode byte
582 return round_to(current_offset, alignment_required()) - current_offset;
583 }
584
585 // The address of the call instruction needs to be 4-byte aligned to
586 // ensure that it does not span a cache line so that it can be patched.
587 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const
588 {
589 current_offset += clear_avx_size(); // skip vzeroupper
590 current_offset += 11; // skip movq instruction + call opcode byte
591 return round_to(current_offset, alignment_required()) - current_offset;
592 }
593
594 // EMIT_RM()
595 void emit_rm(CodeBuffer &cbuf, int f1, int f2, int f3) {
596 unsigned char c = (unsigned char) ((f1 << 6) | (f2 << 3) | f3);
597 cbuf.insts()->emit_int8(c);
598 }
599
600 // EMIT_CC()
601 void emit_cc(CodeBuffer &cbuf, int f1, int f2) {
602 unsigned char c = (unsigned char) (f1 | f2);
603 cbuf.insts()->emit_int8(c);
604 }
605
606 // EMIT_OPCODE()
607 void emit_opcode(CodeBuffer &cbuf, int code) {
608 cbuf.insts()->emit_int8((unsigned char) code);
609 }
610
611 // EMIT_OPCODE() w/ relocation information
612 void emit_opcode(CodeBuffer &cbuf,
613 int code, relocInfo::relocType reloc, int offset, int format)
614 {
615 cbuf.relocate(cbuf.insts_mark() + offset, reloc, format);
616 emit_opcode(cbuf, code);
617 }
618
619 // EMIT_D8()
620 void emit_d8(CodeBuffer &cbuf, int d8) {
621 cbuf.insts()->emit_int8((unsigned char) d8);
622 }
623
624 // EMIT_D16()
625 void emit_d16(CodeBuffer &cbuf, int d16) {
626 cbuf.insts()->emit_int16(d16);
627 }
628
629 // EMIT_D32()
630 void emit_d32(CodeBuffer &cbuf, int d32) {
631 cbuf.insts()->emit_int32(d32);
632 }
633
634 // EMIT_D64()
635 void emit_d64(CodeBuffer &cbuf, int64_t d64) {
636 cbuf.insts()->emit_int64(d64);
637 }
638
639 // emit 32 bit value and construct relocation entry from relocInfo::relocType
640 void emit_d32_reloc(CodeBuffer& cbuf,
641 int d32,
642 relocInfo::relocType reloc,
643 int format)
644 {
645 assert(reloc != relocInfo::external_word_type, "use 2-arg emit_d32_reloc");
646 cbuf.relocate(cbuf.insts_mark(), reloc, format);
647 cbuf.insts()->emit_int32(d32);
648 }
649
650 // emit 32 bit value and construct relocation entry from RelocationHolder
651 void emit_d32_reloc(CodeBuffer& cbuf, int d32, RelocationHolder const& rspec, int format) {
652 #ifdef ASSERT
653 if (rspec.reloc()->type() == relocInfo::oop_type &&
654 d32 != 0 && d32 != (intptr_t) Universe::non_oop_word()) {
655 assert(Universe::heap()->is_in_reserved((address)(intptr_t)d32), "should be real oop");
656 assert(cast_to_oop((intptr_t)d32)->is_oop() && (ScavengeRootsInCode || !cast_to_oop((intptr_t)d32)->is_scavengable()), "cannot embed scavengable oops in code");
657 }
658 #endif
659 cbuf.relocate(cbuf.insts_mark(), rspec, format);
660 cbuf.insts()->emit_int32(d32);
661 }
662
663 void emit_d32_reloc(CodeBuffer& cbuf, address addr) {
664 address next_ip = cbuf.insts_end() + 4;
665 emit_d32_reloc(cbuf, (int) (addr - next_ip),
666 external_word_Relocation::spec(addr),
667 RELOC_DISP32);
668 }
669
670
671 // emit 64 bit value and construct relocation entry from relocInfo::relocType
672 void emit_d64_reloc(CodeBuffer& cbuf, int64_t d64, relocInfo::relocType reloc, int format) {
673 cbuf.relocate(cbuf.insts_mark(), reloc, format);
674 cbuf.insts()->emit_int64(d64);
675 }
676
677 // emit 64 bit value and construct relocation entry from RelocationHolder
678 void emit_d64_reloc(CodeBuffer& cbuf, int64_t d64, RelocationHolder const& rspec, int format) {
679 #ifdef ASSERT
680 if (rspec.reloc()->type() == relocInfo::oop_type &&
681 d64 != 0 && d64 != (int64_t) Universe::non_oop_word()) {
682 assert(Universe::heap()->is_in_reserved((address)d64), "should be real oop");
683 assert(cast_to_oop(d64)->is_oop() && (ScavengeRootsInCode || !cast_to_oop(d64)->is_scavengable()),
684 "cannot embed scavengable oops in code");
685 }
686 #endif
687 cbuf.relocate(cbuf.insts_mark(), rspec, format);
688 cbuf.insts()->emit_int64(d64);
689 }
690
691 // Access stack slot for load or store
692 void store_to_stackslot(CodeBuffer &cbuf, int opcode, int rm_field, int disp)
693 {
694 emit_opcode(cbuf, opcode); // (e.g., FILD [RSP+src])
695 if (-0x80 <= disp && disp < 0x80) {
696 emit_rm(cbuf, 0x01, rm_field, RSP_enc); // R/M byte
697 emit_rm(cbuf, 0x00, RSP_enc, RSP_enc); // SIB byte
698 emit_d8(cbuf, disp); // Displacement // R/M byte
699 } else {
700 emit_rm(cbuf, 0x02, rm_field, RSP_enc); // R/M byte
701 emit_rm(cbuf, 0x00, RSP_enc, RSP_enc); // SIB byte
702 emit_d32(cbuf, disp); // Displacement // R/M byte
703 }
704 }
705
706 // rRegI ereg, memory mem) %{ // emit_reg_mem
707 void encode_RegMem(CodeBuffer &cbuf,
708 int reg,
709 int base, int index, int scale, int disp, relocInfo::relocType disp_reloc)
710 {
711 assert(disp_reloc == relocInfo::none, "cannot have disp");
712 int regenc = reg & 7;
713 int baseenc = base & 7;
714 int indexenc = index & 7;
715
716 // There is no index & no scale, use form without SIB byte
717 if (index == 0x4 && scale == 0 && base != RSP_enc && base != R12_enc) {
718 // If no displacement, mode is 0x0; unless base is [RBP] or [R13]
719 if (disp == 0 && base != RBP_enc && base != R13_enc) {
720 emit_rm(cbuf, 0x0, regenc, baseenc); // *
721 } else if (-0x80 <= disp && disp < 0x80 && disp_reloc == relocInfo::none) {
722 // If 8-bit displacement, mode 0x1
723 emit_rm(cbuf, 0x1, regenc, baseenc); // *
724 emit_d8(cbuf, disp);
725 } else {
726 // If 32-bit displacement
727 if (base == -1) { // Special flag for absolute address
728 emit_rm(cbuf, 0x0, regenc, 0x5); // *
729 if (disp_reloc != relocInfo::none) {
730 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);
731 } else {
732 emit_d32(cbuf, disp);
733 }
734 } else {
735 // Normal base + offset
736 emit_rm(cbuf, 0x2, regenc, baseenc); // *
737 if (disp_reloc != relocInfo::none) {
738 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);
739 } else {
740 emit_d32(cbuf, disp);
741 }
742 }
743 }
744 } else {
745 // Else, encode with the SIB byte
746 // If no displacement, mode is 0x0; unless base is [RBP] or [R13]
747 if (disp == 0 && base != RBP_enc && base != R13_enc) {
748 // If no displacement
749 emit_rm(cbuf, 0x0, regenc, 0x4); // *
750 emit_rm(cbuf, scale, indexenc, baseenc);
751 } else {
752 if (-0x80 <= disp && disp < 0x80 && disp_reloc == relocInfo::none) {
753 // If 8-bit displacement, mode 0x1
754 emit_rm(cbuf, 0x1, regenc, 0x4); // *
755 emit_rm(cbuf, scale, indexenc, baseenc);
756 emit_d8(cbuf, disp);
757 } else {
758 // If 32-bit displacement
759 if (base == 0x04 ) {
760 emit_rm(cbuf, 0x2, regenc, 0x4);
761 emit_rm(cbuf, scale, indexenc, 0x04); // XXX is this valid???
762 } else {
763 emit_rm(cbuf, 0x2, regenc, 0x4);
764 emit_rm(cbuf, scale, indexenc, baseenc); // *
765 }
766 if (disp_reloc != relocInfo::none) {
767 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);
768 } else {
769 emit_d32(cbuf, disp);
770 }
771 }
772 }
773 }
774 }
775
776 // This could be in MacroAssembler but it's fairly C2 specific
777 void emit_cmpfp_fixup(MacroAssembler& _masm) {
778 Label exit;
779 __ jccb(Assembler::noParity, exit);
780 __ pushf();
781 //
782 // comiss/ucomiss instructions set ZF,PF,CF flags and
783 // zero OF,AF,SF for NaN values.
784 // Fixup flags by zeroing ZF,PF so that compare of NaN
785 // values returns 'less than' result (CF is set).
786 // Leave the rest of flags unchanged.
787 //
788 // 7 6 5 4 3 2 1 0
789 // |S|Z|r|A|r|P|r|C| (r - reserved bit)
790 // 0 0 1 0 1 0 1 1 (0x2B)
791 //
792 __ andq(Address(rsp, 0), 0xffffff2b);
793 __ popf();
794 __ bind(exit);
795 }
796
797 void emit_cmpfp3(MacroAssembler& _masm, Register dst) {
798 Label done;
799 __ movl(dst, -1);
800 __ jcc(Assembler::parity, done);
801 __ jcc(Assembler::below, done);
802 __ setb(Assembler::notEqual, dst);
803 __ movzbl(dst, dst);
804 __ bind(done);
805 }
806
807
808 //=============================================================================
809 const RegMask& MachConstantBaseNode::_out_RegMask = RegMask::Empty;
810
811 int Compile::ConstantTable::calculate_table_base_offset() const {
812 return 0; // absolute addressing, no offset
813 }
814
815 bool MachConstantBaseNode::requires_postalloc_expand() const { return false; }
816 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) {
817 ShouldNotReachHere();
818 }
819
820 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
821 // Empty encoding
822 }
823
824 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {
825 return 0;
826 }
827
828 #ifndef PRODUCT
829 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
830 st->print("# MachConstantBaseNode (empty encoding)");
831 }
832 #endif
833
834
835 //=============================================================================
836 #ifndef PRODUCT
837 void MachPrologNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
838 Compile* C = ra_->C;
839
840 int framesize = C->frame_size_in_bytes();
841 int bangsize = C->bang_size_in_bytes();
842 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
843 // Remove wordSize for return addr which is already pushed.
844 framesize -= wordSize;
845
846 if (C->need_stack_bang(bangsize)) {
847 framesize -= wordSize;
848 st->print("# stack bang (%d bytes)", bangsize);
849 st->print("\n\t");
850 st->print("pushq rbp\t# Save rbp");
851 if (PreserveFramePointer) {
852 st->print("\n\t");
853 st->print("movq rbp, rsp\t# Save the caller's SP into rbp");
854 }
855 if (framesize) {
856 st->print("\n\t");
857 st->print("subq rsp, #%d\t# Create frame",framesize);
858 }
859 } else {
860 st->print("subq rsp, #%d\t# Create frame",framesize);
861 st->print("\n\t");
862 framesize -= wordSize;
863 st->print("movq [rsp + #%d], rbp\t# Save rbp",framesize);
864 if (PreserveFramePointer) {
865 st->print("\n\t");
866 st->print("movq rbp, rsp\t# Save the caller's SP into rbp");
867 if (framesize > 0) {
868 st->print("\n\t");
869 st->print("addq rbp, #%d", framesize);
870 }
871 }
872 }
873
874 if (VerifyStackAtCalls) {
875 st->print("\n\t");
876 framesize -= wordSize;
877 st->print("movq [rsp + #%d], 0xbadb100d\t# Majik cookie for stack depth check",framesize);
878 #ifdef ASSERT
879 st->print("\n\t");
880 st->print("# stack alignment check");
881 #endif
882 }
883 st->cr();
884 }
885 #endif
886
887 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
888 Compile* C = ra_->C;
889 MacroAssembler _masm(&cbuf);
890
891 int framesize = C->frame_size_in_bytes();
892 int bangsize = C->bang_size_in_bytes();
893
894 __ verified_entry(framesize, C->need_stack_bang(bangsize)?bangsize:0, false);
895
896 C->set_frame_complete(cbuf.insts_size());
897
898 if (C->has_mach_constant_base_node()) {
899 // NOTE: We set the table base offset here because users might be
900 // emitted before MachConstantBaseNode.
901 Compile::ConstantTable& constant_table = C->constant_table();
902 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset());
903 }
904 }
905
906 uint MachPrologNode::size(PhaseRegAlloc* ra_) const
907 {
908 return MachNode::size(ra_); // too many variables; just compute it
909 // the hard way
910 }
911
912 int MachPrologNode::reloc() const
913 {
914 return 0; // a large enough number
915 }
916
917 //=============================================================================
918 #ifndef PRODUCT
919 void MachEpilogNode::format(PhaseRegAlloc* ra_, outputStream* st) const
920 {
921 Compile* C = ra_->C;
922 if (C->max_vector_size() > 16) {
923 st->print("vzeroupper");
924 st->cr(); st->print("\t");
925 }
926
927 int framesize = C->frame_size_in_bytes();
928 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
929 // Remove word for return adr already pushed
930 // and RBP
931 framesize -= 2*wordSize;
932
933 if (framesize) {
934 st->print_cr("addq rsp, %d\t# Destroy frame", framesize);
935 st->print("\t");
936 }
937
938 st->print_cr("popq rbp");
939 if (do_polling() && C->is_method_compilation()) {
940 st->print("\t");
941 if (Assembler::is_polling_page_far()) {
942 st->print_cr("movq rscratch1, #polling_page_address\n\t"
943 "testl rax, [rscratch1]\t"
944 "# Safepoint: poll for GC");
945 } else {
946 st->print_cr("testl rax, [rip + #offset_to_poll_page]\t"
947 "# Safepoint: poll for GC");
948 }
949 }
950 }
951 #endif
952
953 void MachEpilogNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
954 {
955 Compile* C = ra_->C;
956 MacroAssembler _masm(&cbuf);
957
958 if (C->max_vector_size() > 16) {
959 // Clear upper bits of YMM registers when current compiled code uses
960 // wide vectors to avoid AVX <-> SSE transition penalty during call.
961 __ vzeroupper();
962 }
963
964 int framesize = C->frame_size_in_bytes();
965 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
966 // Remove word for return adr already pushed
967 // and RBP
968 framesize -= 2*wordSize;
969
970 // Note that VerifyStackAtCalls' Majik cookie does not change the frame size popped here
971
972 if (framesize) {
973 emit_opcode(cbuf, Assembler::REX_W);
974 if (framesize < 0x80) {
975 emit_opcode(cbuf, 0x83); // addq rsp, #framesize
976 emit_rm(cbuf, 0x3, 0x00, RSP_enc);
977 emit_d8(cbuf, framesize);
978 } else {
979 emit_opcode(cbuf, 0x81); // addq rsp, #framesize
980 emit_rm(cbuf, 0x3, 0x00, RSP_enc);
981 emit_d32(cbuf, framesize);
982 }
983 }
984
985 // popq rbp
986 emit_opcode(cbuf, 0x58 | RBP_enc);
987
988 if (StackReservedPages > 0 && C->has_reserved_stack_access()) {
989 __ reserved_stack_check();
990 }
991
992 if (do_polling() && C->is_method_compilation()) {
993 MacroAssembler _masm(&cbuf);
994 AddressLiteral polling_page(os::get_polling_page(), relocInfo::poll_return_type);
995 if (Assembler::is_polling_page_far()) {
996 __ lea(rscratch1, polling_page);
997 __ relocate(relocInfo::poll_return_type);
998 __ testl(rax, Address(rscratch1, 0));
999 } else {
1000 __ testl(rax, polling_page);
1001 }
1002 }
1003 }
1004
1005 uint MachEpilogNode::size(PhaseRegAlloc* ra_) const
1006 {
1007 return MachNode::size(ra_); // too many variables; just compute it
1008 // the hard way
1009 }
1010
1011 int MachEpilogNode::reloc() const
1012 {
1013 return 2; // a large enough number
1014 }
1015
1016 const Pipeline* MachEpilogNode::pipeline() const
1017 {
1018 return MachNode::pipeline_class();
1019 }
1020
1021 int MachEpilogNode::safepoint_offset() const
1022 {
1023 return 0;
1024 }
1025
1026 //=============================================================================
1027
1028 enum RC {
1029 rc_bad,
1030 rc_int,
1031 rc_float,
1032 rc_stack
1033 };
1034
1035 static enum RC rc_class(OptoReg::Name reg)
1036 {
1037 if( !OptoReg::is_valid(reg) ) return rc_bad;
1038
1039 if (OptoReg::is_stack(reg)) return rc_stack;
1040
1041 VMReg r = OptoReg::as_VMReg(reg);
1042
1043 if (r->is_Register()) return rc_int;
1044
1045 assert(r->is_XMMRegister(), "must be");
1046 return rc_float;
1047 }
1048
1049 // Next two methods are shared by 32- and 64-bit VM. They are defined in x86.ad.
1050 static int vec_mov_helper(CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
1051 int src_hi, int dst_hi, uint ireg, outputStream* st);
1052
1053 static int vec_spill_helper(CodeBuffer *cbuf, bool do_size, bool is_load,
1054 int stack_offset, int reg, uint ireg, outputStream* st);
1055
1056 static void vec_stack_to_stack_helper(CodeBuffer *cbuf, int src_offset,
1057 int dst_offset, uint ireg, outputStream* st) {
1058 if (cbuf) {
1059 MacroAssembler _masm(cbuf);
1060 switch (ireg) {
1061 case Op_VecS:
1062 __ movq(Address(rsp, -8), rax);
1063 __ movl(rax, Address(rsp, src_offset));
1064 __ movl(Address(rsp, dst_offset), rax);
1065 __ movq(rax, Address(rsp, -8));
1066 break;
1067 case Op_VecD:
1068 __ pushq(Address(rsp, src_offset));
1069 __ popq (Address(rsp, dst_offset));
1070 break;
1071 case Op_VecX:
1072 __ pushq(Address(rsp, src_offset));
1073 __ popq (Address(rsp, dst_offset));
1074 __ pushq(Address(rsp, src_offset+8));
1075 __ popq (Address(rsp, dst_offset+8));
1076 break;
1077 case Op_VecY:
1078 __ vmovdqu(Address(rsp, -32), xmm0);
1079 __ vmovdqu(xmm0, Address(rsp, src_offset));
1080 __ vmovdqu(Address(rsp, dst_offset), xmm0);
1081 __ vmovdqu(xmm0, Address(rsp, -32));
1082 break;
1083 case Op_VecZ:
1084 __ evmovdquq(Address(rsp, -64), xmm0, 2);
1085 __ evmovdquq(xmm0, Address(rsp, src_offset), 2);
1086 __ evmovdquq(Address(rsp, dst_offset), xmm0, 2);
1087 __ evmovdquq(xmm0, Address(rsp, -64), 2);
1088 break;
1089 default:
1090 ShouldNotReachHere();
1091 }
1092 #ifndef PRODUCT
1093 } else {
1094 switch (ireg) {
1095 case Op_VecS:
1096 st->print("movq [rsp - #8], rax\t# 32-bit mem-mem spill\n\t"
1097 "movl rax, [rsp + #%d]\n\t"
1098 "movl [rsp + #%d], rax\n\t"
1099 "movq rax, [rsp - #8]",
1100 src_offset, dst_offset);
1101 break;
1102 case Op_VecD:
1103 st->print("pushq [rsp + #%d]\t# 64-bit mem-mem spill\n\t"
1104 "popq [rsp + #%d]",
1105 src_offset, dst_offset);
1106 break;
1107 case Op_VecX:
1108 st->print("pushq [rsp + #%d]\t# 128-bit mem-mem spill\n\t"
1109 "popq [rsp + #%d]\n\t"
1110 "pushq [rsp + #%d]\n\t"
1111 "popq [rsp + #%d]",
1112 src_offset, dst_offset, src_offset+8, dst_offset+8);
1113 break;
1114 case Op_VecY:
1115 st->print("vmovdqu [rsp - #32], xmm0\t# 256-bit mem-mem spill\n\t"
1116 "vmovdqu xmm0, [rsp + #%d]\n\t"
1117 "vmovdqu [rsp + #%d], xmm0\n\t"
1118 "vmovdqu xmm0, [rsp - #32]",
1119 src_offset, dst_offset);
1120 break;
1121 case Op_VecZ:
1122 st->print("vmovdqu [rsp - #64], xmm0\t# 512-bit mem-mem spill\n\t"
1123 "vmovdqu xmm0, [rsp + #%d]\n\t"
1124 "vmovdqu [rsp + #%d], xmm0\n\t"
1125 "vmovdqu xmm0, [rsp - #64]",
1126 src_offset, dst_offset);
1127 break;
1128 default:
1129 ShouldNotReachHere();
1130 }
1131 #endif
1132 }
1133 }
1134
1135 uint MachSpillCopyNode::implementation(CodeBuffer* cbuf,
1136 PhaseRegAlloc* ra_,
1137 bool do_size,
1138 outputStream* st) const {
1139 assert(cbuf != NULL || st != NULL, "sanity");
1140 // Get registers to move
1141 OptoReg::Name src_second = ra_->get_reg_second(in(1));
1142 OptoReg::Name src_first = ra_->get_reg_first(in(1));
1143 OptoReg::Name dst_second = ra_->get_reg_second(this);
1144 OptoReg::Name dst_first = ra_->get_reg_first(this);
1145
1146 enum RC src_second_rc = rc_class(src_second);
1147 enum RC src_first_rc = rc_class(src_first);
1148 enum RC dst_second_rc = rc_class(dst_second);
1149 enum RC dst_first_rc = rc_class(dst_first);
1150
1151 assert(OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first),
1152 "must move at least 1 register" );
1153
1154 if (src_first == dst_first && src_second == dst_second) {
1155 // Self copy, no move
1156 return 0;
1157 }
1158 if (bottom_type()->isa_vect() != NULL) {
1159 uint ireg = ideal_reg();
1160 assert((src_first_rc != rc_int && dst_first_rc != rc_int), "sanity");
1161 assert((ireg == Op_VecS || ireg == Op_VecD || ireg == Op_VecX || ireg == Op_VecY || ireg == Op_VecZ ), "sanity");
1162 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
1163 // mem -> mem
1164 int src_offset = ra_->reg2offset(src_first);
1165 int dst_offset = ra_->reg2offset(dst_first);
1166 vec_stack_to_stack_helper(cbuf, src_offset, dst_offset, ireg, st);
1167 } else if (src_first_rc == rc_float && dst_first_rc == rc_float ) {
1168 vec_mov_helper(cbuf, false, src_first, dst_first, src_second, dst_second, ireg, st);
1169 } else if (src_first_rc == rc_float && dst_first_rc == rc_stack ) {
1170 int stack_offset = ra_->reg2offset(dst_first);
1171 vec_spill_helper(cbuf, false, false, stack_offset, src_first, ireg, st);
1172 } else if (src_first_rc == rc_stack && dst_first_rc == rc_float ) {
1173 int stack_offset = ra_->reg2offset(src_first);
1174 vec_spill_helper(cbuf, false, true, stack_offset, dst_first, ireg, st);
1175 } else {
1176 ShouldNotReachHere();
1177 }
1178 return 0;
1179 }
1180 if (src_first_rc == rc_stack) {
1181 // mem ->
1182 if (dst_first_rc == rc_stack) {
1183 // mem -> mem
1184 assert(src_second != dst_first, "overlap");
1185 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1186 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1187 // 64-bit
1188 int src_offset = ra_->reg2offset(src_first);
1189 int dst_offset = ra_->reg2offset(dst_first);
1190 if (cbuf) {
1191 MacroAssembler _masm(cbuf);
1192 __ pushq(Address(rsp, src_offset));
1193 __ popq (Address(rsp, dst_offset));
1194 #ifndef PRODUCT
1195 } else {
1196 st->print("pushq [rsp + #%d]\t# 64-bit mem-mem spill\n\t"
1197 "popq [rsp + #%d]",
1198 src_offset, dst_offset);
1199 #endif
1200 }
1201 } else {
1202 // 32-bit
1203 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1204 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1205 // No pushl/popl, so:
1206 int src_offset = ra_->reg2offset(src_first);
1207 int dst_offset = ra_->reg2offset(dst_first);
1208 if (cbuf) {
1209 MacroAssembler _masm(cbuf);
1210 __ movq(Address(rsp, -8), rax);
1211 __ movl(rax, Address(rsp, src_offset));
1212 __ movl(Address(rsp, dst_offset), rax);
1213 __ movq(rax, Address(rsp, -8));
1214 #ifndef PRODUCT
1215 } else {
1216 st->print("movq [rsp - #8], rax\t# 32-bit mem-mem spill\n\t"
1217 "movl rax, [rsp + #%d]\n\t"
1218 "movl [rsp + #%d], rax\n\t"
1219 "movq rax, [rsp - #8]",
1220 src_offset, dst_offset);
1221 #endif
1222 }
1223 }
1224 return 0;
1225 } else if (dst_first_rc == rc_int) {
1226 // mem -> gpr
1227 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1228 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1229 // 64-bit
1230 int offset = ra_->reg2offset(src_first);
1231 if (cbuf) {
1232 MacroAssembler _masm(cbuf);
1233 __ movq(as_Register(Matcher::_regEncode[dst_first]), Address(rsp, offset));
1234 #ifndef PRODUCT
1235 } else {
1236 st->print("movq %s, [rsp + #%d]\t# spill",
1237 Matcher::regName[dst_first],
1238 offset);
1239 #endif
1240 }
1241 } else {
1242 // 32-bit
1243 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1244 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1245 int offset = ra_->reg2offset(src_first);
1246 if (cbuf) {
1247 MacroAssembler _masm(cbuf);
1248 __ movl(as_Register(Matcher::_regEncode[dst_first]), Address(rsp, offset));
1249 #ifndef PRODUCT
1250 } else {
1251 st->print("movl %s, [rsp + #%d]\t# spill",
1252 Matcher::regName[dst_first],
1253 offset);
1254 #endif
1255 }
1256 }
1257 return 0;
1258 } else if (dst_first_rc == rc_float) {
1259 // mem-> xmm
1260 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1261 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1262 // 64-bit
1263 int offset = ra_->reg2offset(src_first);
1264 if (cbuf) {
1265 MacroAssembler _masm(cbuf);
1266 __ movdbl( as_XMMRegister(Matcher::_regEncode[dst_first]), Address(rsp, offset));
1267 #ifndef PRODUCT
1268 } else {
1269 st->print("%s %s, [rsp + #%d]\t# spill",
1270 UseXmmLoadAndClearUpper ? "movsd " : "movlpd",
1271 Matcher::regName[dst_first],
1272 offset);
1273 #endif
1274 }
1275 } else {
1276 // 32-bit
1277 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1278 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1279 int offset = ra_->reg2offset(src_first);
1280 if (cbuf) {
1281 MacroAssembler _masm(cbuf);
1282 __ movflt( as_XMMRegister(Matcher::_regEncode[dst_first]), Address(rsp, offset));
1283 #ifndef PRODUCT
1284 } else {
1285 st->print("movss %s, [rsp + #%d]\t# spill",
1286 Matcher::regName[dst_first],
1287 offset);
1288 #endif
1289 }
1290 }
1291 return 0;
1292 }
1293 } else if (src_first_rc == rc_int) {
1294 // gpr ->
1295 if (dst_first_rc == rc_stack) {
1296 // gpr -> mem
1297 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1298 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1299 // 64-bit
1300 int offset = ra_->reg2offset(dst_first);
1301 if (cbuf) {
1302 MacroAssembler _masm(cbuf);
1303 __ movq(Address(rsp, offset), as_Register(Matcher::_regEncode[src_first]));
1304 #ifndef PRODUCT
1305 } else {
1306 st->print("movq [rsp + #%d], %s\t# spill",
1307 offset,
1308 Matcher::regName[src_first]);
1309 #endif
1310 }
1311 } else {
1312 // 32-bit
1313 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1314 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1315 int offset = ra_->reg2offset(dst_first);
1316 if (cbuf) {
1317 MacroAssembler _masm(cbuf);
1318 __ movl(Address(rsp, offset), as_Register(Matcher::_regEncode[src_first]));
1319 #ifndef PRODUCT
1320 } else {
1321 st->print("movl [rsp + #%d], %s\t# spill",
1322 offset,
1323 Matcher::regName[src_first]);
1324 #endif
1325 }
1326 }
1327 return 0;
1328 } else if (dst_first_rc == rc_int) {
1329 // gpr -> gpr
1330 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1331 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1332 // 64-bit
1333 if (cbuf) {
1334 MacroAssembler _masm(cbuf);
1335 __ movq(as_Register(Matcher::_regEncode[dst_first]),
1336 as_Register(Matcher::_regEncode[src_first]));
1337 #ifndef PRODUCT
1338 } else {
1339 st->print("movq %s, %s\t# spill",
1340 Matcher::regName[dst_first],
1341 Matcher::regName[src_first]);
1342 #endif
1343 }
1344 return 0;
1345 } else {
1346 // 32-bit
1347 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1348 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1349 if (cbuf) {
1350 MacroAssembler _masm(cbuf);
1351 __ movl(as_Register(Matcher::_regEncode[dst_first]),
1352 as_Register(Matcher::_regEncode[src_first]));
1353 #ifndef PRODUCT
1354 } else {
1355 st->print("movl %s, %s\t# spill",
1356 Matcher::regName[dst_first],
1357 Matcher::regName[src_first]);
1358 #endif
1359 }
1360 return 0;
1361 }
1362 } else if (dst_first_rc == rc_float) {
1363 // gpr -> xmm
1364 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1365 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1366 // 64-bit
1367 if (cbuf) {
1368 MacroAssembler _masm(cbuf);
1369 __ movdq( as_XMMRegister(Matcher::_regEncode[dst_first]), as_Register(Matcher::_regEncode[src_first]));
1370 #ifndef PRODUCT
1371 } else {
1372 st->print("movdq %s, %s\t# spill",
1373 Matcher::regName[dst_first],
1374 Matcher::regName[src_first]);
1375 #endif
1376 }
1377 } else {
1378 // 32-bit
1379 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1380 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1381 if (cbuf) {
1382 MacroAssembler _masm(cbuf);
1383 __ movdl( as_XMMRegister(Matcher::_regEncode[dst_first]), as_Register(Matcher::_regEncode[src_first]));
1384 #ifndef PRODUCT
1385 } else {
1386 st->print("movdl %s, %s\t# spill",
1387 Matcher::regName[dst_first],
1388 Matcher::regName[src_first]);
1389 #endif
1390 }
1391 }
1392 return 0;
1393 }
1394 } else if (src_first_rc == rc_float) {
1395 // xmm ->
1396 if (dst_first_rc == rc_stack) {
1397 // xmm -> mem
1398 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1399 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1400 // 64-bit
1401 int offset = ra_->reg2offset(dst_first);
1402 if (cbuf) {
1403 MacroAssembler _masm(cbuf);
1404 __ movdbl( Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[src_first]));
1405 #ifndef PRODUCT
1406 } else {
1407 st->print("movsd [rsp + #%d], %s\t# spill",
1408 offset,
1409 Matcher::regName[src_first]);
1410 #endif
1411 }
1412 } else {
1413 // 32-bit
1414 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1415 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1416 int offset = ra_->reg2offset(dst_first);
1417 if (cbuf) {
1418 MacroAssembler _masm(cbuf);
1419 __ movflt(Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[src_first]));
1420 #ifndef PRODUCT
1421 } else {
1422 st->print("movss [rsp + #%d], %s\t# spill",
1423 offset,
1424 Matcher::regName[src_first]);
1425 #endif
1426 }
1427 }
1428 return 0;
1429 } else if (dst_first_rc == rc_int) {
1430 // xmm -> gpr
1431 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1432 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1433 // 64-bit
1434 if (cbuf) {
1435 MacroAssembler _masm(cbuf);
1436 __ movdq( as_Register(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
1437 #ifndef PRODUCT
1438 } else {
1439 st->print("movdq %s, %s\t# spill",
1440 Matcher::regName[dst_first],
1441 Matcher::regName[src_first]);
1442 #endif
1443 }
1444 } else {
1445 // 32-bit
1446 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1447 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1448 if (cbuf) {
1449 MacroAssembler _masm(cbuf);
1450 __ movdl( as_Register(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
1451 #ifndef PRODUCT
1452 } else {
1453 st->print("movdl %s, %s\t# spill",
1454 Matcher::regName[dst_first],
1455 Matcher::regName[src_first]);
1456 #endif
1457 }
1458 }
1459 return 0;
1460 } else if (dst_first_rc == rc_float) {
1461 // xmm -> xmm
1462 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1463 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1464 // 64-bit
1465 if (cbuf) {
1466 MacroAssembler _masm(cbuf);
1467 __ movdbl( as_XMMRegister(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
1468 #ifndef PRODUCT
1469 } else {
1470 st->print("%s %s, %s\t# spill",
1471 UseXmmRegToRegMoveAll ? "movapd" : "movsd ",
1472 Matcher::regName[dst_first],
1473 Matcher::regName[src_first]);
1474 #endif
1475 }
1476 } else {
1477 // 32-bit
1478 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1479 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1480 if (cbuf) {
1481 MacroAssembler _masm(cbuf);
1482 __ movflt( as_XMMRegister(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
1483 #ifndef PRODUCT
1484 } else {
1485 st->print("%s %s, %s\t# spill",
1486 UseXmmRegToRegMoveAll ? "movaps" : "movss ",
1487 Matcher::regName[dst_first],
1488 Matcher::regName[src_first]);
1489 #endif
1490 }
1491 }
1492 return 0;
1493 }
1494 }
1495
1496 assert(0," foo ");
1497 Unimplemented();
1498 return 0;
1499 }
1500
1501 #ifndef PRODUCT
1502 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream* st) const {
1503 implementation(NULL, ra_, false, st);
1504 }
1505 #endif
1506
1507 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1508 implementation(&cbuf, ra_, false, NULL);
1509 }
1510
1511 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1512 return MachNode::size(ra_);
1513 }
1514
1515 //=============================================================================
1516 #ifndef PRODUCT
1517 void BoxLockNode::format(PhaseRegAlloc* ra_, outputStream* st) const
1518 {
1519 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1520 int reg = ra_->get_reg_first(this);
1521 st->print("leaq %s, [rsp + #%d]\t# box lock",
1522 Matcher::regName[reg], offset);
1523 }
1524 #endif
1525
1526 void BoxLockNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
1527 {
1528 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1529 int reg = ra_->get_encode(this);
1530 if (offset >= 0x80) {
1531 emit_opcode(cbuf, reg < 8 ? Assembler::REX_W : Assembler::REX_WR);
1532 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1533 emit_rm(cbuf, 0x2, reg & 7, 0x04);
1534 emit_rm(cbuf, 0x0, 0x04, RSP_enc);
1535 emit_d32(cbuf, offset);
1536 } else {
1537 emit_opcode(cbuf, reg < 8 ? Assembler::REX_W : Assembler::REX_WR);
1538 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1539 emit_rm(cbuf, 0x1, reg & 7, 0x04);
1540 emit_rm(cbuf, 0x0, 0x04, RSP_enc);
1541 emit_d8(cbuf, offset);
1542 }
1543 }
1544
1545 uint BoxLockNode::size(PhaseRegAlloc *ra_) const
1546 {
1547 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1548 return (offset < 0x80) ? 5 : 8; // REX
1549 }
1550
1551 //=============================================================================
1552 #ifndef PRODUCT
1553 void MachUEPNode::format(PhaseRegAlloc* ra_, outputStream* st) const
1554 {
1555 if (UseCompressedClassPointers) {
1556 st->print_cr("movl rscratch1, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t# compressed klass");
1557 st->print_cr("\tdecode_klass_not_null rscratch1, rscratch1");
1558 st->print_cr("\tcmpq rax, rscratch1\t # Inline cache check");
1559 } else {
1560 st->print_cr("\tcmpq rax, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t"
1561 "# Inline cache check");
1562 }
1563 st->print_cr("\tjne SharedRuntime::_ic_miss_stub");
1564 st->print_cr("\tnop\t# nops to align entry point");
1565 }
1566 #endif
1567
1568 void MachUEPNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
1569 {
1570 MacroAssembler masm(&cbuf);
1571 uint insts_size = cbuf.insts_size();
1572 if (UseCompressedClassPointers) {
1573 masm.load_klass(rscratch1, j_rarg0);
1574 masm.cmpptr(rax, rscratch1);
1575 } else {
1576 masm.cmpptr(rax, Address(j_rarg0, oopDesc::klass_offset_in_bytes()));
1577 }
1578
1579 masm.jump_cc(Assembler::notEqual, RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
1580
1581 /* WARNING these NOPs are critical so that verified entry point is properly
1582 4 bytes aligned for patching by NativeJump::patch_verified_entry() */
1583 int nops_cnt = 4 - ((cbuf.insts_size() - insts_size) & 0x3);
1584 if (OptoBreakpoint) {
1585 // Leave space for int3
1586 nops_cnt -= 1;
1587 }
1588 nops_cnt &= 0x3; // Do not add nops if code is aligned.
1589 if (nops_cnt > 0)
1590 masm.nop(nops_cnt);
1591 }
1592
1593 uint MachUEPNode::size(PhaseRegAlloc* ra_) const
1594 {
1595 return MachNode::size(ra_); // too many variables; just compute it
1596 // the hard way
1597 }
1598
1599
1600 //=============================================================================
1601
1602 int Matcher::regnum_to_fpu_offset(int regnum)
1603 {
1604 return regnum - 32; // The FP registers are in the second chunk
1605 }
1606
1607 // This is UltraSparc specific, true just means we have fast l2f conversion
1608 const bool Matcher::convL2FSupported(void) {
1609 return true;
1610 }
1611
1612 // Is this branch offset short enough that a short branch can be used?
1613 //
1614 // NOTE: If the platform does not provide any short branch variants, then
1615 // this method should return false for offset 0.
1616 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
1617 // The passed offset is relative to address of the branch.
1618 // On 86 a branch displacement is calculated relative to address
1619 // of a next instruction.
1620 offset -= br_size;
1621
1622 // the short version of jmpConUCF2 contains multiple branches,
1623 // making the reach slightly less
1624 if (rule == jmpConUCF2_rule)
1625 return (-126 <= offset && offset <= 125);
1626 return (-128 <= offset && offset <= 127);
1627 }
1628
1629 const bool Matcher::isSimpleConstant64(jlong value) {
1630 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
1631 //return value == (int) value; // Cf. storeImmL and immL32.
1632
1633 // Probably always true, even if a temp register is required.
1634 return true;
1635 }
1636
1637 // The ecx parameter to rep stosq for the ClearArray node is in words.
1638 const bool Matcher::init_array_count_is_in_bytes = false;
1639
1640 // No additional cost for CMOVL.
1641 const int Matcher::long_cmove_cost() { return 0; }
1642
1643 // No CMOVF/CMOVD with SSE2
1644 const int Matcher::float_cmove_cost() { return ConditionalMoveLimit; }
1645
1646 // Does the CPU require late expand (see block.cpp for description of late expand)?
1647 const bool Matcher::require_postalloc_expand = false;
1648
1649 // Do we need to mask the count passed to shift instructions or does
1650 // the cpu only look at the lower 5/6 bits anyway?
1651 const bool Matcher::need_masked_shift_count = false;
1652
1653 bool Matcher::narrow_oop_use_complex_address() {
1654 assert(UseCompressedOops, "only for compressed oops code");
1655 return (LogMinObjAlignmentInBytes <= 3);
1656 }
1657
1658 bool Matcher::narrow_klass_use_complex_address() {
1659 assert(UseCompressedClassPointers, "only for compressed klass code");
1660 return (LogKlassAlignmentInBytes <= 3);
1661 }
1662
1663 bool Matcher::const_oop_prefer_decode() {
1664 // Prefer ConN+DecodeN over ConP.
1665 return true;
1666 }
1667
1668 bool Matcher::const_klass_prefer_decode() {
1669 // TODO: Either support matching DecodeNKlass (heap-based) in operand
1670 // or condisider the following:
1671 // Prefer ConNKlass+DecodeNKlass over ConP in simple compressed klass mode.
1672 //return Universe::narrow_klass_base() == NULL;
1673 return true;
1674 }
1675
1676 // Is it better to copy float constants, or load them directly from
1677 // memory? Intel can load a float constant from a direct address,
1678 // requiring no extra registers. Most RISCs will have to materialize
1679 // an address into a register first, so they would do better to copy
1680 // the constant from stack.
1681 const bool Matcher::rematerialize_float_constants = true; // XXX
1682
1683 // If CPU can load and store mis-aligned doubles directly then no
1684 // fixup is needed. Else we split the double into 2 integer pieces
1685 // and move it piece-by-piece. Only happens when passing doubles into
1686 // C code as the Java calling convention forces doubles to be aligned.
1687 const bool Matcher::misaligned_doubles_ok = true;
1688
1689 // No-op on amd64
1690 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {}
1691
1692 // Advertise here if the CPU requires explicit rounding operations to
1693 // implement the UseStrictFP mode.
1694 const bool Matcher::strict_fp_requires_explicit_rounding = true;
1695
1696 // Are floats conerted to double when stored to stack during deoptimization?
1697 // On x64 it is stored without convertion so we can use normal access.
1698 bool Matcher::float_in_double() { return false; }
1699
1700 // Do ints take an entire long register or just half?
1701 const bool Matcher::int_in_long = true;
1702
1703 // Return whether or not this register is ever used as an argument.
1704 // This function is used on startup to build the trampoline stubs in
1705 // generateOptoStub. Registers not mentioned will be killed by the VM
1706 // call in the trampoline, and arguments in those registers not be
1707 // available to the callee.
1708 bool Matcher::can_be_java_arg(int reg)
1709 {
1710 return
1711 reg == RDI_num || reg == RDI_H_num ||
1712 reg == RSI_num || reg == RSI_H_num ||
1713 reg == RDX_num || reg == RDX_H_num ||
1714 reg == RCX_num || reg == RCX_H_num ||
1715 reg == R8_num || reg == R8_H_num ||
1716 reg == R9_num || reg == R9_H_num ||
1717 reg == R12_num || reg == R12_H_num ||
1718 reg == XMM0_num || reg == XMM0b_num ||
1719 reg == XMM1_num || reg == XMM1b_num ||
1720 reg == XMM2_num || reg == XMM2b_num ||
1721 reg == XMM3_num || reg == XMM3b_num ||
1722 reg == XMM4_num || reg == XMM4b_num ||
1723 reg == XMM5_num || reg == XMM5b_num ||
1724 reg == XMM6_num || reg == XMM6b_num ||
1725 reg == XMM7_num || reg == XMM7b_num;
1726 }
1727
1728 bool Matcher::is_spillable_arg(int reg)
1729 {
1730 return can_be_java_arg(reg);
1731 }
1732
1733 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) {
1734 // In 64 bit mode a code which use multiply when
1735 // devisor is constant is faster than hardware
1736 // DIV instruction (it uses MulHiL).
1737 return false;
1738 }
1739
1740 // Register for DIVI projection of divmodI
1741 RegMask Matcher::divI_proj_mask() {
1742 return INT_RAX_REG_mask();
1743 }
1744
1745 // Register for MODI projection of divmodI
1746 RegMask Matcher::modI_proj_mask() {
1747 return INT_RDX_REG_mask();
1748 }
1749
1750 // Register for DIVL projection of divmodL
1751 RegMask Matcher::divL_proj_mask() {
1752 return LONG_RAX_REG_mask();
1753 }
1754
1755 // Register for MODL projection of divmodL
1756 RegMask Matcher::modL_proj_mask() {
1757 return LONG_RDX_REG_mask();
1758 }
1759
1760 // Register for saving SP into on method handle invokes. Not used on x86_64.
1761 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
1762 return NO_REG_mask();
1763 }
1764
1765 %}
1766
1767 //----------ENCODING BLOCK-----------------------------------------------------
1768 // This block specifies the encoding classes used by the compiler to
1769 // output byte streams. Encoding classes are parameterized macros
1770 // used by Machine Instruction Nodes in order to generate the bit
1771 // encoding of the instruction. Operands specify their base encoding
1772 // interface with the interface keyword. There are currently
1773 // supported four interfaces, REG_INTER, CONST_INTER, MEMORY_INTER, &
1774 // COND_INTER. REG_INTER causes an operand to generate a function
1775 // which returns its register number when queried. CONST_INTER causes
1776 // an operand to generate a function which returns the value of the
1777 // constant when queried. MEMORY_INTER causes an operand to generate
1778 // four functions which return the Base Register, the Index Register,
1779 // the Scale Value, and the Offset Value of the operand when queried.
1780 // COND_INTER causes an operand to generate six functions which return
1781 // the encoding code (ie - encoding bits for the instruction)
1782 // associated with each basic boolean condition for a conditional
1783 // instruction.
1784 //
1785 // Instructions specify two basic values for encoding. Again, a
1786 // function is available to check if the constant displacement is an
1787 // oop. They use the ins_encode keyword to specify their encoding
1788 // classes (which must be a sequence of enc_class names, and their
1789 // parameters, specified in the encoding block), and they use the
1790 // opcode keyword to specify, in order, their primary, secondary, and
1791 // tertiary opcode. Only the opcode sections which a particular
1792 // instruction needs for encoding need to be specified.
1793 encode %{
1794 // Build emit functions for each basic byte or larger field in the
1795 // intel encoding scheme (opcode, rm, sib, immediate), and call them
1796 // from C++ code in the enc_class source block. Emit functions will
1797 // live in the main source block for now. In future, we can
1798 // generalize this by adding a syntax that specifies the sizes of
1799 // fields in an order, so that the adlc can build the emit functions
1800 // automagically
1801
1802 // Emit primary opcode
1803 enc_class OpcP
1804 %{
1805 emit_opcode(cbuf, $primary);
1806 %}
1807
1808 // Emit secondary opcode
1809 enc_class OpcS
1810 %{
1811 emit_opcode(cbuf, $secondary);
1812 %}
1813
1814 // Emit tertiary opcode
1815 enc_class OpcT
1816 %{
1817 emit_opcode(cbuf, $tertiary);
1818 %}
1819
1820 // Emit opcode directly
1821 enc_class Opcode(immI d8)
1822 %{
1823 emit_opcode(cbuf, $d8$$constant);
1824 %}
1825
1826 // Emit size prefix
1827 enc_class SizePrefix
1828 %{
1829 emit_opcode(cbuf, 0x66);
1830 %}
1831
1832 enc_class reg(rRegI reg)
1833 %{
1834 emit_rm(cbuf, 0x3, 0, $reg$$reg & 7);
1835 %}
1836
1837 enc_class reg_reg(rRegI dst, rRegI src)
1838 %{
1839 emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7);
1840 %}
1841
1842 enc_class opc_reg_reg(immI opcode, rRegI dst, rRegI src)
1843 %{
1844 emit_opcode(cbuf, $opcode$$constant);
1845 emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7);
1846 %}
1847
1848 enc_class cdql_enc(no_rax_rdx_RegI div)
1849 %{
1850 // Full implementation of Java idiv and irem; checks for
1851 // special case as described in JVM spec., p.243 & p.271.
1852 //
1853 // normal case special case
1854 //
1855 // input : rax: dividend min_int
1856 // reg: divisor -1
1857 //
1858 // output: rax: quotient (= rax idiv reg) min_int
1859 // rdx: remainder (= rax irem reg) 0
1860 //
1861 // Code sequnce:
1862 //
1863 // 0: 3d 00 00 00 80 cmp $0x80000000,%eax
1864 // 5: 75 07/08 jne e <normal>
1865 // 7: 33 d2 xor %edx,%edx
1866 // [div >= 8 -> offset + 1]
1867 // [REX_B]
1868 // 9: 83 f9 ff cmp $0xffffffffffffffff,$div
1869 // c: 74 03/04 je 11 <done>
1870 // 000000000000000e <normal>:
1871 // e: 99 cltd
1872 // [div >= 8 -> offset + 1]
1873 // [REX_B]
1874 // f: f7 f9 idiv $div
1875 // 0000000000000011 <done>:
1876
1877 // cmp $0x80000000,%eax
1878 emit_opcode(cbuf, 0x3d);
1879 emit_d8(cbuf, 0x00);
1880 emit_d8(cbuf, 0x00);
1881 emit_d8(cbuf, 0x00);
1882 emit_d8(cbuf, 0x80);
1883
1884 // jne e <normal>
1885 emit_opcode(cbuf, 0x75);
1886 emit_d8(cbuf, $div$$reg < 8 ? 0x07 : 0x08);
1887
1888 // xor %edx,%edx
1889 emit_opcode(cbuf, 0x33);
1890 emit_d8(cbuf, 0xD2);
1891
1892 // cmp $0xffffffffffffffff,%ecx
1893 if ($div$$reg >= 8) {
1894 emit_opcode(cbuf, Assembler::REX_B);
1895 }
1896 emit_opcode(cbuf, 0x83);
1897 emit_rm(cbuf, 0x3, 0x7, $div$$reg & 7);
1898 emit_d8(cbuf, 0xFF);
1899
1900 // je 11 <done>
1901 emit_opcode(cbuf, 0x74);
1902 emit_d8(cbuf, $div$$reg < 8 ? 0x03 : 0x04);
1903
1904 // <normal>
1905 // cltd
1906 emit_opcode(cbuf, 0x99);
1907
1908 // idivl (note: must be emitted by the user of this rule)
1909 // <done>
1910 %}
1911
1912 enc_class cdqq_enc(no_rax_rdx_RegL div)
1913 %{
1914 // Full implementation of Java ldiv and lrem; checks for
1915 // special case as described in JVM spec., p.243 & p.271.
1916 //
1917 // normal case special case
1918 //
1919 // input : rax: dividend min_long
1920 // reg: divisor -1
1921 //
1922 // output: rax: quotient (= rax idiv reg) min_long
1923 // rdx: remainder (= rax irem reg) 0
1924 //
1925 // Code sequnce:
1926 //
1927 // 0: 48 ba 00 00 00 00 00 mov $0x8000000000000000,%rdx
1928 // 7: 00 00 80
1929 // a: 48 39 d0 cmp %rdx,%rax
1930 // d: 75 08 jne 17 <normal>
1931 // f: 33 d2 xor %edx,%edx
1932 // 11: 48 83 f9 ff cmp $0xffffffffffffffff,$div
1933 // 15: 74 05 je 1c <done>
1934 // 0000000000000017 <normal>:
1935 // 17: 48 99 cqto
1936 // 19: 48 f7 f9 idiv $div
1937 // 000000000000001c <done>:
1938
1939 // mov $0x8000000000000000,%rdx
1940 emit_opcode(cbuf, Assembler::REX_W);
1941 emit_opcode(cbuf, 0xBA);
1942 emit_d8(cbuf, 0x00);
1943 emit_d8(cbuf, 0x00);
1944 emit_d8(cbuf, 0x00);
1945 emit_d8(cbuf, 0x00);
1946 emit_d8(cbuf, 0x00);
1947 emit_d8(cbuf, 0x00);
1948 emit_d8(cbuf, 0x00);
1949 emit_d8(cbuf, 0x80);
1950
1951 // cmp %rdx,%rax
1952 emit_opcode(cbuf, Assembler::REX_W);
1953 emit_opcode(cbuf, 0x39);
1954 emit_d8(cbuf, 0xD0);
1955
1956 // jne 17 <normal>
1957 emit_opcode(cbuf, 0x75);
1958 emit_d8(cbuf, 0x08);
1959
1960 // xor %edx,%edx
1961 emit_opcode(cbuf, 0x33);
1962 emit_d8(cbuf, 0xD2);
1963
1964 // cmp $0xffffffffffffffff,$div
1965 emit_opcode(cbuf, $div$$reg < 8 ? Assembler::REX_W : Assembler::REX_WB);
1966 emit_opcode(cbuf, 0x83);
1967 emit_rm(cbuf, 0x3, 0x7, $div$$reg & 7);
1968 emit_d8(cbuf, 0xFF);
1969
1970 // je 1e <done>
1971 emit_opcode(cbuf, 0x74);
1972 emit_d8(cbuf, 0x05);
1973
1974 // <normal>
1975 // cqto
1976 emit_opcode(cbuf, Assembler::REX_W);
1977 emit_opcode(cbuf, 0x99);
1978
1979 // idivq (note: must be emitted by the user of this rule)
1980 // <done>
1981 %}
1982
1983 // Opcde enc_class for 8/32 bit immediate instructions with sign-extension
1984 enc_class OpcSE(immI imm)
1985 %{
1986 // Emit primary opcode and set sign-extend bit
1987 // Check for 8-bit immediate, and set sign extend bit in opcode
1988 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
1989 emit_opcode(cbuf, $primary | 0x02);
1990 } else {
1991 // 32-bit immediate
1992 emit_opcode(cbuf, $primary);
1993 }
1994 %}
1995
1996 enc_class OpcSErm(rRegI dst, immI imm)
1997 %{
1998 // OpcSEr/m
1999 int dstenc = $dst$$reg;
2000 if (dstenc >= 8) {
2001 emit_opcode(cbuf, Assembler::REX_B);
2002 dstenc -= 8;
2003 }
2004 // Emit primary opcode and set sign-extend bit
2005 // Check for 8-bit immediate, and set sign extend bit in opcode
2006 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
2007 emit_opcode(cbuf, $primary | 0x02);
2008 } else {
2009 // 32-bit immediate
2010 emit_opcode(cbuf, $primary);
2011 }
2012 // Emit r/m byte with secondary opcode, after primary opcode.
2013 emit_rm(cbuf, 0x3, $secondary, dstenc);
2014 %}
2015
2016 enc_class OpcSErm_wide(rRegL dst, immI imm)
2017 %{
2018 // OpcSEr/m
2019 int dstenc = $dst$$reg;
2020 if (dstenc < 8) {
2021 emit_opcode(cbuf, Assembler::REX_W);
2022 } else {
2023 emit_opcode(cbuf, Assembler::REX_WB);
2024 dstenc -= 8;
2025 }
2026 // Emit primary opcode and set sign-extend bit
2027 // Check for 8-bit immediate, and set sign extend bit in opcode
2028 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
2029 emit_opcode(cbuf, $primary | 0x02);
2030 } else {
2031 // 32-bit immediate
2032 emit_opcode(cbuf, $primary);
2033 }
2034 // Emit r/m byte with secondary opcode, after primary opcode.
2035 emit_rm(cbuf, 0x3, $secondary, dstenc);
2036 %}
2037
2038 enc_class Con8or32(immI imm)
2039 %{
2040 // Check for 8-bit immediate, and set sign extend bit in opcode
2041 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
2042 $$$emit8$imm$$constant;
2043 } else {
2044 // 32-bit immediate
2045 $$$emit32$imm$$constant;
2046 }
2047 %}
2048
2049 enc_class opc2_reg(rRegI dst)
2050 %{
2051 // BSWAP
2052 emit_cc(cbuf, $secondary, $dst$$reg);
2053 %}
2054
2055 enc_class opc3_reg(rRegI dst)
2056 %{
2057 // BSWAP
2058 emit_cc(cbuf, $tertiary, $dst$$reg);
2059 %}
2060
2061 enc_class reg_opc(rRegI div)
2062 %{
2063 // INC, DEC, IDIV, IMOD, JMP indirect, ...
2064 emit_rm(cbuf, 0x3, $secondary, $div$$reg & 7);
2065 %}
2066
2067 enc_class enc_cmov(cmpOp cop)
2068 %{
2069 // CMOV
2070 $$$emit8$primary;
2071 emit_cc(cbuf, $secondary, $cop$$cmpcode);
2072 %}
2073
2074 enc_class enc_PartialSubtypeCheck()
2075 %{
2076 Register Rrdi = as_Register(RDI_enc); // result register
2077 Register Rrax = as_Register(RAX_enc); // super class
2078 Register Rrcx = as_Register(RCX_enc); // killed
2079 Register Rrsi = as_Register(RSI_enc); // sub class
2080 Label miss;
2081 const bool set_cond_codes = true;
2082
2083 MacroAssembler _masm(&cbuf);
2084 __ check_klass_subtype_slow_path(Rrsi, Rrax, Rrcx, Rrdi,
2085 NULL, &miss,
2086 /*set_cond_codes:*/ true);
2087 if ($primary) {
2088 __ xorptr(Rrdi, Rrdi);
2089 }
2090 __ bind(miss);
2091 %}
2092
2093 enc_class clear_avx %{
2094 debug_only(int off0 = cbuf.insts_size());
2095 if (ra_->C->max_vector_size() > 16) {
2096 // Clear upper bits of YMM registers when current compiled code uses
2097 // wide vectors to avoid AVX <-> SSE transition penalty during call.
2098 MacroAssembler _masm(&cbuf);
2099 __ vzeroupper();
2100 }
2101 debug_only(int off1 = cbuf.insts_size());
2102 assert(off1 - off0 == clear_avx_size(), "correct size prediction");
2103 %}
2104
2105 enc_class Java_To_Runtime(method meth) %{
2106 // No relocation needed
2107 MacroAssembler _masm(&cbuf);
2108 __ mov64(r10, (int64_t) $meth$$method);
2109 __ call(r10);
2110 %}
2111
2112 enc_class Java_To_Interpreter(method meth)
2113 %{
2114 // CALL Java_To_Interpreter
2115 // This is the instruction starting address for relocation info.
2116 cbuf.set_insts_mark();
2117 $$$emit8$primary;
2118 // CALL directly to the runtime
2119 emit_d32_reloc(cbuf,
2120 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
2121 runtime_call_Relocation::spec(),
2122 RELOC_DISP32);
2123 %}
2124
2125 enc_class Java_Static_Call(method meth)
2126 %{
2127 // JAVA STATIC CALL
2128 // CALL to fixup routine. Fixup routine uses ScopeDesc info to
2129 // determine who we intended to call.
2130 cbuf.set_insts_mark();
2131 $$$emit8$primary;
2132
2133 if (!_method) {
2134 emit_d32_reloc(cbuf, (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
2135 runtime_call_Relocation::spec(),
2136 RELOC_DISP32);
2137 } else {
2138 int method_index = resolved_method_index(cbuf);
2139 RelocationHolder rspec = _optimized_virtual ? opt_virtual_call_Relocation::spec(method_index)
2140 : static_call_Relocation::spec(method_index);
2141 emit_d32_reloc(cbuf, (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
2142 rspec, RELOC_DISP32);
2143 // Emit stubs for static call.
2144 address mark = cbuf.insts_mark();
2145 address stub = CompiledStaticCall::emit_to_interp_stub(cbuf, mark);
2146 if (stub == NULL) {
2147 ciEnv::current()->record_failure("CodeCache is full");
2148 return;
2149 }
2150 }
2151 %}
2152
2153 enc_class Java_Dynamic_Call(method meth) %{
2154 MacroAssembler _masm(&cbuf);
2155 __ ic_call((address)$meth$$method, resolved_method_index(cbuf));
2156 %}
2157
2158 enc_class Java_Compiled_Call(method meth)
2159 %{
2160 // JAVA COMPILED CALL
2161 int disp = in_bytes(Method:: from_compiled_offset());
2162
2163 // XXX XXX offset is 128 is 1.5 NON-PRODUCT !!!
2164 // assert(-0x80 <= disp && disp < 0x80, "compiled_code_offset isn't small");
2165
2166 // callq *disp(%rax)
2167 cbuf.set_insts_mark();
2168 $$$emit8$primary;
2169 if (disp < 0x80) {
2170 emit_rm(cbuf, 0x01, $secondary, RAX_enc); // R/M byte
2171 emit_d8(cbuf, disp); // Displacement
2172 } else {
2173 emit_rm(cbuf, 0x02, $secondary, RAX_enc); // R/M byte
2174 emit_d32(cbuf, disp); // Displacement
2175 }
2176 %}
2177
2178 enc_class reg_opc_imm(rRegI dst, immI8 shift)
2179 %{
2180 // SAL, SAR, SHR
2181 int dstenc = $dst$$reg;
2182 if (dstenc >= 8) {
2183 emit_opcode(cbuf, Assembler::REX_B);
2184 dstenc -= 8;
2185 }
2186 $$$emit8$primary;
2187 emit_rm(cbuf, 0x3, $secondary, dstenc);
2188 $$$emit8$shift$$constant;
2189 %}
2190
2191 enc_class reg_opc_imm_wide(rRegL dst, immI8 shift)
2192 %{
2193 // SAL, SAR, SHR
2194 int dstenc = $dst$$reg;
2195 if (dstenc < 8) {
2196 emit_opcode(cbuf, Assembler::REX_W);
2197 } else {
2198 emit_opcode(cbuf, Assembler::REX_WB);
2199 dstenc -= 8;
2200 }
2201 $$$emit8$primary;
2202 emit_rm(cbuf, 0x3, $secondary, dstenc);
2203 $$$emit8$shift$$constant;
2204 %}
2205
2206 enc_class load_immI(rRegI dst, immI src)
2207 %{
2208 int dstenc = $dst$$reg;
2209 if (dstenc >= 8) {
2210 emit_opcode(cbuf, Assembler::REX_B);
2211 dstenc -= 8;
2212 }
2213 emit_opcode(cbuf, 0xB8 | dstenc);
2214 $$$emit32$src$$constant;
2215 %}
2216
2217 enc_class load_immL(rRegL dst, immL src)
2218 %{
2219 int dstenc = $dst$$reg;
2220 if (dstenc < 8) {
2221 emit_opcode(cbuf, Assembler::REX_W);
2222 } else {
2223 emit_opcode(cbuf, Assembler::REX_WB);
2224 dstenc -= 8;
2225 }
2226 emit_opcode(cbuf, 0xB8 | dstenc);
2227 emit_d64(cbuf, $src$$constant);
2228 %}
2229
2230 enc_class load_immUL32(rRegL dst, immUL32 src)
2231 %{
2232 // same as load_immI, but this time we care about zeroes in the high word
2233 int dstenc = $dst$$reg;
2234 if (dstenc >= 8) {
2235 emit_opcode(cbuf, Assembler::REX_B);
2236 dstenc -= 8;
2237 }
2238 emit_opcode(cbuf, 0xB8 | dstenc);
2239 $$$emit32$src$$constant;
2240 %}
2241
2242 enc_class load_immL32(rRegL dst, immL32 src)
2243 %{
2244 int dstenc = $dst$$reg;
2245 if (dstenc < 8) {
2246 emit_opcode(cbuf, Assembler::REX_W);
2247 } else {
2248 emit_opcode(cbuf, Assembler::REX_WB);
2249 dstenc -= 8;
2250 }
2251 emit_opcode(cbuf, 0xC7);
2252 emit_rm(cbuf, 0x03, 0x00, dstenc);
2253 $$$emit32$src$$constant;
2254 %}
2255
2256 enc_class load_immP31(rRegP dst, immP32 src)
2257 %{
2258 // same as load_immI, but this time we care about zeroes in the high word
2259 int dstenc = $dst$$reg;
2260 if (dstenc >= 8) {
2261 emit_opcode(cbuf, Assembler::REX_B);
2262 dstenc -= 8;
2263 }
2264 emit_opcode(cbuf, 0xB8 | dstenc);
2265 $$$emit32$src$$constant;
2266 %}
2267
2268 enc_class load_immP(rRegP dst, immP src)
2269 %{
2270 int dstenc = $dst$$reg;
2271 if (dstenc < 8) {
2272 emit_opcode(cbuf, Assembler::REX_W);
2273 } else {
2274 emit_opcode(cbuf, Assembler::REX_WB);
2275 dstenc -= 8;
2276 }
2277 emit_opcode(cbuf, 0xB8 | dstenc);
2278 // This next line should be generated from ADLC
2279 if ($src->constant_reloc() != relocInfo::none) {
2280 emit_d64_reloc(cbuf, $src$$constant, $src->constant_reloc(), RELOC_IMM64);
2281 } else {
2282 emit_d64(cbuf, $src$$constant);
2283 }
2284 %}
2285
2286 enc_class Con32(immI src)
2287 %{
2288 // Output immediate
2289 $$$emit32$src$$constant;
2290 %}
2291
2292 enc_class Con32F_as_bits(immF src)
2293 %{
2294 // Output Float immediate bits
2295 jfloat jf = $src$$constant;
2296 jint jf_as_bits = jint_cast(jf);
2297 emit_d32(cbuf, jf_as_bits);
2298 %}
2299
2300 enc_class Con16(immI src)
2301 %{
2302 // Output immediate
2303 $$$emit16$src$$constant;
2304 %}
2305
2306 // How is this different from Con32??? XXX
2307 enc_class Con_d32(immI src)
2308 %{
2309 emit_d32(cbuf,$src$$constant);
2310 %}
2311
2312 enc_class conmemref (rRegP t1) %{ // Con32(storeImmI)
2313 // Output immediate memory reference
2314 emit_rm(cbuf, 0x00, $t1$$reg, 0x05 );
2315 emit_d32(cbuf, 0x00);
2316 %}
2317
2318 enc_class lock_prefix()
2319 %{
2320 if (os::is_MP()) {
2321 emit_opcode(cbuf, 0xF0); // lock
2322 }
2323 %}
2324
2325 enc_class REX_mem(memory mem)
2326 %{
2327 if ($mem$$base >= 8) {
2328 if ($mem$$index < 8) {
2329 emit_opcode(cbuf, Assembler::REX_B);
2330 } else {
2331 emit_opcode(cbuf, Assembler::REX_XB);
2332 }
2333 } else {
2334 if ($mem$$index >= 8) {
2335 emit_opcode(cbuf, Assembler::REX_X);
2336 }
2337 }
2338 %}
2339
2340 enc_class REX_mem_wide(memory mem)
2341 %{
2342 if ($mem$$base >= 8) {
2343 if ($mem$$index < 8) {
2344 emit_opcode(cbuf, Assembler::REX_WB);
2345 } else {
2346 emit_opcode(cbuf, Assembler::REX_WXB);
2347 }
2348 } else {
2349 if ($mem$$index < 8) {
2350 emit_opcode(cbuf, Assembler::REX_W);
2351 } else {
2352 emit_opcode(cbuf, Assembler::REX_WX);
2353 }
2354 }
2355 %}
2356
2357 // for byte regs
2358 enc_class REX_breg(rRegI reg)
2359 %{
2360 if ($reg$$reg >= 4) {
2361 emit_opcode(cbuf, $reg$$reg < 8 ? Assembler::REX : Assembler::REX_B);
2362 }
2363 %}
2364
2365 // for byte regs
2366 enc_class REX_reg_breg(rRegI dst, rRegI src)
2367 %{
2368 if ($dst$$reg < 8) {
2369 if ($src$$reg >= 4) {
2370 emit_opcode(cbuf, $src$$reg < 8 ? Assembler::REX : Assembler::REX_B);
2371 }
2372 } else {
2373 if ($src$$reg < 8) {
2374 emit_opcode(cbuf, Assembler::REX_R);
2375 } else {
2376 emit_opcode(cbuf, Assembler::REX_RB);
2377 }
2378 }
2379 %}
2380
2381 // for byte regs
2382 enc_class REX_breg_mem(rRegI reg, memory mem)
2383 %{
2384 if ($reg$$reg < 8) {
2385 if ($mem$$base < 8) {
2386 if ($mem$$index >= 8) {
2387 emit_opcode(cbuf, Assembler::REX_X);
2388 } else if ($reg$$reg >= 4) {
2389 emit_opcode(cbuf, Assembler::REX);
2390 }
2391 } else {
2392 if ($mem$$index < 8) {
2393 emit_opcode(cbuf, Assembler::REX_B);
2394 } else {
2395 emit_opcode(cbuf, Assembler::REX_XB);
2396 }
2397 }
2398 } else {
2399 if ($mem$$base < 8) {
2400 if ($mem$$index < 8) {
2401 emit_opcode(cbuf, Assembler::REX_R);
2402 } else {
2403 emit_opcode(cbuf, Assembler::REX_RX);
2404 }
2405 } else {
2406 if ($mem$$index < 8) {
2407 emit_opcode(cbuf, Assembler::REX_RB);
2408 } else {
2409 emit_opcode(cbuf, Assembler::REX_RXB);
2410 }
2411 }
2412 }
2413 %}
2414
2415 enc_class REX_reg(rRegI reg)
2416 %{
2417 if ($reg$$reg >= 8) {
2418 emit_opcode(cbuf, Assembler::REX_B);
2419 }
2420 %}
2421
2422 enc_class REX_reg_wide(rRegI reg)
2423 %{
2424 if ($reg$$reg < 8) {
2425 emit_opcode(cbuf, Assembler::REX_W);
2426 } else {
2427 emit_opcode(cbuf, Assembler::REX_WB);
2428 }
2429 %}
2430
2431 enc_class REX_reg_reg(rRegI dst, rRegI src)
2432 %{
2433 if ($dst$$reg < 8) {
2434 if ($src$$reg >= 8) {
2435 emit_opcode(cbuf, Assembler::REX_B);
2436 }
2437 } else {
2438 if ($src$$reg < 8) {
2439 emit_opcode(cbuf, Assembler::REX_R);
2440 } else {
2441 emit_opcode(cbuf, Assembler::REX_RB);
2442 }
2443 }
2444 %}
2445
2446 enc_class REX_reg_reg_wide(rRegI dst, rRegI src)
2447 %{
2448 if ($dst$$reg < 8) {
2449 if ($src$$reg < 8) {
2450 emit_opcode(cbuf, Assembler::REX_W);
2451 } else {
2452 emit_opcode(cbuf, Assembler::REX_WB);
2453 }
2454 } else {
2455 if ($src$$reg < 8) {
2456 emit_opcode(cbuf, Assembler::REX_WR);
2457 } else {
2458 emit_opcode(cbuf, Assembler::REX_WRB);
2459 }
2460 }
2461 %}
2462
2463 enc_class REX_reg_mem(rRegI reg, memory mem)
2464 %{
2465 if ($reg$$reg < 8) {
2466 if ($mem$$base < 8) {
2467 if ($mem$$index >= 8) {
2468 emit_opcode(cbuf, Assembler::REX_X);
2469 }
2470 } else {
2471 if ($mem$$index < 8) {
2472 emit_opcode(cbuf, Assembler::REX_B);
2473 } else {
2474 emit_opcode(cbuf, Assembler::REX_XB);
2475 }
2476 }
2477 } else {
2478 if ($mem$$base < 8) {
2479 if ($mem$$index < 8) {
2480 emit_opcode(cbuf, Assembler::REX_R);
2481 } else {
2482 emit_opcode(cbuf, Assembler::REX_RX);
2483 }
2484 } else {
2485 if ($mem$$index < 8) {
2486 emit_opcode(cbuf, Assembler::REX_RB);
2487 } else {
2488 emit_opcode(cbuf, Assembler::REX_RXB);
2489 }
2490 }
2491 }
2492 %}
2493
2494 enc_class REX_reg_mem_wide(rRegL reg, memory mem)
2495 %{
2496 if ($reg$$reg < 8) {
2497 if ($mem$$base < 8) {
2498 if ($mem$$index < 8) {
2499 emit_opcode(cbuf, Assembler::REX_W);
2500 } else {
2501 emit_opcode(cbuf, Assembler::REX_WX);
2502 }
2503 } else {
2504 if ($mem$$index < 8) {
2505 emit_opcode(cbuf, Assembler::REX_WB);
2506 } else {
2507 emit_opcode(cbuf, Assembler::REX_WXB);
2508 }
2509 }
2510 } else {
2511 if ($mem$$base < 8) {
2512 if ($mem$$index < 8) {
2513 emit_opcode(cbuf, Assembler::REX_WR);
2514 } else {
2515 emit_opcode(cbuf, Assembler::REX_WRX);
2516 }
2517 } else {
2518 if ($mem$$index < 8) {
2519 emit_opcode(cbuf, Assembler::REX_WRB);
2520 } else {
2521 emit_opcode(cbuf, Assembler::REX_WRXB);
2522 }
2523 }
2524 }
2525 %}
2526
2527 enc_class reg_mem(rRegI ereg, memory mem)
2528 %{
2529 // High registers handle in encode_RegMem
2530 int reg = $ereg$$reg;
2531 int base = $mem$$base;
2532 int index = $mem$$index;
2533 int scale = $mem$$scale;
2534 int disp = $mem$$disp;
2535 relocInfo::relocType disp_reloc = $mem->disp_reloc();
2536
2537 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
2538 %}
2539
2540 enc_class RM_opc_mem(immI rm_opcode, memory mem)
2541 %{
2542 int rm_byte_opcode = $rm_opcode$$constant;
2543
2544 // High registers handle in encode_RegMem
2545 int base = $mem$$base;
2546 int index = $mem$$index;
2547 int scale = $mem$$scale;
2548 int displace = $mem$$disp;
2549
2550 relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when
2551 // working with static
2552 // globals
2553 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace,
2554 disp_reloc);
2555 %}
2556
2557 enc_class reg_lea(rRegI dst, rRegI src0, immI src1)
2558 %{
2559 int reg_encoding = $dst$$reg;
2560 int base = $src0$$reg; // 0xFFFFFFFF indicates no base
2561 int index = 0x04; // 0x04 indicates no index
2562 int scale = 0x00; // 0x00 indicates no scale
2563 int displace = $src1$$constant; // 0x00 indicates no displacement
2564 relocInfo::relocType disp_reloc = relocInfo::none;
2565 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace,
2566 disp_reloc);
2567 %}
2568
2569 enc_class neg_reg(rRegI dst)
2570 %{
2571 int dstenc = $dst$$reg;
2572 if (dstenc >= 8) {
2573 emit_opcode(cbuf, Assembler::REX_B);
2574 dstenc -= 8;
2575 }
2576 // NEG $dst
2577 emit_opcode(cbuf, 0xF7);
2578 emit_rm(cbuf, 0x3, 0x03, dstenc);
2579 %}
2580
2581 enc_class neg_reg_wide(rRegI dst)
2582 %{
2583 int dstenc = $dst$$reg;
2584 if (dstenc < 8) {
2585 emit_opcode(cbuf, Assembler::REX_W);
2586 } else {
2587 emit_opcode(cbuf, Assembler::REX_WB);
2588 dstenc -= 8;
2589 }
2590 // NEG $dst
2591 emit_opcode(cbuf, 0xF7);
2592 emit_rm(cbuf, 0x3, 0x03, dstenc);
2593 %}
2594
2595 enc_class setLT_reg(rRegI dst)
2596 %{
2597 int dstenc = $dst$$reg;
2598 if (dstenc >= 8) {
2599 emit_opcode(cbuf, Assembler::REX_B);
2600 dstenc -= 8;
2601 } else if (dstenc >= 4) {
2602 emit_opcode(cbuf, Assembler::REX);
2603 }
2604 // SETLT $dst
2605 emit_opcode(cbuf, 0x0F);
2606 emit_opcode(cbuf, 0x9C);
2607 emit_rm(cbuf, 0x3, 0x0, dstenc);
2608 %}
2609
2610 enc_class setNZ_reg(rRegI dst)
2611 %{
2612 int dstenc = $dst$$reg;
2613 if (dstenc >= 8) {
2614 emit_opcode(cbuf, Assembler::REX_B);
2615 dstenc -= 8;
2616 } else if (dstenc >= 4) {
2617 emit_opcode(cbuf, Assembler::REX);
2618 }
2619 // SETNZ $dst
2620 emit_opcode(cbuf, 0x0F);
2621 emit_opcode(cbuf, 0x95);
2622 emit_rm(cbuf, 0x3, 0x0, dstenc);
2623 %}
2624
2625
2626 // Compare the lonogs and set -1, 0, or 1 into dst
2627 enc_class cmpl3_flag(rRegL src1, rRegL src2, rRegI dst)
2628 %{
2629 int src1enc = $src1$$reg;
2630 int src2enc = $src2$$reg;
2631 int dstenc = $dst$$reg;
2632
2633 // cmpq $src1, $src2
2634 if (src1enc < 8) {
2635 if (src2enc < 8) {
2636 emit_opcode(cbuf, Assembler::REX_W);
2637 } else {
2638 emit_opcode(cbuf, Assembler::REX_WB);
2639 }
2640 } else {
2641 if (src2enc < 8) {
2642 emit_opcode(cbuf, Assembler::REX_WR);
2643 } else {
2644 emit_opcode(cbuf, Assembler::REX_WRB);
2645 }
2646 }
2647 emit_opcode(cbuf, 0x3B);
2648 emit_rm(cbuf, 0x3, src1enc & 7, src2enc & 7);
2649
2650 // movl $dst, -1
2651 if (dstenc >= 8) {
2652 emit_opcode(cbuf, Assembler::REX_B);
2653 }
2654 emit_opcode(cbuf, 0xB8 | (dstenc & 7));
2655 emit_d32(cbuf, -1);
2656
2657 // jl,s done
2658 emit_opcode(cbuf, 0x7C);
2659 emit_d8(cbuf, dstenc < 4 ? 0x06 : 0x08);
2660
2661 // setne $dst
2662 if (dstenc >= 4) {
2663 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_B);
2664 }
2665 emit_opcode(cbuf, 0x0F);
2666 emit_opcode(cbuf, 0x95);
2667 emit_opcode(cbuf, 0xC0 | (dstenc & 7));
2668
2669 // movzbl $dst, $dst
2670 if (dstenc >= 4) {
2671 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_RB);
2672 }
2673 emit_opcode(cbuf, 0x0F);
2674 emit_opcode(cbuf, 0xB6);
2675 emit_rm(cbuf, 0x3, dstenc & 7, dstenc & 7);
2676 %}
2677
2678 enc_class Push_ResultXD(regD dst) %{
2679 MacroAssembler _masm(&cbuf);
2680 __ fstp_d(Address(rsp, 0));
2681 __ movdbl($dst$$XMMRegister, Address(rsp, 0));
2682 __ addptr(rsp, 8);
2683 %}
2684
2685 enc_class Push_SrcXD(regD src) %{
2686 MacroAssembler _masm(&cbuf);
2687 __ subptr(rsp, 8);
2688 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
2689 __ fld_d(Address(rsp, 0));
2690 %}
2691
2692
2693 enc_class enc_rethrow()
2694 %{
2695 cbuf.set_insts_mark();
2696 emit_opcode(cbuf, 0xE9); // jmp entry
2697 emit_d32_reloc(cbuf,
2698 (int) (OptoRuntime::rethrow_stub() - cbuf.insts_end() - 4),
2699 runtime_call_Relocation::spec(),
2700 RELOC_DISP32);
2701 %}
2702
2703 %}
2704
2705
2706
2707 //----------FRAME--------------------------------------------------------------
2708 // Definition of frame structure and management information.
2709 //
2710 // S T A C K L A Y O U T Allocators stack-slot number
2711 // | (to get allocators register number
2712 // G Owned by | | v add OptoReg::stack0())
2713 // r CALLER | |
2714 // o | +--------+ pad to even-align allocators stack-slot
2715 // w V | pad0 | numbers; owned by CALLER
2716 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
2717 // h ^ | in | 5
2718 // | | args | 4 Holes in incoming args owned by SELF
2719 // | | | | 3
2720 // | | +--------+
2721 // V | | old out| Empty on Intel, window on Sparc
2722 // | old |preserve| Must be even aligned.
2723 // | SP-+--------+----> Matcher::_old_SP, even aligned
2724 // | | in | 3 area for Intel ret address
2725 // Owned by |preserve| Empty on Sparc.
2726 // SELF +--------+
2727 // | | pad2 | 2 pad to align old SP
2728 // | +--------+ 1
2729 // | | locks | 0
2730 // | +--------+----> OptoReg::stack0(), even aligned
2731 // | | pad1 | 11 pad to align new SP
2732 // | +--------+
2733 // | | | 10
2734 // | | spills | 9 spills
2735 // V | | 8 (pad0 slot for callee)
2736 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
2737 // ^ | out | 7
2738 // | | args | 6 Holes in outgoing args owned by CALLEE
2739 // Owned by +--------+
2740 // CALLEE | new out| 6 Empty on Intel, window on Sparc
2741 // | new |preserve| Must be even-aligned.
2742 // | SP-+--------+----> Matcher::_new_SP, even aligned
2743 // | | |
2744 //
2745 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
2746 // known from SELF's arguments and the Java calling convention.
2747 // Region 6-7 is determined per call site.
2748 // Note 2: If the calling convention leaves holes in the incoming argument
2749 // area, those holes are owned by SELF. Holes in the outgoing area
2750 // are owned by the CALLEE. Holes should not be nessecary in the
2751 // incoming area, as the Java calling convention is completely under
2752 // the control of the AD file. Doubles can be sorted and packed to
2753 // avoid holes. Holes in the outgoing arguments may be nessecary for
2754 // varargs C calling conventions.
2755 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
2756 // even aligned with pad0 as needed.
2757 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
2758 // region 6-11 is even aligned; it may be padded out more so that
2759 // the region from SP to FP meets the minimum stack alignment.
2760 // Note 4: For I2C adapters, the incoming FP may not meet the minimum stack
2761 // alignment. Region 11, pad1, may be dynamically extended so that
2762 // SP meets the minimum alignment.
2763
2764 frame
2765 %{
2766 // What direction does stack grow in (assumed to be same for C & Java)
2767 stack_direction(TOWARDS_LOW);
2768
2769 // These three registers define part of the calling convention
2770 // between compiled code and the interpreter.
2771 inline_cache_reg(RAX); // Inline Cache Register
2772 interpreter_method_oop_reg(RBX); // Method Oop Register when
2773 // calling interpreter
2774
2775 // Optional: name the operand used by cisc-spilling to access
2776 // [stack_pointer + offset]
2777 cisc_spilling_operand_name(indOffset32);
2778
2779 // Number of stack slots consumed by locking an object
2780 sync_stack_slots(2);
2781
2782 // Compiled code's Frame Pointer
2783 frame_pointer(RSP);
2784
2785 // Interpreter stores its frame pointer in a register which is
2786 // stored to the stack by I2CAdaptors.
2787 // I2CAdaptors convert from interpreted java to compiled java.
2788 interpreter_frame_pointer(RBP);
2789
2790 // Stack alignment requirement
2791 stack_alignment(StackAlignmentInBytes); // Alignment size in bytes (128-bit -> 16 bytes)
2792
2793 // Number of stack slots between incoming argument block and the start of
2794 // a new frame. The PROLOG must add this many slots to the stack. The
2795 // EPILOG must remove this many slots. amd64 needs two slots for
2796 // return address.
2797 in_preserve_stack_slots(4 + 2 * VerifyStackAtCalls);
2798
2799 // Number of outgoing stack slots killed above the out_preserve_stack_slots
2800 // for calls to C. Supports the var-args backing area for register parms.
2801 varargs_C_out_slots_killed(frame::arg_reg_save_area_bytes/BytesPerInt);
2802
2803 // The after-PROLOG location of the return address. Location of
2804 // return address specifies a type (REG or STACK) and a number
2805 // representing the register number (i.e. - use a register name) or
2806 // stack slot.
2807 // Ret Addr is on stack in slot 0 if no locks or verification or alignment.
2808 // Otherwise, it is above the locks and verification slot and alignment word
2809 return_addr(STACK - 2 +
2810 round_to((Compile::current()->in_preserve_stack_slots() +
2811 Compile::current()->fixed_slots()),
2812 stack_alignment_in_slots()));
2813
2814 // Body of function which returns an integer array locating
2815 // arguments either in registers or in stack slots. Passed an array
2816 // of ideal registers called "sig" and a "length" count. Stack-slot
2817 // offsets are based on outgoing arguments, i.e. a CALLER setting up
2818 // arguments for a CALLEE. Incoming stack arguments are
2819 // automatically biased by the preserve_stack_slots field above.
2820
2821 calling_convention
2822 %{
2823 // No difference between ingoing/outgoing just pass false
2824 SharedRuntime::java_calling_convention(sig_bt, regs, length, false);
2825 %}
2826
2827 c_calling_convention
2828 %{
2829 // This is obviously always outgoing
2830 (void) SharedRuntime::c_calling_convention(sig_bt, regs, /*regs2=*/NULL, length);
2831 %}
2832
2833 // Location of compiled Java return values. Same as C for now.
2834 return_value
2835 %{
2836 assert(ideal_reg >= Op_RegI && ideal_reg <= Op_RegL,
2837 "only return normal values");
2838
2839 static const int lo[Op_RegL + 1] = {
2840 0,
2841 0,
2842 RAX_num, // Op_RegN
2843 RAX_num, // Op_RegI
2844 RAX_num, // Op_RegP
2845 XMM0_num, // Op_RegF
2846 XMM0_num, // Op_RegD
2847 RAX_num // Op_RegL
2848 };
2849 static const int hi[Op_RegL + 1] = {
2850 0,
2851 0,
2852 OptoReg::Bad, // Op_RegN
2853 OptoReg::Bad, // Op_RegI
2854 RAX_H_num, // Op_RegP
2855 OptoReg::Bad, // Op_RegF
2856 XMM0b_num, // Op_RegD
2857 RAX_H_num // Op_RegL
2858 };
2859 // Excluded flags and vector registers.
2860 assert(ARRAY_SIZE(hi) == _last_machine_leaf - 6, "missing type");
2861 return OptoRegPair(hi[ideal_reg], lo[ideal_reg]);
2862 %}
2863 %}
2864
2865 //----------ATTRIBUTES---------------------------------------------------------
2866 //----------Operand Attributes-------------------------------------------------
2867 op_attrib op_cost(0); // Required cost attribute
2868
2869 //----------Instruction Attributes---------------------------------------------
2870 ins_attrib ins_cost(100); // Required cost attribute
2871 ins_attrib ins_size(8); // Required size attribute (in bits)
2872 ins_attrib ins_short_branch(0); // Required flag: is this instruction
2873 // a non-matching short branch variant
2874 // of some long branch?
2875 ins_attrib ins_alignment(1); // Required alignment attribute (must
2876 // be a power of 2) specifies the
2877 // alignment that some part of the
2878 // instruction (not necessarily the
2879 // start) requires. If > 1, a
2880 // compute_padding() function must be
2881 // provided for the instruction
2882
2883 //----------OPERANDS-----------------------------------------------------------
2884 // Operand definitions must precede instruction definitions for correct parsing
2885 // in the ADLC because operands constitute user defined types which are used in
2886 // instruction definitions.
2887
2888 //----------Simple Operands----------------------------------------------------
2889 // Immediate Operands
2890 // Integer Immediate
2891 operand immI()
2892 %{
2893 match(ConI);
2894
2895 op_cost(10);
2896 format %{ %}
2897 interface(CONST_INTER);
2898 %}
2899
2900 // Constant for test vs zero
2901 operand immI0()
2902 %{
2903 predicate(n->get_int() == 0);
2904 match(ConI);
2905
2906 op_cost(0);
2907 format %{ %}
2908 interface(CONST_INTER);
2909 %}
2910
2911 // Constant for increment
2912 operand immI1()
2913 %{
2914 predicate(n->get_int() == 1);
2915 match(ConI);
2916
2917 op_cost(0);
2918 format %{ %}
2919 interface(CONST_INTER);
2920 %}
2921
2922 // Constant for decrement
2923 operand immI_M1()
2924 %{
2925 predicate(n->get_int() == -1);
2926 match(ConI);
2927
2928 op_cost(0);
2929 format %{ %}
2930 interface(CONST_INTER);
2931 %}
2932
2933 // Valid scale values for addressing modes
2934 operand immI2()
2935 %{
2936 predicate(0 <= n->get_int() && (n->get_int() <= 3));
2937 match(ConI);
2938
2939 format %{ %}
2940 interface(CONST_INTER);
2941 %}
2942
2943 operand immI8()
2944 %{
2945 predicate((-0x80 <= n->get_int()) && (n->get_int() < 0x80));
2946 match(ConI);
2947
2948 op_cost(5);
2949 format %{ %}
2950 interface(CONST_INTER);
2951 %}
2952
2953 operand immI16()
2954 %{
2955 predicate((-32768 <= n->get_int()) && (n->get_int() <= 32767));
2956 match(ConI);
2957
2958 op_cost(10);
2959 format %{ %}
2960 interface(CONST_INTER);
2961 %}
2962
2963 // Int Immediate non-negative
2964 operand immU31()
2965 %{
2966 predicate(n->get_int() >= 0);
2967 match(ConI);
2968
2969 op_cost(0);
2970 format %{ %}
2971 interface(CONST_INTER);
2972 %}
2973
2974 // Constant for long shifts
2975 operand immI_32()
2976 %{
2977 predicate( n->get_int() == 32 );
2978 match(ConI);
2979
2980 op_cost(0);
2981 format %{ %}
2982 interface(CONST_INTER);
2983 %}
2984
2985 // Constant for long shifts
2986 operand immI_64()
2987 %{
2988 predicate( n->get_int() == 64 );
2989 match(ConI);
2990
2991 op_cost(0);
2992 format %{ %}
2993 interface(CONST_INTER);
2994 %}
2995
2996 // Pointer Immediate
2997 operand immP()
2998 %{
2999 match(ConP);
3000
3001 op_cost(10);
3002 format %{ %}
3003 interface(CONST_INTER);
3004 %}
3005
3006 // NULL Pointer Immediate
3007 operand immP0()
3008 %{
3009 predicate(n->get_ptr() == 0);
3010 match(ConP);
3011
3012 op_cost(5);
3013 format %{ %}
3014 interface(CONST_INTER);
3015 %}
3016
3017 // Pointer Immediate
3018 operand immN() %{
3019 match(ConN);
3020
3021 op_cost(10);
3022 format %{ %}
3023 interface(CONST_INTER);
3024 %}
3025
3026 operand immNKlass() %{
3027 match(ConNKlass);
3028
3029 op_cost(10);
3030 format %{ %}
3031 interface(CONST_INTER);
3032 %}
3033
3034 // NULL Pointer Immediate
3035 operand immN0() %{
3036 predicate(n->get_narrowcon() == 0);
3037 match(ConN);
3038
3039 op_cost(5);
3040 format %{ %}
3041 interface(CONST_INTER);
3042 %}
3043
3044 operand immP31()
3045 %{
3046 predicate(n->as_Type()->type()->reloc() == relocInfo::none
3047 && (n->get_ptr() >> 31) == 0);
3048 match(ConP);
3049
3050 op_cost(5);
3051 format %{ %}
3052 interface(CONST_INTER);
3053 %}
3054
3055
3056 // Long Immediate
3057 operand immL()
3058 %{
3059 match(ConL);
3060
3061 op_cost(20);
3062 format %{ %}
3063 interface(CONST_INTER);
3064 %}
3065
3066 // Long Immediate 8-bit
3067 operand immL8()
3068 %{
3069 predicate(-0x80L <= n->get_long() && n->get_long() < 0x80L);
3070 match(ConL);
3071
3072 op_cost(5);
3073 format %{ %}
3074 interface(CONST_INTER);
3075 %}
3076
3077 // Long Immediate 32-bit unsigned
3078 operand immUL32()
3079 %{
3080 predicate(n->get_long() == (unsigned int) (n->get_long()));
3081 match(ConL);
3082
3083 op_cost(10);
3084 format %{ %}
3085 interface(CONST_INTER);
3086 %}
3087
3088 // Long Immediate 32-bit signed
3089 operand immL32()
3090 %{
3091 predicate(n->get_long() == (int) (n->get_long()));
3092 match(ConL);
3093
3094 op_cost(15);
3095 format %{ %}
3096 interface(CONST_INTER);
3097 %}
3098
3099 // Long Immediate zero
3100 operand immL0()
3101 %{
3102 predicate(n->get_long() == 0L);
3103 match(ConL);
3104
3105 op_cost(10);
3106 format %{ %}
3107 interface(CONST_INTER);
3108 %}
3109
3110 // Constant for increment
3111 operand immL1()
3112 %{
3113 predicate(n->get_long() == 1);
3114 match(ConL);
3115
3116 format %{ %}
3117 interface(CONST_INTER);
3118 %}
3119
3120 // Constant for decrement
3121 operand immL_M1()
3122 %{
3123 predicate(n->get_long() == -1);
3124 match(ConL);
3125
3126 format %{ %}
3127 interface(CONST_INTER);
3128 %}
3129
3130 // Long Immediate: the value 10
3131 operand immL10()
3132 %{
3133 predicate(n->get_long() == 10);
3134 match(ConL);
3135
3136 format %{ %}
3137 interface(CONST_INTER);
3138 %}
3139
3140 // Long immediate from 0 to 127.
3141 // Used for a shorter form of long mul by 10.
3142 operand immL_127()
3143 %{
3144 predicate(0 <= n->get_long() && n->get_long() < 0x80);
3145 match(ConL);
3146
3147 op_cost(10);
3148 format %{ %}
3149 interface(CONST_INTER);
3150 %}
3151
3152 // Long Immediate: low 32-bit mask
3153 operand immL_32bits()
3154 %{
3155 predicate(n->get_long() == 0xFFFFFFFFL);
3156 match(ConL);
3157 op_cost(20);
3158
3159 format %{ %}
3160 interface(CONST_INTER);
3161 %}
3162
3163 // Float Immediate zero
3164 operand immF0()
3165 %{
3166 predicate(jint_cast(n->getf()) == 0);
3167 match(ConF);
3168
3169 op_cost(5);
3170 format %{ %}
3171 interface(CONST_INTER);
3172 %}
3173
3174 // Float Immediate
3175 operand immF()
3176 %{
3177 match(ConF);
3178
3179 op_cost(15);
3180 format %{ %}
3181 interface(CONST_INTER);
3182 %}
3183
3184 // Double Immediate zero
3185 operand immD0()
3186 %{
3187 predicate(jlong_cast(n->getd()) == 0);
3188 match(ConD);
3189
3190 op_cost(5);
3191 format %{ %}
3192 interface(CONST_INTER);
3193 %}
3194
3195 // Double Immediate
3196 operand immD()
3197 %{
3198 match(ConD);
3199
3200 op_cost(15);
3201 format %{ %}
3202 interface(CONST_INTER);
3203 %}
3204
3205 // Immediates for special shifts (sign extend)
3206
3207 // Constants for increment
3208 operand immI_16()
3209 %{
3210 predicate(n->get_int() == 16);
3211 match(ConI);
3212
3213 format %{ %}
3214 interface(CONST_INTER);
3215 %}
3216
3217 operand immI_24()
3218 %{
3219 predicate(n->get_int() == 24);
3220 match(ConI);
3221
3222 format %{ %}
3223 interface(CONST_INTER);
3224 %}
3225
3226 // Constant for byte-wide masking
3227 operand immI_255()
3228 %{
3229 predicate(n->get_int() == 255);
3230 match(ConI);
3231
3232 format %{ %}
3233 interface(CONST_INTER);
3234 %}
3235
3236 // Constant for short-wide masking
3237 operand immI_65535()
3238 %{
3239 predicate(n->get_int() == 65535);
3240 match(ConI);
3241
3242 format %{ %}
3243 interface(CONST_INTER);
3244 %}
3245
3246 // Constant for byte-wide masking
3247 operand immL_255()
3248 %{
3249 predicate(n->get_long() == 255);
3250 match(ConL);
3251
3252 format %{ %}
3253 interface(CONST_INTER);
3254 %}
3255
3256 // Constant for short-wide masking
3257 operand immL_65535()
3258 %{
3259 predicate(n->get_long() == 65535);
3260 match(ConL);
3261
3262 format %{ %}
3263 interface(CONST_INTER);
3264 %}
3265
3266 // Register Operands
3267 // Integer Register
3268 operand rRegI()
3269 %{
3270 constraint(ALLOC_IN_RC(int_reg));
3271 match(RegI);
3272
3273 match(rax_RegI);
3274 match(rbx_RegI);
3275 match(rcx_RegI);
3276 match(rdx_RegI);
3277 match(rdi_RegI);
3278
3279 format %{ %}
3280 interface(REG_INTER);
3281 %}
3282
3283 // Special Registers
3284 operand rax_RegI()
3285 %{
3286 constraint(ALLOC_IN_RC(int_rax_reg));
3287 match(RegI);
3288 match(rRegI);
3289
3290 format %{ "RAX" %}
3291 interface(REG_INTER);
3292 %}
3293
3294 // Special Registers
3295 operand rbx_RegI()
3296 %{
3297 constraint(ALLOC_IN_RC(int_rbx_reg));
3298 match(RegI);
3299 match(rRegI);
3300
3301 format %{ "RBX" %}
3302 interface(REG_INTER);
3303 %}
3304
3305 operand rcx_RegI()
3306 %{
3307 constraint(ALLOC_IN_RC(int_rcx_reg));
3308 match(RegI);
3309 match(rRegI);
3310
3311 format %{ "RCX" %}
3312 interface(REG_INTER);
3313 %}
3314
3315 operand rdx_RegI()
3316 %{
3317 constraint(ALLOC_IN_RC(int_rdx_reg));
3318 match(RegI);
3319 match(rRegI);
3320
3321 format %{ "RDX" %}
3322 interface(REG_INTER);
3323 %}
3324
3325 operand rdi_RegI()
3326 %{
3327 constraint(ALLOC_IN_RC(int_rdi_reg));
3328 match(RegI);
3329 match(rRegI);
3330
3331 format %{ "RDI" %}
3332 interface(REG_INTER);
3333 %}
3334
3335 operand no_rcx_RegI()
3336 %{
3337 constraint(ALLOC_IN_RC(int_no_rcx_reg));
3338 match(RegI);
3339 match(rax_RegI);
3340 match(rbx_RegI);
3341 match(rdx_RegI);
3342 match(rdi_RegI);
3343
3344 format %{ %}
3345 interface(REG_INTER);
3346 %}
3347
3348 operand no_rax_rdx_RegI()
3349 %{
3350 constraint(ALLOC_IN_RC(int_no_rax_rdx_reg));
3351 match(RegI);
3352 match(rbx_RegI);
3353 match(rcx_RegI);
3354 match(rdi_RegI);
3355
3356 format %{ %}
3357 interface(REG_INTER);
3358 %}
3359
3360 // Pointer Register
3361 operand any_RegP()
3362 %{
3363 constraint(ALLOC_IN_RC(any_reg));
3364 match(RegP);
3365 match(rax_RegP);
3366 match(rbx_RegP);
3367 match(rdi_RegP);
3368 match(rsi_RegP);
3369 match(rbp_RegP);
3370 match(r15_RegP);
3371 match(rRegP);
3372
3373 format %{ %}
3374 interface(REG_INTER);
3375 %}
3376
3377 operand rRegP()
3378 %{
3379 constraint(ALLOC_IN_RC(ptr_reg));
3380 match(RegP);
3381 match(rax_RegP);
3382 match(rbx_RegP);
3383 match(rdi_RegP);
3384 match(rsi_RegP);
3385 match(rbp_RegP); // See Q&A below about
3386 match(r15_RegP); // r15_RegP and rbp_RegP.
3387
3388 format %{ %}
3389 interface(REG_INTER);
3390 %}
3391
3392 operand rRegN() %{
3393 constraint(ALLOC_IN_RC(int_reg));
3394 match(RegN);
3395
3396 format %{ %}
3397 interface(REG_INTER);
3398 %}
3399
3400 // Question: Why is r15_RegP (the read-only TLS register) a match for rRegP?
3401 // Answer: Operand match rules govern the DFA as it processes instruction inputs.
3402 // It's fine for an instruction input that expects rRegP to match a r15_RegP.
3403 // The output of an instruction is controlled by the allocator, which respects
3404 // register class masks, not match rules. Unless an instruction mentions
3405 // r15_RegP or any_RegP explicitly as its output, r15 will not be considered
3406 // by the allocator as an input.
3407 // The same logic applies to rbp_RegP being a match for rRegP: If PreserveFramePointer==true,
3408 // the RBP is used as a proper frame pointer and is not included in ptr_reg. As a
3409 // result, RBP is not included in the output of the instruction either.
3410
3411 operand no_rax_RegP()
3412 %{
3413 constraint(ALLOC_IN_RC(ptr_no_rax_reg));
3414 match(RegP);
3415 match(rbx_RegP);
3416 match(rsi_RegP);
3417 match(rdi_RegP);
3418
3419 format %{ %}
3420 interface(REG_INTER);
3421 %}
3422
3423 // This operand is not allowed to use RBP even if
3424 // RBP is not used to hold the frame pointer.
3425 operand no_rbp_RegP()
3426 %{
3427 constraint(ALLOC_IN_RC(ptr_reg_no_rbp));
3428 match(RegP);
3429 match(rbx_RegP);
3430 match(rsi_RegP);
3431 match(rdi_RegP);
3432
3433 format %{ %}
3434 interface(REG_INTER);
3435 %}
3436
3437 operand no_rax_rbx_RegP()
3438 %{
3439 constraint(ALLOC_IN_RC(ptr_no_rax_rbx_reg));
3440 match(RegP);
3441 match(rsi_RegP);
3442 match(rdi_RegP);
3443
3444 format %{ %}
3445 interface(REG_INTER);
3446 %}
3447
3448 // Special Registers
3449 // Return a pointer value
3450 operand rax_RegP()
3451 %{
3452 constraint(ALLOC_IN_RC(ptr_rax_reg));
3453 match(RegP);
3454 match(rRegP);
3455
3456 format %{ %}
3457 interface(REG_INTER);
3458 %}
3459
3460 // Special Registers
3461 // Return a compressed pointer value
3462 operand rax_RegN()
3463 %{
3464 constraint(ALLOC_IN_RC(int_rax_reg));
3465 match(RegN);
3466 match(rRegN);
3467
3468 format %{ %}
3469 interface(REG_INTER);
3470 %}
3471
3472 // Used in AtomicAdd
3473 operand rbx_RegP()
3474 %{
3475 constraint(ALLOC_IN_RC(ptr_rbx_reg));
3476 match(RegP);
3477 match(rRegP);
3478
3479 format %{ %}
3480 interface(REG_INTER);
3481 %}
3482
3483 operand rsi_RegP()
3484 %{
3485 constraint(ALLOC_IN_RC(ptr_rsi_reg));
3486 match(RegP);
3487 match(rRegP);
3488
3489 format %{ %}
3490 interface(REG_INTER);
3491 %}
3492
3493 // Used in rep stosq
3494 operand rdi_RegP()
3495 %{
3496 constraint(ALLOC_IN_RC(ptr_rdi_reg));
3497 match(RegP);
3498 match(rRegP);
3499
3500 format %{ %}
3501 interface(REG_INTER);
3502 %}
3503
3504 operand r15_RegP()
3505 %{
3506 constraint(ALLOC_IN_RC(ptr_r15_reg));
3507 match(RegP);
3508 match(rRegP);
3509
3510 format %{ %}
3511 interface(REG_INTER);
3512 %}
3513
3514 operand rRegL()
3515 %{
3516 constraint(ALLOC_IN_RC(long_reg));
3517 match(RegL);
3518 match(rax_RegL);
3519 match(rdx_RegL);
3520
3521 format %{ %}
3522 interface(REG_INTER);
3523 %}
3524
3525 // Special Registers
3526 operand no_rax_rdx_RegL()
3527 %{
3528 constraint(ALLOC_IN_RC(long_no_rax_rdx_reg));
3529 match(RegL);
3530 match(rRegL);
3531
3532 format %{ %}
3533 interface(REG_INTER);
3534 %}
3535
3536 operand no_rax_RegL()
3537 %{
3538 constraint(ALLOC_IN_RC(long_no_rax_rdx_reg));
3539 match(RegL);
3540 match(rRegL);
3541 match(rdx_RegL);
3542
3543 format %{ %}
3544 interface(REG_INTER);
3545 %}
3546
3547 operand no_rcx_RegL()
3548 %{
3549 constraint(ALLOC_IN_RC(long_no_rcx_reg));
3550 match(RegL);
3551 match(rRegL);
3552
3553 format %{ %}
3554 interface(REG_INTER);
3555 %}
3556
3557 operand rax_RegL()
3558 %{
3559 constraint(ALLOC_IN_RC(long_rax_reg));
3560 match(RegL);
3561 match(rRegL);
3562
3563 format %{ "RAX" %}
3564 interface(REG_INTER);
3565 %}
3566
3567 operand rcx_RegL()
3568 %{
3569 constraint(ALLOC_IN_RC(long_rcx_reg));
3570 match(RegL);
3571 match(rRegL);
3572
3573 format %{ %}
3574 interface(REG_INTER);
3575 %}
3576
3577 operand rdx_RegL()
3578 %{
3579 constraint(ALLOC_IN_RC(long_rdx_reg));
3580 match(RegL);
3581 match(rRegL);
3582
3583 format %{ %}
3584 interface(REG_INTER);
3585 %}
3586
3587 // Flags register, used as output of compare instructions
3588 operand rFlagsReg()
3589 %{
3590 constraint(ALLOC_IN_RC(int_flags));
3591 match(RegFlags);
3592
3593 format %{ "RFLAGS" %}
3594 interface(REG_INTER);
3595 %}
3596
3597 // Flags register, used as output of FLOATING POINT compare instructions
3598 operand rFlagsRegU()
3599 %{
3600 constraint(ALLOC_IN_RC(int_flags));
3601 match(RegFlags);
3602
3603 format %{ "RFLAGS_U" %}
3604 interface(REG_INTER);
3605 %}
3606
3607 operand rFlagsRegUCF() %{
3608 constraint(ALLOC_IN_RC(int_flags));
3609 match(RegFlags);
3610 predicate(false);
3611
3612 format %{ "RFLAGS_U_CF" %}
3613 interface(REG_INTER);
3614 %}
3615
3616 // Float register operands
3617 operand regF() %{
3618 constraint(ALLOC_IN_RC(float_reg));
3619 match(RegF);
3620
3621 format %{ %}
3622 interface(REG_INTER);
3623 %}
3624
3625 // Double register operands
3626 operand regD() %{
3627 constraint(ALLOC_IN_RC(double_reg));
3628 match(RegD);
3629
3630 format %{ %}
3631 interface(REG_INTER);
3632 %}
3633
3634 // Vectors
3635 operand vecS() %{
3636 constraint(ALLOC_IN_RC(vectors_reg));
3637 match(VecS);
3638
3639 format %{ %}
3640 interface(REG_INTER);
3641 %}
3642
3643 operand vecD() %{
3644 constraint(ALLOC_IN_RC(vectord_reg));
3645 match(VecD);
3646
3647 format %{ %}
3648 interface(REG_INTER);
3649 %}
3650
3651 operand vecX() %{
3652 constraint(ALLOC_IN_RC(vectorx_reg));
3653 match(VecX);
3654
3655 format %{ %}
3656 interface(REG_INTER);
3657 %}
3658
3659 operand vecY() %{
3660 constraint(ALLOC_IN_RC(vectory_reg));
3661 match(VecY);
3662
3663 format %{ %}
3664 interface(REG_INTER);
3665 %}
3666
3667 //----------Memory Operands----------------------------------------------------
3668 // Direct Memory Operand
3669 // operand direct(immP addr)
3670 // %{
3671 // match(addr);
3672
3673 // format %{ "[$addr]" %}
3674 // interface(MEMORY_INTER) %{
3675 // base(0xFFFFFFFF);
3676 // index(0x4);
3677 // scale(0x0);
3678 // disp($addr);
3679 // %}
3680 // %}
3681
3682 // Indirect Memory Operand
3683 operand indirect(any_RegP reg)
3684 %{
3685 constraint(ALLOC_IN_RC(ptr_reg));
3686 match(reg);
3687
3688 format %{ "[$reg]" %}
3689 interface(MEMORY_INTER) %{
3690 base($reg);
3691 index(0x4);
3692 scale(0x0);
3693 disp(0x0);
3694 %}
3695 %}
3696
3697 // Indirect Memory Plus Short Offset Operand
3698 operand indOffset8(any_RegP reg, immL8 off)
3699 %{
3700 constraint(ALLOC_IN_RC(ptr_reg));
3701 match(AddP reg off);
3702
3703 format %{ "[$reg + $off (8-bit)]" %}
3704 interface(MEMORY_INTER) %{
3705 base($reg);
3706 index(0x4);
3707 scale(0x0);
3708 disp($off);
3709 %}
3710 %}
3711
3712 // Indirect Memory Plus Long Offset Operand
3713 operand indOffset32(any_RegP reg, immL32 off)
3714 %{
3715 constraint(ALLOC_IN_RC(ptr_reg));
3716 match(AddP reg off);
3717
3718 format %{ "[$reg + $off (32-bit)]" %}
3719 interface(MEMORY_INTER) %{
3720 base($reg);
3721 index(0x4);
3722 scale(0x0);
3723 disp($off);
3724 %}
3725 %}
3726
3727 // Indirect Memory Plus Index Register Plus Offset Operand
3728 operand indIndexOffset(any_RegP reg, rRegL lreg, immL32 off)
3729 %{
3730 constraint(ALLOC_IN_RC(ptr_reg));
3731 match(AddP (AddP reg lreg) off);
3732
3733 op_cost(10);
3734 format %{"[$reg + $off + $lreg]" %}
3735 interface(MEMORY_INTER) %{
3736 base($reg);
3737 index($lreg);
3738 scale(0x0);
3739 disp($off);
3740 %}
3741 %}
3742
3743 // Indirect Memory Plus Index Register Plus Offset Operand
3744 operand indIndex(any_RegP reg, rRegL lreg)
3745 %{
3746 constraint(ALLOC_IN_RC(ptr_reg));
3747 match(AddP reg lreg);
3748
3749 op_cost(10);
3750 format %{"[$reg + $lreg]" %}
3751 interface(MEMORY_INTER) %{
3752 base($reg);
3753 index($lreg);
3754 scale(0x0);
3755 disp(0x0);
3756 %}
3757 %}
3758
3759 // Indirect Memory Times Scale Plus Index Register
3760 operand indIndexScale(any_RegP reg, rRegL lreg, immI2 scale)
3761 %{
3762 constraint(ALLOC_IN_RC(ptr_reg));
3763 match(AddP reg (LShiftL lreg scale));
3764
3765 op_cost(10);
3766 format %{"[$reg + $lreg << $scale]" %}
3767 interface(MEMORY_INTER) %{
3768 base($reg);
3769 index($lreg);
3770 scale($scale);
3771 disp(0x0);
3772 %}
3773 %}
3774
3775 operand indPosIndexScale(any_RegP reg, rRegI idx, immI2 scale)
3776 %{
3777 constraint(ALLOC_IN_RC(ptr_reg));
3778 predicate(n->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0);
3779 match(AddP reg (LShiftL (ConvI2L idx) scale));
3780
3781 op_cost(10);
3782 format %{"[$reg + pos $idx << $scale]" %}
3783 interface(MEMORY_INTER) %{
3784 base($reg);
3785 index($idx);
3786 scale($scale);
3787 disp(0x0);
3788 %}
3789 %}
3790
3791 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
3792 operand indIndexScaleOffset(any_RegP reg, immL32 off, rRegL lreg, immI2 scale)
3793 %{
3794 constraint(ALLOC_IN_RC(ptr_reg));
3795 match(AddP (AddP reg (LShiftL lreg scale)) off);
3796
3797 op_cost(10);
3798 format %{"[$reg + $off + $lreg << $scale]" %}
3799 interface(MEMORY_INTER) %{
3800 base($reg);
3801 index($lreg);
3802 scale($scale);
3803 disp($off);
3804 %}
3805 %}
3806
3807 // Indirect Memory Plus Positive Index Register Plus Offset Operand
3808 operand indPosIndexOffset(any_RegP reg, immL32 off, rRegI idx)
3809 %{
3810 constraint(ALLOC_IN_RC(ptr_reg));
3811 predicate(n->in(2)->in(3)->as_Type()->type()->is_long()->_lo >= 0);
3812 match(AddP (AddP reg (ConvI2L idx)) off);
3813
3814 op_cost(10);
3815 format %{"[$reg + $off + $idx]" %}
3816 interface(MEMORY_INTER) %{
3817 base($reg);
3818 index($idx);
3819 scale(0x0);
3820 disp($off);
3821 %}
3822 %}
3823
3824 // Indirect Memory Times Scale Plus Positive Index Register Plus Offset Operand
3825 operand indPosIndexScaleOffset(any_RegP reg, immL32 off, rRegI idx, immI2 scale)
3826 %{
3827 constraint(ALLOC_IN_RC(ptr_reg));
3828 predicate(n->in(2)->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0);
3829 match(AddP (AddP reg (LShiftL (ConvI2L idx) scale)) off);
3830
3831 op_cost(10);
3832 format %{"[$reg + $off + $idx << $scale]" %}
3833 interface(MEMORY_INTER) %{
3834 base($reg);
3835 index($idx);
3836 scale($scale);
3837 disp($off);
3838 %}
3839 %}
3840
3841 // Indirect Narrow Oop Plus Offset Operand
3842 // Note: x86 architecture doesn't support "scale * index + offset" without a base
3843 // we can't free r12 even with Universe::narrow_oop_base() == NULL.
3844 operand indCompressedOopOffset(rRegN reg, immL32 off) %{
3845 predicate(UseCompressedOops && (Universe::narrow_oop_shift() == Address::times_8));
3846 constraint(ALLOC_IN_RC(ptr_reg));
3847 match(AddP (DecodeN reg) off);
3848
3849 op_cost(10);
3850 format %{"[R12 + $reg << 3 + $off] (compressed oop addressing)" %}
3851 interface(MEMORY_INTER) %{
3852 base(0xc); // R12
3853 index($reg);
3854 scale(0x3);
3855 disp($off);
3856 %}
3857 %}
3858
3859 // Indirect Memory Operand
3860 operand indirectNarrow(rRegN reg)
3861 %{
3862 predicate(Universe::narrow_oop_shift() == 0);
3863 constraint(ALLOC_IN_RC(ptr_reg));
3864 match(DecodeN reg);
3865
3866 format %{ "[$reg]" %}
3867 interface(MEMORY_INTER) %{
3868 base($reg);
3869 index(0x4);
3870 scale(0x0);
3871 disp(0x0);
3872 %}
3873 %}
3874
3875 // Indirect Memory Plus Short Offset Operand
3876 operand indOffset8Narrow(rRegN reg, immL8 off)
3877 %{
3878 predicate(Universe::narrow_oop_shift() == 0);
3879 constraint(ALLOC_IN_RC(ptr_reg));
3880 match(AddP (DecodeN reg) off);
3881
3882 format %{ "[$reg + $off (8-bit)]" %}
3883 interface(MEMORY_INTER) %{
3884 base($reg);
3885 index(0x4);
3886 scale(0x0);
3887 disp($off);
3888 %}
3889 %}
3890
3891 // Indirect Memory Plus Long Offset Operand
3892 operand indOffset32Narrow(rRegN reg, immL32 off)
3893 %{
3894 predicate(Universe::narrow_oop_shift() == 0);
3895 constraint(ALLOC_IN_RC(ptr_reg));
3896 match(AddP (DecodeN reg) off);
3897
3898 format %{ "[$reg + $off (32-bit)]" %}
3899 interface(MEMORY_INTER) %{
3900 base($reg);
3901 index(0x4);
3902 scale(0x0);
3903 disp($off);
3904 %}
3905 %}
3906
3907 // Indirect Memory Plus Index Register Plus Offset Operand
3908 operand indIndexOffsetNarrow(rRegN reg, rRegL lreg, immL32 off)
3909 %{
3910 predicate(Universe::narrow_oop_shift() == 0);
3911 constraint(ALLOC_IN_RC(ptr_reg));
3912 match(AddP (AddP (DecodeN reg) lreg) off);
3913
3914 op_cost(10);
3915 format %{"[$reg + $off + $lreg]" %}
3916 interface(MEMORY_INTER) %{
3917 base($reg);
3918 index($lreg);
3919 scale(0x0);
3920 disp($off);
3921 %}
3922 %}
3923
3924 // Indirect Memory Plus Index Register Plus Offset Operand
3925 operand indIndexNarrow(rRegN reg, rRegL lreg)
3926 %{
3927 predicate(Universe::narrow_oop_shift() == 0);
3928 constraint(ALLOC_IN_RC(ptr_reg));
3929 match(AddP (DecodeN reg) lreg);
3930
3931 op_cost(10);
3932 format %{"[$reg + $lreg]" %}
3933 interface(MEMORY_INTER) %{
3934 base($reg);
3935 index($lreg);
3936 scale(0x0);
3937 disp(0x0);
3938 %}
3939 %}
3940
3941 // Indirect Memory Times Scale Plus Index Register
3942 operand indIndexScaleNarrow(rRegN reg, rRegL lreg, immI2 scale)
3943 %{
3944 predicate(Universe::narrow_oop_shift() == 0);
3945 constraint(ALLOC_IN_RC(ptr_reg));
3946 match(AddP (DecodeN reg) (LShiftL lreg scale));
3947
3948 op_cost(10);
3949 format %{"[$reg + $lreg << $scale]" %}
3950 interface(MEMORY_INTER) %{
3951 base($reg);
3952 index($lreg);
3953 scale($scale);
3954 disp(0x0);
3955 %}
3956 %}
3957
3958 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
3959 operand indIndexScaleOffsetNarrow(rRegN reg, immL32 off, rRegL lreg, immI2 scale)
3960 %{
3961 predicate(Universe::narrow_oop_shift() == 0);
3962 constraint(ALLOC_IN_RC(ptr_reg));
3963 match(AddP (AddP (DecodeN reg) (LShiftL lreg scale)) off);
3964
3965 op_cost(10);
3966 format %{"[$reg + $off + $lreg << $scale]" %}
3967 interface(MEMORY_INTER) %{
3968 base($reg);
3969 index($lreg);
3970 scale($scale);
3971 disp($off);
3972 %}
3973 %}
3974
3975 // Indirect Memory Times Plus Positive Index Register Plus Offset Operand
3976 operand indPosIndexOffsetNarrow(rRegN reg, immL32 off, rRegI idx)
3977 %{
3978 constraint(ALLOC_IN_RC(ptr_reg));
3979 predicate(Universe::narrow_oop_shift() == 0 && n->in(2)->in(3)->as_Type()->type()->is_long()->_lo >= 0);
3980 match(AddP (AddP (DecodeN reg) (ConvI2L idx)) off);
3981
3982 op_cost(10);
3983 format %{"[$reg + $off + $idx]" %}
3984 interface(MEMORY_INTER) %{
3985 base($reg);
3986 index($idx);
3987 scale(0x0);
3988 disp($off);
3989 %}
3990 %}
3991
3992 // Indirect Memory Times Scale Plus Positive Index Register Plus Offset Operand
3993 operand indPosIndexScaleOffsetNarrow(rRegN reg, immL32 off, rRegI idx, immI2 scale)
3994 %{
3995 constraint(ALLOC_IN_RC(ptr_reg));
3996 predicate(Universe::narrow_oop_shift() == 0 && n->in(2)->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0);
3997 match(AddP (AddP (DecodeN reg) (LShiftL (ConvI2L idx) scale)) off);
3998
3999 op_cost(10);
4000 format %{"[$reg + $off + $idx << $scale]" %}
4001 interface(MEMORY_INTER) %{
4002 base($reg);
4003 index($idx);
4004 scale($scale);
4005 disp($off);
4006 %}
4007 %}
4008
4009 //----------Special Memory Operands--------------------------------------------
4010 // Stack Slot Operand - This operand is used for loading and storing temporary
4011 // values on the stack where a match requires a value to
4012 // flow through memory.
4013 operand stackSlotP(sRegP reg)
4014 %{
4015 constraint(ALLOC_IN_RC(stack_slots));
4016 // No match rule because this operand is only generated in matching
4017
4018 format %{ "[$reg]" %}
4019 interface(MEMORY_INTER) %{
4020 base(0x4); // RSP
4021 index(0x4); // No Index
4022 scale(0x0); // No Scale
4023 disp($reg); // Stack Offset
4024 %}
4025 %}
4026
4027 operand stackSlotI(sRegI reg)
4028 %{
4029 constraint(ALLOC_IN_RC(stack_slots));
4030 // No match rule because this operand is only generated in matching
4031
4032 format %{ "[$reg]" %}
4033 interface(MEMORY_INTER) %{
4034 base(0x4); // RSP
4035 index(0x4); // No Index
4036 scale(0x0); // No Scale
4037 disp($reg); // Stack Offset
4038 %}
4039 %}
4040
4041 operand stackSlotF(sRegF reg)
4042 %{
4043 constraint(ALLOC_IN_RC(stack_slots));
4044 // No match rule because this operand is only generated in matching
4045
4046 format %{ "[$reg]" %}
4047 interface(MEMORY_INTER) %{
4048 base(0x4); // RSP
4049 index(0x4); // No Index
4050 scale(0x0); // No Scale
4051 disp($reg); // Stack Offset
4052 %}
4053 %}
4054
4055 operand stackSlotD(sRegD reg)
4056 %{
4057 constraint(ALLOC_IN_RC(stack_slots));
4058 // No match rule because this operand is only generated in matching
4059
4060 format %{ "[$reg]" %}
4061 interface(MEMORY_INTER) %{
4062 base(0x4); // RSP
4063 index(0x4); // No Index
4064 scale(0x0); // No Scale
4065 disp($reg); // Stack Offset
4066 %}
4067 %}
4068 operand stackSlotL(sRegL reg)
4069 %{
4070 constraint(ALLOC_IN_RC(stack_slots));
4071 // No match rule because this operand is only generated in matching
4072
4073 format %{ "[$reg]" %}
4074 interface(MEMORY_INTER) %{
4075 base(0x4); // RSP
4076 index(0x4); // No Index
4077 scale(0x0); // No Scale
4078 disp($reg); // Stack Offset
4079 %}
4080 %}
4081
4082 //----------Conditional Branch Operands----------------------------------------
4083 // Comparison Op - This is the operation of the comparison, and is limited to
4084 // the following set of codes:
4085 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
4086 //
4087 // Other attributes of the comparison, such as unsignedness, are specified
4088 // by the comparison instruction that sets a condition code flags register.
4089 // That result is represented by a flags operand whose subtype is appropriate
4090 // to the unsignedness (etc.) of the comparison.
4091 //
4092 // Later, the instruction which matches both the Comparison Op (a Bool) and
4093 // the flags (produced by the Cmp) specifies the coding of the comparison op
4094 // by matching a specific subtype of Bool operand below, such as cmpOpU.
4095
4096 // Comparision Code
4097 operand cmpOp()
4098 %{
4099 match(Bool);
4100
4101 format %{ "" %}
4102 interface(COND_INTER) %{
4103 equal(0x4, "e");
4104 not_equal(0x5, "ne");
4105 less(0xC, "l");
4106 greater_equal(0xD, "ge");
4107 less_equal(0xE, "le");
4108 greater(0xF, "g");
4109 overflow(0x0, "o");
4110 no_overflow(0x1, "no");
4111 %}
4112 %}
4113
4114 // Comparison Code, unsigned compare. Used by FP also, with
4115 // C2 (unordered) turned into GT or LT already. The other bits
4116 // C0 and C3 are turned into Carry & Zero flags.
4117 operand cmpOpU()
4118 %{
4119 match(Bool);
4120
4121 format %{ "" %}
4122 interface(COND_INTER) %{
4123 equal(0x4, "e");
4124 not_equal(0x5, "ne");
4125 less(0x2, "b");
4126 greater_equal(0x3, "nb");
4127 less_equal(0x6, "be");
4128 greater(0x7, "nbe");
4129 overflow(0x0, "o");
4130 no_overflow(0x1, "no");
4131 %}
4132 %}
4133
4134
4135 // Floating comparisons that don't require any fixup for the unordered case
4136 operand cmpOpUCF() %{
4137 match(Bool);
4138 predicate(n->as_Bool()->_test._test == BoolTest::lt ||
4139 n->as_Bool()->_test._test == BoolTest::ge ||
4140 n->as_Bool()->_test._test == BoolTest::le ||
4141 n->as_Bool()->_test._test == BoolTest::gt);
4142 format %{ "" %}
4143 interface(COND_INTER) %{
4144 equal(0x4, "e");
4145 not_equal(0x5, "ne");
4146 less(0x2, "b");
4147 greater_equal(0x3, "nb");
4148 less_equal(0x6, "be");
4149 greater(0x7, "nbe");
4150 overflow(0x0, "o");
4151 no_overflow(0x1, "no");
4152 %}
4153 %}
4154
4155
4156 // Floating comparisons that can be fixed up with extra conditional jumps
4157 operand cmpOpUCF2() %{
4158 match(Bool);
4159 predicate(n->as_Bool()->_test._test == BoolTest::ne ||
4160 n->as_Bool()->_test._test == BoolTest::eq);
4161 format %{ "" %}
4162 interface(COND_INTER) %{
4163 equal(0x4, "e");
4164 not_equal(0x5, "ne");
4165 less(0x2, "b");
4166 greater_equal(0x3, "nb");
4167 less_equal(0x6, "be");
4168 greater(0x7, "nbe");
4169 overflow(0x0, "o");
4170 no_overflow(0x1, "no");
4171 %}
4172 %}
4173
4174
4175 //----------OPERAND CLASSES----------------------------------------------------
4176 // Operand Classes are groups of operands that are used as to simplify
4177 // instruction definitions by not requiring the AD writer to specify separate
4178 // instructions for every form of operand when the instruction accepts
4179 // multiple operand types with the same basic encoding and format. The classic
4180 // case of this is memory operands.
4181
4182 opclass memory(indirect, indOffset8, indOffset32, indIndexOffset, indIndex,
4183 indIndexScale, indPosIndexScale, indIndexScaleOffset, indPosIndexOffset, indPosIndexScaleOffset,
4184 indCompressedOopOffset,
4185 indirectNarrow, indOffset8Narrow, indOffset32Narrow,
4186 indIndexOffsetNarrow, indIndexNarrow, indIndexScaleNarrow,
4187 indIndexScaleOffsetNarrow, indPosIndexOffsetNarrow, indPosIndexScaleOffsetNarrow);
4188
4189 //----------PIPELINE-----------------------------------------------------------
4190 // Rules which define the behavior of the target architectures pipeline.
4191 pipeline %{
4192
4193 //----------ATTRIBUTES---------------------------------------------------------
4194 attributes %{
4195 variable_size_instructions; // Fixed size instructions
4196 max_instructions_per_bundle = 3; // Up to 3 instructions per bundle
4197 instruction_unit_size = 1; // An instruction is 1 bytes long
4198 instruction_fetch_unit_size = 16; // The processor fetches one line
4199 instruction_fetch_units = 1; // of 16 bytes
4200
4201 // List of nop instructions
4202 nops( MachNop );
4203 %}
4204
4205 //----------RESOURCES----------------------------------------------------------
4206 // Resources are the functional units available to the machine
4207
4208 // Generic P2/P3 pipeline
4209 // 3 decoders, only D0 handles big operands; a "bundle" is the limit of
4210 // 3 instructions decoded per cycle.
4211 // 2 load/store ops per cycle, 1 branch, 1 FPU,
4212 // 3 ALU op, only ALU0 handles mul instructions.
4213 resources( D0, D1, D2, DECODE = D0 | D1 | D2,
4214 MS0, MS1, MS2, MEM = MS0 | MS1 | MS2,
4215 BR, FPU,
4216 ALU0, ALU1, ALU2, ALU = ALU0 | ALU1 | ALU2);
4217
4218 //----------PIPELINE DESCRIPTION-----------------------------------------------
4219 // Pipeline Description specifies the stages in the machine's pipeline
4220
4221 // Generic P2/P3 pipeline
4222 pipe_desc(S0, S1, S2, S3, S4, S5);
4223
4224 //----------PIPELINE CLASSES---------------------------------------------------
4225 // Pipeline Classes describe the stages in which input and output are
4226 // referenced by the hardware pipeline.
4227
4228 // Naming convention: ialu or fpu
4229 // Then: _reg
4230 // Then: _reg if there is a 2nd register
4231 // Then: _long if it's a pair of instructions implementing a long
4232 // Then: _fat if it requires the big decoder
4233 // Or: _mem if it requires the big decoder and a memory unit.
4234
4235 // Integer ALU reg operation
4236 pipe_class ialu_reg(rRegI dst)
4237 %{
4238 single_instruction;
4239 dst : S4(write);
4240 dst : S3(read);
4241 DECODE : S0; // any decoder
4242 ALU : S3; // any alu
4243 %}
4244
4245 // Long ALU reg operation
4246 pipe_class ialu_reg_long(rRegL dst)
4247 %{
4248 instruction_count(2);
4249 dst : S4(write);
4250 dst : S3(read);
4251 DECODE : S0(2); // any 2 decoders
4252 ALU : S3(2); // both alus
4253 %}
4254
4255 // Integer ALU reg operation using big decoder
4256 pipe_class ialu_reg_fat(rRegI dst)
4257 %{
4258 single_instruction;
4259 dst : S4(write);
4260 dst : S3(read);
4261 D0 : S0; // big decoder only
4262 ALU : S3; // any alu
4263 %}
4264
4265 // Long ALU reg operation using big decoder
4266 pipe_class ialu_reg_long_fat(rRegL dst)
4267 %{
4268 instruction_count(2);
4269 dst : S4(write);
4270 dst : S3(read);
4271 D0 : S0(2); // big decoder only; twice
4272 ALU : S3(2); // any 2 alus
4273 %}
4274
4275 // Integer ALU reg-reg operation
4276 pipe_class ialu_reg_reg(rRegI dst, rRegI src)
4277 %{
4278 single_instruction;
4279 dst : S4(write);
4280 src : S3(read);
4281 DECODE : S0; // any decoder
4282 ALU : S3; // any alu
4283 %}
4284
4285 // Long ALU reg-reg operation
4286 pipe_class ialu_reg_reg_long(rRegL dst, rRegL src)
4287 %{
4288 instruction_count(2);
4289 dst : S4(write);
4290 src : S3(read);
4291 DECODE : S0(2); // any 2 decoders
4292 ALU : S3(2); // both alus
4293 %}
4294
4295 // Integer ALU reg-reg operation
4296 pipe_class ialu_reg_reg_fat(rRegI dst, memory src)
4297 %{
4298 single_instruction;
4299 dst : S4(write);
4300 src : S3(read);
4301 D0 : S0; // big decoder only
4302 ALU : S3; // any alu
4303 %}
4304
4305 // Long ALU reg-reg operation
4306 pipe_class ialu_reg_reg_long_fat(rRegL dst, rRegL src)
4307 %{
4308 instruction_count(2);
4309 dst : S4(write);
4310 src : S3(read);
4311 D0 : S0(2); // big decoder only; twice
4312 ALU : S3(2); // both alus
4313 %}
4314
4315 // Integer ALU reg-mem operation
4316 pipe_class ialu_reg_mem(rRegI dst, memory mem)
4317 %{
4318 single_instruction;
4319 dst : S5(write);
4320 mem : S3(read);
4321 D0 : S0; // big decoder only
4322 ALU : S4; // any alu
4323 MEM : S3; // any mem
4324 %}
4325
4326 // Integer mem operation (prefetch)
4327 pipe_class ialu_mem(memory mem)
4328 %{
4329 single_instruction;
4330 mem : S3(read);
4331 D0 : S0; // big decoder only
4332 MEM : S3; // any mem
4333 %}
4334
4335 // Integer Store to Memory
4336 pipe_class ialu_mem_reg(memory mem, rRegI src)
4337 %{
4338 single_instruction;
4339 mem : S3(read);
4340 src : S5(read);
4341 D0 : S0; // big decoder only
4342 ALU : S4; // any alu
4343 MEM : S3;
4344 %}
4345
4346 // // Long Store to Memory
4347 // pipe_class ialu_mem_long_reg(memory mem, rRegL src)
4348 // %{
4349 // instruction_count(2);
4350 // mem : S3(read);
4351 // src : S5(read);
4352 // D0 : S0(2); // big decoder only; twice
4353 // ALU : S4(2); // any 2 alus
4354 // MEM : S3(2); // Both mems
4355 // %}
4356
4357 // Integer Store to Memory
4358 pipe_class ialu_mem_imm(memory mem)
4359 %{
4360 single_instruction;
4361 mem : S3(read);
4362 D0 : S0; // big decoder only
4363 ALU : S4; // any alu
4364 MEM : S3;
4365 %}
4366
4367 // Integer ALU0 reg-reg operation
4368 pipe_class ialu_reg_reg_alu0(rRegI dst, rRegI src)
4369 %{
4370 single_instruction;
4371 dst : S4(write);
4372 src : S3(read);
4373 D0 : S0; // Big decoder only
4374 ALU0 : S3; // only alu0
4375 %}
4376
4377 // Integer ALU0 reg-mem operation
4378 pipe_class ialu_reg_mem_alu0(rRegI dst, memory mem)
4379 %{
4380 single_instruction;
4381 dst : S5(write);
4382 mem : S3(read);
4383 D0 : S0; // big decoder only
4384 ALU0 : S4; // ALU0 only
4385 MEM : S3; // any mem
4386 %}
4387
4388 // Integer ALU reg-reg operation
4389 pipe_class ialu_cr_reg_reg(rFlagsReg cr, rRegI src1, rRegI src2)
4390 %{
4391 single_instruction;
4392 cr : S4(write);
4393 src1 : S3(read);
4394 src2 : S3(read);
4395 DECODE : S0; // any decoder
4396 ALU : S3; // any alu
4397 %}
4398
4399 // Integer ALU reg-imm operation
4400 pipe_class ialu_cr_reg_imm(rFlagsReg cr, rRegI src1)
4401 %{
4402 single_instruction;
4403 cr : S4(write);
4404 src1 : S3(read);
4405 DECODE : S0; // any decoder
4406 ALU : S3; // any alu
4407 %}
4408
4409 // Integer ALU reg-mem operation
4410 pipe_class ialu_cr_reg_mem(rFlagsReg cr, rRegI src1, memory src2)
4411 %{
4412 single_instruction;
4413 cr : S4(write);
4414 src1 : S3(read);
4415 src2 : S3(read);
4416 D0 : S0; // big decoder only
4417 ALU : S4; // any alu
4418 MEM : S3;
4419 %}
4420
4421 // Conditional move reg-reg
4422 pipe_class pipe_cmplt( rRegI p, rRegI q, rRegI y)
4423 %{
4424 instruction_count(4);
4425 y : S4(read);
4426 q : S3(read);
4427 p : S3(read);
4428 DECODE : S0(4); // any decoder
4429 %}
4430
4431 // Conditional move reg-reg
4432 pipe_class pipe_cmov_reg( rRegI dst, rRegI src, rFlagsReg cr)
4433 %{
4434 single_instruction;
4435 dst : S4(write);
4436 src : S3(read);
4437 cr : S3(read);
4438 DECODE : S0; // any decoder
4439 %}
4440
4441 // Conditional move reg-mem
4442 pipe_class pipe_cmov_mem( rFlagsReg cr, rRegI dst, memory src)
4443 %{
4444 single_instruction;
4445 dst : S4(write);
4446 src : S3(read);
4447 cr : S3(read);
4448 DECODE : S0; // any decoder
4449 MEM : S3;
4450 %}
4451
4452 // Conditional move reg-reg long
4453 pipe_class pipe_cmov_reg_long( rFlagsReg cr, rRegL dst, rRegL src)
4454 %{
4455 single_instruction;
4456 dst : S4(write);
4457 src : S3(read);
4458 cr : S3(read);
4459 DECODE : S0(2); // any 2 decoders
4460 %}
4461
4462 // XXX
4463 // // Conditional move double reg-reg
4464 // pipe_class pipe_cmovD_reg( rFlagsReg cr, regDPR1 dst, regD src)
4465 // %{
4466 // single_instruction;
4467 // dst : S4(write);
4468 // src : S3(read);
4469 // cr : S3(read);
4470 // DECODE : S0; // any decoder
4471 // %}
4472
4473 // Float reg-reg operation
4474 pipe_class fpu_reg(regD dst)
4475 %{
4476 instruction_count(2);
4477 dst : S3(read);
4478 DECODE : S0(2); // any 2 decoders
4479 FPU : S3;
4480 %}
4481
4482 // Float reg-reg operation
4483 pipe_class fpu_reg_reg(regD dst, regD src)
4484 %{
4485 instruction_count(2);
4486 dst : S4(write);
4487 src : S3(read);
4488 DECODE : S0(2); // any 2 decoders
4489 FPU : S3;
4490 %}
4491
4492 // Float reg-reg operation
4493 pipe_class fpu_reg_reg_reg(regD dst, regD src1, regD src2)
4494 %{
4495 instruction_count(3);
4496 dst : S4(write);
4497 src1 : S3(read);
4498 src2 : S3(read);
4499 DECODE : S0(3); // any 3 decoders
4500 FPU : S3(2);
4501 %}
4502
4503 // Float reg-reg operation
4504 pipe_class fpu_reg_reg_reg_reg(regD dst, regD src1, regD src2, regD src3)
4505 %{
4506 instruction_count(4);
4507 dst : S4(write);
4508 src1 : S3(read);
4509 src2 : S3(read);
4510 src3 : S3(read);
4511 DECODE : S0(4); // any 3 decoders
4512 FPU : S3(2);
4513 %}
4514
4515 // Float reg-reg operation
4516 pipe_class fpu_reg_mem_reg_reg(regD dst, memory src1, regD src2, regD src3)
4517 %{
4518 instruction_count(4);
4519 dst : S4(write);
4520 src1 : S3(read);
4521 src2 : S3(read);
4522 src3 : S3(read);
4523 DECODE : S1(3); // any 3 decoders
4524 D0 : S0; // Big decoder only
4525 FPU : S3(2);
4526 MEM : S3;
4527 %}
4528
4529 // Float reg-mem operation
4530 pipe_class fpu_reg_mem(regD dst, memory mem)
4531 %{
4532 instruction_count(2);
4533 dst : S5(write);
4534 mem : S3(read);
4535 D0 : S0; // big decoder only
4536 DECODE : S1; // any decoder for FPU POP
4537 FPU : S4;
4538 MEM : S3; // any mem
4539 %}
4540
4541 // Float reg-mem operation
4542 pipe_class fpu_reg_reg_mem(regD dst, regD src1, memory mem)
4543 %{
4544 instruction_count(3);
4545 dst : S5(write);
4546 src1 : S3(read);
4547 mem : S3(read);
4548 D0 : S0; // big decoder only
4549 DECODE : S1(2); // any decoder for FPU POP
4550 FPU : S4;
4551 MEM : S3; // any mem
4552 %}
4553
4554 // Float mem-reg operation
4555 pipe_class fpu_mem_reg(memory mem, regD src)
4556 %{
4557 instruction_count(2);
4558 src : S5(read);
4559 mem : S3(read);
4560 DECODE : S0; // any decoder for FPU PUSH
4561 D0 : S1; // big decoder only
4562 FPU : S4;
4563 MEM : S3; // any mem
4564 %}
4565
4566 pipe_class fpu_mem_reg_reg(memory mem, regD src1, regD src2)
4567 %{
4568 instruction_count(3);
4569 src1 : S3(read);
4570 src2 : S3(read);
4571 mem : S3(read);
4572 DECODE : S0(2); // any decoder for FPU PUSH
4573 D0 : S1; // big decoder only
4574 FPU : S4;
4575 MEM : S3; // any mem
4576 %}
4577
4578 pipe_class fpu_mem_reg_mem(memory mem, regD src1, memory src2)
4579 %{
4580 instruction_count(3);
4581 src1 : S3(read);
4582 src2 : S3(read);
4583 mem : S4(read);
4584 DECODE : S0; // any decoder for FPU PUSH
4585 D0 : S0(2); // big decoder only
4586 FPU : S4;
4587 MEM : S3(2); // any mem
4588 %}
4589
4590 pipe_class fpu_mem_mem(memory dst, memory src1)
4591 %{
4592 instruction_count(2);
4593 src1 : S3(read);
4594 dst : S4(read);
4595 D0 : S0(2); // big decoder only
4596 MEM : S3(2); // any mem
4597 %}
4598
4599 pipe_class fpu_mem_mem_mem(memory dst, memory src1, memory src2)
4600 %{
4601 instruction_count(3);
4602 src1 : S3(read);
4603 src2 : S3(read);
4604 dst : S4(read);
4605 D0 : S0(3); // big decoder only
4606 FPU : S4;
4607 MEM : S3(3); // any mem
4608 %}
4609
4610 pipe_class fpu_mem_reg_con(memory mem, regD src1)
4611 %{
4612 instruction_count(3);
4613 src1 : S4(read);
4614 mem : S4(read);
4615 DECODE : S0; // any decoder for FPU PUSH
4616 D0 : S0(2); // big decoder only
4617 FPU : S4;
4618 MEM : S3(2); // any mem
4619 %}
4620
4621 // Float load constant
4622 pipe_class fpu_reg_con(regD dst)
4623 %{
4624 instruction_count(2);
4625 dst : S5(write);
4626 D0 : S0; // big decoder only for the load
4627 DECODE : S1; // any decoder for FPU POP
4628 FPU : S4;
4629 MEM : S3; // any mem
4630 %}
4631
4632 // Float load constant
4633 pipe_class fpu_reg_reg_con(regD dst, regD src)
4634 %{
4635 instruction_count(3);
4636 dst : S5(write);
4637 src : S3(read);
4638 D0 : S0; // big decoder only for the load
4639 DECODE : S1(2); // any decoder for FPU POP
4640 FPU : S4;
4641 MEM : S3; // any mem
4642 %}
4643
4644 // UnConditional branch
4645 pipe_class pipe_jmp(label labl)
4646 %{
4647 single_instruction;
4648 BR : S3;
4649 %}
4650
4651 // Conditional branch
4652 pipe_class pipe_jcc(cmpOp cmp, rFlagsReg cr, label labl)
4653 %{
4654 single_instruction;
4655 cr : S1(read);
4656 BR : S3;
4657 %}
4658
4659 // Allocation idiom
4660 pipe_class pipe_cmpxchg(rRegP dst, rRegP heap_ptr)
4661 %{
4662 instruction_count(1); force_serialization;
4663 fixed_latency(6);
4664 heap_ptr : S3(read);
4665 DECODE : S0(3);
4666 D0 : S2;
4667 MEM : S3;
4668 ALU : S3(2);
4669 dst : S5(write);
4670 BR : S5;
4671 %}
4672
4673 // Generic big/slow expanded idiom
4674 pipe_class pipe_slow()
4675 %{
4676 instruction_count(10); multiple_bundles; force_serialization;
4677 fixed_latency(100);
4678 D0 : S0(2);
4679 MEM : S3(2);
4680 %}
4681
4682 // The real do-nothing guy
4683 pipe_class empty()
4684 %{
4685 instruction_count(0);
4686 %}
4687
4688 // Define the class for the Nop node
4689 define
4690 %{
4691 MachNop = empty;
4692 %}
4693
4694 %}
4695
4696 //----------INSTRUCTIONS-------------------------------------------------------
4697 //
4698 // match -- States which machine-independent subtree may be replaced
4699 // by this instruction.
4700 // ins_cost -- The estimated cost of this instruction is used by instruction
4701 // selection to identify a minimum cost tree of machine
4702 // instructions that matches a tree of machine-independent
4703 // instructions.
4704 // format -- A string providing the disassembly for this instruction.
4705 // The value of an instruction's operand may be inserted
4706 // by referring to it with a '$' prefix.
4707 // opcode -- Three instruction opcodes may be provided. These are referred
4708 // to within an encode class as $primary, $secondary, and $tertiary
4709 // rrspectively. The primary opcode is commonly used to
4710 // indicate the type of machine instruction, while secondary
4711 // and tertiary are often used for prefix options or addressing
4712 // modes.
4713 // ins_encode -- A list of encode classes with parameters. The encode class
4714 // name must have been defined in an 'enc_class' specification
4715 // in the encode section of the architecture description.
4716
4717
4718 //----------Load/Store/Move Instructions---------------------------------------
4719 //----------Load Instructions--------------------------------------------------
4720
4721 // Load Byte (8 bit signed)
4722 instruct loadB(rRegI dst, memory mem)
4723 %{
4724 match(Set dst (LoadB mem));
4725
4726 ins_cost(125);
4727 format %{ "movsbl $dst, $mem\t# byte" %}
4728
4729 ins_encode %{
4730 __ movsbl($dst$$Register, $mem$$Address);
4731 %}
4732
4733 ins_pipe(ialu_reg_mem);
4734 %}
4735
4736 // Load Byte (8 bit signed) into Long Register
4737 instruct loadB2L(rRegL dst, memory mem)
4738 %{
4739 match(Set dst (ConvI2L (LoadB mem)));
4740
4741 ins_cost(125);
4742 format %{ "movsbq $dst, $mem\t# byte -> long" %}
4743
4744 ins_encode %{
4745 __ movsbq($dst$$Register, $mem$$Address);
4746 %}
4747
4748 ins_pipe(ialu_reg_mem);
4749 %}
4750
4751 // Load Unsigned Byte (8 bit UNsigned)
4752 instruct loadUB(rRegI dst, memory mem)
4753 %{
4754 match(Set dst (LoadUB mem));
4755
4756 ins_cost(125);
4757 format %{ "movzbl $dst, $mem\t# ubyte" %}
4758
4759 ins_encode %{
4760 __ movzbl($dst$$Register, $mem$$Address);
4761 %}
4762
4763 ins_pipe(ialu_reg_mem);
4764 %}
4765
4766 // Load Unsigned Byte (8 bit UNsigned) into Long Register
4767 instruct loadUB2L(rRegL dst, memory mem)
4768 %{
4769 match(Set dst (ConvI2L (LoadUB mem)));
4770
4771 ins_cost(125);
4772 format %{ "movzbq $dst, $mem\t# ubyte -> long" %}
4773
4774 ins_encode %{
4775 __ movzbq($dst$$Register, $mem$$Address);
4776 %}
4777
4778 ins_pipe(ialu_reg_mem);
4779 %}
4780
4781 // Load Unsigned Byte (8 bit UNsigned) with 32-bit mask into Long Register
4782 instruct loadUB2L_immI(rRegL dst, memory mem, immI mask, rFlagsReg cr) %{
4783 match(Set dst (ConvI2L (AndI (LoadUB mem) mask)));
4784 effect(KILL cr);
4785
4786 format %{ "movzbq $dst, $mem\t# ubyte & 32-bit mask -> long\n\t"
4787 "andl $dst, right_n_bits($mask, 8)" %}
4788 ins_encode %{
4789 Register Rdst = $dst$$Register;
4790 __ movzbq(Rdst, $mem$$Address);
4791 __ andl(Rdst, $mask$$constant & right_n_bits(8));
4792 %}
4793 ins_pipe(ialu_reg_mem);
4794 %}
4795
4796 // Load Short (16 bit signed)
4797 instruct loadS(rRegI dst, memory mem)
4798 %{
4799 match(Set dst (LoadS mem));
4800
4801 ins_cost(125);
4802 format %{ "movswl $dst, $mem\t# short" %}
4803
4804 ins_encode %{
4805 __ movswl($dst$$Register, $mem$$Address);
4806 %}
4807
4808 ins_pipe(ialu_reg_mem);
4809 %}
4810
4811 // Load Short (16 bit signed) to Byte (8 bit signed)
4812 instruct loadS2B(rRegI dst, memory mem, immI_24 twentyfour) %{
4813 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour));
4814
4815 ins_cost(125);
4816 format %{ "movsbl $dst, $mem\t# short -> byte" %}
4817 ins_encode %{
4818 __ movsbl($dst$$Register, $mem$$Address);
4819 %}
4820 ins_pipe(ialu_reg_mem);
4821 %}
4822
4823 // Load Short (16 bit signed) into Long Register
4824 instruct loadS2L(rRegL dst, memory mem)
4825 %{
4826 match(Set dst (ConvI2L (LoadS mem)));
4827
4828 ins_cost(125);
4829 format %{ "movswq $dst, $mem\t# short -> long" %}
4830
4831 ins_encode %{
4832 __ movswq($dst$$Register, $mem$$Address);
4833 %}
4834
4835 ins_pipe(ialu_reg_mem);
4836 %}
4837
4838 // Load Unsigned Short/Char (16 bit UNsigned)
4839 instruct loadUS(rRegI dst, memory mem)
4840 %{
4841 match(Set dst (LoadUS mem));
4842
4843 ins_cost(125);
4844 format %{ "movzwl $dst, $mem\t# ushort/char" %}
4845
4846 ins_encode %{
4847 __ movzwl($dst$$Register, $mem$$Address);
4848 %}
4849
4850 ins_pipe(ialu_reg_mem);
4851 %}
4852
4853 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed)
4854 instruct loadUS2B(rRegI dst, memory mem, immI_24 twentyfour) %{
4855 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour));
4856
4857 ins_cost(125);
4858 format %{ "movsbl $dst, $mem\t# ushort -> byte" %}
4859 ins_encode %{
4860 __ movsbl($dst$$Register, $mem$$Address);
4861 %}
4862 ins_pipe(ialu_reg_mem);
4863 %}
4864
4865 // Load Unsigned Short/Char (16 bit UNsigned) into Long Register
4866 instruct loadUS2L(rRegL dst, memory mem)
4867 %{
4868 match(Set dst (ConvI2L (LoadUS mem)));
4869
4870 ins_cost(125);
4871 format %{ "movzwq $dst, $mem\t# ushort/char -> long" %}
4872
4873 ins_encode %{
4874 __ movzwq($dst$$Register, $mem$$Address);
4875 %}
4876
4877 ins_pipe(ialu_reg_mem);
4878 %}
4879
4880 // Load Unsigned Short/Char (16 bit UNsigned) with mask 0xFF into Long Register
4881 instruct loadUS2L_immI_255(rRegL dst, memory mem, immI_255 mask) %{
4882 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
4883
4884 format %{ "movzbq $dst, $mem\t# ushort/char & 0xFF -> long" %}
4885 ins_encode %{
4886 __ movzbq($dst$$Register, $mem$$Address);
4887 %}
4888 ins_pipe(ialu_reg_mem);
4889 %}
4890
4891 // Load Unsigned Short/Char (16 bit UNsigned) with 32-bit mask into Long Register
4892 instruct loadUS2L_immI(rRegL dst, memory mem, immI mask, rFlagsReg cr) %{
4893 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
4894 effect(KILL cr);
4895
4896 format %{ "movzwq $dst, $mem\t# ushort/char & 32-bit mask -> long\n\t"
4897 "andl $dst, right_n_bits($mask, 16)" %}
4898 ins_encode %{
4899 Register Rdst = $dst$$Register;
4900 __ movzwq(Rdst, $mem$$Address);
4901 __ andl(Rdst, $mask$$constant & right_n_bits(16));
4902 %}
4903 ins_pipe(ialu_reg_mem);
4904 %}
4905
4906 // Load Integer
4907 instruct loadI(rRegI dst, memory mem)
4908 %{
4909 match(Set dst (LoadI mem));
4910
4911 ins_cost(125);
4912 format %{ "movl $dst, $mem\t# int" %}
4913
4914 ins_encode %{
4915 __ movl($dst$$Register, $mem$$Address);
4916 %}
4917
4918 ins_pipe(ialu_reg_mem);
4919 %}
4920
4921 // Load Integer (32 bit signed) to Byte (8 bit signed)
4922 instruct loadI2B(rRegI dst, memory mem, immI_24 twentyfour) %{
4923 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour));
4924
4925 ins_cost(125);
4926 format %{ "movsbl $dst, $mem\t# int -> byte" %}
4927 ins_encode %{
4928 __ movsbl($dst$$Register, $mem$$Address);
4929 %}
4930 ins_pipe(ialu_reg_mem);
4931 %}
4932
4933 // Load Integer (32 bit signed) to Unsigned Byte (8 bit UNsigned)
4934 instruct loadI2UB(rRegI dst, memory mem, immI_255 mask) %{
4935 match(Set dst (AndI (LoadI mem) mask));
4936
4937 ins_cost(125);
4938 format %{ "movzbl $dst, $mem\t# int -> ubyte" %}
4939 ins_encode %{
4940 __ movzbl($dst$$Register, $mem$$Address);
4941 %}
4942 ins_pipe(ialu_reg_mem);
4943 %}
4944
4945 // Load Integer (32 bit signed) to Short (16 bit signed)
4946 instruct loadI2S(rRegI dst, memory mem, immI_16 sixteen) %{
4947 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen));
4948
4949 ins_cost(125);
4950 format %{ "movswl $dst, $mem\t# int -> short" %}
4951 ins_encode %{
4952 __ movswl($dst$$Register, $mem$$Address);
4953 %}
4954 ins_pipe(ialu_reg_mem);
4955 %}
4956
4957 // Load Integer (32 bit signed) to Unsigned Short/Char (16 bit UNsigned)
4958 instruct loadI2US(rRegI dst, memory mem, immI_65535 mask) %{
4959 match(Set dst (AndI (LoadI mem) mask));
4960
4961 ins_cost(125);
4962 format %{ "movzwl $dst, $mem\t# int -> ushort/char" %}
4963 ins_encode %{
4964 __ movzwl($dst$$Register, $mem$$Address);
4965 %}
4966 ins_pipe(ialu_reg_mem);
4967 %}
4968
4969 // Load Integer into Long Register
4970 instruct loadI2L(rRegL dst, memory mem)
4971 %{
4972 match(Set dst (ConvI2L (LoadI mem)));
4973
4974 ins_cost(125);
4975 format %{ "movslq $dst, $mem\t# int -> long" %}
4976
4977 ins_encode %{
4978 __ movslq($dst$$Register, $mem$$Address);
4979 %}
4980
4981 ins_pipe(ialu_reg_mem);
4982 %}
4983
4984 // Load Integer with mask 0xFF into Long Register
4985 instruct loadI2L_immI_255(rRegL dst, memory mem, immI_255 mask) %{
4986 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
4987
4988 format %{ "movzbq $dst, $mem\t# int & 0xFF -> long" %}
4989 ins_encode %{
4990 __ movzbq($dst$$Register, $mem$$Address);
4991 %}
4992 ins_pipe(ialu_reg_mem);
4993 %}
4994
4995 // Load Integer with mask 0xFFFF into Long Register
4996 instruct loadI2L_immI_65535(rRegL dst, memory mem, immI_65535 mask) %{
4997 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
4998
4999 format %{ "movzwq $dst, $mem\t# int & 0xFFFF -> long" %}
5000 ins_encode %{
5001 __ movzwq($dst$$Register, $mem$$Address);
5002 %}
5003 ins_pipe(ialu_reg_mem);
5004 %}
5005
5006 // Load Integer with a 31-bit mask into Long Register
5007 instruct loadI2L_immU31(rRegL dst, memory mem, immU31 mask, rFlagsReg cr) %{
5008 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5009 effect(KILL cr);
5010
5011 format %{ "movl $dst, $mem\t# int & 31-bit mask -> long\n\t"
5012 "andl $dst, $mask" %}
5013 ins_encode %{
5014 Register Rdst = $dst$$Register;
5015 __ movl(Rdst, $mem$$Address);
5016 __ andl(Rdst, $mask$$constant);
5017 %}
5018 ins_pipe(ialu_reg_mem);
5019 %}
5020
5021 // Load Unsigned Integer into Long Register
5022 instruct loadUI2L(rRegL dst, memory mem, immL_32bits mask)
5023 %{
5024 match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
5025
5026 ins_cost(125);
5027 format %{ "movl $dst, $mem\t# uint -> long" %}
5028
5029 ins_encode %{
5030 __ movl($dst$$Register, $mem$$Address);
5031 %}
5032
5033 ins_pipe(ialu_reg_mem);
5034 %}
5035
5036 // Load Long
5037 instruct loadL(rRegL dst, memory mem)
5038 %{
5039 match(Set dst (LoadL mem));
5040
5041 ins_cost(125);
5042 format %{ "movq $dst, $mem\t# long" %}
5043
5044 ins_encode %{
5045 __ movq($dst$$Register, $mem$$Address);
5046 %}
5047
5048 ins_pipe(ialu_reg_mem); // XXX
5049 %}
5050
5051 // Load Range
5052 instruct loadRange(rRegI dst, memory mem)
5053 %{
5054 match(Set dst (LoadRange mem));
5055
5056 ins_cost(125); // XXX
5057 format %{ "movl $dst, $mem\t# range" %}
5058 opcode(0x8B);
5059 ins_encode(REX_reg_mem(dst, mem), OpcP, reg_mem(dst, mem));
5060 ins_pipe(ialu_reg_mem);
5061 %}
5062
5063 // Load Pointer
5064 instruct loadP(rRegP dst, memory mem)
5065 %{
5066 match(Set dst (LoadP mem));
5067
5068 ins_cost(125); // XXX
5069 format %{ "movq $dst, $mem\t# ptr" %}
5070 opcode(0x8B);
5071 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5072 ins_pipe(ialu_reg_mem); // XXX
5073 %}
5074
5075 // Load Compressed Pointer
5076 instruct loadN(rRegN dst, memory mem)
5077 %{
5078 match(Set dst (LoadN mem));
5079
5080 ins_cost(125); // XXX
5081 format %{ "movl $dst, $mem\t# compressed ptr" %}
5082 ins_encode %{
5083 __ movl($dst$$Register, $mem$$Address);
5084 %}
5085 ins_pipe(ialu_reg_mem); // XXX
5086 %}
5087
5088
5089 // Load Klass Pointer
5090 instruct loadKlass(rRegP dst, memory mem)
5091 %{
5092 match(Set dst (LoadKlass mem));
5093
5094 ins_cost(125); // XXX
5095 format %{ "movq $dst, $mem\t# class" %}
5096 opcode(0x8B);
5097 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5098 ins_pipe(ialu_reg_mem); // XXX
5099 %}
5100
5101 // Load narrow Klass Pointer
5102 instruct loadNKlass(rRegN dst, memory mem)
5103 %{
5104 match(Set dst (LoadNKlass mem));
5105
5106 ins_cost(125); // XXX
5107 format %{ "movl $dst, $mem\t# compressed klass ptr" %}
5108 ins_encode %{
5109 __ movl($dst$$Register, $mem$$Address);
5110 %}
5111 ins_pipe(ialu_reg_mem); // XXX
5112 %}
5113
5114 // Load Float
5115 instruct loadF(regF dst, memory mem)
5116 %{
5117 match(Set dst (LoadF mem));
5118
5119 ins_cost(145); // XXX
5120 format %{ "movss $dst, $mem\t# float" %}
5121 ins_encode %{
5122 __ movflt($dst$$XMMRegister, $mem$$Address);
5123 %}
5124 ins_pipe(pipe_slow); // XXX
5125 %}
5126
5127 // Load Double
5128 instruct loadD_partial(regD dst, memory mem)
5129 %{
5130 predicate(!UseXmmLoadAndClearUpper);
5131 match(Set dst (LoadD mem));
5132
5133 ins_cost(145); // XXX
5134 format %{ "movlpd $dst, $mem\t# double" %}
5135 ins_encode %{
5136 __ movdbl($dst$$XMMRegister, $mem$$Address);
5137 %}
5138 ins_pipe(pipe_slow); // XXX
5139 %}
5140
5141 instruct loadD(regD dst, memory mem)
5142 %{
5143 predicate(UseXmmLoadAndClearUpper);
5144 match(Set dst (LoadD mem));
5145
5146 ins_cost(145); // XXX
5147 format %{ "movsd $dst, $mem\t# double" %}
5148 ins_encode %{
5149 __ movdbl($dst$$XMMRegister, $mem$$Address);
5150 %}
5151 ins_pipe(pipe_slow); // XXX
5152 %}
5153
5154 // Load Effective Address
5155 instruct leaP8(rRegP dst, indOffset8 mem)
5156 %{
5157 match(Set dst mem);
5158
5159 ins_cost(110); // XXX
5160 format %{ "leaq $dst, $mem\t# ptr 8" %}
5161 opcode(0x8D);
5162 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5163 ins_pipe(ialu_reg_reg_fat);
5164 %}
5165
5166 instruct leaP32(rRegP dst, indOffset32 mem)
5167 %{
5168 match(Set dst mem);
5169
5170 ins_cost(110);
5171 format %{ "leaq $dst, $mem\t# ptr 32" %}
5172 opcode(0x8D);
5173 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5174 ins_pipe(ialu_reg_reg_fat);
5175 %}
5176
5177 // instruct leaPIdx(rRegP dst, indIndex mem)
5178 // %{
5179 // match(Set dst mem);
5180
5181 // ins_cost(110);
5182 // format %{ "leaq $dst, $mem\t# ptr idx" %}
5183 // opcode(0x8D);
5184 // ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5185 // ins_pipe(ialu_reg_reg_fat);
5186 // %}
5187
5188 instruct leaPIdxOff(rRegP dst, indIndexOffset mem)
5189 %{
5190 match(Set dst mem);
5191
5192 ins_cost(110);
5193 format %{ "leaq $dst, $mem\t# ptr idxoff" %}
5194 opcode(0x8D);
5195 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5196 ins_pipe(ialu_reg_reg_fat);
5197 %}
5198
5199 instruct leaPIdxScale(rRegP dst, indIndexScale mem)
5200 %{
5201 match(Set dst mem);
5202
5203 ins_cost(110);
5204 format %{ "leaq $dst, $mem\t# ptr idxscale" %}
5205 opcode(0x8D);
5206 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5207 ins_pipe(ialu_reg_reg_fat);
5208 %}
5209
5210 instruct leaPPosIdxScale(rRegP dst, indPosIndexScale mem)
5211 %{
5212 match(Set dst mem);
5213
5214 ins_cost(110);
5215 format %{ "leaq $dst, $mem\t# ptr idxscale" %}
5216 opcode(0x8D);
5217 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5218 ins_pipe(ialu_reg_reg_fat);
5219 %}
5220
5221 instruct leaPIdxScaleOff(rRegP dst, indIndexScaleOffset mem)
5222 %{
5223 match(Set dst mem);
5224
5225 ins_cost(110);
5226 format %{ "leaq $dst, $mem\t# ptr idxscaleoff" %}
5227 opcode(0x8D);
5228 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5229 ins_pipe(ialu_reg_reg_fat);
5230 %}
5231
5232 instruct leaPPosIdxOff(rRegP dst, indPosIndexOffset mem)
5233 %{
5234 match(Set dst mem);
5235
5236 ins_cost(110);
5237 format %{ "leaq $dst, $mem\t# ptr posidxoff" %}
5238 opcode(0x8D);
5239 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5240 ins_pipe(ialu_reg_reg_fat);
5241 %}
5242
5243 instruct leaPPosIdxScaleOff(rRegP dst, indPosIndexScaleOffset mem)
5244 %{
5245 match(Set dst mem);
5246
5247 ins_cost(110);
5248 format %{ "leaq $dst, $mem\t# ptr posidxscaleoff" %}
5249 opcode(0x8D);
5250 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5251 ins_pipe(ialu_reg_reg_fat);
5252 %}
5253
5254 // Load Effective Address which uses Narrow (32-bits) oop
5255 instruct leaPCompressedOopOffset(rRegP dst, indCompressedOopOffset mem)
5256 %{
5257 predicate(UseCompressedOops && (Universe::narrow_oop_shift() != 0));
5258 match(Set dst mem);
5259
5260 ins_cost(110);
5261 format %{ "leaq $dst, $mem\t# ptr compressedoopoff32" %}
5262 opcode(0x8D);
5263 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5264 ins_pipe(ialu_reg_reg_fat);
5265 %}
5266
5267 instruct leaP8Narrow(rRegP dst, indOffset8Narrow mem)
5268 %{
5269 predicate(Universe::narrow_oop_shift() == 0);
5270 match(Set dst mem);
5271
5272 ins_cost(110); // XXX
5273 format %{ "leaq $dst, $mem\t# ptr off8narrow" %}
5274 opcode(0x8D);
5275 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5276 ins_pipe(ialu_reg_reg_fat);
5277 %}
5278
5279 instruct leaP32Narrow(rRegP dst, indOffset32Narrow mem)
5280 %{
5281 predicate(Universe::narrow_oop_shift() == 0);
5282 match(Set dst mem);
5283
5284 ins_cost(110);
5285 format %{ "leaq $dst, $mem\t# ptr off32narrow" %}
5286 opcode(0x8D);
5287 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5288 ins_pipe(ialu_reg_reg_fat);
5289 %}
5290
5291 instruct leaPIdxOffNarrow(rRegP dst, indIndexOffsetNarrow mem)
5292 %{
5293 predicate(Universe::narrow_oop_shift() == 0);
5294 match(Set dst mem);
5295
5296 ins_cost(110);
5297 format %{ "leaq $dst, $mem\t# ptr idxoffnarrow" %}
5298 opcode(0x8D);
5299 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5300 ins_pipe(ialu_reg_reg_fat);
5301 %}
5302
5303 instruct leaPIdxScaleNarrow(rRegP dst, indIndexScaleNarrow mem)
5304 %{
5305 predicate(Universe::narrow_oop_shift() == 0);
5306 match(Set dst mem);
5307
5308 ins_cost(110);
5309 format %{ "leaq $dst, $mem\t# ptr idxscalenarrow" %}
5310 opcode(0x8D);
5311 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5312 ins_pipe(ialu_reg_reg_fat);
5313 %}
5314
5315 instruct leaPIdxScaleOffNarrow(rRegP dst, indIndexScaleOffsetNarrow mem)
5316 %{
5317 predicate(Universe::narrow_oop_shift() == 0);
5318 match(Set dst mem);
5319
5320 ins_cost(110);
5321 format %{ "leaq $dst, $mem\t# ptr idxscaleoffnarrow" %}
5322 opcode(0x8D);
5323 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5324 ins_pipe(ialu_reg_reg_fat);
5325 %}
5326
5327 instruct leaPPosIdxOffNarrow(rRegP dst, indPosIndexOffsetNarrow mem)
5328 %{
5329 predicate(Universe::narrow_oop_shift() == 0);
5330 match(Set dst mem);
5331
5332 ins_cost(110);
5333 format %{ "leaq $dst, $mem\t# ptr posidxoffnarrow" %}
5334 opcode(0x8D);
5335 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5336 ins_pipe(ialu_reg_reg_fat);
5337 %}
5338
5339 instruct leaPPosIdxScaleOffNarrow(rRegP dst, indPosIndexScaleOffsetNarrow mem)
5340 %{
5341 predicate(Universe::narrow_oop_shift() == 0);
5342 match(Set dst mem);
5343
5344 ins_cost(110);
5345 format %{ "leaq $dst, $mem\t# ptr posidxscaleoffnarrow" %}
5346 opcode(0x8D);
5347 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5348 ins_pipe(ialu_reg_reg_fat);
5349 %}
5350
5351 instruct loadConI(rRegI dst, immI src)
5352 %{
5353 match(Set dst src);
5354
5355 format %{ "movl $dst, $src\t# int" %}
5356 ins_encode(load_immI(dst, src));
5357 ins_pipe(ialu_reg_fat); // XXX
5358 %}
5359
5360 instruct loadConI0(rRegI dst, immI0 src, rFlagsReg cr)
5361 %{
5362 match(Set dst src);
5363 effect(KILL cr);
5364
5365 ins_cost(50);
5366 format %{ "xorl $dst, $dst\t# int" %}
5367 opcode(0x33); /* + rd */
5368 ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst));
5369 ins_pipe(ialu_reg);
5370 %}
5371
5372 instruct loadConL(rRegL dst, immL src)
5373 %{
5374 match(Set dst src);
5375
5376 ins_cost(150);
5377 format %{ "movq $dst, $src\t# long" %}
5378 ins_encode(load_immL(dst, src));
5379 ins_pipe(ialu_reg);
5380 %}
5381
5382 instruct loadConL0(rRegL dst, immL0 src, rFlagsReg cr)
5383 %{
5384 match(Set dst src);
5385 effect(KILL cr);
5386
5387 ins_cost(50);
5388 format %{ "xorl $dst, $dst\t# long" %}
5389 opcode(0x33); /* + rd */
5390 ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst));
5391 ins_pipe(ialu_reg); // XXX
5392 %}
5393
5394 instruct loadConUL32(rRegL dst, immUL32 src)
5395 %{
5396 match(Set dst src);
5397
5398 ins_cost(60);
5399 format %{ "movl $dst, $src\t# long (unsigned 32-bit)" %}
5400 ins_encode(load_immUL32(dst, src));
5401 ins_pipe(ialu_reg);
5402 %}
5403
5404 instruct loadConL32(rRegL dst, immL32 src)
5405 %{
5406 match(Set dst src);
5407
5408 ins_cost(70);
5409 format %{ "movq $dst, $src\t# long (32-bit)" %}
5410 ins_encode(load_immL32(dst, src));
5411 ins_pipe(ialu_reg);
5412 %}
5413
5414 instruct loadConP(rRegP dst, immP con) %{
5415 match(Set dst con);
5416
5417 format %{ "movq $dst, $con\t# ptr" %}
5418 ins_encode(load_immP(dst, con));
5419 ins_pipe(ialu_reg_fat); // XXX
5420 %}
5421
5422 instruct loadConP0(rRegP dst, immP0 src, rFlagsReg cr)
5423 %{
5424 match(Set dst src);
5425 effect(KILL cr);
5426
5427 ins_cost(50);
5428 format %{ "xorl $dst, $dst\t# ptr" %}
5429 opcode(0x33); /* + rd */
5430 ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst));
5431 ins_pipe(ialu_reg);
5432 %}
5433
5434 instruct loadConP31(rRegP dst, immP31 src, rFlagsReg cr)
5435 %{
5436 match(Set dst src);
5437 effect(KILL cr);
5438
5439 ins_cost(60);
5440 format %{ "movl $dst, $src\t# ptr (positive 32-bit)" %}
5441 ins_encode(load_immP31(dst, src));
5442 ins_pipe(ialu_reg);
5443 %}
5444
5445 instruct loadConF(regF dst, immF con) %{
5446 match(Set dst con);
5447 ins_cost(125);
5448 format %{ "movss $dst, [$constantaddress]\t# load from constant table: float=$con" %}
5449 ins_encode %{
5450 __ movflt($dst$$XMMRegister, $constantaddress($con));
5451 %}
5452 ins_pipe(pipe_slow);
5453 %}
5454
5455 instruct loadConN0(rRegN dst, immN0 src, rFlagsReg cr) %{
5456 match(Set dst src);
5457 effect(KILL cr);
5458 format %{ "xorq $dst, $src\t# compressed NULL ptr" %}
5459 ins_encode %{
5460 __ xorq($dst$$Register, $dst$$Register);
5461 %}
5462 ins_pipe(ialu_reg);
5463 %}
5464
5465 instruct loadConN(rRegN dst, immN src) %{
5466 match(Set dst src);
5467
5468 ins_cost(125);
5469 format %{ "movl $dst, $src\t# compressed ptr" %}
5470 ins_encode %{
5471 address con = (address)$src$$constant;
5472 if (con == NULL) {
5473 ShouldNotReachHere();
5474 } else {
5475 __ set_narrow_oop($dst$$Register, (jobject)$src$$constant);
5476 }
5477 %}
5478 ins_pipe(ialu_reg_fat); // XXX
5479 %}
5480
5481 instruct loadConNKlass(rRegN dst, immNKlass src) %{
5482 match(Set dst src);
5483
5484 ins_cost(125);
5485 format %{ "movl $dst, $src\t# compressed klass ptr" %}
5486 ins_encode %{
5487 address con = (address)$src$$constant;
5488 if (con == NULL) {
5489 ShouldNotReachHere();
5490 } else {
5491 __ set_narrow_klass($dst$$Register, (Klass*)$src$$constant);
5492 }
5493 %}
5494 ins_pipe(ialu_reg_fat); // XXX
5495 %}
5496
5497 instruct loadConF0(regF dst, immF0 src)
5498 %{
5499 match(Set dst src);
5500 ins_cost(100);
5501
5502 format %{ "xorps $dst, $dst\t# float 0.0" %}
5503 ins_encode %{
5504 __ xorps($dst$$XMMRegister, $dst$$XMMRegister);
5505 %}
5506 ins_pipe(pipe_slow);
5507 %}
5508
5509 // Use the same format since predicate() can not be used here.
5510 instruct loadConD(regD dst, immD con) %{
5511 match(Set dst con);
5512 ins_cost(125);
5513 format %{ "movsd $dst, [$constantaddress]\t# load from constant table: double=$con" %}
5514 ins_encode %{
5515 __ movdbl($dst$$XMMRegister, $constantaddress($con));
5516 %}
5517 ins_pipe(pipe_slow);
5518 %}
5519
5520 instruct loadConD0(regD dst, immD0 src)
5521 %{
5522 match(Set dst src);
5523 ins_cost(100);
5524
5525 format %{ "xorpd $dst, $dst\t# double 0.0" %}
5526 ins_encode %{
5527 __ xorpd ($dst$$XMMRegister, $dst$$XMMRegister);
5528 %}
5529 ins_pipe(pipe_slow);
5530 %}
5531
5532 instruct loadSSI(rRegI dst, stackSlotI src)
5533 %{
5534 match(Set dst src);
5535
5536 ins_cost(125);
5537 format %{ "movl $dst, $src\t# int stk" %}
5538 opcode(0x8B);
5539 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
5540 ins_pipe(ialu_reg_mem);
5541 %}
5542
5543 instruct loadSSL(rRegL dst, stackSlotL src)
5544 %{
5545 match(Set dst src);
5546
5547 ins_cost(125);
5548 format %{ "movq $dst, $src\t# long stk" %}
5549 opcode(0x8B);
5550 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
5551 ins_pipe(ialu_reg_mem);
5552 %}
5553
5554 instruct loadSSP(rRegP dst, stackSlotP src)
5555 %{
5556 match(Set dst src);
5557
5558 ins_cost(125);
5559 format %{ "movq $dst, $src\t# ptr stk" %}
5560 opcode(0x8B);
5561 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
5562 ins_pipe(ialu_reg_mem);
5563 %}
5564
5565 instruct loadSSF(regF dst, stackSlotF src)
5566 %{
5567 match(Set dst src);
5568
5569 ins_cost(125);
5570 format %{ "movss $dst, $src\t# float stk" %}
5571 ins_encode %{
5572 __ movflt($dst$$XMMRegister, Address(rsp, $src$$disp));
5573 %}
5574 ins_pipe(pipe_slow); // XXX
5575 %}
5576
5577 // Use the same format since predicate() can not be used here.
5578 instruct loadSSD(regD dst, stackSlotD src)
5579 %{
5580 match(Set dst src);
5581
5582 ins_cost(125);
5583 format %{ "movsd $dst, $src\t# double stk" %}
5584 ins_encode %{
5585 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
5586 %}
5587 ins_pipe(pipe_slow); // XXX
5588 %}
5589
5590 // Prefetch instructions for allocation.
5591 // Must be safe to execute with invalid address (cannot fault).
5592
5593 instruct prefetchAlloc( memory mem ) %{
5594 predicate(AllocatePrefetchInstr==3);
5595 match(PrefetchAllocation mem);
5596 ins_cost(125);
5597
5598 format %{ "PREFETCHW $mem\t# Prefetch allocation into level 1 cache and mark modified" %}
5599 ins_encode %{
5600 __ prefetchw($mem$$Address);
5601 %}
5602 ins_pipe(ialu_mem);
5603 %}
5604
5605 instruct prefetchAllocNTA( memory mem ) %{
5606 predicate(AllocatePrefetchInstr==0);
5607 match(PrefetchAllocation mem);
5608 ins_cost(125);
5609
5610 format %{ "PREFETCHNTA $mem\t# Prefetch allocation to non-temporal cache for write" %}
5611 ins_encode %{
5612 __ prefetchnta($mem$$Address);
5613 %}
5614 ins_pipe(ialu_mem);
5615 %}
5616
5617 instruct prefetchAllocT0( memory mem ) %{
5618 predicate(AllocatePrefetchInstr==1);
5619 match(PrefetchAllocation mem);
5620 ins_cost(125);
5621
5622 format %{ "PREFETCHT0 $mem\t# Prefetch allocation to level 1 and 2 caches for write" %}
5623 ins_encode %{
5624 __ prefetcht0($mem$$Address);
5625 %}
5626 ins_pipe(ialu_mem);
5627 %}
5628
5629 instruct prefetchAllocT2( memory mem ) %{
5630 predicate(AllocatePrefetchInstr==2);
5631 match(PrefetchAllocation mem);
5632 ins_cost(125);
5633
5634 format %{ "PREFETCHT2 $mem\t# Prefetch allocation to level 2 cache for write" %}
5635 ins_encode %{
5636 __ prefetcht2($mem$$Address);
5637 %}
5638 ins_pipe(ialu_mem);
5639 %}
5640
5641 //----------Store Instructions-------------------------------------------------
5642
5643 // Store Byte
5644 instruct storeB(memory mem, rRegI src)
5645 %{
5646 match(Set mem (StoreB mem src));
5647
5648 ins_cost(125); // XXX
5649 format %{ "movb $mem, $src\t# byte" %}
5650 opcode(0x88);
5651 ins_encode(REX_breg_mem(src, mem), OpcP, reg_mem(src, mem));
5652 ins_pipe(ialu_mem_reg);
5653 %}
5654
5655 // Store Char/Short
5656 instruct storeC(memory mem, rRegI src)
5657 %{
5658 match(Set mem (StoreC mem src));
5659
5660 ins_cost(125); // XXX
5661 format %{ "movw $mem, $src\t# char/short" %}
5662 opcode(0x89);
5663 ins_encode(SizePrefix, REX_reg_mem(src, mem), OpcP, reg_mem(src, mem));
5664 ins_pipe(ialu_mem_reg);
5665 %}
5666
5667 // Store Integer
5668 instruct storeI(memory mem, rRegI src)
5669 %{
5670 match(Set mem (StoreI mem src));
5671
5672 ins_cost(125); // XXX
5673 format %{ "movl $mem, $src\t# int" %}
5674 opcode(0x89);
5675 ins_encode(REX_reg_mem(src, mem), OpcP, reg_mem(src, mem));
5676 ins_pipe(ialu_mem_reg);
5677 %}
5678
5679 // Store Long
5680 instruct storeL(memory mem, rRegL src)
5681 %{
5682 match(Set mem (StoreL mem src));
5683
5684 ins_cost(125); // XXX
5685 format %{ "movq $mem, $src\t# long" %}
5686 opcode(0x89);
5687 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem));
5688 ins_pipe(ialu_mem_reg); // XXX
5689 %}
5690
5691 // Store Pointer
5692 instruct storeP(memory mem, any_RegP src)
5693 %{
5694 match(Set mem (StoreP mem src));
5695
5696 ins_cost(125); // XXX
5697 format %{ "movq $mem, $src\t# ptr" %}
5698 opcode(0x89);
5699 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem));
5700 ins_pipe(ialu_mem_reg);
5701 %}
5702
5703 instruct storeImmP0(memory mem, immP0 zero)
5704 %{
5705 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
5706 match(Set mem (StoreP mem zero));
5707
5708 ins_cost(125); // XXX
5709 format %{ "movq $mem, R12\t# ptr (R12_heapbase==0)" %}
5710 ins_encode %{
5711 __ movq($mem$$Address, r12);
5712 %}
5713 ins_pipe(ialu_mem_reg);
5714 %}
5715
5716 // Store NULL Pointer, mark word, or other simple pointer constant.
5717 instruct storeImmP(memory mem, immP31 src)
5718 %{
5719 match(Set mem (StoreP mem src));
5720
5721 ins_cost(150); // XXX
5722 format %{ "movq $mem, $src\t# ptr" %}
5723 opcode(0xC7); /* C7 /0 */
5724 ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src));
5725 ins_pipe(ialu_mem_imm);
5726 %}
5727
5728 // Store Compressed Pointer
5729 instruct storeN(memory mem, rRegN src)
5730 %{
5731 match(Set mem (StoreN mem src));
5732
5733 ins_cost(125); // XXX
5734 format %{ "movl $mem, $src\t# compressed ptr" %}
5735 ins_encode %{
5736 __ movl($mem$$Address, $src$$Register);
5737 %}
5738 ins_pipe(ialu_mem_reg);
5739 %}
5740
5741 instruct storeNKlass(memory mem, rRegN src)
5742 %{
5743 match(Set mem (StoreNKlass mem src));
5744
5745 ins_cost(125); // XXX
5746 format %{ "movl $mem, $src\t# compressed klass ptr" %}
5747 ins_encode %{
5748 __ movl($mem$$Address, $src$$Register);
5749 %}
5750 ins_pipe(ialu_mem_reg);
5751 %}
5752
5753 instruct storeImmN0(memory mem, immN0 zero)
5754 %{
5755 predicate(Universe::narrow_oop_base() == NULL && Universe::narrow_klass_base() == NULL);
5756 match(Set mem (StoreN mem zero));
5757
5758 ins_cost(125); // XXX
5759 format %{ "movl $mem, R12\t# compressed ptr (R12_heapbase==0)" %}
5760 ins_encode %{
5761 __ movl($mem$$Address, r12);
5762 %}
5763 ins_pipe(ialu_mem_reg);
5764 %}
5765
5766 instruct storeImmN(memory mem, immN src)
5767 %{
5768 match(Set mem (StoreN mem src));
5769
5770 ins_cost(150); // XXX
5771 format %{ "movl $mem, $src\t# compressed ptr" %}
5772 ins_encode %{
5773 address con = (address)$src$$constant;
5774 if (con == NULL) {
5775 __ movl($mem$$Address, (int32_t)0);
5776 } else {
5777 __ set_narrow_oop($mem$$Address, (jobject)$src$$constant);
5778 }
5779 %}
5780 ins_pipe(ialu_mem_imm);
5781 %}
5782
5783 instruct storeImmNKlass(memory mem, immNKlass src)
5784 %{
5785 match(Set mem (StoreNKlass mem src));
5786
5787 ins_cost(150); // XXX
5788 format %{ "movl $mem, $src\t# compressed klass ptr" %}
5789 ins_encode %{
5790 __ set_narrow_klass($mem$$Address, (Klass*)$src$$constant);
5791 %}
5792 ins_pipe(ialu_mem_imm);
5793 %}
5794
5795 // Store Integer Immediate
5796 instruct storeImmI0(memory mem, immI0 zero)
5797 %{
5798 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
5799 match(Set mem (StoreI mem zero));
5800
5801 ins_cost(125); // XXX
5802 format %{ "movl $mem, R12\t# int (R12_heapbase==0)" %}
5803 ins_encode %{
5804 __ movl($mem$$Address, r12);
5805 %}
5806 ins_pipe(ialu_mem_reg);
5807 %}
5808
5809 instruct storeImmI(memory mem, immI src)
5810 %{
5811 match(Set mem (StoreI mem src));
5812
5813 ins_cost(150);
5814 format %{ "movl $mem, $src\t# int" %}
5815 opcode(0xC7); /* C7 /0 */
5816 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src));
5817 ins_pipe(ialu_mem_imm);
5818 %}
5819
5820 // Store Long Immediate
5821 instruct storeImmL0(memory mem, immL0 zero)
5822 %{
5823 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
5824 match(Set mem (StoreL mem zero));
5825
5826 ins_cost(125); // XXX
5827 format %{ "movq $mem, R12\t# long (R12_heapbase==0)" %}
5828 ins_encode %{
5829 __ movq($mem$$Address, r12);
5830 %}
5831 ins_pipe(ialu_mem_reg);
5832 %}
5833
5834 instruct storeImmL(memory mem, immL32 src)
5835 %{
5836 match(Set mem (StoreL mem src));
5837
5838 ins_cost(150);
5839 format %{ "movq $mem, $src\t# long" %}
5840 opcode(0xC7); /* C7 /0 */
5841 ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src));
5842 ins_pipe(ialu_mem_imm);
5843 %}
5844
5845 // Store Short/Char Immediate
5846 instruct storeImmC0(memory mem, immI0 zero)
5847 %{
5848 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
5849 match(Set mem (StoreC mem zero));
5850
5851 ins_cost(125); // XXX
5852 format %{ "movw $mem, R12\t# short/char (R12_heapbase==0)" %}
5853 ins_encode %{
5854 __ movw($mem$$Address, r12);
5855 %}
5856 ins_pipe(ialu_mem_reg);
5857 %}
5858
5859 instruct storeImmI16(memory mem, immI16 src)
5860 %{
5861 predicate(UseStoreImmI16);
5862 match(Set mem (StoreC mem src));
5863
5864 ins_cost(150);
5865 format %{ "movw $mem, $src\t# short/char" %}
5866 opcode(0xC7); /* C7 /0 Same as 32 store immediate with prefix */
5867 ins_encode(SizePrefix, REX_mem(mem), OpcP, RM_opc_mem(0x00, mem),Con16(src));
5868 ins_pipe(ialu_mem_imm);
5869 %}
5870
5871 // Store Byte Immediate
5872 instruct storeImmB0(memory mem, immI0 zero)
5873 %{
5874 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
5875 match(Set mem (StoreB mem zero));
5876
5877 ins_cost(125); // XXX
5878 format %{ "movb $mem, R12\t# short/char (R12_heapbase==0)" %}
5879 ins_encode %{
5880 __ movb($mem$$Address, r12);
5881 %}
5882 ins_pipe(ialu_mem_reg);
5883 %}
5884
5885 instruct storeImmB(memory mem, immI8 src)
5886 %{
5887 match(Set mem (StoreB mem src));
5888
5889 ins_cost(150); // XXX
5890 format %{ "movb $mem, $src\t# byte" %}
5891 opcode(0xC6); /* C6 /0 */
5892 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con8or32(src));
5893 ins_pipe(ialu_mem_imm);
5894 %}
5895
5896 // Store CMS card-mark Immediate
5897 instruct storeImmCM0_reg(memory mem, immI0 zero)
5898 %{
5899 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
5900 match(Set mem (StoreCM mem zero));
5901
5902 ins_cost(125); // XXX
5903 format %{ "movb $mem, R12\t# CMS card-mark byte 0 (R12_heapbase==0)" %}
5904 ins_encode %{
5905 __ movb($mem$$Address, r12);
5906 %}
5907 ins_pipe(ialu_mem_reg);
5908 %}
5909
5910 instruct storeImmCM0(memory mem, immI0 src)
5911 %{
5912 match(Set mem (StoreCM mem src));
5913
5914 ins_cost(150); // XXX
5915 format %{ "movb $mem, $src\t# CMS card-mark byte 0" %}
5916 opcode(0xC6); /* C6 /0 */
5917 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con8or32(src));
5918 ins_pipe(ialu_mem_imm);
5919 %}
5920
5921 // Store Float
5922 instruct storeF(memory mem, regF src)
5923 %{
5924 match(Set mem (StoreF mem src));
5925
5926 ins_cost(95); // XXX
5927 format %{ "movss $mem, $src\t# float" %}
5928 ins_encode %{
5929 __ movflt($mem$$Address, $src$$XMMRegister);
5930 %}
5931 ins_pipe(pipe_slow); // XXX
5932 %}
5933
5934 // Store immediate Float value (it is faster than store from XMM register)
5935 instruct storeF0(memory mem, immF0 zero)
5936 %{
5937 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
5938 match(Set mem (StoreF mem zero));
5939
5940 ins_cost(25); // XXX
5941 format %{ "movl $mem, R12\t# float 0. (R12_heapbase==0)" %}
5942 ins_encode %{
5943 __ movl($mem$$Address, r12);
5944 %}
5945 ins_pipe(ialu_mem_reg);
5946 %}
5947
5948 instruct storeF_imm(memory mem, immF src)
5949 %{
5950 match(Set mem (StoreF mem src));
5951
5952 ins_cost(50);
5953 format %{ "movl $mem, $src\t# float" %}
5954 opcode(0xC7); /* C7 /0 */
5955 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con32F_as_bits(src));
5956 ins_pipe(ialu_mem_imm);
5957 %}
5958
5959 // Store Double
5960 instruct storeD(memory mem, regD src)
5961 %{
5962 match(Set mem (StoreD mem src));
5963
5964 ins_cost(95); // XXX
5965 format %{ "movsd $mem, $src\t# double" %}
5966 ins_encode %{
5967 __ movdbl($mem$$Address, $src$$XMMRegister);
5968 %}
5969 ins_pipe(pipe_slow); // XXX
5970 %}
5971
5972 // Store immediate double 0.0 (it is faster than store from XMM register)
5973 instruct storeD0_imm(memory mem, immD0 src)
5974 %{
5975 predicate(!UseCompressedOops || (Universe::narrow_oop_base() != NULL));
5976 match(Set mem (StoreD mem src));
5977
5978 ins_cost(50);
5979 format %{ "movq $mem, $src\t# double 0." %}
5980 opcode(0xC7); /* C7 /0 */
5981 ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32F_as_bits(src));
5982 ins_pipe(ialu_mem_imm);
5983 %}
5984
5985 instruct storeD0(memory mem, immD0 zero)
5986 %{
5987 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
5988 match(Set mem (StoreD mem zero));
5989
5990 ins_cost(25); // XXX
5991 format %{ "movq $mem, R12\t# double 0. (R12_heapbase==0)" %}
5992 ins_encode %{
5993 __ movq($mem$$Address, r12);
5994 %}
5995 ins_pipe(ialu_mem_reg);
5996 %}
5997
5998 instruct storeSSI(stackSlotI dst, rRegI src)
5999 %{
6000 match(Set dst src);
6001
6002 ins_cost(100);
6003 format %{ "movl $dst, $src\t# int stk" %}
6004 opcode(0x89);
6005 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
6006 ins_pipe( ialu_mem_reg );
6007 %}
6008
6009 instruct storeSSL(stackSlotL dst, rRegL src)
6010 %{
6011 match(Set dst src);
6012
6013 ins_cost(100);
6014 format %{ "movq $dst, $src\t# long stk" %}
6015 opcode(0x89);
6016 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
6017 ins_pipe(ialu_mem_reg);
6018 %}
6019
6020 instruct storeSSP(stackSlotP dst, rRegP src)
6021 %{
6022 match(Set dst src);
6023
6024 ins_cost(100);
6025 format %{ "movq $dst, $src\t# ptr stk" %}
6026 opcode(0x89);
6027 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
6028 ins_pipe(ialu_mem_reg);
6029 %}
6030
6031 instruct storeSSF(stackSlotF dst, regF src)
6032 %{
6033 match(Set dst src);
6034
6035 ins_cost(95); // XXX
6036 format %{ "movss $dst, $src\t# float stk" %}
6037 ins_encode %{
6038 __ movflt(Address(rsp, $dst$$disp), $src$$XMMRegister);
6039 %}
6040 ins_pipe(pipe_slow); // XXX
6041 %}
6042
6043 instruct storeSSD(stackSlotD dst, regD src)
6044 %{
6045 match(Set dst src);
6046
6047 ins_cost(95); // XXX
6048 format %{ "movsd $dst, $src\t# double stk" %}
6049 ins_encode %{
6050 __ movdbl(Address(rsp, $dst$$disp), $src$$XMMRegister);
6051 %}
6052 ins_pipe(pipe_slow); // XXX
6053 %}
6054
6055 //----------BSWAP Instructions-------------------------------------------------
6056 instruct bytes_reverse_int(rRegI dst) %{
6057 match(Set dst (ReverseBytesI dst));
6058
6059 format %{ "bswapl $dst" %}
6060 opcode(0x0F, 0xC8); /*Opcode 0F /C8 */
6061 ins_encode( REX_reg(dst), OpcP, opc2_reg(dst) );
6062 ins_pipe( ialu_reg );
6063 %}
6064
6065 instruct bytes_reverse_long(rRegL dst) %{
6066 match(Set dst (ReverseBytesL dst));
6067
6068 format %{ "bswapq $dst" %}
6069 opcode(0x0F, 0xC8); /* Opcode 0F /C8 */
6070 ins_encode( REX_reg_wide(dst), OpcP, opc2_reg(dst) );
6071 ins_pipe( ialu_reg);
6072 %}
6073
6074 instruct bytes_reverse_unsigned_short(rRegI dst, rFlagsReg cr) %{
6075 match(Set dst (ReverseBytesUS dst));
6076 effect(KILL cr);
6077
6078 format %{ "bswapl $dst\n\t"
6079 "shrl $dst,16\n\t" %}
6080 ins_encode %{
6081 __ bswapl($dst$$Register);
6082 __ shrl($dst$$Register, 16);
6083 %}
6084 ins_pipe( ialu_reg );
6085 %}
6086
6087 instruct bytes_reverse_short(rRegI dst, rFlagsReg cr) %{
6088 match(Set dst (ReverseBytesS dst));
6089 effect(KILL cr);
6090
6091 format %{ "bswapl $dst\n\t"
6092 "sar $dst,16\n\t" %}
6093 ins_encode %{
6094 __ bswapl($dst$$Register);
6095 __ sarl($dst$$Register, 16);
6096 %}
6097 ins_pipe( ialu_reg );
6098 %}
6099
6100 //---------- Zeros Count Instructions ------------------------------------------
6101
6102 instruct countLeadingZerosI(rRegI dst, rRegI src, rFlagsReg cr) %{
6103 predicate(UseCountLeadingZerosInstruction);
6104 match(Set dst (CountLeadingZerosI src));
6105 effect(KILL cr);
6106
6107 format %{ "lzcntl $dst, $src\t# count leading zeros (int)" %}
6108 ins_encode %{
6109 __ lzcntl($dst$$Register, $src$$Register);
6110 %}
6111 ins_pipe(ialu_reg);
6112 %}
6113
6114 instruct countLeadingZerosI_bsr(rRegI dst, rRegI src, rFlagsReg cr) %{
6115 predicate(!UseCountLeadingZerosInstruction);
6116 match(Set dst (CountLeadingZerosI src));
6117 effect(KILL cr);
6118
6119 format %{ "bsrl $dst, $src\t# count leading zeros (int)\n\t"
6120 "jnz skip\n\t"
6121 "movl $dst, -1\n"
6122 "skip:\n\t"
6123 "negl $dst\n\t"
6124 "addl $dst, 31" %}
6125 ins_encode %{
6126 Register Rdst = $dst$$Register;
6127 Register Rsrc = $src$$Register;
6128 Label skip;
6129 __ bsrl(Rdst, Rsrc);
6130 __ jccb(Assembler::notZero, skip);
6131 __ movl(Rdst, -1);
6132 __ bind(skip);
6133 __ negl(Rdst);
6134 __ addl(Rdst, BitsPerInt - 1);
6135 %}
6136 ins_pipe(ialu_reg);
6137 %}
6138
6139 instruct countLeadingZerosL(rRegI dst, rRegL src, rFlagsReg cr) %{
6140 predicate(UseCountLeadingZerosInstruction);
6141 match(Set dst (CountLeadingZerosL src));
6142 effect(KILL cr);
6143
6144 format %{ "lzcntq $dst, $src\t# count leading zeros (long)" %}
6145 ins_encode %{
6146 __ lzcntq($dst$$Register, $src$$Register);
6147 %}
6148 ins_pipe(ialu_reg);
6149 %}
6150
6151 instruct countLeadingZerosL_bsr(rRegI dst, rRegL src, rFlagsReg cr) %{
6152 predicate(!UseCountLeadingZerosInstruction);
6153 match(Set dst (CountLeadingZerosL src));
6154 effect(KILL cr);
6155
6156 format %{ "bsrq $dst, $src\t# count leading zeros (long)\n\t"
6157 "jnz skip\n\t"
6158 "movl $dst, -1\n"
6159 "skip:\n\t"
6160 "negl $dst\n\t"
6161 "addl $dst, 63" %}
6162 ins_encode %{
6163 Register Rdst = $dst$$Register;
6164 Register Rsrc = $src$$Register;
6165 Label skip;
6166 __ bsrq(Rdst, Rsrc);
6167 __ jccb(Assembler::notZero, skip);
6168 __ movl(Rdst, -1);
6169 __ bind(skip);
6170 __ negl(Rdst);
6171 __ addl(Rdst, BitsPerLong - 1);
6172 %}
6173 ins_pipe(ialu_reg);
6174 %}
6175
6176 instruct countTrailingZerosI(rRegI dst, rRegI src, rFlagsReg cr) %{
6177 predicate(UseCountTrailingZerosInstruction);
6178 match(Set dst (CountTrailingZerosI src));
6179 effect(KILL cr);
6180
6181 format %{ "tzcntl $dst, $src\t# count trailing zeros (int)" %}
6182 ins_encode %{
6183 __ tzcntl($dst$$Register, $src$$Register);
6184 %}
6185 ins_pipe(ialu_reg);
6186 %}
6187
6188 instruct countTrailingZerosI_bsf(rRegI dst, rRegI src, rFlagsReg cr) %{
6189 predicate(!UseCountTrailingZerosInstruction);
6190 match(Set dst (CountTrailingZerosI src));
6191 effect(KILL cr);
6192
6193 format %{ "bsfl $dst, $src\t# count trailing zeros (int)\n\t"
6194 "jnz done\n\t"
6195 "movl $dst, 32\n"
6196 "done:" %}
6197 ins_encode %{
6198 Register Rdst = $dst$$Register;
6199 Label done;
6200 __ bsfl(Rdst, $src$$Register);
6201 __ jccb(Assembler::notZero, done);
6202 __ movl(Rdst, BitsPerInt);
6203 __ bind(done);
6204 %}
6205 ins_pipe(ialu_reg);
6206 %}
6207
6208 instruct countTrailingZerosL(rRegI dst, rRegL src, rFlagsReg cr) %{
6209 predicate(UseCountTrailingZerosInstruction);
6210 match(Set dst (CountTrailingZerosL src));
6211 effect(KILL cr);
6212
6213 format %{ "tzcntq $dst, $src\t# count trailing zeros (long)" %}
6214 ins_encode %{
6215 __ tzcntq($dst$$Register, $src$$Register);
6216 %}
6217 ins_pipe(ialu_reg);
6218 %}
6219
6220 instruct countTrailingZerosL_bsf(rRegI dst, rRegL src, rFlagsReg cr) %{
6221 predicate(!UseCountTrailingZerosInstruction);
6222 match(Set dst (CountTrailingZerosL src));
6223 effect(KILL cr);
6224
6225 format %{ "bsfq $dst, $src\t# count trailing zeros (long)\n\t"
6226 "jnz done\n\t"
6227 "movl $dst, 64\n"
6228 "done:" %}
6229 ins_encode %{
6230 Register Rdst = $dst$$Register;
6231 Label done;
6232 __ bsfq(Rdst, $src$$Register);
6233 __ jccb(Assembler::notZero, done);
6234 __ movl(Rdst, BitsPerLong);
6235 __ bind(done);
6236 %}
6237 ins_pipe(ialu_reg);
6238 %}
6239
6240
6241 //---------- Population Count Instructions -------------------------------------
6242
6243 instruct popCountI(rRegI dst, rRegI src, rFlagsReg cr) %{
6244 predicate(UsePopCountInstruction);
6245 match(Set dst (PopCountI src));
6246 effect(KILL cr);
6247
6248 format %{ "popcnt $dst, $src" %}
6249 ins_encode %{
6250 __ popcntl($dst$$Register, $src$$Register);
6251 %}
6252 ins_pipe(ialu_reg);
6253 %}
6254
6255 instruct popCountI_mem(rRegI dst, memory mem, rFlagsReg cr) %{
6256 predicate(UsePopCountInstruction);
6257 match(Set dst (PopCountI (LoadI mem)));
6258 effect(KILL cr);
6259
6260 format %{ "popcnt $dst, $mem" %}
6261 ins_encode %{
6262 __ popcntl($dst$$Register, $mem$$Address);
6263 %}
6264 ins_pipe(ialu_reg);
6265 %}
6266
6267 // Note: Long.bitCount(long) returns an int.
6268 instruct popCountL(rRegI dst, rRegL src, rFlagsReg cr) %{
6269 predicate(UsePopCountInstruction);
6270 match(Set dst (PopCountL src));
6271 effect(KILL cr);
6272
6273 format %{ "popcnt $dst, $src" %}
6274 ins_encode %{
6275 __ popcntq($dst$$Register, $src$$Register);
6276 %}
6277 ins_pipe(ialu_reg);
6278 %}
6279
6280 // Note: Long.bitCount(long) returns an int.
6281 instruct popCountL_mem(rRegI dst, memory mem, rFlagsReg cr) %{
6282 predicate(UsePopCountInstruction);
6283 match(Set dst (PopCountL (LoadL mem)));
6284 effect(KILL cr);
6285
6286 format %{ "popcnt $dst, $mem" %}
6287 ins_encode %{
6288 __ popcntq($dst$$Register, $mem$$Address);
6289 %}
6290 ins_pipe(ialu_reg);
6291 %}
6292
6293
6294 //----------MemBar Instructions-----------------------------------------------
6295 // Memory barrier flavors
6296
6297 instruct membar_acquire()
6298 %{
6299 match(MemBarAcquire);
6300 match(LoadFence);
6301 ins_cost(0);
6302
6303 size(0);
6304 format %{ "MEMBAR-acquire ! (empty encoding)" %}
6305 ins_encode();
6306 ins_pipe(empty);
6307 %}
6308
6309 instruct membar_acquire_lock()
6310 %{
6311 match(MemBarAcquireLock);
6312 ins_cost(0);
6313
6314 size(0);
6315 format %{ "MEMBAR-acquire (prior CMPXCHG in FastLock so empty encoding)" %}
6316 ins_encode();
6317 ins_pipe(empty);
6318 %}
6319
6320 instruct membar_release()
6321 %{
6322 match(MemBarRelease);
6323 match(StoreFence);
6324 ins_cost(0);
6325
6326 size(0);
6327 format %{ "MEMBAR-release ! (empty encoding)" %}
6328 ins_encode();
6329 ins_pipe(empty);
6330 %}
6331
6332 instruct membar_release_lock()
6333 %{
6334 match(MemBarReleaseLock);
6335 ins_cost(0);
6336
6337 size(0);
6338 format %{ "MEMBAR-release (a FastUnlock follows so empty encoding)" %}
6339 ins_encode();
6340 ins_pipe(empty);
6341 %}
6342
6343 instruct membar_volatile(rFlagsReg cr) %{
6344 match(MemBarVolatile);
6345 effect(KILL cr);
6346 ins_cost(400);
6347
6348 format %{
6349 $$template
6350 if (os::is_MP()) {
6351 $$emit$$"lock addl [rsp + #0], 0\t! membar_volatile"
6352 } else {
6353 $$emit$$"MEMBAR-volatile ! (empty encoding)"
6354 }
6355 %}
6356 ins_encode %{
6357 __ membar(Assembler::StoreLoad);
6358 %}
6359 ins_pipe(pipe_slow);
6360 %}
6361
6362 instruct unnecessary_membar_volatile()
6363 %{
6364 match(MemBarVolatile);
6365 predicate(Matcher::post_store_load_barrier(n));
6366 ins_cost(0);
6367
6368 size(0);
6369 format %{ "MEMBAR-volatile (unnecessary so empty encoding)" %}
6370 ins_encode();
6371 ins_pipe(empty);
6372 %}
6373
6374 instruct membar_storestore() %{
6375 match(MemBarStoreStore);
6376 ins_cost(0);
6377
6378 size(0);
6379 format %{ "MEMBAR-storestore (empty encoding)" %}
6380 ins_encode( );
6381 ins_pipe(empty);
6382 %}
6383
6384 //----------Move Instructions--------------------------------------------------
6385
6386 instruct castX2P(rRegP dst, rRegL src)
6387 %{
6388 match(Set dst (CastX2P src));
6389
6390 format %{ "movq $dst, $src\t# long->ptr" %}
6391 ins_encode %{
6392 if ($dst$$reg != $src$$reg) {
6393 __ movptr($dst$$Register, $src$$Register);
6394 }
6395 %}
6396 ins_pipe(ialu_reg_reg); // XXX
6397 %}
6398
6399 instruct castP2X(rRegL dst, rRegP src)
6400 %{
6401 match(Set dst (CastP2X src));
6402
6403 format %{ "movq $dst, $src\t# ptr -> long" %}
6404 ins_encode %{
6405 if ($dst$$reg != $src$$reg) {
6406 __ movptr($dst$$Register, $src$$Register);
6407 }
6408 %}
6409 ins_pipe(ialu_reg_reg); // XXX
6410 %}
6411
6412 // Convert oop into int for vectors alignment masking
6413 instruct convP2I(rRegI dst, rRegP src)
6414 %{
6415 match(Set dst (ConvL2I (CastP2X src)));
6416
6417 format %{ "movl $dst, $src\t# ptr -> int" %}
6418 ins_encode %{
6419 __ movl($dst$$Register, $src$$Register);
6420 %}
6421 ins_pipe(ialu_reg_reg); // XXX
6422 %}
6423
6424 // Convert compressed oop into int for vectors alignment masking
6425 // in case of 32bit oops (heap < 4Gb).
6426 instruct convN2I(rRegI dst, rRegN src)
6427 %{
6428 predicate(Universe::narrow_oop_shift() == 0);
6429 match(Set dst (ConvL2I (CastP2X (DecodeN src))));
6430
6431 format %{ "movl $dst, $src\t# compressed ptr -> int" %}
6432 ins_encode %{
6433 __ movl($dst$$Register, $src$$Register);
6434 %}
6435 ins_pipe(ialu_reg_reg); // XXX
6436 %}
6437
6438 // Convert oop pointer into compressed form
6439 instruct encodeHeapOop(rRegN dst, rRegP src, rFlagsReg cr) %{
6440 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull);
6441 match(Set dst (EncodeP src));
6442 effect(KILL cr);
6443 format %{ "encode_heap_oop $dst,$src" %}
6444 ins_encode %{
6445 Register s = $src$$Register;
6446 Register d = $dst$$Register;
6447 if (s != d) {
6448 __ movq(d, s);
6449 }
6450 __ encode_heap_oop(d);
6451 %}
6452 ins_pipe(ialu_reg_long);
6453 %}
6454
6455 instruct encodeHeapOop_not_null(rRegN dst, rRegP src, rFlagsReg cr) %{
6456 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull);
6457 match(Set dst (EncodeP src));
6458 effect(KILL cr);
6459 format %{ "encode_heap_oop_not_null $dst,$src" %}
6460 ins_encode %{
6461 __ encode_heap_oop_not_null($dst$$Register, $src$$Register);
6462 %}
6463 ins_pipe(ialu_reg_long);
6464 %}
6465
6466 instruct decodeHeapOop(rRegP dst, rRegN src, rFlagsReg cr) %{
6467 predicate(n->bottom_type()->is_ptr()->ptr() != TypePtr::NotNull &&
6468 n->bottom_type()->is_ptr()->ptr() != TypePtr::Constant);
6469 match(Set dst (DecodeN src));
6470 effect(KILL cr);
6471 format %{ "decode_heap_oop $dst,$src" %}
6472 ins_encode %{
6473 Register s = $src$$Register;
6474 Register d = $dst$$Register;
6475 if (s != d) {
6476 __ movq(d, s);
6477 }
6478 __ decode_heap_oop(d);
6479 %}
6480 ins_pipe(ialu_reg_long);
6481 %}
6482
6483 instruct decodeHeapOop_not_null(rRegP dst, rRegN src, rFlagsReg cr) %{
6484 predicate(n->bottom_type()->is_ptr()->ptr() == TypePtr::NotNull ||
6485 n->bottom_type()->is_ptr()->ptr() == TypePtr::Constant);
6486 match(Set dst (DecodeN src));
6487 effect(KILL cr);
6488 format %{ "decode_heap_oop_not_null $dst,$src" %}
6489 ins_encode %{
6490 Register s = $src$$Register;
6491 Register d = $dst$$Register;
6492 if (s != d) {
6493 __ decode_heap_oop_not_null(d, s);
6494 } else {
6495 __ decode_heap_oop_not_null(d);
6496 }
6497 %}
6498 ins_pipe(ialu_reg_long);
6499 %}
6500
6501 instruct encodeKlass_not_null(rRegN dst, rRegP src, rFlagsReg cr) %{
6502 match(Set dst (EncodePKlass src));
6503 effect(KILL cr);
6504 format %{ "encode_klass_not_null $dst,$src" %}
6505 ins_encode %{
6506 __ encode_klass_not_null($dst$$Register, $src$$Register);
6507 %}
6508 ins_pipe(ialu_reg_long);
6509 %}
6510
6511 instruct decodeKlass_not_null(rRegP dst, rRegN src, rFlagsReg cr) %{
6512 match(Set dst (DecodeNKlass src));
6513 effect(KILL cr);
6514 format %{ "decode_klass_not_null $dst,$src" %}
6515 ins_encode %{
6516 Register s = $src$$Register;
6517 Register d = $dst$$Register;
6518 if (s != d) {
6519 __ decode_klass_not_null(d, s);
6520 } else {
6521 __ decode_klass_not_null(d);
6522 }
6523 %}
6524 ins_pipe(ialu_reg_long);
6525 %}
6526
6527
6528 //----------Conditional Move---------------------------------------------------
6529 // Jump
6530 // dummy instruction for generating temp registers
6531 instruct jumpXtnd_offset(rRegL switch_val, immI2 shift, rRegI dest) %{
6532 match(Jump (LShiftL switch_val shift));
6533 ins_cost(350);
6534 predicate(false);
6535 effect(TEMP dest);
6536
6537 format %{ "leaq $dest, [$constantaddress]\n\t"
6538 "jmp [$dest + $switch_val << $shift]\n\t" %}
6539 ins_encode %{
6540 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10
6541 // to do that and the compiler is using that register as one it can allocate.
6542 // So we build it all by hand.
6543 // Address index(noreg, switch_reg, (Address::ScaleFactor)$shift$$constant);
6544 // ArrayAddress dispatch(table, index);
6545 Address dispatch($dest$$Register, $switch_val$$Register, (Address::ScaleFactor) $shift$$constant);
6546 __ lea($dest$$Register, $constantaddress);
6547 __ jmp(dispatch);
6548 %}
6549 ins_pipe(pipe_jmp);
6550 %}
6551
6552 instruct jumpXtnd_addr(rRegL switch_val, immI2 shift, immL32 offset, rRegI dest) %{
6553 match(Jump (AddL (LShiftL switch_val shift) offset));
6554 ins_cost(350);
6555 effect(TEMP dest);
6556
6557 format %{ "leaq $dest, [$constantaddress]\n\t"
6558 "jmp [$dest + $switch_val << $shift + $offset]\n\t" %}
6559 ins_encode %{
6560 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10
6561 // to do that and the compiler is using that register as one it can allocate.
6562 // So we build it all by hand.
6563 // Address index(noreg, switch_reg, (Address::ScaleFactor) $shift$$constant, (int) $offset$$constant);
6564 // ArrayAddress dispatch(table, index);
6565 Address dispatch($dest$$Register, $switch_val$$Register, (Address::ScaleFactor) $shift$$constant, (int) $offset$$constant);
6566 __ lea($dest$$Register, $constantaddress);
6567 __ jmp(dispatch);
6568 %}
6569 ins_pipe(pipe_jmp);
6570 %}
6571
6572 instruct jumpXtnd(rRegL switch_val, rRegI dest) %{
6573 match(Jump switch_val);
6574 ins_cost(350);
6575 effect(TEMP dest);
6576
6577 format %{ "leaq $dest, [$constantaddress]\n\t"
6578 "jmp [$dest + $switch_val]\n\t" %}
6579 ins_encode %{
6580 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10
6581 // to do that and the compiler is using that register as one it can allocate.
6582 // So we build it all by hand.
6583 // Address index(noreg, switch_reg, Address::times_1);
6584 // ArrayAddress dispatch(table, index);
6585 Address dispatch($dest$$Register, $switch_val$$Register, Address::times_1);
6586 __ lea($dest$$Register, $constantaddress);
6587 __ jmp(dispatch);
6588 %}
6589 ins_pipe(pipe_jmp);
6590 %}
6591
6592 // Conditional move
6593 instruct cmovI_reg(rRegI dst, rRegI src, rFlagsReg cr, cmpOp cop)
6594 %{
6595 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
6596
6597 ins_cost(200); // XXX
6598 format %{ "cmovl$cop $dst, $src\t# signed, int" %}
6599 opcode(0x0F, 0x40);
6600 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src));
6601 ins_pipe(pipe_cmov_reg);
6602 %}
6603
6604 instruct cmovI_regU(cmpOpU cop, rFlagsRegU cr, rRegI dst, rRegI src) %{
6605 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
6606
6607 ins_cost(200); // XXX
6608 format %{ "cmovl$cop $dst, $src\t# unsigned, int" %}
6609 opcode(0x0F, 0x40);
6610 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src));
6611 ins_pipe(pipe_cmov_reg);
6612 %}
6613
6614 instruct cmovI_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegI dst, rRegI src) %{
6615 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
6616 ins_cost(200);
6617 expand %{
6618 cmovI_regU(cop, cr, dst, src);
6619 %}
6620 %}
6621
6622 // Conditional move
6623 instruct cmovI_mem(cmpOp cop, rFlagsReg cr, rRegI dst, memory src) %{
6624 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
6625
6626 ins_cost(250); // XXX
6627 format %{ "cmovl$cop $dst, $src\t# signed, int" %}
6628 opcode(0x0F, 0x40);
6629 ins_encode(REX_reg_mem(dst, src), enc_cmov(cop), reg_mem(dst, src));
6630 ins_pipe(pipe_cmov_mem);
6631 %}
6632
6633 // Conditional move
6634 instruct cmovI_memU(cmpOpU cop, rFlagsRegU cr, rRegI dst, memory src)
6635 %{
6636 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
6637
6638 ins_cost(250); // XXX
6639 format %{ "cmovl$cop $dst, $src\t# unsigned, int" %}
6640 opcode(0x0F, 0x40);
6641 ins_encode(REX_reg_mem(dst, src), enc_cmov(cop), reg_mem(dst, src));
6642 ins_pipe(pipe_cmov_mem);
6643 %}
6644
6645 instruct cmovI_memUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegI dst, memory src) %{
6646 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
6647 ins_cost(250);
6648 expand %{
6649 cmovI_memU(cop, cr, dst, src);
6650 %}
6651 %}
6652
6653 // Conditional move
6654 instruct cmovN_reg(rRegN dst, rRegN src, rFlagsReg cr, cmpOp cop)
6655 %{
6656 match(Set dst (CMoveN (Binary cop cr) (Binary dst src)));
6657
6658 ins_cost(200); // XXX
6659 format %{ "cmovl$cop $dst, $src\t# signed, compressed ptr" %}
6660 opcode(0x0F, 0x40);
6661 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src));
6662 ins_pipe(pipe_cmov_reg);
6663 %}
6664
6665 // Conditional move
6666 instruct cmovN_regU(cmpOpU cop, rFlagsRegU cr, rRegN dst, rRegN src)
6667 %{
6668 match(Set dst (CMoveN (Binary cop cr) (Binary dst src)));
6669
6670 ins_cost(200); // XXX
6671 format %{ "cmovl$cop $dst, $src\t# unsigned, compressed ptr" %}
6672 opcode(0x0F, 0x40);
6673 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src));
6674 ins_pipe(pipe_cmov_reg);
6675 %}
6676
6677 instruct cmovN_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegN dst, rRegN src) %{
6678 match(Set dst (CMoveN (Binary cop cr) (Binary dst src)));
6679 ins_cost(200);
6680 expand %{
6681 cmovN_regU(cop, cr, dst, src);
6682 %}
6683 %}
6684
6685 // Conditional move
6686 instruct cmovP_reg(rRegP dst, rRegP src, rFlagsReg cr, cmpOp cop)
6687 %{
6688 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
6689
6690 ins_cost(200); // XXX
6691 format %{ "cmovq$cop $dst, $src\t# signed, ptr" %}
6692 opcode(0x0F, 0x40);
6693 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src));
6694 ins_pipe(pipe_cmov_reg); // XXX
6695 %}
6696
6697 // Conditional move
6698 instruct cmovP_regU(cmpOpU cop, rFlagsRegU cr, rRegP dst, rRegP src)
6699 %{
6700 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
6701
6702 ins_cost(200); // XXX
6703 format %{ "cmovq$cop $dst, $src\t# unsigned, ptr" %}
6704 opcode(0x0F, 0x40);
6705 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src));
6706 ins_pipe(pipe_cmov_reg); // XXX
6707 %}
6708
6709 instruct cmovP_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegP dst, rRegP src) %{
6710 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
6711 ins_cost(200);
6712 expand %{
6713 cmovP_regU(cop, cr, dst, src);
6714 %}
6715 %}
6716
6717 // DISABLED: Requires the ADLC to emit a bottom_type call that
6718 // correctly meets the two pointer arguments; one is an incoming
6719 // register but the other is a memory operand. ALSO appears to
6720 // be buggy with implicit null checks.
6721 //
6722 //// Conditional move
6723 //instruct cmovP_mem(cmpOp cop, rFlagsReg cr, rRegP dst, memory src)
6724 //%{
6725 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
6726 // ins_cost(250);
6727 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
6728 // opcode(0x0F,0x40);
6729 // ins_encode( enc_cmov(cop), reg_mem( dst, src ) );
6730 // ins_pipe( pipe_cmov_mem );
6731 //%}
6732 //
6733 //// Conditional move
6734 //instruct cmovP_memU(cmpOpU cop, rFlagsRegU cr, rRegP dst, memory src)
6735 //%{
6736 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
6737 // ins_cost(250);
6738 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
6739 // opcode(0x0F,0x40);
6740 // ins_encode( enc_cmov(cop), reg_mem( dst, src ) );
6741 // ins_pipe( pipe_cmov_mem );
6742 //%}
6743
6744 instruct cmovL_reg(cmpOp cop, rFlagsReg cr, rRegL dst, rRegL src)
6745 %{
6746 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
6747
6748 ins_cost(200); // XXX
6749 format %{ "cmovq$cop $dst, $src\t# signed, long" %}
6750 opcode(0x0F, 0x40);
6751 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src));
6752 ins_pipe(pipe_cmov_reg); // XXX
6753 %}
6754
6755 instruct cmovL_mem(cmpOp cop, rFlagsReg cr, rRegL dst, memory src)
6756 %{
6757 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src))));
6758
6759 ins_cost(200); // XXX
6760 format %{ "cmovq$cop $dst, $src\t# signed, long" %}
6761 opcode(0x0F, 0x40);
6762 ins_encode(REX_reg_mem_wide(dst, src), enc_cmov(cop), reg_mem(dst, src));
6763 ins_pipe(pipe_cmov_mem); // XXX
6764 %}
6765
6766 instruct cmovL_regU(cmpOpU cop, rFlagsRegU cr, rRegL dst, rRegL src)
6767 %{
6768 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
6769
6770 ins_cost(200); // XXX
6771 format %{ "cmovq$cop $dst, $src\t# unsigned, long" %}
6772 opcode(0x0F, 0x40);
6773 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src));
6774 ins_pipe(pipe_cmov_reg); // XXX
6775 %}
6776
6777 instruct cmovL_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegL dst, rRegL src) %{
6778 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
6779 ins_cost(200);
6780 expand %{
6781 cmovL_regU(cop, cr, dst, src);
6782 %}
6783 %}
6784
6785 instruct cmovL_memU(cmpOpU cop, rFlagsRegU cr, rRegL dst, memory src)
6786 %{
6787 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src))));
6788
6789 ins_cost(200); // XXX
6790 format %{ "cmovq$cop $dst, $src\t# unsigned, long" %}
6791 opcode(0x0F, 0x40);
6792 ins_encode(REX_reg_mem_wide(dst, src), enc_cmov(cop), reg_mem(dst, src));
6793 ins_pipe(pipe_cmov_mem); // XXX
6794 %}
6795
6796 instruct cmovL_memUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegL dst, memory src) %{
6797 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src))));
6798 ins_cost(200);
6799 expand %{
6800 cmovL_memU(cop, cr, dst, src);
6801 %}
6802 %}
6803
6804 instruct cmovF_reg(cmpOp cop, rFlagsReg cr, regF dst, regF src)
6805 %{
6806 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
6807
6808 ins_cost(200); // XXX
6809 format %{ "jn$cop skip\t# signed cmove float\n\t"
6810 "movss $dst, $src\n"
6811 "skip:" %}
6812 ins_encode %{
6813 Label Lskip;
6814 // Invert sense of branch from sense of CMOV
6815 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
6816 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
6817 __ bind(Lskip);
6818 %}
6819 ins_pipe(pipe_slow);
6820 %}
6821
6822 // instruct cmovF_mem(cmpOp cop, rFlagsReg cr, regF dst, memory src)
6823 // %{
6824 // match(Set dst (CMoveF (Binary cop cr) (Binary dst (LoadL src))));
6825
6826 // ins_cost(200); // XXX
6827 // format %{ "jn$cop skip\t# signed cmove float\n\t"
6828 // "movss $dst, $src\n"
6829 // "skip:" %}
6830 // ins_encode(enc_cmovf_mem_branch(cop, dst, src));
6831 // ins_pipe(pipe_slow);
6832 // %}
6833
6834 instruct cmovF_regU(cmpOpU cop, rFlagsRegU cr, regF dst, regF src)
6835 %{
6836 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
6837
6838 ins_cost(200); // XXX
6839 format %{ "jn$cop skip\t# unsigned cmove float\n\t"
6840 "movss $dst, $src\n"
6841 "skip:" %}
6842 ins_encode %{
6843 Label Lskip;
6844 // Invert sense of branch from sense of CMOV
6845 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
6846 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
6847 __ bind(Lskip);
6848 %}
6849 ins_pipe(pipe_slow);
6850 %}
6851
6852 instruct cmovF_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, regF dst, regF src) %{
6853 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
6854 ins_cost(200);
6855 expand %{
6856 cmovF_regU(cop, cr, dst, src);
6857 %}
6858 %}
6859
6860 instruct cmovD_reg(cmpOp cop, rFlagsReg cr, regD dst, regD src)
6861 %{
6862 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
6863
6864 ins_cost(200); // XXX
6865 format %{ "jn$cop skip\t# signed cmove double\n\t"
6866 "movsd $dst, $src\n"
6867 "skip:" %}
6868 ins_encode %{
6869 Label Lskip;
6870 // Invert sense of branch from sense of CMOV
6871 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
6872 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
6873 __ bind(Lskip);
6874 %}
6875 ins_pipe(pipe_slow);
6876 %}
6877
6878 instruct cmovD_regU(cmpOpU cop, rFlagsRegU cr, regD dst, regD src)
6879 %{
6880 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
6881
6882 ins_cost(200); // XXX
6883 format %{ "jn$cop skip\t# unsigned cmove double\n\t"
6884 "movsd $dst, $src\n"
6885 "skip:" %}
6886 ins_encode %{
6887 Label Lskip;
6888 // Invert sense of branch from sense of CMOV
6889 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
6890 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
6891 __ bind(Lskip);
6892 %}
6893 ins_pipe(pipe_slow);
6894 %}
6895
6896 instruct cmovD_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, regD dst, regD src) %{
6897 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
6898 ins_cost(200);
6899 expand %{
6900 cmovD_regU(cop, cr, dst, src);
6901 %}
6902 %}
6903
6904 //----------Arithmetic Instructions--------------------------------------------
6905 //----------Addition Instructions----------------------------------------------
6906
6907 instruct addI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
6908 %{
6909 match(Set dst (AddI dst src));
6910 effect(KILL cr);
6911
6912 format %{ "addl $dst, $src\t# int" %}
6913 opcode(0x03);
6914 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
6915 ins_pipe(ialu_reg_reg);
6916 %}
6917
6918 instruct addI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
6919 %{
6920 match(Set dst (AddI dst src));
6921 effect(KILL cr);
6922
6923 format %{ "addl $dst, $src\t# int" %}
6924 opcode(0x81, 0x00); /* /0 id */
6925 ins_encode(OpcSErm(dst, src), Con8or32(src));
6926 ins_pipe( ialu_reg );
6927 %}
6928
6929 instruct addI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
6930 %{
6931 match(Set dst (AddI dst (LoadI src)));
6932 effect(KILL cr);
6933
6934 ins_cost(125); // XXX
6935 format %{ "addl $dst, $src\t# int" %}
6936 opcode(0x03);
6937 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
6938 ins_pipe(ialu_reg_mem);
6939 %}
6940
6941 instruct addI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
6942 %{
6943 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
6944 effect(KILL cr);
6945
6946 ins_cost(150); // XXX
6947 format %{ "addl $dst, $src\t# int" %}
6948 opcode(0x01); /* Opcode 01 /r */
6949 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
6950 ins_pipe(ialu_mem_reg);
6951 %}
6952
6953 instruct addI_mem_imm(memory dst, immI src, rFlagsReg cr)
6954 %{
6955 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
6956 effect(KILL cr);
6957
6958 ins_cost(125); // XXX
6959 format %{ "addl $dst, $src\t# int" %}
6960 opcode(0x81); /* Opcode 81 /0 id */
6961 ins_encode(REX_mem(dst), OpcSE(src), RM_opc_mem(0x00, dst), Con8or32(src));
6962 ins_pipe(ialu_mem_imm);
6963 %}
6964
6965 instruct incI_rReg(rRegI dst, immI1 src, rFlagsReg cr)
6966 %{
6967 predicate(UseIncDec);
6968 match(Set dst (AddI dst src));
6969 effect(KILL cr);
6970
6971 format %{ "incl $dst\t# int" %}
6972 opcode(0xFF, 0x00); // FF /0
6973 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
6974 ins_pipe(ialu_reg);
6975 %}
6976
6977 instruct incI_mem(memory dst, immI1 src, rFlagsReg cr)
6978 %{
6979 predicate(UseIncDec);
6980 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
6981 effect(KILL cr);
6982
6983 ins_cost(125); // XXX
6984 format %{ "incl $dst\t# int" %}
6985 opcode(0xFF); /* Opcode FF /0 */
6986 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(0x00, dst));
6987 ins_pipe(ialu_mem_imm);
6988 %}
6989
6990 // XXX why does that use AddI
6991 instruct decI_rReg(rRegI dst, immI_M1 src, rFlagsReg cr)
6992 %{
6993 predicate(UseIncDec);
6994 match(Set dst (AddI dst src));
6995 effect(KILL cr);
6996
6997 format %{ "decl $dst\t# int" %}
6998 opcode(0xFF, 0x01); // FF /1
6999 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
7000 ins_pipe(ialu_reg);
7001 %}
7002
7003 // XXX why does that use AddI
7004 instruct decI_mem(memory dst, immI_M1 src, rFlagsReg cr)
7005 %{
7006 predicate(UseIncDec);
7007 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7008 effect(KILL cr);
7009
7010 ins_cost(125); // XXX
7011 format %{ "decl $dst\t# int" %}
7012 opcode(0xFF); /* Opcode FF /1 */
7013 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(0x01, dst));
7014 ins_pipe(ialu_mem_imm);
7015 %}
7016
7017 instruct leaI_rReg_immI(rRegI dst, rRegI src0, immI src1)
7018 %{
7019 match(Set dst (AddI src0 src1));
7020
7021 ins_cost(110);
7022 format %{ "addr32 leal $dst, [$src0 + $src1]\t# int" %}
7023 opcode(0x8D); /* 0x8D /r */
7024 ins_encode(Opcode(0x67), REX_reg_reg(dst, src0), OpcP, reg_lea(dst, src0, src1)); // XXX
7025 ins_pipe(ialu_reg_reg);
7026 %}
7027
7028 instruct addL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
7029 %{
7030 match(Set dst (AddL dst src));
7031 effect(KILL cr);
7032
7033 format %{ "addq $dst, $src\t# long" %}
7034 opcode(0x03);
7035 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
7036 ins_pipe(ialu_reg_reg);
7037 %}
7038
7039 instruct addL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
7040 %{
7041 match(Set dst (AddL dst src));
7042 effect(KILL cr);
7043
7044 format %{ "addq $dst, $src\t# long" %}
7045 opcode(0x81, 0x00); /* /0 id */
7046 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
7047 ins_pipe( ialu_reg );
7048 %}
7049
7050 instruct addL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
7051 %{
7052 match(Set dst (AddL dst (LoadL src)));
7053 effect(KILL cr);
7054
7055 ins_cost(125); // XXX
7056 format %{ "addq $dst, $src\t# long" %}
7057 opcode(0x03);
7058 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
7059 ins_pipe(ialu_reg_mem);
7060 %}
7061
7062 instruct addL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
7063 %{
7064 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
7065 effect(KILL cr);
7066
7067 ins_cost(150); // XXX
7068 format %{ "addq $dst, $src\t# long" %}
7069 opcode(0x01); /* Opcode 01 /r */
7070 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
7071 ins_pipe(ialu_mem_reg);
7072 %}
7073
7074 instruct addL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
7075 %{
7076 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
7077 effect(KILL cr);
7078
7079 ins_cost(125); // XXX
7080 format %{ "addq $dst, $src\t# long" %}
7081 opcode(0x81); /* Opcode 81 /0 id */
7082 ins_encode(REX_mem_wide(dst),
7083 OpcSE(src), RM_opc_mem(0x00, dst), Con8or32(src));
7084 ins_pipe(ialu_mem_imm);
7085 %}
7086
7087 instruct incL_rReg(rRegI dst, immL1 src, rFlagsReg cr)
7088 %{
7089 predicate(UseIncDec);
7090 match(Set dst (AddL dst src));
7091 effect(KILL cr);
7092
7093 format %{ "incq $dst\t# long" %}
7094 opcode(0xFF, 0x00); // FF /0
7095 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
7096 ins_pipe(ialu_reg);
7097 %}
7098
7099 instruct incL_mem(memory dst, immL1 src, rFlagsReg cr)
7100 %{
7101 predicate(UseIncDec);
7102 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
7103 effect(KILL cr);
7104
7105 ins_cost(125); // XXX
7106 format %{ "incq $dst\t# long" %}
7107 opcode(0xFF); /* Opcode FF /0 */
7108 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(0x00, dst));
7109 ins_pipe(ialu_mem_imm);
7110 %}
7111
7112 // XXX why does that use AddL
7113 instruct decL_rReg(rRegL dst, immL_M1 src, rFlagsReg cr)
7114 %{
7115 predicate(UseIncDec);
7116 match(Set dst (AddL dst src));
7117 effect(KILL cr);
7118
7119 format %{ "decq $dst\t# long" %}
7120 opcode(0xFF, 0x01); // FF /1
7121 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
7122 ins_pipe(ialu_reg);
7123 %}
7124
7125 // XXX why does that use AddL
7126 instruct decL_mem(memory dst, immL_M1 src, rFlagsReg cr)
7127 %{
7128 predicate(UseIncDec);
7129 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
7130 effect(KILL cr);
7131
7132 ins_cost(125); // XXX
7133 format %{ "decq $dst\t# long" %}
7134 opcode(0xFF); /* Opcode FF /1 */
7135 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(0x01, dst));
7136 ins_pipe(ialu_mem_imm);
7137 %}
7138
7139 instruct leaL_rReg_immL(rRegL dst, rRegL src0, immL32 src1)
7140 %{
7141 match(Set dst (AddL src0 src1));
7142
7143 ins_cost(110);
7144 format %{ "leaq $dst, [$src0 + $src1]\t# long" %}
7145 opcode(0x8D); /* 0x8D /r */
7146 ins_encode(REX_reg_reg_wide(dst, src0), OpcP, reg_lea(dst, src0, src1)); // XXX
7147 ins_pipe(ialu_reg_reg);
7148 %}
7149
7150 instruct addP_rReg(rRegP dst, rRegL src, rFlagsReg cr)
7151 %{
7152 match(Set dst (AddP dst src));
7153 effect(KILL cr);
7154
7155 format %{ "addq $dst, $src\t# ptr" %}
7156 opcode(0x03);
7157 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
7158 ins_pipe(ialu_reg_reg);
7159 %}
7160
7161 instruct addP_rReg_imm(rRegP dst, immL32 src, rFlagsReg cr)
7162 %{
7163 match(Set dst (AddP dst src));
7164 effect(KILL cr);
7165
7166 format %{ "addq $dst, $src\t# ptr" %}
7167 opcode(0x81, 0x00); /* /0 id */
7168 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
7169 ins_pipe( ialu_reg );
7170 %}
7171
7172 // XXX addP mem ops ????
7173
7174 instruct leaP_rReg_imm(rRegP dst, rRegP src0, immL32 src1)
7175 %{
7176 match(Set dst (AddP src0 src1));
7177
7178 ins_cost(110);
7179 format %{ "leaq $dst, [$src0 + $src1]\t# ptr" %}
7180 opcode(0x8D); /* 0x8D /r */
7181 ins_encode(REX_reg_reg_wide(dst, src0), OpcP, reg_lea(dst, src0, src1));// XXX
7182 ins_pipe(ialu_reg_reg);
7183 %}
7184
7185 instruct checkCastPP(rRegP dst)
7186 %{
7187 match(Set dst (CheckCastPP dst));
7188
7189 size(0);
7190 format %{ "# checkcastPP of $dst" %}
7191 ins_encode(/* empty encoding */);
7192 ins_pipe(empty);
7193 %}
7194
7195 instruct castPP(rRegP dst)
7196 %{
7197 match(Set dst (CastPP dst));
7198
7199 size(0);
7200 format %{ "# castPP of $dst" %}
7201 ins_encode(/* empty encoding */);
7202 ins_pipe(empty);
7203 %}
7204
7205 instruct castII(rRegI dst)
7206 %{
7207 match(Set dst (CastII dst));
7208
7209 size(0);
7210 format %{ "# castII of $dst" %}
7211 ins_encode(/* empty encoding */);
7212 ins_cost(0);
7213 ins_pipe(empty);
7214 %}
7215
7216 // LoadP-locked same as a regular LoadP when used with compare-swap
7217 instruct loadPLocked(rRegP dst, memory mem)
7218 %{
7219 match(Set dst (LoadPLocked mem));
7220
7221 ins_cost(125); // XXX
7222 format %{ "movq $dst, $mem\t# ptr locked" %}
7223 opcode(0x8B);
7224 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
7225 ins_pipe(ialu_reg_mem); // XXX
7226 %}
7227
7228 // Conditional-store of the updated heap-top.
7229 // Used during allocation of the shared heap.
7230 // Sets flags (EQ) on success. Implemented with a CMPXCHG on Intel.
7231
7232 instruct storePConditional(memory heap_top_ptr,
7233 rax_RegP oldval, rRegP newval,
7234 rFlagsReg cr)
7235 %{
7236 match(Set cr (StorePConditional heap_top_ptr (Binary oldval newval)));
7237
7238 format %{ "cmpxchgq $heap_top_ptr, $newval\t# (ptr) "
7239 "If rax == $heap_top_ptr then store $newval into $heap_top_ptr" %}
7240 opcode(0x0F, 0xB1);
7241 ins_encode(lock_prefix,
7242 REX_reg_mem_wide(newval, heap_top_ptr),
7243 OpcP, OpcS,
7244 reg_mem(newval, heap_top_ptr));
7245 ins_pipe(pipe_cmpxchg);
7246 %}
7247
7248 // Conditional-store of an int value.
7249 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG.
7250 instruct storeIConditional(memory mem, rax_RegI oldval, rRegI newval, rFlagsReg cr)
7251 %{
7252 match(Set cr (StoreIConditional mem (Binary oldval newval)));
7253 effect(KILL oldval);
7254
7255 format %{ "cmpxchgl $mem, $newval\t# If rax == $mem then store $newval into $mem" %}
7256 opcode(0x0F, 0xB1);
7257 ins_encode(lock_prefix,
7258 REX_reg_mem(newval, mem),
7259 OpcP, OpcS,
7260 reg_mem(newval, mem));
7261 ins_pipe(pipe_cmpxchg);
7262 %}
7263
7264 // Conditional-store of a long value.
7265 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG.
7266 instruct storeLConditional(memory mem, rax_RegL oldval, rRegL newval, rFlagsReg cr)
7267 %{
7268 match(Set cr (StoreLConditional mem (Binary oldval newval)));
7269 effect(KILL oldval);
7270
7271 format %{ "cmpxchgq $mem, $newval\t# If rax == $mem then store $newval into $mem" %}
7272 opcode(0x0F, 0xB1);
7273 ins_encode(lock_prefix,
7274 REX_reg_mem_wide(newval, mem),
7275 OpcP, OpcS,
7276 reg_mem(newval, mem));
7277 ins_pipe(pipe_cmpxchg);
7278 %}
7279
7280
7281 // XXX No flag versions for CompareAndSwap{P,I,L} because matcher can't match them
7282 instruct compareAndSwapP(rRegI res,
7283 memory mem_ptr,
7284 rax_RegP oldval, rRegP newval,
7285 rFlagsReg cr)
7286 %{
7287 predicate(VM_Version::supports_cx8());
7288 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
7289 match(Set res (WeakCompareAndSwapP mem_ptr (Binary oldval newval)));
7290 effect(KILL cr, KILL oldval);
7291
7292 format %{ "cmpxchgq $mem_ptr,$newval\t# "
7293 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7294 "sete $res\n\t"
7295 "movzbl $res, $res" %}
7296 opcode(0x0F, 0xB1);
7297 ins_encode(lock_prefix,
7298 REX_reg_mem_wide(newval, mem_ptr),
7299 OpcP, OpcS,
7300 reg_mem(newval, mem_ptr),
7301 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7302 REX_reg_breg(res, res), // movzbl
7303 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7304 ins_pipe( pipe_cmpxchg );
7305 %}
7306
7307 instruct compareAndSwapL(rRegI res,
7308 memory mem_ptr,
7309 rax_RegL oldval, rRegL newval,
7310 rFlagsReg cr)
7311 %{
7312 predicate(VM_Version::supports_cx8());
7313 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
7314 match(Set res (WeakCompareAndSwapL mem_ptr (Binary oldval newval)));
7315 effect(KILL cr, KILL oldval);
7316
7317 format %{ "cmpxchgq $mem_ptr,$newval\t# "
7318 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7319 "sete $res\n\t"
7320 "movzbl $res, $res" %}
7321 opcode(0x0F, 0xB1);
7322 ins_encode(lock_prefix,
7323 REX_reg_mem_wide(newval, mem_ptr),
7324 OpcP, OpcS,
7325 reg_mem(newval, mem_ptr),
7326 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7327 REX_reg_breg(res, res), // movzbl
7328 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7329 ins_pipe( pipe_cmpxchg );
7330 %}
7331
7332 instruct compareAndSwapI(rRegI res,
7333 memory mem_ptr,
7334 rax_RegI oldval, rRegI newval,
7335 rFlagsReg cr)
7336 %{
7337 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
7338 match(Set res (WeakCompareAndSwapI mem_ptr (Binary oldval newval)));
7339 effect(KILL cr, KILL oldval);
7340
7341 format %{ "cmpxchgl $mem_ptr,$newval\t# "
7342 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7343 "sete $res\n\t"
7344 "movzbl $res, $res" %}
7345 opcode(0x0F, 0xB1);
7346 ins_encode(lock_prefix,
7347 REX_reg_mem(newval, mem_ptr),
7348 OpcP, OpcS,
7349 reg_mem(newval, mem_ptr),
7350 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7351 REX_reg_breg(res, res), // movzbl
7352 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7353 ins_pipe( pipe_cmpxchg );
7354 %}
7355
7356 instruct compareAndSwapB(rRegI res,
7357 memory mem_ptr,
7358 rax_RegI oldval, rRegI newval,
7359 rFlagsReg cr)
7360 %{
7361 match(Set res (CompareAndSwapB mem_ptr (Binary oldval newval)));
7362 match(Set res (WeakCompareAndSwapB mem_ptr (Binary oldval newval)));
7363 effect(KILL cr, KILL oldval);
7364
7365 format %{ "cmpxchgb $mem_ptr,$newval\t# "
7366 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7367 "sete $res\n\t"
7368 "movzbl $res, $res" %}
7369 opcode(0x0F, 0xB0);
7370 ins_encode(lock_prefix,
7371 REX_breg_mem(newval, mem_ptr),
7372 OpcP, OpcS,
7373 reg_mem(newval, mem_ptr),
7374 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7375 REX_reg_breg(res, res), // movzbl
7376 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7377 ins_pipe( pipe_cmpxchg );
7378 %}
7379
7380 instruct compareAndSwapS(rRegI res,
7381 memory mem_ptr,
7382 rax_RegI oldval, rRegI newval,
7383 rFlagsReg cr)
7384 %{
7385 match(Set res (CompareAndSwapS mem_ptr (Binary oldval newval)));
7386 match(Set res (WeakCompareAndSwapS mem_ptr (Binary oldval newval)));
7387 effect(KILL cr, KILL oldval);
7388
7389 format %{ "cmpxchgw $mem_ptr,$newval\t# "
7390 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7391 "sete $res\n\t"
7392 "movzbl $res, $res" %}
7393 opcode(0x0F, 0xB1);
7394 ins_encode(lock_prefix,
7395 SizePrefix,
7396 REX_reg_mem(newval, mem_ptr),
7397 OpcP, OpcS,
7398 reg_mem(newval, mem_ptr),
7399 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7400 REX_reg_breg(res, res), // movzbl
7401 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7402 ins_pipe( pipe_cmpxchg );
7403 %}
7404
7405 instruct compareAndSwapN(rRegI res,
7406 memory mem_ptr,
7407 rax_RegN oldval, rRegN newval,
7408 rFlagsReg cr) %{
7409 match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval)));
7410 match(Set res (WeakCompareAndSwapN mem_ptr (Binary oldval newval)));
7411 effect(KILL cr, KILL oldval);
7412
7413 format %{ "cmpxchgl $mem_ptr,$newval\t# "
7414 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7415 "sete $res\n\t"
7416 "movzbl $res, $res" %}
7417 opcode(0x0F, 0xB1);
7418 ins_encode(lock_prefix,
7419 REX_reg_mem(newval, mem_ptr),
7420 OpcP, OpcS,
7421 reg_mem(newval, mem_ptr),
7422 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7423 REX_reg_breg(res, res), // movzbl
7424 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7425 ins_pipe( pipe_cmpxchg );
7426 %}
7427
7428 instruct compareAndExchangeB(
7429 memory mem_ptr,
7430 rax_RegI oldval, rRegI newval,
7431 rFlagsReg cr)
7432 %{
7433 match(Set oldval (CompareAndExchangeB mem_ptr (Binary oldval newval)));
7434 effect(KILL cr);
7435
7436 format %{ "cmpxchgb $mem_ptr,$newval\t# "
7437 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" %}
7438 opcode(0x0F, 0xB0);
7439 ins_encode(lock_prefix,
7440 REX_breg_mem(newval, mem_ptr),
7441 OpcP, OpcS,
7442 reg_mem(newval, mem_ptr) // lock cmpxchg
7443 );
7444 ins_pipe( pipe_cmpxchg );
7445 %}
7446
7447 instruct compareAndExchangeS(
7448 memory mem_ptr,
7449 rax_RegI oldval, rRegI newval,
7450 rFlagsReg cr)
7451 %{
7452 match(Set oldval (CompareAndExchangeS mem_ptr (Binary oldval newval)));
7453 effect(KILL cr);
7454
7455 format %{ "cmpxchgw $mem_ptr,$newval\t# "
7456 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" %}
7457 opcode(0x0F, 0xB1);
7458 ins_encode(lock_prefix,
7459 SizePrefix,
7460 REX_reg_mem(newval, mem_ptr),
7461 OpcP, OpcS,
7462 reg_mem(newval, mem_ptr) // lock cmpxchg
7463 );
7464 ins_pipe( pipe_cmpxchg );
7465 %}
7466
7467 instruct compareAndExchangeI(
7468 memory mem_ptr,
7469 rax_RegI oldval, rRegI newval,
7470 rFlagsReg cr)
7471 %{
7472 match(Set oldval (CompareAndExchangeI mem_ptr (Binary oldval newval)));
7473 effect(KILL cr);
7474
7475 format %{ "cmpxchgl $mem_ptr,$newval\t# "
7476 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" %}
7477 opcode(0x0F, 0xB1);
7478 ins_encode(lock_prefix,
7479 REX_reg_mem(newval, mem_ptr),
7480 OpcP, OpcS,
7481 reg_mem(newval, mem_ptr) // lock cmpxchg
7482 );
7483 ins_pipe( pipe_cmpxchg );
7484 %}
7485
7486 instruct compareAndExchangeL(
7487 memory mem_ptr,
7488 rax_RegL oldval, rRegL newval,
7489 rFlagsReg cr)
7490 %{
7491 predicate(VM_Version::supports_cx8());
7492 match(Set oldval (CompareAndExchangeL mem_ptr (Binary oldval newval)));
7493 effect(KILL cr);
7494
7495 format %{ "cmpxchgq $mem_ptr,$newval\t# "
7496 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" %}
7497 opcode(0x0F, 0xB1);
7498 ins_encode(lock_prefix,
7499 REX_reg_mem_wide(newval, mem_ptr),
7500 OpcP, OpcS,
7501 reg_mem(newval, mem_ptr) // lock cmpxchg
7502 );
7503 ins_pipe( pipe_cmpxchg );
7504 %}
7505
7506 instruct compareAndExchangeN(
7507 memory mem_ptr,
7508 rax_RegN oldval, rRegN newval,
7509 rFlagsReg cr) %{
7510 match(Set oldval (CompareAndExchangeN mem_ptr (Binary oldval newval)));
7511 effect(KILL cr);
7512
7513 format %{ "cmpxchgl $mem_ptr,$newval\t# "
7514 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" %}
7515 opcode(0x0F, 0xB1);
7516 ins_encode(lock_prefix,
7517 REX_reg_mem(newval, mem_ptr),
7518 OpcP, OpcS,
7519 reg_mem(newval, mem_ptr) // lock cmpxchg
7520 );
7521 ins_pipe( pipe_cmpxchg );
7522 %}
7523
7524 instruct compareAndExchangeP(
7525 memory mem_ptr,
7526 rax_RegP oldval, rRegP newval,
7527 rFlagsReg cr)
7528 %{
7529 predicate(VM_Version::supports_cx8());
7530 match(Set oldval (CompareAndExchangeP mem_ptr (Binary oldval newval)));
7531 effect(KILL cr);
7532
7533 format %{ "cmpxchgq $mem_ptr,$newval\t# "
7534 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" %}
7535 opcode(0x0F, 0xB1);
7536 ins_encode(lock_prefix,
7537 REX_reg_mem_wide(newval, mem_ptr),
7538 OpcP, OpcS,
7539 reg_mem(newval, mem_ptr) // lock cmpxchg
7540 );
7541 ins_pipe( pipe_cmpxchg );
7542 %}
7543
7544 instruct xaddB_no_res( memory mem, Universe dummy, immI add, rFlagsReg cr) %{
7545 predicate(n->as_LoadStore()->result_not_used());
7546 match(Set dummy (GetAndAddB mem add));
7547 effect(KILL cr);
7548 format %{ "ADDB [$mem],$add" %}
7549 ins_encode %{
7550 if (os::is_MP()) { __ lock(); }
7551 __ addb($mem$$Address, $add$$constant);
7552 %}
7553 ins_pipe( pipe_cmpxchg );
7554 %}
7555
7556 instruct xaddB( memory mem, rRegI newval, rFlagsReg cr) %{
7557 match(Set newval (GetAndAddB mem newval));
7558 effect(KILL cr);
7559 format %{ "XADDB [$mem],$newval" %}
7560 ins_encode %{
7561 if (os::is_MP()) { __ lock(); }
7562 __ xaddb($mem$$Address, $newval$$Register);
7563 %}
7564 ins_pipe( pipe_cmpxchg );
7565 %}
7566
7567 instruct xaddS_no_res( memory mem, Universe dummy, immI add, rFlagsReg cr) %{
7568 predicate(n->as_LoadStore()->result_not_used());
7569 match(Set dummy (GetAndAddS mem add));
7570 effect(KILL cr);
7571 format %{ "ADDW [$mem],$add" %}
7572 ins_encode %{
7573 if (os::is_MP()) { __ lock(); }
7574 __ addw($mem$$Address, $add$$constant);
7575 %}
7576 ins_pipe( pipe_cmpxchg );
7577 %}
7578
7579 instruct xaddS( memory mem, rRegI newval, rFlagsReg cr) %{
7580 match(Set newval (GetAndAddS mem newval));
7581 effect(KILL cr);
7582 format %{ "XADDW [$mem],$newval" %}
7583 ins_encode %{
7584 if (os::is_MP()) { __ lock(); }
7585 __ xaddw($mem$$Address, $newval$$Register);
7586 %}
7587 ins_pipe( pipe_cmpxchg );
7588 %}
7589
7590 instruct xaddI_no_res( memory mem, Universe dummy, immI add, rFlagsReg cr) %{
7591 predicate(n->as_LoadStore()->result_not_used());
7592 match(Set dummy (GetAndAddI mem add));
7593 effect(KILL cr);
7594 format %{ "ADDL [$mem],$add" %}
7595 ins_encode %{
7596 if (os::is_MP()) { __ lock(); }
7597 __ addl($mem$$Address, $add$$constant);
7598 %}
7599 ins_pipe( pipe_cmpxchg );
7600 %}
7601
7602 instruct xaddI( memory mem, rRegI newval, rFlagsReg cr) %{
7603 match(Set newval (GetAndAddI mem newval));
7604 effect(KILL cr);
7605 format %{ "XADDL [$mem],$newval" %}
7606 ins_encode %{
7607 if (os::is_MP()) { __ lock(); }
7608 __ xaddl($mem$$Address, $newval$$Register);
7609 %}
7610 ins_pipe( pipe_cmpxchg );
7611 %}
7612
7613 instruct xaddL_no_res( memory mem, Universe dummy, immL32 add, rFlagsReg cr) %{
7614 predicate(n->as_LoadStore()->result_not_used());
7615 match(Set dummy (GetAndAddL mem add));
7616 effect(KILL cr);
7617 format %{ "ADDQ [$mem],$add" %}
7618 ins_encode %{
7619 if (os::is_MP()) { __ lock(); }
7620 __ addq($mem$$Address, $add$$constant);
7621 %}
7622 ins_pipe( pipe_cmpxchg );
7623 %}
7624
7625 instruct xaddL( memory mem, rRegL newval, rFlagsReg cr) %{
7626 match(Set newval (GetAndAddL mem newval));
7627 effect(KILL cr);
7628 format %{ "XADDQ [$mem],$newval" %}
7629 ins_encode %{
7630 if (os::is_MP()) { __ lock(); }
7631 __ xaddq($mem$$Address, $newval$$Register);
7632 %}
7633 ins_pipe( pipe_cmpxchg );
7634 %}
7635
7636 instruct xchgB( memory mem, rRegI newval) %{
7637 match(Set newval (GetAndSetB mem newval));
7638 format %{ "XCHGB $newval,[$mem]" %}
7639 ins_encode %{
7640 __ xchgb($newval$$Register, $mem$$Address);
7641 %}
7642 ins_pipe( pipe_cmpxchg );
7643 %}
7644
7645 instruct xchgS( memory mem, rRegI newval) %{
7646 match(Set newval (GetAndSetS mem newval));
7647 format %{ "XCHGW $newval,[$mem]" %}
7648 ins_encode %{
7649 __ xchgw($newval$$Register, $mem$$Address);
7650 %}
7651 ins_pipe( pipe_cmpxchg );
7652 %}
7653
7654 instruct xchgI( memory mem, rRegI newval) %{
7655 match(Set newval (GetAndSetI mem newval));
7656 format %{ "XCHGL $newval,[$mem]" %}
7657 ins_encode %{
7658 __ xchgl($newval$$Register, $mem$$Address);
7659 %}
7660 ins_pipe( pipe_cmpxchg );
7661 %}
7662
7663 instruct xchgL( memory mem, rRegL newval) %{
7664 match(Set newval (GetAndSetL mem newval));
7665 format %{ "XCHGL $newval,[$mem]" %}
7666 ins_encode %{
7667 __ xchgq($newval$$Register, $mem$$Address);
7668 %}
7669 ins_pipe( pipe_cmpxchg );
7670 %}
7671
7672 instruct xchgP( memory mem, rRegP newval) %{
7673 match(Set newval (GetAndSetP mem newval));
7674 format %{ "XCHGQ $newval,[$mem]" %}
7675 ins_encode %{
7676 __ xchgq($newval$$Register, $mem$$Address);
7677 %}
7678 ins_pipe( pipe_cmpxchg );
7679 %}
7680
7681 instruct xchgN( memory mem, rRegN newval) %{
7682 match(Set newval (GetAndSetN mem newval));
7683 format %{ "XCHGL $newval,$mem]" %}
7684 ins_encode %{
7685 __ xchgl($newval$$Register, $mem$$Address);
7686 %}
7687 ins_pipe( pipe_cmpxchg );
7688 %}
7689
7690 //----------Subtraction Instructions-------------------------------------------
7691
7692 // Integer Subtraction Instructions
7693 instruct subI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
7694 %{
7695 match(Set dst (SubI dst src));
7696 effect(KILL cr);
7697
7698 format %{ "subl $dst, $src\t# int" %}
7699 opcode(0x2B);
7700 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
7701 ins_pipe(ialu_reg_reg);
7702 %}
7703
7704 instruct subI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
7705 %{
7706 match(Set dst (SubI dst src));
7707 effect(KILL cr);
7708
7709 format %{ "subl $dst, $src\t# int" %}
7710 opcode(0x81, 0x05); /* Opcode 81 /5 */
7711 ins_encode(OpcSErm(dst, src), Con8or32(src));
7712 ins_pipe(ialu_reg);
7713 %}
7714
7715 instruct subI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
7716 %{
7717 match(Set dst (SubI dst (LoadI src)));
7718 effect(KILL cr);
7719
7720 ins_cost(125);
7721 format %{ "subl $dst, $src\t# int" %}
7722 opcode(0x2B);
7723 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
7724 ins_pipe(ialu_reg_mem);
7725 %}
7726
7727 instruct subI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
7728 %{
7729 match(Set dst (StoreI dst (SubI (LoadI dst) src)));
7730 effect(KILL cr);
7731
7732 ins_cost(150);
7733 format %{ "subl $dst, $src\t# int" %}
7734 opcode(0x29); /* Opcode 29 /r */
7735 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
7736 ins_pipe(ialu_mem_reg);
7737 %}
7738
7739 instruct subI_mem_imm(memory dst, immI src, rFlagsReg cr)
7740 %{
7741 match(Set dst (StoreI dst (SubI (LoadI dst) src)));
7742 effect(KILL cr);
7743
7744 ins_cost(125); // XXX
7745 format %{ "subl $dst, $src\t# int" %}
7746 opcode(0x81); /* Opcode 81 /5 id */
7747 ins_encode(REX_mem(dst), OpcSE(src), RM_opc_mem(0x05, dst), Con8or32(src));
7748 ins_pipe(ialu_mem_imm);
7749 %}
7750
7751 instruct subL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
7752 %{
7753 match(Set dst (SubL dst src));
7754 effect(KILL cr);
7755
7756 format %{ "subq $dst, $src\t# long" %}
7757 opcode(0x2B);
7758 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
7759 ins_pipe(ialu_reg_reg);
7760 %}
7761
7762 instruct subL_rReg_imm(rRegI dst, immL32 src, rFlagsReg cr)
7763 %{
7764 match(Set dst (SubL dst src));
7765 effect(KILL cr);
7766
7767 format %{ "subq $dst, $src\t# long" %}
7768 opcode(0x81, 0x05); /* Opcode 81 /5 */
7769 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
7770 ins_pipe(ialu_reg);
7771 %}
7772
7773 instruct subL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
7774 %{
7775 match(Set dst (SubL dst (LoadL src)));
7776 effect(KILL cr);
7777
7778 ins_cost(125);
7779 format %{ "subq $dst, $src\t# long" %}
7780 opcode(0x2B);
7781 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
7782 ins_pipe(ialu_reg_mem);
7783 %}
7784
7785 instruct subL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
7786 %{
7787 match(Set dst (StoreL dst (SubL (LoadL dst) src)));
7788 effect(KILL cr);
7789
7790 ins_cost(150);
7791 format %{ "subq $dst, $src\t# long" %}
7792 opcode(0x29); /* Opcode 29 /r */
7793 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
7794 ins_pipe(ialu_mem_reg);
7795 %}
7796
7797 instruct subL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
7798 %{
7799 match(Set dst (StoreL dst (SubL (LoadL dst) src)));
7800 effect(KILL cr);
7801
7802 ins_cost(125); // XXX
7803 format %{ "subq $dst, $src\t# long" %}
7804 opcode(0x81); /* Opcode 81 /5 id */
7805 ins_encode(REX_mem_wide(dst),
7806 OpcSE(src), RM_opc_mem(0x05, dst), Con8or32(src));
7807 ins_pipe(ialu_mem_imm);
7808 %}
7809
7810 // Subtract from a pointer
7811 // XXX hmpf???
7812 instruct subP_rReg(rRegP dst, rRegI src, immI0 zero, rFlagsReg cr)
7813 %{
7814 match(Set dst (AddP dst (SubI zero src)));
7815 effect(KILL cr);
7816
7817 format %{ "subq $dst, $src\t# ptr - int" %}
7818 opcode(0x2B);
7819 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
7820 ins_pipe(ialu_reg_reg);
7821 %}
7822
7823 instruct negI_rReg(rRegI dst, immI0 zero, rFlagsReg cr)
7824 %{
7825 match(Set dst (SubI zero dst));
7826 effect(KILL cr);
7827
7828 format %{ "negl $dst\t# int" %}
7829 opcode(0xF7, 0x03); // Opcode F7 /3
7830 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
7831 ins_pipe(ialu_reg);
7832 %}
7833
7834 instruct negI_mem(memory dst, immI0 zero, rFlagsReg cr)
7835 %{
7836 match(Set dst (StoreI dst (SubI zero (LoadI dst))));
7837 effect(KILL cr);
7838
7839 format %{ "negl $dst\t# int" %}
7840 opcode(0xF7, 0x03); // Opcode F7 /3
7841 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
7842 ins_pipe(ialu_reg);
7843 %}
7844
7845 instruct negL_rReg(rRegL dst, immL0 zero, rFlagsReg cr)
7846 %{
7847 match(Set dst (SubL zero dst));
7848 effect(KILL cr);
7849
7850 format %{ "negq $dst\t# long" %}
7851 opcode(0xF7, 0x03); // Opcode F7 /3
7852 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
7853 ins_pipe(ialu_reg);
7854 %}
7855
7856 instruct negL_mem(memory dst, immL0 zero, rFlagsReg cr)
7857 %{
7858 match(Set dst (StoreL dst (SubL zero (LoadL dst))));
7859 effect(KILL cr);
7860
7861 format %{ "negq $dst\t# long" %}
7862 opcode(0xF7, 0x03); // Opcode F7 /3
7863 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
7864 ins_pipe(ialu_reg);
7865 %}
7866
7867 //----------Multiplication/Division Instructions-------------------------------
7868 // Integer Multiplication Instructions
7869 // Multiply Register
7870
7871 instruct mulI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
7872 %{
7873 match(Set dst (MulI dst src));
7874 effect(KILL cr);
7875
7876 ins_cost(300);
7877 format %{ "imull $dst, $src\t# int" %}
7878 opcode(0x0F, 0xAF);
7879 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
7880 ins_pipe(ialu_reg_reg_alu0);
7881 %}
7882
7883 instruct mulI_rReg_imm(rRegI dst, rRegI src, immI imm, rFlagsReg cr)
7884 %{
7885 match(Set dst (MulI src imm));
7886 effect(KILL cr);
7887
7888 ins_cost(300);
7889 format %{ "imull $dst, $src, $imm\t# int" %}
7890 opcode(0x69); /* 69 /r id */
7891 ins_encode(REX_reg_reg(dst, src),
7892 OpcSE(imm), reg_reg(dst, src), Con8or32(imm));
7893 ins_pipe(ialu_reg_reg_alu0);
7894 %}
7895
7896 instruct mulI_mem(rRegI dst, memory src, rFlagsReg cr)
7897 %{
7898 match(Set dst (MulI dst (LoadI src)));
7899 effect(KILL cr);
7900
7901 ins_cost(350);
7902 format %{ "imull $dst, $src\t# int" %}
7903 opcode(0x0F, 0xAF);
7904 ins_encode(REX_reg_mem(dst, src), OpcP, OpcS, reg_mem(dst, src));
7905 ins_pipe(ialu_reg_mem_alu0);
7906 %}
7907
7908 instruct mulI_mem_imm(rRegI dst, memory src, immI imm, rFlagsReg cr)
7909 %{
7910 match(Set dst (MulI (LoadI src) imm));
7911 effect(KILL cr);
7912
7913 ins_cost(300);
7914 format %{ "imull $dst, $src, $imm\t# int" %}
7915 opcode(0x69); /* 69 /r id */
7916 ins_encode(REX_reg_mem(dst, src),
7917 OpcSE(imm), reg_mem(dst, src), Con8or32(imm));
7918 ins_pipe(ialu_reg_mem_alu0);
7919 %}
7920
7921 instruct mulL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
7922 %{
7923 match(Set dst (MulL dst src));
7924 effect(KILL cr);
7925
7926 ins_cost(300);
7927 format %{ "imulq $dst, $src\t# long" %}
7928 opcode(0x0F, 0xAF);
7929 ins_encode(REX_reg_reg_wide(dst, src), OpcP, OpcS, reg_reg(dst, src));
7930 ins_pipe(ialu_reg_reg_alu0);
7931 %}
7932
7933 instruct mulL_rReg_imm(rRegL dst, rRegL src, immL32 imm, rFlagsReg cr)
7934 %{
7935 match(Set dst (MulL src imm));
7936 effect(KILL cr);
7937
7938 ins_cost(300);
7939 format %{ "imulq $dst, $src, $imm\t# long" %}
7940 opcode(0x69); /* 69 /r id */
7941 ins_encode(REX_reg_reg_wide(dst, src),
7942 OpcSE(imm), reg_reg(dst, src), Con8or32(imm));
7943 ins_pipe(ialu_reg_reg_alu0);
7944 %}
7945
7946 instruct mulL_mem(rRegL dst, memory src, rFlagsReg cr)
7947 %{
7948 match(Set dst (MulL dst (LoadL src)));
7949 effect(KILL cr);
7950
7951 ins_cost(350);
7952 format %{ "imulq $dst, $src\t# long" %}
7953 opcode(0x0F, 0xAF);
7954 ins_encode(REX_reg_mem_wide(dst, src), OpcP, OpcS, reg_mem(dst, src));
7955 ins_pipe(ialu_reg_mem_alu0);
7956 %}
7957
7958 instruct mulL_mem_imm(rRegL dst, memory src, immL32 imm, rFlagsReg cr)
7959 %{
7960 match(Set dst (MulL (LoadL src) imm));
7961 effect(KILL cr);
7962
7963 ins_cost(300);
7964 format %{ "imulq $dst, $src, $imm\t# long" %}
7965 opcode(0x69); /* 69 /r id */
7966 ins_encode(REX_reg_mem_wide(dst, src),
7967 OpcSE(imm), reg_mem(dst, src), Con8or32(imm));
7968 ins_pipe(ialu_reg_mem_alu0);
7969 %}
7970
7971 instruct mulHiL_rReg(rdx_RegL dst, no_rax_RegL src, rax_RegL rax, rFlagsReg cr)
7972 %{
7973 match(Set dst (MulHiL src rax));
7974 effect(USE_KILL rax, KILL cr);
7975
7976 ins_cost(300);
7977 format %{ "imulq RDX:RAX, RAX, $src\t# mulhi" %}
7978 opcode(0xF7, 0x5); /* Opcode F7 /5 */
7979 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src));
7980 ins_pipe(ialu_reg_reg_alu0);
7981 %}
7982
7983 instruct divI_rReg(rax_RegI rax, rdx_RegI rdx, no_rax_rdx_RegI div,
7984 rFlagsReg cr)
7985 %{
7986 match(Set rax (DivI rax div));
7987 effect(KILL rdx, KILL cr);
7988
7989 ins_cost(30*100+10*100); // XXX
7990 format %{ "cmpl rax, 0x80000000\t# idiv\n\t"
7991 "jne,s normal\n\t"
7992 "xorl rdx, rdx\n\t"
7993 "cmpl $div, -1\n\t"
7994 "je,s done\n"
7995 "normal: cdql\n\t"
7996 "idivl $div\n"
7997 "done:" %}
7998 opcode(0xF7, 0x7); /* Opcode F7 /7 */
7999 ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div));
8000 ins_pipe(ialu_reg_reg_alu0);
8001 %}
8002
8003 instruct divL_rReg(rax_RegL rax, rdx_RegL rdx, no_rax_rdx_RegL div,
8004 rFlagsReg cr)
8005 %{
8006 match(Set rax (DivL rax div));
8007 effect(KILL rdx, KILL cr);
8008
8009 ins_cost(30*100+10*100); // XXX
8010 format %{ "movq rdx, 0x8000000000000000\t# ldiv\n\t"
8011 "cmpq rax, rdx\n\t"
8012 "jne,s normal\n\t"
8013 "xorl rdx, rdx\n\t"
8014 "cmpq $div, -1\n\t"
8015 "je,s done\n"
8016 "normal: cdqq\n\t"
8017 "idivq $div\n"
8018 "done:" %}
8019 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8020 ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div));
8021 ins_pipe(ialu_reg_reg_alu0);
8022 %}
8023
8024 // Integer DIVMOD with Register, both quotient and mod results
8025 instruct divModI_rReg_divmod(rax_RegI rax, rdx_RegI rdx, no_rax_rdx_RegI div,
8026 rFlagsReg cr)
8027 %{
8028 match(DivModI rax div);
8029 effect(KILL cr);
8030
8031 ins_cost(30*100+10*100); // XXX
8032 format %{ "cmpl rax, 0x80000000\t# idiv\n\t"
8033 "jne,s normal\n\t"
8034 "xorl rdx, rdx\n\t"
8035 "cmpl $div, -1\n\t"
8036 "je,s done\n"
8037 "normal: cdql\n\t"
8038 "idivl $div\n"
8039 "done:" %}
8040 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8041 ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div));
8042 ins_pipe(pipe_slow);
8043 %}
8044
8045 // Long DIVMOD with Register, both quotient and mod results
8046 instruct divModL_rReg_divmod(rax_RegL rax, rdx_RegL rdx, no_rax_rdx_RegL div,
8047 rFlagsReg cr)
8048 %{
8049 match(DivModL rax div);
8050 effect(KILL cr);
8051
8052 ins_cost(30*100+10*100); // XXX
8053 format %{ "movq rdx, 0x8000000000000000\t# ldiv\n\t"
8054 "cmpq rax, rdx\n\t"
8055 "jne,s normal\n\t"
8056 "xorl rdx, rdx\n\t"
8057 "cmpq $div, -1\n\t"
8058 "je,s done\n"
8059 "normal: cdqq\n\t"
8060 "idivq $div\n"
8061 "done:" %}
8062 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8063 ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div));
8064 ins_pipe(pipe_slow);
8065 %}
8066
8067 //----------- DivL-By-Constant-Expansions--------------------------------------
8068 // DivI cases are handled by the compiler
8069
8070 // Magic constant, reciprocal of 10
8071 instruct loadConL_0x6666666666666667(rRegL dst)
8072 %{
8073 effect(DEF dst);
8074
8075 format %{ "movq $dst, #0x666666666666667\t# Used in div-by-10" %}
8076 ins_encode(load_immL(dst, 0x6666666666666667));
8077 ins_pipe(ialu_reg);
8078 %}
8079
8080 instruct mul_hi(rdx_RegL dst, no_rax_RegL src, rax_RegL rax, rFlagsReg cr)
8081 %{
8082 effect(DEF dst, USE src, USE_KILL rax, KILL cr);
8083
8084 format %{ "imulq rdx:rax, rax, $src\t# Used in div-by-10" %}
8085 opcode(0xF7, 0x5); /* Opcode F7 /5 */
8086 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src));
8087 ins_pipe(ialu_reg_reg_alu0);
8088 %}
8089
8090 instruct sarL_rReg_63(rRegL dst, rFlagsReg cr)
8091 %{
8092 effect(USE_DEF dst, KILL cr);
8093
8094 format %{ "sarq $dst, #63\t# Used in div-by-10" %}
8095 opcode(0xC1, 0x7); /* C1 /7 ib */
8096 ins_encode(reg_opc_imm_wide(dst, 0x3F));
8097 ins_pipe(ialu_reg);
8098 %}
8099
8100 instruct sarL_rReg_2(rRegL dst, rFlagsReg cr)
8101 %{
8102 effect(USE_DEF dst, KILL cr);
8103
8104 format %{ "sarq $dst, #2\t# Used in div-by-10" %}
8105 opcode(0xC1, 0x7); /* C1 /7 ib */
8106 ins_encode(reg_opc_imm_wide(dst, 0x2));
8107 ins_pipe(ialu_reg);
8108 %}
8109
8110 instruct divL_10(rdx_RegL dst, no_rax_RegL src, immL10 div)
8111 %{
8112 match(Set dst (DivL src div));
8113
8114 ins_cost((5+8)*100);
8115 expand %{
8116 rax_RegL rax; // Killed temp
8117 rFlagsReg cr; // Killed
8118 loadConL_0x6666666666666667(rax); // movq rax, 0x6666666666666667
8119 mul_hi(dst, src, rax, cr); // mulq rdx:rax <= rax * $src
8120 sarL_rReg_63(src, cr); // sarq src, 63
8121 sarL_rReg_2(dst, cr); // sarq rdx, 2
8122 subL_rReg(dst, src, cr); // subl rdx, src
8123 %}
8124 %}
8125
8126 //-----------------------------------------------------------------------------
8127
8128 instruct modI_rReg(rdx_RegI rdx, rax_RegI rax, no_rax_rdx_RegI div,
8129 rFlagsReg cr)
8130 %{
8131 match(Set rdx (ModI rax div));
8132 effect(KILL rax, KILL cr);
8133
8134 ins_cost(300); // XXX
8135 format %{ "cmpl rax, 0x80000000\t# irem\n\t"
8136 "jne,s normal\n\t"
8137 "xorl rdx, rdx\n\t"
8138 "cmpl $div, -1\n\t"
8139 "je,s done\n"
8140 "normal: cdql\n\t"
8141 "idivl $div\n"
8142 "done:" %}
8143 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8144 ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div));
8145 ins_pipe(ialu_reg_reg_alu0);
8146 %}
8147
8148 instruct modL_rReg(rdx_RegL rdx, rax_RegL rax, no_rax_rdx_RegL div,
8149 rFlagsReg cr)
8150 %{
8151 match(Set rdx (ModL rax div));
8152 effect(KILL rax, KILL cr);
8153
8154 ins_cost(300); // XXX
8155 format %{ "movq rdx, 0x8000000000000000\t# lrem\n\t"
8156 "cmpq rax, rdx\n\t"
8157 "jne,s normal\n\t"
8158 "xorl rdx, rdx\n\t"
8159 "cmpq $div, -1\n\t"
8160 "je,s done\n"
8161 "normal: cdqq\n\t"
8162 "idivq $div\n"
8163 "done:" %}
8164 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8165 ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div));
8166 ins_pipe(ialu_reg_reg_alu0);
8167 %}
8168
8169 // Integer Shift Instructions
8170 // Shift Left by one
8171 instruct salI_rReg_1(rRegI dst, immI1 shift, rFlagsReg cr)
8172 %{
8173 match(Set dst (LShiftI dst shift));
8174 effect(KILL cr);
8175
8176 format %{ "sall $dst, $shift" %}
8177 opcode(0xD1, 0x4); /* D1 /4 */
8178 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8179 ins_pipe(ialu_reg);
8180 %}
8181
8182 // Shift Left by one
8183 instruct salI_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8184 %{
8185 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift)));
8186 effect(KILL cr);
8187
8188 format %{ "sall $dst, $shift\t" %}
8189 opcode(0xD1, 0x4); /* D1 /4 */
8190 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8191 ins_pipe(ialu_mem_imm);
8192 %}
8193
8194 // Shift Left by 8-bit immediate
8195 instruct salI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr)
8196 %{
8197 match(Set dst (LShiftI dst shift));
8198 effect(KILL cr);
8199
8200 format %{ "sall $dst, $shift" %}
8201 opcode(0xC1, 0x4); /* C1 /4 ib */
8202 ins_encode(reg_opc_imm(dst, shift));
8203 ins_pipe(ialu_reg);
8204 %}
8205
8206 // Shift Left by 8-bit immediate
8207 instruct salI_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8208 %{
8209 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift)));
8210 effect(KILL cr);
8211
8212 format %{ "sall $dst, $shift" %}
8213 opcode(0xC1, 0x4); /* C1 /4 ib */
8214 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst), Con8or32(shift));
8215 ins_pipe(ialu_mem_imm);
8216 %}
8217
8218 // Shift Left by variable
8219 instruct salI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr)
8220 %{
8221 match(Set dst (LShiftI dst shift));
8222 effect(KILL cr);
8223
8224 format %{ "sall $dst, $shift" %}
8225 opcode(0xD3, 0x4); /* D3 /4 */
8226 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8227 ins_pipe(ialu_reg_reg);
8228 %}
8229
8230 // Shift Left by variable
8231 instruct salI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8232 %{
8233 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift)));
8234 effect(KILL cr);
8235
8236 format %{ "sall $dst, $shift" %}
8237 opcode(0xD3, 0x4); /* D3 /4 */
8238 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8239 ins_pipe(ialu_mem_reg);
8240 %}
8241
8242 // Arithmetic shift right by one
8243 instruct sarI_rReg_1(rRegI dst, immI1 shift, rFlagsReg cr)
8244 %{
8245 match(Set dst (RShiftI dst shift));
8246 effect(KILL cr);
8247
8248 format %{ "sarl $dst, $shift" %}
8249 opcode(0xD1, 0x7); /* D1 /7 */
8250 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8251 ins_pipe(ialu_reg);
8252 %}
8253
8254 // Arithmetic shift right by one
8255 instruct sarI_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8256 %{
8257 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8258 effect(KILL cr);
8259
8260 format %{ "sarl $dst, $shift" %}
8261 opcode(0xD1, 0x7); /* D1 /7 */
8262 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8263 ins_pipe(ialu_mem_imm);
8264 %}
8265
8266 // Arithmetic Shift Right by 8-bit immediate
8267 instruct sarI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr)
8268 %{
8269 match(Set dst (RShiftI dst shift));
8270 effect(KILL cr);
8271
8272 format %{ "sarl $dst, $shift" %}
8273 opcode(0xC1, 0x7); /* C1 /7 ib */
8274 ins_encode(reg_opc_imm(dst, shift));
8275 ins_pipe(ialu_mem_imm);
8276 %}
8277
8278 // Arithmetic Shift Right by 8-bit immediate
8279 instruct sarI_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8280 %{
8281 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8282 effect(KILL cr);
8283
8284 format %{ "sarl $dst, $shift" %}
8285 opcode(0xC1, 0x7); /* C1 /7 ib */
8286 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst), Con8or32(shift));
8287 ins_pipe(ialu_mem_imm);
8288 %}
8289
8290 // Arithmetic Shift Right by variable
8291 instruct sarI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr)
8292 %{
8293 match(Set dst (RShiftI dst shift));
8294 effect(KILL cr);
8295
8296 format %{ "sarl $dst, $shift" %}
8297 opcode(0xD3, 0x7); /* D3 /7 */
8298 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8299 ins_pipe(ialu_reg_reg);
8300 %}
8301
8302 // Arithmetic Shift Right by variable
8303 instruct sarI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8304 %{
8305 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8306 effect(KILL cr);
8307
8308 format %{ "sarl $dst, $shift" %}
8309 opcode(0xD3, 0x7); /* D3 /7 */
8310 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8311 ins_pipe(ialu_mem_reg);
8312 %}
8313
8314 // Logical shift right by one
8315 instruct shrI_rReg_1(rRegI dst, immI1 shift, rFlagsReg cr)
8316 %{
8317 match(Set dst (URShiftI dst shift));
8318 effect(KILL cr);
8319
8320 format %{ "shrl $dst, $shift" %}
8321 opcode(0xD1, 0x5); /* D1 /5 */
8322 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8323 ins_pipe(ialu_reg);
8324 %}
8325
8326 // Logical shift right by one
8327 instruct shrI_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8328 %{
8329 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift)));
8330 effect(KILL cr);
8331
8332 format %{ "shrl $dst, $shift" %}
8333 opcode(0xD1, 0x5); /* D1 /5 */
8334 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8335 ins_pipe(ialu_mem_imm);
8336 %}
8337
8338 // Logical Shift Right by 8-bit immediate
8339 instruct shrI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr)
8340 %{
8341 match(Set dst (URShiftI dst shift));
8342 effect(KILL cr);
8343
8344 format %{ "shrl $dst, $shift" %}
8345 opcode(0xC1, 0x5); /* C1 /5 ib */
8346 ins_encode(reg_opc_imm(dst, shift));
8347 ins_pipe(ialu_reg);
8348 %}
8349
8350 // Logical Shift Right by 8-bit immediate
8351 instruct shrI_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8352 %{
8353 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift)));
8354 effect(KILL cr);
8355
8356 format %{ "shrl $dst, $shift" %}
8357 opcode(0xC1, 0x5); /* C1 /5 ib */
8358 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst), Con8or32(shift));
8359 ins_pipe(ialu_mem_imm);
8360 %}
8361
8362 // Logical Shift Right by variable
8363 instruct shrI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr)
8364 %{
8365 match(Set dst (URShiftI dst shift));
8366 effect(KILL cr);
8367
8368 format %{ "shrl $dst, $shift" %}
8369 opcode(0xD3, 0x5); /* D3 /5 */
8370 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8371 ins_pipe(ialu_reg_reg);
8372 %}
8373
8374 // Logical Shift Right by variable
8375 instruct shrI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8376 %{
8377 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift)));
8378 effect(KILL cr);
8379
8380 format %{ "shrl $dst, $shift" %}
8381 opcode(0xD3, 0x5); /* D3 /5 */
8382 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8383 ins_pipe(ialu_mem_reg);
8384 %}
8385
8386 // Long Shift Instructions
8387 // Shift Left by one
8388 instruct salL_rReg_1(rRegL dst, immI1 shift, rFlagsReg cr)
8389 %{
8390 match(Set dst (LShiftL dst shift));
8391 effect(KILL cr);
8392
8393 format %{ "salq $dst, $shift" %}
8394 opcode(0xD1, 0x4); /* D1 /4 */
8395 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8396 ins_pipe(ialu_reg);
8397 %}
8398
8399 // Shift Left by one
8400 instruct salL_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8401 %{
8402 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift)));
8403 effect(KILL cr);
8404
8405 format %{ "salq $dst, $shift" %}
8406 opcode(0xD1, 0x4); /* D1 /4 */
8407 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8408 ins_pipe(ialu_mem_imm);
8409 %}
8410
8411 // Shift Left by 8-bit immediate
8412 instruct salL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr)
8413 %{
8414 match(Set dst (LShiftL dst shift));
8415 effect(KILL cr);
8416
8417 format %{ "salq $dst, $shift" %}
8418 opcode(0xC1, 0x4); /* C1 /4 ib */
8419 ins_encode(reg_opc_imm_wide(dst, shift));
8420 ins_pipe(ialu_reg);
8421 %}
8422
8423 // Shift Left by 8-bit immediate
8424 instruct salL_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8425 %{
8426 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift)));
8427 effect(KILL cr);
8428
8429 format %{ "salq $dst, $shift" %}
8430 opcode(0xC1, 0x4); /* C1 /4 ib */
8431 ins_encode(REX_mem_wide(dst), OpcP,
8432 RM_opc_mem(secondary, dst), Con8or32(shift));
8433 ins_pipe(ialu_mem_imm);
8434 %}
8435
8436 // Shift Left by variable
8437 instruct salL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr)
8438 %{
8439 match(Set dst (LShiftL dst shift));
8440 effect(KILL cr);
8441
8442 format %{ "salq $dst, $shift" %}
8443 opcode(0xD3, 0x4); /* D3 /4 */
8444 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8445 ins_pipe(ialu_reg_reg);
8446 %}
8447
8448 // Shift Left by variable
8449 instruct salL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8450 %{
8451 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift)));
8452 effect(KILL cr);
8453
8454 format %{ "salq $dst, $shift" %}
8455 opcode(0xD3, 0x4); /* D3 /4 */
8456 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8457 ins_pipe(ialu_mem_reg);
8458 %}
8459
8460 // Arithmetic shift right by one
8461 instruct sarL_rReg_1(rRegL dst, immI1 shift, rFlagsReg cr)
8462 %{
8463 match(Set dst (RShiftL dst shift));
8464 effect(KILL cr);
8465
8466 format %{ "sarq $dst, $shift" %}
8467 opcode(0xD1, 0x7); /* D1 /7 */
8468 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8469 ins_pipe(ialu_reg);
8470 %}
8471
8472 // Arithmetic shift right by one
8473 instruct sarL_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8474 %{
8475 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift)));
8476 effect(KILL cr);
8477
8478 format %{ "sarq $dst, $shift" %}
8479 opcode(0xD1, 0x7); /* D1 /7 */
8480 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8481 ins_pipe(ialu_mem_imm);
8482 %}
8483
8484 // Arithmetic Shift Right by 8-bit immediate
8485 instruct sarL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr)
8486 %{
8487 match(Set dst (RShiftL dst shift));
8488 effect(KILL cr);
8489
8490 format %{ "sarq $dst, $shift" %}
8491 opcode(0xC1, 0x7); /* C1 /7 ib */
8492 ins_encode(reg_opc_imm_wide(dst, shift));
8493 ins_pipe(ialu_mem_imm);
8494 %}
8495
8496 // Arithmetic Shift Right by 8-bit immediate
8497 instruct sarL_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8498 %{
8499 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift)));
8500 effect(KILL cr);
8501
8502 format %{ "sarq $dst, $shift" %}
8503 opcode(0xC1, 0x7); /* C1 /7 ib */
8504 ins_encode(REX_mem_wide(dst), OpcP,
8505 RM_opc_mem(secondary, dst), Con8or32(shift));
8506 ins_pipe(ialu_mem_imm);
8507 %}
8508
8509 // Arithmetic Shift Right by variable
8510 instruct sarL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr)
8511 %{
8512 match(Set dst (RShiftL dst shift));
8513 effect(KILL cr);
8514
8515 format %{ "sarq $dst, $shift" %}
8516 opcode(0xD3, 0x7); /* D3 /7 */
8517 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8518 ins_pipe(ialu_reg_reg);
8519 %}
8520
8521 // Arithmetic Shift Right by variable
8522 instruct sarL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8523 %{
8524 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift)));
8525 effect(KILL cr);
8526
8527 format %{ "sarq $dst, $shift" %}
8528 opcode(0xD3, 0x7); /* D3 /7 */
8529 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8530 ins_pipe(ialu_mem_reg);
8531 %}
8532
8533 // Logical shift right by one
8534 instruct shrL_rReg_1(rRegL dst, immI1 shift, rFlagsReg cr)
8535 %{
8536 match(Set dst (URShiftL dst shift));
8537 effect(KILL cr);
8538
8539 format %{ "shrq $dst, $shift" %}
8540 opcode(0xD1, 0x5); /* D1 /5 */
8541 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst ));
8542 ins_pipe(ialu_reg);
8543 %}
8544
8545 // Logical shift right by one
8546 instruct shrL_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8547 %{
8548 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift)));
8549 effect(KILL cr);
8550
8551 format %{ "shrq $dst, $shift" %}
8552 opcode(0xD1, 0x5); /* D1 /5 */
8553 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8554 ins_pipe(ialu_mem_imm);
8555 %}
8556
8557 // Logical Shift Right by 8-bit immediate
8558 instruct shrL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr)
8559 %{
8560 match(Set dst (URShiftL dst shift));
8561 effect(KILL cr);
8562
8563 format %{ "shrq $dst, $shift" %}
8564 opcode(0xC1, 0x5); /* C1 /5 ib */
8565 ins_encode(reg_opc_imm_wide(dst, shift));
8566 ins_pipe(ialu_reg);
8567 %}
8568
8569
8570 // Logical Shift Right by 8-bit immediate
8571 instruct shrL_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8572 %{
8573 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift)));
8574 effect(KILL cr);
8575
8576 format %{ "shrq $dst, $shift" %}
8577 opcode(0xC1, 0x5); /* C1 /5 ib */
8578 ins_encode(REX_mem_wide(dst), OpcP,
8579 RM_opc_mem(secondary, dst), Con8or32(shift));
8580 ins_pipe(ialu_mem_imm);
8581 %}
8582
8583 // Logical Shift Right by variable
8584 instruct shrL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr)
8585 %{
8586 match(Set dst (URShiftL dst shift));
8587 effect(KILL cr);
8588
8589 format %{ "shrq $dst, $shift" %}
8590 opcode(0xD3, 0x5); /* D3 /5 */
8591 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8592 ins_pipe(ialu_reg_reg);
8593 %}
8594
8595 // Logical Shift Right by variable
8596 instruct shrL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8597 %{
8598 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift)));
8599 effect(KILL cr);
8600
8601 format %{ "shrq $dst, $shift" %}
8602 opcode(0xD3, 0x5); /* D3 /5 */
8603 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8604 ins_pipe(ialu_mem_reg);
8605 %}
8606
8607 // Logical Shift Right by 24, followed by Arithmetic Shift Left by 24.
8608 // This idiom is used by the compiler for the i2b bytecode.
8609 instruct i2b(rRegI dst, rRegI src, immI_24 twentyfour)
8610 %{
8611 match(Set dst (RShiftI (LShiftI src twentyfour) twentyfour));
8612
8613 format %{ "movsbl $dst, $src\t# i2b" %}
8614 opcode(0x0F, 0xBE);
8615 ins_encode(REX_reg_breg(dst, src), OpcP, OpcS, reg_reg(dst, src));
8616 ins_pipe(ialu_reg_reg);
8617 %}
8618
8619 // Logical Shift Right by 16, followed by Arithmetic Shift Left by 16.
8620 // This idiom is used by the compiler the i2s bytecode.
8621 instruct i2s(rRegI dst, rRegI src, immI_16 sixteen)
8622 %{
8623 match(Set dst (RShiftI (LShiftI src sixteen) sixteen));
8624
8625 format %{ "movswl $dst, $src\t# i2s" %}
8626 opcode(0x0F, 0xBF);
8627 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
8628 ins_pipe(ialu_reg_reg);
8629 %}
8630
8631 // ROL/ROR instructions
8632
8633 // ROL expand
8634 instruct rolI_rReg_imm1(rRegI dst, rFlagsReg cr) %{
8635 effect(KILL cr, USE_DEF dst);
8636
8637 format %{ "roll $dst" %}
8638 opcode(0xD1, 0x0); /* Opcode D1 /0 */
8639 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8640 ins_pipe(ialu_reg);
8641 %}
8642
8643 instruct rolI_rReg_imm8(rRegI dst, immI8 shift, rFlagsReg cr) %{
8644 effect(USE_DEF dst, USE shift, KILL cr);
8645
8646 format %{ "roll $dst, $shift" %}
8647 opcode(0xC1, 0x0); /* Opcode C1 /0 ib */
8648 ins_encode( reg_opc_imm(dst, shift) );
8649 ins_pipe(ialu_reg);
8650 %}
8651
8652 instruct rolI_rReg_CL(no_rcx_RegI dst, rcx_RegI shift, rFlagsReg cr)
8653 %{
8654 effect(USE_DEF dst, USE shift, KILL cr);
8655
8656 format %{ "roll $dst, $shift" %}
8657 opcode(0xD3, 0x0); /* Opcode D3 /0 */
8658 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8659 ins_pipe(ialu_reg_reg);
8660 %}
8661 // end of ROL expand
8662
8663 // Rotate Left by one
8664 instruct rolI_rReg_i1(rRegI dst, immI1 lshift, immI_M1 rshift, rFlagsReg cr)
8665 %{
8666 match(Set dst (OrI (LShiftI dst lshift) (URShiftI dst rshift)));
8667
8668 expand %{
8669 rolI_rReg_imm1(dst, cr);
8670 %}
8671 %}
8672
8673 // Rotate Left by 8-bit immediate
8674 instruct rolI_rReg_i8(rRegI dst, immI8 lshift, immI8 rshift, rFlagsReg cr)
8675 %{
8676 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8677 match(Set dst (OrI (LShiftI dst lshift) (URShiftI dst rshift)));
8678
8679 expand %{
8680 rolI_rReg_imm8(dst, lshift, cr);
8681 %}
8682 %}
8683
8684 // Rotate Left by variable
8685 instruct rolI_rReg_Var_C0(no_rcx_RegI dst, rcx_RegI shift, immI0 zero, rFlagsReg cr)
8686 %{
8687 match(Set dst (OrI (LShiftI dst shift) (URShiftI dst (SubI zero shift))));
8688
8689 expand %{
8690 rolI_rReg_CL(dst, shift, cr);
8691 %}
8692 %}
8693
8694 // Rotate Left by variable
8695 instruct rolI_rReg_Var_C32(no_rcx_RegI dst, rcx_RegI shift, immI_32 c32, rFlagsReg cr)
8696 %{
8697 match(Set dst (OrI (LShiftI dst shift) (URShiftI dst (SubI c32 shift))));
8698
8699 expand %{
8700 rolI_rReg_CL(dst, shift, cr);
8701 %}
8702 %}
8703
8704 // ROR expand
8705 instruct rorI_rReg_imm1(rRegI dst, rFlagsReg cr)
8706 %{
8707 effect(USE_DEF dst, KILL cr);
8708
8709 format %{ "rorl $dst" %}
8710 opcode(0xD1, 0x1); /* D1 /1 */
8711 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8712 ins_pipe(ialu_reg);
8713 %}
8714
8715 instruct rorI_rReg_imm8(rRegI dst, immI8 shift, rFlagsReg cr)
8716 %{
8717 effect(USE_DEF dst, USE shift, KILL cr);
8718
8719 format %{ "rorl $dst, $shift" %}
8720 opcode(0xC1, 0x1); /* C1 /1 ib */
8721 ins_encode(reg_opc_imm(dst, shift));
8722 ins_pipe(ialu_reg);
8723 %}
8724
8725 instruct rorI_rReg_CL(no_rcx_RegI dst, rcx_RegI shift, rFlagsReg cr)
8726 %{
8727 effect(USE_DEF dst, USE shift, KILL cr);
8728
8729 format %{ "rorl $dst, $shift" %}
8730 opcode(0xD3, 0x1); /* D3 /1 */
8731 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8732 ins_pipe(ialu_reg_reg);
8733 %}
8734 // end of ROR expand
8735
8736 // Rotate Right by one
8737 instruct rorI_rReg_i1(rRegI dst, immI1 rshift, immI_M1 lshift, rFlagsReg cr)
8738 %{
8739 match(Set dst (OrI (URShiftI dst rshift) (LShiftI dst lshift)));
8740
8741 expand %{
8742 rorI_rReg_imm1(dst, cr);
8743 %}
8744 %}
8745
8746 // Rotate Right by 8-bit immediate
8747 instruct rorI_rReg_i8(rRegI dst, immI8 rshift, immI8 lshift, rFlagsReg cr)
8748 %{
8749 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8750 match(Set dst (OrI (URShiftI dst rshift) (LShiftI dst lshift)));
8751
8752 expand %{
8753 rorI_rReg_imm8(dst, rshift, cr);
8754 %}
8755 %}
8756
8757 // Rotate Right by variable
8758 instruct rorI_rReg_Var_C0(no_rcx_RegI dst, rcx_RegI shift, immI0 zero, rFlagsReg cr)
8759 %{
8760 match(Set dst (OrI (URShiftI dst shift) (LShiftI dst (SubI zero shift))));
8761
8762 expand %{
8763 rorI_rReg_CL(dst, shift, cr);
8764 %}
8765 %}
8766
8767 // Rotate Right by variable
8768 instruct rorI_rReg_Var_C32(no_rcx_RegI dst, rcx_RegI shift, immI_32 c32, rFlagsReg cr)
8769 %{
8770 match(Set dst (OrI (URShiftI dst shift) (LShiftI dst (SubI c32 shift))));
8771
8772 expand %{
8773 rorI_rReg_CL(dst, shift, cr);
8774 %}
8775 %}
8776
8777 // for long rotate
8778 // ROL expand
8779 instruct rolL_rReg_imm1(rRegL dst, rFlagsReg cr) %{
8780 effect(USE_DEF dst, KILL cr);
8781
8782 format %{ "rolq $dst" %}
8783 opcode(0xD1, 0x0); /* Opcode D1 /0 */
8784 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8785 ins_pipe(ialu_reg);
8786 %}
8787
8788 instruct rolL_rReg_imm8(rRegL dst, immI8 shift, rFlagsReg cr) %{
8789 effect(USE_DEF dst, USE shift, KILL cr);
8790
8791 format %{ "rolq $dst, $shift" %}
8792 opcode(0xC1, 0x0); /* Opcode C1 /0 ib */
8793 ins_encode( reg_opc_imm_wide(dst, shift) );
8794 ins_pipe(ialu_reg);
8795 %}
8796
8797 instruct rolL_rReg_CL(no_rcx_RegL dst, rcx_RegI shift, rFlagsReg cr)
8798 %{
8799 effect(USE_DEF dst, USE shift, KILL cr);
8800
8801 format %{ "rolq $dst, $shift" %}
8802 opcode(0xD3, 0x0); /* Opcode D3 /0 */
8803 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8804 ins_pipe(ialu_reg_reg);
8805 %}
8806 // end of ROL expand
8807
8808 // Rotate Left by one
8809 instruct rolL_rReg_i1(rRegL dst, immI1 lshift, immI_M1 rshift, rFlagsReg cr)
8810 %{
8811 match(Set dst (OrL (LShiftL dst lshift) (URShiftL dst rshift)));
8812
8813 expand %{
8814 rolL_rReg_imm1(dst, cr);
8815 %}
8816 %}
8817
8818 // Rotate Left by 8-bit immediate
8819 instruct rolL_rReg_i8(rRegL dst, immI8 lshift, immI8 rshift, rFlagsReg cr)
8820 %{
8821 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f));
8822 match(Set dst (OrL (LShiftL dst lshift) (URShiftL dst rshift)));
8823
8824 expand %{
8825 rolL_rReg_imm8(dst, lshift, cr);
8826 %}
8827 %}
8828
8829 // Rotate Left by variable
8830 instruct rolL_rReg_Var_C0(no_rcx_RegL dst, rcx_RegI shift, immI0 zero, rFlagsReg cr)
8831 %{
8832 match(Set dst (OrL (LShiftL dst shift) (URShiftL dst (SubI zero shift))));
8833
8834 expand %{
8835 rolL_rReg_CL(dst, shift, cr);
8836 %}
8837 %}
8838
8839 // Rotate Left by variable
8840 instruct rolL_rReg_Var_C64(no_rcx_RegL dst, rcx_RegI shift, immI_64 c64, rFlagsReg cr)
8841 %{
8842 match(Set dst (OrL (LShiftL dst shift) (URShiftL dst (SubI c64 shift))));
8843
8844 expand %{
8845 rolL_rReg_CL(dst, shift, cr);
8846 %}
8847 %}
8848
8849 // ROR expand
8850 instruct rorL_rReg_imm1(rRegL dst, rFlagsReg cr)
8851 %{
8852 effect(USE_DEF dst, KILL cr);
8853
8854 format %{ "rorq $dst" %}
8855 opcode(0xD1, 0x1); /* D1 /1 */
8856 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8857 ins_pipe(ialu_reg);
8858 %}
8859
8860 instruct rorL_rReg_imm8(rRegL dst, immI8 shift, rFlagsReg cr)
8861 %{
8862 effect(USE_DEF dst, USE shift, KILL cr);
8863
8864 format %{ "rorq $dst, $shift" %}
8865 opcode(0xC1, 0x1); /* C1 /1 ib */
8866 ins_encode(reg_opc_imm_wide(dst, shift));
8867 ins_pipe(ialu_reg);
8868 %}
8869
8870 instruct rorL_rReg_CL(no_rcx_RegL dst, rcx_RegI shift, rFlagsReg cr)
8871 %{
8872 effect(USE_DEF dst, USE shift, KILL cr);
8873
8874 format %{ "rorq $dst, $shift" %}
8875 opcode(0xD3, 0x1); /* D3 /1 */
8876 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8877 ins_pipe(ialu_reg_reg);
8878 %}
8879 // end of ROR expand
8880
8881 // Rotate Right by one
8882 instruct rorL_rReg_i1(rRegL dst, immI1 rshift, immI_M1 lshift, rFlagsReg cr)
8883 %{
8884 match(Set dst (OrL (URShiftL dst rshift) (LShiftL dst lshift)));
8885
8886 expand %{
8887 rorL_rReg_imm1(dst, cr);
8888 %}
8889 %}
8890
8891 // Rotate Right by 8-bit immediate
8892 instruct rorL_rReg_i8(rRegL dst, immI8 rshift, immI8 lshift, rFlagsReg cr)
8893 %{
8894 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f));
8895 match(Set dst (OrL (URShiftL dst rshift) (LShiftL dst lshift)));
8896
8897 expand %{
8898 rorL_rReg_imm8(dst, rshift, cr);
8899 %}
8900 %}
8901
8902 // Rotate Right by variable
8903 instruct rorL_rReg_Var_C0(no_rcx_RegL dst, rcx_RegI shift, immI0 zero, rFlagsReg cr)
8904 %{
8905 match(Set dst (OrL (URShiftL dst shift) (LShiftL dst (SubI zero shift))));
8906
8907 expand %{
8908 rorL_rReg_CL(dst, shift, cr);
8909 %}
8910 %}
8911
8912 // Rotate Right by variable
8913 instruct rorL_rReg_Var_C64(no_rcx_RegL dst, rcx_RegI shift, immI_64 c64, rFlagsReg cr)
8914 %{
8915 match(Set dst (OrL (URShiftL dst shift) (LShiftL dst (SubI c64 shift))));
8916
8917 expand %{
8918 rorL_rReg_CL(dst, shift, cr);
8919 %}
8920 %}
8921
8922 // Logical Instructions
8923
8924 // Integer Logical Instructions
8925
8926 // And Instructions
8927 // And Register with Register
8928 instruct andI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
8929 %{
8930 match(Set dst (AndI dst src));
8931 effect(KILL cr);
8932
8933 format %{ "andl $dst, $src\t# int" %}
8934 opcode(0x23);
8935 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
8936 ins_pipe(ialu_reg_reg);
8937 %}
8938
8939 // And Register with Immediate 255
8940 instruct andI_rReg_imm255(rRegI dst, immI_255 src)
8941 %{
8942 match(Set dst (AndI dst src));
8943
8944 format %{ "movzbl $dst, $dst\t# int & 0xFF" %}
8945 opcode(0x0F, 0xB6);
8946 ins_encode(REX_reg_breg(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
8947 ins_pipe(ialu_reg);
8948 %}
8949
8950 // And Register with Immediate 255 and promote to long
8951 instruct andI2L_rReg_imm255(rRegL dst, rRegI src, immI_255 mask)
8952 %{
8953 match(Set dst (ConvI2L (AndI src mask)));
8954
8955 format %{ "movzbl $dst, $src\t# int & 0xFF -> long" %}
8956 opcode(0x0F, 0xB6);
8957 ins_encode(REX_reg_breg(dst, src), OpcP, OpcS, reg_reg(dst, src));
8958 ins_pipe(ialu_reg);
8959 %}
8960
8961 // And Register with Immediate 65535
8962 instruct andI_rReg_imm65535(rRegI dst, immI_65535 src)
8963 %{
8964 match(Set dst (AndI dst src));
8965
8966 format %{ "movzwl $dst, $dst\t# int & 0xFFFF" %}
8967 opcode(0x0F, 0xB7);
8968 ins_encode(REX_reg_reg(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
8969 ins_pipe(ialu_reg);
8970 %}
8971
8972 // And Register with Immediate 65535 and promote to long
8973 instruct andI2L_rReg_imm65535(rRegL dst, rRegI src, immI_65535 mask)
8974 %{
8975 match(Set dst (ConvI2L (AndI src mask)));
8976
8977 format %{ "movzwl $dst, $src\t# int & 0xFFFF -> long" %}
8978 opcode(0x0F, 0xB7);
8979 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
8980 ins_pipe(ialu_reg);
8981 %}
8982
8983 // And Register with Immediate
8984 instruct andI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
8985 %{
8986 match(Set dst (AndI dst src));
8987 effect(KILL cr);
8988
8989 format %{ "andl $dst, $src\t# int" %}
8990 opcode(0x81, 0x04); /* Opcode 81 /4 */
8991 ins_encode(OpcSErm(dst, src), Con8or32(src));
8992 ins_pipe(ialu_reg);
8993 %}
8994
8995 // And Register with Memory
8996 instruct andI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
8997 %{
8998 match(Set dst (AndI dst (LoadI src)));
8999 effect(KILL cr);
9000
9001 ins_cost(125);
9002 format %{ "andl $dst, $src\t# int" %}
9003 opcode(0x23);
9004 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
9005 ins_pipe(ialu_reg_mem);
9006 %}
9007
9008 // And Memory with Register
9009 instruct andI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
9010 %{
9011 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
9012 effect(KILL cr);
9013
9014 ins_cost(150);
9015 format %{ "andl $dst, $src\t# int" %}
9016 opcode(0x21); /* Opcode 21 /r */
9017 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
9018 ins_pipe(ialu_mem_reg);
9019 %}
9020
9021 // And Memory with Immediate
9022 instruct andI_mem_imm(memory dst, immI src, rFlagsReg cr)
9023 %{
9024 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
9025 effect(KILL cr);
9026
9027 ins_cost(125);
9028 format %{ "andl $dst, $src\t# int" %}
9029 opcode(0x81, 0x4); /* Opcode 81 /4 id */
9030 ins_encode(REX_mem(dst), OpcSE(src),
9031 RM_opc_mem(secondary, dst), Con8or32(src));
9032 ins_pipe(ialu_mem_imm);
9033 %}
9034
9035 // BMI1 instructions
9036 instruct andnI_rReg_rReg_mem(rRegI dst, rRegI src1, memory src2, immI_M1 minus_1, rFlagsReg cr) %{
9037 match(Set dst (AndI (XorI src1 minus_1) (LoadI src2)));
9038 predicate(UseBMI1Instructions);
9039 effect(KILL cr);
9040
9041 ins_cost(125);
9042 format %{ "andnl $dst, $src1, $src2" %}
9043
9044 ins_encode %{
9045 __ andnl($dst$$Register, $src1$$Register, $src2$$Address);
9046 %}
9047 ins_pipe(ialu_reg_mem);
9048 %}
9049
9050 instruct andnI_rReg_rReg_rReg(rRegI dst, rRegI src1, rRegI src2, immI_M1 minus_1, rFlagsReg cr) %{
9051 match(Set dst (AndI (XorI src1 minus_1) src2));
9052 predicate(UseBMI1Instructions);
9053 effect(KILL cr);
9054
9055 format %{ "andnl $dst, $src1, $src2" %}
9056
9057 ins_encode %{
9058 __ andnl($dst$$Register, $src1$$Register, $src2$$Register);
9059 %}
9060 ins_pipe(ialu_reg);
9061 %}
9062
9063 instruct blsiI_rReg_rReg(rRegI dst, rRegI src, immI0 imm_zero, rFlagsReg cr) %{
9064 match(Set dst (AndI (SubI imm_zero src) src));
9065 predicate(UseBMI1Instructions);
9066 effect(KILL cr);
9067
9068 format %{ "blsil $dst, $src" %}
9069
9070 ins_encode %{
9071 __ blsil($dst$$Register, $src$$Register);
9072 %}
9073 ins_pipe(ialu_reg);
9074 %}
9075
9076 instruct blsiI_rReg_mem(rRegI dst, memory src, immI0 imm_zero, rFlagsReg cr) %{
9077 match(Set dst (AndI (SubI imm_zero (LoadI src) ) (LoadI src) ));
9078 predicate(UseBMI1Instructions);
9079 effect(KILL cr);
9080
9081 ins_cost(125);
9082 format %{ "blsil $dst, $src" %}
9083
9084 ins_encode %{
9085 __ blsil($dst$$Register, $src$$Address);
9086 %}
9087 ins_pipe(ialu_reg_mem);
9088 %}
9089
9090 instruct blsmskI_rReg_mem(rRegI dst, memory src, immI_M1 minus_1, rFlagsReg cr)
9091 %{
9092 match(Set dst (XorI (AddI (LoadI src) minus_1) (LoadI src) ) );
9093 predicate(UseBMI1Instructions);
9094 effect(KILL cr);
9095
9096 ins_cost(125);
9097 format %{ "blsmskl $dst, $src" %}
9098
9099 ins_encode %{
9100 __ blsmskl($dst$$Register, $src$$Address);
9101 %}
9102 ins_pipe(ialu_reg_mem);
9103 %}
9104
9105 instruct blsmskI_rReg_rReg(rRegI dst, rRegI src, immI_M1 minus_1, rFlagsReg cr)
9106 %{
9107 match(Set dst (XorI (AddI src minus_1) src));
9108 predicate(UseBMI1Instructions);
9109 effect(KILL cr);
9110
9111 format %{ "blsmskl $dst, $src" %}
9112
9113 ins_encode %{
9114 __ blsmskl($dst$$Register, $src$$Register);
9115 %}
9116
9117 ins_pipe(ialu_reg);
9118 %}
9119
9120 instruct blsrI_rReg_rReg(rRegI dst, rRegI src, immI_M1 minus_1, rFlagsReg cr)
9121 %{
9122 match(Set dst (AndI (AddI src minus_1) src) );
9123 predicate(UseBMI1Instructions);
9124 effect(KILL cr);
9125
9126 format %{ "blsrl $dst, $src" %}
9127
9128 ins_encode %{
9129 __ blsrl($dst$$Register, $src$$Register);
9130 %}
9131
9132 ins_pipe(ialu_reg_mem);
9133 %}
9134
9135 instruct blsrI_rReg_mem(rRegI dst, memory src, immI_M1 minus_1, rFlagsReg cr)
9136 %{
9137 match(Set dst (AndI (AddI (LoadI src) minus_1) (LoadI src) ) );
9138 predicate(UseBMI1Instructions);
9139 effect(KILL cr);
9140
9141 ins_cost(125);
9142 format %{ "blsrl $dst, $src" %}
9143
9144 ins_encode %{
9145 __ blsrl($dst$$Register, $src$$Address);
9146 %}
9147
9148 ins_pipe(ialu_reg);
9149 %}
9150
9151 // Or Instructions
9152 // Or Register with Register
9153 instruct orI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
9154 %{
9155 match(Set dst (OrI dst src));
9156 effect(KILL cr);
9157
9158 format %{ "orl $dst, $src\t# int" %}
9159 opcode(0x0B);
9160 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
9161 ins_pipe(ialu_reg_reg);
9162 %}
9163
9164 // Or Register with Immediate
9165 instruct orI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
9166 %{
9167 match(Set dst (OrI dst src));
9168 effect(KILL cr);
9169
9170 format %{ "orl $dst, $src\t# int" %}
9171 opcode(0x81, 0x01); /* Opcode 81 /1 id */
9172 ins_encode(OpcSErm(dst, src), Con8or32(src));
9173 ins_pipe(ialu_reg);
9174 %}
9175
9176 // Or Register with Memory
9177 instruct orI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
9178 %{
9179 match(Set dst (OrI dst (LoadI src)));
9180 effect(KILL cr);
9181
9182 ins_cost(125);
9183 format %{ "orl $dst, $src\t# int" %}
9184 opcode(0x0B);
9185 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
9186 ins_pipe(ialu_reg_mem);
9187 %}
9188
9189 // Or Memory with Register
9190 instruct orI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
9191 %{
9192 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
9193 effect(KILL cr);
9194
9195 ins_cost(150);
9196 format %{ "orl $dst, $src\t# int" %}
9197 opcode(0x09); /* Opcode 09 /r */
9198 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
9199 ins_pipe(ialu_mem_reg);
9200 %}
9201
9202 // Or Memory with Immediate
9203 instruct orI_mem_imm(memory dst, immI src, rFlagsReg cr)
9204 %{
9205 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
9206 effect(KILL cr);
9207
9208 ins_cost(125);
9209 format %{ "orl $dst, $src\t# int" %}
9210 opcode(0x81, 0x1); /* Opcode 81 /1 id */
9211 ins_encode(REX_mem(dst), OpcSE(src),
9212 RM_opc_mem(secondary, dst), Con8or32(src));
9213 ins_pipe(ialu_mem_imm);
9214 %}
9215
9216 // Xor Instructions
9217 // Xor Register with Register
9218 instruct xorI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
9219 %{
9220 match(Set dst (XorI dst src));
9221 effect(KILL cr);
9222
9223 format %{ "xorl $dst, $src\t# int" %}
9224 opcode(0x33);
9225 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
9226 ins_pipe(ialu_reg_reg);
9227 %}
9228
9229 // Xor Register with Immediate -1
9230 instruct xorI_rReg_im1(rRegI dst, immI_M1 imm) %{
9231 match(Set dst (XorI dst imm));
9232
9233 format %{ "not $dst" %}
9234 ins_encode %{
9235 __ notl($dst$$Register);
9236 %}
9237 ins_pipe(ialu_reg);
9238 %}
9239
9240 // Xor Register with Immediate
9241 instruct xorI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
9242 %{
9243 match(Set dst (XorI dst src));
9244 effect(KILL cr);
9245
9246 format %{ "xorl $dst, $src\t# int" %}
9247 opcode(0x81, 0x06); /* Opcode 81 /6 id */
9248 ins_encode(OpcSErm(dst, src), Con8or32(src));
9249 ins_pipe(ialu_reg);
9250 %}
9251
9252 // Xor Register with Memory
9253 instruct xorI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
9254 %{
9255 match(Set dst (XorI dst (LoadI src)));
9256 effect(KILL cr);
9257
9258 ins_cost(125);
9259 format %{ "xorl $dst, $src\t# int" %}
9260 opcode(0x33);
9261 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
9262 ins_pipe(ialu_reg_mem);
9263 %}
9264
9265 // Xor Memory with Register
9266 instruct xorI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
9267 %{
9268 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
9269 effect(KILL cr);
9270
9271 ins_cost(150);
9272 format %{ "xorl $dst, $src\t# int" %}
9273 opcode(0x31); /* Opcode 31 /r */
9274 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
9275 ins_pipe(ialu_mem_reg);
9276 %}
9277
9278 // Xor Memory with Immediate
9279 instruct xorI_mem_imm(memory dst, immI src, rFlagsReg cr)
9280 %{
9281 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
9282 effect(KILL cr);
9283
9284 ins_cost(125);
9285 format %{ "xorl $dst, $src\t# int" %}
9286 opcode(0x81, 0x6); /* Opcode 81 /6 id */
9287 ins_encode(REX_mem(dst), OpcSE(src),
9288 RM_opc_mem(secondary, dst), Con8or32(src));
9289 ins_pipe(ialu_mem_imm);
9290 %}
9291
9292
9293 // Long Logical Instructions
9294
9295 // And Instructions
9296 // And Register with Register
9297 instruct andL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
9298 %{
9299 match(Set dst (AndL dst src));
9300 effect(KILL cr);
9301
9302 format %{ "andq $dst, $src\t# long" %}
9303 opcode(0x23);
9304 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
9305 ins_pipe(ialu_reg_reg);
9306 %}
9307
9308 // And Register with Immediate 255
9309 instruct andL_rReg_imm255(rRegL dst, immL_255 src)
9310 %{
9311 match(Set dst (AndL dst src));
9312
9313 format %{ "movzbq $dst, $dst\t# long & 0xFF" %}
9314 opcode(0x0F, 0xB6);
9315 ins_encode(REX_reg_reg_wide(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
9316 ins_pipe(ialu_reg);
9317 %}
9318
9319 // And Register with Immediate 65535
9320 instruct andL_rReg_imm65535(rRegL dst, immL_65535 src)
9321 %{
9322 match(Set dst (AndL dst src));
9323
9324 format %{ "movzwq $dst, $dst\t# long & 0xFFFF" %}
9325 opcode(0x0F, 0xB7);
9326 ins_encode(REX_reg_reg_wide(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
9327 ins_pipe(ialu_reg);
9328 %}
9329
9330 // And Register with Immediate
9331 instruct andL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
9332 %{
9333 match(Set dst (AndL dst src));
9334 effect(KILL cr);
9335
9336 format %{ "andq $dst, $src\t# long" %}
9337 opcode(0x81, 0x04); /* Opcode 81 /4 */
9338 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
9339 ins_pipe(ialu_reg);
9340 %}
9341
9342 // And Register with Memory
9343 instruct andL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
9344 %{
9345 match(Set dst (AndL dst (LoadL src)));
9346 effect(KILL cr);
9347
9348 ins_cost(125);
9349 format %{ "andq $dst, $src\t# long" %}
9350 opcode(0x23);
9351 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
9352 ins_pipe(ialu_reg_mem);
9353 %}
9354
9355 // And Memory with Register
9356 instruct andL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
9357 %{
9358 match(Set dst (StoreL dst (AndL (LoadL dst) src)));
9359 effect(KILL cr);
9360
9361 ins_cost(150);
9362 format %{ "andq $dst, $src\t# long" %}
9363 opcode(0x21); /* Opcode 21 /r */
9364 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
9365 ins_pipe(ialu_mem_reg);
9366 %}
9367
9368 // And Memory with Immediate
9369 instruct andL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
9370 %{
9371 match(Set dst (StoreL dst (AndL (LoadL dst) src)));
9372 effect(KILL cr);
9373
9374 ins_cost(125);
9375 format %{ "andq $dst, $src\t# long" %}
9376 opcode(0x81, 0x4); /* Opcode 81 /4 id */
9377 ins_encode(REX_mem_wide(dst), OpcSE(src),
9378 RM_opc_mem(secondary, dst), Con8or32(src));
9379 ins_pipe(ialu_mem_imm);
9380 %}
9381
9382 // BMI1 instructions
9383 instruct andnL_rReg_rReg_mem(rRegL dst, rRegL src1, memory src2, immL_M1 minus_1, rFlagsReg cr) %{
9384 match(Set dst (AndL (XorL src1 minus_1) (LoadL src2)));
9385 predicate(UseBMI1Instructions);
9386 effect(KILL cr);
9387
9388 ins_cost(125);
9389 format %{ "andnq $dst, $src1, $src2" %}
9390
9391 ins_encode %{
9392 __ andnq($dst$$Register, $src1$$Register, $src2$$Address);
9393 %}
9394 ins_pipe(ialu_reg_mem);
9395 %}
9396
9397 instruct andnL_rReg_rReg_rReg(rRegL dst, rRegL src1, rRegL src2, immL_M1 minus_1, rFlagsReg cr) %{
9398 match(Set dst (AndL (XorL src1 minus_1) src2));
9399 predicate(UseBMI1Instructions);
9400 effect(KILL cr);
9401
9402 format %{ "andnq $dst, $src1, $src2" %}
9403
9404 ins_encode %{
9405 __ andnq($dst$$Register, $src1$$Register, $src2$$Register);
9406 %}
9407 ins_pipe(ialu_reg_mem);
9408 %}
9409
9410 instruct blsiL_rReg_rReg(rRegL dst, rRegL src, immL0 imm_zero, rFlagsReg cr) %{
9411 match(Set dst (AndL (SubL imm_zero src) src));
9412 predicate(UseBMI1Instructions);
9413 effect(KILL cr);
9414
9415 format %{ "blsiq $dst, $src" %}
9416
9417 ins_encode %{
9418 __ blsiq($dst$$Register, $src$$Register);
9419 %}
9420 ins_pipe(ialu_reg);
9421 %}
9422
9423 instruct blsiL_rReg_mem(rRegL dst, memory src, immL0 imm_zero, rFlagsReg cr) %{
9424 match(Set dst (AndL (SubL imm_zero (LoadL src) ) (LoadL src) ));
9425 predicate(UseBMI1Instructions);
9426 effect(KILL cr);
9427
9428 ins_cost(125);
9429 format %{ "blsiq $dst, $src" %}
9430
9431 ins_encode %{
9432 __ blsiq($dst$$Register, $src$$Address);
9433 %}
9434 ins_pipe(ialu_reg_mem);
9435 %}
9436
9437 instruct blsmskL_rReg_mem(rRegL dst, memory src, immL_M1 minus_1, rFlagsReg cr)
9438 %{
9439 match(Set dst (XorL (AddL (LoadL src) minus_1) (LoadL src) ) );
9440 predicate(UseBMI1Instructions);
9441 effect(KILL cr);
9442
9443 ins_cost(125);
9444 format %{ "blsmskq $dst, $src" %}
9445
9446 ins_encode %{
9447 __ blsmskq($dst$$Register, $src$$Address);
9448 %}
9449 ins_pipe(ialu_reg_mem);
9450 %}
9451
9452 instruct blsmskL_rReg_rReg(rRegL dst, rRegL src, immL_M1 minus_1, rFlagsReg cr)
9453 %{
9454 match(Set dst (XorL (AddL src minus_1) src));
9455 predicate(UseBMI1Instructions);
9456 effect(KILL cr);
9457
9458 format %{ "blsmskq $dst, $src" %}
9459
9460 ins_encode %{
9461 __ blsmskq($dst$$Register, $src$$Register);
9462 %}
9463
9464 ins_pipe(ialu_reg);
9465 %}
9466
9467 instruct blsrL_rReg_rReg(rRegL dst, rRegL src, immL_M1 minus_1, rFlagsReg cr)
9468 %{
9469 match(Set dst (AndL (AddL src minus_1) src) );
9470 predicate(UseBMI1Instructions);
9471 effect(KILL cr);
9472
9473 format %{ "blsrq $dst, $src" %}
9474
9475 ins_encode %{
9476 __ blsrq($dst$$Register, $src$$Register);
9477 %}
9478
9479 ins_pipe(ialu_reg);
9480 %}
9481
9482 instruct blsrL_rReg_mem(rRegL dst, memory src, immL_M1 minus_1, rFlagsReg cr)
9483 %{
9484 match(Set dst (AndL (AddL (LoadL src) minus_1) (LoadL src)) );
9485 predicate(UseBMI1Instructions);
9486 effect(KILL cr);
9487
9488 ins_cost(125);
9489 format %{ "blsrq $dst, $src" %}
9490
9491 ins_encode %{
9492 __ blsrq($dst$$Register, $src$$Address);
9493 %}
9494
9495 ins_pipe(ialu_reg);
9496 %}
9497
9498 // Or Instructions
9499 // Or Register with Register
9500 instruct orL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
9501 %{
9502 match(Set dst (OrL dst src));
9503 effect(KILL cr);
9504
9505 format %{ "orq $dst, $src\t# long" %}
9506 opcode(0x0B);
9507 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
9508 ins_pipe(ialu_reg_reg);
9509 %}
9510
9511 // Use any_RegP to match R15 (TLS register) without spilling.
9512 instruct orL_rReg_castP2X(rRegL dst, any_RegP src, rFlagsReg cr) %{
9513 match(Set dst (OrL dst (CastP2X src)));
9514 effect(KILL cr);
9515
9516 format %{ "orq $dst, $src\t# long" %}
9517 opcode(0x0B);
9518 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
9519 ins_pipe(ialu_reg_reg);
9520 %}
9521
9522
9523 // Or Register with Immediate
9524 instruct orL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
9525 %{
9526 match(Set dst (OrL dst src));
9527 effect(KILL cr);
9528
9529 format %{ "orq $dst, $src\t# long" %}
9530 opcode(0x81, 0x01); /* Opcode 81 /1 id */
9531 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
9532 ins_pipe(ialu_reg);
9533 %}
9534
9535 // Or Register with Memory
9536 instruct orL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
9537 %{
9538 match(Set dst (OrL dst (LoadL src)));
9539 effect(KILL cr);
9540
9541 ins_cost(125);
9542 format %{ "orq $dst, $src\t# long" %}
9543 opcode(0x0B);
9544 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
9545 ins_pipe(ialu_reg_mem);
9546 %}
9547
9548 // Or Memory with Register
9549 instruct orL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
9550 %{
9551 match(Set dst (StoreL dst (OrL (LoadL dst) src)));
9552 effect(KILL cr);
9553
9554 ins_cost(150);
9555 format %{ "orq $dst, $src\t# long" %}
9556 opcode(0x09); /* Opcode 09 /r */
9557 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
9558 ins_pipe(ialu_mem_reg);
9559 %}
9560
9561 // Or Memory with Immediate
9562 instruct orL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
9563 %{
9564 match(Set dst (StoreL dst (OrL (LoadL dst) src)));
9565 effect(KILL cr);
9566
9567 ins_cost(125);
9568 format %{ "orq $dst, $src\t# long" %}
9569 opcode(0x81, 0x1); /* Opcode 81 /1 id */
9570 ins_encode(REX_mem_wide(dst), OpcSE(src),
9571 RM_opc_mem(secondary, dst), Con8or32(src));
9572 ins_pipe(ialu_mem_imm);
9573 %}
9574
9575 // Xor Instructions
9576 // Xor Register with Register
9577 instruct xorL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
9578 %{
9579 match(Set dst (XorL dst src));
9580 effect(KILL cr);
9581
9582 format %{ "xorq $dst, $src\t# long" %}
9583 opcode(0x33);
9584 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
9585 ins_pipe(ialu_reg_reg);
9586 %}
9587
9588 // Xor Register with Immediate -1
9589 instruct xorL_rReg_im1(rRegL dst, immL_M1 imm) %{
9590 match(Set dst (XorL dst imm));
9591
9592 format %{ "notq $dst" %}
9593 ins_encode %{
9594 __ notq($dst$$Register);
9595 %}
9596 ins_pipe(ialu_reg);
9597 %}
9598
9599 // Xor Register with Immediate
9600 instruct xorL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
9601 %{
9602 match(Set dst (XorL dst src));
9603 effect(KILL cr);
9604
9605 format %{ "xorq $dst, $src\t# long" %}
9606 opcode(0x81, 0x06); /* Opcode 81 /6 id */
9607 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
9608 ins_pipe(ialu_reg);
9609 %}
9610
9611 // Xor Register with Memory
9612 instruct xorL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
9613 %{
9614 match(Set dst (XorL dst (LoadL src)));
9615 effect(KILL cr);
9616
9617 ins_cost(125);
9618 format %{ "xorq $dst, $src\t# long" %}
9619 opcode(0x33);
9620 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
9621 ins_pipe(ialu_reg_mem);
9622 %}
9623
9624 // Xor Memory with Register
9625 instruct xorL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
9626 %{
9627 match(Set dst (StoreL dst (XorL (LoadL dst) src)));
9628 effect(KILL cr);
9629
9630 ins_cost(150);
9631 format %{ "xorq $dst, $src\t# long" %}
9632 opcode(0x31); /* Opcode 31 /r */
9633 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
9634 ins_pipe(ialu_mem_reg);
9635 %}
9636
9637 // Xor Memory with Immediate
9638 instruct xorL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
9639 %{
9640 match(Set dst (StoreL dst (XorL (LoadL dst) src)));
9641 effect(KILL cr);
9642
9643 ins_cost(125);
9644 format %{ "xorq $dst, $src\t# long" %}
9645 opcode(0x81, 0x6); /* Opcode 81 /6 id */
9646 ins_encode(REX_mem_wide(dst), OpcSE(src),
9647 RM_opc_mem(secondary, dst), Con8or32(src));
9648 ins_pipe(ialu_mem_imm);
9649 %}
9650
9651 // Convert Int to Boolean
9652 instruct convI2B(rRegI dst, rRegI src, rFlagsReg cr)
9653 %{
9654 match(Set dst (Conv2B src));
9655 effect(KILL cr);
9656
9657 format %{ "testl $src, $src\t# ci2b\n\t"
9658 "setnz $dst\n\t"
9659 "movzbl $dst, $dst" %}
9660 ins_encode(REX_reg_reg(src, src), opc_reg_reg(0x85, src, src), // testl
9661 setNZ_reg(dst),
9662 REX_reg_breg(dst, dst), // movzbl
9663 Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst));
9664 ins_pipe(pipe_slow); // XXX
9665 %}
9666
9667 // Convert Pointer to Boolean
9668 instruct convP2B(rRegI dst, rRegP src, rFlagsReg cr)
9669 %{
9670 match(Set dst (Conv2B src));
9671 effect(KILL cr);
9672
9673 format %{ "testq $src, $src\t# cp2b\n\t"
9674 "setnz $dst\n\t"
9675 "movzbl $dst, $dst" %}
9676 ins_encode(REX_reg_reg_wide(src, src), opc_reg_reg(0x85, src, src), // testq
9677 setNZ_reg(dst),
9678 REX_reg_breg(dst, dst), // movzbl
9679 Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst));
9680 ins_pipe(pipe_slow); // XXX
9681 %}
9682
9683 instruct cmpLTMask(rRegI dst, rRegI p, rRegI q, rFlagsReg cr)
9684 %{
9685 match(Set dst (CmpLTMask p q));
9686 effect(KILL cr);
9687
9688 ins_cost(400);
9689 format %{ "cmpl $p, $q\t# cmpLTMask\n\t"
9690 "setlt $dst\n\t"
9691 "movzbl $dst, $dst\n\t"
9692 "negl $dst" %}
9693 ins_encode(REX_reg_reg(p, q), opc_reg_reg(0x3B, p, q), // cmpl
9694 setLT_reg(dst),
9695 REX_reg_breg(dst, dst), // movzbl
9696 Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst),
9697 neg_reg(dst));
9698 ins_pipe(pipe_slow);
9699 %}
9700
9701 instruct cmpLTMask0(rRegI dst, immI0 zero, rFlagsReg cr)
9702 %{
9703 match(Set dst (CmpLTMask dst zero));
9704 effect(KILL cr);
9705
9706 ins_cost(100);
9707 format %{ "sarl $dst, #31\t# cmpLTMask0" %}
9708 ins_encode %{
9709 __ sarl($dst$$Register, 31);
9710 %}
9711 ins_pipe(ialu_reg);
9712 %}
9713
9714 /* Better to save a register than avoid a branch */
9715 instruct cadd_cmpLTMask(rRegI p, rRegI q, rRegI y, rFlagsReg cr)
9716 %{
9717 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)));
9718 effect(KILL cr);
9719 ins_cost(300);
9720 format %{ "subl $p,$q\t# cadd_cmpLTMask\n\t"
9721 "jge done\n\t"
9722 "addl $p,$y\n"
9723 "done: " %}
9724 ins_encode %{
9725 Register Rp = $p$$Register;
9726 Register Rq = $q$$Register;
9727 Register Ry = $y$$Register;
9728 Label done;
9729 __ subl(Rp, Rq);
9730 __ jccb(Assembler::greaterEqual, done);
9731 __ addl(Rp, Ry);
9732 __ bind(done);
9733 %}
9734 ins_pipe(pipe_cmplt);
9735 %}
9736
9737 /* Better to save a register than avoid a branch */
9738 instruct and_cmpLTMask(rRegI p, rRegI q, rRegI y, rFlagsReg cr)
9739 %{
9740 match(Set y (AndI (CmpLTMask p q) y));
9741 effect(KILL cr);
9742
9743 ins_cost(300);
9744
9745 format %{ "cmpl $p, $q\t# and_cmpLTMask\n\t"
9746 "jlt done\n\t"
9747 "xorl $y, $y\n"
9748 "done: " %}
9749 ins_encode %{
9750 Register Rp = $p$$Register;
9751 Register Rq = $q$$Register;
9752 Register Ry = $y$$Register;
9753 Label done;
9754 __ cmpl(Rp, Rq);
9755 __ jccb(Assembler::less, done);
9756 __ xorl(Ry, Ry);
9757 __ bind(done);
9758 %}
9759 ins_pipe(pipe_cmplt);
9760 %}
9761
9762
9763 //---------- FP Instructions------------------------------------------------
9764
9765 instruct cmpF_cc_reg(rFlagsRegU cr, regF src1, regF src2)
9766 %{
9767 match(Set cr (CmpF src1 src2));
9768
9769 ins_cost(145);
9770 format %{ "ucomiss $src1, $src2\n\t"
9771 "jnp,s exit\n\t"
9772 "pushfq\t# saw NaN, set CF\n\t"
9773 "andq [rsp], #0xffffff2b\n\t"
9774 "popfq\n"
9775 "exit:" %}
9776 ins_encode %{
9777 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
9778 emit_cmpfp_fixup(_masm);
9779 %}
9780 ins_pipe(pipe_slow);
9781 %}
9782
9783 instruct cmpF_cc_reg_CF(rFlagsRegUCF cr, regF src1, regF src2) %{
9784 match(Set cr (CmpF src1 src2));
9785
9786 ins_cost(100);
9787 format %{ "ucomiss $src1, $src2" %}
9788 ins_encode %{
9789 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
9790 %}
9791 ins_pipe(pipe_slow);
9792 %}
9793
9794 instruct cmpF_cc_mem(rFlagsRegU cr, regF src1, memory src2)
9795 %{
9796 match(Set cr (CmpF src1 (LoadF src2)));
9797
9798 ins_cost(145);
9799 format %{ "ucomiss $src1, $src2\n\t"
9800 "jnp,s exit\n\t"
9801 "pushfq\t# saw NaN, set CF\n\t"
9802 "andq [rsp], #0xffffff2b\n\t"
9803 "popfq\n"
9804 "exit:" %}
9805 ins_encode %{
9806 __ ucomiss($src1$$XMMRegister, $src2$$Address);
9807 emit_cmpfp_fixup(_masm);
9808 %}
9809 ins_pipe(pipe_slow);
9810 %}
9811
9812 instruct cmpF_cc_memCF(rFlagsRegUCF cr, regF src1, memory src2) %{
9813 match(Set cr (CmpF src1 (LoadF src2)));
9814
9815 ins_cost(100);
9816 format %{ "ucomiss $src1, $src2" %}
9817 ins_encode %{
9818 __ ucomiss($src1$$XMMRegister, $src2$$Address);
9819 %}
9820 ins_pipe(pipe_slow);
9821 %}
9822
9823 instruct cmpF_cc_imm(rFlagsRegU cr, regF src, immF con) %{
9824 match(Set cr (CmpF src con));
9825
9826 ins_cost(145);
9827 format %{ "ucomiss $src, [$constantaddress]\t# load from constant table: float=$con\n\t"
9828 "jnp,s exit\n\t"
9829 "pushfq\t# saw NaN, set CF\n\t"
9830 "andq [rsp], #0xffffff2b\n\t"
9831 "popfq\n"
9832 "exit:" %}
9833 ins_encode %{
9834 __ ucomiss($src$$XMMRegister, $constantaddress($con));
9835 emit_cmpfp_fixup(_masm);
9836 %}
9837 ins_pipe(pipe_slow);
9838 %}
9839
9840 instruct cmpF_cc_immCF(rFlagsRegUCF cr, regF src, immF con) %{
9841 match(Set cr (CmpF src con));
9842 ins_cost(100);
9843 format %{ "ucomiss $src, [$constantaddress]\t# load from constant table: float=$con" %}
9844 ins_encode %{
9845 __ ucomiss($src$$XMMRegister, $constantaddress($con));
9846 %}
9847 ins_pipe(pipe_slow);
9848 %}
9849
9850 instruct cmpD_cc_reg(rFlagsRegU cr, regD src1, regD src2)
9851 %{
9852 match(Set cr (CmpD src1 src2));
9853
9854 ins_cost(145);
9855 format %{ "ucomisd $src1, $src2\n\t"
9856 "jnp,s exit\n\t"
9857 "pushfq\t# saw NaN, set CF\n\t"
9858 "andq [rsp], #0xffffff2b\n\t"
9859 "popfq\n"
9860 "exit:" %}
9861 ins_encode %{
9862 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
9863 emit_cmpfp_fixup(_masm);
9864 %}
9865 ins_pipe(pipe_slow);
9866 %}
9867
9868 instruct cmpD_cc_reg_CF(rFlagsRegUCF cr, regD src1, regD src2) %{
9869 match(Set cr (CmpD src1 src2));
9870
9871 ins_cost(100);
9872 format %{ "ucomisd $src1, $src2 test" %}
9873 ins_encode %{
9874 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
9875 %}
9876 ins_pipe(pipe_slow);
9877 %}
9878
9879 instruct cmpD_cc_mem(rFlagsRegU cr, regD src1, memory src2)
9880 %{
9881 match(Set cr (CmpD src1 (LoadD src2)));
9882
9883 ins_cost(145);
9884 format %{ "ucomisd $src1, $src2\n\t"
9885 "jnp,s exit\n\t"
9886 "pushfq\t# saw NaN, set CF\n\t"
9887 "andq [rsp], #0xffffff2b\n\t"
9888 "popfq\n"
9889 "exit:" %}
9890 ins_encode %{
9891 __ ucomisd($src1$$XMMRegister, $src2$$Address);
9892 emit_cmpfp_fixup(_masm);
9893 %}
9894 ins_pipe(pipe_slow);
9895 %}
9896
9897 instruct cmpD_cc_memCF(rFlagsRegUCF cr, regD src1, memory src2) %{
9898 match(Set cr (CmpD src1 (LoadD src2)));
9899
9900 ins_cost(100);
9901 format %{ "ucomisd $src1, $src2" %}
9902 ins_encode %{
9903 __ ucomisd($src1$$XMMRegister, $src2$$Address);
9904 %}
9905 ins_pipe(pipe_slow);
9906 %}
9907
9908 instruct cmpD_cc_imm(rFlagsRegU cr, regD src, immD con) %{
9909 match(Set cr (CmpD src con));
9910
9911 ins_cost(145);
9912 format %{ "ucomisd $src, [$constantaddress]\t# load from constant table: double=$con\n\t"
9913 "jnp,s exit\n\t"
9914 "pushfq\t# saw NaN, set CF\n\t"
9915 "andq [rsp], #0xffffff2b\n\t"
9916 "popfq\n"
9917 "exit:" %}
9918 ins_encode %{
9919 __ ucomisd($src$$XMMRegister, $constantaddress($con));
9920 emit_cmpfp_fixup(_masm);
9921 %}
9922 ins_pipe(pipe_slow);
9923 %}
9924
9925 instruct cmpD_cc_immCF(rFlagsRegUCF cr, regD src, immD con) %{
9926 match(Set cr (CmpD src con));
9927 ins_cost(100);
9928 format %{ "ucomisd $src, [$constantaddress]\t# load from constant table: double=$con" %}
9929 ins_encode %{
9930 __ ucomisd($src$$XMMRegister, $constantaddress($con));
9931 %}
9932 ins_pipe(pipe_slow);
9933 %}
9934
9935 // Compare into -1,0,1
9936 instruct cmpF_reg(rRegI dst, regF src1, regF src2, rFlagsReg cr)
9937 %{
9938 match(Set dst (CmpF3 src1 src2));
9939 effect(KILL cr);
9940
9941 ins_cost(275);
9942 format %{ "ucomiss $src1, $src2\n\t"
9943 "movl $dst, #-1\n\t"
9944 "jp,s done\n\t"
9945 "jb,s done\n\t"
9946 "setne $dst\n\t"
9947 "movzbl $dst, $dst\n"
9948 "done:" %}
9949 ins_encode %{
9950 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
9951 emit_cmpfp3(_masm, $dst$$Register);
9952 %}
9953 ins_pipe(pipe_slow);
9954 %}
9955
9956 // Compare into -1,0,1
9957 instruct cmpF_mem(rRegI dst, regF src1, memory src2, rFlagsReg cr)
9958 %{
9959 match(Set dst (CmpF3 src1 (LoadF src2)));
9960 effect(KILL cr);
9961
9962 ins_cost(275);
9963 format %{ "ucomiss $src1, $src2\n\t"
9964 "movl $dst, #-1\n\t"
9965 "jp,s done\n\t"
9966 "jb,s done\n\t"
9967 "setne $dst\n\t"
9968 "movzbl $dst, $dst\n"
9969 "done:" %}
9970 ins_encode %{
9971 __ ucomiss($src1$$XMMRegister, $src2$$Address);
9972 emit_cmpfp3(_masm, $dst$$Register);
9973 %}
9974 ins_pipe(pipe_slow);
9975 %}
9976
9977 // Compare into -1,0,1
9978 instruct cmpF_imm(rRegI dst, regF src, immF con, rFlagsReg cr) %{
9979 match(Set dst (CmpF3 src con));
9980 effect(KILL cr);
9981
9982 ins_cost(275);
9983 format %{ "ucomiss $src, [$constantaddress]\t# load from constant table: float=$con\n\t"
9984 "movl $dst, #-1\n\t"
9985 "jp,s done\n\t"
9986 "jb,s done\n\t"
9987 "setne $dst\n\t"
9988 "movzbl $dst, $dst\n"
9989 "done:" %}
9990 ins_encode %{
9991 __ ucomiss($src$$XMMRegister, $constantaddress($con));
9992 emit_cmpfp3(_masm, $dst$$Register);
9993 %}
9994 ins_pipe(pipe_slow);
9995 %}
9996
9997 // Compare into -1,0,1
9998 instruct cmpD_reg(rRegI dst, regD src1, regD src2, rFlagsReg cr)
9999 %{
10000 match(Set dst (CmpD3 src1 src2));
10001 effect(KILL cr);
10002
10003 ins_cost(275);
10004 format %{ "ucomisd $src1, $src2\n\t"
10005 "movl $dst, #-1\n\t"
10006 "jp,s done\n\t"
10007 "jb,s done\n\t"
10008 "setne $dst\n\t"
10009 "movzbl $dst, $dst\n"
10010 "done:" %}
10011 ins_encode %{
10012 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
10013 emit_cmpfp3(_masm, $dst$$Register);
10014 %}
10015 ins_pipe(pipe_slow);
10016 %}
10017
10018 // Compare into -1,0,1
10019 instruct cmpD_mem(rRegI dst, regD src1, memory src2, rFlagsReg cr)
10020 %{
10021 match(Set dst (CmpD3 src1 (LoadD src2)));
10022 effect(KILL cr);
10023
10024 ins_cost(275);
10025 format %{ "ucomisd $src1, $src2\n\t"
10026 "movl $dst, #-1\n\t"
10027 "jp,s done\n\t"
10028 "jb,s done\n\t"
10029 "setne $dst\n\t"
10030 "movzbl $dst, $dst\n"
10031 "done:" %}
10032 ins_encode %{
10033 __ ucomisd($src1$$XMMRegister, $src2$$Address);
10034 emit_cmpfp3(_masm, $dst$$Register);
10035 %}
10036 ins_pipe(pipe_slow);
10037 %}
10038
10039 // Compare into -1,0,1
10040 instruct cmpD_imm(rRegI dst, regD src, immD con, rFlagsReg cr) %{
10041 match(Set dst (CmpD3 src con));
10042 effect(KILL cr);
10043
10044 ins_cost(275);
10045 format %{ "ucomisd $src, [$constantaddress]\t# load from constant table: double=$con\n\t"
10046 "movl $dst, #-1\n\t"
10047 "jp,s done\n\t"
10048 "jb,s done\n\t"
10049 "setne $dst\n\t"
10050 "movzbl $dst, $dst\n"
10051 "done:" %}
10052 ins_encode %{
10053 __ ucomisd($src$$XMMRegister, $constantaddress($con));
10054 emit_cmpfp3(_masm, $dst$$Register);
10055 %}
10056 ins_pipe(pipe_slow);
10057 %}
10058
10059 //----------Arithmetic Conversion Instructions---------------------------------
10060
10061 instruct roundFloat_nop(regF dst)
10062 %{
10063 match(Set dst (RoundFloat dst));
10064
10065 ins_cost(0);
10066 ins_encode();
10067 ins_pipe(empty);
10068 %}
10069
10070 instruct roundDouble_nop(regD dst)
10071 %{
10072 match(Set dst (RoundDouble dst));
10073
10074 ins_cost(0);
10075 ins_encode();
10076 ins_pipe(empty);
10077 %}
10078
10079 instruct convF2D_reg_reg(regD dst, regF src)
10080 %{
10081 match(Set dst (ConvF2D src));
10082
10083 format %{ "cvtss2sd $dst, $src" %}
10084 ins_encode %{
10085 __ cvtss2sd ($dst$$XMMRegister, $src$$XMMRegister);
10086 %}
10087 ins_pipe(pipe_slow); // XXX
10088 %}
10089
10090 instruct convF2D_reg_mem(regD dst, memory src)
10091 %{
10092 match(Set dst (ConvF2D (LoadF src)));
10093
10094 format %{ "cvtss2sd $dst, $src" %}
10095 ins_encode %{
10096 __ cvtss2sd ($dst$$XMMRegister, $src$$Address);
10097 %}
10098 ins_pipe(pipe_slow); // XXX
10099 %}
10100
10101 instruct convD2F_reg_reg(regF dst, regD src)
10102 %{
10103 match(Set dst (ConvD2F src));
10104
10105 format %{ "cvtsd2ss $dst, $src" %}
10106 ins_encode %{
10107 __ cvtsd2ss ($dst$$XMMRegister, $src$$XMMRegister);
10108 %}
10109 ins_pipe(pipe_slow); // XXX
10110 %}
10111
10112 instruct convD2F_reg_mem(regF dst, memory src)
10113 %{
10114 match(Set dst (ConvD2F (LoadD src)));
10115
10116 format %{ "cvtsd2ss $dst, $src" %}
10117 ins_encode %{
10118 __ cvtsd2ss ($dst$$XMMRegister, $src$$Address);
10119 %}
10120 ins_pipe(pipe_slow); // XXX
10121 %}
10122
10123 // XXX do mem variants
10124 instruct convF2I_reg_reg(rRegI dst, regF src, rFlagsReg cr)
10125 %{
10126 match(Set dst (ConvF2I src));
10127 effect(KILL cr);
10128
10129 format %{ "cvttss2sil $dst, $src\t# f2i\n\t"
10130 "cmpl $dst, #0x80000000\n\t"
10131 "jne,s done\n\t"
10132 "subq rsp, #8\n\t"
10133 "movss [rsp], $src\n\t"
10134 "call f2i_fixup\n\t"
10135 "popq $dst\n"
10136 "done: "%}
10137 ins_encode %{
10138 Label done;
10139 __ cvttss2sil($dst$$Register, $src$$XMMRegister);
10140 __ cmpl($dst$$Register, 0x80000000);
10141 __ jccb(Assembler::notEqual, done);
10142 __ subptr(rsp, 8);
10143 __ movflt(Address(rsp, 0), $src$$XMMRegister);
10144 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::f2i_fixup())));
10145 __ pop($dst$$Register);
10146 __ bind(done);
10147 %}
10148 ins_pipe(pipe_slow);
10149 %}
10150
10151 instruct convF2L_reg_reg(rRegL dst, regF src, rFlagsReg cr)
10152 %{
10153 match(Set dst (ConvF2L src));
10154 effect(KILL cr);
10155
10156 format %{ "cvttss2siq $dst, $src\t# f2l\n\t"
10157 "cmpq $dst, [0x8000000000000000]\n\t"
10158 "jne,s done\n\t"
10159 "subq rsp, #8\n\t"
10160 "movss [rsp], $src\n\t"
10161 "call f2l_fixup\n\t"
10162 "popq $dst\n"
10163 "done: "%}
10164 ins_encode %{
10165 Label done;
10166 __ cvttss2siq($dst$$Register, $src$$XMMRegister);
10167 __ cmp64($dst$$Register,
10168 ExternalAddress((address) StubRoutines::x86::double_sign_flip()));
10169 __ jccb(Assembler::notEqual, done);
10170 __ subptr(rsp, 8);
10171 __ movflt(Address(rsp, 0), $src$$XMMRegister);
10172 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::f2l_fixup())));
10173 __ pop($dst$$Register);
10174 __ bind(done);
10175 %}
10176 ins_pipe(pipe_slow);
10177 %}
10178
10179 instruct convD2I_reg_reg(rRegI dst, regD src, rFlagsReg cr)
10180 %{
10181 match(Set dst (ConvD2I src));
10182 effect(KILL cr);
10183
10184 format %{ "cvttsd2sil $dst, $src\t# d2i\n\t"
10185 "cmpl $dst, #0x80000000\n\t"
10186 "jne,s done\n\t"
10187 "subq rsp, #8\n\t"
10188 "movsd [rsp], $src\n\t"
10189 "call d2i_fixup\n\t"
10190 "popq $dst\n"
10191 "done: "%}
10192 ins_encode %{
10193 Label done;
10194 __ cvttsd2sil($dst$$Register, $src$$XMMRegister);
10195 __ cmpl($dst$$Register, 0x80000000);
10196 __ jccb(Assembler::notEqual, done);
10197 __ subptr(rsp, 8);
10198 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
10199 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::d2i_fixup())));
10200 __ pop($dst$$Register);
10201 __ bind(done);
10202 %}
10203 ins_pipe(pipe_slow);
10204 %}
10205
10206 instruct convD2L_reg_reg(rRegL dst, regD src, rFlagsReg cr)
10207 %{
10208 match(Set dst (ConvD2L src));
10209 effect(KILL cr);
10210
10211 format %{ "cvttsd2siq $dst, $src\t# d2l\n\t"
10212 "cmpq $dst, [0x8000000000000000]\n\t"
10213 "jne,s done\n\t"
10214 "subq rsp, #8\n\t"
10215 "movsd [rsp], $src\n\t"
10216 "call d2l_fixup\n\t"
10217 "popq $dst\n"
10218 "done: "%}
10219 ins_encode %{
10220 Label done;
10221 __ cvttsd2siq($dst$$Register, $src$$XMMRegister);
10222 __ cmp64($dst$$Register,
10223 ExternalAddress((address) StubRoutines::x86::double_sign_flip()));
10224 __ jccb(Assembler::notEqual, done);
10225 __ subptr(rsp, 8);
10226 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
10227 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::d2l_fixup())));
10228 __ pop($dst$$Register);
10229 __ bind(done);
10230 %}
10231 ins_pipe(pipe_slow);
10232 %}
10233
10234 instruct convI2F_reg_reg(regF dst, rRegI src)
10235 %{
10236 predicate(!UseXmmI2F);
10237 match(Set dst (ConvI2F src));
10238
10239 format %{ "cvtsi2ssl $dst, $src\t# i2f" %}
10240 ins_encode %{
10241 __ cvtsi2ssl ($dst$$XMMRegister, $src$$Register);
10242 %}
10243 ins_pipe(pipe_slow); // XXX
10244 %}
10245
10246 instruct convI2F_reg_mem(regF dst, memory src)
10247 %{
10248 match(Set dst (ConvI2F (LoadI src)));
10249
10250 format %{ "cvtsi2ssl $dst, $src\t# i2f" %}
10251 ins_encode %{
10252 __ cvtsi2ssl ($dst$$XMMRegister, $src$$Address);
10253 %}
10254 ins_pipe(pipe_slow); // XXX
10255 %}
10256
10257 instruct convI2D_reg_reg(regD dst, rRegI src)
10258 %{
10259 predicate(!UseXmmI2D);
10260 match(Set dst (ConvI2D src));
10261
10262 format %{ "cvtsi2sdl $dst, $src\t# i2d" %}
10263 ins_encode %{
10264 __ cvtsi2sdl ($dst$$XMMRegister, $src$$Register);
10265 %}
10266 ins_pipe(pipe_slow); // XXX
10267 %}
10268
10269 instruct convI2D_reg_mem(regD dst, memory src)
10270 %{
10271 match(Set dst (ConvI2D (LoadI src)));
10272
10273 format %{ "cvtsi2sdl $dst, $src\t# i2d" %}
10274 ins_encode %{
10275 __ cvtsi2sdl ($dst$$XMMRegister, $src$$Address);
10276 %}
10277 ins_pipe(pipe_slow); // XXX
10278 %}
10279
10280 instruct convXI2F_reg(regF dst, rRegI src)
10281 %{
10282 predicate(UseXmmI2F);
10283 match(Set dst (ConvI2F src));
10284
10285 format %{ "movdl $dst, $src\n\t"
10286 "cvtdq2psl $dst, $dst\t# i2f" %}
10287 ins_encode %{
10288 __ movdl($dst$$XMMRegister, $src$$Register);
10289 __ cvtdq2ps($dst$$XMMRegister, $dst$$XMMRegister);
10290 %}
10291 ins_pipe(pipe_slow); // XXX
10292 %}
10293
10294 instruct convXI2D_reg(regD dst, rRegI src)
10295 %{
10296 predicate(UseXmmI2D);
10297 match(Set dst (ConvI2D src));
10298
10299 format %{ "movdl $dst, $src\n\t"
10300 "cvtdq2pdl $dst, $dst\t# i2d" %}
10301 ins_encode %{
10302 __ movdl($dst$$XMMRegister, $src$$Register);
10303 __ cvtdq2pd($dst$$XMMRegister, $dst$$XMMRegister);
10304 %}
10305 ins_pipe(pipe_slow); // XXX
10306 %}
10307
10308 instruct convL2F_reg_reg(regF dst, rRegL src)
10309 %{
10310 match(Set dst (ConvL2F src));
10311
10312 format %{ "cvtsi2ssq $dst, $src\t# l2f" %}
10313 ins_encode %{
10314 __ cvtsi2ssq ($dst$$XMMRegister, $src$$Register);
10315 %}
10316 ins_pipe(pipe_slow); // XXX
10317 %}
10318
10319 instruct convL2F_reg_mem(regF dst, memory src)
10320 %{
10321 match(Set dst (ConvL2F (LoadL src)));
10322
10323 format %{ "cvtsi2ssq $dst, $src\t# l2f" %}
10324 ins_encode %{
10325 __ cvtsi2ssq ($dst$$XMMRegister, $src$$Address);
10326 %}
10327 ins_pipe(pipe_slow); // XXX
10328 %}
10329
10330 instruct convL2D_reg_reg(regD dst, rRegL src)
10331 %{
10332 match(Set dst (ConvL2D src));
10333
10334 format %{ "cvtsi2sdq $dst, $src\t# l2d" %}
10335 ins_encode %{
10336 __ cvtsi2sdq ($dst$$XMMRegister, $src$$Register);
10337 %}
10338 ins_pipe(pipe_slow); // XXX
10339 %}
10340
10341 instruct convL2D_reg_mem(regD dst, memory src)
10342 %{
10343 match(Set dst (ConvL2D (LoadL src)));
10344
10345 format %{ "cvtsi2sdq $dst, $src\t# l2d" %}
10346 ins_encode %{
10347 __ cvtsi2sdq ($dst$$XMMRegister, $src$$Address);
10348 %}
10349 ins_pipe(pipe_slow); // XXX
10350 %}
10351
10352 instruct convI2L_reg_reg(rRegL dst, rRegI src)
10353 %{
10354 match(Set dst (ConvI2L src));
10355
10356 ins_cost(125);
10357 format %{ "movslq $dst, $src\t# i2l" %}
10358 ins_encode %{
10359 __ movslq($dst$$Register, $src$$Register);
10360 %}
10361 ins_pipe(ialu_reg_reg);
10362 %}
10363
10364 // instruct convI2L_reg_reg_foo(rRegL dst, rRegI src)
10365 // %{
10366 // match(Set dst (ConvI2L src));
10367 // // predicate(_kids[0]->_leaf->as_Type()->type()->is_int()->_lo >= 0 &&
10368 // // _kids[0]->_leaf->as_Type()->type()->is_int()->_hi >= 0);
10369 // predicate(((const TypeNode*) n)->type()->is_long()->_hi ==
10370 // (unsigned int) ((const TypeNode*) n)->type()->is_long()->_hi &&
10371 // ((const TypeNode*) n)->type()->is_long()->_lo ==
10372 // (unsigned int) ((const TypeNode*) n)->type()->is_long()->_lo);
10373
10374 // format %{ "movl $dst, $src\t# unsigned i2l" %}
10375 // ins_encode(enc_copy(dst, src));
10376 // // opcode(0x63); // needs REX.W
10377 // // ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst,src));
10378 // ins_pipe(ialu_reg_reg);
10379 // %}
10380
10381 // Zero-extend convert int to long
10382 instruct convI2L_reg_reg_zex(rRegL dst, rRegI src, immL_32bits mask)
10383 %{
10384 match(Set dst (AndL (ConvI2L src) mask));
10385
10386 format %{ "movl $dst, $src\t# i2l zero-extend\n\t" %}
10387 ins_encode %{
10388 if ($dst$$reg != $src$$reg) {
10389 __ movl($dst$$Register, $src$$Register);
10390 }
10391 %}
10392 ins_pipe(ialu_reg_reg);
10393 %}
10394
10395 // Zero-extend convert int to long
10396 instruct convI2L_reg_mem_zex(rRegL dst, memory src, immL_32bits mask)
10397 %{
10398 match(Set dst (AndL (ConvI2L (LoadI src)) mask));
10399
10400 format %{ "movl $dst, $src\t# i2l zero-extend\n\t" %}
10401 ins_encode %{
10402 __ movl($dst$$Register, $src$$Address);
10403 %}
10404 ins_pipe(ialu_reg_mem);
10405 %}
10406
10407 instruct zerox_long_reg_reg(rRegL dst, rRegL src, immL_32bits mask)
10408 %{
10409 match(Set dst (AndL src mask));
10410
10411 format %{ "movl $dst, $src\t# zero-extend long" %}
10412 ins_encode %{
10413 __ movl($dst$$Register, $src$$Register);
10414 %}
10415 ins_pipe(ialu_reg_reg);
10416 %}
10417
10418 instruct convL2I_reg_reg(rRegI dst, rRegL src)
10419 %{
10420 match(Set dst (ConvL2I src));
10421
10422 format %{ "movl $dst, $src\t# l2i" %}
10423 ins_encode %{
10424 __ movl($dst$$Register, $src$$Register);
10425 %}
10426 ins_pipe(ialu_reg_reg);
10427 %}
10428
10429
10430 instruct MoveF2I_stack_reg(rRegI dst, stackSlotF src) %{
10431 match(Set dst (MoveF2I src));
10432 effect(DEF dst, USE src);
10433
10434 ins_cost(125);
10435 format %{ "movl $dst, $src\t# MoveF2I_stack_reg" %}
10436 ins_encode %{
10437 __ movl($dst$$Register, Address(rsp, $src$$disp));
10438 %}
10439 ins_pipe(ialu_reg_mem);
10440 %}
10441
10442 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{
10443 match(Set dst (MoveI2F src));
10444 effect(DEF dst, USE src);
10445
10446 ins_cost(125);
10447 format %{ "movss $dst, $src\t# MoveI2F_stack_reg" %}
10448 ins_encode %{
10449 __ movflt($dst$$XMMRegister, Address(rsp, $src$$disp));
10450 %}
10451 ins_pipe(pipe_slow);
10452 %}
10453
10454 instruct MoveD2L_stack_reg(rRegL dst, stackSlotD src) %{
10455 match(Set dst (MoveD2L src));
10456 effect(DEF dst, USE src);
10457
10458 ins_cost(125);
10459 format %{ "movq $dst, $src\t# MoveD2L_stack_reg" %}
10460 ins_encode %{
10461 __ movq($dst$$Register, Address(rsp, $src$$disp));
10462 %}
10463 ins_pipe(ialu_reg_mem);
10464 %}
10465
10466 instruct MoveL2D_stack_reg_partial(regD dst, stackSlotL src) %{
10467 predicate(!UseXmmLoadAndClearUpper);
10468 match(Set dst (MoveL2D src));
10469 effect(DEF dst, USE src);
10470
10471 ins_cost(125);
10472 format %{ "movlpd $dst, $src\t# MoveL2D_stack_reg" %}
10473 ins_encode %{
10474 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
10475 %}
10476 ins_pipe(pipe_slow);
10477 %}
10478
10479 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{
10480 predicate(UseXmmLoadAndClearUpper);
10481 match(Set dst (MoveL2D src));
10482 effect(DEF dst, USE src);
10483
10484 ins_cost(125);
10485 format %{ "movsd $dst, $src\t# MoveL2D_stack_reg" %}
10486 ins_encode %{
10487 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
10488 %}
10489 ins_pipe(pipe_slow);
10490 %}
10491
10492
10493 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{
10494 match(Set dst (MoveF2I src));
10495 effect(DEF dst, USE src);
10496
10497 ins_cost(95); // XXX
10498 format %{ "movss $dst, $src\t# MoveF2I_reg_stack" %}
10499 ins_encode %{
10500 __ movflt(Address(rsp, $dst$$disp), $src$$XMMRegister);
10501 %}
10502 ins_pipe(pipe_slow);
10503 %}
10504
10505 instruct MoveI2F_reg_stack(stackSlotF dst, rRegI src) %{
10506 match(Set dst (MoveI2F src));
10507 effect(DEF dst, USE src);
10508
10509 ins_cost(100);
10510 format %{ "movl $dst, $src\t# MoveI2F_reg_stack" %}
10511 ins_encode %{
10512 __ movl(Address(rsp, $dst$$disp), $src$$Register);
10513 %}
10514 ins_pipe( ialu_mem_reg );
10515 %}
10516
10517 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{
10518 match(Set dst (MoveD2L src));
10519 effect(DEF dst, USE src);
10520
10521 ins_cost(95); // XXX
10522 format %{ "movsd $dst, $src\t# MoveL2D_reg_stack" %}
10523 ins_encode %{
10524 __ movdbl(Address(rsp, $dst$$disp), $src$$XMMRegister);
10525 %}
10526 ins_pipe(pipe_slow);
10527 %}
10528
10529 instruct MoveL2D_reg_stack(stackSlotD dst, rRegL src) %{
10530 match(Set dst (MoveL2D src));
10531 effect(DEF dst, USE src);
10532
10533 ins_cost(100);
10534 format %{ "movq $dst, $src\t# MoveL2D_reg_stack" %}
10535 ins_encode %{
10536 __ movq(Address(rsp, $dst$$disp), $src$$Register);
10537 %}
10538 ins_pipe(ialu_mem_reg);
10539 %}
10540
10541 instruct MoveF2I_reg_reg(rRegI dst, regF src) %{
10542 match(Set dst (MoveF2I src));
10543 effect(DEF dst, USE src);
10544 ins_cost(85);
10545 format %{ "movd $dst,$src\t# MoveF2I" %}
10546 ins_encode %{
10547 __ movdl($dst$$Register, $src$$XMMRegister);
10548 %}
10549 ins_pipe( pipe_slow );
10550 %}
10551
10552 instruct MoveD2L_reg_reg(rRegL dst, regD src) %{
10553 match(Set dst (MoveD2L src));
10554 effect(DEF dst, USE src);
10555 ins_cost(85);
10556 format %{ "movd $dst,$src\t# MoveD2L" %}
10557 ins_encode %{
10558 __ movdq($dst$$Register, $src$$XMMRegister);
10559 %}
10560 ins_pipe( pipe_slow );
10561 %}
10562
10563 instruct MoveI2F_reg_reg(regF dst, rRegI src) %{
10564 match(Set dst (MoveI2F src));
10565 effect(DEF dst, USE src);
10566 ins_cost(100);
10567 format %{ "movd $dst,$src\t# MoveI2F" %}
10568 ins_encode %{
10569 __ movdl($dst$$XMMRegister, $src$$Register);
10570 %}
10571 ins_pipe( pipe_slow );
10572 %}
10573
10574 instruct MoveL2D_reg_reg(regD dst, rRegL src) %{
10575 match(Set dst (MoveL2D src));
10576 effect(DEF dst, USE src);
10577 ins_cost(100);
10578 format %{ "movd $dst,$src\t# MoveL2D" %}
10579 ins_encode %{
10580 __ movdq($dst$$XMMRegister, $src$$Register);
10581 %}
10582 ins_pipe( pipe_slow );
10583 %}
10584
10585
10586 // =======================================================================
10587 // fast clearing of an array
10588 instruct rep_stos(rcx_RegL cnt, rdi_RegP base, rax_RegI zero, Universe dummy,
10589 rFlagsReg cr)
10590 %{
10591 predicate(!((ClearArrayNode*)n)->is_large());
10592 match(Set dummy (ClearArray cnt base));
10593 effect(USE_KILL cnt, USE_KILL base, KILL zero, KILL cr);
10594
10595 format %{ $$template
10596 $$emit$$"xorq rax, rax\t# ClearArray:\n\t"
10597 $$emit$$"cmp InitArrayShortSize,rcx\n\t"
10598 $$emit$$"jg LARGE\n\t"
10599 $$emit$$"dec rcx\n\t"
10600 $$emit$$"js DONE\t# Zero length\n\t"
10601 $$emit$$"mov rax,(rdi,rcx,8)\t# LOOP\n\t"
10602 $$emit$$"dec rcx\n\t"
10603 $$emit$$"jge LOOP\n\t"
10604 $$emit$$"jmp DONE\n\t"
10605 $$emit$$"# LARGE:\n\t"
10606 if (UseFastStosb) {
10607 $$emit$$"shlq rcx,3\t# Convert doublewords to bytes\n\t"
10608 $$emit$$"rep stosb\t# Store rax to *rdi++ while rcx--\n\t"
10609 } else {
10610 $$emit$$"rep stosq\t# Store rax to *rdi++ while rcx--\n\t"
10611 }
10612 $$emit$$"# DONE"
10613 %}
10614 ins_encode %{
10615 __ clear_mem($base$$Register, $cnt$$Register, $zero$$Register, false);
10616 %}
10617 ins_pipe(pipe_slow);
10618 %}
10619
10620 instruct rep_stos_large(rcx_RegL cnt, rdi_RegP base, rax_RegI zero, Universe dummy,
10621 rFlagsReg cr)
10622 %{
10623 predicate(((ClearArrayNode*)n)->is_large());
10624 match(Set dummy (ClearArray cnt base));
10625 effect(USE_KILL cnt, USE_KILL base, KILL zero, KILL cr);
10626
10627 format %{ $$template
10628 $$emit$$"xorq rax, rax\t# ClearArray:\n\t"
10629 if (UseFastStosb) {
10630 $$emit$$"shlq rcx,3\t# Convert doublewords to bytes\n\t"
10631 $$emit$$"rep stosb\t# Store rax to *rdi++ while rcx--"
10632 } else {
10633 $$emit$$"rep stosq\t# Store rax to *rdi++ while rcx--"
10634 }
10635 %}
10636 ins_encode %{
10637 __ clear_mem($base$$Register, $cnt$$Register, $zero$$Register, true);
10638 %}
10639 ins_pipe(pipe_slow);
10640 %}
10641
10642 instruct string_compareL(rdi_RegP str1, rcx_RegI cnt1, rsi_RegP str2, rdx_RegI cnt2,
10643 rax_RegI result, regD tmp1, rFlagsReg cr)
10644 %{
10645 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::LL);
10646 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10647 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
10648
10649 format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
10650 ins_encode %{
10651 __ string_compare($str1$$Register, $str2$$Register,
10652 $cnt1$$Register, $cnt2$$Register, $result$$Register,
10653 $tmp1$$XMMRegister, StrIntrinsicNode::LL);
10654 %}
10655 ins_pipe( pipe_slow );
10656 %}
10657
10658 instruct string_compareU(rdi_RegP str1, rcx_RegI cnt1, rsi_RegP str2, rdx_RegI cnt2,
10659 rax_RegI result, regD tmp1, rFlagsReg cr)
10660 %{
10661 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::UU);
10662 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10663 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
10664
10665 format %{ "String Compare char[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
10666 ins_encode %{
10667 __ string_compare($str1$$Register, $str2$$Register,
10668 $cnt1$$Register, $cnt2$$Register, $result$$Register,
10669 $tmp1$$XMMRegister, StrIntrinsicNode::UU);
10670 %}
10671 ins_pipe( pipe_slow );
10672 %}
10673
10674 instruct string_compareLU(rdi_RegP str1, rcx_RegI cnt1, rsi_RegP str2, rdx_RegI cnt2,
10675 rax_RegI result, regD tmp1, rFlagsReg cr)
10676 %{
10677 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::LU);
10678 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10679 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
10680
10681 format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
10682 ins_encode %{
10683 __ string_compare($str1$$Register, $str2$$Register,
10684 $cnt1$$Register, $cnt2$$Register, $result$$Register,
10685 $tmp1$$XMMRegister, StrIntrinsicNode::LU);
10686 %}
10687 ins_pipe( pipe_slow );
10688 %}
10689
10690 instruct string_compareUL(rsi_RegP str1, rdx_RegI cnt1, rdi_RegP str2, rcx_RegI cnt2,
10691 rax_RegI result, regD tmp1, rFlagsReg cr)
10692 %{
10693 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::UL);
10694 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10695 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
10696
10697 format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
10698 ins_encode %{
10699 __ string_compare($str2$$Register, $str1$$Register,
10700 $cnt2$$Register, $cnt1$$Register, $result$$Register,
10701 $tmp1$$XMMRegister, StrIntrinsicNode::UL);
10702 %}
10703 ins_pipe( pipe_slow );
10704 %}
10705
10706 // fast search of substring with known size.
10707 instruct string_indexof_conL(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, immI int_cnt2,
10708 rbx_RegI result, regD vec, rax_RegI cnt2, rcx_RegI tmp, rFlagsReg cr)
10709 %{
10710 predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL));
10711 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
10712 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, KILL cnt2, KILL tmp, KILL cr);
10713
10714 format %{ "String IndexOf byte[] $str1,$cnt1,$str2,$int_cnt2 -> $result // KILL $vec, $cnt1, $cnt2, $tmp" %}
10715 ins_encode %{
10716 int icnt2 = (int)$int_cnt2$$constant;
10717 if (icnt2 >= 16) {
10718 // IndexOf for constant substrings with size >= 16 elements
10719 // which don't need to be loaded through stack.
10720 __ string_indexofC8($str1$$Register, $str2$$Register,
10721 $cnt1$$Register, $cnt2$$Register,
10722 icnt2, $result$$Register,
10723 $vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::LL);
10724 } else {
10725 // Small strings are loaded through stack if they cross page boundary.
10726 __ string_indexof($str1$$Register, $str2$$Register,
10727 $cnt1$$Register, $cnt2$$Register,
10728 icnt2, $result$$Register,
10729 $vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::LL);
10730 }
10731 %}
10732 ins_pipe( pipe_slow );
10733 %}
10734
10735 // fast search of substring with known size.
10736 instruct string_indexof_conU(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, immI int_cnt2,
10737 rbx_RegI result, regD vec, rax_RegI cnt2, rcx_RegI tmp, rFlagsReg cr)
10738 %{
10739 predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU));
10740 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
10741 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, KILL cnt2, KILL tmp, KILL cr);
10742
10743 format %{ "String IndexOf char[] $str1,$cnt1,$str2,$int_cnt2 -> $result // KILL $vec, $cnt1, $cnt2, $tmp" %}
10744 ins_encode %{
10745 int icnt2 = (int)$int_cnt2$$constant;
10746 if (icnt2 >= 8) {
10747 // IndexOf for constant substrings with size >= 8 elements
10748 // which don't need to be loaded through stack.
10749 __ string_indexofC8($str1$$Register, $str2$$Register,
10750 $cnt1$$Register, $cnt2$$Register,
10751 icnt2, $result$$Register,
10752 $vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UU);
10753 } else {
10754 // Small strings are loaded through stack if they cross page boundary.
10755 __ string_indexof($str1$$Register, $str2$$Register,
10756 $cnt1$$Register, $cnt2$$Register,
10757 icnt2, $result$$Register,
10758 $vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UU);
10759 }
10760 %}
10761 ins_pipe( pipe_slow );
10762 %}
10763
10764 // fast search of substring with known size.
10765 instruct string_indexof_conUL(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, immI int_cnt2,
10766 rbx_RegI result, regD vec, rax_RegI cnt2, rcx_RegI tmp, rFlagsReg cr)
10767 %{
10768 predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL));
10769 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
10770 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, KILL cnt2, KILL tmp, KILL cr);
10771
10772 format %{ "String IndexOf char[] $str1,$cnt1,$str2,$int_cnt2 -> $result // KILL $vec, $cnt1, $cnt2, $tmp" %}
10773 ins_encode %{
10774 int icnt2 = (int)$int_cnt2$$constant;
10775 if (icnt2 >= 8) {
10776 // IndexOf for constant substrings with size >= 8 elements
10777 // which don't need to be loaded through stack.
10778 __ string_indexofC8($str1$$Register, $str2$$Register,
10779 $cnt1$$Register, $cnt2$$Register,
10780 icnt2, $result$$Register,
10781 $vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UL);
10782 } else {
10783 // Small strings are loaded through stack if they cross page boundary.
10784 __ string_indexof($str1$$Register, $str2$$Register,
10785 $cnt1$$Register, $cnt2$$Register,
10786 icnt2, $result$$Register,
10787 $vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UL);
10788 }
10789 %}
10790 ins_pipe( pipe_slow );
10791 %}
10792
10793 instruct string_indexofL(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, rax_RegI cnt2,
10794 rbx_RegI result, regD vec, rcx_RegI tmp, rFlagsReg cr)
10795 %{
10796 predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL));
10797 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
10798 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp, KILL cr);
10799
10800 format %{ "String IndexOf byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL all" %}
10801 ins_encode %{
10802 __ string_indexof($str1$$Register, $str2$$Register,
10803 $cnt1$$Register, $cnt2$$Register,
10804 (-1), $result$$Register,
10805 $vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::LL);
10806 %}
10807 ins_pipe( pipe_slow );
10808 %}
10809
10810 instruct string_indexofU(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, rax_RegI cnt2,
10811 rbx_RegI result, regD vec, rcx_RegI tmp, rFlagsReg cr)
10812 %{
10813 predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU));
10814 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
10815 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp, KILL cr);
10816
10817 format %{ "String IndexOf char[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL all" %}
10818 ins_encode %{
10819 __ string_indexof($str1$$Register, $str2$$Register,
10820 $cnt1$$Register, $cnt2$$Register,
10821 (-1), $result$$Register,
10822 $vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UU);
10823 %}
10824 ins_pipe( pipe_slow );
10825 %}
10826
10827 instruct string_indexofUL(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, rax_RegI cnt2,
10828 rbx_RegI result, regD vec, rcx_RegI tmp, rFlagsReg cr)
10829 %{
10830 predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL));
10831 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
10832 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp, KILL cr);
10833
10834 format %{ "String IndexOf char[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL all" %}
10835 ins_encode %{
10836 __ string_indexof($str1$$Register, $str2$$Register,
10837 $cnt1$$Register, $cnt2$$Register,
10838 (-1), $result$$Register,
10839 $vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UL);
10840 %}
10841 ins_pipe( pipe_slow );
10842 %}
10843
10844 instruct string_indexofU_char(rdi_RegP str1, rdx_RegI cnt1, rax_RegI ch,
10845 rbx_RegI result, regD vec1, regD vec2, regD vec3, rcx_RegI tmp, rFlagsReg cr)
10846 %{
10847 predicate(UseSSE42Intrinsics);
10848 match(Set result (StrIndexOfChar (Binary str1 cnt1) ch));
10849 effect(TEMP vec1, TEMP vec2, TEMP vec3, USE_KILL str1, USE_KILL cnt1, USE_KILL ch, TEMP tmp, KILL cr);
10850 format %{ "String IndexOf char[] $str1,$cnt1,$ch -> $result // KILL all" %}
10851 ins_encode %{
10852 __ string_indexof_char($str1$$Register, $cnt1$$Register, $ch$$Register, $result$$Register,
10853 $vec1$$XMMRegister, $vec2$$XMMRegister, $vec3$$XMMRegister, $tmp$$Register);
10854 %}
10855 ins_pipe( pipe_slow );
10856 %}
10857
10858 // fast string equals
10859 instruct string_equals(rdi_RegP str1, rsi_RegP str2, rcx_RegI cnt, rax_RegI result,
10860 regD tmp1, regD tmp2, rbx_RegI tmp3, rFlagsReg cr)
10861 %{
10862 match(Set result (StrEquals (Binary str1 str2) cnt));
10863 effect(TEMP tmp1, TEMP tmp2, USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp3, KILL cr);
10864
10865 format %{ "String Equals $str1,$str2,$cnt -> $result // KILL $tmp1, $tmp2, $tmp3" %}
10866 ins_encode %{
10867 __ arrays_equals(false, $str1$$Register, $str2$$Register,
10868 $cnt$$Register, $result$$Register, $tmp3$$Register,
10869 $tmp1$$XMMRegister, $tmp2$$XMMRegister, false /* char */);
10870 %}
10871 ins_pipe( pipe_slow );
10872 %}
10873
10874 // fast array equals
10875 instruct array_equalsB(rdi_RegP ary1, rsi_RegP ary2, rax_RegI result,
10876 regD tmp1, regD tmp2, rcx_RegI tmp3, rbx_RegI tmp4, rFlagsReg cr)
10877 %{
10878 predicate(((AryEqNode*)n)->encoding() == StrIntrinsicNode::LL);
10879 match(Set result (AryEq ary1 ary2));
10880 effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr);
10881
10882 format %{ "Array Equals byte[] $ary1,$ary2 -> $result // KILL $tmp1, $tmp2, $tmp3, $tmp4" %}
10883 ins_encode %{
10884 __ arrays_equals(true, $ary1$$Register, $ary2$$Register,
10885 $tmp3$$Register, $result$$Register, $tmp4$$Register,
10886 $tmp1$$XMMRegister, $tmp2$$XMMRegister, false /* char */);
10887 %}
10888 ins_pipe( pipe_slow );
10889 %}
10890
10891 instruct array_equalsC(rdi_RegP ary1, rsi_RegP ary2, rax_RegI result,
10892 regD tmp1, regD tmp2, rcx_RegI tmp3, rbx_RegI tmp4, rFlagsReg cr)
10893 %{
10894 predicate(((AryEqNode*)n)->encoding() == StrIntrinsicNode::UU);
10895 match(Set result (AryEq ary1 ary2));
10896 effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr);
10897
10898 format %{ "Array Equals char[] $ary1,$ary2 -> $result // KILL $tmp1, $tmp2, $tmp3, $tmp4" %}
10899 ins_encode %{
10900 __ arrays_equals(true, $ary1$$Register, $ary2$$Register,
10901 $tmp3$$Register, $result$$Register, $tmp4$$Register,
10902 $tmp1$$XMMRegister, $tmp2$$XMMRegister, true /* char */);
10903 %}
10904 ins_pipe( pipe_slow );
10905 %}
10906
10907 instruct has_negatives(rsi_RegP ary1, rcx_RegI len, rax_RegI result,
10908 regD tmp1, regD tmp2, rbx_RegI tmp3, rFlagsReg cr)
10909 %{
10910 match(Set result (HasNegatives ary1 len));
10911 effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL len, KILL tmp3, KILL cr);
10912
10913 format %{ "has negatives byte[] $ary1,$len -> $result // KILL $tmp1, $tmp2, $tmp3" %}
10914 ins_encode %{
10915 __ has_negatives($ary1$$Register, $len$$Register,
10916 $result$$Register, $tmp3$$Register,
10917 $tmp1$$XMMRegister, $tmp2$$XMMRegister);
10918 %}
10919 ins_pipe( pipe_slow );
10920 %}
10921
10922 // fast char[] to byte[] compression
10923 instruct string_compress(rsi_RegP src, rdi_RegP dst, rdx_RegI len, regD tmp1, regD tmp2, regD tmp3, regD tmp4,
10924 rcx_RegI tmp5, rax_RegI result, rFlagsReg cr) %{
10925 match(Set result (StrCompressedCopy src (Binary dst len)));
10926 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, USE_KILL src, USE_KILL dst, USE_KILL len, KILL tmp5, KILL cr);
10927
10928 format %{ "String Compress $src,$dst -> $result // KILL RAX, RCX, RDX" %}
10929 ins_encode %{
10930 __ char_array_compress($src$$Register, $dst$$Register, $len$$Register,
10931 $tmp1$$XMMRegister, $tmp2$$XMMRegister, $tmp3$$XMMRegister,
10932 $tmp4$$XMMRegister, $tmp5$$Register, $result$$Register);
10933 %}
10934 ins_pipe( pipe_slow );
10935 %}
10936
10937 // fast byte[] to char[] inflation
10938 instruct string_inflate(Universe dummy, rsi_RegP src, rdi_RegP dst, rdx_RegI len,
10939 regD tmp1, rcx_RegI tmp2, rFlagsReg cr) %{
10940 match(Set dummy (StrInflatedCopy src (Binary dst len)));
10941 effect(TEMP tmp1, TEMP tmp2, USE_KILL src, USE_KILL dst, USE_KILL len, KILL cr);
10942
10943 format %{ "String Inflate $src,$dst // KILL $tmp1, $tmp2" %}
10944 ins_encode %{
10945 __ byte_array_inflate($src$$Register, $dst$$Register, $len$$Register,
10946 $tmp1$$XMMRegister, $tmp2$$Register);
10947 %}
10948 ins_pipe( pipe_slow );
10949 %}
10950
10951 // encode char[] to byte[] in ISO_8859_1
10952 instruct encode_iso_array(rsi_RegP src, rdi_RegP dst, rdx_RegI len,
10953 regD tmp1, regD tmp2, regD tmp3, regD tmp4,
10954 rcx_RegI tmp5, rax_RegI result, rFlagsReg cr) %{
10955 match(Set result (EncodeISOArray src (Binary dst len)));
10956 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, USE_KILL src, USE_KILL dst, USE_KILL len, KILL tmp5, KILL cr);
10957
10958 format %{ "Encode array $src,$dst,$len -> $result // KILL RCX, RDX, $tmp1, $tmp2, $tmp3, $tmp4, RSI, RDI " %}
10959 ins_encode %{
10960 __ encode_iso_array($src$$Register, $dst$$Register, $len$$Register,
10961 $tmp1$$XMMRegister, $tmp2$$XMMRegister, $tmp3$$XMMRegister,
10962 $tmp4$$XMMRegister, $tmp5$$Register, $result$$Register);
10963 %}
10964 ins_pipe( pipe_slow );
10965 %}
10966
10967 //----------Overflow Math Instructions-----------------------------------------
10968
10969 instruct overflowAddI_rReg(rFlagsReg cr, rax_RegI op1, rRegI op2)
10970 %{
10971 match(Set cr (OverflowAddI op1 op2));
10972 effect(DEF cr, USE_KILL op1, USE op2);
10973
10974 format %{ "addl $op1, $op2\t# overflow check int" %}
10975
10976 ins_encode %{
10977 __ addl($op1$$Register, $op2$$Register);
10978 %}
10979 ins_pipe(ialu_reg_reg);
10980 %}
10981
10982 instruct overflowAddI_rReg_imm(rFlagsReg cr, rax_RegI op1, immI op2)
10983 %{
10984 match(Set cr (OverflowAddI op1 op2));
10985 effect(DEF cr, USE_KILL op1, USE op2);
10986
10987 format %{ "addl $op1, $op2\t# overflow check int" %}
10988
10989 ins_encode %{
10990 __ addl($op1$$Register, $op2$$constant);
10991 %}
10992 ins_pipe(ialu_reg_reg);
10993 %}
10994
10995 instruct overflowAddL_rReg(rFlagsReg cr, rax_RegL op1, rRegL op2)
10996 %{
10997 match(Set cr (OverflowAddL op1 op2));
10998 effect(DEF cr, USE_KILL op1, USE op2);
10999
11000 format %{ "addq $op1, $op2\t# overflow check long" %}
11001 ins_encode %{
11002 __ addq($op1$$Register, $op2$$Register);
11003 %}
11004 ins_pipe(ialu_reg_reg);
11005 %}
11006
11007 instruct overflowAddL_rReg_imm(rFlagsReg cr, rax_RegL op1, immL32 op2)
11008 %{
11009 match(Set cr (OverflowAddL op1 op2));
11010 effect(DEF cr, USE_KILL op1, USE op2);
11011
11012 format %{ "addq $op1, $op2\t# overflow check long" %}
11013 ins_encode %{
11014 __ addq($op1$$Register, $op2$$constant);
11015 %}
11016 ins_pipe(ialu_reg_reg);
11017 %}
11018
11019 instruct overflowSubI_rReg(rFlagsReg cr, rRegI op1, rRegI op2)
11020 %{
11021 match(Set cr (OverflowSubI op1 op2));
11022
11023 format %{ "cmpl $op1, $op2\t# overflow check int" %}
11024 ins_encode %{
11025 __ cmpl($op1$$Register, $op2$$Register);
11026 %}
11027 ins_pipe(ialu_reg_reg);
11028 %}
11029
11030 instruct overflowSubI_rReg_imm(rFlagsReg cr, rRegI op1, immI op2)
11031 %{
11032 match(Set cr (OverflowSubI op1 op2));
11033
11034 format %{ "cmpl $op1, $op2\t# overflow check int" %}
11035 ins_encode %{
11036 __ cmpl($op1$$Register, $op2$$constant);
11037 %}
11038 ins_pipe(ialu_reg_reg);
11039 %}
11040
11041 instruct overflowSubL_rReg(rFlagsReg cr, rRegL op1, rRegL op2)
11042 %{
11043 match(Set cr (OverflowSubL op1 op2));
11044
11045 format %{ "cmpq $op1, $op2\t# overflow check long" %}
11046 ins_encode %{
11047 __ cmpq($op1$$Register, $op2$$Register);
11048 %}
11049 ins_pipe(ialu_reg_reg);
11050 %}
11051
11052 instruct overflowSubL_rReg_imm(rFlagsReg cr, rRegL op1, immL32 op2)
11053 %{
11054 match(Set cr (OverflowSubL op1 op2));
11055
11056 format %{ "cmpq $op1, $op2\t# overflow check long" %}
11057 ins_encode %{
11058 __ cmpq($op1$$Register, $op2$$constant);
11059 %}
11060 ins_pipe(ialu_reg_reg);
11061 %}
11062
11063 instruct overflowNegI_rReg(rFlagsReg cr, immI0 zero, rax_RegI op2)
11064 %{
11065 match(Set cr (OverflowSubI zero op2));
11066 effect(DEF cr, USE_KILL op2);
11067
11068 format %{ "negl $op2\t# overflow check int" %}
11069 ins_encode %{
11070 __ negl($op2$$Register);
11071 %}
11072 ins_pipe(ialu_reg_reg);
11073 %}
11074
11075 instruct overflowNegL_rReg(rFlagsReg cr, immL0 zero, rax_RegL op2)
11076 %{
11077 match(Set cr (OverflowSubL zero op2));
11078 effect(DEF cr, USE_KILL op2);
11079
11080 format %{ "negq $op2\t# overflow check long" %}
11081 ins_encode %{
11082 __ negq($op2$$Register);
11083 %}
11084 ins_pipe(ialu_reg_reg);
11085 %}
11086
11087 instruct overflowMulI_rReg(rFlagsReg cr, rax_RegI op1, rRegI op2)
11088 %{
11089 match(Set cr (OverflowMulI op1 op2));
11090 effect(DEF cr, USE_KILL op1, USE op2);
11091
11092 format %{ "imull $op1, $op2\t# overflow check int" %}
11093 ins_encode %{
11094 __ imull($op1$$Register, $op2$$Register);
11095 %}
11096 ins_pipe(ialu_reg_reg_alu0);
11097 %}
11098
11099 instruct overflowMulI_rReg_imm(rFlagsReg cr, rRegI op1, immI op2, rRegI tmp)
11100 %{
11101 match(Set cr (OverflowMulI op1 op2));
11102 effect(DEF cr, TEMP tmp, USE op1, USE op2);
11103
11104 format %{ "imull $tmp, $op1, $op2\t# overflow check int" %}
11105 ins_encode %{
11106 __ imull($tmp$$Register, $op1$$Register, $op2$$constant);
11107 %}
11108 ins_pipe(ialu_reg_reg_alu0);
11109 %}
11110
11111 instruct overflowMulL_rReg(rFlagsReg cr, rax_RegL op1, rRegL op2)
11112 %{
11113 match(Set cr (OverflowMulL op1 op2));
11114 effect(DEF cr, USE_KILL op1, USE op2);
11115
11116 format %{ "imulq $op1, $op2\t# overflow check long" %}
11117 ins_encode %{
11118 __ imulq($op1$$Register, $op2$$Register);
11119 %}
11120 ins_pipe(ialu_reg_reg_alu0);
11121 %}
11122
11123 instruct overflowMulL_rReg_imm(rFlagsReg cr, rRegL op1, immL32 op2, rRegL tmp)
11124 %{
11125 match(Set cr (OverflowMulL op1 op2));
11126 effect(DEF cr, TEMP tmp, USE op1, USE op2);
11127
11128 format %{ "imulq $tmp, $op1, $op2\t# overflow check long" %}
11129 ins_encode %{
11130 __ imulq($tmp$$Register, $op1$$Register, $op2$$constant);
11131 %}
11132 ins_pipe(ialu_reg_reg_alu0);
11133 %}
11134
11135
11136 //----------Control Flow Instructions------------------------------------------
11137 // Signed compare Instructions
11138
11139 // XXX more variants!!
11140 instruct compI_rReg(rFlagsReg cr, rRegI op1, rRegI op2)
11141 %{
11142 match(Set cr (CmpI op1 op2));
11143 effect(DEF cr, USE op1, USE op2);
11144
11145 format %{ "cmpl $op1, $op2" %}
11146 opcode(0x3B); /* Opcode 3B /r */
11147 ins_encode(REX_reg_reg(op1, op2), OpcP, reg_reg(op1, op2));
11148 ins_pipe(ialu_cr_reg_reg);
11149 %}
11150
11151 instruct compI_rReg_imm(rFlagsReg cr, rRegI op1, immI op2)
11152 %{
11153 match(Set cr (CmpI op1 op2));
11154
11155 format %{ "cmpl $op1, $op2" %}
11156 opcode(0x81, 0x07); /* Opcode 81 /7 */
11157 ins_encode(OpcSErm(op1, op2), Con8or32(op2));
11158 ins_pipe(ialu_cr_reg_imm);
11159 %}
11160
11161 instruct compI_rReg_mem(rFlagsReg cr, rRegI op1, memory op2)
11162 %{
11163 match(Set cr (CmpI op1 (LoadI op2)));
11164
11165 ins_cost(500); // XXX
11166 format %{ "cmpl $op1, $op2" %}
11167 opcode(0x3B); /* Opcode 3B /r */
11168 ins_encode(REX_reg_mem(op1, op2), OpcP, reg_mem(op1, op2));
11169 ins_pipe(ialu_cr_reg_mem);
11170 %}
11171
11172 instruct testI_reg(rFlagsReg cr, rRegI src, immI0 zero)
11173 %{
11174 match(Set cr (CmpI src zero));
11175
11176 format %{ "testl $src, $src" %}
11177 opcode(0x85);
11178 ins_encode(REX_reg_reg(src, src), OpcP, reg_reg(src, src));
11179 ins_pipe(ialu_cr_reg_imm);
11180 %}
11181
11182 instruct testI_reg_imm(rFlagsReg cr, rRegI src, immI con, immI0 zero)
11183 %{
11184 match(Set cr (CmpI (AndI src con) zero));
11185
11186 format %{ "testl $src, $con" %}
11187 opcode(0xF7, 0x00);
11188 ins_encode(REX_reg(src), OpcP, reg_opc(src), Con32(con));
11189 ins_pipe(ialu_cr_reg_imm);
11190 %}
11191
11192 instruct testI_reg_mem(rFlagsReg cr, rRegI src, memory mem, immI0 zero)
11193 %{
11194 match(Set cr (CmpI (AndI src (LoadI mem)) zero));
11195
11196 format %{ "testl $src, $mem" %}
11197 opcode(0x85);
11198 ins_encode(REX_reg_mem(src, mem), OpcP, reg_mem(src, mem));
11199 ins_pipe(ialu_cr_reg_mem);
11200 %}
11201
11202 // Unsigned compare Instructions; really, same as signed except they
11203 // produce an rFlagsRegU instead of rFlagsReg.
11204 instruct compU_rReg(rFlagsRegU cr, rRegI op1, rRegI op2)
11205 %{
11206 match(Set cr (CmpU op1 op2));
11207
11208 format %{ "cmpl $op1, $op2\t# unsigned" %}
11209 opcode(0x3B); /* Opcode 3B /r */
11210 ins_encode(REX_reg_reg(op1, op2), OpcP, reg_reg(op1, op2));
11211 ins_pipe(ialu_cr_reg_reg);
11212 %}
11213
11214 instruct compU_rReg_imm(rFlagsRegU cr, rRegI op1, immI op2)
11215 %{
11216 match(Set cr (CmpU op1 op2));
11217
11218 format %{ "cmpl $op1, $op2\t# unsigned" %}
11219 opcode(0x81,0x07); /* Opcode 81 /7 */
11220 ins_encode(OpcSErm(op1, op2), Con8or32(op2));
11221 ins_pipe(ialu_cr_reg_imm);
11222 %}
11223
11224 instruct compU_rReg_mem(rFlagsRegU cr, rRegI op1, memory op2)
11225 %{
11226 match(Set cr (CmpU op1 (LoadI op2)));
11227
11228 ins_cost(500); // XXX
11229 format %{ "cmpl $op1, $op2\t# unsigned" %}
11230 opcode(0x3B); /* Opcode 3B /r */
11231 ins_encode(REX_reg_mem(op1, op2), OpcP, reg_mem(op1, op2));
11232 ins_pipe(ialu_cr_reg_mem);
11233 %}
11234
11235 // // // Cisc-spilled version of cmpU_rReg
11236 // //instruct compU_mem_rReg(rFlagsRegU cr, memory op1, rRegI op2)
11237 // //%{
11238 // // match(Set cr (CmpU (LoadI op1) op2));
11239 // //
11240 // // format %{ "CMPu $op1,$op2" %}
11241 // // ins_cost(500);
11242 // // opcode(0x39); /* Opcode 39 /r */
11243 // // ins_encode( OpcP, reg_mem( op1, op2) );
11244 // //%}
11245
11246 instruct testU_reg(rFlagsRegU cr, rRegI src, immI0 zero)
11247 %{
11248 match(Set cr (CmpU src zero));
11249
11250 format %{ "testl $src, $src\t# unsigned" %}
11251 opcode(0x85);
11252 ins_encode(REX_reg_reg(src, src), OpcP, reg_reg(src, src));
11253 ins_pipe(ialu_cr_reg_imm);
11254 %}
11255
11256 instruct compP_rReg(rFlagsRegU cr, rRegP op1, rRegP op2)
11257 %{
11258 match(Set cr (CmpP op1 op2));
11259
11260 format %{ "cmpq $op1, $op2\t# ptr" %}
11261 opcode(0x3B); /* Opcode 3B /r */
11262 ins_encode(REX_reg_reg_wide(op1, op2), OpcP, reg_reg(op1, op2));
11263 ins_pipe(ialu_cr_reg_reg);
11264 %}
11265
11266 instruct compP_rReg_mem(rFlagsRegU cr, rRegP op1, memory op2)
11267 %{
11268 match(Set cr (CmpP op1 (LoadP op2)));
11269
11270 ins_cost(500); // XXX
11271 format %{ "cmpq $op1, $op2\t# ptr" %}
11272 opcode(0x3B); /* Opcode 3B /r */
11273 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2));
11274 ins_pipe(ialu_cr_reg_mem);
11275 %}
11276
11277 // // // Cisc-spilled version of cmpP_rReg
11278 // //instruct compP_mem_rReg(rFlagsRegU cr, memory op1, rRegP op2)
11279 // //%{
11280 // // match(Set cr (CmpP (LoadP op1) op2));
11281 // //
11282 // // format %{ "CMPu $op1,$op2" %}
11283 // // ins_cost(500);
11284 // // opcode(0x39); /* Opcode 39 /r */
11285 // // ins_encode( OpcP, reg_mem( op1, op2) );
11286 // //%}
11287
11288 // XXX this is generalized by compP_rReg_mem???
11289 // Compare raw pointer (used in out-of-heap check).
11290 // Only works because non-oop pointers must be raw pointers
11291 // and raw pointers have no anti-dependencies.
11292 instruct compP_mem_rReg(rFlagsRegU cr, rRegP op1, memory op2)
11293 %{
11294 predicate(n->in(2)->in(2)->bottom_type()->reloc() == relocInfo::none);
11295 match(Set cr (CmpP op1 (LoadP op2)));
11296
11297 format %{ "cmpq $op1, $op2\t# raw ptr" %}
11298 opcode(0x3B); /* Opcode 3B /r */
11299 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2));
11300 ins_pipe(ialu_cr_reg_mem);
11301 %}
11302
11303 // This will generate a signed flags result. This should be OK since
11304 // any compare to a zero should be eq/neq.
11305 instruct testP_reg(rFlagsReg cr, rRegP src, immP0 zero)
11306 %{
11307 match(Set cr (CmpP src zero));
11308
11309 format %{ "testq $src, $src\t# ptr" %}
11310 opcode(0x85);
11311 ins_encode(REX_reg_reg_wide(src, src), OpcP, reg_reg(src, src));
11312 ins_pipe(ialu_cr_reg_imm);
11313 %}
11314
11315 // This will generate a signed flags result. This should be OK since
11316 // any compare to a zero should be eq/neq.
11317 instruct testP_mem(rFlagsReg cr, memory op, immP0 zero)
11318 %{
11319 predicate(!UseCompressedOops || (Universe::narrow_oop_base() != NULL));
11320 match(Set cr (CmpP (LoadP op) zero));
11321
11322 ins_cost(500); // XXX
11323 format %{ "testq $op, 0xffffffffffffffff\t# ptr" %}
11324 opcode(0xF7); /* Opcode F7 /0 */
11325 ins_encode(REX_mem_wide(op),
11326 OpcP, RM_opc_mem(0x00, op), Con_d32(0xFFFFFFFF));
11327 ins_pipe(ialu_cr_reg_imm);
11328 %}
11329
11330 instruct testP_mem_reg0(rFlagsReg cr, memory mem, immP0 zero)
11331 %{
11332 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
11333 match(Set cr (CmpP (LoadP mem) zero));
11334
11335 format %{ "cmpq R12, $mem\t# ptr (R12_heapbase==0)" %}
11336 ins_encode %{
11337 __ cmpq(r12, $mem$$Address);
11338 %}
11339 ins_pipe(ialu_cr_reg_mem);
11340 %}
11341
11342 instruct compN_rReg(rFlagsRegU cr, rRegN op1, rRegN op2)
11343 %{
11344 match(Set cr (CmpN op1 op2));
11345
11346 format %{ "cmpl $op1, $op2\t# compressed ptr" %}
11347 ins_encode %{ __ cmpl($op1$$Register, $op2$$Register); %}
11348 ins_pipe(ialu_cr_reg_reg);
11349 %}
11350
11351 instruct compN_rReg_mem(rFlagsRegU cr, rRegN src, memory mem)
11352 %{
11353 match(Set cr (CmpN src (LoadN mem)));
11354
11355 format %{ "cmpl $src, $mem\t# compressed ptr" %}
11356 ins_encode %{
11357 __ cmpl($src$$Register, $mem$$Address);
11358 %}
11359 ins_pipe(ialu_cr_reg_mem);
11360 %}
11361
11362 instruct compN_rReg_imm(rFlagsRegU cr, rRegN op1, immN op2) %{
11363 match(Set cr (CmpN op1 op2));
11364
11365 format %{ "cmpl $op1, $op2\t# compressed ptr" %}
11366 ins_encode %{
11367 __ cmp_narrow_oop($op1$$Register, (jobject)$op2$$constant);
11368 %}
11369 ins_pipe(ialu_cr_reg_imm);
11370 %}
11371
11372 instruct compN_mem_imm(rFlagsRegU cr, memory mem, immN src)
11373 %{
11374 match(Set cr (CmpN src (LoadN mem)));
11375
11376 format %{ "cmpl $mem, $src\t# compressed ptr" %}
11377 ins_encode %{
11378 __ cmp_narrow_oop($mem$$Address, (jobject)$src$$constant);
11379 %}
11380 ins_pipe(ialu_cr_reg_mem);
11381 %}
11382
11383 instruct compN_rReg_imm_klass(rFlagsRegU cr, rRegN op1, immNKlass op2) %{
11384 match(Set cr (CmpN op1 op2));
11385
11386 format %{ "cmpl $op1, $op2\t# compressed klass ptr" %}
11387 ins_encode %{
11388 __ cmp_narrow_klass($op1$$Register, (Klass*)$op2$$constant);
11389 %}
11390 ins_pipe(ialu_cr_reg_imm);
11391 %}
11392
11393 instruct compN_mem_imm_klass(rFlagsRegU cr, memory mem, immNKlass src)
11394 %{
11395 match(Set cr (CmpN src (LoadNKlass mem)));
11396
11397 format %{ "cmpl $mem, $src\t# compressed klass ptr" %}
11398 ins_encode %{
11399 __ cmp_narrow_klass($mem$$Address, (Klass*)$src$$constant);
11400 %}
11401 ins_pipe(ialu_cr_reg_mem);
11402 %}
11403
11404 instruct testN_reg(rFlagsReg cr, rRegN src, immN0 zero) %{
11405 match(Set cr (CmpN src zero));
11406
11407 format %{ "testl $src, $src\t# compressed ptr" %}
11408 ins_encode %{ __ testl($src$$Register, $src$$Register); %}
11409 ins_pipe(ialu_cr_reg_imm);
11410 %}
11411
11412 instruct testN_mem(rFlagsReg cr, memory mem, immN0 zero)
11413 %{
11414 predicate(Universe::narrow_oop_base() != NULL);
11415 match(Set cr (CmpN (LoadN mem) zero));
11416
11417 ins_cost(500); // XXX
11418 format %{ "testl $mem, 0xffffffff\t# compressed ptr" %}
11419 ins_encode %{
11420 __ cmpl($mem$$Address, (int)0xFFFFFFFF);
11421 %}
11422 ins_pipe(ialu_cr_reg_mem);
11423 %}
11424
11425 instruct testN_mem_reg0(rFlagsReg cr, memory mem, immN0 zero)
11426 %{
11427 predicate(Universe::narrow_oop_base() == NULL && (Universe::narrow_klass_base() == NULL));
11428 match(Set cr (CmpN (LoadN mem) zero));
11429
11430 format %{ "cmpl R12, $mem\t# compressed ptr (R12_heapbase==0)" %}
11431 ins_encode %{
11432 __ cmpl(r12, $mem$$Address);
11433 %}
11434 ins_pipe(ialu_cr_reg_mem);
11435 %}
11436
11437 // Yanked all unsigned pointer compare operations.
11438 // Pointer compares are done with CmpP which is already unsigned.
11439
11440 instruct compL_rReg(rFlagsReg cr, rRegL op1, rRegL op2)
11441 %{
11442 match(Set cr (CmpL op1 op2));
11443
11444 format %{ "cmpq $op1, $op2" %}
11445 opcode(0x3B); /* Opcode 3B /r */
11446 ins_encode(REX_reg_reg_wide(op1, op2), OpcP, reg_reg(op1, op2));
11447 ins_pipe(ialu_cr_reg_reg);
11448 %}
11449
11450 instruct compL_rReg_imm(rFlagsReg cr, rRegL op1, immL32 op2)
11451 %{
11452 match(Set cr (CmpL op1 op2));
11453
11454 format %{ "cmpq $op1, $op2" %}
11455 opcode(0x81, 0x07); /* Opcode 81 /7 */
11456 ins_encode(OpcSErm_wide(op1, op2), Con8or32(op2));
11457 ins_pipe(ialu_cr_reg_imm);
11458 %}
11459
11460 instruct compL_rReg_mem(rFlagsReg cr, rRegL op1, memory op2)
11461 %{
11462 match(Set cr (CmpL op1 (LoadL op2)));
11463
11464 format %{ "cmpq $op1, $op2" %}
11465 opcode(0x3B); /* Opcode 3B /r */
11466 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2));
11467 ins_pipe(ialu_cr_reg_mem);
11468 %}
11469
11470 instruct testL_reg(rFlagsReg cr, rRegL src, immL0 zero)
11471 %{
11472 match(Set cr (CmpL src zero));
11473
11474 format %{ "testq $src, $src" %}
11475 opcode(0x85);
11476 ins_encode(REX_reg_reg_wide(src, src), OpcP, reg_reg(src, src));
11477 ins_pipe(ialu_cr_reg_imm);
11478 %}
11479
11480 instruct testL_reg_imm(rFlagsReg cr, rRegL src, immL32 con, immL0 zero)
11481 %{
11482 match(Set cr (CmpL (AndL src con) zero));
11483
11484 format %{ "testq $src, $con\t# long" %}
11485 opcode(0xF7, 0x00);
11486 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src), Con32(con));
11487 ins_pipe(ialu_cr_reg_imm);
11488 %}
11489
11490 instruct testL_reg_mem(rFlagsReg cr, rRegL src, memory mem, immL0 zero)
11491 %{
11492 match(Set cr (CmpL (AndL src (LoadL mem)) zero));
11493
11494 format %{ "testq $src, $mem" %}
11495 opcode(0x85);
11496 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem));
11497 ins_pipe(ialu_cr_reg_mem);
11498 %}
11499
11500 // Manifest a CmpL result in an integer register. Very painful.
11501 // This is the test to avoid.
11502 instruct cmpL3_reg_reg(rRegI dst, rRegL src1, rRegL src2, rFlagsReg flags)
11503 %{
11504 match(Set dst (CmpL3 src1 src2));
11505 effect(KILL flags);
11506
11507 ins_cost(275); // XXX
11508 format %{ "cmpq $src1, $src2\t# CmpL3\n\t"
11509 "movl $dst, -1\n\t"
11510 "jl,s done\n\t"
11511 "setne $dst\n\t"
11512 "movzbl $dst, $dst\n\t"
11513 "done:" %}
11514 ins_encode(cmpl3_flag(src1, src2, dst));
11515 ins_pipe(pipe_slow);
11516 %}
11517
11518 //----------Max and Min--------------------------------------------------------
11519 // Min Instructions
11520
11521 instruct cmovI_reg_g(rRegI dst, rRegI src, rFlagsReg cr)
11522 %{
11523 effect(USE_DEF dst, USE src, USE cr);
11524
11525 format %{ "cmovlgt $dst, $src\t# min" %}
11526 opcode(0x0F, 0x4F);
11527 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
11528 ins_pipe(pipe_cmov_reg);
11529 %}
11530
11531
11532 instruct minI_rReg(rRegI dst, rRegI src)
11533 %{
11534 match(Set dst (MinI dst src));
11535
11536 ins_cost(200);
11537 expand %{
11538 rFlagsReg cr;
11539 compI_rReg(cr, dst, src);
11540 cmovI_reg_g(dst, src, cr);
11541 %}
11542 %}
11543
11544 instruct cmovI_reg_l(rRegI dst, rRegI src, rFlagsReg cr)
11545 %{
11546 effect(USE_DEF dst, USE src, USE cr);
11547
11548 format %{ "cmovllt $dst, $src\t# max" %}
11549 opcode(0x0F, 0x4C);
11550 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
11551 ins_pipe(pipe_cmov_reg);
11552 %}
11553
11554
11555 instruct maxI_rReg(rRegI dst, rRegI src)
11556 %{
11557 match(Set dst (MaxI dst src));
11558
11559 ins_cost(200);
11560 expand %{
11561 rFlagsReg cr;
11562 compI_rReg(cr, dst, src);
11563 cmovI_reg_l(dst, src, cr);
11564 %}
11565 %}
11566
11567 // ============================================================================
11568 // Branch Instructions
11569
11570 // Jump Direct - Label defines a relative address from JMP+1
11571 instruct jmpDir(label labl)
11572 %{
11573 match(Goto);
11574 effect(USE labl);
11575
11576 ins_cost(300);
11577 format %{ "jmp $labl" %}
11578 size(5);
11579 ins_encode %{
11580 Label* L = $labl$$label;
11581 __ jmp(*L, false); // Always long jump
11582 %}
11583 ins_pipe(pipe_jmp);
11584 %}
11585
11586 // Jump Direct Conditional - Label defines a relative address from Jcc+1
11587 instruct jmpCon(cmpOp cop, rFlagsReg cr, label labl)
11588 %{
11589 match(If cop cr);
11590 effect(USE labl);
11591
11592 ins_cost(300);
11593 format %{ "j$cop $labl" %}
11594 size(6);
11595 ins_encode %{
11596 Label* L = $labl$$label;
11597 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
11598 %}
11599 ins_pipe(pipe_jcc);
11600 %}
11601
11602 // Jump Direct Conditional - Label defines a relative address from Jcc+1
11603 instruct jmpLoopEnd(cmpOp cop, rFlagsReg cr, label labl)
11604 %{
11605 predicate(!n->has_vector_mask_set());
11606 match(CountedLoopEnd cop cr);
11607 effect(USE labl);
11608
11609 ins_cost(300);
11610 format %{ "j$cop $labl\t# loop end" %}
11611 size(6);
11612 ins_encode %{
11613 Label* L = $labl$$label;
11614 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
11615 %}
11616 ins_pipe(pipe_jcc);
11617 %}
11618
11619 // Jump Direct Conditional - Label defines a relative address from Jcc+1
11620 instruct jmpLoopEndU(cmpOpU cop, rFlagsRegU cmp, label labl) %{
11621 predicate(!n->has_vector_mask_set());
11622 match(CountedLoopEnd cop cmp);
11623 effect(USE labl);
11624
11625 ins_cost(300);
11626 format %{ "j$cop,u $labl\t# loop end" %}
11627 size(6);
11628 ins_encode %{
11629 Label* L = $labl$$label;
11630 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
11631 %}
11632 ins_pipe(pipe_jcc);
11633 %}
11634
11635 instruct jmpLoopEndUCF(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
11636 predicate(!n->has_vector_mask_set());
11637 match(CountedLoopEnd cop cmp);
11638 effect(USE labl);
11639
11640 ins_cost(200);
11641 format %{ "j$cop,u $labl\t# loop end" %}
11642 size(6);
11643 ins_encode %{
11644 Label* L = $labl$$label;
11645 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
11646 %}
11647 ins_pipe(pipe_jcc);
11648 %}
11649
11650 // mask version
11651 // Jump Direct Conditional - Label defines a relative address from Jcc+1
11652 instruct jmpLoopEnd_and_restoreMask(cmpOp cop, rFlagsReg cr, label labl)
11653 %{
11654 predicate(n->has_vector_mask_set());
11655 match(CountedLoopEnd cop cr);
11656 effect(USE labl);
11657
11658 ins_cost(400);
11659 format %{ "j$cop $labl\t# loop end\n\t"
11660 "restorevectmask \t# vector mask restore for loops" %}
11661 size(10);
11662 ins_encode %{
11663 Label* L = $labl$$label;
11664 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
11665 __ restorevectmask();
11666 %}
11667 ins_pipe(pipe_jcc);
11668 %}
11669
11670 // Jump Direct Conditional - Label defines a relative address from Jcc+1
11671 instruct jmpLoopEndU_and_restoreMask(cmpOpU cop, rFlagsRegU cmp, label labl) %{
11672 predicate(n->has_vector_mask_set());
11673 match(CountedLoopEnd cop cmp);
11674 effect(USE labl);
11675
11676 ins_cost(400);
11677 format %{ "j$cop,u $labl\t# loop end\n\t"
11678 "restorevectmask \t# vector mask restore for loops" %}
11679 size(10);
11680 ins_encode %{
11681 Label* L = $labl$$label;
11682 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
11683 __ restorevectmask();
11684 %}
11685 ins_pipe(pipe_jcc);
11686 %}
11687
11688 instruct jmpLoopEndUCF_and_restoreMask(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
11689 predicate(n->has_vector_mask_set());
11690 match(CountedLoopEnd cop cmp);
11691 effect(USE labl);
11692
11693 ins_cost(300);
11694 format %{ "j$cop,u $labl\t# loop end\n\t"
11695 "restorevectmask \t# vector mask restore for loops" %}
11696 size(10);
11697 ins_encode %{
11698 Label* L = $labl$$label;
11699 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
11700 __ restorevectmask();
11701 %}
11702 ins_pipe(pipe_jcc);
11703 %}
11704
11705 // Jump Direct Conditional - using unsigned comparison
11706 instruct jmpConU(cmpOpU cop, rFlagsRegU cmp, label labl) %{
11707 match(If cop cmp);
11708 effect(USE labl);
11709
11710 ins_cost(300);
11711 format %{ "j$cop,u $labl" %}
11712 size(6);
11713 ins_encode %{
11714 Label* L = $labl$$label;
11715 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
11716 %}
11717 ins_pipe(pipe_jcc);
11718 %}
11719
11720 instruct jmpConUCF(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
11721 match(If cop cmp);
11722 effect(USE labl);
11723
11724 ins_cost(200);
11725 format %{ "j$cop,u $labl" %}
11726 size(6);
11727 ins_encode %{
11728 Label* L = $labl$$label;
11729 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
11730 %}
11731 ins_pipe(pipe_jcc);
11732 %}
11733
11734 instruct jmpConUCF2(cmpOpUCF2 cop, rFlagsRegUCF cmp, label labl) %{
11735 match(If cop cmp);
11736 effect(USE labl);
11737
11738 ins_cost(200);
11739 format %{ $$template
11740 if ($cop$$cmpcode == Assembler::notEqual) {
11741 $$emit$$"jp,u $labl\n\t"
11742 $$emit$$"j$cop,u $labl"
11743 } else {
11744 $$emit$$"jp,u done\n\t"
11745 $$emit$$"j$cop,u $labl\n\t"
11746 $$emit$$"done:"
11747 }
11748 %}
11749 ins_encode %{
11750 Label* l = $labl$$label;
11751 if ($cop$$cmpcode == Assembler::notEqual) {
11752 __ jcc(Assembler::parity, *l, false);
11753 __ jcc(Assembler::notEqual, *l, false);
11754 } else if ($cop$$cmpcode == Assembler::equal) {
11755 Label done;
11756 __ jccb(Assembler::parity, done);
11757 __ jcc(Assembler::equal, *l, false);
11758 __ bind(done);
11759 } else {
11760 ShouldNotReachHere();
11761 }
11762 %}
11763 ins_pipe(pipe_jcc);
11764 %}
11765
11766 // ============================================================================
11767 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary
11768 // superklass array for an instance of the superklass. Set a hidden
11769 // internal cache on a hit (cache is checked with exposed code in
11770 // gen_subtype_check()). Return NZ for a miss or zero for a hit. The
11771 // encoding ALSO sets flags.
11772
11773 instruct partialSubtypeCheck(rdi_RegP result,
11774 rsi_RegP sub, rax_RegP super, rcx_RegI rcx,
11775 rFlagsReg cr)
11776 %{
11777 match(Set result (PartialSubtypeCheck sub super));
11778 effect(KILL rcx, KILL cr);
11779
11780 ins_cost(1100); // slightly larger than the next version
11781 format %{ "movq rdi, [$sub + in_bytes(Klass::secondary_supers_offset())]\n\t"
11782 "movl rcx, [rdi + Array<Klass*>::length_offset_in_bytes()]\t# length to scan\n\t"
11783 "addq rdi, Array<Klass*>::base_offset_in_bytes()\t# Skip to start of data; set NZ in case count is zero\n\t"
11784 "repne scasq\t# Scan *rdi++ for a match with rax while rcx--\n\t"
11785 "jne,s miss\t\t# Missed: rdi not-zero\n\t"
11786 "movq [$sub + in_bytes(Klass::secondary_super_cache_offset())], $super\t# Hit: update cache\n\t"
11787 "xorq $result, $result\t\t Hit: rdi zero\n\t"
11788 "miss:\t" %}
11789
11790 opcode(0x1); // Force a XOR of RDI
11791 ins_encode(enc_PartialSubtypeCheck());
11792 ins_pipe(pipe_slow);
11793 %}
11794
11795 instruct partialSubtypeCheck_vs_Zero(rFlagsReg cr,
11796 rsi_RegP sub, rax_RegP super, rcx_RegI rcx,
11797 immP0 zero,
11798 rdi_RegP result)
11799 %{
11800 match(Set cr (CmpP (PartialSubtypeCheck sub super) zero));
11801 effect(KILL rcx, KILL result);
11802
11803 ins_cost(1000);
11804 format %{ "movq rdi, [$sub + in_bytes(Klass::secondary_supers_offset())]\n\t"
11805 "movl rcx, [rdi + Array<Klass*>::length_offset_in_bytes()]\t# length to scan\n\t"
11806 "addq rdi, Array<Klass*>::base_offset_in_bytes()\t# Skip to start of data; set NZ in case count is zero\n\t"
11807 "repne scasq\t# Scan *rdi++ for a match with rax while cx-- != 0\n\t"
11808 "jne,s miss\t\t# Missed: flags nz\n\t"
11809 "movq [$sub + in_bytes(Klass::secondary_super_cache_offset())], $super\t# Hit: update cache\n\t"
11810 "miss:\t" %}
11811
11812 opcode(0x0); // No need to XOR RDI
11813 ins_encode(enc_PartialSubtypeCheck());
11814 ins_pipe(pipe_slow);
11815 %}
11816
11817 // ============================================================================
11818 // Branch Instructions -- short offset versions
11819 //
11820 // These instructions are used to replace jumps of a long offset (the default
11821 // match) with jumps of a shorter offset. These instructions are all tagged
11822 // with the ins_short_branch attribute, which causes the ADLC to suppress the
11823 // match rules in general matching. Instead, the ADLC generates a conversion
11824 // method in the MachNode which can be used to do in-place replacement of the
11825 // long variant with the shorter variant. The compiler will determine if a
11826 // branch can be taken by the is_short_branch_offset() predicate in the machine
11827 // specific code section of the file.
11828
11829 // Jump Direct - Label defines a relative address from JMP+1
11830 instruct jmpDir_short(label labl) %{
11831 match(Goto);
11832 effect(USE labl);
11833
11834 ins_cost(300);
11835 format %{ "jmp,s $labl" %}
11836 size(2);
11837 ins_encode %{
11838 Label* L = $labl$$label;
11839 __ jmpb(*L);
11840 %}
11841 ins_pipe(pipe_jmp);
11842 ins_short_branch(1);
11843 %}
11844
11845 // Jump Direct Conditional - Label defines a relative address from Jcc+1
11846 instruct jmpCon_short(cmpOp cop, rFlagsReg cr, label labl) %{
11847 match(If cop cr);
11848 effect(USE labl);
11849
11850 ins_cost(300);
11851 format %{ "j$cop,s $labl" %}
11852 size(2);
11853 ins_encode %{
11854 Label* L = $labl$$label;
11855 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
11856 %}
11857 ins_pipe(pipe_jcc);
11858 ins_short_branch(1);
11859 %}
11860
11861 // Jump Direct Conditional - Label defines a relative address from Jcc+1
11862 instruct jmpLoopEnd_short(cmpOp cop, rFlagsReg cr, label labl) %{
11863 match(CountedLoopEnd cop cr);
11864 effect(USE labl);
11865
11866 ins_cost(300);
11867 format %{ "j$cop,s $labl\t# loop end" %}
11868 size(2);
11869 ins_encode %{
11870 Label* L = $labl$$label;
11871 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
11872 %}
11873 ins_pipe(pipe_jcc);
11874 ins_short_branch(1);
11875 %}
11876
11877 // Jump Direct Conditional - Label defines a relative address from Jcc+1
11878 instruct jmpLoopEndU_short(cmpOpU cop, rFlagsRegU cmp, label labl) %{
11879 match(CountedLoopEnd cop cmp);
11880 effect(USE labl);
11881
11882 ins_cost(300);
11883 format %{ "j$cop,us $labl\t# loop end" %}
11884 size(2);
11885 ins_encode %{
11886 Label* L = $labl$$label;
11887 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
11888 %}
11889 ins_pipe(pipe_jcc);
11890 ins_short_branch(1);
11891 %}
11892
11893 instruct jmpLoopEndUCF_short(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
11894 match(CountedLoopEnd cop cmp);
11895 effect(USE labl);
11896
11897 ins_cost(300);
11898 format %{ "j$cop,us $labl\t# loop end" %}
11899 size(2);
11900 ins_encode %{
11901 Label* L = $labl$$label;
11902 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
11903 %}
11904 ins_pipe(pipe_jcc);
11905 ins_short_branch(1);
11906 %}
11907
11908 // Jump Direct Conditional - using unsigned comparison
11909 instruct jmpConU_short(cmpOpU cop, rFlagsRegU cmp, label labl) %{
11910 match(If cop cmp);
11911 effect(USE labl);
11912
11913 ins_cost(300);
11914 format %{ "j$cop,us $labl" %}
11915 size(2);
11916 ins_encode %{
11917 Label* L = $labl$$label;
11918 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
11919 %}
11920 ins_pipe(pipe_jcc);
11921 ins_short_branch(1);
11922 %}
11923
11924 instruct jmpConUCF_short(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
11925 match(If cop cmp);
11926 effect(USE labl);
11927
11928 ins_cost(300);
11929 format %{ "j$cop,us $labl" %}
11930 size(2);
11931 ins_encode %{
11932 Label* L = $labl$$label;
11933 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
11934 %}
11935 ins_pipe(pipe_jcc);
11936 ins_short_branch(1);
11937 %}
11938
11939 instruct jmpConUCF2_short(cmpOpUCF2 cop, rFlagsRegUCF cmp, label labl) %{
11940 match(If cop cmp);
11941 effect(USE labl);
11942
11943 ins_cost(300);
11944 format %{ $$template
11945 if ($cop$$cmpcode == Assembler::notEqual) {
11946 $$emit$$"jp,u,s $labl\n\t"
11947 $$emit$$"j$cop,u,s $labl"
11948 } else {
11949 $$emit$$"jp,u,s done\n\t"
11950 $$emit$$"j$cop,u,s $labl\n\t"
11951 $$emit$$"done:"
11952 }
11953 %}
11954 size(4);
11955 ins_encode %{
11956 Label* l = $labl$$label;
11957 if ($cop$$cmpcode == Assembler::notEqual) {
11958 __ jccb(Assembler::parity, *l);
11959 __ jccb(Assembler::notEqual, *l);
11960 } else if ($cop$$cmpcode == Assembler::equal) {
11961 Label done;
11962 __ jccb(Assembler::parity, done);
11963 __ jccb(Assembler::equal, *l);
11964 __ bind(done);
11965 } else {
11966 ShouldNotReachHere();
11967 }
11968 %}
11969 ins_pipe(pipe_jcc);
11970 ins_short_branch(1);
11971 %}
11972
11973 // ============================================================================
11974 // inlined locking and unlocking
11975
11976 instruct cmpFastLockRTM(rFlagsReg cr, rRegP object, rbx_RegP box, rax_RegI tmp, rdx_RegI scr, rRegI cx1, rRegI cx2) %{
11977 predicate(Compile::current()->use_rtm());
11978 match(Set cr (FastLock object box));
11979 effect(TEMP tmp, TEMP scr, TEMP cx1, TEMP cx2, USE_KILL box);
11980 ins_cost(300);
11981 format %{ "fastlock $object,$box\t! kills $box,$tmp,$scr,$cx1,$cx2" %}
11982 ins_encode %{
11983 __ fast_lock($object$$Register, $box$$Register, $tmp$$Register,
11984 $scr$$Register, $cx1$$Register, $cx2$$Register,
11985 _counters, _rtm_counters, _stack_rtm_counters,
11986 ((Method*)(ra_->C->method()->constant_encoding()))->method_data(),
11987 true, ra_->C->profile_rtm());
11988 %}
11989 ins_pipe(pipe_slow);
11990 %}
11991
11992 instruct cmpFastLock(rFlagsReg cr, rRegP object, rbx_RegP box, rax_RegI tmp, rRegP scr) %{
11993 predicate(!Compile::current()->use_rtm());
11994 match(Set cr (FastLock object box));
11995 effect(TEMP tmp, TEMP scr, USE_KILL box);
11996 ins_cost(300);
11997 format %{ "fastlock $object,$box\t! kills $box,$tmp,$scr" %}
11998 ins_encode %{
11999 __ fast_lock($object$$Register, $box$$Register, $tmp$$Register,
12000 $scr$$Register, noreg, noreg, _counters, NULL, NULL, NULL, false, false);
12001 %}
12002 ins_pipe(pipe_slow);
12003 %}
12004
12005 instruct cmpFastUnlock(rFlagsReg cr, rRegP object, rax_RegP box, rRegP tmp) %{
12006 match(Set cr (FastUnlock object box));
12007 effect(TEMP tmp, USE_KILL box);
12008 ins_cost(300);
12009 format %{ "fastunlock $object,$box\t! kills $box,$tmp" %}
12010 ins_encode %{
12011 __ fast_unlock($object$$Register, $box$$Register, $tmp$$Register, ra_->C->use_rtm());
12012 %}
12013 ins_pipe(pipe_slow);
12014 %}
12015
12016
12017 // ============================================================================
12018 // Safepoint Instructions
12019 instruct safePoint_poll(rFlagsReg cr)
12020 %{
12021 predicate(!Assembler::is_polling_page_far());
12022 match(SafePoint);
12023 effect(KILL cr);
12024
12025 format %{ "testl rax, [rip + #offset_to_poll_page]\t"
12026 "# Safepoint: poll for GC" %}
12027 ins_cost(125);
12028 ins_encode %{
12029 AddressLiteral addr(os::get_polling_page(), relocInfo::poll_type);
12030 __ testl(rax, addr);
12031 %}
12032 ins_pipe(ialu_reg_mem);
12033 %}
12034
12035 instruct safePoint_poll_far(rFlagsReg cr, rRegP poll)
12036 %{
12037 predicate(Assembler::is_polling_page_far());
12038 match(SafePoint poll);
12039 effect(KILL cr, USE poll);
12040
12041 format %{ "testl rax, [$poll]\t"
12042 "# Safepoint: poll for GC" %}
12043 ins_cost(125);
12044 ins_encode %{
12045 __ relocate(relocInfo::poll_type);
12046 __ testl(rax, Address($poll$$Register, 0));
12047 %}
12048 ins_pipe(ialu_reg_mem);
12049 %}
12050
12051 // ============================================================================
12052 // Procedure Call/Return Instructions
12053 // Call Java Static Instruction
12054 // Note: If this code changes, the corresponding ret_addr_offset() and
12055 // compute_padding() functions will have to be adjusted.
12056 instruct CallStaticJavaDirect(method meth) %{
12057 match(CallStaticJava);
12058 effect(USE meth);
12059
12060 ins_cost(300);
12061 format %{ "call,static " %}
12062 opcode(0xE8); /* E8 cd */
12063 ins_encode(clear_avx, Java_Static_Call(meth), call_epilog);
12064 ins_pipe(pipe_slow);
12065 ins_alignment(4);
12066 %}
12067
12068 // Call Java Dynamic Instruction
12069 // Note: If this code changes, the corresponding ret_addr_offset() and
12070 // compute_padding() functions will have to be adjusted.
12071 instruct CallDynamicJavaDirect(method meth)
12072 %{
12073 match(CallDynamicJava);
12074 effect(USE meth);
12075
12076 ins_cost(300);
12077 format %{ "movq rax, #Universe::non_oop_word()\n\t"
12078 "call,dynamic " %}
12079 ins_encode(clear_avx, Java_Dynamic_Call(meth), call_epilog);
12080 ins_pipe(pipe_slow);
12081 ins_alignment(4);
12082 %}
12083
12084 // Call Runtime Instruction
12085 instruct CallRuntimeDirect(method meth)
12086 %{
12087 match(CallRuntime);
12088 effect(USE meth);
12089
12090 ins_cost(300);
12091 format %{ "call,runtime " %}
12092 ins_encode(clear_avx, Java_To_Runtime(meth));
12093 ins_pipe(pipe_slow);
12094 %}
12095
12096 // Call runtime without safepoint
12097 instruct CallLeafDirect(method meth)
12098 %{
12099 match(CallLeaf);
12100 effect(USE meth);
12101
12102 ins_cost(300);
12103 format %{ "call_leaf,runtime " %}
12104 ins_encode(clear_avx, Java_To_Runtime(meth));
12105 ins_pipe(pipe_slow);
12106 %}
12107
12108 // Call runtime without safepoint
12109 instruct CallLeafNoFPDirect(method meth)
12110 %{
12111 match(CallLeafNoFP);
12112 effect(USE meth);
12113
12114 ins_cost(300);
12115 format %{ "call_leaf_nofp,runtime " %}
12116 ins_encode(Java_To_Runtime(meth));
12117 ins_pipe(pipe_slow);
12118 %}
12119
12120 // Return Instruction
12121 // Remove the return address & jump to it.
12122 // Notice: We always emit a nop after a ret to make sure there is room
12123 // for safepoint patching
12124 instruct Ret()
12125 %{
12126 match(Return);
12127
12128 format %{ "ret" %}
12129 opcode(0xC3);
12130 ins_encode(OpcP);
12131 ins_pipe(pipe_jmp);
12132 %}
12133
12134 // Tail Call; Jump from runtime stub to Java code.
12135 // Also known as an 'interprocedural jump'.
12136 // Target of jump will eventually return to caller.
12137 // TailJump below removes the return address.
12138 instruct TailCalljmpInd(no_rbp_RegP jump_target, rbx_RegP method_oop)
12139 %{
12140 match(TailCall jump_target method_oop);
12141
12142 ins_cost(300);
12143 format %{ "jmp $jump_target\t# rbx holds method oop" %}
12144 opcode(0xFF, 0x4); /* Opcode FF /4 */
12145 ins_encode(REX_reg(jump_target), OpcP, reg_opc(jump_target));
12146 ins_pipe(pipe_jmp);
12147 %}
12148
12149 // Tail Jump; remove the return address; jump to target.
12150 // TailCall above leaves the return address around.
12151 instruct tailjmpInd(no_rbp_RegP jump_target, rax_RegP ex_oop)
12152 %{
12153 match(TailJump jump_target ex_oop);
12154
12155 ins_cost(300);
12156 format %{ "popq rdx\t# pop return address\n\t"
12157 "jmp $jump_target" %}
12158 opcode(0xFF, 0x4); /* Opcode FF /4 */
12159 ins_encode(Opcode(0x5a), // popq rdx
12160 REX_reg(jump_target), OpcP, reg_opc(jump_target));
12161 ins_pipe(pipe_jmp);
12162 %}
12163
12164 // Create exception oop: created by stack-crawling runtime code.
12165 // Created exception is now available to this handler, and is setup
12166 // just prior to jumping to this handler. No code emitted.
12167 instruct CreateException(rax_RegP ex_oop)
12168 %{
12169 match(Set ex_oop (CreateEx));
12170
12171 size(0);
12172 // use the following format syntax
12173 format %{ "# exception oop is in rax; no code emitted" %}
12174 ins_encode();
12175 ins_pipe(empty);
12176 %}
12177
12178 // Rethrow exception:
12179 // The exception oop will come in the first argument position.
12180 // Then JUMP (not call) to the rethrow stub code.
12181 instruct RethrowException()
12182 %{
12183 match(Rethrow);
12184
12185 // use the following format syntax
12186 format %{ "jmp rethrow_stub" %}
12187 ins_encode(enc_rethrow);
12188 ins_pipe(pipe_jmp);
12189 %}
12190
12191
12192 // ============================================================================
12193 // This name is KNOWN by the ADLC and cannot be changed.
12194 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
12195 // for this guy.
12196 instruct tlsLoadP(r15_RegP dst) %{
12197 match(Set dst (ThreadLocal));
12198 effect(DEF dst);
12199
12200 size(0);
12201 format %{ "# TLS is in R15" %}
12202 ins_encode( /*empty encoding*/ );
12203 ins_pipe(ialu_reg_reg);
12204 %}
12205
12206
12207 //----------PEEPHOLE RULES-----------------------------------------------------
12208 // These must follow all instruction definitions as they use the names
12209 // defined in the instructions definitions.
12210 //
12211 // peepmatch ( root_instr_name [preceding_instruction]* );
12212 //
12213 // peepconstraint %{
12214 // (instruction_number.operand_name relational_op instruction_number.operand_name
12215 // [, ...] );
12216 // // instruction numbers are zero-based using left to right order in peepmatch
12217 //
12218 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
12219 // // provide an instruction_number.operand_name for each operand that appears
12220 // // in the replacement instruction's match rule
12221 //
12222 // ---------VM FLAGS---------------------------------------------------------
12223 //
12224 // All peephole optimizations can be turned off using -XX:-OptoPeephole
12225 //
12226 // Each peephole rule is given an identifying number starting with zero and
12227 // increasing by one in the order seen by the parser. An individual peephole
12228 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
12229 // on the command-line.
12230 //
12231 // ---------CURRENT LIMITATIONS----------------------------------------------
12232 //
12233 // Only match adjacent instructions in same basic block
12234 // Only equality constraints
12235 // Only constraints between operands, not (0.dest_reg == RAX_enc)
12236 // Only one replacement instruction
12237 //
12238 // ---------EXAMPLE----------------------------------------------------------
12239 //
12240 // // pertinent parts of existing instructions in architecture description
12241 // instruct movI(rRegI dst, rRegI src)
12242 // %{
12243 // match(Set dst (CopyI src));
12244 // %}
12245 //
12246 // instruct incI_rReg(rRegI dst, immI1 src, rFlagsReg cr)
12247 // %{
12248 // match(Set dst (AddI dst src));
12249 // effect(KILL cr);
12250 // %}
12251 //
12252 // // Change (inc mov) to lea
12253 // peephole %{
12254 // // increment preceeded by register-register move
12255 // peepmatch ( incI_rReg movI );
12256 // // require that the destination register of the increment
12257 // // match the destination register of the move
12258 // peepconstraint ( 0.dst == 1.dst );
12259 // // construct a replacement instruction that sets
12260 // // the destination to ( move's source register + one )
12261 // peepreplace ( leaI_rReg_immI( 0.dst 1.src 0.src ) );
12262 // %}
12263 //
12264
12265 // Implementation no longer uses movX instructions since
12266 // machine-independent system no longer uses CopyX nodes.
12267 //
12268 // peephole
12269 // %{
12270 // peepmatch (incI_rReg movI);
12271 // peepconstraint (0.dst == 1.dst);
12272 // peepreplace (leaI_rReg_immI(0.dst 1.src 0.src));
12273 // %}
12274
12275 // peephole
12276 // %{
12277 // peepmatch (decI_rReg movI);
12278 // peepconstraint (0.dst == 1.dst);
12279 // peepreplace (leaI_rReg_immI(0.dst 1.src 0.src));
12280 // %}
12281
12282 // peephole
12283 // %{
12284 // peepmatch (addI_rReg_imm movI);
12285 // peepconstraint (0.dst == 1.dst);
12286 // peepreplace (leaI_rReg_immI(0.dst 1.src 0.src));
12287 // %}
12288
12289 // peephole
12290 // %{
12291 // peepmatch (incL_rReg movL);
12292 // peepconstraint (0.dst == 1.dst);
12293 // peepreplace (leaL_rReg_immL(0.dst 1.src 0.src));
12294 // %}
12295
12296 // peephole
12297 // %{
12298 // peepmatch (decL_rReg movL);
12299 // peepconstraint (0.dst == 1.dst);
12300 // peepreplace (leaL_rReg_immL(0.dst 1.src 0.src));
12301 // %}
12302
12303 // peephole
12304 // %{
12305 // peepmatch (addL_rReg_imm movL);
12306 // peepconstraint (0.dst == 1.dst);
12307 // peepreplace (leaL_rReg_immL(0.dst 1.src 0.src));
12308 // %}
12309
12310 // peephole
12311 // %{
12312 // peepmatch (addP_rReg_imm movP);
12313 // peepconstraint (0.dst == 1.dst);
12314 // peepreplace (leaP_rReg_imm(0.dst 1.src 0.src));
12315 // %}
12316
12317 // // Change load of spilled value to only a spill
12318 // instruct storeI(memory mem, rRegI src)
12319 // %{
12320 // match(Set mem (StoreI mem src));
12321 // %}
12322 //
12323 // instruct loadI(rRegI dst, memory mem)
12324 // %{
12325 // match(Set dst (LoadI mem));
12326 // %}
12327 //
12328
12329 peephole
12330 %{
12331 peepmatch (loadI storeI);
12332 peepconstraint (1.src == 0.dst, 1.mem == 0.mem);
12333 peepreplace (storeI(1.mem 1.mem 1.src));
12334 %}
12335
12336 peephole
12337 %{
12338 peepmatch (loadL storeL);
12339 peepconstraint (1.src == 0.dst, 1.mem == 0.mem);
12340 peepreplace (storeL(1.mem 1.mem 1.src));
12341 %}
12342
12343 //----------SMARTSPILL RULES---------------------------------------------------
12344 // These must follow all instruction definitions as they use the names
12345 // defined in the instructions definitions.