1 /*
   2  * Copyright (c) 1997, 2017, Oracle and/or its affiliates. All rights reserved.
   3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   4  *
   5  * This code is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 only, as
   7  * published by the Free Software Foundation.
   8  *
   9  * This code is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * version 2 for more details (a copy is included in the LICENSE file that
  13  * accompanied this code).
  14  *
  15  * You should have received a copy of the GNU General Public License version
  16  * 2 along with this work; if not, write to the Free Software Foundation,
  17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  18  *
  19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  20  * or visit www.oracle.com if you need additional information or have any
  21  * questions.
  22  *
  23  */
  24 
  25 #include "precompiled.hpp"
  26 #include "asm/assembler.hpp"
  27 #include "asm/assembler.inline.hpp"
  28 #include "compiler/disassembler.hpp"
  29 #include "gc/shared/cardTableModRefBS.hpp"
  30 #include "gc/shared/collectedHeap.inline.hpp"
  31 #include "interpreter/interpreter.hpp"
  32 #include "memory/resourceArea.hpp"
  33 #include "memory/universe.hpp"
  34 #include "oops/klass.inline.hpp"
  35 #include "prims/methodHandles.hpp"
  36 #include "runtime/biasedLocking.hpp"
  37 #include "runtime/interfaceSupport.hpp"
  38 #include "runtime/objectMonitor.hpp"
  39 #include "runtime/os.hpp"
  40 #include "runtime/sharedRuntime.hpp"
  41 #include "runtime/stubRoutines.hpp"
  42 #include "runtime/thread.hpp"
  43 #include "utilities/macros.hpp"
  44 #if INCLUDE_ALL_GCS
  45 #include "gc/g1/g1CollectedHeap.inline.hpp"
  46 #include "gc/g1/g1SATBCardTableModRefBS.hpp"
  47 #include "gc/g1/heapRegion.hpp"
  48 #endif // INCLUDE_ALL_GCS
  49 #include "crc32c.h"
  50 #ifdef COMPILER2
  51 #include "opto/intrinsicnode.hpp"
  52 #endif
  53 
  54 #ifdef PRODUCT
  55 #define BLOCK_COMMENT(str) /* nothing */
  56 #define STOP(error) stop(error)
  57 #else
  58 #define BLOCK_COMMENT(str) block_comment(str)
  59 #define STOP(error) block_comment(error); stop(error)
  60 #endif
  61 
  62 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
  63 
  64 #ifdef ASSERT
  65 bool AbstractAssembler::pd_check_instruction_mark() { return true; }
  66 #endif
  67 
  68 static Assembler::Condition reverse[] = {
  69     Assembler::noOverflow     /* overflow      = 0x0 */ ,
  70     Assembler::overflow       /* noOverflow    = 0x1 */ ,
  71     Assembler::aboveEqual     /* carrySet      = 0x2, below         = 0x2 */ ,
  72     Assembler::below          /* aboveEqual    = 0x3, carryClear    = 0x3 */ ,
  73     Assembler::notZero        /* zero          = 0x4, equal         = 0x4 */ ,
  74     Assembler::zero           /* notZero       = 0x5, notEqual      = 0x5 */ ,
  75     Assembler::above          /* belowEqual    = 0x6 */ ,
  76     Assembler::belowEqual     /* above         = 0x7 */ ,
  77     Assembler::positive       /* negative      = 0x8 */ ,
  78     Assembler::negative       /* positive      = 0x9 */ ,
  79     Assembler::noParity       /* parity        = 0xa */ ,
  80     Assembler::parity         /* noParity      = 0xb */ ,
  81     Assembler::greaterEqual   /* less          = 0xc */ ,
  82     Assembler::less           /* greaterEqual  = 0xd */ ,
  83     Assembler::greater        /* lessEqual     = 0xe */ ,
  84     Assembler::lessEqual      /* greater       = 0xf, */
  85 
  86 };
  87 
  88 
  89 // Implementation of MacroAssembler
  90 
  91 // First all the versions that have distinct versions depending on 32/64 bit
  92 // Unless the difference is trivial (1 line or so).
  93 
  94 #ifndef _LP64
  95 
  96 // 32bit versions
  97 
  98 Address MacroAssembler::as_Address(AddressLiteral adr) {
  99   return Address(adr.target(), adr.rspec());
 100 }
 101 
 102 Address MacroAssembler::as_Address(ArrayAddress adr) {
 103   return Address::make_array(adr);
 104 }
 105 
 106 void MacroAssembler::call_VM_leaf_base(address entry_point,
 107                                        int number_of_arguments) {
 108   call(RuntimeAddress(entry_point));
 109   increment(rsp, number_of_arguments * wordSize);
 110 }
 111 
 112 void MacroAssembler::cmpklass(Address src1, Metadata* obj) {
 113   cmp_literal32(src1, (int32_t)obj, metadata_Relocation::spec_for_immediate());
 114 }
 115 
 116 void MacroAssembler::cmpklass(Register src1, Metadata* obj) {
 117   cmp_literal32(src1, (int32_t)obj, metadata_Relocation::spec_for_immediate());
 118 }
 119 
 120 void MacroAssembler::cmpoop(Address src1, jobject obj) {
 121   cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate());
 122 }
 123 
 124 void MacroAssembler::cmpoop(Register src1, jobject obj) {
 125   cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate());
 126 }
 127 
 128 void MacroAssembler::extend_sign(Register hi, Register lo) {
 129   // According to Intel Doc. AP-526, "Integer Divide", p.18.
 130   if (VM_Version::is_P6() && hi == rdx && lo == rax) {
 131     cdql();
 132   } else {
 133     movl(hi, lo);
 134     sarl(hi, 31);
 135   }
 136 }
 137 
 138 void MacroAssembler::jC2(Register tmp, Label& L) {
 139   // set parity bit if FPU flag C2 is set (via rax)
 140   save_rax(tmp);
 141   fwait(); fnstsw_ax();
 142   sahf();
 143   restore_rax(tmp);
 144   // branch
 145   jcc(Assembler::parity, L);
 146 }
 147 
 148 void MacroAssembler::jnC2(Register tmp, Label& L) {
 149   // set parity bit if FPU flag C2 is set (via rax)
 150   save_rax(tmp);
 151   fwait(); fnstsw_ax();
 152   sahf();
 153   restore_rax(tmp);
 154   // branch
 155   jcc(Assembler::noParity, L);
 156 }
 157 
 158 // 32bit can do a case table jump in one instruction but we no longer allow the base
 159 // to be installed in the Address class
 160 void MacroAssembler::jump(ArrayAddress entry) {
 161   jmp(as_Address(entry));
 162 }
 163 
 164 // Note: y_lo will be destroyed
 165 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) {
 166   // Long compare for Java (semantics as described in JVM spec.)
 167   Label high, low, done;
 168 
 169   cmpl(x_hi, y_hi);
 170   jcc(Assembler::less, low);
 171   jcc(Assembler::greater, high);
 172   // x_hi is the return register
 173   xorl(x_hi, x_hi);
 174   cmpl(x_lo, y_lo);
 175   jcc(Assembler::below, low);
 176   jcc(Assembler::equal, done);
 177 
 178   bind(high);
 179   xorl(x_hi, x_hi);
 180   increment(x_hi);
 181   jmp(done);
 182 
 183   bind(low);
 184   xorl(x_hi, x_hi);
 185   decrementl(x_hi);
 186 
 187   bind(done);
 188 }
 189 
 190 void MacroAssembler::lea(Register dst, AddressLiteral src) {
 191     mov_literal32(dst, (int32_t)src.target(), src.rspec());
 192 }
 193 
 194 void MacroAssembler::lea(Address dst, AddressLiteral adr) {
 195   // leal(dst, as_Address(adr));
 196   // see note in movl as to why we must use a move
 197   mov_literal32(dst, (int32_t) adr.target(), adr.rspec());
 198 }
 199 
 200 void MacroAssembler::leave() {
 201   mov(rsp, rbp);
 202   pop(rbp);
 203 }
 204 
 205 void MacroAssembler::lmul(int x_rsp_offset, int y_rsp_offset) {
 206   // Multiplication of two Java long values stored on the stack
 207   // as illustrated below. Result is in rdx:rax.
 208   //
 209   // rsp ---> [  ??  ] \               \
 210   //            ....    | y_rsp_offset  |
 211   //          [ y_lo ] /  (in bytes)    | x_rsp_offset
 212   //          [ y_hi ]                  | (in bytes)
 213   //            ....                    |
 214   //          [ x_lo ]                 /
 215   //          [ x_hi ]
 216   //            ....
 217   //
 218   // Basic idea: lo(result) = lo(x_lo * y_lo)
 219   //             hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
 220   Address x_hi(rsp, x_rsp_offset + wordSize); Address x_lo(rsp, x_rsp_offset);
 221   Address y_hi(rsp, y_rsp_offset + wordSize); Address y_lo(rsp, y_rsp_offset);
 222   Label quick;
 223   // load x_hi, y_hi and check if quick
 224   // multiplication is possible
 225   movl(rbx, x_hi);
 226   movl(rcx, y_hi);
 227   movl(rax, rbx);
 228   orl(rbx, rcx);                                 // rbx, = 0 <=> x_hi = 0 and y_hi = 0
 229   jcc(Assembler::zero, quick);                   // if rbx, = 0 do quick multiply
 230   // do full multiplication
 231   // 1st step
 232   mull(y_lo);                                    // x_hi * y_lo
 233   movl(rbx, rax);                                // save lo(x_hi * y_lo) in rbx,
 234   // 2nd step
 235   movl(rax, x_lo);
 236   mull(rcx);                                     // x_lo * y_hi
 237   addl(rbx, rax);                                // add lo(x_lo * y_hi) to rbx,
 238   // 3rd step
 239   bind(quick);                                   // note: rbx, = 0 if quick multiply!
 240   movl(rax, x_lo);
 241   mull(y_lo);                                    // x_lo * y_lo
 242   addl(rdx, rbx);                                // correct hi(x_lo * y_lo)
 243 }
 244 
 245 void MacroAssembler::lneg(Register hi, Register lo) {
 246   negl(lo);
 247   adcl(hi, 0);
 248   negl(hi);
 249 }
 250 
 251 void MacroAssembler::lshl(Register hi, Register lo) {
 252   // Java shift left long support (semantics as described in JVM spec., p.305)
 253   // (basic idea for shift counts s >= n: x << s == (x << n) << (s - n))
 254   // shift value is in rcx !
 255   assert(hi != rcx, "must not use rcx");
 256   assert(lo != rcx, "must not use rcx");
 257   const Register s = rcx;                        // shift count
 258   const int      n = BitsPerWord;
 259   Label L;
 260   andl(s, 0x3f);                                 // s := s & 0x3f (s < 0x40)
 261   cmpl(s, n);                                    // if (s < n)
 262   jcc(Assembler::less, L);                       // else (s >= n)
 263   movl(hi, lo);                                  // x := x << n
 264   xorl(lo, lo);
 265   // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n!
 266   bind(L);                                       // s (mod n) < n
 267   shldl(hi, lo);                                 // x := x << s
 268   shll(lo);
 269 }
 270 
 271 
 272 void MacroAssembler::lshr(Register hi, Register lo, bool sign_extension) {
 273   // Java shift right long support (semantics as described in JVM spec., p.306 & p.310)
 274   // (basic idea for shift counts s >= n: x >> s == (x >> n) >> (s - n))
 275   assert(hi != rcx, "must not use rcx");
 276   assert(lo != rcx, "must not use rcx");
 277   const Register s = rcx;                        // shift count
 278   const int      n = BitsPerWord;
 279   Label L;
 280   andl(s, 0x3f);                                 // s := s & 0x3f (s < 0x40)
 281   cmpl(s, n);                                    // if (s < n)
 282   jcc(Assembler::less, L);                       // else (s >= n)
 283   movl(lo, hi);                                  // x := x >> n
 284   if (sign_extension) sarl(hi, 31);
 285   else                xorl(hi, hi);
 286   // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n!
 287   bind(L);                                       // s (mod n) < n
 288   shrdl(lo, hi);                                 // x := x >> s
 289   if (sign_extension) sarl(hi);
 290   else                shrl(hi);
 291 }
 292 
 293 void MacroAssembler::movoop(Register dst, jobject obj) {
 294   mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate());
 295 }
 296 
 297 void MacroAssembler::movoop(Address dst, jobject obj) {
 298   mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate());
 299 }
 300 
 301 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) {
 302   mov_literal32(dst, (int32_t)obj, metadata_Relocation::spec_for_immediate());
 303 }
 304 
 305 void MacroAssembler::mov_metadata(Address dst, Metadata* obj) {
 306   mov_literal32(dst, (int32_t)obj, metadata_Relocation::spec_for_immediate());
 307 }
 308 
 309 void MacroAssembler::movptr(Register dst, AddressLiteral src, Register scratch) {
 310   // scratch register is not used,
 311   // it is defined to match parameters of 64-bit version of this method.
 312   if (src.is_lval()) {
 313     mov_literal32(dst, (intptr_t)src.target(), src.rspec());
 314   } else {
 315     movl(dst, as_Address(src));
 316   }
 317 }
 318 
 319 void MacroAssembler::movptr(ArrayAddress dst, Register src) {
 320   movl(as_Address(dst), src);
 321 }
 322 
 323 void MacroAssembler::movptr(Register dst, ArrayAddress src) {
 324   movl(dst, as_Address(src));
 325 }
 326 
 327 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
 328 void MacroAssembler::movptr(Address dst, intptr_t src) {
 329   movl(dst, src);
 330 }
 331 
 332 
 333 void MacroAssembler::pop_callee_saved_registers() {
 334   pop(rcx);
 335   pop(rdx);
 336   pop(rdi);
 337   pop(rsi);
 338 }
 339 
 340 void MacroAssembler::pop_fTOS() {
 341   fld_d(Address(rsp, 0));
 342   addl(rsp, 2 * wordSize);
 343 }
 344 
 345 void MacroAssembler::push_callee_saved_registers() {
 346   push(rsi);
 347   push(rdi);
 348   push(rdx);
 349   push(rcx);
 350 }
 351 
 352 void MacroAssembler::push_fTOS() {
 353   subl(rsp, 2 * wordSize);
 354   fstp_d(Address(rsp, 0));
 355 }
 356 
 357 
 358 void MacroAssembler::pushoop(jobject obj) {
 359   push_literal32((int32_t)obj, oop_Relocation::spec_for_immediate());
 360 }
 361 
 362 void MacroAssembler::pushklass(Metadata* obj) {
 363   push_literal32((int32_t)obj, metadata_Relocation::spec_for_immediate());
 364 }
 365 
 366 void MacroAssembler::pushptr(AddressLiteral src) {
 367   if (src.is_lval()) {
 368     push_literal32((int32_t)src.target(), src.rspec());
 369   } else {
 370     pushl(as_Address(src));
 371   }
 372 }
 373 
 374 void MacroAssembler::set_word_if_not_zero(Register dst) {
 375   xorl(dst, dst);
 376   set_byte_if_not_zero(dst);
 377 }
 378 
 379 static void pass_arg0(MacroAssembler* masm, Register arg) {
 380   masm->push(arg);
 381 }
 382 
 383 static void pass_arg1(MacroAssembler* masm, Register arg) {
 384   masm->push(arg);
 385 }
 386 
 387 static void pass_arg2(MacroAssembler* masm, Register arg) {
 388   masm->push(arg);
 389 }
 390 
 391 static void pass_arg3(MacroAssembler* masm, Register arg) {
 392   masm->push(arg);
 393 }
 394 
 395 #ifndef PRODUCT
 396 extern "C" void findpc(intptr_t x);
 397 #endif
 398 
 399 void MacroAssembler::debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg) {
 400   // In order to get locks to work, we need to fake a in_VM state
 401   JavaThread* thread = JavaThread::current();
 402   JavaThreadState saved_state = thread->thread_state();
 403   thread->set_thread_state(_thread_in_vm);
 404   if (ShowMessageBoxOnError) {
 405     JavaThread* thread = JavaThread::current();
 406     JavaThreadState saved_state = thread->thread_state();
 407     thread->set_thread_state(_thread_in_vm);
 408     if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
 409       ttyLocker ttyl;
 410       BytecodeCounter::print();
 411     }
 412     // To see where a verify_oop failed, get $ebx+40/X for this frame.
 413     // This is the value of eip which points to where verify_oop will return.
 414     if (os::message_box(msg, "Execution stopped, print registers?")) {
 415       print_state32(rdi, rsi, rbp, rsp, rbx, rdx, rcx, rax, eip);
 416       BREAKPOINT;
 417     }
 418   } else {
 419     ttyLocker ttyl;
 420     ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n", msg);
 421   }
 422   // Don't assert holding the ttyLock
 423     assert(false, "DEBUG MESSAGE: %s", msg);
 424   ThreadStateTransition::transition(thread, _thread_in_vm, saved_state);
 425 }
 426 
 427 void MacroAssembler::print_state32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip) {
 428   ttyLocker ttyl;
 429   FlagSetting fs(Debugging, true);
 430   tty->print_cr("eip = 0x%08x", eip);
 431 #ifndef PRODUCT
 432   if ((WizardMode || Verbose) && PrintMiscellaneous) {
 433     tty->cr();
 434     findpc(eip);
 435     tty->cr();
 436   }
 437 #endif
 438 #define PRINT_REG(rax) \
 439   { tty->print("%s = ", #rax); os::print_location(tty, rax); }
 440   PRINT_REG(rax);
 441   PRINT_REG(rbx);
 442   PRINT_REG(rcx);
 443   PRINT_REG(rdx);
 444   PRINT_REG(rdi);
 445   PRINT_REG(rsi);
 446   PRINT_REG(rbp);
 447   PRINT_REG(rsp);
 448 #undef PRINT_REG
 449   // Print some words near top of staack.
 450   int* dump_sp = (int*) rsp;
 451   for (int col1 = 0; col1 < 8; col1++) {
 452     tty->print("(rsp+0x%03x) 0x%08x: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
 453     os::print_location(tty, *dump_sp++);
 454   }
 455   for (int row = 0; row < 16; row++) {
 456     tty->print("(rsp+0x%03x) 0x%08x: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
 457     for (int col = 0; col < 8; col++) {
 458       tty->print(" 0x%08x", *dump_sp++);
 459     }
 460     tty->cr();
 461   }
 462   // Print some instructions around pc:
 463   Disassembler::decode((address)eip-64, (address)eip);
 464   tty->print_cr("--------");
 465   Disassembler::decode((address)eip, (address)eip+32);
 466 }
 467 
 468 void MacroAssembler::stop(const char* msg) {
 469   ExternalAddress message((address)msg);
 470   // push address of message
 471   pushptr(message.addr());
 472   { Label L; call(L, relocInfo::none); bind(L); }     // push eip
 473   pusha();                                            // push registers
 474   call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug32)));
 475   hlt();
 476 }
 477 
 478 void MacroAssembler::warn(const char* msg) {
 479   push_CPU_state();
 480 
 481   ExternalAddress message((address) msg);
 482   // push address of message
 483   pushptr(message.addr());
 484 
 485   call(RuntimeAddress(CAST_FROM_FN_PTR(address, warning)));
 486   addl(rsp, wordSize);       // discard argument
 487   pop_CPU_state();
 488 }
 489 
 490 void MacroAssembler::print_state() {
 491   { Label L; call(L, relocInfo::none); bind(L); }     // push eip
 492   pusha();                                            // push registers
 493 
 494   push_CPU_state();
 495   call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::print_state32)));
 496   pop_CPU_state();
 497 
 498   popa();
 499   addl(rsp, wordSize);
 500 }
 501 
 502 #else // _LP64
 503 
 504 // 64 bit versions
 505 
 506 Address MacroAssembler::as_Address(AddressLiteral adr) {
 507   // amd64 always does this as a pc-rel
 508   // we can be absolute or disp based on the instruction type
 509   // jmp/call are displacements others are absolute
 510   assert(!adr.is_lval(), "must be rval");
 511   assert(reachable(adr), "must be");
 512   return Address((int32_t)(intptr_t)(adr.target() - pc()), adr.target(), adr.reloc());
 513 
 514 }
 515 
 516 Address MacroAssembler::as_Address(ArrayAddress adr) {
 517   AddressLiteral base = adr.base();
 518   lea(rscratch1, base);
 519   Address index = adr.index();
 520   assert(index._disp == 0, "must not have disp"); // maybe it can?
 521   Address array(rscratch1, index._index, index._scale, index._disp);
 522   return array;
 523 }
 524 
 525 void MacroAssembler::call_VM_leaf_base(address entry_point, int num_args) {
 526   Label L, E;
 527 
 528 #ifdef _WIN64
 529   // Windows always allocates space for it's register args
 530   assert(num_args <= 4, "only register arguments supported");
 531   subq(rsp,  frame::arg_reg_save_area_bytes);
 532 #endif
 533 
 534   // Align stack if necessary
 535   testl(rsp, 15);
 536   jcc(Assembler::zero, L);
 537 
 538   subq(rsp, 8);
 539   {
 540     call(RuntimeAddress(entry_point));
 541   }
 542   addq(rsp, 8);
 543   jmp(E);
 544 
 545   bind(L);
 546   {
 547     call(RuntimeAddress(entry_point));
 548   }
 549 
 550   bind(E);
 551 
 552 #ifdef _WIN64
 553   // restore stack pointer
 554   addq(rsp, frame::arg_reg_save_area_bytes);
 555 #endif
 556 
 557 }
 558 
 559 void MacroAssembler::cmp64(Register src1, AddressLiteral src2) {
 560   assert(!src2.is_lval(), "should use cmpptr");
 561 
 562   if (reachable(src2)) {
 563     cmpq(src1, as_Address(src2));
 564   } else {
 565     lea(rscratch1, src2);
 566     Assembler::cmpq(src1, Address(rscratch1, 0));
 567   }
 568 }
 569 
 570 int MacroAssembler::corrected_idivq(Register reg) {
 571   // Full implementation of Java ldiv and lrem; checks for special
 572   // case as described in JVM spec., p.243 & p.271.  The function
 573   // returns the (pc) offset of the idivl instruction - may be needed
 574   // for implicit exceptions.
 575   //
 576   //         normal case                           special case
 577   //
 578   // input : rax: dividend                         min_long
 579   //         reg: divisor   (may not be eax/edx)   -1
 580   //
 581   // output: rax: quotient  (= rax idiv reg)       min_long
 582   //         rdx: remainder (= rax irem reg)       0
 583   assert(reg != rax && reg != rdx, "reg cannot be rax or rdx register");
 584   static const int64_t min_long = 0x8000000000000000;
 585   Label normal_case, special_case;
 586 
 587   // check for special case
 588   cmp64(rax, ExternalAddress((address) &min_long));
 589   jcc(Assembler::notEqual, normal_case);
 590   xorl(rdx, rdx); // prepare rdx for possible special case (where
 591                   // remainder = 0)
 592   cmpq(reg, -1);
 593   jcc(Assembler::equal, special_case);
 594 
 595   // handle normal case
 596   bind(normal_case);
 597   cdqq();
 598   int idivq_offset = offset();
 599   idivq(reg);
 600 
 601   // normal and special case exit
 602   bind(special_case);
 603 
 604   return idivq_offset;
 605 }
 606 
 607 void MacroAssembler::decrementq(Register reg, int value) {
 608   if (value == min_jint) { subq(reg, value); return; }
 609   if (value <  0) { incrementq(reg, -value); return; }
 610   if (value == 0) {                        ; return; }
 611   if (value == 1 && UseIncDec) { decq(reg) ; return; }
 612   /* else */      { subq(reg, value)       ; return; }
 613 }
 614 
 615 void MacroAssembler::decrementq(Address dst, int value) {
 616   if (value == min_jint) { subq(dst, value); return; }
 617   if (value <  0) { incrementq(dst, -value); return; }
 618   if (value == 0) {                        ; return; }
 619   if (value == 1 && UseIncDec) { decq(dst) ; return; }
 620   /* else */      { subq(dst, value)       ; return; }
 621 }
 622 
 623 void MacroAssembler::incrementq(AddressLiteral dst) {
 624   if (reachable(dst)) {
 625     incrementq(as_Address(dst));
 626   } else {
 627     lea(rscratch1, dst);
 628     incrementq(Address(rscratch1, 0));
 629   }
 630 }
 631 
 632 void MacroAssembler::incrementq(Register reg, int value) {
 633   if (value == min_jint) { addq(reg, value); return; }
 634   if (value <  0) { decrementq(reg, -value); return; }
 635   if (value == 0) {                        ; return; }
 636   if (value == 1 && UseIncDec) { incq(reg) ; return; }
 637   /* else */      { addq(reg, value)       ; return; }
 638 }
 639 
 640 void MacroAssembler::incrementq(Address dst, int value) {
 641   if (value == min_jint) { addq(dst, value); return; }
 642   if (value <  0) { decrementq(dst, -value); return; }
 643   if (value == 0) {                        ; return; }
 644   if (value == 1 && UseIncDec) { incq(dst) ; return; }
 645   /* else */      { addq(dst, value)       ; return; }
 646 }
 647 
 648 // 32bit can do a case table jump in one instruction but we no longer allow the base
 649 // to be installed in the Address class
 650 void MacroAssembler::jump(ArrayAddress entry) {
 651   lea(rscratch1, entry.base());
 652   Address dispatch = entry.index();
 653   assert(dispatch._base == noreg, "must be");
 654   dispatch._base = rscratch1;
 655   jmp(dispatch);
 656 }
 657 
 658 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) {
 659   ShouldNotReachHere(); // 64bit doesn't use two regs
 660   cmpq(x_lo, y_lo);
 661 }
 662 
 663 void MacroAssembler::lea(Register dst, AddressLiteral src) {
 664     mov_literal64(dst, (intptr_t)src.target(), src.rspec());
 665 }
 666 
 667 void MacroAssembler::lea(Address dst, AddressLiteral adr) {
 668   mov_literal64(rscratch1, (intptr_t)adr.target(), adr.rspec());
 669   movptr(dst, rscratch1);
 670 }
 671 
 672 void MacroAssembler::leave() {
 673   // %%% is this really better? Why not on 32bit too?
 674   emit_int8((unsigned char)0xC9); // LEAVE
 675 }
 676 
 677 void MacroAssembler::lneg(Register hi, Register lo) {
 678   ShouldNotReachHere(); // 64bit doesn't use two regs
 679   negq(lo);
 680 }
 681 
 682 void MacroAssembler::movoop(Register dst, jobject obj) {
 683   mov_literal64(dst, (intptr_t)obj, oop_Relocation::spec_for_immediate());
 684 }
 685 
 686 void MacroAssembler::movoop(Address dst, jobject obj) {
 687   mov_literal64(rscratch1, (intptr_t)obj, oop_Relocation::spec_for_immediate());
 688   movq(dst, rscratch1);
 689 }
 690 
 691 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) {
 692   mov_literal64(dst, (intptr_t)obj, metadata_Relocation::spec_for_immediate());
 693 }
 694 
 695 void MacroAssembler::mov_metadata(Address dst, Metadata* obj) {
 696   mov_literal64(rscratch1, (intptr_t)obj, metadata_Relocation::spec_for_immediate());
 697   movq(dst, rscratch1);
 698 }
 699 
 700 void MacroAssembler::movptr(Register dst, AddressLiteral src, Register scratch) {
 701   if (src.is_lval()) {
 702     mov_literal64(dst, (intptr_t)src.target(), src.rspec());
 703   } else {
 704     if (reachable(src)) {
 705       movq(dst, as_Address(src));
 706     } else {
 707       lea(scratch, src);
 708       movq(dst, Address(scratch, 0));
 709     }
 710   }
 711 }
 712 
 713 void MacroAssembler::movptr(ArrayAddress dst, Register src) {
 714   movq(as_Address(dst), src);
 715 }
 716 
 717 void MacroAssembler::movptr(Register dst, ArrayAddress src) {
 718   movq(dst, as_Address(src));
 719 }
 720 
 721 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
 722 void MacroAssembler::movptr(Address dst, intptr_t src) {
 723   mov64(rscratch1, src);
 724   movq(dst, rscratch1);
 725 }
 726 
 727 // These are mostly for initializing NULL
 728 void MacroAssembler::movptr(Address dst, int32_t src) {
 729   movslq(dst, src);
 730 }
 731 
 732 void MacroAssembler::movptr(Register dst, int32_t src) {
 733   mov64(dst, (intptr_t)src);
 734 }
 735 
 736 void MacroAssembler::pushoop(jobject obj) {
 737   movoop(rscratch1, obj);
 738   push(rscratch1);
 739 }
 740 
 741 void MacroAssembler::pushklass(Metadata* obj) {
 742   mov_metadata(rscratch1, obj);
 743   push(rscratch1);
 744 }
 745 
 746 void MacroAssembler::pushptr(AddressLiteral src) {
 747   lea(rscratch1, src);
 748   if (src.is_lval()) {
 749     push(rscratch1);
 750   } else {
 751     pushq(Address(rscratch1, 0));
 752   }
 753 }
 754 
 755 void MacroAssembler::reset_last_Java_frame(bool clear_fp) {
 756   // we must set sp to zero to clear frame
 757   movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), NULL_WORD);
 758   // must clear fp, so that compiled frames are not confused; it is
 759   // possible that we need it only for debugging
 760   if (clear_fp) {
 761     movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()), NULL_WORD);
 762   }
 763 
 764   // Always clear the pc because it could have been set by make_walkable()
 765   movptr(Address(r15_thread, JavaThread::last_Java_pc_offset()), NULL_WORD);
 766 }
 767 
 768 void MacroAssembler::set_last_Java_frame(Register last_java_sp,
 769                                          Register last_java_fp,
 770                                          address  last_java_pc) {
 771   // determine last_java_sp register
 772   if (!last_java_sp->is_valid()) {
 773     last_java_sp = rsp;
 774   }
 775 
 776   // last_java_fp is optional
 777   if (last_java_fp->is_valid()) {
 778     movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()),
 779            last_java_fp);
 780   }
 781 
 782   // last_java_pc is optional
 783   if (last_java_pc != NULL) {
 784     Address java_pc(r15_thread,
 785                     JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset());
 786     lea(rscratch1, InternalAddress(last_java_pc));
 787     movptr(java_pc, rscratch1);
 788   }
 789 
 790   movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), last_java_sp);
 791 }
 792 
 793 static void pass_arg0(MacroAssembler* masm, Register arg) {
 794   if (c_rarg0 != arg ) {
 795     masm->mov(c_rarg0, arg);
 796   }
 797 }
 798 
 799 static void pass_arg1(MacroAssembler* masm, Register arg) {
 800   if (c_rarg1 != arg ) {
 801     masm->mov(c_rarg1, arg);
 802   }
 803 }
 804 
 805 static void pass_arg2(MacroAssembler* masm, Register arg) {
 806   if (c_rarg2 != arg ) {
 807     masm->mov(c_rarg2, arg);
 808   }
 809 }
 810 
 811 static void pass_arg3(MacroAssembler* masm, Register arg) {
 812   if (c_rarg3 != arg ) {
 813     masm->mov(c_rarg3, arg);
 814   }
 815 }
 816 
 817 void MacroAssembler::stop(const char* msg) {
 818   address rip = pc();
 819   pusha(); // get regs on stack
 820   lea(c_rarg0, ExternalAddress((address) msg));
 821   lea(c_rarg1, InternalAddress(rip));
 822   movq(c_rarg2, rsp); // pass pointer to regs array
 823   andq(rsp, -16); // align stack as required by ABI
 824   call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug64)));
 825   hlt();
 826 }
 827 
 828 void MacroAssembler::warn(const char* msg) {
 829   push(rbp);
 830   movq(rbp, rsp);
 831   andq(rsp, -16);     // align stack as required by push_CPU_state and call
 832   push_CPU_state();   // keeps alignment at 16 bytes
 833   lea(c_rarg0, ExternalAddress((address) msg));
 834   call_VM_leaf(CAST_FROM_FN_PTR(address, warning), c_rarg0);
 835   pop_CPU_state();
 836   mov(rsp, rbp);
 837   pop(rbp);
 838 }
 839 
 840 void MacroAssembler::print_state() {
 841   address rip = pc();
 842   pusha();            // get regs on stack
 843   push(rbp);
 844   movq(rbp, rsp);
 845   andq(rsp, -16);     // align stack as required by push_CPU_state and call
 846   push_CPU_state();   // keeps alignment at 16 bytes
 847 
 848   lea(c_rarg0, InternalAddress(rip));
 849   lea(c_rarg1, Address(rbp, wordSize)); // pass pointer to regs array
 850   call_VM_leaf(CAST_FROM_FN_PTR(address, MacroAssembler::print_state64), c_rarg0, c_rarg1);
 851 
 852   pop_CPU_state();
 853   mov(rsp, rbp);
 854   pop(rbp);
 855   popa();
 856 }
 857 
 858 #ifndef PRODUCT
 859 extern "C" void findpc(intptr_t x);
 860 #endif
 861 
 862 void MacroAssembler::debug64(char* msg, int64_t pc, int64_t regs[]) {
 863   // In order to get locks to work, we need to fake a in_VM state
 864   if (ShowMessageBoxOnError) {
 865     JavaThread* thread = JavaThread::current();
 866     JavaThreadState saved_state = thread->thread_state();
 867     thread->set_thread_state(_thread_in_vm);
 868 #ifndef PRODUCT
 869     if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
 870       ttyLocker ttyl;
 871       BytecodeCounter::print();
 872     }
 873 #endif
 874     // To see where a verify_oop failed, get $ebx+40/X for this frame.
 875     // XXX correct this offset for amd64
 876     // This is the value of eip which points to where verify_oop will return.
 877     if (os::message_box(msg, "Execution stopped, print registers?")) {
 878       print_state64(pc, regs);
 879       BREAKPOINT;
 880       assert(false, "start up GDB");
 881     }
 882     ThreadStateTransition::transition(thread, _thread_in_vm, saved_state);
 883   } else {
 884     ttyLocker ttyl;
 885     ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n",
 886                     msg);
 887     assert(false, "DEBUG MESSAGE: %s", msg);
 888   }
 889 }
 890 
 891 void MacroAssembler::print_state64(int64_t pc, int64_t regs[]) {
 892   ttyLocker ttyl;
 893   FlagSetting fs(Debugging, true);
 894   tty->print_cr("rip = 0x%016lx", pc);
 895 #ifndef PRODUCT
 896   tty->cr();
 897   findpc(pc);
 898   tty->cr();
 899 #endif
 900 #define PRINT_REG(rax, value) \
 901   { tty->print("%s = ", #rax); os::print_location(tty, value); }
 902   PRINT_REG(rax, regs[15]);
 903   PRINT_REG(rbx, regs[12]);
 904   PRINT_REG(rcx, regs[14]);
 905   PRINT_REG(rdx, regs[13]);
 906   PRINT_REG(rdi, regs[8]);
 907   PRINT_REG(rsi, regs[9]);
 908   PRINT_REG(rbp, regs[10]);
 909   PRINT_REG(rsp, regs[11]);
 910   PRINT_REG(r8 , regs[7]);
 911   PRINT_REG(r9 , regs[6]);
 912   PRINT_REG(r10, regs[5]);
 913   PRINT_REG(r11, regs[4]);
 914   PRINT_REG(r12, regs[3]);
 915   PRINT_REG(r13, regs[2]);
 916   PRINT_REG(r14, regs[1]);
 917   PRINT_REG(r15, regs[0]);
 918 #undef PRINT_REG
 919   // Print some words near top of staack.
 920   int64_t* rsp = (int64_t*) regs[11];
 921   int64_t* dump_sp = rsp;
 922   for (int col1 = 0; col1 < 8; col1++) {
 923     tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (int64_t)dump_sp);
 924     os::print_location(tty, *dump_sp++);
 925   }
 926   for (int row = 0; row < 25; row++) {
 927     tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (int64_t)dump_sp);
 928     for (int col = 0; col < 4; col++) {
 929       tty->print(" 0x%016lx", *dump_sp++);
 930     }
 931     tty->cr();
 932   }
 933   // Print some instructions around pc:
 934   Disassembler::decode((address)pc-64, (address)pc);
 935   tty->print_cr("--------");
 936   Disassembler::decode((address)pc, (address)pc+32);
 937 }
 938 
 939 #endif // _LP64
 940 
 941 // Now versions that are common to 32/64 bit
 942 
 943 void MacroAssembler::addptr(Register dst, int32_t imm32) {
 944   LP64_ONLY(addq(dst, imm32)) NOT_LP64(addl(dst, imm32));
 945 }
 946 
 947 void MacroAssembler::addptr(Register dst, Register src) {
 948   LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src));
 949 }
 950 
 951 void MacroAssembler::addptr(Address dst, Register src) {
 952   LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src));
 953 }
 954 
 955 void MacroAssembler::addsd(XMMRegister dst, AddressLiteral src) {
 956   if (reachable(src)) {
 957     Assembler::addsd(dst, as_Address(src));
 958   } else {
 959     lea(rscratch1, src);
 960     Assembler::addsd(dst, Address(rscratch1, 0));
 961   }
 962 }
 963 
 964 void MacroAssembler::addss(XMMRegister dst, AddressLiteral src) {
 965   if (reachable(src)) {
 966     addss(dst, as_Address(src));
 967   } else {
 968     lea(rscratch1, src);
 969     addss(dst, Address(rscratch1, 0));
 970   }
 971 }
 972 
 973 void MacroAssembler::addpd(XMMRegister dst, AddressLiteral src) {
 974   if (reachable(src)) {
 975     Assembler::addpd(dst, as_Address(src));
 976   } else {
 977     lea(rscratch1, src);
 978     Assembler::addpd(dst, Address(rscratch1, 0));
 979   }
 980 }
 981 
 982 void MacroAssembler::align(int modulus) {
 983   align(modulus, offset());
 984 }
 985 
 986 void MacroAssembler::align(int modulus, int target) {
 987   if (target % modulus != 0) {
 988     nop(modulus - (target % modulus));
 989   }
 990 }
 991 
 992 void MacroAssembler::andpd(XMMRegister dst, AddressLiteral src) {
 993   // Used in sign-masking with aligned address.
 994   assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
 995   if (reachable(src)) {
 996     Assembler::andpd(dst, as_Address(src));
 997   } else {
 998     lea(rscratch1, src);
 999     Assembler::andpd(dst, Address(rscratch1, 0));
1000   }
1001 }
1002 
1003 void MacroAssembler::andps(XMMRegister dst, AddressLiteral src) {
1004   // Used in sign-masking with aligned address.
1005   assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
1006   if (reachable(src)) {
1007     Assembler::andps(dst, as_Address(src));
1008   } else {
1009     lea(rscratch1, src);
1010     Assembler::andps(dst, Address(rscratch1, 0));
1011   }
1012 }
1013 
1014 void MacroAssembler::andptr(Register dst, int32_t imm32) {
1015   LP64_ONLY(andq(dst, imm32)) NOT_LP64(andl(dst, imm32));
1016 }
1017 
1018 void MacroAssembler::atomic_incl(Address counter_addr) {
1019   if (os::is_MP())
1020     lock();
1021   incrementl(counter_addr);
1022 }
1023 
1024 void MacroAssembler::atomic_incl(AddressLiteral counter_addr, Register scr) {
1025   if (reachable(counter_addr)) {
1026     atomic_incl(as_Address(counter_addr));
1027   } else {
1028     lea(scr, counter_addr);
1029     atomic_incl(Address(scr, 0));
1030   }
1031 }
1032 
1033 #ifdef _LP64
1034 void MacroAssembler::atomic_incq(Address counter_addr) {
1035   if (os::is_MP())
1036     lock();
1037   incrementq(counter_addr);
1038 }
1039 
1040 void MacroAssembler::atomic_incq(AddressLiteral counter_addr, Register scr) {
1041   if (reachable(counter_addr)) {
1042     atomic_incq(as_Address(counter_addr));
1043   } else {
1044     lea(scr, counter_addr);
1045     atomic_incq(Address(scr, 0));
1046   }
1047 }
1048 #endif
1049 
1050 // Writes to stack successive pages until offset reached to check for
1051 // stack overflow + shadow pages.  This clobbers tmp.
1052 void MacroAssembler::bang_stack_size(Register size, Register tmp) {
1053   movptr(tmp, rsp);
1054   // Bang stack for total size given plus shadow page size.
1055   // Bang one page at a time because large size can bang beyond yellow and
1056   // red zones.
1057   Label loop;
1058   bind(loop);
1059   movl(Address(tmp, (-os::vm_page_size())), size );
1060   subptr(tmp, os::vm_page_size());
1061   subl(size, os::vm_page_size());
1062   jcc(Assembler::greater, loop);
1063 
1064   // Bang down shadow pages too.
1065   // At this point, (tmp-0) is the last address touched, so don't
1066   // touch it again.  (It was touched as (tmp-pagesize) but then tmp
1067   // was post-decremented.)  Skip this address by starting at i=1, and
1068   // touch a few more pages below.  N.B.  It is important to touch all
1069   // the way down including all pages in the shadow zone.
1070   for (int i = 1; i < ((int)JavaThread::stack_shadow_zone_size() / os::vm_page_size()); i++) {
1071     // this could be any sized move but this is can be a debugging crumb
1072     // so the bigger the better.
1073     movptr(Address(tmp, (-i*os::vm_page_size())), size );
1074   }
1075 }
1076 
1077 void MacroAssembler::reserved_stack_check() {
1078     // testing if reserved zone needs to be enabled
1079     Label no_reserved_zone_enabling;
1080     Register thread = NOT_LP64(rsi) LP64_ONLY(r15_thread);
1081     NOT_LP64(get_thread(rsi);)
1082 
1083     cmpptr(rsp, Address(thread, JavaThread::reserved_stack_activation_offset()));
1084     jcc(Assembler::below, no_reserved_zone_enabling);
1085 
1086     call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::enable_stack_reserved_zone), thread);
1087     jump(RuntimeAddress(StubRoutines::throw_delayed_StackOverflowError_entry()));
1088     should_not_reach_here();
1089 
1090     bind(no_reserved_zone_enabling);
1091 }
1092 
1093 int MacroAssembler::biased_locking_enter(Register lock_reg,
1094                                          Register obj_reg,
1095                                          Register swap_reg,
1096                                          Register tmp_reg,
1097                                          bool swap_reg_contains_mark,
1098                                          Label& done,
1099                                          Label* slow_case,
1100                                          BiasedLockingCounters* counters) {
1101   assert(UseBiasedLocking, "why call this otherwise?");
1102   assert(swap_reg == rax, "swap_reg must be rax for cmpxchgq");
1103   assert(tmp_reg != noreg, "tmp_reg must be supplied");
1104   assert_different_registers(lock_reg, obj_reg, swap_reg, tmp_reg);
1105   assert(markOopDesc::age_shift == markOopDesc::lock_bits + markOopDesc::biased_lock_bits, "biased locking makes assumptions about bit layout");
1106   Address mark_addr      (obj_reg, oopDesc::mark_offset_in_bytes());
1107   NOT_LP64( Address saved_mark_addr(lock_reg, 0); )
1108 
1109   if (PrintBiasedLockingStatistics && counters == NULL) {
1110     counters = BiasedLocking::counters();
1111   }
1112   // Biased locking
1113   // See whether the lock is currently biased toward our thread and
1114   // whether the epoch is still valid
1115   // Note that the runtime guarantees sufficient alignment of JavaThread
1116   // pointers to allow age to be placed into low bits
1117   // First check to see whether biasing is even enabled for this object
1118   Label cas_label;
1119   int null_check_offset = -1;
1120   if (!swap_reg_contains_mark) {
1121     null_check_offset = offset();
1122     movptr(swap_reg, mark_addr);
1123   }
1124   movptr(tmp_reg, swap_reg);
1125   andptr(tmp_reg, markOopDesc::biased_lock_mask_in_place);
1126   cmpptr(tmp_reg, markOopDesc::biased_lock_pattern);
1127   jcc(Assembler::notEqual, cas_label);
1128   // The bias pattern is present in the object's header. Need to check
1129   // whether the bias owner and the epoch are both still current.
1130 #ifndef _LP64
1131   // Note that because there is no current thread register on x86_32 we
1132   // need to store off the mark word we read out of the object to
1133   // avoid reloading it and needing to recheck invariants below. This
1134   // store is unfortunate but it makes the overall code shorter and
1135   // simpler.
1136   movptr(saved_mark_addr, swap_reg);
1137 #endif
1138   if (swap_reg_contains_mark) {
1139     null_check_offset = offset();
1140   }
1141   load_prototype_header(tmp_reg, obj_reg);
1142 #ifdef _LP64
1143   orptr(tmp_reg, r15_thread);
1144   xorptr(tmp_reg, swap_reg);
1145   Register header_reg = tmp_reg;
1146 #else
1147   xorptr(tmp_reg, swap_reg);
1148   get_thread(swap_reg);
1149   xorptr(swap_reg, tmp_reg);
1150   Register header_reg = swap_reg;
1151 #endif
1152   andptr(header_reg, ~((int) markOopDesc::age_mask_in_place));
1153   if (counters != NULL) {
1154     cond_inc32(Assembler::zero,
1155                ExternalAddress((address) counters->biased_lock_entry_count_addr()));
1156   }
1157   jcc(Assembler::equal, done);
1158 
1159   Label try_revoke_bias;
1160   Label try_rebias;
1161 
1162   // At this point we know that the header has the bias pattern and
1163   // that we are not the bias owner in the current epoch. We need to
1164   // figure out more details about the state of the header in order to
1165   // know what operations can be legally performed on the object's
1166   // header.
1167 
1168   // If the low three bits in the xor result aren't clear, that means
1169   // the prototype header is no longer biased and we have to revoke
1170   // the bias on this object.
1171   testptr(header_reg, markOopDesc::biased_lock_mask_in_place);
1172   jccb(Assembler::notZero, try_revoke_bias);
1173 
1174   // Biasing is still enabled for this data type. See whether the
1175   // epoch of the current bias is still valid, meaning that the epoch
1176   // bits of the mark word are equal to the epoch bits of the
1177   // prototype header. (Note that the prototype header's epoch bits
1178   // only change at a safepoint.) If not, attempt to rebias the object
1179   // toward the current thread. Note that we must be absolutely sure
1180   // that the current epoch is invalid in order to do this because
1181   // otherwise the manipulations it performs on the mark word are
1182   // illegal.
1183   testptr(header_reg, markOopDesc::epoch_mask_in_place);
1184   jccb(Assembler::notZero, try_rebias);
1185 
1186   // The epoch of the current bias is still valid but we know nothing
1187   // about the owner; it might be set or it might be clear. Try to
1188   // acquire the bias of the object using an atomic operation. If this
1189   // fails we will go in to the runtime to revoke the object's bias.
1190   // Note that we first construct the presumed unbiased header so we
1191   // don't accidentally blow away another thread's valid bias.
1192   NOT_LP64( movptr(swap_reg, saved_mark_addr); )
1193   andptr(swap_reg,
1194          markOopDesc::biased_lock_mask_in_place | markOopDesc::age_mask_in_place | markOopDesc::epoch_mask_in_place);
1195 #ifdef _LP64
1196   movptr(tmp_reg, swap_reg);
1197   orptr(tmp_reg, r15_thread);
1198 #else
1199   get_thread(tmp_reg);
1200   orptr(tmp_reg, swap_reg);
1201 #endif
1202   if (os::is_MP()) {
1203     lock();
1204   }
1205   cmpxchgptr(tmp_reg, mark_addr); // compare tmp_reg and swap_reg
1206   // If the biasing toward our thread failed, this means that
1207   // another thread succeeded in biasing it toward itself and we
1208   // need to revoke that bias. The revocation will occur in the
1209   // interpreter runtime in the slow case.
1210   if (counters != NULL) {
1211     cond_inc32(Assembler::zero,
1212                ExternalAddress((address) counters->anonymously_biased_lock_entry_count_addr()));
1213   }
1214   if (slow_case != NULL) {
1215     jcc(Assembler::notZero, *slow_case);
1216   }
1217   jmp(done);
1218 
1219   bind(try_rebias);
1220   // At this point we know the epoch has expired, meaning that the
1221   // current "bias owner", if any, is actually invalid. Under these
1222   // circumstances _only_, we are allowed to use the current header's
1223   // value as the comparison value when doing the cas to acquire the
1224   // bias in the current epoch. In other words, we allow transfer of
1225   // the bias from one thread to another directly in this situation.
1226   //
1227   // FIXME: due to a lack of registers we currently blow away the age
1228   // bits in this situation. Should attempt to preserve them.
1229   load_prototype_header(tmp_reg, obj_reg);
1230 #ifdef _LP64
1231   orptr(tmp_reg, r15_thread);
1232 #else
1233   get_thread(swap_reg);
1234   orptr(tmp_reg, swap_reg);
1235   movptr(swap_reg, saved_mark_addr);
1236 #endif
1237   if (os::is_MP()) {
1238     lock();
1239   }
1240   cmpxchgptr(tmp_reg, mark_addr); // compare tmp_reg and swap_reg
1241   // If the biasing toward our thread failed, then another thread
1242   // succeeded in biasing it toward itself and we need to revoke that
1243   // bias. The revocation will occur in the runtime in the slow case.
1244   if (counters != NULL) {
1245     cond_inc32(Assembler::zero,
1246                ExternalAddress((address) counters->rebiased_lock_entry_count_addr()));
1247   }
1248   if (slow_case != NULL) {
1249     jcc(Assembler::notZero, *slow_case);
1250   }
1251   jmp(done);
1252 
1253   bind(try_revoke_bias);
1254   // The prototype mark in the klass doesn't have the bias bit set any
1255   // more, indicating that objects of this data type are not supposed
1256   // to be biased any more. We are going to try to reset the mark of
1257   // this object to the prototype value and fall through to the
1258   // CAS-based locking scheme. Note that if our CAS fails, it means
1259   // that another thread raced us for the privilege of revoking the
1260   // bias of this particular object, so it's okay to continue in the
1261   // normal locking code.
1262   //
1263   // FIXME: due to a lack of registers we currently blow away the age
1264   // bits in this situation. Should attempt to preserve them.
1265   NOT_LP64( movptr(swap_reg, saved_mark_addr); )
1266   load_prototype_header(tmp_reg, obj_reg);
1267   if (os::is_MP()) {
1268     lock();
1269   }
1270   cmpxchgptr(tmp_reg, mark_addr); // compare tmp_reg and swap_reg
1271   // Fall through to the normal CAS-based lock, because no matter what
1272   // the result of the above CAS, some thread must have succeeded in
1273   // removing the bias bit from the object's header.
1274   if (counters != NULL) {
1275     cond_inc32(Assembler::zero,
1276                ExternalAddress((address) counters->revoked_lock_entry_count_addr()));
1277   }
1278 
1279   bind(cas_label);
1280 
1281   return null_check_offset;
1282 }
1283 
1284 void MacroAssembler::biased_locking_exit(Register obj_reg, Register temp_reg, Label& done) {
1285   assert(UseBiasedLocking, "why call this otherwise?");
1286 
1287   // Check for biased locking unlock case, which is a no-op
1288   // Note: we do not have to check the thread ID for two reasons.
1289   // First, the interpreter checks for IllegalMonitorStateException at
1290   // a higher level. Second, if the bias was revoked while we held the
1291   // lock, the object could not be rebiased toward another thread, so
1292   // the bias bit would be clear.
1293   movptr(temp_reg, Address(obj_reg, oopDesc::mark_offset_in_bytes()));
1294   andptr(temp_reg, markOopDesc::biased_lock_mask_in_place);
1295   cmpptr(temp_reg, markOopDesc::biased_lock_pattern);
1296   jcc(Assembler::equal, done);
1297 }
1298 
1299 #ifdef COMPILER2
1300 
1301 #if INCLUDE_RTM_OPT
1302 
1303 // Update rtm_counters based on abort status
1304 // input: abort_status
1305 //        rtm_counters (RTMLockingCounters*)
1306 // flags are killed
1307 void MacroAssembler::rtm_counters_update(Register abort_status, Register rtm_counters) {
1308 
1309   atomic_incptr(Address(rtm_counters, RTMLockingCounters::abort_count_offset()));
1310   if (PrintPreciseRTMLockingStatistics) {
1311     for (int i = 0; i < RTMLockingCounters::ABORT_STATUS_LIMIT; i++) {
1312       Label check_abort;
1313       testl(abort_status, (1<<i));
1314       jccb(Assembler::equal, check_abort);
1315       atomic_incptr(Address(rtm_counters, RTMLockingCounters::abortX_count_offset() + (i * sizeof(uintx))));
1316       bind(check_abort);
1317     }
1318   }
1319 }
1320 
1321 // Branch if (random & (count-1) != 0), count is 2^n
1322 // tmp, scr and flags are killed
1323 void MacroAssembler::branch_on_random_using_rdtsc(Register tmp, Register scr, int count, Label& brLabel) {
1324   assert(tmp == rax, "");
1325   assert(scr == rdx, "");
1326   rdtsc(); // modifies EDX:EAX
1327   andptr(tmp, count-1);
1328   jccb(Assembler::notZero, brLabel);
1329 }
1330 
1331 // Perform abort ratio calculation, set no_rtm bit if high ratio
1332 // input:  rtm_counters_Reg (RTMLockingCounters* address)
1333 // tmpReg, rtm_counters_Reg and flags are killed
1334 void MacroAssembler::rtm_abort_ratio_calculation(Register tmpReg,
1335                                                  Register rtm_counters_Reg,
1336                                                  RTMLockingCounters* rtm_counters,
1337                                                  Metadata* method_data) {
1338   Label L_done, L_check_always_rtm1, L_check_always_rtm2;
1339 
1340   if (RTMLockingCalculationDelay > 0) {
1341     // Delay calculation
1342     movptr(tmpReg, ExternalAddress((address) RTMLockingCounters::rtm_calculation_flag_addr()), tmpReg);
1343     testptr(tmpReg, tmpReg);
1344     jccb(Assembler::equal, L_done);
1345   }
1346   // Abort ratio calculation only if abort_count > RTMAbortThreshold
1347   //   Aborted transactions = abort_count * 100
1348   //   All transactions = total_count *  RTMTotalCountIncrRate
1349   //   Set no_rtm bit if (Aborted transactions >= All transactions * RTMAbortRatio)
1350 
1351   movptr(tmpReg, Address(rtm_counters_Reg, RTMLockingCounters::abort_count_offset()));
1352   cmpptr(tmpReg, RTMAbortThreshold);
1353   jccb(Assembler::below, L_check_always_rtm2);
1354   imulptr(tmpReg, tmpReg, 100);
1355 
1356   Register scrReg = rtm_counters_Reg;
1357   movptr(scrReg, Address(rtm_counters_Reg, RTMLockingCounters::total_count_offset()));
1358   imulptr(scrReg, scrReg, RTMTotalCountIncrRate);
1359   imulptr(scrReg, scrReg, RTMAbortRatio);
1360   cmpptr(tmpReg, scrReg);
1361   jccb(Assembler::below, L_check_always_rtm1);
1362   if (method_data != NULL) {
1363     // set rtm_state to "no rtm" in MDO
1364     mov_metadata(tmpReg, method_data);
1365     if (os::is_MP()) {
1366       lock();
1367     }
1368     orl(Address(tmpReg, MethodData::rtm_state_offset_in_bytes()), NoRTM);
1369   }
1370   jmpb(L_done);
1371   bind(L_check_always_rtm1);
1372   // Reload RTMLockingCounters* address
1373   lea(rtm_counters_Reg, ExternalAddress((address)rtm_counters));
1374   bind(L_check_always_rtm2);
1375   movptr(tmpReg, Address(rtm_counters_Reg, RTMLockingCounters::total_count_offset()));
1376   cmpptr(tmpReg, RTMLockingThreshold / RTMTotalCountIncrRate);
1377   jccb(Assembler::below, L_done);
1378   if (method_data != NULL) {
1379     // set rtm_state to "always rtm" in MDO
1380     mov_metadata(tmpReg, method_data);
1381     if (os::is_MP()) {
1382       lock();
1383     }
1384     orl(Address(tmpReg, MethodData::rtm_state_offset_in_bytes()), UseRTM);
1385   }
1386   bind(L_done);
1387 }
1388 
1389 // Update counters and perform abort ratio calculation
1390 // input:  abort_status_Reg
1391 // rtm_counters_Reg, flags are killed
1392 void MacroAssembler::rtm_profiling(Register abort_status_Reg,
1393                                    Register rtm_counters_Reg,
1394                                    RTMLockingCounters* rtm_counters,
1395                                    Metadata* method_data,
1396                                    bool profile_rtm) {
1397 
1398   assert(rtm_counters != NULL, "should not be NULL when profiling RTM");
1399   // update rtm counters based on rax value at abort
1400   // reads abort_status_Reg, updates flags
1401   lea(rtm_counters_Reg, ExternalAddress((address)rtm_counters));
1402   rtm_counters_update(abort_status_Reg, rtm_counters_Reg);
1403   if (profile_rtm) {
1404     // Save abort status because abort_status_Reg is used by following code.
1405     if (RTMRetryCount > 0) {
1406       push(abort_status_Reg);
1407     }
1408     assert(rtm_counters != NULL, "should not be NULL when profiling RTM");
1409     rtm_abort_ratio_calculation(abort_status_Reg, rtm_counters_Reg, rtm_counters, method_data);
1410     // restore abort status
1411     if (RTMRetryCount > 0) {
1412       pop(abort_status_Reg);
1413     }
1414   }
1415 }
1416 
1417 // Retry on abort if abort's status is 0x6: can retry (0x2) | memory conflict (0x4)
1418 // inputs: retry_count_Reg
1419 //       : abort_status_Reg
1420 // output: retry_count_Reg decremented by 1
1421 // flags are killed
1422 void MacroAssembler::rtm_retry_lock_on_abort(Register retry_count_Reg, Register abort_status_Reg, Label& retryLabel) {
1423   Label doneRetry;
1424   assert(abort_status_Reg == rax, "");
1425   // The abort reason bits are in eax (see all states in rtmLocking.hpp)
1426   // 0x6 = conflict on which we can retry (0x2) | memory conflict (0x4)
1427   // if reason is in 0x6 and retry count != 0 then retry
1428   andptr(abort_status_Reg, 0x6);
1429   jccb(Assembler::zero, doneRetry);
1430   testl(retry_count_Reg, retry_count_Reg);
1431   jccb(Assembler::zero, doneRetry);
1432   pause();
1433   decrementl(retry_count_Reg);
1434   jmp(retryLabel);
1435   bind(doneRetry);
1436 }
1437 
1438 // Spin and retry if lock is busy,
1439 // inputs: box_Reg (monitor address)
1440 //       : retry_count_Reg
1441 // output: retry_count_Reg decremented by 1
1442 //       : clear z flag if retry count exceeded
1443 // tmp_Reg, scr_Reg, flags are killed
1444 void MacroAssembler::rtm_retry_lock_on_busy(Register retry_count_Reg, Register box_Reg,
1445                                             Register tmp_Reg, Register scr_Reg, Label& retryLabel) {
1446   Label SpinLoop, SpinExit, doneRetry;
1447   int owner_offset = OM_OFFSET_NO_MONITOR_VALUE_TAG(owner);
1448 
1449   testl(retry_count_Reg, retry_count_Reg);
1450   jccb(Assembler::zero, doneRetry);
1451   decrementl(retry_count_Reg);
1452   movptr(scr_Reg, RTMSpinLoopCount);
1453 
1454   bind(SpinLoop);
1455   pause();
1456   decrementl(scr_Reg);
1457   jccb(Assembler::lessEqual, SpinExit);
1458   movptr(tmp_Reg, Address(box_Reg, owner_offset));
1459   testptr(tmp_Reg, tmp_Reg);
1460   jccb(Assembler::notZero, SpinLoop);
1461 
1462   bind(SpinExit);
1463   jmp(retryLabel);
1464   bind(doneRetry);
1465   incrementl(retry_count_Reg); // clear z flag
1466 }
1467 
1468 // Use RTM for normal stack locks
1469 // Input: objReg (object to lock)
1470 void MacroAssembler::rtm_stack_locking(Register objReg, Register tmpReg, Register scrReg,
1471                                        Register retry_on_abort_count_Reg,
1472                                        RTMLockingCounters* stack_rtm_counters,
1473                                        Metadata* method_data, bool profile_rtm,
1474                                        Label& DONE_LABEL, Label& IsInflated) {
1475   assert(UseRTMForStackLocks, "why call this otherwise?");
1476   assert(!UseBiasedLocking, "Biased locking is not supported with RTM locking");
1477   assert(tmpReg == rax, "");
1478   assert(scrReg == rdx, "");
1479   Label L_rtm_retry, L_decrement_retry, L_on_abort;
1480 
1481   if (RTMRetryCount > 0) {
1482     movl(retry_on_abort_count_Reg, RTMRetryCount); // Retry on abort
1483     bind(L_rtm_retry);
1484   }
1485   movptr(tmpReg, Address(objReg, 0));
1486   testptr(tmpReg, markOopDesc::monitor_value);  // inflated vs stack-locked|neutral|biased
1487   jcc(Assembler::notZero, IsInflated);
1488 
1489   if (PrintPreciseRTMLockingStatistics || profile_rtm) {
1490     Label L_noincrement;
1491     if (RTMTotalCountIncrRate > 1) {
1492       // tmpReg, scrReg and flags are killed
1493       branch_on_random_using_rdtsc(tmpReg, scrReg, (int)RTMTotalCountIncrRate, L_noincrement);
1494     }
1495     assert(stack_rtm_counters != NULL, "should not be NULL when profiling RTM");
1496     atomic_incptr(ExternalAddress((address)stack_rtm_counters->total_count_addr()), scrReg);
1497     bind(L_noincrement);
1498   }
1499   xbegin(L_on_abort);
1500   movptr(tmpReg, Address(objReg, 0));       // fetch markword
1501   andptr(tmpReg, markOopDesc::biased_lock_mask_in_place); // look at 3 lock bits
1502   cmpptr(tmpReg, markOopDesc::unlocked_value);            // bits = 001 unlocked
1503   jcc(Assembler::equal, DONE_LABEL);        // all done if unlocked
1504 
1505   Register abort_status_Reg = tmpReg; // status of abort is stored in RAX
1506   if (UseRTMXendForLockBusy) {
1507     xend();
1508     movptr(abort_status_Reg, 0x2);   // Set the abort status to 2 (so we can retry)
1509     jmp(L_decrement_retry);
1510   }
1511   else {
1512     xabort(0);
1513   }
1514   bind(L_on_abort);
1515   if (PrintPreciseRTMLockingStatistics || profile_rtm) {
1516     rtm_profiling(abort_status_Reg, scrReg, stack_rtm_counters, method_data, profile_rtm);
1517   }
1518   bind(L_decrement_retry);
1519   if (RTMRetryCount > 0) {
1520     // retry on lock abort if abort status is 'can retry' (0x2) or 'memory conflict' (0x4)
1521     rtm_retry_lock_on_abort(retry_on_abort_count_Reg, abort_status_Reg, L_rtm_retry);
1522   }
1523 }
1524 
1525 // Use RTM for inflating locks
1526 // inputs: objReg (object to lock)
1527 //         boxReg (on-stack box address (displaced header location) - KILLED)
1528 //         tmpReg (ObjectMonitor address + markOopDesc::monitor_value)
1529 void MacroAssembler::rtm_inflated_locking(Register objReg, Register boxReg, Register tmpReg,
1530                                           Register scrReg, Register retry_on_busy_count_Reg,
1531                                           Register retry_on_abort_count_Reg,
1532                                           RTMLockingCounters* rtm_counters,
1533                                           Metadata* method_data, bool profile_rtm,
1534                                           Label& DONE_LABEL) {
1535   assert(UseRTMLocking, "why call this otherwise?");
1536   assert(tmpReg == rax, "");
1537   assert(scrReg == rdx, "");
1538   Label L_rtm_retry, L_decrement_retry, L_on_abort;
1539   int owner_offset = OM_OFFSET_NO_MONITOR_VALUE_TAG(owner);
1540 
1541   // Without cast to int32_t a movptr will destroy r10 which is typically obj
1542   movptr(Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark()));
1543   movptr(boxReg, tmpReg); // Save ObjectMonitor address
1544 
1545   if (RTMRetryCount > 0) {
1546     movl(retry_on_busy_count_Reg, RTMRetryCount);  // Retry on lock busy
1547     movl(retry_on_abort_count_Reg, RTMRetryCount); // Retry on abort
1548     bind(L_rtm_retry);
1549   }
1550   if (PrintPreciseRTMLockingStatistics || profile_rtm) {
1551     Label L_noincrement;
1552     if (RTMTotalCountIncrRate > 1) {
1553       // tmpReg, scrReg and flags are killed
1554       branch_on_random_using_rdtsc(tmpReg, scrReg, (int)RTMTotalCountIncrRate, L_noincrement);
1555     }
1556     assert(rtm_counters != NULL, "should not be NULL when profiling RTM");
1557     atomic_incptr(ExternalAddress((address)rtm_counters->total_count_addr()), scrReg);
1558     bind(L_noincrement);
1559   }
1560   xbegin(L_on_abort);
1561   movptr(tmpReg, Address(objReg, 0));
1562   movptr(tmpReg, Address(tmpReg, owner_offset));
1563   testptr(tmpReg, tmpReg);
1564   jcc(Assembler::zero, DONE_LABEL);
1565   if (UseRTMXendForLockBusy) {
1566     xend();
1567     jmp(L_decrement_retry);
1568   }
1569   else {
1570     xabort(0);
1571   }
1572   bind(L_on_abort);
1573   Register abort_status_Reg = tmpReg; // status of abort is stored in RAX
1574   if (PrintPreciseRTMLockingStatistics || profile_rtm) {
1575     rtm_profiling(abort_status_Reg, scrReg, rtm_counters, method_data, profile_rtm);
1576   }
1577   if (RTMRetryCount > 0) {
1578     // retry on lock abort if abort status is 'can retry' (0x2) or 'memory conflict' (0x4)
1579     rtm_retry_lock_on_abort(retry_on_abort_count_Reg, abort_status_Reg, L_rtm_retry);
1580   }
1581 
1582   movptr(tmpReg, Address(boxReg, owner_offset)) ;
1583   testptr(tmpReg, tmpReg) ;
1584   jccb(Assembler::notZero, L_decrement_retry) ;
1585 
1586   // Appears unlocked - try to swing _owner from null to non-null.
1587   // Invariant: tmpReg == 0.  tmpReg is EAX which is the implicit cmpxchg comparand.
1588 #ifdef _LP64
1589   Register threadReg = r15_thread;
1590 #else
1591   get_thread(scrReg);
1592   Register threadReg = scrReg;
1593 #endif
1594   if (os::is_MP()) {
1595     lock();
1596   }
1597   cmpxchgptr(threadReg, Address(boxReg, owner_offset)); // Updates tmpReg
1598 
1599   if (RTMRetryCount > 0) {
1600     // success done else retry
1601     jccb(Assembler::equal, DONE_LABEL) ;
1602     bind(L_decrement_retry);
1603     // Spin and retry if lock is busy.
1604     rtm_retry_lock_on_busy(retry_on_busy_count_Reg, boxReg, tmpReg, scrReg, L_rtm_retry);
1605   }
1606   else {
1607     bind(L_decrement_retry);
1608   }
1609 }
1610 
1611 #endif //  INCLUDE_RTM_OPT
1612 
1613 // Fast_Lock and Fast_Unlock used by C2
1614 
1615 // Because the transitions from emitted code to the runtime
1616 // monitorenter/exit helper stubs are so slow it's critical that
1617 // we inline both the stack-locking fast-path and the inflated fast path.
1618 //
1619 // See also: cmpFastLock and cmpFastUnlock.
1620 //
1621 // What follows is a specialized inline transliteration of the code
1622 // in slow_enter() and slow_exit().  If we're concerned about I$ bloat
1623 // another option would be to emit TrySlowEnter and TrySlowExit methods
1624 // at startup-time.  These methods would accept arguments as
1625 // (rax,=Obj, rbx=Self, rcx=box, rdx=Scratch) and return success-failure
1626 // indications in the icc.ZFlag.  Fast_Lock and Fast_Unlock would simply
1627 // marshal the arguments and emit calls to TrySlowEnter and TrySlowExit.
1628 // In practice, however, the # of lock sites is bounded and is usually small.
1629 // Besides the call overhead, TrySlowEnter and TrySlowExit might suffer
1630 // if the processor uses simple bimodal branch predictors keyed by EIP
1631 // Since the helper routines would be called from multiple synchronization
1632 // sites.
1633 //
1634 // An even better approach would be write "MonitorEnter()" and "MonitorExit()"
1635 // in java - using j.u.c and unsafe - and just bind the lock and unlock sites
1636 // to those specialized methods.  That'd give us a mostly platform-independent
1637 // implementation that the JITs could optimize and inline at their pleasure.
1638 // Done correctly, the only time we'd need to cross to native could would be
1639 // to park() or unpark() threads.  We'd also need a few more unsafe operators
1640 // to (a) prevent compiler-JIT reordering of non-volatile accesses, and
1641 // (b) explicit barriers or fence operations.
1642 //
1643 // TODO:
1644 //
1645 // *  Arrange for C2 to pass "Self" into Fast_Lock and Fast_Unlock in one of the registers (scr).
1646 //    This avoids manifesting the Self pointer in the Fast_Lock and Fast_Unlock terminals.
1647 //    Given TLAB allocation, Self is usually manifested in a register, so passing it into
1648 //    the lock operators would typically be faster than reifying Self.
1649 //
1650 // *  Ideally I'd define the primitives as:
1651 //       fast_lock   (nax Obj, nax box, EAX tmp, nax scr) where box, tmp and scr are KILLED.
1652 //       fast_unlock (nax Obj, EAX box, nax tmp) where box and tmp are KILLED
1653 //    Unfortunately ADLC bugs prevent us from expressing the ideal form.
1654 //    Instead, we're stuck with a rather awkward and brittle register assignments below.
1655 //    Furthermore the register assignments are overconstrained, possibly resulting in
1656 //    sub-optimal code near the synchronization site.
1657 //
1658 // *  Eliminate the sp-proximity tests and just use "== Self" tests instead.
1659 //    Alternately, use a better sp-proximity test.
1660 //
1661 // *  Currently ObjectMonitor._Owner can hold either an sp value or a (THREAD *) value.
1662 //    Either one is sufficient to uniquely identify a thread.
1663 //    TODO: eliminate use of sp in _owner and use get_thread(tr) instead.
1664 //
1665 // *  Intrinsify notify() and notifyAll() for the common cases where the
1666 //    object is locked by the calling thread but the waitlist is empty.
1667 //    avoid the expensive JNI call to JVM_Notify() and JVM_NotifyAll().
1668 //
1669 // *  use jccb and jmpb instead of jcc and jmp to improve code density.
1670 //    But beware of excessive branch density on AMD Opterons.
1671 //
1672 // *  Both Fast_Lock and Fast_Unlock set the ICC.ZF to indicate success
1673 //    or failure of the fast-path.  If the fast-path fails then we pass
1674 //    control to the slow-path, typically in C.  In Fast_Lock and
1675 //    Fast_Unlock we often branch to DONE_LABEL, just to find that C2
1676 //    will emit a conditional branch immediately after the node.
1677 //    So we have branches to branches and lots of ICC.ZF games.
1678 //    Instead, it might be better to have C2 pass a "FailureLabel"
1679 //    into Fast_Lock and Fast_Unlock.  In the case of success, control
1680 //    will drop through the node.  ICC.ZF is undefined at exit.
1681 //    In the case of failure, the node will branch directly to the
1682 //    FailureLabel
1683 
1684 
1685 // obj: object to lock
1686 // box: on-stack box address (displaced header location) - KILLED
1687 // rax,: tmp -- KILLED
1688 // scr: tmp -- KILLED
1689 void MacroAssembler::fast_lock(Register objReg, Register boxReg, Register tmpReg,
1690                                Register scrReg, Register cx1Reg, Register cx2Reg,
1691                                BiasedLockingCounters* counters,
1692                                RTMLockingCounters* rtm_counters,
1693                                RTMLockingCounters* stack_rtm_counters,
1694                                Metadata* method_data,
1695                                bool use_rtm, bool profile_rtm) {
1696   // Ensure the register assignments are disjoint
1697   assert(tmpReg == rax, "");
1698 
1699   if (use_rtm) {
1700     assert_different_registers(objReg, boxReg, tmpReg, scrReg, cx1Reg, cx2Reg);
1701   } else {
1702     assert(cx1Reg == noreg, "");
1703     assert(cx2Reg == noreg, "");
1704     assert_different_registers(objReg, boxReg, tmpReg, scrReg);
1705   }
1706 
1707   if (counters != NULL) {
1708     atomic_incl(ExternalAddress((address)counters->total_entry_count_addr()), scrReg);
1709   }
1710   if (EmitSync & 1) {
1711       // set box->dhw = markOopDesc::unused_mark()
1712       // Force all sync thru slow-path: slow_enter() and slow_exit()
1713       movptr (Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark()));
1714       cmpptr (rsp, (int32_t)NULL_WORD);
1715   } else {
1716     // Possible cases that we'll encounter in fast_lock
1717     // ------------------------------------------------
1718     // * Inflated
1719     //    -- unlocked
1720     //    -- Locked
1721     //       = by self
1722     //       = by other
1723     // * biased
1724     //    -- by Self
1725     //    -- by other
1726     // * neutral
1727     // * stack-locked
1728     //    -- by self
1729     //       = sp-proximity test hits
1730     //       = sp-proximity test generates false-negative
1731     //    -- by other
1732     //
1733 
1734     Label IsInflated, DONE_LABEL;
1735 
1736     // it's stack-locked, biased or neutral
1737     // TODO: optimize away redundant LDs of obj->mark and improve the markword triage
1738     // order to reduce the number of conditional branches in the most common cases.
1739     // Beware -- there's a subtle invariant that fetch of the markword
1740     // at [FETCH], below, will never observe a biased encoding (*101b).
1741     // If this invariant is not held we risk exclusion (safety) failure.
1742     if (UseBiasedLocking && !UseOptoBiasInlining) {
1743       biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, counters);
1744     }
1745 
1746 #if INCLUDE_RTM_OPT
1747     if (UseRTMForStackLocks && use_rtm) {
1748       rtm_stack_locking(objReg, tmpReg, scrReg, cx2Reg,
1749                         stack_rtm_counters, method_data, profile_rtm,
1750                         DONE_LABEL, IsInflated);
1751     }
1752 #endif // INCLUDE_RTM_OPT
1753 
1754     movptr(tmpReg, Address(objReg, 0));          // [FETCH]
1755     testptr(tmpReg, markOopDesc::monitor_value); // inflated vs stack-locked|neutral|biased
1756     jccb(Assembler::notZero, IsInflated);
1757 
1758     // Attempt stack-locking ...
1759     orptr (tmpReg, markOopDesc::unlocked_value);
1760     movptr(Address(boxReg, 0), tmpReg);          // Anticipate successful CAS
1761     if (os::is_MP()) {
1762       lock();
1763     }
1764     cmpxchgptr(boxReg, Address(objReg, 0));      // Updates tmpReg
1765     if (counters != NULL) {
1766       cond_inc32(Assembler::equal,
1767                  ExternalAddress((address)counters->fast_path_entry_count_addr()));
1768     }
1769     jcc(Assembler::equal, DONE_LABEL);           // Success
1770 
1771     // Recursive locking.
1772     // The object is stack-locked: markword contains stack pointer to BasicLock.
1773     // Locked by current thread if difference with current SP is less than one page.
1774     subptr(tmpReg, rsp);
1775     // Next instruction set ZFlag == 1 (Success) if difference is less then one page.
1776     andptr(tmpReg, (int32_t) (NOT_LP64(0xFFFFF003) LP64_ONLY(7 - os::vm_page_size())) );
1777     movptr(Address(boxReg, 0), tmpReg);
1778     if (counters != NULL) {
1779       cond_inc32(Assembler::equal,
1780                  ExternalAddress((address)counters->fast_path_entry_count_addr()));
1781     }
1782     jmp(DONE_LABEL);
1783 
1784     bind(IsInflated);
1785     // The object is inflated. tmpReg contains pointer to ObjectMonitor* + markOopDesc::monitor_value
1786 
1787 #if INCLUDE_RTM_OPT
1788     // Use the same RTM locking code in 32- and 64-bit VM.
1789     if (use_rtm) {
1790       rtm_inflated_locking(objReg, boxReg, tmpReg, scrReg, cx1Reg, cx2Reg,
1791                            rtm_counters, method_data, profile_rtm, DONE_LABEL);
1792     } else {
1793 #endif // INCLUDE_RTM_OPT
1794 
1795 #ifndef _LP64
1796     // The object is inflated.
1797 
1798     // boxReg refers to the on-stack BasicLock in the current frame.
1799     // We'd like to write:
1800     //   set box->_displaced_header = markOopDesc::unused_mark().  Any non-0 value suffices.
1801     // This is convenient but results a ST-before-CAS penalty.  The following CAS suffers
1802     // additional latency as we have another ST in the store buffer that must drain.
1803 
1804     if (EmitSync & 8192) {
1805        movptr(Address(boxReg, 0), 3);            // results in ST-before-CAS penalty
1806        get_thread (scrReg);
1807        movptr(boxReg, tmpReg);                    // consider: LEA box, [tmp-2]
1808        movptr(tmpReg, NULL_WORD);                 // consider: xor vs mov
1809        if (os::is_MP()) {
1810          lock();
1811        }
1812        cmpxchgptr(scrReg, Address(boxReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
1813     } else
1814     if ((EmitSync & 128) == 0) {                      // avoid ST-before-CAS
1815        // register juggle because we need tmpReg for cmpxchgptr below
1816        movptr(scrReg, boxReg);
1817        movptr(boxReg, tmpReg);                   // consider: LEA box, [tmp-2]
1818 
1819        // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes
1820        if ((EmitSync & 2048) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
1821           // prefetchw [eax + Offset(_owner)-2]
1822           prefetchw(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
1823        }
1824 
1825        if ((EmitSync & 64) == 0) {
1826          // Optimistic form: consider XORL tmpReg,tmpReg
1827          movptr(tmpReg, NULL_WORD);
1828        } else {
1829          // Can suffer RTS->RTO upgrades on shared or cold $ lines
1830          // Test-And-CAS instead of CAS
1831          movptr(tmpReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));   // rax, = m->_owner
1832          testptr(tmpReg, tmpReg);                   // Locked ?
1833          jccb  (Assembler::notZero, DONE_LABEL);
1834        }
1835 
1836        // Appears unlocked - try to swing _owner from null to non-null.
1837        // Ideally, I'd manifest "Self" with get_thread and then attempt
1838        // to CAS the register containing Self into m->Owner.
1839        // But we don't have enough registers, so instead we can either try to CAS
1840        // rsp or the address of the box (in scr) into &m->owner.  If the CAS succeeds
1841        // we later store "Self" into m->Owner.  Transiently storing a stack address
1842        // (rsp or the address of the box) into  m->owner is harmless.
1843        // Invariant: tmpReg == 0.  tmpReg is EAX which is the implicit cmpxchg comparand.
1844        if (os::is_MP()) {
1845          lock();
1846        }
1847        cmpxchgptr(scrReg, Address(boxReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
1848        movptr(Address(scrReg, 0), 3);          // box->_displaced_header = 3
1849        // If we weren't able to swing _owner from NULL to the BasicLock
1850        // then take the slow path.
1851        jccb  (Assembler::notZero, DONE_LABEL);
1852        // update _owner from BasicLock to thread
1853        get_thread (scrReg);                    // beware: clobbers ICCs
1854        movptr(Address(boxReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), scrReg);
1855        xorptr(boxReg, boxReg);                 // set icc.ZFlag = 1 to indicate success
1856 
1857        // If the CAS fails we can either retry or pass control to the slow-path.
1858        // We use the latter tactic.
1859        // Pass the CAS result in the icc.ZFlag into DONE_LABEL
1860        // If the CAS was successful ...
1861        //   Self has acquired the lock
1862        //   Invariant: m->_recursions should already be 0, so we don't need to explicitly set it.
1863        // Intentional fall-through into DONE_LABEL ...
1864     } else {
1865        movptr(Address(boxReg, 0), intptr_t(markOopDesc::unused_mark()));  // results in ST-before-CAS penalty
1866        movptr(boxReg, tmpReg);
1867 
1868        // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes
1869        if ((EmitSync & 2048) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
1870           // prefetchw [eax + Offset(_owner)-2]
1871           prefetchw(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
1872        }
1873 
1874        if ((EmitSync & 64) == 0) {
1875          // Optimistic form
1876          xorptr  (tmpReg, tmpReg);
1877        } else {
1878          // Can suffer RTS->RTO upgrades on shared or cold $ lines
1879          movptr(tmpReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));   // rax, = m->_owner
1880          testptr(tmpReg, tmpReg);                   // Locked ?
1881          jccb  (Assembler::notZero, DONE_LABEL);
1882        }
1883 
1884        // Appears unlocked - try to swing _owner from null to non-null.
1885        // Use either "Self" (in scr) or rsp as thread identity in _owner.
1886        // Invariant: tmpReg == 0.  tmpReg is EAX which is the implicit cmpxchg comparand.
1887        get_thread (scrReg);
1888        if (os::is_MP()) {
1889          lock();
1890        }
1891        cmpxchgptr(scrReg, Address(boxReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
1892 
1893        // If the CAS fails we can either retry or pass control to the slow-path.
1894        // We use the latter tactic.
1895        // Pass the CAS result in the icc.ZFlag into DONE_LABEL
1896        // If the CAS was successful ...
1897        //   Self has acquired the lock
1898        //   Invariant: m->_recursions should already be 0, so we don't need to explicitly set it.
1899        // Intentional fall-through into DONE_LABEL ...
1900     }
1901 #else // _LP64
1902     // It's inflated
1903     movq(scrReg, tmpReg);
1904     xorq(tmpReg, tmpReg);
1905 
1906     if (os::is_MP()) {
1907       lock();
1908     }
1909     cmpxchgptr(r15_thread, Address(scrReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
1910     // Unconditionally set box->_displaced_header = markOopDesc::unused_mark().
1911     // Without cast to int32_t movptr will destroy r10 which is typically obj.
1912     movptr(Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark()));
1913     // Intentional fall-through into DONE_LABEL ...
1914     // Propagate ICC.ZF from CAS above into DONE_LABEL.
1915 #endif // _LP64
1916 #if INCLUDE_RTM_OPT
1917     } // use_rtm()
1918 #endif
1919     // DONE_LABEL is a hot target - we'd really like to place it at the
1920     // start of cache line by padding with NOPs.
1921     // See the AMD and Intel software optimization manuals for the
1922     // most efficient "long" NOP encodings.
1923     // Unfortunately none of our alignment mechanisms suffice.
1924     bind(DONE_LABEL);
1925 
1926     // At DONE_LABEL the icc ZFlag is set as follows ...
1927     // Fast_Unlock uses the same protocol.
1928     // ZFlag == 1 -> Success
1929     // ZFlag == 0 -> Failure - force control through the slow-path
1930   }
1931 }
1932 
1933 // obj: object to unlock
1934 // box: box address (displaced header location), killed.  Must be EAX.
1935 // tmp: killed, cannot be obj nor box.
1936 //
1937 // Some commentary on balanced locking:
1938 //
1939 // Fast_Lock and Fast_Unlock are emitted only for provably balanced lock sites.
1940 // Methods that don't have provably balanced locking are forced to run in the
1941 // interpreter - such methods won't be compiled to use fast_lock and fast_unlock.
1942 // The interpreter provides two properties:
1943 // I1:  At return-time the interpreter automatically and quietly unlocks any
1944 //      objects acquired the current activation (frame).  Recall that the
1945 //      interpreter maintains an on-stack list of locks currently held by
1946 //      a frame.
1947 // I2:  If a method attempts to unlock an object that is not held by the
1948 //      the frame the interpreter throws IMSX.
1949 //
1950 // Lets say A(), which has provably balanced locking, acquires O and then calls B().
1951 // B() doesn't have provably balanced locking so it runs in the interpreter.
1952 // Control returns to A() and A() unlocks O.  By I1 and I2, above, we know that O
1953 // is still locked by A().
1954 //
1955 // The only other source of unbalanced locking would be JNI.  The "Java Native Interface:
1956 // Programmer's Guide and Specification" claims that an object locked by jni_monitorenter
1957 // should not be unlocked by "normal" java-level locking and vice-versa.  The specification
1958 // doesn't specify what will occur if a program engages in such mixed-mode locking, however.
1959 // Arguably given that the spec legislates the JNI case as undefined our implementation
1960 // could reasonably *avoid* checking owner in Fast_Unlock().
1961 // In the interest of performance we elide m->Owner==Self check in unlock.
1962 // A perfectly viable alternative is to elide the owner check except when
1963 // Xcheck:jni is enabled.
1964 
1965 void MacroAssembler::fast_unlock(Register objReg, Register boxReg, Register tmpReg, bool use_rtm) {
1966   assert(boxReg == rax, "");
1967   assert_different_registers(objReg, boxReg, tmpReg);
1968 
1969   if (EmitSync & 4) {
1970     // Disable - inhibit all inlining.  Force control through the slow-path
1971     cmpptr (rsp, 0);
1972   } else {
1973     Label DONE_LABEL, Stacked, CheckSucc;
1974 
1975     // Critically, the biased locking test must have precedence over
1976     // and appear before the (box->dhw == 0) recursive stack-lock test.
1977     if (UseBiasedLocking && !UseOptoBiasInlining) {
1978        biased_locking_exit(objReg, tmpReg, DONE_LABEL);
1979     }
1980 
1981 #if INCLUDE_RTM_OPT
1982     if (UseRTMForStackLocks && use_rtm) {
1983       assert(!UseBiasedLocking, "Biased locking is not supported with RTM locking");
1984       Label L_regular_unlock;
1985       movptr(tmpReg, Address(objReg, 0));           // fetch markword
1986       andptr(tmpReg, markOopDesc::biased_lock_mask_in_place); // look at 3 lock bits
1987       cmpptr(tmpReg, markOopDesc::unlocked_value);            // bits = 001 unlocked
1988       jccb(Assembler::notEqual, L_regular_unlock);  // if !HLE RegularLock
1989       xend();                                       // otherwise end...
1990       jmp(DONE_LABEL);                              // ... and we're done
1991       bind(L_regular_unlock);
1992     }
1993 #endif
1994 
1995     cmpptr(Address(boxReg, 0), (int32_t)NULL_WORD); // Examine the displaced header
1996     jcc   (Assembler::zero, DONE_LABEL);            // 0 indicates recursive stack-lock
1997     movptr(tmpReg, Address(objReg, 0));             // Examine the object's markword
1998     testptr(tmpReg, markOopDesc::monitor_value);    // Inflated?
1999     jccb  (Assembler::zero, Stacked);
2000 
2001     // It's inflated.
2002 #if INCLUDE_RTM_OPT
2003     if (use_rtm) {
2004       Label L_regular_inflated_unlock;
2005       int owner_offset = OM_OFFSET_NO_MONITOR_VALUE_TAG(owner);
2006       movptr(boxReg, Address(tmpReg, owner_offset));
2007       testptr(boxReg, boxReg);
2008       jccb(Assembler::notZero, L_regular_inflated_unlock);
2009       xend();
2010       jmpb(DONE_LABEL);
2011       bind(L_regular_inflated_unlock);
2012     }
2013 #endif
2014 
2015     // Despite our balanced locking property we still check that m->_owner == Self
2016     // as java routines or native JNI code called by this thread might
2017     // have released the lock.
2018     // Refer to the comments in synchronizer.cpp for how we might encode extra
2019     // state in _succ so we can avoid fetching EntryList|cxq.
2020     //
2021     // I'd like to add more cases in fast_lock() and fast_unlock() --
2022     // such as recursive enter and exit -- but we have to be wary of
2023     // I$ bloat, T$ effects and BP$ effects.
2024     //
2025     // If there's no contention try a 1-0 exit.  That is, exit without
2026     // a costly MEMBAR or CAS.  See synchronizer.cpp for details on how
2027     // we detect and recover from the race that the 1-0 exit admits.
2028     //
2029     // Conceptually Fast_Unlock() must execute a STST|LDST "release" barrier
2030     // before it STs null into _owner, releasing the lock.  Updates
2031     // to data protected by the critical section must be visible before
2032     // we drop the lock (and thus before any other thread could acquire
2033     // the lock and observe the fields protected by the lock).
2034     // IA32's memory-model is SPO, so STs are ordered with respect to
2035     // each other and there's no need for an explicit barrier (fence).
2036     // See also http://gee.cs.oswego.edu/dl/jmm/cookbook.html.
2037 #ifndef _LP64
2038     get_thread (boxReg);
2039     if ((EmitSync & 4096) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
2040       // prefetchw [ebx + Offset(_owner)-2]
2041       prefetchw(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
2042     }
2043 
2044     // Note that we could employ various encoding schemes to reduce
2045     // the number of loads below (currently 4) to just 2 or 3.
2046     // Refer to the comments in synchronizer.cpp.
2047     // In practice the chain of fetches doesn't seem to impact performance, however.
2048     xorptr(boxReg, boxReg);
2049     if ((EmitSync & 65536) == 0 && (EmitSync & 256)) {
2050        // Attempt to reduce branch density - AMD's branch predictor.
2051        orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(recursions)));
2052        orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(EntryList)));
2053        orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(cxq)));
2054        jccb  (Assembler::notZero, DONE_LABEL);
2055        movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), NULL_WORD);
2056        jmpb  (DONE_LABEL);
2057     } else {
2058        orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(recursions)));
2059        jccb  (Assembler::notZero, DONE_LABEL);
2060        movptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(EntryList)));
2061        orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(cxq)));
2062        jccb  (Assembler::notZero, CheckSucc);
2063        movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), NULL_WORD);
2064        jmpb  (DONE_LABEL);
2065     }
2066 
2067     // The Following code fragment (EmitSync & 65536) improves the performance of
2068     // contended applications and contended synchronization microbenchmarks.
2069     // Unfortunately the emission of the code - even though not executed - causes regressions
2070     // in scimark and jetstream, evidently because of $ effects.  Replacing the code
2071     // with an equal number of never-executed NOPs results in the same regression.
2072     // We leave it off by default.
2073 
2074     if ((EmitSync & 65536) != 0) {
2075        Label LSuccess, LGoSlowPath ;
2076 
2077        bind  (CheckSucc);
2078 
2079        // Optional pre-test ... it's safe to elide this
2080        cmpptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(succ)), (int32_t)NULL_WORD);
2081        jccb(Assembler::zero, LGoSlowPath);
2082 
2083        // We have a classic Dekker-style idiom:
2084        //    ST m->_owner = 0 ; MEMBAR; LD m->_succ
2085        // There are a number of ways to implement the barrier:
2086        // (1) lock:andl &m->_owner, 0
2087        //     is fast, but mask doesn't currently support the "ANDL M,IMM32" form.
2088        //     LOCK: ANDL [ebx+Offset(_Owner)-2], 0
2089        //     Encodes as 81 31 OFF32 IMM32 or 83 63 OFF8 IMM8
2090        // (2) If supported, an explicit MFENCE is appealing.
2091        //     In older IA32 processors MFENCE is slower than lock:add or xchg
2092        //     particularly if the write-buffer is full as might be the case if
2093        //     if stores closely precede the fence or fence-equivalent instruction.
2094        //     See https://blogs.oracle.com/dave/entry/instruction_selection_for_volatile_fences
2095        //     as the situation has changed with Nehalem and Shanghai.
2096        // (3) In lieu of an explicit fence, use lock:addl to the top-of-stack
2097        //     The $lines underlying the top-of-stack should be in M-state.
2098        //     The locked add instruction is serializing, of course.
2099        // (4) Use xchg, which is serializing
2100        //     mov boxReg, 0; xchgl boxReg, [tmpReg + Offset(_owner)-2] also works
2101        // (5) ST m->_owner = 0 and then execute lock:orl &m->_succ, 0.
2102        //     The integer condition codes will tell us if succ was 0.
2103        //     Since _succ and _owner should reside in the same $line and
2104        //     we just stored into _owner, it's likely that the $line
2105        //     remains in M-state for the lock:orl.
2106        //
2107        // We currently use (3), although it's likely that switching to (2)
2108        // is correct for the future.
2109 
2110        movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), NULL_WORD);
2111        if (os::is_MP()) {
2112          lock(); addptr(Address(rsp, 0), 0);
2113        }
2114        // Ratify _succ remains non-null
2115        cmpptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(succ)), 0);
2116        jccb  (Assembler::notZero, LSuccess);
2117 
2118        xorptr(boxReg, boxReg);                  // box is really EAX
2119        if (os::is_MP()) { lock(); }
2120        cmpxchgptr(rsp, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
2121        // There's no successor so we tried to regrab the lock with the
2122        // placeholder value. If that didn't work, then another thread
2123        // grabbed the lock so we're done (and exit was a success).
2124        jccb  (Assembler::notEqual, LSuccess);
2125        // Since we're low on registers we installed rsp as a placeholding in _owner.
2126        // Now install Self over rsp.  This is safe as we're transitioning from
2127        // non-null to non=null
2128        get_thread (boxReg);
2129        movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), boxReg);
2130        // Intentional fall-through into LGoSlowPath ...
2131 
2132        bind  (LGoSlowPath);
2133        orptr(boxReg, 1);                      // set ICC.ZF=0 to indicate failure
2134        jmpb  (DONE_LABEL);
2135 
2136        bind  (LSuccess);
2137        xorptr(boxReg, boxReg);                 // set ICC.ZF=1 to indicate success
2138        jmpb  (DONE_LABEL);
2139     }
2140 
2141     bind (Stacked);
2142     // It's not inflated and it's not recursively stack-locked and it's not biased.
2143     // It must be stack-locked.
2144     // Try to reset the header to displaced header.
2145     // The "box" value on the stack is stable, so we can reload
2146     // and be assured we observe the same value as above.
2147     movptr(tmpReg, Address(boxReg, 0));
2148     if (os::is_MP()) {
2149       lock();
2150     }
2151     cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses RAX which is box
2152     // Intention fall-thru into DONE_LABEL
2153 
2154     // DONE_LABEL is a hot target - we'd really like to place it at the
2155     // start of cache line by padding with NOPs.
2156     // See the AMD and Intel software optimization manuals for the
2157     // most efficient "long" NOP encodings.
2158     // Unfortunately none of our alignment mechanisms suffice.
2159     if ((EmitSync & 65536) == 0) {
2160        bind (CheckSucc);
2161     }
2162 #else // _LP64
2163     // It's inflated
2164     if (EmitSync & 1024) {
2165       // Emit code to check that _owner == Self
2166       // We could fold the _owner test into subsequent code more efficiently
2167       // than using a stand-alone check, but since _owner checking is off by
2168       // default we don't bother. We also might consider predicating the
2169       // _owner==Self check on Xcheck:jni or running on a debug build.
2170       movptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
2171       xorptr(boxReg, r15_thread);
2172     } else {
2173       xorptr(boxReg, boxReg);
2174     }
2175     orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(recursions)));
2176     jccb  (Assembler::notZero, DONE_LABEL);
2177     movptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(cxq)));
2178     orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(EntryList)));
2179     jccb  (Assembler::notZero, CheckSucc);
2180     movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), (int32_t)NULL_WORD);
2181     jmpb  (DONE_LABEL);
2182 
2183     if ((EmitSync & 65536) == 0) {
2184       // Try to avoid passing control into the slow_path ...
2185       Label LSuccess, LGoSlowPath ;
2186       bind  (CheckSucc);
2187 
2188       // The following optional optimization can be elided if necessary
2189       // Effectively: if (succ == null) goto SlowPath
2190       // The code reduces the window for a race, however,
2191       // and thus benefits performance.
2192       cmpptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(succ)), (int32_t)NULL_WORD);
2193       jccb  (Assembler::zero, LGoSlowPath);
2194 
2195       xorptr(boxReg, boxReg);
2196       if ((EmitSync & 16) && os::is_MP()) {
2197         xchgptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
2198       } else {
2199         movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), (int32_t)NULL_WORD);
2200         if (os::is_MP()) {
2201           // Memory barrier/fence
2202           // Dekker pivot point -- fulcrum : ST Owner; MEMBAR; LD Succ
2203           // Instead of MFENCE we use a dummy locked add of 0 to the top-of-stack.
2204           // This is faster on Nehalem and AMD Shanghai/Barcelona.
2205           // See https://blogs.oracle.com/dave/entry/instruction_selection_for_volatile_fences
2206           // We might also restructure (ST Owner=0;barrier;LD _Succ) to
2207           // (mov box,0; xchgq box, &m->Owner; LD _succ) .
2208           lock(); addl(Address(rsp, 0), 0);
2209         }
2210       }
2211       cmpptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(succ)), (int32_t)NULL_WORD);
2212       jccb  (Assembler::notZero, LSuccess);
2213 
2214       // Rare inopportune interleaving - race.
2215       // The successor vanished in the small window above.
2216       // The lock is contended -- (cxq|EntryList) != null -- and there's no apparent successor.
2217       // We need to ensure progress and succession.
2218       // Try to reacquire the lock.
2219       // If that fails then the new owner is responsible for succession and this
2220       // thread needs to take no further action and can exit via the fast path (success).
2221       // If the re-acquire succeeds then pass control into the slow path.
2222       // As implemented, this latter mode is horrible because we generated more
2223       // coherence traffic on the lock *and* artifically extended the critical section
2224       // length while by virtue of passing control into the slow path.
2225 
2226       // box is really RAX -- the following CMPXCHG depends on that binding
2227       // cmpxchg R,[M] is equivalent to rax = CAS(M,rax,R)
2228       if (os::is_MP()) { lock(); }
2229       cmpxchgptr(r15_thread, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
2230       // There's no successor so we tried to regrab the lock.
2231       // If that didn't work, then another thread grabbed the
2232       // lock so we're done (and exit was a success).
2233       jccb  (Assembler::notEqual, LSuccess);
2234       // Intentional fall-through into slow-path
2235 
2236       bind  (LGoSlowPath);
2237       orl   (boxReg, 1);                      // set ICC.ZF=0 to indicate failure
2238       jmpb  (DONE_LABEL);
2239 
2240       bind  (LSuccess);
2241       testl (boxReg, 0);                      // set ICC.ZF=1 to indicate success
2242       jmpb  (DONE_LABEL);
2243     }
2244 
2245     bind  (Stacked);
2246     movptr(tmpReg, Address (boxReg, 0));      // re-fetch
2247     if (os::is_MP()) { lock(); }
2248     cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses RAX which is box
2249 
2250     if (EmitSync & 65536) {
2251        bind (CheckSucc);
2252     }
2253 #endif
2254     bind(DONE_LABEL);
2255   }
2256 }
2257 #endif // COMPILER2
2258 
2259 void MacroAssembler::c2bool(Register x) {
2260   // implements x == 0 ? 0 : 1
2261   // note: must only look at least-significant byte of x
2262   //       since C-style booleans are stored in one byte
2263   //       only! (was bug)
2264   andl(x, 0xFF);
2265   setb(Assembler::notZero, x);
2266 }
2267 
2268 // Wouldn't need if AddressLiteral version had new name
2269 void MacroAssembler::call(Label& L, relocInfo::relocType rtype) {
2270   Assembler::call(L, rtype);
2271 }
2272 
2273 void MacroAssembler::call(Register entry) {
2274   Assembler::call(entry);
2275 }
2276 
2277 void MacroAssembler::call(AddressLiteral entry) {
2278   if (reachable(entry)) {
2279     Assembler::call_literal(entry.target(), entry.rspec());
2280   } else {
2281     lea(rscratch1, entry);
2282     Assembler::call(rscratch1);
2283   }
2284 }
2285 
2286 void MacroAssembler::ic_call(address entry, jint method_index) {
2287   RelocationHolder rh = virtual_call_Relocation::spec(pc(), method_index);
2288   movptr(rax, (intptr_t)Universe::non_oop_word());
2289   call(AddressLiteral(entry, rh));
2290 }
2291 
2292 // Implementation of call_VM versions
2293 
2294 void MacroAssembler::call_VM(Register oop_result,
2295                              address entry_point,
2296                              bool check_exceptions) {
2297   Label C, E;
2298   call(C, relocInfo::none);
2299   jmp(E);
2300 
2301   bind(C);
2302   call_VM_helper(oop_result, entry_point, 0, check_exceptions);
2303   ret(0);
2304 
2305   bind(E);
2306 }
2307 
2308 void MacroAssembler::call_VM(Register oop_result,
2309                              address entry_point,
2310                              Register arg_1,
2311                              bool check_exceptions) {
2312   Label C, E;
2313   call(C, relocInfo::none);
2314   jmp(E);
2315 
2316   bind(C);
2317   pass_arg1(this, arg_1);
2318   call_VM_helper(oop_result, entry_point, 1, check_exceptions);
2319   ret(0);
2320 
2321   bind(E);
2322 }
2323 
2324 void MacroAssembler::call_VM(Register oop_result,
2325                              address entry_point,
2326                              Register arg_1,
2327                              Register arg_2,
2328                              bool check_exceptions) {
2329   Label C, E;
2330   call(C, relocInfo::none);
2331   jmp(E);
2332 
2333   bind(C);
2334 
2335   LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2336 
2337   pass_arg2(this, arg_2);
2338   pass_arg1(this, arg_1);
2339   call_VM_helper(oop_result, entry_point, 2, check_exceptions);
2340   ret(0);
2341 
2342   bind(E);
2343 }
2344 
2345 void MacroAssembler::call_VM(Register oop_result,
2346                              address entry_point,
2347                              Register arg_1,
2348                              Register arg_2,
2349                              Register arg_3,
2350                              bool check_exceptions) {
2351   Label C, E;
2352   call(C, relocInfo::none);
2353   jmp(E);
2354 
2355   bind(C);
2356 
2357   LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
2358   LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
2359   pass_arg3(this, arg_3);
2360 
2361   LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2362   pass_arg2(this, arg_2);
2363 
2364   pass_arg1(this, arg_1);
2365   call_VM_helper(oop_result, entry_point, 3, check_exceptions);
2366   ret(0);
2367 
2368   bind(E);
2369 }
2370 
2371 void MacroAssembler::call_VM(Register oop_result,
2372                              Register last_java_sp,
2373                              address entry_point,
2374                              int number_of_arguments,
2375                              bool check_exceptions) {
2376   Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg);
2377   call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions);
2378 }
2379 
2380 void MacroAssembler::call_VM(Register oop_result,
2381                              Register last_java_sp,
2382                              address entry_point,
2383                              Register arg_1,
2384                              bool check_exceptions) {
2385   pass_arg1(this, arg_1);
2386   call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
2387 }
2388 
2389 void MacroAssembler::call_VM(Register oop_result,
2390                              Register last_java_sp,
2391                              address entry_point,
2392                              Register arg_1,
2393                              Register arg_2,
2394                              bool check_exceptions) {
2395 
2396   LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2397   pass_arg2(this, arg_2);
2398   pass_arg1(this, arg_1);
2399   call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
2400 }
2401 
2402 void MacroAssembler::call_VM(Register oop_result,
2403                              Register last_java_sp,
2404                              address entry_point,
2405                              Register arg_1,
2406                              Register arg_2,
2407                              Register arg_3,
2408                              bool check_exceptions) {
2409   LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
2410   LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
2411   pass_arg3(this, arg_3);
2412   LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2413   pass_arg2(this, arg_2);
2414   pass_arg1(this, arg_1);
2415   call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
2416 }
2417 
2418 void MacroAssembler::super_call_VM(Register oop_result,
2419                                    Register last_java_sp,
2420                                    address entry_point,
2421                                    int number_of_arguments,
2422                                    bool check_exceptions) {
2423   Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg);
2424   MacroAssembler::call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions);
2425 }
2426 
2427 void MacroAssembler::super_call_VM(Register oop_result,
2428                                    Register last_java_sp,
2429                                    address entry_point,
2430                                    Register arg_1,
2431                                    bool check_exceptions) {
2432   pass_arg1(this, arg_1);
2433   super_call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
2434 }
2435 
2436 void MacroAssembler::super_call_VM(Register oop_result,
2437                                    Register last_java_sp,
2438                                    address entry_point,
2439                                    Register arg_1,
2440                                    Register arg_2,
2441                                    bool check_exceptions) {
2442 
2443   LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2444   pass_arg2(this, arg_2);
2445   pass_arg1(this, arg_1);
2446   super_call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
2447 }
2448 
2449 void MacroAssembler::super_call_VM(Register oop_result,
2450                                    Register last_java_sp,
2451                                    address entry_point,
2452                                    Register arg_1,
2453                                    Register arg_2,
2454                                    Register arg_3,
2455                                    bool check_exceptions) {
2456   LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
2457   LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
2458   pass_arg3(this, arg_3);
2459   LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2460   pass_arg2(this, arg_2);
2461   pass_arg1(this, arg_1);
2462   super_call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
2463 }
2464 
2465 void MacroAssembler::call_VM_base(Register oop_result,
2466                                   Register java_thread,
2467                                   Register last_java_sp,
2468                                   address  entry_point,
2469                                   int      number_of_arguments,
2470                                   bool     check_exceptions) {
2471   // determine java_thread register
2472   if (!java_thread->is_valid()) {
2473 #ifdef _LP64
2474     java_thread = r15_thread;
2475 #else
2476     java_thread = rdi;
2477     get_thread(java_thread);
2478 #endif // LP64
2479   }
2480   // determine last_java_sp register
2481   if (!last_java_sp->is_valid()) {
2482     last_java_sp = rsp;
2483   }
2484   // debugging support
2485   assert(number_of_arguments >= 0   , "cannot have negative number of arguments");
2486   LP64_ONLY(assert(java_thread == r15_thread, "unexpected register"));
2487 #ifdef ASSERT
2488   // TraceBytecodes does not use r12 but saves it over the call, so don't verify
2489   // r12 is the heapbase.
2490   LP64_ONLY(if ((UseCompressedOops || UseCompressedClassPointers) && !TraceBytecodes) verify_heapbase("call_VM_base: heap base corrupted?");)
2491 #endif // ASSERT
2492 
2493   assert(java_thread != oop_result  , "cannot use the same register for java_thread & oop_result");
2494   assert(java_thread != last_java_sp, "cannot use the same register for java_thread & last_java_sp");
2495 
2496   // push java thread (becomes first argument of C function)
2497 
2498   NOT_LP64(push(java_thread); number_of_arguments++);
2499   LP64_ONLY(mov(c_rarg0, r15_thread));
2500 
2501   // set last Java frame before call
2502   assert(last_java_sp != rbp, "can't use ebp/rbp");
2503 
2504   // Only interpreter should have to set fp
2505   set_last_Java_frame(java_thread, last_java_sp, rbp, NULL);
2506 
2507   // do the call, remove parameters
2508   MacroAssembler::call_VM_leaf_base(entry_point, number_of_arguments);
2509 
2510   // restore the thread (cannot use the pushed argument since arguments
2511   // may be overwritten by C code generated by an optimizing compiler);
2512   // however can use the register value directly if it is callee saved.
2513   if (LP64_ONLY(true ||) java_thread == rdi || java_thread == rsi) {
2514     // rdi & rsi (also r15) are callee saved -> nothing to do
2515 #ifdef ASSERT
2516     guarantee(java_thread != rax, "change this code");
2517     push(rax);
2518     { Label L;
2519       get_thread(rax);
2520       cmpptr(java_thread, rax);
2521       jcc(Assembler::equal, L);
2522       STOP("MacroAssembler::call_VM_base: rdi not callee saved?");
2523       bind(L);
2524     }
2525     pop(rax);
2526 #endif
2527   } else {
2528     get_thread(java_thread);
2529   }
2530   // reset last Java frame
2531   // Only interpreter should have to clear fp
2532   reset_last_Java_frame(java_thread, true);
2533 
2534    // C++ interp handles this in the interpreter
2535   check_and_handle_popframe(java_thread);
2536   check_and_handle_earlyret(java_thread);
2537 
2538   if (check_exceptions) {
2539     // check for pending exceptions (java_thread is set upon return)
2540     cmpptr(Address(java_thread, Thread::pending_exception_offset()), (int32_t) NULL_WORD);
2541 #ifndef _LP64
2542     jump_cc(Assembler::notEqual,
2543             RuntimeAddress(StubRoutines::forward_exception_entry()));
2544 #else
2545     // This used to conditionally jump to forward_exception however it is
2546     // possible if we relocate that the branch will not reach. So we must jump
2547     // around so we can always reach
2548 
2549     Label ok;
2550     jcc(Assembler::equal, ok);
2551     jump(RuntimeAddress(StubRoutines::forward_exception_entry()));
2552     bind(ok);
2553 #endif // LP64
2554   }
2555 
2556   // get oop result if there is one and reset the value in the thread
2557   if (oop_result->is_valid()) {
2558     get_vm_result(oop_result, java_thread);
2559   }
2560 }
2561 
2562 void MacroAssembler::call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) {
2563 
2564   // Calculate the value for last_Java_sp
2565   // somewhat subtle. call_VM does an intermediate call
2566   // which places a return address on the stack just under the
2567   // stack pointer as the user finsihed with it. This allows
2568   // use to retrieve last_Java_pc from last_Java_sp[-1].
2569   // On 32bit we then have to push additional args on the stack to accomplish
2570   // the actual requested call. On 64bit call_VM only can use register args
2571   // so the only extra space is the return address that call_VM created.
2572   // This hopefully explains the calculations here.
2573 
2574 #ifdef _LP64
2575   // We've pushed one address, correct last_Java_sp
2576   lea(rax, Address(rsp, wordSize));
2577 #else
2578   lea(rax, Address(rsp, (1 + number_of_arguments) * wordSize));
2579 #endif // LP64
2580 
2581   call_VM_base(oop_result, noreg, rax, entry_point, number_of_arguments, check_exceptions);
2582 
2583 }
2584 
2585 // Use this method when MacroAssembler version of call_VM_leaf_base() should be called from Interpreter.
2586 void MacroAssembler::call_VM_leaf0(address entry_point) {
2587   MacroAssembler::call_VM_leaf_base(entry_point, 0);
2588 }
2589 
2590 void MacroAssembler::call_VM_leaf(address entry_point, int number_of_arguments) {
2591   call_VM_leaf_base(entry_point, number_of_arguments);
2592 }
2593 
2594 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0) {
2595   pass_arg0(this, arg_0);
2596   call_VM_leaf(entry_point, 1);
2597 }
2598 
2599 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
2600 
2601   LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2602   pass_arg1(this, arg_1);
2603   pass_arg0(this, arg_0);
2604   call_VM_leaf(entry_point, 2);
2605 }
2606 
2607 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
2608   LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg"));
2609   LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2610   pass_arg2(this, arg_2);
2611   LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2612   pass_arg1(this, arg_1);
2613   pass_arg0(this, arg_0);
2614   call_VM_leaf(entry_point, 3);
2615 }
2616 
2617 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0) {
2618   pass_arg0(this, arg_0);
2619   MacroAssembler::call_VM_leaf_base(entry_point, 1);
2620 }
2621 
2622 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
2623 
2624   LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2625   pass_arg1(this, arg_1);
2626   pass_arg0(this, arg_0);
2627   MacroAssembler::call_VM_leaf_base(entry_point, 2);
2628 }
2629 
2630 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
2631   LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg"));
2632   LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2633   pass_arg2(this, arg_2);
2634   LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2635   pass_arg1(this, arg_1);
2636   pass_arg0(this, arg_0);
2637   MacroAssembler::call_VM_leaf_base(entry_point, 3);
2638 }
2639 
2640 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2, Register arg_3) {
2641   LP64_ONLY(assert(arg_0 != c_rarg3, "smashed arg"));
2642   LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
2643   LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
2644   pass_arg3(this, arg_3);
2645   LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg"));
2646   LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2647   pass_arg2(this, arg_2);
2648   LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2649   pass_arg1(this, arg_1);
2650   pass_arg0(this, arg_0);
2651   MacroAssembler::call_VM_leaf_base(entry_point, 4);
2652 }
2653 
2654 void MacroAssembler::get_vm_result(Register oop_result, Register java_thread) {
2655   movptr(oop_result, Address(java_thread, JavaThread::vm_result_offset()));
2656   movptr(Address(java_thread, JavaThread::vm_result_offset()), NULL_WORD);
2657   verify_oop(oop_result, "broken oop in call_VM_base");
2658 }
2659 
2660 void MacroAssembler::get_vm_result_2(Register metadata_result, Register java_thread) {
2661   movptr(metadata_result, Address(java_thread, JavaThread::vm_result_2_offset()));
2662   movptr(Address(java_thread, JavaThread::vm_result_2_offset()), NULL_WORD);
2663 }
2664 
2665 void MacroAssembler::check_and_handle_earlyret(Register java_thread) {
2666 }
2667 
2668 void MacroAssembler::check_and_handle_popframe(Register java_thread) {
2669 }
2670 
2671 void MacroAssembler::cmp32(AddressLiteral src1, int32_t imm) {
2672   if (reachable(src1)) {
2673     cmpl(as_Address(src1), imm);
2674   } else {
2675     lea(rscratch1, src1);
2676     cmpl(Address(rscratch1, 0), imm);
2677   }
2678 }
2679 
2680 void MacroAssembler::cmp32(Register src1, AddressLiteral src2) {
2681   assert(!src2.is_lval(), "use cmpptr");
2682   if (reachable(src2)) {
2683     cmpl(src1, as_Address(src2));
2684   } else {
2685     lea(rscratch1, src2);
2686     cmpl(src1, Address(rscratch1, 0));
2687   }
2688 }
2689 
2690 void MacroAssembler::cmp32(Register src1, int32_t imm) {
2691   Assembler::cmpl(src1, imm);
2692 }
2693 
2694 void MacroAssembler::cmp32(Register src1, Address src2) {
2695   Assembler::cmpl(src1, src2);
2696 }
2697 
2698 void MacroAssembler::cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) {
2699   ucomisd(opr1, opr2);
2700 
2701   Label L;
2702   if (unordered_is_less) {
2703     movl(dst, -1);
2704     jcc(Assembler::parity, L);
2705     jcc(Assembler::below , L);
2706     movl(dst, 0);
2707     jcc(Assembler::equal , L);
2708     increment(dst);
2709   } else { // unordered is greater
2710     movl(dst, 1);
2711     jcc(Assembler::parity, L);
2712     jcc(Assembler::above , L);
2713     movl(dst, 0);
2714     jcc(Assembler::equal , L);
2715     decrementl(dst);
2716   }
2717   bind(L);
2718 }
2719 
2720 void MacroAssembler::cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) {
2721   ucomiss(opr1, opr2);
2722 
2723   Label L;
2724   if (unordered_is_less) {
2725     movl(dst, -1);
2726     jcc(Assembler::parity, L);
2727     jcc(Assembler::below , L);
2728     movl(dst, 0);
2729     jcc(Assembler::equal , L);
2730     increment(dst);
2731   } else { // unordered is greater
2732     movl(dst, 1);
2733     jcc(Assembler::parity, L);
2734     jcc(Assembler::above , L);
2735     movl(dst, 0);
2736     jcc(Assembler::equal , L);
2737     decrementl(dst);
2738   }
2739   bind(L);
2740 }
2741 
2742 
2743 void MacroAssembler::cmp8(AddressLiteral src1, int imm) {
2744   if (reachable(src1)) {
2745     cmpb(as_Address(src1), imm);
2746   } else {
2747     lea(rscratch1, src1);
2748     cmpb(Address(rscratch1, 0), imm);
2749   }
2750 }
2751 
2752 void MacroAssembler::cmpptr(Register src1, AddressLiteral src2) {
2753 #ifdef _LP64
2754   if (src2.is_lval()) {
2755     movptr(rscratch1, src2);
2756     Assembler::cmpq(src1, rscratch1);
2757   } else if (reachable(src2)) {
2758     cmpq(src1, as_Address(src2));
2759   } else {
2760     lea(rscratch1, src2);
2761     Assembler::cmpq(src1, Address(rscratch1, 0));
2762   }
2763 #else
2764   if (src2.is_lval()) {
2765     cmp_literal32(src1, (int32_t) src2.target(), src2.rspec());
2766   } else {
2767     cmpl(src1, as_Address(src2));
2768   }
2769 #endif // _LP64
2770 }
2771 
2772 void MacroAssembler::cmpptr(Address src1, AddressLiteral src2) {
2773   assert(src2.is_lval(), "not a mem-mem compare");
2774 #ifdef _LP64
2775   // moves src2's literal address
2776   movptr(rscratch1, src2);
2777   Assembler::cmpq(src1, rscratch1);
2778 #else
2779   cmp_literal32(src1, (int32_t) src2.target(), src2.rspec());
2780 #endif // _LP64
2781 }
2782 
2783 void MacroAssembler::locked_cmpxchgptr(Register reg, AddressLiteral adr) {
2784   if (reachable(adr)) {
2785     if (os::is_MP())
2786       lock();
2787     cmpxchgptr(reg, as_Address(adr));
2788   } else {
2789     lea(rscratch1, adr);
2790     if (os::is_MP())
2791       lock();
2792     cmpxchgptr(reg, Address(rscratch1, 0));
2793   }
2794 }
2795 
2796 void MacroAssembler::cmpxchgptr(Register reg, Address adr) {
2797   LP64_ONLY(cmpxchgq(reg, adr)) NOT_LP64(cmpxchgl(reg, adr));
2798 }
2799 
2800 void MacroAssembler::comisd(XMMRegister dst, AddressLiteral src) {
2801   if (reachable(src)) {
2802     Assembler::comisd(dst, as_Address(src));
2803   } else {
2804     lea(rscratch1, src);
2805     Assembler::comisd(dst, Address(rscratch1, 0));
2806   }
2807 }
2808 
2809 void MacroAssembler::comiss(XMMRegister dst, AddressLiteral src) {
2810   if (reachable(src)) {
2811     Assembler::comiss(dst, as_Address(src));
2812   } else {
2813     lea(rscratch1, src);
2814     Assembler::comiss(dst, Address(rscratch1, 0));
2815   }
2816 }
2817 
2818 
2819 void MacroAssembler::cond_inc32(Condition cond, AddressLiteral counter_addr) {
2820   Condition negated_cond = negate_condition(cond);
2821   Label L;
2822   jcc(negated_cond, L);
2823   pushf(); // Preserve flags
2824   atomic_incl(counter_addr);
2825   popf();
2826   bind(L);
2827 }
2828 
2829 int MacroAssembler::corrected_idivl(Register reg) {
2830   // Full implementation of Java idiv and irem; checks for
2831   // special case as described in JVM spec., p.243 & p.271.
2832   // The function returns the (pc) offset of the idivl
2833   // instruction - may be needed for implicit exceptions.
2834   //
2835   //         normal case                           special case
2836   //
2837   // input : rax,: dividend                         min_int
2838   //         reg: divisor   (may not be rax,/rdx)   -1
2839   //
2840   // output: rax,: quotient  (= rax, idiv reg)       min_int
2841   //         rdx: remainder (= rax, irem reg)       0
2842   assert(reg != rax && reg != rdx, "reg cannot be rax, or rdx register");
2843   const int min_int = 0x80000000;
2844   Label normal_case, special_case;
2845 
2846   // check for special case
2847   cmpl(rax, min_int);
2848   jcc(Assembler::notEqual, normal_case);
2849   xorl(rdx, rdx); // prepare rdx for possible special case (where remainder = 0)
2850   cmpl(reg, -1);
2851   jcc(Assembler::equal, special_case);
2852 
2853   // handle normal case
2854   bind(normal_case);
2855   cdql();
2856   int idivl_offset = offset();
2857   idivl(reg);
2858 
2859   // normal and special case exit
2860   bind(special_case);
2861 
2862   return idivl_offset;
2863 }
2864 
2865 
2866 
2867 void MacroAssembler::decrementl(Register reg, int value) {
2868   if (value == min_jint) {subl(reg, value) ; return; }
2869   if (value <  0) { incrementl(reg, -value); return; }
2870   if (value == 0) {                        ; return; }
2871   if (value == 1 && UseIncDec) { decl(reg) ; return; }
2872   /* else */      { subl(reg, value)       ; return; }
2873 }
2874 
2875 void MacroAssembler::decrementl(Address dst, int value) {
2876   if (value == min_jint) {subl(dst, value) ; return; }
2877   if (value <  0) { incrementl(dst, -value); return; }
2878   if (value == 0) {                        ; return; }
2879   if (value == 1 && UseIncDec) { decl(dst) ; return; }
2880   /* else */      { subl(dst, value)       ; return; }
2881 }
2882 
2883 void MacroAssembler::division_with_shift (Register reg, int shift_value) {
2884   assert (shift_value > 0, "illegal shift value");
2885   Label _is_positive;
2886   testl (reg, reg);
2887   jcc (Assembler::positive, _is_positive);
2888   int offset = (1 << shift_value) - 1 ;
2889 
2890   if (offset == 1) {
2891     incrementl(reg);
2892   } else {
2893     addl(reg, offset);
2894   }
2895 
2896   bind (_is_positive);
2897   sarl(reg, shift_value);
2898 }
2899 
2900 void MacroAssembler::divsd(XMMRegister dst, AddressLiteral src) {
2901   if (reachable(src)) {
2902     Assembler::divsd(dst, as_Address(src));
2903   } else {
2904     lea(rscratch1, src);
2905     Assembler::divsd(dst, Address(rscratch1, 0));
2906   }
2907 }
2908 
2909 void MacroAssembler::divss(XMMRegister dst, AddressLiteral src) {
2910   if (reachable(src)) {
2911     Assembler::divss(dst, as_Address(src));
2912   } else {
2913     lea(rscratch1, src);
2914     Assembler::divss(dst, Address(rscratch1, 0));
2915   }
2916 }
2917 
2918 // !defined(COMPILER2) is because of stupid core builds
2919 #if !defined(_LP64) || defined(COMPILER1) || !defined(COMPILER2) || INCLUDE_JVMCI
2920 void MacroAssembler::empty_FPU_stack() {
2921   if (VM_Version::supports_mmx()) {
2922     emms();
2923   } else {
2924     for (int i = 8; i-- > 0; ) ffree(i);
2925   }
2926 }
2927 #endif // !LP64 || C1 || !C2 || INCLUDE_JVMCI
2928 
2929 
2930 // Defines obj, preserves var_size_in_bytes
2931 void MacroAssembler::eden_allocate(Register obj,
2932                                    Register var_size_in_bytes,
2933                                    int con_size_in_bytes,
2934                                    Register t1,
2935                                    Label& slow_case) {
2936   assert(obj == rax, "obj must be in rax, for cmpxchg");
2937   assert_different_registers(obj, var_size_in_bytes, t1);
2938   if (!GC::gc()->heap()->supports_inline_contig_alloc()) {
2939     jmp(slow_case);
2940   } else {
2941     Register end = t1;
2942     Label retry;
2943     bind(retry);
2944     ExternalAddress heap_top((address) GC::gc()->heap()->top_addr());
2945     movptr(obj, heap_top);
2946     if (var_size_in_bytes == noreg) {
2947       lea(end, Address(obj, con_size_in_bytes));
2948     } else {
2949       lea(end, Address(obj, var_size_in_bytes, Address::times_1));
2950     }
2951     // if end < obj then we wrapped around => object too long => slow case
2952     cmpptr(end, obj);
2953     jcc(Assembler::below, slow_case);
2954     cmpptr(end, ExternalAddress((address) GC::gc()->heap()->end_addr()));
2955     jcc(Assembler::above, slow_case);
2956     // Compare obj with the top addr, and if still equal, store the new top addr in
2957     // end at the address of the top addr pointer. Sets ZF if was equal, and clears
2958     // it otherwise. Use lock prefix for atomicity on MPs.
2959     locked_cmpxchgptr(end, heap_top);
2960     jcc(Assembler::notEqual, retry);
2961   }
2962 }
2963 
2964 void MacroAssembler::enter() {
2965   push(rbp);
2966   mov(rbp, rsp);
2967 }
2968 
2969 // A 5 byte nop that is safe for patching (see patch_verified_entry)
2970 void MacroAssembler::fat_nop() {
2971   if (UseAddressNop) {
2972     addr_nop_5();
2973   } else {
2974     emit_int8(0x26); // es:
2975     emit_int8(0x2e); // cs:
2976     emit_int8(0x64); // fs:
2977     emit_int8(0x65); // gs:
2978     emit_int8((unsigned char)0x90);
2979   }
2980 }
2981 
2982 void MacroAssembler::fcmp(Register tmp) {
2983   fcmp(tmp, 1, true, true);
2984 }
2985 
2986 void MacroAssembler::fcmp(Register tmp, int index, bool pop_left, bool pop_right) {
2987   assert(!pop_right || pop_left, "usage error");
2988   if (VM_Version::supports_cmov()) {
2989     assert(tmp == noreg, "unneeded temp");
2990     if (pop_left) {
2991       fucomip(index);
2992     } else {
2993       fucomi(index);
2994     }
2995     if (pop_right) {
2996       fpop();
2997     }
2998   } else {
2999     assert(tmp != noreg, "need temp");
3000     if (pop_left) {
3001       if (pop_right) {
3002         fcompp();
3003       } else {
3004         fcomp(index);
3005       }
3006     } else {
3007       fcom(index);
3008     }
3009     // convert FPU condition into eflags condition via rax,
3010     save_rax(tmp);
3011     fwait(); fnstsw_ax();
3012     sahf();
3013     restore_rax(tmp);
3014   }
3015   // condition codes set as follows:
3016   //
3017   // CF (corresponds to C0) if x < y
3018   // PF (corresponds to C2) if unordered
3019   // ZF (corresponds to C3) if x = y
3020 }
3021 
3022 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less) {
3023   fcmp2int(dst, unordered_is_less, 1, true, true);
3024 }
3025 
3026 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right) {
3027   fcmp(VM_Version::supports_cmov() ? noreg : dst, index, pop_left, pop_right);
3028   Label L;
3029   if (unordered_is_less) {
3030     movl(dst, -1);
3031     jcc(Assembler::parity, L);
3032     jcc(Assembler::below , L);
3033     movl(dst, 0);
3034     jcc(Assembler::equal , L);
3035     increment(dst);
3036   } else { // unordered is greater
3037     movl(dst, 1);
3038     jcc(Assembler::parity, L);
3039     jcc(Assembler::above , L);
3040     movl(dst, 0);
3041     jcc(Assembler::equal , L);
3042     decrementl(dst);
3043   }
3044   bind(L);
3045 }
3046 
3047 void MacroAssembler::fld_d(AddressLiteral src) {
3048   fld_d(as_Address(src));
3049 }
3050 
3051 void MacroAssembler::fld_s(AddressLiteral src) {
3052   fld_s(as_Address(src));
3053 }
3054 
3055 void MacroAssembler::fld_x(AddressLiteral src) {
3056   Assembler::fld_x(as_Address(src));
3057 }
3058 
3059 void MacroAssembler::fldcw(AddressLiteral src) {
3060   Assembler::fldcw(as_Address(src));
3061 }
3062 
3063 void MacroAssembler::mulpd(XMMRegister dst, AddressLiteral src) {
3064   if (reachable(src)) {
3065     Assembler::mulpd(dst, as_Address(src));
3066   } else {
3067     lea(rscratch1, src);
3068     Assembler::mulpd(dst, Address(rscratch1, 0));
3069   }
3070 }
3071 
3072 void MacroAssembler::increase_precision() {
3073   subptr(rsp, BytesPerWord);
3074   fnstcw(Address(rsp, 0));
3075   movl(rax, Address(rsp, 0));
3076   orl(rax, 0x300);
3077   push(rax);
3078   fldcw(Address(rsp, 0));
3079   pop(rax);
3080 }
3081 
3082 void MacroAssembler::restore_precision() {
3083   fldcw(Address(rsp, 0));
3084   addptr(rsp, BytesPerWord);
3085 }
3086 
3087 void MacroAssembler::fpop() {
3088   ffree();
3089   fincstp();
3090 }
3091 
3092 void MacroAssembler::load_float(Address src) {
3093   if (UseSSE >= 1) {
3094     movflt(xmm0, src);
3095   } else {
3096     LP64_ONLY(ShouldNotReachHere());
3097     NOT_LP64(fld_s(src));
3098   }
3099 }
3100 
3101 void MacroAssembler::store_float(Address dst) {
3102   if (UseSSE >= 1) {
3103     movflt(dst, xmm0);
3104   } else {
3105     LP64_ONLY(ShouldNotReachHere());
3106     NOT_LP64(fstp_s(dst));
3107   }
3108 }
3109 
3110 void MacroAssembler::load_double(Address src) {
3111   if (UseSSE >= 2) {
3112     movdbl(xmm0, src);
3113   } else {
3114     LP64_ONLY(ShouldNotReachHere());
3115     NOT_LP64(fld_d(src));
3116   }
3117 }
3118 
3119 void MacroAssembler::store_double(Address dst) {
3120   if (UseSSE >= 2) {
3121     movdbl(dst, xmm0);
3122   } else {
3123     LP64_ONLY(ShouldNotReachHere());
3124     NOT_LP64(fstp_d(dst));
3125   }
3126 }
3127 
3128 void MacroAssembler::fremr(Register tmp) {
3129   save_rax(tmp);
3130   { Label L;
3131     bind(L);
3132     fprem();
3133     fwait(); fnstsw_ax();
3134 #ifdef _LP64
3135     testl(rax, 0x400);
3136     jcc(Assembler::notEqual, L);
3137 #else
3138     sahf();
3139     jcc(Assembler::parity, L);
3140 #endif // _LP64
3141   }
3142   restore_rax(tmp);
3143   // Result is in ST0.
3144   // Note: fxch & fpop to get rid of ST1
3145   // (otherwise FPU stack could overflow eventually)
3146   fxch(1);
3147   fpop();
3148 }
3149 
3150 // dst = c = a * b + c
3151 void MacroAssembler::fmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c) {
3152   Assembler::vfmadd231sd(c, a, b);
3153   if (dst != c) {
3154     movdbl(dst, c);
3155   }
3156 }
3157 
3158 // dst = c = a * b + c
3159 void MacroAssembler::fmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c) {
3160   Assembler::vfmadd231ss(c, a, b);
3161   if (dst != c) {
3162     movflt(dst, c);
3163   }
3164 }
3165 
3166 
3167 
3168 
3169 void MacroAssembler::incrementl(AddressLiteral dst) {
3170   if (reachable(dst)) {
3171     incrementl(as_Address(dst));
3172   } else {
3173     lea(rscratch1, dst);
3174     incrementl(Address(rscratch1, 0));
3175   }
3176 }
3177 
3178 void MacroAssembler::incrementl(ArrayAddress dst) {
3179   incrementl(as_Address(dst));
3180 }
3181 
3182 void MacroAssembler::incrementl(Register reg, int value) {
3183   if (value == min_jint) {addl(reg, value) ; return; }
3184   if (value <  0) { decrementl(reg, -value); return; }
3185   if (value == 0) {                        ; return; }
3186   if (value == 1 && UseIncDec) { incl(reg) ; return; }
3187   /* else */      { addl(reg, value)       ; return; }
3188 }
3189 
3190 void MacroAssembler::incrementl(Address dst, int value) {
3191   if (value == min_jint) {addl(dst, value) ; return; }
3192   if (value <  0) { decrementl(dst, -value); return; }
3193   if (value == 0) {                        ; return; }
3194   if (value == 1 && UseIncDec) { incl(dst) ; return; }
3195   /* else */      { addl(dst, value)       ; return; }
3196 }
3197 
3198 void MacroAssembler::jump(AddressLiteral dst) {
3199   if (reachable(dst)) {
3200     jmp_literal(dst.target(), dst.rspec());
3201   } else {
3202     lea(rscratch1, dst);
3203     jmp(rscratch1);
3204   }
3205 }
3206 
3207 void MacroAssembler::jump_cc(Condition cc, AddressLiteral dst) {
3208   if (reachable(dst)) {
3209     InstructionMark im(this);
3210     relocate(dst.reloc());
3211     const int short_size = 2;
3212     const int long_size = 6;
3213     int offs = (intptr_t)dst.target() - ((intptr_t)pc());
3214     if (dst.reloc() == relocInfo::none && is8bit(offs - short_size)) {
3215       // 0111 tttn #8-bit disp
3216       emit_int8(0x70 | cc);
3217       emit_int8((offs - short_size) & 0xFF);
3218     } else {
3219       // 0000 1111 1000 tttn #32-bit disp
3220       emit_int8(0x0F);
3221       emit_int8((unsigned char)(0x80 | cc));
3222       emit_int32(offs - long_size);
3223     }
3224   } else {
3225 #ifdef ASSERT
3226     warning("reversing conditional branch");
3227 #endif /* ASSERT */
3228     Label skip;
3229     jccb(reverse[cc], skip);
3230     lea(rscratch1, dst);
3231     Assembler::jmp(rscratch1);
3232     bind(skip);
3233   }
3234 }
3235 
3236 void MacroAssembler::ldmxcsr(AddressLiteral src) {
3237   if (reachable(src)) {
3238     Assembler::ldmxcsr(as_Address(src));
3239   } else {
3240     lea(rscratch1, src);
3241     Assembler::ldmxcsr(Address(rscratch1, 0));
3242   }
3243 }
3244 
3245 int MacroAssembler::load_signed_byte(Register dst, Address src) {
3246   int off;
3247   if (LP64_ONLY(true ||) VM_Version::is_P6()) {
3248     off = offset();
3249     movsbl(dst, src); // movsxb
3250   } else {
3251     off = load_unsigned_byte(dst, src);
3252     shll(dst, 24);
3253     sarl(dst, 24);
3254   }
3255   return off;
3256 }
3257 
3258 // Note: load_signed_short used to be called load_signed_word.
3259 // Although the 'w' in x86 opcodes refers to the term "word" in the assembler
3260 // manual, which means 16 bits, that usage is found nowhere in HotSpot code.
3261 // The term "word" in HotSpot means a 32- or 64-bit machine word.
3262 int MacroAssembler::load_signed_short(Register dst, Address src) {
3263   int off;
3264   if (LP64_ONLY(true ||) VM_Version::is_P6()) {
3265     // This is dubious to me since it seems safe to do a signed 16 => 64 bit
3266     // version but this is what 64bit has always done. This seems to imply
3267     // that users are only using 32bits worth.
3268     off = offset();
3269     movswl(dst, src); // movsxw
3270   } else {
3271     off = load_unsigned_short(dst, src);
3272     shll(dst, 16);
3273     sarl(dst, 16);
3274   }
3275   return off;
3276 }
3277 
3278 int MacroAssembler::load_unsigned_byte(Register dst, Address src) {
3279   // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16,
3280   // and "3.9 Partial Register Penalties", p. 22).
3281   int off;
3282   if (LP64_ONLY(true || ) VM_Version::is_P6() || src.uses(dst)) {
3283     off = offset();
3284     movzbl(dst, src); // movzxb
3285   } else {
3286     xorl(dst, dst);
3287     off = offset();
3288     movb(dst, src);
3289   }
3290   return off;
3291 }
3292 
3293 // Note: load_unsigned_short used to be called load_unsigned_word.
3294 int MacroAssembler::load_unsigned_short(Register dst, Address src) {
3295   // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16,
3296   // and "3.9 Partial Register Penalties", p. 22).
3297   int off;
3298   if (LP64_ONLY(true ||) VM_Version::is_P6() || src.uses(dst)) {
3299     off = offset();
3300     movzwl(dst, src); // movzxw
3301   } else {
3302     xorl(dst, dst);
3303     off = offset();
3304     movw(dst, src);
3305   }
3306   return off;
3307 }
3308 
3309 void MacroAssembler::load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2) {
3310   switch (size_in_bytes) {
3311 #ifndef _LP64
3312   case  8:
3313     assert(dst2 != noreg, "second dest register required");
3314     movl(dst,  src);
3315     movl(dst2, src.plus_disp(BytesPerInt));
3316     break;
3317 #else
3318   case  8:  movq(dst, src); break;
3319 #endif
3320   case  4:  movl(dst, src); break;
3321   case  2:  is_signed ? load_signed_short(dst, src) : load_unsigned_short(dst, src); break;
3322   case  1:  is_signed ? load_signed_byte( dst, src) : load_unsigned_byte( dst, src); break;
3323   default:  ShouldNotReachHere();
3324   }
3325 }
3326 
3327 void MacroAssembler::store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2) {
3328   switch (size_in_bytes) {
3329 #ifndef _LP64
3330   case  8:
3331     assert(src2 != noreg, "second source register required");
3332     movl(dst,                        src);
3333     movl(dst.plus_disp(BytesPerInt), src2);
3334     break;
3335 #else
3336   case  8:  movq(dst, src); break;
3337 #endif
3338   case  4:  movl(dst, src); break;
3339   case  2:  movw(dst, src); break;
3340   case  1:  movb(dst, src); break;
3341   default:  ShouldNotReachHere();
3342   }
3343 }
3344 
3345 void MacroAssembler::mov32(AddressLiteral dst, Register src) {
3346   if (reachable(dst)) {
3347     movl(as_Address(dst), src);
3348   } else {
3349     lea(rscratch1, dst);
3350     movl(Address(rscratch1, 0), src);
3351   }
3352 }
3353 
3354 void MacroAssembler::mov32(Register dst, AddressLiteral src) {
3355   if (reachable(src)) {
3356     movl(dst, as_Address(src));
3357   } else {
3358     lea(rscratch1, src);
3359     movl(dst, Address(rscratch1, 0));
3360   }
3361 }
3362 
3363 // C++ bool manipulation
3364 
3365 void MacroAssembler::movbool(Register dst, Address src) {
3366   if(sizeof(bool) == 1)
3367     movb(dst, src);
3368   else if(sizeof(bool) == 2)
3369     movw(dst, src);
3370   else if(sizeof(bool) == 4)
3371     movl(dst, src);
3372   else
3373     // unsupported
3374     ShouldNotReachHere();
3375 }
3376 
3377 void MacroAssembler::movbool(Address dst, bool boolconst) {
3378   if(sizeof(bool) == 1)
3379     movb(dst, (int) boolconst);
3380   else if(sizeof(bool) == 2)
3381     movw(dst, (int) boolconst);
3382   else if(sizeof(bool) == 4)
3383     movl(dst, (int) boolconst);
3384   else
3385     // unsupported
3386     ShouldNotReachHere();
3387 }
3388 
3389 void MacroAssembler::movbool(Address dst, Register src) {
3390   if(sizeof(bool) == 1)
3391     movb(dst, src);
3392   else if(sizeof(bool) == 2)
3393     movw(dst, src);
3394   else if(sizeof(bool) == 4)
3395     movl(dst, src);
3396   else
3397     // unsupported
3398     ShouldNotReachHere();
3399 }
3400 
3401 void MacroAssembler::movbyte(ArrayAddress dst, int src) {
3402   movb(as_Address(dst), src);
3403 }
3404 
3405 void MacroAssembler::movdl(XMMRegister dst, AddressLiteral src) {
3406   if (reachable(src)) {
3407     movdl(dst, as_Address(src));
3408   } else {
3409     lea(rscratch1, src);
3410     movdl(dst, Address(rscratch1, 0));
3411   }
3412 }
3413 
3414 void MacroAssembler::movq(XMMRegister dst, AddressLiteral src) {
3415   if (reachable(src)) {
3416     movq(dst, as_Address(src));
3417   } else {
3418     lea(rscratch1, src);
3419     movq(dst, Address(rscratch1, 0));
3420   }
3421 }
3422 
3423 void MacroAssembler::setvectmask(Register dst, Register src) {
3424   Assembler::movl(dst, 1);
3425   Assembler::shlxl(dst, dst, src);
3426   Assembler::decl(dst);
3427   Assembler::kmovdl(k1, dst);
3428   Assembler::movl(dst, src);
3429 }
3430 
3431 void MacroAssembler::restorevectmask() {
3432   Assembler::knotwl(k1, k0);
3433 }
3434 
3435 void MacroAssembler::movdbl(XMMRegister dst, AddressLiteral src) {
3436   if (reachable(src)) {
3437     if (UseXmmLoadAndClearUpper) {
3438       movsd (dst, as_Address(src));
3439     } else {
3440       movlpd(dst, as_Address(src));
3441     }
3442   } else {
3443     lea(rscratch1, src);
3444     if (UseXmmLoadAndClearUpper) {
3445       movsd (dst, Address(rscratch1, 0));
3446     } else {
3447       movlpd(dst, Address(rscratch1, 0));
3448     }
3449   }
3450 }
3451 
3452 void MacroAssembler::movflt(XMMRegister dst, AddressLiteral src) {
3453   if (reachable(src)) {
3454     movss(dst, as_Address(src));
3455   } else {
3456     lea(rscratch1, src);
3457     movss(dst, Address(rscratch1, 0));
3458   }
3459 }
3460 
3461 void MacroAssembler::movptr(Register dst, Register src) {
3462   LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
3463 }
3464 
3465 void MacroAssembler::movptr(Register dst, Address src) {
3466   LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
3467 }
3468 
3469 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
3470 void MacroAssembler::movptr(Register dst, intptr_t src) {
3471   LP64_ONLY(mov64(dst, src)) NOT_LP64(movl(dst, src));
3472 }
3473 
3474 void MacroAssembler::movptr(Address dst, Register src) {
3475   LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
3476 }
3477 
3478 void MacroAssembler::movdqu(Address dst, XMMRegister src) {
3479   if (UseAVX > 2 && !VM_Version::supports_avx512vl() && (src->encoding() > 15)) {
3480     Assembler::vextractf32x4(dst, src, 0);
3481   } else {
3482     Assembler::movdqu(dst, src);
3483   }
3484 }
3485 
3486 void MacroAssembler::movdqu(XMMRegister dst, Address src) {
3487   if (UseAVX > 2 && !VM_Version::supports_avx512vl() && (dst->encoding() > 15)) {
3488     Assembler::vinsertf32x4(dst, dst, src, 0);
3489   } else {
3490     Assembler::movdqu(dst, src);
3491   }
3492 }
3493 
3494 void MacroAssembler::movdqu(XMMRegister dst, XMMRegister src) {
3495   if (UseAVX > 2 && !VM_Version::supports_avx512vl()) {
3496     Assembler::evmovdqul(dst, src, Assembler::AVX_512bit);
3497   } else {
3498     Assembler::movdqu(dst, src);
3499   }
3500 }
3501 
3502 void MacroAssembler::movdqu(XMMRegister dst, AddressLiteral src, Register scratchReg) {
3503   if (reachable(src)) {
3504     movdqu(dst, as_Address(src));
3505   } else {
3506     lea(scratchReg, src);
3507     movdqu(dst, Address(scratchReg, 0));
3508   }
3509 }
3510 
3511 void MacroAssembler::vmovdqu(Address dst, XMMRegister src) {
3512   if (UseAVX > 2 && !VM_Version::supports_avx512vl() && (src->encoding() > 15)) {
3513     vextractf64x4_low(dst, src);
3514   } else {
3515     Assembler::vmovdqu(dst, src);
3516   }
3517 }
3518 
3519 void MacroAssembler::vmovdqu(XMMRegister dst, Address src) {
3520   if (UseAVX > 2 && !VM_Version::supports_avx512vl() && (dst->encoding() > 15)) {
3521     vinsertf64x4_low(dst, src);
3522   } else {
3523     Assembler::vmovdqu(dst, src);
3524   }
3525 }
3526 
3527 void MacroAssembler::vmovdqu(XMMRegister dst, XMMRegister src) {
3528   if (UseAVX > 2 && !VM_Version::supports_avx512vl()) {
3529     Assembler::evmovdqul(dst, src, Assembler::AVX_512bit);
3530   }
3531   else {
3532     Assembler::vmovdqu(dst, src);
3533   }
3534 }
3535 
3536 void MacroAssembler::vmovdqu(XMMRegister dst, AddressLiteral src) {
3537   if (reachable(src)) {
3538     vmovdqu(dst, as_Address(src));
3539   }
3540   else {
3541     lea(rscratch1, src);
3542     vmovdqu(dst, Address(rscratch1, 0));
3543   }
3544 }
3545 
3546 void MacroAssembler::movdqa(XMMRegister dst, AddressLiteral src) {
3547   if (reachable(src)) {
3548     Assembler::movdqa(dst, as_Address(src));
3549   } else {
3550     lea(rscratch1, src);
3551     Assembler::movdqa(dst, Address(rscratch1, 0));
3552   }
3553 }
3554 
3555 void MacroAssembler::movsd(XMMRegister dst, AddressLiteral src) {
3556   if (reachable(src)) {
3557     Assembler::movsd(dst, as_Address(src));
3558   } else {
3559     lea(rscratch1, src);
3560     Assembler::movsd(dst, Address(rscratch1, 0));
3561   }
3562 }
3563 
3564 void MacroAssembler::movss(XMMRegister dst, AddressLiteral src) {
3565   if (reachable(src)) {
3566     Assembler::movss(dst, as_Address(src));
3567   } else {
3568     lea(rscratch1, src);
3569     Assembler::movss(dst, Address(rscratch1, 0));
3570   }
3571 }
3572 
3573 void MacroAssembler::mulsd(XMMRegister dst, AddressLiteral src) {
3574   if (reachable(src)) {
3575     Assembler::mulsd(dst, as_Address(src));
3576   } else {
3577     lea(rscratch1, src);
3578     Assembler::mulsd(dst, Address(rscratch1, 0));
3579   }
3580 }
3581 
3582 void MacroAssembler::mulss(XMMRegister dst, AddressLiteral src) {
3583   if (reachable(src)) {
3584     Assembler::mulss(dst, as_Address(src));
3585   } else {
3586     lea(rscratch1, src);
3587     Assembler::mulss(dst, Address(rscratch1, 0));
3588   }
3589 }
3590 
3591 void MacroAssembler::null_check(Register reg, int offset) {
3592   if (needs_explicit_null_check(offset)) {
3593     // provoke OS NULL exception if reg = NULL by
3594     // accessing M[reg] w/o changing any (non-CC) registers
3595     // NOTE: cmpl is plenty here to provoke a segv
3596     cmpptr(rax, Address(reg, 0));
3597     // Note: should probably use testl(rax, Address(reg, 0));
3598     //       may be shorter code (however, this version of
3599     //       testl needs to be implemented first)
3600   } else {
3601     // nothing to do, (later) access of M[reg + offset]
3602     // will provoke OS NULL exception if reg = NULL
3603   }
3604 }
3605 
3606 void MacroAssembler::os_breakpoint() {
3607   // instead of directly emitting a breakpoint, call os:breakpoint for better debugability
3608   // (e.g., MSVC can't call ps() otherwise)
3609   call(RuntimeAddress(CAST_FROM_FN_PTR(address, os::breakpoint)));
3610 }
3611 
3612 #ifdef _LP64
3613 #define XSTATE_BV 0x200
3614 #endif
3615 
3616 void MacroAssembler::pop_CPU_state() {
3617   pop_FPU_state();
3618   pop_IU_state();
3619 }
3620 
3621 void MacroAssembler::pop_FPU_state() {
3622 #ifndef _LP64
3623   frstor(Address(rsp, 0));
3624 #else
3625   fxrstor(Address(rsp, 0));
3626 #endif
3627   addptr(rsp, FPUStateSizeInWords * wordSize);
3628 }
3629 
3630 void MacroAssembler::pop_IU_state() {
3631   popa();
3632   LP64_ONLY(addq(rsp, 8));
3633   popf();
3634 }
3635 
3636 // Save Integer and Float state
3637 // Warning: Stack must be 16 byte aligned (64bit)
3638 void MacroAssembler::push_CPU_state() {
3639   push_IU_state();
3640   push_FPU_state();
3641 }
3642 
3643 void MacroAssembler::push_FPU_state() {
3644   subptr(rsp, FPUStateSizeInWords * wordSize);
3645 #ifndef _LP64
3646   fnsave(Address(rsp, 0));
3647   fwait();
3648 #else
3649   fxsave(Address(rsp, 0));
3650 #endif // LP64
3651 }
3652 
3653 void MacroAssembler::push_IU_state() {
3654   // Push flags first because pusha kills them
3655   pushf();
3656   // Make sure rsp stays 16-byte aligned
3657   LP64_ONLY(subq(rsp, 8));
3658   pusha();
3659 }
3660 
3661 void MacroAssembler::reset_last_Java_frame(Register java_thread, bool clear_fp) { // determine java_thread register
3662   if (!java_thread->is_valid()) {
3663     java_thread = rdi;
3664     get_thread(java_thread);
3665   }
3666   // we must set sp to zero to clear frame
3667   movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), NULL_WORD);
3668   if (clear_fp) {
3669     movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), NULL_WORD);
3670   }
3671 
3672   // Always clear the pc because it could have been set by make_walkable()
3673   movptr(Address(java_thread, JavaThread::last_Java_pc_offset()), NULL_WORD);
3674 
3675 }
3676 
3677 void MacroAssembler::restore_rax(Register tmp) {
3678   if (tmp == noreg) pop(rax);
3679   else if (tmp != rax) mov(rax, tmp);
3680 }
3681 
3682 void MacroAssembler::round_to(Register reg, int modulus) {
3683   addptr(reg, modulus - 1);
3684   andptr(reg, -modulus);
3685 }
3686 
3687 void MacroAssembler::save_rax(Register tmp) {
3688   if (tmp == noreg) push(rax);
3689   else if (tmp != rax) mov(tmp, rax);
3690 }
3691 
3692 // Write serialization page so VM thread can do a pseudo remote membar.
3693 // We use the current thread pointer to calculate a thread specific
3694 // offset to write to within the page. This minimizes bus traffic
3695 // due to cache line collision.
3696 void MacroAssembler::serialize_memory(Register thread, Register tmp) {
3697   movl(tmp, thread);
3698   shrl(tmp, os::get_serialize_page_shift_count());
3699   andl(tmp, (os::vm_page_size() - sizeof(int)));
3700 
3701   Address index(noreg, tmp, Address::times_1);
3702   ExternalAddress page(os::get_memory_serialize_page());
3703 
3704   // Size of store must match masking code above
3705   movl(as_Address(ArrayAddress(page, index)), tmp);
3706 }
3707 
3708 // Calls to C land
3709 //
3710 // When entering C land, the rbp, & rsp of the last Java frame have to be recorded
3711 // in the (thread-local) JavaThread object. When leaving C land, the last Java fp
3712 // has to be reset to 0. This is required to allow proper stack traversal.
3713 void MacroAssembler::set_last_Java_frame(Register java_thread,
3714                                          Register last_java_sp,
3715                                          Register last_java_fp,
3716                                          address  last_java_pc) {
3717   // determine java_thread register
3718   if (!java_thread->is_valid()) {
3719     java_thread = rdi;
3720     get_thread(java_thread);
3721   }
3722   // determine last_java_sp register
3723   if (!last_java_sp->is_valid()) {
3724     last_java_sp = rsp;
3725   }
3726 
3727   // last_java_fp is optional
3728 
3729   if (last_java_fp->is_valid()) {
3730     movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), last_java_fp);
3731   }
3732 
3733   // last_java_pc is optional
3734 
3735   if (last_java_pc != NULL) {
3736     lea(Address(java_thread,
3737                  JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset()),
3738         InternalAddress(last_java_pc));
3739 
3740   }
3741   movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), last_java_sp);
3742 }
3743 
3744 void MacroAssembler::shlptr(Register dst, int imm8) {
3745   LP64_ONLY(shlq(dst, imm8)) NOT_LP64(shll(dst, imm8));
3746 }
3747 
3748 void MacroAssembler::shrptr(Register dst, int imm8) {
3749   LP64_ONLY(shrq(dst, imm8)) NOT_LP64(shrl(dst, imm8));
3750 }
3751 
3752 void MacroAssembler::sign_extend_byte(Register reg) {
3753   if (LP64_ONLY(true ||) (VM_Version::is_P6() && reg->has_byte_register())) {
3754     movsbl(reg, reg); // movsxb
3755   } else {
3756     shll(reg, 24);
3757     sarl(reg, 24);
3758   }
3759 }
3760 
3761 void MacroAssembler::sign_extend_short(Register reg) {
3762   if (LP64_ONLY(true ||) VM_Version::is_P6()) {
3763     movswl(reg, reg); // movsxw
3764   } else {
3765     shll(reg, 16);
3766     sarl(reg, 16);
3767   }
3768 }
3769 
3770 void MacroAssembler::testl(Register dst, AddressLiteral src) {
3771   assert(reachable(src), "Address should be reachable");
3772   testl(dst, as_Address(src));
3773 }
3774 
3775 void MacroAssembler::pcmpeqb(XMMRegister dst, XMMRegister src) {
3776   int dst_enc = dst->encoding();
3777   int src_enc = src->encoding();
3778   if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
3779     Assembler::pcmpeqb(dst, src);
3780   } else if ((dst_enc < 16) && (src_enc < 16)) {
3781     Assembler::pcmpeqb(dst, src);
3782   } else if (src_enc < 16) {
3783     subptr(rsp, 64);
3784     evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3785     evmovdqul(xmm0, dst, Assembler::AVX_512bit);
3786     Assembler::pcmpeqb(xmm0, src);
3787     movdqu(dst, xmm0);
3788     evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3789     addptr(rsp, 64);
3790   } else if (dst_enc < 16) {
3791     subptr(rsp, 64);
3792     evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3793     evmovdqul(xmm0, src, Assembler::AVX_512bit);
3794     Assembler::pcmpeqb(dst, xmm0);
3795     evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3796     addptr(rsp, 64);
3797   } else {
3798     subptr(rsp, 64);
3799     evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3800     subptr(rsp, 64);
3801     evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
3802     movdqu(xmm0, src);
3803     movdqu(xmm1, dst);
3804     Assembler::pcmpeqb(xmm1, xmm0);
3805     movdqu(dst, xmm1);
3806     evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
3807     addptr(rsp, 64);
3808     evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3809     addptr(rsp, 64);
3810   }
3811 }
3812 
3813 void MacroAssembler::pcmpeqw(XMMRegister dst, XMMRegister src) {
3814   int dst_enc = dst->encoding();
3815   int src_enc = src->encoding();
3816   if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
3817     Assembler::pcmpeqw(dst, src);
3818   } else if ((dst_enc < 16) && (src_enc < 16)) {
3819     Assembler::pcmpeqw(dst, src);
3820   } else if (src_enc < 16) {
3821     subptr(rsp, 64);
3822     evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3823     evmovdqul(xmm0, dst, Assembler::AVX_512bit);
3824     Assembler::pcmpeqw(xmm0, src);
3825     movdqu(dst, xmm0);
3826     evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3827     addptr(rsp, 64);
3828   } else if (dst_enc < 16) {
3829     subptr(rsp, 64);
3830     evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3831     evmovdqul(xmm0, src, Assembler::AVX_512bit);
3832     Assembler::pcmpeqw(dst, xmm0);
3833     evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3834     addptr(rsp, 64);
3835   } else {
3836     subptr(rsp, 64);
3837     evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3838     subptr(rsp, 64);
3839     evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
3840     movdqu(xmm0, src);
3841     movdqu(xmm1, dst);
3842     Assembler::pcmpeqw(xmm1, xmm0);
3843     movdqu(dst, xmm1);
3844     evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
3845     addptr(rsp, 64);
3846     evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3847     addptr(rsp, 64);
3848   }
3849 }
3850 
3851 void MacroAssembler::pcmpestri(XMMRegister dst, Address src, int imm8) {
3852   int dst_enc = dst->encoding();
3853   if (dst_enc < 16) {
3854     Assembler::pcmpestri(dst, src, imm8);
3855   } else {
3856     subptr(rsp, 64);
3857     evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3858     evmovdqul(xmm0, dst, Assembler::AVX_512bit);
3859     Assembler::pcmpestri(xmm0, src, imm8);
3860     movdqu(dst, xmm0);
3861     evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3862     addptr(rsp, 64);
3863   }
3864 }
3865 
3866 void MacroAssembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) {
3867   int dst_enc = dst->encoding();
3868   int src_enc = src->encoding();
3869   if ((dst_enc < 16) && (src_enc < 16)) {
3870     Assembler::pcmpestri(dst, src, imm8);
3871   } else if (src_enc < 16) {
3872     subptr(rsp, 64);
3873     evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3874     evmovdqul(xmm0, dst, Assembler::AVX_512bit);
3875     Assembler::pcmpestri(xmm0, src, imm8);
3876     movdqu(dst, xmm0);
3877     evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3878     addptr(rsp, 64);
3879   } else if (dst_enc < 16) {
3880     subptr(rsp, 64);
3881     evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3882     evmovdqul(xmm0, src, Assembler::AVX_512bit);
3883     Assembler::pcmpestri(dst, xmm0, imm8);
3884     evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3885     addptr(rsp, 64);
3886   } else {
3887     subptr(rsp, 64);
3888     evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3889     subptr(rsp, 64);
3890     evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
3891     movdqu(xmm0, src);
3892     movdqu(xmm1, dst);
3893     Assembler::pcmpestri(xmm1, xmm0, imm8);
3894     movdqu(dst, xmm1);
3895     evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
3896     addptr(rsp, 64);
3897     evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3898     addptr(rsp, 64);
3899   }
3900 }
3901 
3902 void MacroAssembler::pmovzxbw(XMMRegister dst, XMMRegister src) {
3903   int dst_enc = dst->encoding();
3904   int src_enc = src->encoding();
3905   if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
3906     Assembler::pmovzxbw(dst, src);
3907   } else if ((dst_enc < 16) && (src_enc < 16)) {
3908     Assembler::pmovzxbw(dst, src);
3909   } else if (src_enc < 16) {
3910     subptr(rsp, 64);
3911     evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3912     evmovdqul(xmm0, dst, Assembler::AVX_512bit);
3913     Assembler::pmovzxbw(xmm0, src);
3914     movdqu(dst, xmm0);
3915     evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3916     addptr(rsp, 64);
3917   } else if (dst_enc < 16) {
3918     subptr(rsp, 64);
3919     evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3920     evmovdqul(xmm0, src, Assembler::AVX_512bit);
3921     Assembler::pmovzxbw(dst, xmm0);
3922     evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3923     addptr(rsp, 64);
3924   } else {
3925     subptr(rsp, 64);
3926     evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3927     subptr(rsp, 64);
3928     evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
3929     movdqu(xmm0, src);
3930     movdqu(xmm1, dst);
3931     Assembler::pmovzxbw(xmm1, xmm0);
3932     movdqu(dst, xmm1);
3933     evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
3934     addptr(rsp, 64);
3935     evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3936     addptr(rsp, 64);
3937   }
3938 }
3939 
3940 void MacroAssembler::pmovzxbw(XMMRegister dst, Address src) {
3941   int dst_enc = dst->encoding();
3942   if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
3943     Assembler::pmovzxbw(dst, src);
3944   } else if (dst_enc < 16) {
3945     Assembler::pmovzxbw(dst, src);
3946   } else {
3947     subptr(rsp, 64);
3948     evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3949     evmovdqul(xmm0, dst, Assembler::AVX_512bit);
3950     Assembler::pmovzxbw(xmm0, src);
3951     movdqu(dst, xmm0);
3952     evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3953     addptr(rsp, 64);
3954   }
3955 }
3956 
3957 void MacroAssembler::pmovmskb(Register dst, XMMRegister src) {
3958   int src_enc = src->encoding();
3959   if (src_enc < 16) {
3960     Assembler::pmovmskb(dst, src);
3961   } else {
3962     subptr(rsp, 64);
3963     evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3964     evmovdqul(xmm0, src, Assembler::AVX_512bit);
3965     Assembler::pmovmskb(dst, xmm0);
3966     evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3967     addptr(rsp, 64);
3968   }
3969 }
3970 
3971 void MacroAssembler::ptest(XMMRegister dst, XMMRegister src) {
3972   int dst_enc = dst->encoding();
3973   int src_enc = src->encoding();
3974   if ((dst_enc < 16) && (src_enc < 16)) {
3975     Assembler::ptest(dst, src);
3976   } else if (src_enc < 16) {
3977     subptr(rsp, 64);
3978     evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3979     evmovdqul(xmm0, dst, Assembler::AVX_512bit);
3980     Assembler::ptest(xmm0, src);
3981     evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3982     addptr(rsp, 64);
3983   } else if (dst_enc < 16) {
3984     subptr(rsp, 64);
3985     evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3986     evmovdqul(xmm0, src, Assembler::AVX_512bit);
3987     Assembler::ptest(dst, xmm0);
3988     evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3989     addptr(rsp, 64);
3990   } else {
3991     subptr(rsp, 64);
3992     evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3993     subptr(rsp, 64);
3994     evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
3995     movdqu(xmm0, src);
3996     movdqu(xmm1, dst);
3997     Assembler::ptest(xmm1, xmm0);
3998     evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
3999     addptr(rsp, 64);
4000     evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4001     addptr(rsp, 64);
4002   }
4003 }
4004 
4005 void MacroAssembler::sqrtsd(XMMRegister dst, AddressLiteral src) {
4006   if (reachable(src)) {
4007     Assembler::sqrtsd(dst, as_Address(src));
4008   } else {
4009     lea(rscratch1, src);
4010     Assembler::sqrtsd(dst, Address(rscratch1, 0));
4011   }
4012 }
4013 
4014 void MacroAssembler::sqrtss(XMMRegister dst, AddressLiteral src) {
4015   if (reachable(src)) {
4016     Assembler::sqrtss(dst, as_Address(src));
4017   } else {
4018     lea(rscratch1, src);
4019     Assembler::sqrtss(dst, Address(rscratch1, 0));
4020   }
4021 }
4022 
4023 void MacroAssembler::subsd(XMMRegister dst, AddressLiteral src) {
4024   if (reachable(src)) {
4025     Assembler::subsd(dst, as_Address(src));
4026   } else {
4027     lea(rscratch1, src);
4028     Assembler::subsd(dst, Address(rscratch1, 0));
4029   }
4030 }
4031 
4032 void MacroAssembler::subss(XMMRegister dst, AddressLiteral src) {
4033   if (reachable(src)) {
4034     Assembler::subss(dst, as_Address(src));
4035   } else {
4036     lea(rscratch1, src);
4037     Assembler::subss(dst, Address(rscratch1, 0));
4038   }
4039 }
4040 
4041 void MacroAssembler::ucomisd(XMMRegister dst, AddressLiteral src) {
4042   if (reachable(src)) {
4043     Assembler::ucomisd(dst, as_Address(src));
4044   } else {
4045     lea(rscratch1, src);
4046     Assembler::ucomisd(dst, Address(rscratch1, 0));
4047   }
4048 }
4049 
4050 void MacroAssembler::ucomiss(XMMRegister dst, AddressLiteral src) {
4051   if (reachable(src)) {
4052     Assembler::ucomiss(dst, as_Address(src));
4053   } else {
4054     lea(rscratch1, src);
4055     Assembler::ucomiss(dst, Address(rscratch1, 0));
4056   }
4057 }
4058 
4059 void MacroAssembler::xorpd(XMMRegister dst, AddressLiteral src) {
4060   // Used in sign-bit flipping with aligned address.
4061   assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
4062   if (reachable(src)) {
4063     Assembler::xorpd(dst, as_Address(src));
4064   } else {
4065     lea(rscratch1, src);
4066     Assembler::xorpd(dst, Address(rscratch1, 0));
4067   }
4068 }
4069 
4070 void MacroAssembler::xorpd(XMMRegister dst, XMMRegister src) {
4071   if (UseAVX > 2 && !VM_Version::supports_avx512dq() && (dst->encoding() == src->encoding())) {
4072     Assembler::vpxor(dst, dst, src, Assembler::AVX_512bit);
4073   }
4074   else {
4075     Assembler::xorpd(dst, src);
4076   }
4077 }
4078 
4079 void MacroAssembler::xorps(XMMRegister dst, XMMRegister src) {
4080   if (UseAVX > 2 && !VM_Version::supports_avx512dq() && (dst->encoding() == src->encoding())) {
4081     Assembler::vpxor(dst, dst, src, Assembler::AVX_512bit);
4082   } else {
4083     Assembler::xorps(dst, src);
4084   }
4085 }
4086 
4087 void MacroAssembler::xorps(XMMRegister dst, AddressLiteral src) {
4088   // Used in sign-bit flipping with aligned address.
4089   assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
4090   if (reachable(src)) {
4091     Assembler::xorps(dst, as_Address(src));
4092   } else {
4093     lea(rscratch1, src);
4094     Assembler::xorps(dst, Address(rscratch1, 0));
4095   }
4096 }
4097 
4098 void MacroAssembler::pshufb(XMMRegister dst, AddressLiteral src) {
4099   // Used in sign-bit flipping with aligned address.
4100   bool aligned_adr = (((intptr_t)src.target() & 15) == 0);
4101   assert((UseAVX > 0) || aligned_adr, "SSE mode requires address alignment 16 bytes");
4102   if (reachable(src)) {
4103     Assembler::pshufb(dst, as_Address(src));
4104   } else {
4105     lea(rscratch1, src);
4106     Assembler::pshufb(dst, Address(rscratch1, 0));
4107   }
4108 }
4109 
4110 // AVX 3-operands instructions
4111 
4112 void MacroAssembler::vaddsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
4113   if (reachable(src)) {
4114     vaddsd(dst, nds, as_Address(src));
4115   } else {
4116     lea(rscratch1, src);
4117     vaddsd(dst, nds, Address(rscratch1, 0));
4118   }
4119 }
4120 
4121 void MacroAssembler::vaddss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
4122   if (reachable(src)) {
4123     vaddss(dst, nds, as_Address(src));
4124   } else {
4125     lea(rscratch1, src);
4126     vaddss(dst, nds, Address(rscratch1, 0));
4127   }
4128 }
4129 
4130 void MacroAssembler::vabsss(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len) {
4131   int dst_enc = dst->encoding();
4132   int nds_enc = nds->encoding();
4133   int src_enc = src->encoding();
4134   if ((dst_enc < 16) && (nds_enc < 16)) {
4135     vandps(dst, nds, negate_field, vector_len);
4136   } else if ((src_enc < 16) && (dst_enc < 16)) {
4137     movss(src, nds);
4138     vandps(dst, src, negate_field, vector_len);
4139   } else if (src_enc < 16) {
4140     movss(src, nds);
4141     vandps(src, src, negate_field, vector_len);
4142     movss(dst, src);
4143   } else if (dst_enc < 16) {
4144     movdqu(src, xmm0);
4145     movss(xmm0, nds);
4146     vandps(dst, xmm0, negate_field, vector_len);
4147     movdqu(xmm0, src);
4148   } else if (nds_enc < 16) {
4149     movdqu(src, xmm0);
4150     vandps(xmm0, nds, negate_field, vector_len);
4151     movss(dst, xmm0);
4152     movdqu(xmm0, src);
4153   } else {
4154     movdqu(src, xmm0);
4155     movss(xmm0, nds);
4156     vandps(xmm0, xmm0, negate_field, vector_len);
4157     movss(dst, xmm0);
4158     movdqu(xmm0, src);
4159   }
4160 }
4161 
4162 void MacroAssembler::vabssd(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len) {
4163   int dst_enc = dst->encoding();
4164   int nds_enc = nds->encoding();
4165   int src_enc = src->encoding();
4166   if ((dst_enc < 16) && (nds_enc < 16)) {
4167     vandpd(dst, nds, negate_field, vector_len);
4168   } else if ((src_enc < 16) && (dst_enc < 16)) {
4169     movsd(src, nds);
4170     vandpd(dst, src, negate_field, vector_len);
4171   } else if (src_enc < 16) {
4172     movsd(src, nds);
4173     vandpd(src, src, negate_field, vector_len);
4174     movsd(dst, src);
4175   } else if (dst_enc < 16) {
4176     movdqu(src, xmm0);
4177     movsd(xmm0, nds);
4178     vandpd(dst, xmm0, negate_field, vector_len);
4179     movdqu(xmm0, src);
4180   } else if (nds_enc < 16) {
4181     movdqu(src, xmm0);
4182     vandpd(xmm0, nds, negate_field, vector_len);
4183     movsd(dst, xmm0);
4184     movdqu(xmm0, src);
4185   } else {
4186     movdqu(src, xmm0);
4187     movsd(xmm0, nds);
4188     vandpd(xmm0, xmm0, negate_field, vector_len);
4189     movsd(dst, xmm0);
4190     movdqu(xmm0, src);
4191   }
4192 }
4193 
4194 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4195   int dst_enc = dst->encoding();
4196   int nds_enc = nds->encoding();
4197   int src_enc = src->encoding();
4198   if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4199     Assembler::vpaddb(dst, nds, src, vector_len);
4200   } else if ((dst_enc < 16) && (src_enc < 16)) {
4201     Assembler::vpaddb(dst, dst, src, vector_len);
4202   } else if ((dst_enc < 16) && (nds_enc < 16)) {
4203     // use nds as scratch for src
4204     evmovdqul(nds, src, Assembler::AVX_512bit);
4205     Assembler::vpaddb(dst, dst, nds, vector_len);
4206   } else if ((src_enc < 16) && (nds_enc < 16)) {
4207     // use nds as scratch for dst
4208     evmovdqul(nds, dst, Assembler::AVX_512bit);
4209     Assembler::vpaddb(nds, nds, src, vector_len);
4210     evmovdqul(dst, nds, Assembler::AVX_512bit);
4211   } else if (dst_enc < 16) {
4212     // use nds as scatch for xmm0 to hold src
4213     evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4214     evmovdqul(xmm0, src, Assembler::AVX_512bit);
4215     Assembler::vpaddb(dst, dst, xmm0, vector_len);
4216     evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4217   } else {
4218     // worse case scenario, all regs are in the upper bank
4219     subptr(rsp, 64);
4220     evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4221     evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4222     evmovdqul(xmm1, src, Assembler::AVX_512bit);
4223     evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4224     Assembler::vpaddb(xmm0, xmm0, xmm1, vector_len);
4225     evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4226     evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4227     evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4228     addptr(rsp, 64);
4229   }
4230 }
4231 
4232 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4233   int dst_enc = dst->encoding();
4234   int nds_enc = nds->encoding();
4235   if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4236     Assembler::vpaddb(dst, nds, src, vector_len);
4237   } else if (dst_enc < 16) {
4238     Assembler::vpaddb(dst, dst, src, vector_len);
4239   } else if (nds_enc < 16) {
4240     // implies dst_enc in upper bank with src as scratch
4241     evmovdqul(nds, dst, Assembler::AVX_512bit);
4242     Assembler::vpaddb(nds, nds, src, vector_len);
4243     evmovdqul(dst, nds, Assembler::AVX_512bit);
4244   } else {
4245     // worse case scenario, all regs in upper bank
4246     evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4247     evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4248     Assembler::vpaddb(xmm0, xmm0, src, vector_len);
4249     evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4250   }
4251 }
4252 
4253 void MacroAssembler::vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4254   int dst_enc = dst->encoding();
4255   int nds_enc = nds->encoding();
4256   int src_enc = src->encoding();
4257   if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4258     Assembler::vpaddw(dst, nds, src, vector_len);
4259   } else if ((dst_enc < 16) && (src_enc < 16)) {
4260     Assembler::vpaddw(dst, dst, src, vector_len);
4261   } else if ((dst_enc < 16) && (nds_enc < 16)) {
4262     // use nds as scratch for src
4263     evmovdqul(nds, src, Assembler::AVX_512bit);
4264     Assembler::vpaddw(dst, dst, nds, vector_len);
4265   } else if ((src_enc < 16) && (nds_enc < 16)) {
4266     // use nds as scratch for dst
4267     evmovdqul(nds, dst, Assembler::AVX_512bit);
4268     Assembler::vpaddw(nds, nds, src, vector_len);
4269     evmovdqul(dst, nds, Assembler::AVX_512bit);
4270   } else if (dst_enc < 16) {
4271     // use nds as scatch for xmm0 to hold src
4272     evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4273     evmovdqul(xmm0, src, Assembler::AVX_512bit);
4274     Assembler::vpaddw(dst, dst, xmm0, vector_len);
4275     evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4276   } else {
4277     // worse case scenario, all regs are in the upper bank
4278     subptr(rsp, 64);
4279     evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4280     evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4281     evmovdqul(xmm1, src, Assembler::AVX_512bit);
4282     evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4283     Assembler::vpaddw(xmm0, xmm0, xmm1, vector_len);
4284     evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4285     evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4286     evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4287     addptr(rsp, 64);
4288   }
4289 }
4290 
4291 void MacroAssembler::vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4292   int dst_enc = dst->encoding();
4293   int nds_enc = nds->encoding();
4294   if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4295     Assembler::vpaddw(dst, nds, src, vector_len);
4296   } else if (dst_enc < 16) {
4297     Assembler::vpaddw(dst, dst, src, vector_len);
4298   } else if (nds_enc < 16) {
4299     // implies dst_enc in upper bank with src as scratch
4300     evmovdqul(nds, dst, Assembler::AVX_512bit);
4301     Assembler::vpaddw(nds, nds, src, vector_len);
4302     evmovdqul(dst, nds, Assembler::AVX_512bit);
4303   } else {
4304     // worse case scenario, all regs in upper bank
4305     evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4306     evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4307     Assembler::vpaddw(xmm0, xmm0, src, vector_len);
4308     evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4309   }
4310 }
4311 
4312 void MacroAssembler::vpand(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len) {
4313   if (reachable(src)) {
4314     Assembler::vpand(dst, nds, as_Address(src), vector_len);
4315   } else {
4316     lea(rscratch1, src);
4317     Assembler::vpand(dst, nds, Address(rscratch1, 0), vector_len);
4318   }
4319 }
4320 
4321 void MacroAssembler::vpbroadcastw(XMMRegister dst, XMMRegister src) {
4322   int dst_enc = dst->encoding();
4323   int src_enc = src->encoding();
4324   if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4325     Assembler::vpbroadcastw(dst, src);
4326   } else if ((dst_enc < 16) && (src_enc < 16)) {
4327     Assembler::vpbroadcastw(dst, src);
4328   } else if (src_enc < 16) {
4329     subptr(rsp, 64);
4330     evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4331     evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4332     Assembler::vpbroadcastw(xmm0, src);
4333     movdqu(dst, xmm0);
4334     evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4335     addptr(rsp, 64);
4336   } else if (dst_enc < 16) {
4337     subptr(rsp, 64);
4338     evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4339     evmovdqul(xmm0, src, Assembler::AVX_512bit);
4340     Assembler::vpbroadcastw(dst, xmm0);
4341     evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4342     addptr(rsp, 64);
4343   } else {
4344     subptr(rsp, 64);
4345     evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4346     subptr(rsp, 64);
4347     evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4348     movdqu(xmm0, src);
4349     movdqu(xmm1, dst);
4350     Assembler::vpbroadcastw(xmm1, xmm0);
4351     movdqu(dst, xmm1);
4352     evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4353     addptr(rsp, 64);
4354     evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4355     addptr(rsp, 64);
4356   }
4357 }
4358 
4359 void MacroAssembler::vpcmpeqb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4360   int dst_enc = dst->encoding();
4361   int nds_enc = nds->encoding();
4362   int src_enc = src->encoding();
4363   assert(dst_enc == nds_enc, "");
4364   if ((dst_enc < 16) && (src_enc < 16)) {
4365     Assembler::vpcmpeqb(dst, nds, src, vector_len);
4366   } else if (src_enc < 16) {
4367     subptr(rsp, 64);
4368     evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4369     evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4370     Assembler::vpcmpeqb(xmm0, xmm0, src, vector_len);
4371     movdqu(dst, xmm0);
4372     evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4373     addptr(rsp, 64);
4374   } else if (dst_enc < 16) {
4375     subptr(rsp, 64);
4376     evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4377     evmovdqul(xmm0, src, Assembler::AVX_512bit);
4378     Assembler::vpcmpeqb(dst, dst, xmm0, vector_len);
4379     evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4380     addptr(rsp, 64);
4381   } else {
4382     subptr(rsp, 64);
4383     evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4384     subptr(rsp, 64);
4385     evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4386     movdqu(xmm0, src);
4387     movdqu(xmm1, dst);
4388     Assembler::vpcmpeqb(xmm1, xmm1, xmm0, vector_len);
4389     movdqu(dst, xmm1);
4390     evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4391     addptr(rsp, 64);
4392     evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4393     addptr(rsp, 64);
4394   }
4395 }
4396 
4397 void MacroAssembler::vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4398   int dst_enc = dst->encoding();
4399   int nds_enc = nds->encoding();
4400   int src_enc = src->encoding();
4401   assert(dst_enc == nds_enc, "");
4402   if ((dst_enc < 16) && (src_enc < 16)) {
4403     Assembler::vpcmpeqw(dst, nds, src, vector_len);
4404   } else if (src_enc < 16) {
4405     subptr(rsp, 64);
4406     evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4407     evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4408     Assembler::vpcmpeqw(xmm0, xmm0, src, vector_len);
4409     movdqu(dst, xmm0);
4410     evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4411     addptr(rsp, 64);
4412   } else if (dst_enc < 16) {
4413     subptr(rsp, 64);
4414     evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4415     evmovdqul(xmm0, src, Assembler::AVX_512bit);
4416     Assembler::vpcmpeqw(dst, dst, xmm0, vector_len);
4417     evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4418     addptr(rsp, 64);
4419   } else {
4420     subptr(rsp, 64);
4421     evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4422     subptr(rsp, 64);
4423     evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4424     movdqu(xmm0, src);
4425     movdqu(xmm1, dst);
4426     Assembler::vpcmpeqw(xmm1, xmm1, xmm0, vector_len);
4427     movdqu(dst, xmm1);
4428     evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4429     addptr(rsp, 64);
4430     evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4431     addptr(rsp, 64);
4432   }
4433 }
4434 
4435 void MacroAssembler::vpmovzxbw(XMMRegister dst, Address src, int vector_len) {
4436   int dst_enc = dst->encoding();
4437   if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4438     Assembler::vpmovzxbw(dst, src, vector_len);
4439   } else if (dst_enc < 16) {
4440     Assembler::vpmovzxbw(dst, src, vector_len);
4441   } else {
4442     subptr(rsp, 64);
4443     evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4444     evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4445     Assembler::vpmovzxbw(xmm0, src, vector_len);
4446     movdqu(dst, xmm0);
4447     evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4448     addptr(rsp, 64);
4449   }
4450 }
4451 
4452 void MacroAssembler::vpmovmskb(Register dst, XMMRegister src) {
4453   int src_enc = src->encoding();
4454   if (src_enc < 16) {
4455     Assembler::vpmovmskb(dst, src);
4456   } else {
4457     subptr(rsp, 64);
4458     evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4459     evmovdqul(xmm0, src, Assembler::AVX_512bit);
4460     Assembler::vpmovmskb(dst, xmm0);
4461     evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4462     addptr(rsp, 64);
4463   }
4464 }
4465 
4466 void MacroAssembler::vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4467   int dst_enc = dst->encoding();
4468   int nds_enc = nds->encoding();
4469   int src_enc = src->encoding();
4470   if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4471     Assembler::vpmullw(dst, nds, src, vector_len);
4472   } else if ((dst_enc < 16) && (src_enc < 16)) {
4473     Assembler::vpmullw(dst, dst, src, vector_len);
4474   } else if ((dst_enc < 16) && (nds_enc < 16)) {
4475     // use nds as scratch for src
4476     evmovdqul(nds, src, Assembler::AVX_512bit);
4477     Assembler::vpmullw(dst, dst, nds, vector_len);
4478   } else if ((src_enc < 16) && (nds_enc < 16)) {
4479     // use nds as scratch for dst
4480     evmovdqul(nds, dst, Assembler::AVX_512bit);
4481     Assembler::vpmullw(nds, nds, src, vector_len);
4482     evmovdqul(dst, nds, Assembler::AVX_512bit);
4483   } else if (dst_enc < 16) {
4484     // use nds as scatch for xmm0 to hold src
4485     evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4486     evmovdqul(xmm0, src, Assembler::AVX_512bit);
4487     Assembler::vpmullw(dst, dst, xmm0, vector_len);
4488     evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4489   } else {
4490     // worse case scenario, all regs are in the upper bank
4491     subptr(rsp, 64);
4492     evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4493     evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4494     evmovdqul(xmm1, src, Assembler::AVX_512bit);
4495     evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4496     Assembler::vpmullw(xmm0, xmm0, xmm1, vector_len);
4497     evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4498     evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4499     evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4500     addptr(rsp, 64);
4501   }
4502 }
4503 
4504 void MacroAssembler::vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4505   int dst_enc = dst->encoding();
4506   int nds_enc = nds->encoding();
4507   if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4508     Assembler::vpmullw(dst, nds, src, vector_len);
4509   } else if (dst_enc < 16) {
4510     Assembler::vpmullw(dst, dst, src, vector_len);
4511   } else if (nds_enc < 16) {
4512     // implies dst_enc in upper bank with src as scratch
4513     evmovdqul(nds, dst, Assembler::AVX_512bit);
4514     Assembler::vpmullw(nds, nds, src, vector_len);
4515     evmovdqul(dst, nds, Assembler::AVX_512bit);
4516   } else {
4517     // worse case scenario, all regs in upper bank
4518     evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4519     evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4520     Assembler::vpmullw(xmm0, xmm0, src, vector_len);
4521     evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4522   }
4523 }
4524 
4525 void MacroAssembler::vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4526   int dst_enc = dst->encoding();
4527   int nds_enc = nds->encoding();
4528   int src_enc = src->encoding();
4529   if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4530     Assembler::vpsubb(dst, nds, src, vector_len);
4531   } else if ((dst_enc < 16) && (src_enc < 16)) {
4532     Assembler::vpsubb(dst, dst, src, vector_len);
4533   } else if ((dst_enc < 16) && (nds_enc < 16)) {
4534     // use nds as scratch for src
4535     evmovdqul(nds, src, Assembler::AVX_512bit);
4536     Assembler::vpsubb(dst, dst, nds, vector_len);
4537   } else if ((src_enc < 16) && (nds_enc < 16)) {
4538     // use nds as scratch for dst
4539     evmovdqul(nds, dst, Assembler::AVX_512bit);
4540     Assembler::vpsubb(nds, nds, src, vector_len);
4541     evmovdqul(dst, nds, Assembler::AVX_512bit);
4542   } else if (dst_enc < 16) {
4543     // use nds as scatch for xmm0 to hold src
4544     evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4545     evmovdqul(xmm0, src, Assembler::AVX_512bit);
4546     Assembler::vpsubb(dst, dst, xmm0, vector_len);
4547     evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4548   } else {
4549     // worse case scenario, all regs are in the upper bank
4550     subptr(rsp, 64);
4551     evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4552     evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4553     evmovdqul(xmm1, src, Assembler::AVX_512bit);
4554     evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4555     Assembler::vpsubb(xmm0, xmm0, xmm1, vector_len);
4556     evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4557     evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4558     evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4559     addptr(rsp, 64);
4560   }
4561 }
4562 
4563 void MacroAssembler::vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4564   int dst_enc = dst->encoding();
4565   int nds_enc = nds->encoding();
4566   if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4567     Assembler::vpsubb(dst, nds, src, vector_len);
4568   } else if (dst_enc < 16) {
4569     Assembler::vpsubb(dst, dst, src, vector_len);
4570   } else if (nds_enc < 16) {
4571     // implies dst_enc in upper bank with src as scratch
4572     evmovdqul(nds, dst, Assembler::AVX_512bit);
4573     Assembler::vpsubb(nds, nds, src, vector_len);
4574     evmovdqul(dst, nds, Assembler::AVX_512bit);
4575   } else {
4576     // worse case scenario, all regs in upper bank
4577     evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4578     evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4579     Assembler::vpsubw(xmm0, xmm0, src, vector_len);
4580     evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4581   }
4582 }
4583 
4584 void MacroAssembler::vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4585   int dst_enc = dst->encoding();
4586   int nds_enc = nds->encoding();
4587   int src_enc = src->encoding();
4588   if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4589     Assembler::vpsubw(dst, nds, src, vector_len);
4590   } else if ((dst_enc < 16) && (src_enc < 16)) {
4591     Assembler::vpsubw(dst, dst, src, vector_len);
4592   } else if ((dst_enc < 16) && (nds_enc < 16)) {
4593     // use nds as scratch for src
4594     evmovdqul(nds, src, Assembler::AVX_512bit);
4595     Assembler::vpsubw(dst, dst, nds, vector_len);
4596   } else if ((src_enc < 16) && (nds_enc < 16)) {
4597     // use nds as scratch for dst
4598     evmovdqul(nds, dst, Assembler::AVX_512bit);
4599     Assembler::vpsubw(nds, nds, src, vector_len);
4600     evmovdqul(dst, nds, Assembler::AVX_512bit);
4601   } else if (dst_enc < 16) {
4602     // use nds as scatch for xmm0 to hold src
4603     evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4604     evmovdqul(xmm0, src, Assembler::AVX_512bit);
4605     Assembler::vpsubw(dst, dst, xmm0, vector_len);
4606     evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4607   } else {
4608     // worse case scenario, all regs are in the upper bank
4609     subptr(rsp, 64);
4610     evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4611     evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4612     evmovdqul(xmm1, src, Assembler::AVX_512bit);
4613     evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4614     Assembler::vpsubw(xmm0, xmm0, xmm1, vector_len);
4615     evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4616     evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4617     evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4618     addptr(rsp, 64);
4619   }
4620 }
4621 
4622 void MacroAssembler::vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4623   int dst_enc = dst->encoding();
4624   int nds_enc = nds->encoding();
4625   if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4626     Assembler::vpsubw(dst, nds, src, vector_len);
4627   } else if (dst_enc < 16) {
4628     Assembler::vpsubw(dst, dst, src, vector_len);
4629   } else if (nds_enc < 16) {
4630     // implies dst_enc in upper bank with src as scratch
4631     evmovdqul(nds, dst, Assembler::AVX_512bit);
4632     Assembler::vpsubw(nds, nds, src, vector_len);
4633     evmovdqul(dst, nds, Assembler::AVX_512bit);
4634   } else {
4635     // worse case scenario, all regs in upper bank
4636     evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4637     evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4638     Assembler::vpsubw(xmm0, xmm0, src, vector_len);
4639     evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4640   }
4641 }
4642 
4643 void MacroAssembler::vpsraw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
4644   int dst_enc = dst->encoding();
4645   int nds_enc = nds->encoding();
4646   int shift_enc = shift->encoding();
4647   if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4648     Assembler::vpsraw(dst, nds, shift, vector_len);
4649   } else if ((dst_enc < 16) && (shift_enc < 16)) {
4650     Assembler::vpsraw(dst, dst, shift, vector_len);
4651   } else if ((dst_enc < 16) && (nds_enc < 16)) {
4652     // use nds_enc as scratch with shift
4653     evmovdqul(nds, shift, Assembler::AVX_512bit);
4654     Assembler::vpsraw(dst, dst, nds, vector_len);
4655   } else if ((shift_enc < 16) && (nds_enc < 16)) {
4656     // use nds as scratch with dst
4657     evmovdqul(nds, dst, Assembler::AVX_512bit);
4658     Assembler::vpsraw(nds, nds, shift, vector_len);
4659     evmovdqul(dst, nds, Assembler::AVX_512bit);
4660   } else if (dst_enc < 16) {
4661     // use nds to save a copy of xmm0 and hold shift
4662     evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4663     evmovdqul(xmm0, shift, Assembler::AVX_512bit);
4664     Assembler::vpsraw(dst, dst, xmm0, vector_len);
4665     evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4666   } else if (nds_enc < 16) {
4667     // use nds as dest as temps
4668     evmovdqul(nds, dst, Assembler::AVX_512bit);
4669     evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4670     evmovdqul(xmm0, shift, Assembler::AVX_512bit);
4671     Assembler::vpsraw(nds, nds, xmm0, vector_len);
4672     evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4673     evmovdqul(dst, nds, Assembler::AVX_512bit);
4674   } else {
4675     // worse case scenario, all regs are in the upper bank
4676     subptr(rsp, 64);
4677     evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4678     evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4679     evmovdqul(xmm1, shift, Assembler::AVX_512bit);
4680     evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4681     Assembler::vpsllw(xmm0, xmm0, xmm1, vector_len);
4682     evmovdqul(xmm1, dst, Assembler::AVX_512bit);
4683     evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4684     evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4685     evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4686     addptr(rsp, 64);
4687   }
4688 }
4689 
4690 void MacroAssembler::vpsraw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
4691   int dst_enc = dst->encoding();
4692   int nds_enc = nds->encoding();
4693   if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4694     Assembler::vpsraw(dst, nds, shift, vector_len);
4695   } else if (dst_enc < 16) {
4696     Assembler::vpsraw(dst, dst, shift, vector_len);
4697   } else if (nds_enc < 16) {
4698     // use nds as scratch
4699     evmovdqul(nds, dst, Assembler::AVX_512bit);
4700     Assembler::vpsraw(nds, nds, shift, vector_len);
4701     evmovdqul(dst, nds, Assembler::AVX_512bit);
4702   } else {
4703     // use nds as scratch for xmm0
4704     evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4705     evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4706     Assembler::vpsraw(xmm0, xmm0, shift, vector_len);
4707     evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4708   }
4709 }
4710 
4711 void MacroAssembler::vpsrlw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
4712   int dst_enc = dst->encoding();
4713   int nds_enc = nds->encoding();
4714   int shift_enc = shift->encoding();
4715   if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4716     Assembler::vpsrlw(dst, nds, shift, vector_len);
4717   } else if ((dst_enc < 16) && (shift_enc < 16)) {
4718     Assembler::vpsrlw(dst, dst, shift, vector_len);
4719   } else if ((dst_enc < 16) && (nds_enc < 16)) {
4720     // use nds_enc as scratch with shift
4721     evmovdqul(nds, shift, Assembler::AVX_512bit);
4722     Assembler::vpsrlw(dst, dst, nds, vector_len);
4723   } else if ((shift_enc < 16) && (nds_enc < 16)) {
4724     // use nds as scratch with dst
4725     evmovdqul(nds, dst, Assembler::AVX_512bit);
4726     Assembler::vpsrlw(nds, nds, shift, vector_len);
4727     evmovdqul(dst, nds, Assembler::AVX_512bit);
4728   } else if (dst_enc < 16) {
4729     // use nds to save a copy of xmm0 and hold shift
4730     evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4731     evmovdqul(xmm0, shift, Assembler::AVX_512bit);
4732     Assembler::vpsrlw(dst, dst, xmm0, vector_len);
4733     evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4734   } else if (nds_enc < 16) {
4735     // use nds as dest as temps
4736     evmovdqul(nds, dst, Assembler::AVX_512bit);
4737     evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4738     evmovdqul(xmm0, shift, Assembler::AVX_512bit);
4739     Assembler::vpsrlw(nds, nds, xmm0, vector_len);
4740     evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4741     evmovdqul(dst, nds, Assembler::AVX_512bit);
4742   } else {
4743     // worse case scenario, all regs are in the upper bank
4744     subptr(rsp, 64);
4745     evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4746     evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4747     evmovdqul(xmm1, shift, Assembler::AVX_512bit);
4748     evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4749     Assembler::vpsllw(xmm0, xmm0, xmm1, vector_len);
4750     evmovdqul(xmm1, dst, Assembler::AVX_512bit);
4751     evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4752     evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4753     evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4754     addptr(rsp, 64);
4755   }
4756 }
4757 
4758 void MacroAssembler::vpsrlw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
4759   int dst_enc = dst->encoding();
4760   int nds_enc = nds->encoding();
4761   if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4762     Assembler::vpsrlw(dst, nds, shift, vector_len);
4763   } else if (dst_enc < 16) {
4764     Assembler::vpsrlw(dst, dst, shift, vector_len);
4765   } else if (nds_enc < 16) {
4766     // use nds as scratch
4767     evmovdqul(nds, dst, Assembler::AVX_512bit);
4768     Assembler::vpsrlw(nds, nds, shift, vector_len);
4769     evmovdqul(dst, nds, Assembler::AVX_512bit);
4770   } else {
4771     // use nds as scratch for xmm0
4772     evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4773     evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4774     Assembler::vpsrlw(xmm0, xmm0, shift, vector_len);
4775     evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4776   }
4777 }
4778 
4779 void MacroAssembler::vpsllw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
4780   int dst_enc = dst->encoding();
4781   int nds_enc = nds->encoding();
4782   int shift_enc = shift->encoding();
4783   if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4784     Assembler::vpsllw(dst, nds, shift, vector_len);
4785   } else if ((dst_enc < 16) && (shift_enc < 16)) {
4786     Assembler::vpsllw(dst, dst, shift, vector_len);
4787   } else if ((dst_enc < 16) && (nds_enc < 16)) {
4788     // use nds_enc as scratch with shift
4789     evmovdqul(nds, shift, Assembler::AVX_512bit);
4790     Assembler::vpsllw(dst, dst, nds, vector_len);
4791   } else if ((shift_enc < 16) && (nds_enc < 16)) {
4792     // use nds as scratch with dst
4793     evmovdqul(nds, dst, Assembler::AVX_512bit);
4794     Assembler::vpsllw(nds, nds, shift, vector_len);
4795     evmovdqul(dst, nds, Assembler::AVX_512bit);
4796   } else if (dst_enc < 16) {
4797     // use nds to save a copy of xmm0 and hold shift
4798     evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4799     evmovdqul(xmm0, shift, Assembler::AVX_512bit);
4800     Assembler::vpsllw(dst, dst, xmm0, vector_len);
4801     evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4802   } else if (nds_enc < 16) {
4803     // use nds as dest as temps
4804     evmovdqul(nds, dst, Assembler::AVX_512bit);
4805     evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4806     evmovdqul(xmm0, shift, Assembler::AVX_512bit);
4807     Assembler::vpsllw(nds, nds, xmm0, vector_len);
4808     evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4809     evmovdqul(dst, nds, Assembler::AVX_512bit);
4810   } else {
4811     // worse case scenario, all regs are in the upper bank
4812     subptr(rsp, 64);
4813     evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4814     evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4815     evmovdqul(xmm1, shift, Assembler::AVX_512bit);
4816     evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4817     Assembler::vpsllw(xmm0, xmm0, xmm1, vector_len);
4818     evmovdqul(xmm1, dst, Assembler::AVX_512bit);
4819     evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4820     evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4821     evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4822     addptr(rsp, 64);
4823   }
4824 }
4825 
4826 void MacroAssembler::vpsllw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
4827   int dst_enc = dst->encoding();
4828   int nds_enc = nds->encoding();
4829   if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4830     Assembler::vpsllw(dst, nds, shift, vector_len);
4831   } else if (dst_enc < 16) {
4832     Assembler::vpsllw(dst, dst, shift, vector_len);
4833   } else if (nds_enc < 16) {
4834     // use nds as scratch
4835     evmovdqul(nds, dst, Assembler::AVX_512bit);
4836     Assembler::vpsllw(nds, nds, shift, vector_len);
4837     evmovdqul(dst, nds, Assembler::AVX_512bit);
4838   } else {
4839     // use nds as scratch for xmm0
4840     evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4841     evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4842     Assembler::vpsllw(xmm0, xmm0, shift, vector_len);
4843     evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4844   }
4845 }
4846 
4847 void MacroAssembler::vptest(XMMRegister dst, XMMRegister src) {
4848   int dst_enc = dst->encoding();
4849   int src_enc = src->encoding();
4850   if ((dst_enc < 16) && (src_enc < 16)) {
4851     Assembler::vptest(dst, src);
4852   } else if (src_enc < 16) {
4853     subptr(rsp, 64);
4854     evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4855     evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4856     Assembler::vptest(xmm0, src);
4857     evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4858     addptr(rsp, 64);
4859   } else if (dst_enc < 16) {
4860     subptr(rsp, 64);
4861     evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4862     evmovdqul(xmm0, src, Assembler::AVX_512bit);
4863     Assembler::vptest(dst, xmm0);
4864     evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4865     addptr(rsp, 64);
4866   } else {
4867     subptr(rsp, 64);
4868     evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4869     subptr(rsp, 64);
4870     evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4871     movdqu(xmm0, src);
4872     movdqu(xmm1, dst);
4873     Assembler::vptest(xmm1, xmm0);
4874     evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4875     addptr(rsp, 64);
4876     evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4877     addptr(rsp, 64);
4878   }
4879 }
4880 
4881 // This instruction exists within macros, ergo we cannot control its input
4882 // when emitted through those patterns.
4883 void MacroAssembler::punpcklbw(XMMRegister dst, XMMRegister src) {
4884   if (VM_Version::supports_avx512nobw()) {
4885     int dst_enc = dst->encoding();
4886     int src_enc = src->encoding();
4887     if (dst_enc == src_enc) {
4888       if (dst_enc < 16) {
4889         Assembler::punpcklbw(dst, src);
4890       } else {
4891         subptr(rsp, 64);
4892         evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4893         evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4894         Assembler::punpcklbw(xmm0, xmm0);
4895         evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4896         evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4897         addptr(rsp, 64);
4898       }
4899     } else {
4900       if ((src_enc < 16) && (dst_enc < 16)) {
4901         Assembler::punpcklbw(dst, src);
4902       } else if (src_enc < 16) {
4903         subptr(rsp, 64);
4904         evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4905         evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4906         Assembler::punpcklbw(xmm0, src);
4907         evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4908         evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4909         addptr(rsp, 64);
4910       } else if (dst_enc < 16) {
4911         subptr(rsp, 64);
4912         evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4913         evmovdqul(xmm0, src, Assembler::AVX_512bit);
4914         Assembler::punpcklbw(dst, xmm0);
4915         evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4916         addptr(rsp, 64);
4917       } else {
4918         subptr(rsp, 64);
4919         evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4920         subptr(rsp, 64);
4921         evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4922         evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4923         evmovdqul(xmm1, src, Assembler::AVX_512bit);
4924         Assembler::punpcklbw(xmm0, xmm1);
4925         evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4926         evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4927         addptr(rsp, 64);
4928         evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4929         addptr(rsp, 64);
4930       }
4931     }
4932   } else {
4933     Assembler::punpcklbw(dst, src);
4934   }
4935 }
4936 
4937 // This instruction exists within macros, ergo we cannot control its input
4938 // when emitted through those patterns.
4939 void MacroAssembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) {
4940   if (VM_Version::supports_avx512nobw()) {
4941     int dst_enc = dst->encoding();
4942     int src_enc = src->encoding();
4943     if (dst_enc == src_enc) {
4944       if (dst_enc < 16) {
4945         Assembler::pshuflw(dst, src, mode);
4946       } else {
4947         subptr(rsp, 64);
4948         evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4949         evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4950         Assembler::pshuflw(xmm0, xmm0, mode);
4951         evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4952         evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4953         addptr(rsp, 64);
4954       }
4955     } else {
4956       if ((src_enc < 16) && (dst_enc < 16)) {
4957         Assembler::pshuflw(dst, src, mode);
4958       } else if (src_enc < 16) {
4959         subptr(rsp, 64);
4960         evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4961         evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4962         Assembler::pshuflw(xmm0, src, mode);
4963         evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4964         evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4965         addptr(rsp, 64);
4966       } else if (dst_enc < 16) {
4967         subptr(rsp, 64);
4968         evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4969         evmovdqul(xmm0, src, Assembler::AVX_512bit);
4970         Assembler::pshuflw(dst, xmm0, mode);
4971         evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4972         addptr(rsp, 64);
4973       } else {
4974         subptr(rsp, 64);
4975         evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4976         subptr(rsp, 64);
4977         evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4978         evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4979         evmovdqul(xmm1, src, Assembler::AVX_512bit);
4980         Assembler::pshuflw(xmm0, xmm1, mode);
4981         evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4982         evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4983         addptr(rsp, 64);
4984         evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4985         addptr(rsp, 64);
4986       }
4987     }
4988   } else {
4989     Assembler::pshuflw(dst, src, mode);
4990   }
4991 }
4992 
4993 void MacroAssembler::vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len) {
4994   if (reachable(src)) {
4995     vandpd(dst, nds, as_Address(src), vector_len);
4996   } else {
4997     lea(rscratch1, src);
4998     vandpd(dst, nds, Address(rscratch1, 0), vector_len);
4999   }
5000 }
5001 
5002 void MacroAssembler::vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len) {
5003   if (reachable(src)) {
5004     vandps(dst, nds, as_Address(src), vector_len);
5005   } else {
5006     lea(rscratch1, src);
5007     vandps(dst, nds, Address(rscratch1, 0), vector_len);
5008   }
5009 }
5010 
5011 void MacroAssembler::vdivsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
5012   if (reachable(src)) {
5013     vdivsd(dst, nds, as_Address(src));
5014   } else {
5015     lea(rscratch1, src);
5016     vdivsd(dst, nds, Address(rscratch1, 0));
5017   }
5018 }
5019 
5020 void MacroAssembler::vdivss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
5021   if (reachable(src)) {
5022     vdivss(dst, nds, as_Address(src));
5023   } else {
5024     lea(rscratch1, src);
5025     vdivss(dst, nds, Address(rscratch1, 0));
5026   }
5027 }
5028 
5029 void MacroAssembler::vmulsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
5030   if (reachable(src)) {
5031     vmulsd(dst, nds, as_Address(src));
5032   } else {
5033     lea(rscratch1, src);
5034     vmulsd(dst, nds, Address(rscratch1, 0));
5035   }
5036 }
5037 
5038 void MacroAssembler::vmulss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
5039   if (reachable(src)) {
5040     vmulss(dst, nds, as_Address(src));
5041   } else {
5042     lea(rscratch1, src);
5043     vmulss(dst, nds, Address(rscratch1, 0));
5044   }
5045 }
5046 
5047 void MacroAssembler::vsubsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
5048   if (reachable(src)) {
5049     vsubsd(dst, nds, as_Address(src));
5050   } else {
5051     lea(rscratch1, src);
5052     vsubsd(dst, nds, Address(rscratch1, 0));
5053   }
5054 }
5055 
5056 void MacroAssembler::vsubss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
5057   if (reachable(src)) {
5058     vsubss(dst, nds, as_Address(src));
5059   } else {
5060     lea(rscratch1, src);
5061     vsubss(dst, nds, Address(rscratch1, 0));
5062   }
5063 }
5064 
5065 void MacroAssembler::vnegatess(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
5066   int nds_enc = nds->encoding();
5067   int dst_enc = dst->encoding();
5068   bool dst_upper_bank = (dst_enc > 15);
5069   bool nds_upper_bank = (nds_enc > 15);
5070   if (VM_Version::supports_avx512novl() &&
5071       (nds_upper_bank || dst_upper_bank)) {
5072     if (dst_upper_bank) {
5073       subptr(rsp, 64);
5074       evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
5075       movflt(xmm0, nds);
5076       vxorps(xmm0, xmm0, src, Assembler::AVX_128bit);
5077       movflt(dst, xmm0);
5078       evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
5079       addptr(rsp, 64);
5080     } else {
5081       movflt(dst, nds);
5082       vxorps(dst, dst, src, Assembler::AVX_128bit);
5083     }
5084   } else {
5085     vxorps(dst, nds, src, Assembler::AVX_128bit);
5086   }
5087 }
5088 
5089 void MacroAssembler::vnegatesd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
5090   int nds_enc = nds->encoding();
5091   int dst_enc = dst->encoding();
5092   bool dst_upper_bank = (dst_enc > 15);
5093   bool nds_upper_bank = (nds_enc > 15);
5094   if (VM_Version::supports_avx512novl() &&
5095       (nds_upper_bank || dst_upper_bank)) {
5096     if (dst_upper_bank) {
5097       subptr(rsp, 64);
5098       evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
5099       movdbl(xmm0, nds);
5100       vxorpd(xmm0, xmm0, src, Assembler::AVX_128bit);
5101       movdbl(dst, xmm0);
5102       evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
5103       addptr(rsp, 64);
5104     } else {
5105       movdbl(dst, nds);
5106       vxorpd(dst, dst, src, Assembler::AVX_128bit);
5107     }
5108   } else {
5109     vxorpd(dst, nds, src, Assembler::AVX_128bit);
5110   }
5111 }
5112 
5113 void MacroAssembler::vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len) {
5114   if (reachable(src)) {
5115     vxorpd(dst, nds, as_Address(src), vector_len);
5116   } else {
5117     lea(rscratch1, src);
5118     vxorpd(dst, nds, Address(rscratch1, 0), vector_len);
5119   }
5120 }
5121 
5122 void MacroAssembler::vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len) {
5123   if (reachable(src)) {
5124     vxorps(dst, nds, as_Address(src), vector_len);
5125   } else {
5126     lea(rscratch1, src);
5127     vxorps(dst, nds, Address(rscratch1, 0), vector_len);
5128   }
5129 }
5130 
5131 
5132 void MacroAssembler::resolve_jobject(Register value,
5133                                      Register thread,
5134                                      Register tmp) {
5135   assert_different_registers(value, thread, tmp);
5136   Label done, not_weak;
5137   testptr(value, value);
5138   jcc(Assembler::zero, done);                // Use NULL as-is.
5139   testptr(value, JNIHandles::weak_tag_mask); // Test for jweak tag.
5140   jcc(Assembler::zero, not_weak);
5141   // Resolve jweak.
5142   movptr(value, Address(value, -JNIHandles::weak_tag_value));
5143   verify_oop(value);
5144 #if INCLUDE_ALL_GCS
5145   if (UseG1GC) {
5146     g1_write_barrier_pre(noreg /* obj */,
5147                          value /* pre_val */,
5148                          thread /* thread */,
5149                          tmp /* tmp */,
5150                          true /* tosca_live */,
5151                          true /* expand_call */);
5152   }
5153 #endif // INCLUDE_ALL_GCS
5154   jmp(done);
5155   bind(not_weak);
5156   // Resolve (untagged) jobject.
5157   movptr(value, Address(value, 0));
5158   verify_oop(value);
5159   bind(done);
5160 }
5161 
5162 void MacroAssembler::clear_jweak_tag(Register possibly_jweak) {
5163   const int32_t inverted_jweak_mask = ~static_cast<int32_t>(JNIHandles::weak_tag_mask);
5164   STATIC_ASSERT(inverted_jweak_mask == -2); // otherwise check this code
5165   // The inverted mask is sign-extended
5166   andptr(possibly_jweak, inverted_jweak_mask);
5167 }
5168 
5169 //////////////////////////////////////////////////////////////////////////////////
5170 #if INCLUDE_ALL_GCS
5171 
5172 void MacroAssembler::g1_write_barrier_pre(Register obj,
5173                                           Register pre_val,
5174                                           Register thread,
5175                                           Register tmp,
5176                                           bool tosca_live,
5177                                           bool expand_call) {
5178 
5179   // If expand_call is true then we expand the call_VM_leaf macro
5180   // directly to skip generating the check by
5181   // InterpreterMacroAssembler::call_VM_leaf_base that checks _last_sp.
5182 
5183 #ifdef _LP64
5184   assert(thread == r15_thread, "must be");
5185 #endif // _LP64
5186 
5187   Label done;
5188   Label runtime;
5189 
5190   assert(pre_val != noreg, "check this code");
5191 
5192   if (obj != noreg) {
5193     assert_different_registers(obj, pre_val, tmp);
5194     assert(pre_val != rax, "check this code");
5195   }
5196 
5197   Address in_progress(thread, in_bytes(JavaThread::satb_mark_queue_offset() +
5198                                        SATBMarkQueue::byte_offset_of_active()));
5199   Address index(thread, in_bytes(JavaThread::satb_mark_queue_offset() +
5200                                        SATBMarkQueue::byte_offset_of_index()));
5201   Address buffer(thread, in_bytes(JavaThread::satb_mark_queue_offset() +
5202                                        SATBMarkQueue::byte_offset_of_buf()));
5203 
5204 
5205   // Is marking active?
5206   if (in_bytes(SATBMarkQueue::byte_width_of_active()) == 4) {
5207     cmpl(in_progress, 0);
5208   } else {
5209     assert(in_bytes(SATBMarkQueue::byte_width_of_active()) == 1, "Assumption");
5210     cmpb(in_progress, 0);
5211   }
5212   jcc(Assembler::equal, done);
5213 
5214   // Do we need to load the previous value?
5215   if (obj != noreg) {
5216     load_heap_oop(pre_val, Address(obj, 0));
5217   }
5218 
5219   // Is the previous value null?
5220   cmpptr(pre_val, (int32_t) NULL_WORD);
5221   jcc(Assembler::equal, done);
5222 
5223   // Can we store original value in the thread's buffer?
5224   // Is index == 0?
5225   // (The index field is typed as size_t.)
5226 
5227   movptr(tmp, index);                   // tmp := *index_adr
5228   cmpptr(tmp, 0);                       // tmp == 0?
5229   jcc(Assembler::equal, runtime);       // If yes, goto runtime
5230 
5231   subptr(tmp, wordSize);                // tmp := tmp - wordSize
5232   movptr(index, tmp);                   // *index_adr := tmp
5233   addptr(tmp, buffer);                  // tmp := tmp + *buffer_adr
5234 
5235   // Record the previous value
5236   movptr(Address(tmp, 0), pre_val);
5237   jmp(done);
5238 
5239   bind(runtime);
5240   // save the live input values
5241   if(tosca_live) push(rax);
5242 
5243   if (obj != noreg && obj != rax)
5244     push(obj);
5245 
5246   if (pre_val != rax)
5247     push(pre_val);
5248 
5249   // Calling the runtime using the regular call_VM_leaf mechanism generates
5250   // code (generated by InterpreterMacroAssember::call_VM_leaf_base)
5251   // that checks that the *(ebp+frame::interpreter_frame_last_sp) == NULL.
5252   //
5253   // If we care generating the pre-barrier without a frame (e.g. in the
5254   // intrinsified Reference.get() routine) then ebp might be pointing to
5255   // the caller frame and so this check will most likely fail at runtime.
5256   //
5257   // Expanding the call directly bypasses the generation of the check.
5258   // So when we do not have have a full interpreter frame on the stack
5259   // expand_call should be passed true.
5260 
5261   NOT_LP64( push(thread); )
5262 
5263   if (expand_call) {
5264     LP64_ONLY( assert(pre_val != c_rarg1, "smashed arg"); )
5265     pass_arg1(this, thread);
5266     pass_arg0(this, pre_val);
5267     MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_pre), 2);
5268   } else {
5269     call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_pre), pre_val, thread);
5270   }
5271 
5272   NOT_LP64( pop(thread); )
5273 
5274   // save the live input values
5275   if (pre_val != rax)
5276     pop(pre_val);
5277 
5278   if (obj != noreg && obj != rax)
5279     pop(obj);
5280 
5281   if(tosca_live) pop(rax);
5282 
5283   bind(done);
5284 }
5285 
5286 void MacroAssembler::g1_write_barrier_post(Register store_addr,
5287                                            Register new_val,
5288                                            Register thread,
5289                                            Register tmp,
5290                                            Register tmp2) {
5291 #ifdef _LP64
5292   assert(thread == r15_thread, "must be");
5293 #endif // _LP64
5294 
5295   Address queue_index(thread, in_bytes(JavaThread::dirty_card_queue_offset() +
5296                                        DirtyCardQueue::byte_offset_of_index()));
5297   Address buffer(thread, in_bytes(JavaThread::dirty_card_queue_offset() +
5298                                        DirtyCardQueue::byte_offset_of_buf()));
5299 
5300   CardTableModRefBS* ct =
5301     barrier_set_cast<CardTableModRefBS>(GC::gc()->heap()->barrier_set());
5302   assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code");
5303 
5304   Label done;
5305   Label runtime;
5306 
5307   // Does store cross heap regions?
5308 
5309   movptr(tmp, store_addr);
5310   xorptr(tmp, new_val);
5311   shrptr(tmp, HeapRegion::LogOfHRGrainBytes);
5312   jcc(Assembler::equal, done);
5313 
5314   // crosses regions, storing NULL?
5315 
5316   cmpptr(new_val, (int32_t) NULL_WORD);
5317   jcc(Assembler::equal, done);
5318 
5319   // storing region crossing non-NULL, is card already dirty?
5320 
5321   const Register card_addr = tmp;
5322   const Register cardtable = tmp2;
5323 
5324   movptr(card_addr, store_addr);
5325   shrptr(card_addr, CardTableModRefBS::card_shift);
5326   // Do not use ExternalAddress to load 'byte_map_base', since 'byte_map_base' is NOT
5327   // a valid address and therefore is not properly handled by the relocation code.
5328   movptr(cardtable, (intptr_t)ct->byte_map_base);
5329   addptr(card_addr, cardtable);
5330 
5331   cmpb(Address(card_addr, 0), (int)G1SATBCardTableModRefBS::g1_young_card_val());
5332   jcc(Assembler::equal, done);
5333 
5334   membar(Assembler::Membar_mask_bits(Assembler::StoreLoad));
5335   cmpb(Address(card_addr, 0), (int)CardTableModRefBS::dirty_card_val());
5336   jcc(Assembler::equal, done);
5337 
5338 
5339   // storing a region crossing, non-NULL oop, card is clean.
5340   // dirty card and log.
5341 
5342   movb(Address(card_addr, 0), (int)CardTableModRefBS::dirty_card_val());
5343 
5344   cmpl(queue_index, 0);
5345   jcc(Assembler::equal, runtime);
5346   subl(queue_index, wordSize);
5347   movptr(tmp2, buffer);
5348 #ifdef _LP64
5349   movslq(rscratch1, queue_index);
5350   addq(tmp2, rscratch1);
5351   movq(Address(tmp2, 0), card_addr);
5352 #else
5353   addl(tmp2, queue_index);
5354   movl(Address(tmp2, 0), card_addr);
5355 #endif
5356   jmp(done);
5357 
5358   bind(runtime);
5359   // save the live input values
5360   push(store_addr);
5361   push(new_val);
5362 #ifdef _LP64
5363   call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_post), card_addr, r15_thread);
5364 #else
5365   push(thread);
5366   call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_post), card_addr, thread);
5367   pop(thread);
5368 #endif
5369   pop(new_val);
5370   pop(store_addr);
5371 
5372   bind(done);
5373 }
5374 
5375 #endif // INCLUDE_ALL_GCS
5376 //////////////////////////////////////////////////////////////////////////////////
5377 
5378 
5379 void MacroAssembler::store_check(Register obj, Address dst) {
5380   store_check(obj);
5381 }
5382 
5383 void MacroAssembler::store_check(Register obj) {
5384   // Does a store check for the oop in register obj. The content of
5385   // register obj is destroyed afterwards.
5386   BarrierSet* bs = GC::gc()->heap()->barrier_set();
5387   assert(bs->kind() == BarrierSet::CardTableForRS ||
5388          bs->kind() == BarrierSet::CardTableExtension,
5389          "Wrong barrier set kind");
5390 
5391   CardTableModRefBS* ct = barrier_set_cast<CardTableModRefBS>(bs);
5392   assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code");
5393 
5394   shrptr(obj, CardTableModRefBS::card_shift);
5395 
5396   Address card_addr;
5397 
5398   // The calculation for byte_map_base is as follows:
5399   // byte_map_base = _byte_map - (uintptr_t(low_bound) >> card_shift);
5400   // So this essentially converts an address to a displacement and it will
5401   // never need to be relocated. On 64bit however the value may be too
5402   // large for a 32bit displacement.
5403   intptr_t disp = (intptr_t) ct->byte_map_base;
5404   if (is_simm32(disp)) {
5405     card_addr = Address(noreg, obj, Address::times_1, disp);
5406   } else {
5407     // By doing it as an ExternalAddress 'disp' could be converted to a rip-relative
5408     // displacement and done in a single instruction given favorable mapping and a
5409     // smarter version of as_Address. However, 'ExternalAddress' generates a relocation
5410     // entry and that entry is not properly handled by the relocation code.
5411     AddressLiteral cardtable((address)ct->byte_map_base, relocInfo::none);
5412     Address index(noreg, obj, Address::times_1);
5413     card_addr = as_Address(ArrayAddress(cardtable, index));
5414   }
5415 
5416   int dirty = CardTableModRefBS::dirty_card_val();
5417   if (UseCondCardMark) {
5418     Label L_already_dirty;
5419     if (UseConcMarkSweepGC) {
5420       membar(Assembler::StoreLoad);
5421     }
5422     cmpb(card_addr, dirty);
5423     jcc(Assembler::equal, L_already_dirty);
5424     movb(card_addr, dirty);
5425     bind(L_already_dirty);
5426   } else {
5427     movb(card_addr, dirty);
5428   }
5429 }
5430 
5431 void MacroAssembler::subptr(Register dst, int32_t imm32) {
5432   LP64_ONLY(subq(dst, imm32)) NOT_LP64(subl(dst, imm32));
5433 }
5434 
5435 // Force generation of a 4 byte immediate value even if it fits into 8bit
5436 void MacroAssembler::subptr_imm32(Register dst, int32_t imm32) {
5437   LP64_ONLY(subq_imm32(dst, imm32)) NOT_LP64(subl_imm32(dst, imm32));
5438 }
5439 
5440 void MacroAssembler::subptr(Register dst, Register src) {
5441   LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src));
5442 }
5443 
5444 // C++ bool manipulation
5445 void MacroAssembler::testbool(Register dst) {
5446   if(sizeof(bool) == 1)
5447     testb(dst, 0xff);
5448   else if(sizeof(bool) == 2) {
5449     // testw implementation needed for two byte bools
5450     ShouldNotReachHere();
5451   } else if(sizeof(bool) == 4)
5452     testl(dst, dst);
5453   else
5454     // unsupported
5455     ShouldNotReachHere();
5456 }
5457 
5458 void MacroAssembler::testptr(Register dst, Register src) {
5459   LP64_ONLY(testq(dst, src)) NOT_LP64(testl(dst, src));
5460 }
5461 
5462 // Defines obj, preserves var_size_in_bytes, okay for t2 == var_size_in_bytes.
5463 void MacroAssembler::tlab_allocate(Register obj,
5464                                    Register var_size_in_bytes,
5465                                    int con_size_in_bytes,
5466                                    Register t1,
5467                                    Register t2,
5468                                    Label& slow_case) {
5469   assert_different_registers(obj, t1, t2);
5470   assert_different_registers(obj, var_size_in_bytes, t1);
5471   Register end = t2;
5472   Register thread = NOT_LP64(t1) LP64_ONLY(r15_thread);
5473 
5474   verify_tlab();
5475 
5476   NOT_LP64(get_thread(thread));
5477 
5478   movptr(obj, Address(thread, JavaThread::tlab_top_offset()));
5479   if (var_size_in_bytes == noreg) {
5480     lea(end, Address(obj, con_size_in_bytes));
5481   } else {
5482     lea(end, Address(obj, var_size_in_bytes, Address::times_1));
5483   }
5484   cmpptr(end, Address(thread, JavaThread::tlab_end_offset()));
5485   jcc(Assembler::above, slow_case);
5486 
5487   // update the tlab top pointer
5488   movptr(Address(thread, JavaThread::tlab_top_offset()), end);
5489 
5490   // recover var_size_in_bytes if necessary
5491   if (var_size_in_bytes == end) {
5492     subptr(var_size_in_bytes, obj);
5493   }
5494   verify_tlab();
5495 }
5496 
5497 // Preserves rbx, and rdx.
5498 Register MacroAssembler::tlab_refill(Label& retry,
5499                                      Label& try_eden,
5500                                      Label& slow_case) {
5501   Register top = rax;
5502   Register t1  = rcx; // object size
5503   Register t2  = rsi;
5504   Register thread_reg = NOT_LP64(rdi) LP64_ONLY(r15_thread);
5505   assert_different_registers(top, thread_reg, t1, t2, /* preserve: */ rbx, rdx);
5506   Label do_refill, discard_tlab;
5507 
5508   if (!GC::gc()->heap()->supports_inline_contig_alloc()) {
5509     // No allocation in the shared eden.
5510     jmp(slow_case);
5511   }
5512 
5513   NOT_LP64(get_thread(thread_reg));
5514 
5515   movptr(top, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
5516   movptr(t1,  Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())));
5517 
5518   // calculate amount of free space
5519   subptr(t1, top);
5520   shrptr(t1, LogHeapWordSize);
5521 
5522   // Retain tlab and allocate object in shared space if
5523   // the amount free in the tlab is too large to discard.
5524   cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_refill_waste_limit_offset())));
5525   jcc(Assembler::lessEqual, discard_tlab);
5526 
5527   // Retain
5528   // %%% yuck as movptr...
5529   movptr(t2, (int32_t) ThreadLocalAllocBuffer::refill_waste_limit_increment());
5530   addptr(Address(thread_reg, in_bytes(JavaThread::tlab_refill_waste_limit_offset())), t2);
5531   if (TLABStats) {
5532     // increment number of slow_allocations
5533     addl(Address(thread_reg, in_bytes(JavaThread::tlab_slow_allocations_offset())), 1);
5534   }
5535   jmp(try_eden);
5536 
5537   bind(discard_tlab);
5538   if (TLABStats) {
5539     // increment number of refills
5540     addl(Address(thread_reg, in_bytes(JavaThread::tlab_number_of_refills_offset())), 1);
5541     // accumulate wastage -- t1 is amount free in tlab
5542     addl(Address(thread_reg, in_bytes(JavaThread::tlab_fast_refill_waste_offset())), t1);
5543   }
5544 
5545   // if tlab is currently allocated (top or end != null) then
5546   // fill [top, end + alignment_reserve) with array object
5547   testptr(top, top);
5548   jcc(Assembler::zero, do_refill);
5549 
5550   // set up the mark word
5551   movptr(Address(top, oopDesc::mark_offset_in_bytes()), (intptr_t)markOopDesc::prototype()->copy_set_hash(0x2));
5552   // set the length to the remaining space
5553   subptr(t1, typeArrayOopDesc::header_size(T_INT));
5554   addptr(t1, (int32_t)ThreadLocalAllocBuffer::alignment_reserve());
5555   shlptr(t1, log2_intptr(HeapWordSize/sizeof(jint)));
5556   movl(Address(top, arrayOopDesc::length_offset_in_bytes()), t1);
5557   // set klass to intArrayKlass
5558   // dubious reloc why not an oop reloc?
5559   movptr(t1, ExternalAddress((address)Universe::intArrayKlassObj_addr()));
5560   // store klass last.  concurrent gcs assumes klass length is valid if
5561   // klass field is not null.
5562   store_klass(top, t1);
5563 
5564   movptr(t1, top);
5565   subptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())));
5566   incr_allocated_bytes(thread_reg, t1, 0);
5567 
5568   // refill the tlab with an eden allocation
5569   bind(do_refill);
5570   movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_size_offset())));
5571   shlptr(t1, LogHeapWordSize);
5572   // allocate new tlab, address returned in top
5573   eden_allocate(top, t1, 0, t2, slow_case);
5574 
5575   // Check that t1 was preserved in eden_allocate.
5576 #ifdef ASSERT
5577   if (UseTLAB) {
5578     Label ok;
5579     Register tsize = rsi;
5580     assert_different_registers(tsize, thread_reg, t1);
5581     push(tsize);
5582     movptr(tsize, Address(thread_reg, in_bytes(JavaThread::tlab_size_offset())));
5583     shlptr(tsize, LogHeapWordSize);
5584     cmpptr(t1, tsize);
5585     jcc(Assembler::equal, ok);
5586     STOP("assert(t1 != tlab size)");
5587     should_not_reach_here();
5588 
5589     bind(ok);
5590     pop(tsize);
5591   }
5592 #endif
5593   movptr(Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())), top);
5594   movptr(Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())), top);
5595   addptr(top, t1);
5596   subptr(top, (int32_t)ThreadLocalAllocBuffer::alignment_reserve_in_bytes());
5597   movptr(Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())), top);
5598 
5599   if (ZeroTLAB) {
5600     // This is a fast TLAB refill, therefore the GC is not notified of it.
5601     // So compiled code must fill the new TLAB with zeroes.
5602     movptr(top, Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())));
5603     zero_memory(top, t1, 0, t2);
5604   }
5605 
5606   verify_tlab();
5607   jmp(retry);
5608 
5609   return thread_reg; // for use by caller
5610 }
5611 
5612 // Preserves the contents of address, destroys the contents length_in_bytes and temp.
5613 void MacroAssembler::zero_memory(Register address, Register length_in_bytes, int offset_in_bytes, Register temp) {
5614   assert(address != length_in_bytes && address != temp && temp != length_in_bytes, "registers must be different");
5615   assert((offset_in_bytes & (BytesPerWord - 1)) == 0, "offset must be a multiple of BytesPerWord");
5616   Label done;
5617 
5618   testptr(length_in_bytes, length_in_bytes);
5619   jcc(Assembler::zero, done);
5620 
5621   // initialize topmost word, divide index by 2, check if odd and test if zero
5622   // note: for the remaining code to work, index must be a multiple of BytesPerWord
5623 #ifdef ASSERT
5624   {
5625     Label L;
5626     testptr(length_in_bytes, BytesPerWord - 1);
5627     jcc(Assembler::zero, L);
5628     stop("length must be a multiple of BytesPerWord");
5629     bind(L);
5630   }
5631 #endif
5632   Register index = length_in_bytes;
5633   xorptr(temp, temp);    // use _zero reg to clear memory (shorter code)
5634   if (UseIncDec) {
5635     shrptr(index, 3);  // divide by 8/16 and set carry flag if bit 2 was set
5636   } else {
5637     shrptr(index, 2);  // use 2 instructions to avoid partial flag stall
5638     shrptr(index, 1);
5639   }
5640 #ifndef _LP64
5641   // index could have not been a multiple of 8 (i.e., bit 2 was set)
5642   {
5643     Label even;
5644     // note: if index was a multiple of 8, then it cannot
5645     //       be 0 now otherwise it must have been 0 before
5646     //       => if it is even, we don't need to check for 0 again
5647     jcc(Assembler::carryClear, even);
5648     // clear topmost word (no jump would be needed if conditional assignment worked here)
5649     movptr(Address(address, index, Address::times_8, offset_in_bytes - 0*BytesPerWord), temp);
5650     // index could be 0 now, must check again
5651     jcc(Assembler::zero, done);
5652     bind(even);
5653   }
5654 #endif // !_LP64
5655   // initialize remaining object fields: index is a multiple of 2 now
5656   {
5657     Label loop;
5658     bind(loop);
5659     movptr(Address(address, index, Address::times_8, offset_in_bytes - 1*BytesPerWord), temp);
5660     NOT_LP64(movptr(Address(address, index, Address::times_8, offset_in_bytes - 2*BytesPerWord), temp);)
5661     decrement(index);
5662     jcc(Assembler::notZero, loop);
5663   }
5664 
5665   bind(done);
5666 }
5667 
5668 void MacroAssembler::incr_allocated_bytes(Register thread,
5669                                           Register var_size_in_bytes,
5670                                           int con_size_in_bytes,
5671                                           Register t1) {
5672   if (!thread->is_valid()) {
5673 #ifdef _LP64
5674     thread = r15_thread;
5675 #else
5676     assert(t1->is_valid(), "need temp reg");
5677     thread = t1;
5678     get_thread(thread);
5679 #endif
5680   }
5681 
5682 #ifdef _LP64
5683   if (var_size_in_bytes->is_valid()) {
5684     addq(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), var_size_in_bytes);
5685   } else {
5686     addq(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), con_size_in_bytes);
5687   }
5688 #else
5689   if (var_size_in_bytes->is_valid()) {
5690     addl(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), var_size_in_bytes);
5691   } else {
5692     addl(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), con_size_in_bytes);
5693   }
5694   adcl(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())+4), 0);
5695 #endif
5696 }
5697 
5698 // Look up the method for a megamorphic invokeinterface call.
5699 // The target method is determined by <intf_klass, itable_index>.
5700 // The receiver klass is in recv_klass.
5701 // On success, the result will be in method_result, and execution falls through.
5702 // On failure, execution transfers to the given label.
5703 void MacroAssembler::lookup_interface_method(Register recv_klass,
5704                                              Register intf_klass,
5705                                              RegisterOrConstant itable_index,
5706                                              Register method_result,
5707                                              Register scan_temp,
5708                                              Label& L_no_such_interface) {
5709   assert_different_registers(recv_klass, intf_klass, method_result, scan_temp);
5710   assert(itable_index.is_constant() || itable_index.as_register() == method_result,
5711          "caller must use same register for non-constant itable index as for method");
5712 
5713   // Compute start of first itableOffsetEntry (which is at the end of the vtable)
5714   int vtable_base = in_bytes(Klass::vtable_start_offset());
5715   int itentry_off = itableMethodEntry::method_offset_in_bytes();
5716   int scan_step   = itableOffsetEntry::size() * wordSize;
5717   int vte_size    = vtableEntry::size_in_bytes();
5718   Address::ScaleFactor times_vte_scale = Address::times_ptr;
5719   assert(vte_size == wordSize, "else adjust times_vte_scale");
5720 
5721   movl(scan_temp, Address(recv_klass, Klass::vtable_length_offset()));
5722 
5723   // %%% Could store the aligned, prescaled offset in the klassoop.
5724   lea(scan_temp, Address(recv_klass, scan_temp, times_vte_scale, vtable_base));
5725 
5726   // Adjust recv_klass by scaled itable_index, so we can free itable_index.
5727   assert(itableMethodEntry::size() * wordSize == wordSize, "adjust the scaling in the code below");
5728   lea(recv_klass, Address(recv_klass, itable_index, Address::times_ptr, itentry_off));
5729 
5730   // for (scan = klass->itable(); scan->interface() != NULL; scan += scan_step) {
5731   //   if (scan->interface() == intf) {
5732   //     result = (klass + scan->offset() + itable_index);
5733   //   }
5734   // }
5735   Label search, found_method;
5736 
5737   for (int peel = 1; peel >= 0; peel--) {
5738     movptr(method_result, Address(scan_temp, itableOffsetEntry::interface_offset_in_bytes()));
5739     cmpptr(intf_klass, method_result);
5740 
5741     if (peel) {
5742       jccb(Assembler::equal, found_method);
5743     } else {
5744       jccb(Assembler::notEqual, search);
5745       // (invert the test to fall through to found_method...)
5746     }
5747 
5748     if (!peel)  break;
5749 
5750     bind(search);
5751 
5752     // Check that the previous entry is non-null.  A null entry means that
5753     // the receiver class doesn't implement the interface, and wasn't the
5754     // same as when the caller was compiled.
5755     testptr(method_result, method_result);
5756     jcc(Assembler::zero, L_no_such_interface);
5757     addptr(scan_temp, scan_step);
5758   }
5759 
5760   bind(found_method);
5761 
5762   // Got a hit.
5763   movl(scan_temp, Address(scan_temp, itableOffsetEntry::offset_offset_in_bytes()));
5764   movptr(method_result, Address(recv_klass, scan_temp, Address::times_1));
5765 }
5766 
5767 
5768 // virtual method calling
5769 void MacroAssembler::lookup_virtual_method(Register recv_klass,
5770                                            RegisterOrConstant vtable_index,
5771                                            Register method_result) {
5772   const int base = in_bytes(Klass::vtable_start_offset());
5773   assert(vtableEntry::size() * wordSize == wordSize, "else adjust the scaling in the code below");
5774   Address vtable_entry_addr(recv_klass,
5775                             vtable_index, Address::times_ptr,
5776                             base + vtableEntry::method_offset_in_bytes());
5777   movptr(method_result, vtable_entry_addr);
5778 }
5779 
5780 
5781 void MacroAssembler::check_klass_subtype(Register sub_klass,
5782                            Register super_klass,
5783                            Register temp_reg,
5784                            Label& L_success) {
5785   Label L_failure;
5786   check_klass_subtype_fast_path(sub_klass, super_klass, temp_reg,        &L_success, &L_failure, NULL);
5787   check_klass_subtype_slow_path(sub_klass, super_klass, temp_reg, noreg, &L_success, NULL);
5788   bind(L_failure);
5789 }
5790 
5791 
5792 void MacroAssembler::check_klass_subtype_fast_path(Register sub_klass,
5793                                                    Register super_klass,
5794                                                    Register temp_reg,
5795                                                    Label* L_success,
5796                                                    Label* L_failure,
5797                                                    Label* L_slow_path,
5798                                         RegisterOrConstant super_check_offset) {
5799   assert_different_registers(sub_klass, super_klass, temp_reg);
5800   bool must_load_sco = (super_check_offset.constant_or_zero() == -1);
5801   if (super_check_offset.is_register()) {
5802     assert_different_registers(sub_klass, super_klass,
5803                                super_check_offset.as_register());
5804   } else if (must_load_sco) {
5805     assert(temp_reg != noreg, "supply either a temp or a register offset");
5806   }
5807 
5808   Label L_fallthrough;
5809   int label_nulls = 0;
5810   if (L_success == NULL)   { L_success   = &L_fallthrough; label_nulls++; }
5811   if (L_failure == NULL)   { L_failure   = &L_fallthrough; label_nulls++; }
5812   if (L_slow_path == NULL) { L_slow_path = &L_fallthrough; label_nulls++; }
5813   assert(label_nulls <= 1, "at most one NULL in the batch");
5814 
5815   int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
5816   int sco_offset = in_bytes(Klass::super_check_offset_offset());
5817   Address super_check_offset_addr(super_klass, sco_offset);
5818 
5819   // Hacked jcc, which "knows" that L_fallthrough, at least, is in
5820   // range of a jccb.  If this routine grows larger, reconsider at
5821   // least some of these.
5822 #define local_jcc(assembler_cond, label)                                \
5823   if (&(label) == &L_fallthrough)  jccb(assembler_cond, label);         \
5824   else                             jcc( assembler_cond, label) /*omit semi*/
5825 
5826   // Hacked jmp, which may only be used just before L_fallthrough.
5827 #define final_jmp(label)                                                \
5828   if (&(label) == &L_fallthrough) { /*do nothing*/ }                    \
5829   else                            jmp(label)                /*omit semi*/
5830 
5831   // If the pointers are equal, we are done (e.g., String[] elements).
5832   // This self-check enables sharing of secondary supertype arrays among
5833   // non-primary types such as array-of-interface.  Otherwise, each such
5834   // type would need its own customized SSA.
5835   // We move this check to the front of the fast path because many
5836   // type checks are in fact trivially successful in this manner,
5837   // so we get a nicely predicted branch right at the start of the check.
5838   cmpptr(sub_klass, super_klass);
5839   local_jcc(Assembler::equal, *L_success);
5840 
5841   // Check the supertype display:
5842   if (must_load_sco) {
5843     // Positive movl does right thing on LP64.
5844     movl(temp_reg, super_check_offset_addr);
5845     super_check_offset = RegisterOrConstant(temp_reg);
5846   }
5847   Address super_check_addr(sub_klass, super_check_offset, Address::times_1, 0);
5848   cmpptr(super_klass, super_check_addr); // load displayed supertype
5849 
5850   // This check has worked decisively for primary supers.
5851   // Secondary supers are sought in the super_cache ('super_cache_addr').
5852   // (Secondary supers are interfaces and very deeply nested subtypes.)
5853   // This works in the same check above because of a tricky aliasing
5854   // between the super_cache and the primary super display elements.
5855   // (The 'super_check_addr' can address either, as the case requires.)
5856   // Note that the cache is updated below if it does not help us find
5857   // what we need immediately.
5858   // So if it was a primary super, we can just fail immediately.
5859   // Otherwise, it's the slow path for us (no success at this point).
5860 
5861   if (super_check_offset.is_register()) {
5862     local_jcc(Assembler::equal, *L_success);
5863     cmpl(super_check_offset.as_register(), sc_offset);
5864     if (L_failure == &L_fallthrough) {
5865       local_jcc(Assembler::equal, *L_slow_path);
5866     } else {
5867       local_jcc(Assembler::notEqual, *L_failure);
5868       final_jmp(*L_slow_path);
5869     }
5870   } else if (super_check_offset.as_constant() == sc_offset) {
5871     // Need a slow path; fast failure is impossible.
5872     if (L_slow_path == &L_fallthrough) {
5873       local_jcc(Assembler::equal, *L_success);
5874     } else {
5875       local_jcc(Assembler::notEqual, *L_slow_path);
5876       final_jmp(*L_success);
5877     }
5878   } else {
5879     // No slow path; it's a fast decision.
5880     if (L_failure == &L_fallthrough) {
5881       local_jcc(Assembler::equal, *L_success);
5882     } else {
5883       local_jcc(Assembler::notEqual, *L_failure);
5884       final_jmp(*L_success);
5885     }
5886   }
5887 
5888   bind(L_fallthrough);
5889 
5890 #undef local_jcc
5891 #undef final_jmp
5892 }
5893 
5894 
5895 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass,
5896                                                    Register super_klass,
5897                                                    Register temp_reg,
5898                                                    Register temp2_reg,
5899                                                    Label* L_success,
5900                                                    Label* L_failure,
5901                                                    bool set_cond_codes) {
5902   assert_different_registers(sub_klass, super_klass, temp_reg);
5903   if (temp2_reg != noreg)
5904     assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg);
5905 #define IS_A_TEMP(reg) ((reg) == temp_reg || (reg) == temp2_reg)
5906 
5907   Label L_fallthrough;
5908   int label_nulls = 0;
5909   if (L_success == NULL)   { L_success   = &L_fallthrough; label_nulls++; }
5910   if (L_failure == NULL)   { L_failure   = &L_fallthrough; label_nulls++; }
5911   assert(label_nulls <= 1, "at most one NULL in the batch");
5912 
5913   // a couple of useful fields in sub_klass:
5914   int ss_offset = in_bytes(Klass::secondary_supers_offset());
5915   int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
5916   Address secondary_supers_addr(sub_klass, ss_offset);
5917   Address super_cache_addr(     sub_klass, sc_offset);
5918 
5919   // Do a linear scan of the secondary super-klass chain.
5920   // This code is rarely used, so simplicity is a virtue here.
5921   // The repne_scan instruction uses fixed registers, which we must spill.
5922   // Don't worry too much about pre-existing connections with the input regs.
5923 
5924   assert(sub_klass != rax, "killed reg"); // killed by mov(rax, super)
5925   assert(sub_klass != rcx, "killed reg"); // killed by lea(rcx, &pst_counter)
5926 
5927   // Get super_klass value into rax (even if it was in rdi or rcx).
5928   bool pushed_rax = false, pushed_rcx = false, pushed_rdi = false;
5929   if (super_klass != rax || UseCompressedOops) {
5930     if (!IS_A_TEMP(rax)) { push(rax); pushed_rax = true; }
5931     mov(rax, super_klass);
5932   }
5933   if (!IS_A_TEMP(rcx)) { push(rcx); pushed_rcx = true; }
5934   if (!IS_A_TEMP(rdi)) { push(rdi); pushed_rdi = true; }
5935 
5936 #ifndef PRODUCT
5937   int* pst_counter = &SharedRuntime::_partial_subtype_ctr;
5938   ExternalAddress pst_counter_addr((address) pst_counter);
5939   NOT_LP64(  incrementl(pst_counter_addr) );
5940   LP64_ONLY( lea(rcx, pst_counter_addr) );
5941   LP64_ONLY( incrementl(Address(rcx, 0)) );
5942 #endif //PRODUCT
5943 
5944   // We will consult the secondary-super array.
5945   movptr(rdi, secondary_supers_addr);
5946   // Load the array length.  (Positive movl does right thing on LP64.)
5947   movl(rcx, Address(rdi, Array<Klass*>::length_offset_in_bytes()));
5948   // Skip to start of data.
5949   addptr(rdi, Array<Klass*>::base_offset_in_bytes());
5950 
5951   // Scan RCX words at [RDI] for an occurrence of RAX.
5952   // Set NZ/Z based on last compare.
5953   // Z flag value will not be set by 'repne' if RCX == 0 since 'repne' does
5954   // not change flags (only scas instruction which is repeated sets flags).
5955   // Set Z = 0 (not equal) before 'repne' to indicate that class was not found.
5956 
5957     testptr(rax,rax); // Set Z = 0
5958     repne_scan();
5959 
5960   // Unspill the temp. registers:
5961   if (pushed_rdi)  pop(rdi);
5962   if (pushed_rcx)  pop(rcx);
5963   if (pushed_rax)  pop(rax);
5964 
5965   if (set_cond_codes) {
5966     // Special hack for the AD files:  rdi is guaranteed non-zero.
5967     assert(!pushed_rdi, "rdi must be left non-NULL");
5968     // Also, the condition codes are properly set Z/NZ on succeed/failure.
5969   }
5970 
5971   if (L_failure == &L_fallthrough)
5972         jccb(Assembler::notEqual, *L_failure);
5973   else  jcc(Assembler::notEqual, *L_failure);
5974 
5975   // Success.  Cache the super we found and proceed in triumph.
5976   movptr(super_cache_addr, super_klass);
5977 
5978   if (L_success != &L_fallthrough) {
5979     jmp(*L_success);
5980   }
5981 
5982 #undef IS_A_TEMP
5983 
5984   bind(L_fallthrough);
5985 }
5986 
5987 
5988 void MacroAssembler::cmov32(Condition cc, Register dst, Address src) {
5989   if (VM_Version::supports_cmov()) {
5990     cmovl(cc, dst, src);
5991   } else {
5992     Label L;
5993     jccb(negate_condition(cc), L);
5994     movl(dst, src);
5995     bind(L);
5996   }
5997 }
5998 
5999 void MacroAssembler::cmov32(Condition cc, Register dst, Register src) {
6000   if (VM_Version::supports_cmov()) {
6001     cmovl(cc, dst, src);
6002   } else {
6003     Label L;
6004     jccb(negate_condition(cc), L);
6005     movl(dst, src);
6006     bind(L);
6007   }
6008 }
6009 
6010 void MacroAssembler::verify_oop(Register reg, const char* s) {
6011   if (!VerifyOops) return;
6012 
6013   // Pass register number to verify_oop_subroutine
6014   const char* b = NULL;
6015   {
6016     ResourceMark rm;
6017     stringStream ss;
6018     ss.print("verify_oop: %s: %s", reg->name(), s);
6019     b = code_string(ss.as_string());
6020   }
6021   BLOCK_COMMENT("verify_oop {");
6022 #ifdef _LP64
6023   push(rscratch1);                    // save r10, trashed by movptr()
6024 #endif
6025   push(rax);                          // save rax,
6026   push(reg);                          // pass register argument
6027   ExternalAddress buffer((address) b);
6028   // avoid using pushptr, as it modifies scratch registers
6029   // and our contract is not to modify anything
6030   movptr(rax, buffer.addr());
6031   push(rax);
6032   // call indirectly to solve generation ordering problem
6033   movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
6034   call(rax);
6035   // Caller pops the arguments (oop, message) and restores rax, r10
6036   BLOCK_COMMENT("} verify_oop");
6037 }
6038 
6039 
6040 RegisterOrConstant MacroAssembler::delayed_value_impl(intptr_t* delayed_value_addr,
6041                                                       Register tmp,
6042                                                       int offset) {
6043   intptr_t value = *delayed_value_addr;
6044   if (value != 0)
6045     return RegisterOrConstant(value + offset);
6046 
6047   // load indirectly to solve generation ordering problem
6048   movptr(tmp, ExternalAddress((address) delayed_value_addr));
6049 
6050 #ifdef ASSERT
6051   { Label L;
6052     testptr(tmp, tmp);
6053     if (WizardMode) {
6054       const char* buf = NULL;
6055       {
6056         ResourceMark rm;
6057         stringStream ss;
6058         ss.print("DelayedValue=" INTPTR_FORMAT, delayed_value_addr[1]);
6059         buf = code_string(ss.as_string());
6060       }
6061       jcc(Assembler::notZero, L);
6062       STOP(buf);
6063     } else {
6064       jccb(Assembler::notZero, L);
6065       hlt();
6066     }
6067     bind(L);
6068   }
6069 #endif
6070 
6071   if (offset != 0)
6072     addptr(tmp, offset);
6073 
6074   return RegisterOrConstant(tmp);
6075 }
6076 
6077 
6078 Address MacroAssembler::argument_address(RegisterOrConstant arg_slot,
6079                                          int extra_slot_offset) {
6080   // cf. TemplateTable::prepare_invoke(), if (load_receiver).
6081   int stackElementSize = Interpreter::stackElementSize;
6082   int offset = Interpreter::expr_offset_in_bytes(extra_slot_offset+0);
6083 #ifdef ASSERT
6084   int offset1 = Interpreter::expr_offset_in_bytes(extra_slot_offset+1);
6085   assert(offset1 - offset == stackElementSize, "correct arithmetic");
6086 #endif
6087   Register             scale_reg    = noreg;
6088   Address::ScaleFactor scale_factor = Address::no_scale;
6089   if (arg_slot.is_constant()) {
6090     offset += arg_slot.as_constant() * stackElementSize;
6091   } else {
6092     scale_reg    = arg_slot.as_register();
6093     scale_factor = Address::times(stackElementSize);
6094   }
6095   offset += wordSize;           // return PC is on stack
6096   return Address(rsp, scale_reg, scale_factor, offset);
6097 }
6098 
6099 
6100 void MacroAssembler::verify_oop_addr(Address addr, const char* s) {
6101   if (!VerifyOops) return;
6102 
6103   // Address adjust(addr.base(), addr.index(), addr.scale(), addr.disp() + BytesPerWord);
6104   // Pass register number to verify_oop_subroutine
6105   const char* b = NULL;
6106   {
6107     ResourceMark rm;
6108     stringStream ss;
6109     ss.print("verify_oop_addr: %s", s);
6110     b = code_string(ss.as_string());
6111   }
6112 #ifdef _LP64
6113   push(rscratch1);                    // save r10, trashed by movptr()
6114 #endif
6115   push(rax);                          // save rax,
6116   // addr may contain rsp so we will have to adjust it based on the push
6117   // we just did (and on 64 bit we do two pushes)
6118   // NOTE: 64bit seemed to have had a bug in that it did movq(addr, rax); which
6119   // stores rax into addr which is backwards of what was intended.
6120   if (addr.uses(rsp)) {
6121     lea(rax, addr);
6122     pushptr(Address(rax, LP64_ONLY(2 *) BytesPerWord));
6123   } else {
6124     pushptr(addr);
6125   }
6126 
6127   ExternalAddress buffer((address) b);
6128   // pass msg argument
6129   // avoid using pushptr, as it modifies scratch registers
6130   // and our contract is not to modify anything
6131   movptr(rax, buffer.addr());
6132   push(rax);
6133 
6134   // call indirectly to solve generation ordering problem
6135   movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
6136   call(rax);
6137   // Caller pops the arguments (addr, message) and restores rax, r10.
6138 }
6139 
6140 void MacroAssembler::verify_tlab() {
6141 #ifdef ASSERT
6142   if (UseTLAB && VerifyOops) {
6143     Label next, ok;
6144     Register t1 = rsi;
6145     Register thread_reg = NOT_LP64(rbx) LP64_ONLY(r15_thread);
6146 
6147     push(t1);
6148     NOT_LP64(push(thread_reg));
6149     NOT_LP64(get_thread(thread_reg));
6150 
6151     movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
6152     cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())));
6153     jcc(Assembler::aboveEqual, next);
6154     STOP("assert(top >= start)");
6155     should_not_reach_here();
6156 
6157     bind(next);
6158     movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())));
6159     cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
6160     jcc(Assembler::aboveEqual, ok);
6161     STOP("assert(top <= end)");
6162     should_not_reach_here();
6163 
6164     bind(ok);
6165     NOT_LP64(pop(thread_reg));
6166     pop(t1);
6167   }
6168 #endif
6169 }
6170 
6171 class ControlWord {
6172  public:
6173   int32_t _value;
6174 
6175   int  rounding_control() const        { return  (_value >> 10) & 3      ; }
6176   int  precision_control() const       { return  (_value >>  8) & 3      ; }
6177   bool precision() const               { return ((_value >>  5) & 1) != 0; }
6178   bool underflow() const               { return ((_value >>  4) & 1) != 0; }
6179   bool overflow() const                { return ((_value >>  3) & 1) != 0; }
6180   bool zero_divide() const             { return ((_value >>  2) & 1) != 0; }
6181   bool denormalized() const            { return ((_value >>  1) & 1) != 0; }
6182   bool invalid() const                 { return ((_value >>  0) & 1) != 0; }
6183 
6184   void print() const {
6185     // rounding control
6186     const char* rc;
6187     switch (rounding_control()) {
6188       case 0: rc = "round near"; break;
6189       case 1: rc = "round down"; break;
6190       case 2: rc = "round up  "; break;
6191       case 3: rc = "chop      "; break;
6192     };
6193     // precision control
6194     const char* pc;
6195     switch (precision_control()) {
6196       case 0: pc = "24 bits "; break;
6197       case 1: pc = "reserved"; break;
6198       case 2: pc = "53 bits "; break;
6199       case 3: pc = "64 bits "; break;
6200     };
6201     // flags
6202     char f[9];
6203     f[0] = ' ';
6204     f[1] = ' ';
6205     f[2] = (precision   ()) ? 'P' : 'p';
6206     f[3] = (underflow   ()) ? 'U' : 'u';
6207     f[4] = (overflow    ()) ? 'O' : 'o';
6208     f[5] = (zero_divide ()) ? 'Z' : 'z';
6209     f[6] = (denormalized()) ? 'D' : 'd';
6210     f[7] = (invalid     ()) ? 'I' : 'i';
6211     f[8] = '\x0';
6212     // output
6213     printf("%04x  masks = %s, %s, %s", _value & 0xFFFF, f, rc, pc);
6214   }
6215 
6216 };
6217 
6218 class StatusWord {
6219  public:
6220   int32_t _value;
6221 
6222   bool busy() const                    { return ((_value >> 15) & 1) != 0; }
6223   bool C3() const                      { return ((_value >> 14) & 1) != 0; }
6224   bool C2() const                      { return ((_value >> 10) & 1) != 0; }
6225   bool C1() const                      { return ((_value >>  9) & 1) != 0; }
6226   bool C0() const                      { return ((_value >>  8) & 1) != 0; }
6227   int  top() const                     { return  (_value >> 11) & 7      ; }
6228   bool error_status() const            { return ((_value >>  7) & 1) != 0; }
6229   bool stack_fault() const             { return ((_value >>  6) & 1) != 0; }
6230   bool precision() const               { return ((_value >>  5) & 1) != 0; }
6231   bool underflow() const               { return ((_value >>  4) & 1) != 0; }
6232   bool overflow() const                { return ((_value >>  3) & 1) != 0; }
6233   bool zero_divide() const             { return ((_value >>  2) & 1) != 0; }
6234   bool denormalized() const            { return ((_value >>  1) & 1) != 0; }
6235   bool invalid() const                 { return ((_value >>  0) & 1) != 0; }
6236 
6237   void print() const {
6238     // condition codes
6239     char c[5];
6240     c[0] = (C3()) ? '3' : '-';
6241     c[1] = (C2()) ? '2' : '-';
6242     c[2] = (C1()) ? '1' : '-';
6243     c[3] = (C0()) ? '0' : '-';
6244     c[4] = '\x0';
6245     // flags
6246     char f[9];
6247     f[0] = (error_status()) ? 'E' : '-';
6248     f[1] = (stack_fault ()) ? 'S' : '-';
6249     f[2] = (precision   ()) ? 'P' : '-';
6250     f[3] = (underflow   ()) ? 'U' : '-';
6251     f[4] = (overflow    ()) ? 'O' : '-';
6252     f[5] = (zero_divide ()) ? 'Z' : '-';
6253     f[6] = (denormalized()) ? 'D' : '-';
6254     f[7] = (invalid     ()) ? 'I' : '-';
6255     f[8] = '\x0';
6256     // output
6257     printf("%04x  flags = %s, cc =  %s, top = %d", _value & 0xFFFF, f, c, top());
6258   }
6259 
6260 };
6261 
6262 class TagWord {
6263  public:
6264   int32_t _value;
6265 
6266   int tag_at(int i) const              { return (_value >> (i*2)) & 3; }
6267 
6268   void print() const {
6269     printf("%04x", _value & 0xFFFF);
6270   }
6271 
6272 };
6273 
6274 class FPU_Register {
6275  public:
6276   int32_t _m0;
6277   int32_t _m1;
6278   int16_t _ex;
6279 
6280   bool is_indefinite() const           {
6281     return _ex == -1 && _m1 == (int32_t)0xC0000000 && _m0 == 0;
6282   }
6283 
6284   void print() const {
6285     char  sign = (_ex < 0) ? '-' : '+';
6286     const char* kind = (_ex == 0x7FFF || _ex == (int16_t)-1) ? "NaN" : "   ";
6287     printf("%c%04hx.%08x%08x  %s", sign, _ex, _m1, _m0, kind);
6288   };
6289 
6290 };
6291 
6292 class FPU_State {
6293  public:
6294   enum {
6295     register_size       = 10,
6296     number_of_registers =  8,
6297     register_mask       =  7
6298   };
6299 
6300   ControlWord  _control_word;
6301   StatusWord   _status_word;
6302   TagWord      _tag_word;
6303   int32_t      _error_offset;
6304   int32_t      _error_selector;
6305   int32_t      _data_offset;
6306   int32_t      _data_selector;
6307   int8_t       _register[register_size * number_of_registers];
6308 
6309   int tag_for_st(int i) const          { return _tag_word.tag_at((_status_word.top() + i) & register_mask); }
6310   FPU_Register* st(int i) const        { return (FPU_Register*)&_register[register_size * i]; }
6311 
6312   const char* tag_as_string(int tag) const {
6313     switch (tag) {
6314       case 0: return "valid";
6315       case 1: return "zero";
6316       case 2: return "special";
6317       case 3: return "empty";
6318     }
6319     ShouldNotReachHere();
6320     return NULL;
6321   }
6322 
6323   void print() const {
6324     // print computation registers
6325     { int t = _status_word.top();
6326       for (int i = 0; i < number_of_registers; i++) {
6327         int j = (i - t) & register_mask;
6328         printf("%c r%d = ST%d = ", (j == 0 ? '*' : ' '), i, j);
6329         st(j)->print();
6330         printf(" %s\n", tag_as_string(_tag_word.tag_at(i)));
6331       }
6332     }
6333     printf("\n");
6334     // print control registers
6335     printf("ctrl = "); _control_word.print(); printf("\n");
6336     printf("stat = "); _status_word .print(); printf("\n");
6337     printf("tags = "); _tag_word    .print(); printf("\n");
6338   }
6339 
6340 };
6341 
6342 class Flag_Register {
6343  public:
6344   int32_t _value;
6345 
6346   bool overflow() const                { return ((_value >> 11) & 1) != 0; }
6347   bool direction() const               { return ((_value >> 10) & 1) != 0; }
6348   bool sign() const                    { return ((_value >>  7) & 1) != 0; }
6349   bool zero() const                    { return ((_value >>  6) & 1) != 0; }
6350   bool auxiliary_carry() const         { return ((_value >>  4) & 1) != 0; }
6351   bool parity() const                  { return ((_value >>  2) & 1) != 0; }
6352   bool carry() const                   { return ((_value >>  0) & 1) != 0; }
6353 
6354   void print() const {
6355     // flags
6356     char f[8];
6357     f[0] = (overflow       ()) ? 'O' : '-';
6358     f[1] = (direction      ()) ? 'D' : '-';
6359     f[2] = (sign           ()) ? 'S' : '-';
6360     f[3] = (zero           ()) ? 'Z' : '-';
6361     f[4] = (auxiliary_carry()) ? 'A' : '-';
6362     f[5] = (parity         ()) ? 'P' : '-';
6363     f[6] = (carry          ()) ? 'C' : '-';
6364     f[7] = '\x0';
6365     // output
6366     printf("%08x  flags = %s", _value, f);
6367   }
6368 
6369 };
6370 
6371 class IU_Register {
6372  public:
6373   int32_t _value;
6374 
6375   void print() const {
6376     printf("%08x  %11d", _value, _value);
6377   }
6378 
6379 };
6380 
6381 class IU_State {
6382  public:
6383   Flag_Register _eflags;
6384   IU_Register   _rdi;
6385   IU_Register   _rsi;
6386   IU_Register   _rbp;
6387   IU_Register   _rsp;
6388   IU_Register   _rbx;
6389   IU_Register   _rdx;
6390   IU_Register   _rcx;
6391   IU_Register   _rax;
6392 
6393   void print() const {
6394     // computation registers
6395     printf("rax,  = "); _rax.print(); printf("\n");
6396     printf("rbx,  = "); _rbx.print(); printf("\n");
6397     printf("rcx  = "); _rcx.print(); printf("\n");
6398     printf("rdx  = "); _rdx.print(); printf("\n");
6399     printf("rdi  = "); _rdi.print(); printf("\n");
6400     printf("rsi  = "); _rsi.print(); printf("\n");
6401     printf("rbp,  = "); _rbp.print(); printf("\n");
6402     printf("rsp  = "); _rsp.print(); printf("\n");
6403     printf("\n");
6404     // control registers
6405     printf("flgs = "); _eflags.print(); printf("\n");
6406   }
6407 };
6408 
6409 
6410 class CPU_State {
6411  public:
6412   FPU_State _fpu_state;
6413   IU_State  _iu_state;
6414 
6415   void print() const {
6416     printf("--------------------------------------------------\n");
6417     _iu_state .print();
6418     printf("\n");
6419     _fpu_state.print();
6420     printf("--------------------------------------------------\n");
6421   }
6422 
6423 };
6424 
6425 
6426 static void _print_CPU_state(CPU_State* state) {
6427   state->print();
6428 };
6429 
6430 
6431 void MacroAssembler::print_CPU_state() {
6432   push_CPU_state();
6433   push(rsp);                // pass CPU state
6434   call(RuntimeAddress(CAST_FROM_FN_PTR(address, _print_CPU_state)));
6435   addptr(rsp, wordSize);       // discard argument
6436   pop_CPU_state();
6437 }
6438 
6439 
6440 static bool _verify_FPU(int stack_depth, char* s, CPU_State* state) {
6441   static int counter = 0;
6442   FPU_State* fs = &state->_fpu_state;
6443   counter++;
6444   // For leaf calls, only verify that the top few elements remain empty.
6445   // We only need 1 empty at the top for C2 code.
6446   if( stack_depth < 0 ) {
6447     if( fs->tag_for_st(7) != 3 ) {
6448       printf("FPR7 not empty\n");
6449       state->print();
6450       assert(false, "error");
6451       return false;
6452     }
6453     return true;                // All other stack states do not matter
6454   }
6455 
6456   assert((fs->_control_word._value & 0xffff) == StubRoutines::_fpu_cntrl_wrd_std,
6457          "bad FPU control word");
6458 
6459   // compute stack depth
6460   int i = 0;
6461   while (i < FPU_State::number_of_registers && fs->tag_for_st(i)  < 3) i++;
6462   int d = i;
6463   while (i < FPU_State::number_of_registers && fs->tag_for_st(i) == 3) i++;
6464   // verify findings
6465   if (i != FPU_State::number_of_registers) {
6466     // stack not contiguous
6467     printf("%s: stack not contiguous at ST%d\n", s, i);
6468     state->print();
6469     assert(false, "error");
6470     return false;
6471   }
6472   // check if computed stack depth corresponds to expected stack depth
6473   if (stack_depth < 0) {
6474     // expected stack depth is -stack_depth or less
6475     if (d > -stack_depth) {
6476       // too many elements on the stack
6477       printf("%s: <= %d stack elements expected but found %d\n", s, -stack_depth, d);
6478       state->print();
6479       assert(false, "error");
6480       return false;
6481     }
6482   } else {
6483     // expected stack depth is stack_depth
6484     if (d != stack_depth) {
6485       // wrong stack depth
6486       printf("%s: %d stack elements expected but found %d\n", s, stack_depth, d);
6487       state->print();
6488       assert(false, "error");
6489       return false;
6490     }
6491   }
6492   // everything is cool
6493   return true;
6494 }
6495 
6496 
6497 void MacroAssembler::verify_FPU(int stack_depth, const char* s) {
6498   if (!VerifyFPU) return;
6499   push_CPU_state();
6500   push(rsp);                // pass CPU state
6501   ExternalAddress msg((address) s);
6502   // pass message string s
6503   pushptr(msg.addr());
6504   push(stack_depth);        // pass stack depth
6505   call(RuntimeAddress(CAST_FROM_FN_PTR(address, _verify_FPU)));
6506   addptr(rsp, 3 * wordSize);   // discard arguments
6507   // check for error
6508   { Label L;
6509     testl(rax, rax);
6510     jcc(Assembler::notZero, L);
6511     int3();                  // break if error condition
6512     bind(L);
6513   }
6514   pop_CPU_state();
6515 }
6516 
6517 void MacroAssembler::restore_cpu_control_state_after_jni() {
6518   // Either restore the MXCSR register after returning from the JNI Call
6519   // or verify that it wasn't changed (with -Xcheck:jni flag).
6520   if (VM_Version::supports_sse()) {
6521     if (RestoreMXCSROnJNICalls) {
6522       ldmxcsr(ExternalAddress(StubRoutines::addr_mxcsr_std()));
6523     } else if (CheckJNICalls) {
6524       call(RuntimeAddress(StubRoutines::x86::verify_mxcsr_entry()));
6525     }
6526   }
6527   if (VM_Version::supports_avx()) {
6528     // Clear upper bits of YMM registers to avoid SSE <-> AVX transition penalty.
6529     vzeroupper();
6530   }
6531 
6532 #ifndef _LP64
6533   // Either restore the x87 floating pointer control word after returning
6534   // from the JNI call or verify that it wasn't changed.
6535   if (CheckJNICalls) {
6536     call(RuntimeAddress(StubRoutines::x86::verify_fpu_cntrl_wrd_entry()));
6537   }
6538 #endif // _LP64
6539 }
6540 
6541 void MacroAssembler::load_mirror(Register mirror, Register method) {
6542   // get mirror
6543   const int mirror_offset = in_bytes(Klass::java_mirror_offset());
6544   movptr(mirror, Address(method, Method::const_offset()));
6545   movptr(mirror, Address(mirror, ConstMethod::constants_offset()));
6546   movptr(mirror, Address(mirror, ConstantPool::pool_holder_offset_in_bytes()));
6547   movptr(mirror, Address(mirror, mirror_offset));
6548 }
6549 
6550 void MacroAssembler::load_klass(Register dst, Register src) {
6551 #ifdef _LP64
6552   if (UseCompressedClassPointers) {
6553     movl(dst, Address(src, oopDesc::klass_offset_in_bytes()));
6554     decode_klass_not_null(dst);
6555   } else
6556 #endif
6557     movptr(dst, Address(src, oopDesc::klass_offset_in_bytes()));
6558 }
6559 
6560 void MacroAssembler::load_prototype_header(Register dst, Register src) {
6561   load_klass(dst, src);
6562   movptr(dst, Address(dst, Klass::prototype_header_offset()));
6563 }
6564 
6565 void MacroAssembler::store_klass(Register dst, Register src) {
6566 #ifdef _LP64
6567   if (UseCompressedClassPointers) {
6568     encode_klass_not_null(src);
6569     movl(Address(dst, oopDesc::klass_offset_in_bytes()), src);
6570   } else
6571 #endif
6572     movptr(Address(dst, oopDesc::klass_offset_in_bytes()), src);
6573 }
6574 
6575 void MacroAssembler::load_heap_oop(Register dst, Address src) {
6576 #ifdef _LP64
6577   // FIXME: Must change all places where we try to load the klass.
6578   if (UseCompressedOops) {
6579     movl(dst, src);
6580     decode_heap_oop(dst);
6581   } else
6582 #endif
6583     movptr(dst, src);
6584 }
6585 
6586 // Doesn't do verfication, generates fixed size code
6587 void MacroAssembler::load_heap_oop_not_null(Register dst, Address src) {
6588 #ifdef _LP64
6589   if (UseCompressedOops) {
6590     movl(dst, src);
6591     decode_heap_oop_not_null(dst);
6592   } else
6593 #endif
6594     movptr(dst, src);
6595 }
6596 
6597 void MacroAssembler::store_heap_oop(Address dst, Register src) {
6598 #ifdef _LP64
6599   if (UseCompressedOops) {
6600     assert(!dst.uses(src), "not enough registers");
6601     encode_heap_oop(src);
6602     movl(dst, src);
6603   } else
6604 #endif
6605     movptr(dst, src);
6606 }
6607 
6608 void MacroAssembler::cmp_heap_oop(Register src1, Address src2, Register tmp) {
6609   assert_different_registers(src1, tmp);
6610 #ifdef _LP64
6611   if (UseCompressedOops) {
6612     bool did_push = false;
6613     if (tmp == noreg) {
6614       tmp = rax;
6615       push(tmp);
6616       did_push = true;
6617       assert(!src2.uses(rsp), "can't push");
6618     }
6619     load_heap_oop(tmp, src2);
6620     cmpptr(src1, tmp);
6621     if (did_push)  pop(tmp);
6622   } else
6623 #endif
6624     cmpptr(src1, src2);
6625 }
6626 
6627 // Used for storing NULLs.
6628 void MacroAssembler::store_heap_oop_null(Address dst) {
6629 #ifdef _LP64
6630   if (UseCompressedOops) {
6631     movl(dst, (int32_t)NULL_WORD);
6632   } else {
6633     movslq(dst, (int32_t)NULL_WORD);
6634   }
6635 #else
6636   movl(dst, (int32_t)NULL_WORD);
6637 #endif
6638 }
6639 
6640 #ifdef _LP64
6641 void MacroAssembler::store_klass_gap(Register dst, Register src) {
6642   if (UseCompressedClassPointers) {
6643     // Store to klass gap in destination
6644     movl(Address(dst, oopDesc::klass_gap_offset_in_bytes()), src);
6645   }
6646 }
6647 
6648 #ifdef ASSERT
6649 void MacroAssembler::verify_heapbase(const char* msg) {
6650   assert (UseCompressedOops, "should be compressed");
6651   assert (GC::gc()->heap() != NULL, "java heap should be initialized");
6652   if (CheckCompressedOops) {
6653     Label ok;
6654     push(rscratch1); // cmpptr trashes rscratch1
6655     cmpptr(r12_heapbase, ExternalAddress((address)Universe::narrow_ptrs_base_addr()));
6656     jcc(Assembler::equal, ok);
6657     STOP(msg);
6658     bind(ok);
6659     pop(rscratch1);
6660   }
6661 }
6662 #endif
6663 
6664 // Algorithm must match oop.inline.hpp encode_heap_oop.
6665 void MacroAssembler::encode_heap_oop(Register r) {
6666 #ifdef ASSERT
6667   verify_heapbase("MacroAssembler::encode_heap_oop: heap base corrupted?");
6668 #endif
6669   verify_oop(r, "broken oop in encode_heap_oop");
6670   if (Universe::narrow_oop_base() == NULL) {
6671     if (Universe::narrow_oop_shift() != 0) {
6672       assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
6673       shrq(r, LogMinObjAlignmentInBytes);
6674     }
6675     return;
6676   }
6677   testq(r, r);
6678   cmovq(Assembler::equal, r, r12_heapbase);
6679   subq(r, r12_heapbase);
6680   shrq(r, LogMinObjAlignmentInBytes);
6681 }
6682 
6683 void MacroAssembler::encode_heap_oop_not_null(Register r) {
6684 #ifdef ASSERT
6685   verify_heapbase("MacroAssembler::encode_heap_oop_not_null: heap base corrupted?");
6686   if (CheckCompressedOops) {
6687     Label ok;
6688     testq(r, r);
6689     jcc(Assembler::notEqual, ok);
6690     STOP("null oop passed to encode_heap_oop_not_null");
6691     bind(ok);
6692   }
6693 #endif
6694   verify_oop(r, "broken oop in encode_heap_oop_not_null");
6695   if (Universe::narrow_oop_base() != NULL) {
6696     subq(r, r12_heapbase);
6697   }
6698   if (Universe::narrow_oop_shift() != 0) {
6699     assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
6700     shrq(r, LogMinObjAlignmentInBytes);
6701   }
6702 }
6703 
6704 void MacroAssembler::encode_heap_oop_not_null(Register dst, Register src) {
6705 #ifdef ASSERT
6706   verify_heapbase("MacroAssembler::encode_heap_oop_not_null2: heap base corrupted?");
6707   if (CheckCompressedOops) {
6708     Label ok;
6709     testq(src, src);
6710     jcc(Assembler::notEqual, ok);
6711     STOP("null oop passed to encode_heap_oop_not_null2");
6712     bind(ok);
6713   }
6714 #endif
6715   verify_oop(src, "broken oop in encode_heap_oop_not_null2");
6716   if (dst != src) {
6717     movq(dst, src);
6718   }
6719   if (Universe::narrow_oop_base() != NULL) {
6720     subq(dst, r12_heapbase);
6721   }
6722   if (Universe::narrow_oop_shift() != 0) {
6723     assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
6724     shrq(dst, LogMinObjAlignmentInBytes);
6725   }
6726 }
6727 
6728 void  MacroAssembler::decode_heap_oop(Register r) {
6729 #ifdef ASSERT
6730   verify_heapbase("MacroAssembler::decode_heap_oop: heap base corrupted?");
6731 #endif
6732   if (Universe::narrow_oop_base() == NULL) {
6733     if (Universe::narrow_oop_shift() != 0) {
6734       assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
6735       shlq(r, LogMinObjAlignmentInBytes);
6736     }
6737   } else {
6738     Label done;
6739     shlq(r, LogMinObjAlignmentInBytes);
6740     jccb(Assembler::equal, done);
6741     addq(r, r12_heapbase);
6742     bind(done);
6743   }
6744   verify_oop(r, "broken oop in decode_heap_oop");
6745 }
6746 
6747 void  MacroAssembler::decode_heap_oop_not_null(Register r) {
6748   // Note: it will change flags
6749   assert (UseCompressedOops, "should only be used for compressed headers");
6750   assert (GC::gc()->heap() != NULL, "java heap should be initialized");
6751   // Cannot assert, unverified entry point counts instructions (see .ad file)
6752   // vtableStubs also counts instructions in pd_code_size_limit.
6753   // Also do not verify_oop as this is called by verify_oop.
6754   if (Universe::narrow_oop_shift() != 0) {
6755     assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
6756     shlq(r, LogMinObjAlignmentInBytes);
6757     if (Universe::narrow_oop_base() != NULL) {
6758       addq(r, r12_heapbase);
6759     }
6760   } else {
6761     assert (Universe::narrow_oop_base() == NULL, "sanity");
6762   }
6763 }
6764 
6765 void  MacroAssembler::decode_heap_oop_not_null(Register dst, Register src) {
6766   // Note: it will change flags
6767   assert (UseCompressedOops, "should only be used for compressed headers");
6768   assert (GC::gc()->heap() != NULL, "java heap should be initialized");
6769   // Cannot assert, unverified entry point counts instructions (see .ad file)
6770   // vtableStubs also counts instructions in pd_code_size_limit.
6771   // Also do not verify_oop as this is called by verify_oop.
6772   if (Universe::narrow_oop_shift() != 0) {
6773     assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
6774     if (LogMinObjAlignmentInBytes == Address::times_8) {
6775       leaq(dst, Address(r12_heapbase, src, Address::times_8, 0));
6776     } else {
6777       if (dst != src) {
6778         movq(dst, src);
6779       }
6780       shlq(dst, LogMinObjAlignmentInBytes);
6781       if (Universe::narrow_oop_base() != NULL) {
6782         addq(dst, r12_heapbase);
6783       }
6784     }
6785   } else {
6786     assert (Universe::narrow_oop_base() == NULL, "sanity");
6787     if (dst != src) {
6788       movq(dst, src);
6789     }
6790   }
6791 }
6792 
6793 void MacroAssembler::encode_klass_not_null(Register r) {
6794   if (Universe::narrow_klass_base() != NULL) {
6795     // Use r12 as a scratch register in which to temporarily load the narrow_klass_base.
6796     assert(r != r12_heapbase, "Encoding a klass in r12");
6797     mov64(r12_heapbase, (int64_t)Universe::narrow_klass_base());
6798     subq(r, r12_heapbase);
6799   }
6800   if (Universe::narrow_klass_shift() != 0) {
6801     assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
6802     shrq(r, LogKlassAlignmentInBytes);
6803   }
6804   if (Universe::narrow_klass_base() != NULL) {
6805     reinit_heapbase();
6806   }
6807 }
6808 
6809 void MacroAssembler::encode_klass_not_null(Register dst, Register src) {
6810   if (dst == src) {
6811     encode_klass_not_null(src);
6812   } else {
6813     if (Universe::narrow_klass_base() != NULL) {
6814       mov64(dst, (int64_t)Universe::narrow_klass_base());
6815       negq(dst);
6816       addq(dst, src);
6817     } else {
6818       movptr(dst, src);
6819     }
6820     if (Universe::narrow_klass_shift() != 0) {
6821       assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
6822       shrq(dst, LogKlassAlignmentInBytes);
6823     }
6824   }
6825 }
6826 
6827 // Function instr_size_for_decode_klass_not_null() counts the instructions
6828 // generated by decode_klass_not_null(register r) and reinit_heapbase(),
6829 // when (GC::gc()->heap() != NULL).  Hence, if the instructions they
6830 // generate change, then this method needs to be updated.
6831 int MacroAssembler::instr_size_for_decode_klass_not_null() {
6832   assert (UseCompressedClassPointers, "only for compressed klass ptrs");
6833   if (Universe::narrow_klass_base() != NULL) {
6834     // mov64 + addq + shlq? + mov64  (for reinit_heapbase()).
6835     return (Universe::narrow_klass_shift() == 0 ? 20 : 24);
6836   } else {
6837     // longest load decode klass function, mov64, leaq
6838     return 16;
6839   }
6840 }
6841 
6842 // !!! If the instructions that get generated here change then function
6843 // instr_size_for_decode_klass_not_null() needs to get updated.
6844 void  MacroAssembler::decode_klass_not_null(Register r) {
6845   // Note: it will change flags
6846   assert (UseCompressedClassPointers, "should only be used for compressed headers");
6847   assert(r != r12_heapbase, "Decoding a klass in r12");
6848   // Cannot assert, unverified entry point counts instructions (see .ad file)
6849   // vtableStubs also counts instructions in pd_code_size_limit.
6850   // Also do not verify_oop as this is called by verify_oop.
6851   if (Universe::narrow_klass_shift() != 0) {
6852     assert(LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
6853     shlq(r, LogKlassAlignmentInBytes);
6854   }
6855   // Use r12 as a scratch register in which to temporarily load the narrow_klass_base.
6856   if (Universe::narrow_klass_base() != NULL) {
6857     mov64(r12_heapbase, (int64_t)Universe::narrow_klass_base());
6858     addq(r, r12_heapbase);
6859     reinit_heapbase();
6860   }
6861 }
6862 
6863 void  MacroAssembler::decode_klass_not_null(Register dst, Register src) {
6864   // Note: it will change flags
6865   assert (UseCompressedClassPointers, "should only be used for compressed headers");
6866   if (dst == src) {
6867     decode_klass_not_null(dst);
6868   } else {
6869     // Cannot assert, unverified entry point counts instructions (see .ad file)
6870     // vtableStubs also counts instructions in pd_code_size_limit.
6871     // Also do not verify_oop as this is called by verify_oop.
6872     mov64(dst, (int64_t)Universe::narrow_klass_base());
6873     if (Universe::narrow_klass_shift() != 0) {
6874       assert(LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
6875       assert(LogKlassAlignmentInBytes == Address::times_8, "klass not aligned on 64bits?");
6876       leaq(dst, Address(dst, src, Address::times_8, 0));
6877     } else {
6878       addq(dst, src);
6879     }
6880   }
6881 }
6882 
6883 void  MacroAssembler::set_narrow_oop(Register dst, jobject obj) {
6884   assert (UseCompressedOops, "should only be used for compressed headers");
6885   assert (GC::gc()->heap() != NULL, "java heap should be initialized");
6886   assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6887   int oop_index = oop_recorder()->find_index(obj);
6888   RelocationHolder rspec = oop_Relocation::spec(oop_index);
6889   mov_narrow_oop(dst, oop_index, rspec);
6890 }
6891 
6892 void  MacroAssembler::set_narrow_oop(Address dst, jobject obj) {
6893   assert (UseCompressedOops, "should only be used for compressed headers");
6894   assert (GC::gc()->heap() != NULL, "java heap should be initialized");
6895   assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6896   int oop_index = oop_recorder()->find_index(obj);
6897   RelocationHolder rspec = oop_Relocation::spec(oop_index);
6898   mov_narrow_oop(dst, oop_index, rspec);
6899 }
6900 
6901 void  MacroAssembler::set_narrow_klass(Register dst, Klass* k) {
6902   assert (UseCompressedClassPointers, "should only be used for compressed headers");
6903   assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6904   int klass_index = oop_recorder()->find_index(k);
6905   RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6906   mov_narrow_oop(dst, Klass::encode_klass(k), rspec);
6907 }
6908 
6909 void  MacroAssembler::set_narrow_klass(Address dst, Klass* k) {
6910   assert (UseCompressedClassPointers, "should only be used for compressed headers");
6911   assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6912   int klass_index = oop_recorder()->find_index(k);
6913   RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6914   mov_narrow_oop(dst, Klass::encode_klass(k), rspec);
6915 }
6916 
6917 void  MacroAssembler::cmp_narrow_oop(Register dst, jobject obj) {
6918   assert (UseCompressedOops, "should only be used for compressed headers");
6919   assert (GC::gc()->heap() != NULL, "java heap should be initialized");
6920   assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6921   int oop_index = oop_recorder()->find_index(obj);
6922   RelocationHolder rspec = oop_Relocation::spec(oop_index);
6923   Assembler::cmp_narrow_oop(dst, oop_index, rspec);
6924 }
6925 
6926 void  MacroAssembler::cmp_narrow_oop(Address dst, jobject obj) {
6927   assert (UseCompressedOops, "should only be used for compressed headers");
6928   assert (GC::gc()->heap() != NULL, "java heap should be initialized");
6929   assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6930   int oop_index = oop_recorder()->find_index(obj);
6931   RelocationHolder rspec = oop_Relocation::spec(oop_index);
6932   Assembler::cmp_narrow_oop(dst, oop_index, rspec);
6933 }
6934 
6935 void  MacroAssembler::cmp_narrow_klass(Register dst, Klass* k) {
6936   assert (UseCompressedClassPointers, "should only be used for compressed headers");
6937   assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6938   int klass_index = oop_recorder()->find_index(k);
6939   RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6940   Assembler::cmp_narrow_oop(dst, Klass::encode_klass(k), rspec);
6941 }
6942 
6943 void  MacroAssembler::cmp_narrow_klass(Address dst, Klass* k) {
6944   assert (UseCompressedClassPointers, "should only be used for compressed headers");
6945   assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6946   int klass_index = oop_recorder()->find_index(k);
6947   RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6948   Assembler::cmp_narrow_oop(dst, Klass::encode_klass(k), rspec);
6949 }
6950 
6951 void MacroAssembler::reinit_heapbase() {
6952   if (UseCompressedOops || UseCompressedClassPointers) {
6953     if (GC::is_initialized()) {
6954       if (Universe::narrow_oop_base() == NULL) {
6955         MacroAssembler::xorptr(r12_heapbase, r12_heapbase);
6956       } else {
6957         mov64(r12_heapbase, (int64_t)Universe::narrow_ptrs_base());
6958       }
6959     } else {
6960       movptr(r12_heapbase, ExternalAddress((address)Universe::narrow_ptrs_base_addr()));
6961     }
6962   }
6963 }
6964 
6965 #endif // _LP64
6966 
6967 
6968 // C2 compiled method's prolog code.
6969 void MacroAssembler::verified_entry(int framesize, int stack_bang_size, bool fp_mode_24b) {
6970 
6971   // WARNING: Initial instruction MUST be 5 bytes or longer so that
6972   // NativeJump::patch_verified_entry will be able to patch out the entry
6973   // code safely. The push to verify stack depth is ok at 5 bytes,
6974   // the frame allocation can be either 3 or 6 bytes. So if we don't do
6975   // stack bang then we must use the 6 byte frame allocation even if
6976   // we have no frame. :-(
6977   assert(stack_bang_size >= framesize || stack_bang_size <= 0, "stack bang size incorrect");
6978 
6979   assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
6980   // Remove word for return addr
6981   framesize -= wordSize;
6982   stack_bang_size -= wordSize;
6983 
6984   // Calls to C2R adapters often do not accept exceptional returns.
6985   // We require that their callers must bang for them.  But be careful, because
6986   // some VM calls (such as call site linkage) can use several kilobytes of
6987   // stack.  But the stack safety zone should account for that.
6988   // See bugs 4446381, 4468289, 4497237.
6989   if (stack_bang_size > 0) {
6990     generate_stack_overflow_check(stack_bang_size);
6991 
6992     // We always push rbp, so that on return to interpreter rbp, will be
6993     // restored correctly and we can correct the stack.
6994     push(rbp);
6995     // Save caller's stack pointer into RBP if the frame pointer is preserved.
6996     if (PreserveFramePointer) {
6997       mov(rbp, rsp);
6998     }
6999     // Remove word for ebp
7000     framesize -= wordSize;
7001 
7002     // Create frame
7003     if (framesize) {
7004       subptr(rsp, framesize);
7005     }
7006   } else {
7007     // Create frame (force generation of a 4 byte immediate value)
7008     subptr_imm32(rsp, framesize);
7009 
7010     // Save RBP register now.
7011     framesize -= wordSize;
7012     movptr(Address(rsp, framesize), rbp);
7013     // Save caller's stack pointer into RBP if the frame pointer is preserved.
7014     if (PreserveFramePointer) {
7015       movptr(rbp, rsp);
7016       if (framesize > 0) {
7017         addptr(rbp, framesize);
7018       }
7019     }
7020   }
7021 
7022   if (VerifyStackAtCalls) { // Majik cookie to verify stack depth
7023     framesize -= wordSize;
7024     movptr(Address(rsp, framesize), (int32_t)0xbadb100d);
7025   }
7026 
7027 #ifndef _LP64
7028   // If method sets FPU control word do it now
7029   if (fp_mode_24b) {
7030     fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
7031   }
7032   if (UseSSE >= 2 && VerifyFPU) {
7033     verify_FPU(0, "FPU stack must be clean on entry");
7034   }
7035 #endif
7036 
7037 #ifdef ASSERT
7038   if (VerifyStackAtCalls) {
7039     Label L;
7040     push(rax);
7041     mov(rax, rsp);
7042     andptr(rax, StackAlignmentInBytes-1);
7043     cmpptr(rax, StackAlignmentInBytes-wordSize);
7044     pop(rax);
7045     jcc(Assembler::equal, L);
7046     STOP("Stack is not properly aligned!");
7047     bind(L);
7048   }
7049 #endif
7050 
7051 }
7052 
7053 void MacroAssembler::clear_mem(Register base, Register cnt, Register tmp, bool is_large) {
7054   // cnt - number of qwords (8-byte words).
7055   // base - start address, qword aligned.
7056   // is_large - if optimizers know cnt is larger than InitArrayShortSize
7057   assert(base==rdi, "base register must be edi for rep stos");
7058   assert(tmp==rax,   "tmp register must be eax for rep stos");
7059   assert(cnt==rcx,   "cnt register must be ecx for rep stos");
7060   assert(InitArrayShortSize % BytesPerLong == 0,
7061     "InitArrayShortSize should be the multiple of BytesPerLong");
7062 
7063   Label DONE;
7064 
7065   xorptr(tmp, tmp);
7066 
7067   if (!is_large) {
7068     Label LOOP, LONG;
7069     cmpptr(cnt, InitArrayShortSize/BytesPerLong);
7070     jccb(Assembler::greater, LONG);
7071 
7072     NOT_LP64(shlptr(cnt, 1);) // convert to number of 32-bit words for 32-bit VM
7073 
7074     decrement(cnt);
7075     jccb(Assembler::negative, DONE); // Zero length
7076 
7077     // Use individual pointer-sized stores for small counts:
7078     BIND(LOOP);
7079     movptr(Address(base, cnt, Address::times_ptr), tmp);
7080     decrement(cnt);
7081     jccb(Assembler::greaterEqual, LOOP);
7082     jmpb(DONE);
7083 
7084     BIND(LONG);
7085   }
7086 
7087   // Use longer rep-prefixed ops for non-small counts:
7088   if (UseFastStosb) {
7089     shlptr(cnt, 3); // convert to number of bytes
7090     rep_stosb();
7091   } else {
7092     NOT_LP64(shlptr(cnt, 1);) // convert to number of 32-bit words for 32-bit VM
7093     rep_stos();
7094   }
7095 
7096   BIND(DONE);
7097 }
7098 
7099 #ifdef COMPILER2
7100 
7101 // IndexOf for constant substrings with size >= 8 chars
7102 // which don't need to be loaded through stack.
7103 void MacroAssembler::string_indexofC8(Register str1, Register str2,
7104                                       Register cnt1, Register cnt2,
7105                                       int int_cnt2,  Register result,
7106                                       XMMRegister vec, Register tmp,
7107                                       int ae) {
7108   ShortBranchVerifier sbv(this);
7109   assert(UseSSE42Intrinsics, "SSE4.2 intrinsics are required");
7110   assert(ae != StrIntrinsicNode::LU, "Invalid encoding");
7111 
7112   // This method uses the pcmpestri instruction with bound registers
7113   //   inputs:
7114   //     xmm - substring
7115   //     rax - substring length (elements count)
7116   //     mem - scanned string
7117   //     rdx - string length (elements count)
7118   //     0xd - mode: 1100 (substring search) + 01 (unsigned shorts)
7119   //     0xc - mode: 1100 (substring search) + 00 (unsigned bytes)
7120   //   outputs:
7121   //     rcx - matched index in string
7122   assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri");
7123   int mode   = (ae == StrIntrinsicNode::LL) ? 0x0c : 0x0d; // bytes or shorts
7124   int stride = (ae == StrIntrinsicNode::LL) ? 16 : 8; //UU, UL -> 8
7125   Address::ScaleFactor scale1 = (ae == StrIntrinsicNode::LL) ? Address::times_1 : Address::times_2;
7126   Address::ScaleFactor scale2 = (ae == StrIntrinsicNode::UL) ? Address::times_1 : scale1;
7127 
7128   Label RELOAD_SUBSTR, SCAN_TO_SUBSTR, SCAN_SUBSTR,
7129         RET_FOUND, RET_NOT_FOUND, EXIT, FOUND_SUBSTR,
7130         MATCH_SUBSTR_HEAD, RELOAD_STR, FOUND_CANDIDATE;
7131 
7132   // Note, inline_string_indexOf() generates checks:
7133   // if (substr.count > string.count) return -1;
7134   // if (substr.count == 0) return 0;
7135   assert(int_cnt2 >= stride, "this code is used only for cnt2 >= 8 chars");
7136 
7137   // Load substring.
7138   if (ae == StrIntrinsicNode::UL) {
7139     pmovzxbw(vec, Address(str2, 0));
7140   } else {
7141     movdqu(vec, Address(str2, 0));
7142   }
7143   movl(cnt2, int_cnt2);
7144   movptr(result, str1); // string addr
7145 
7146   if (int_cnt2 > stride) {
7147     jmpb(SCAN_TO_SUBSTR);
7148 
7149     // Reload substr for rescan, this code
7150     // is executed only for large substrings (> 8 chars)
7151     bind(RELOAD_SUBSTR);
7152     if (ae == StrIntrinsicNode::UL) {
7153       pmovzxbw(vec, Address(str2, 0));
7154     } else {
7155       movdqu(vec, Address(str2, 0));
7156     }
7157     negptr(cnt2); // Jumped here with negative cnt2, convert to positive
7158 
7159     bind(RELOAD_STR);
7160     // We came here after the beginning of the substring was
7161     // matched but the rest of it was not so we need to search
7162     // again. Start from the next element after the previous match.
7163 
7164     // cnt2 is number of substring reminding elements and
7165     // cnt1 is number of string reminding elements when cmp failed.
7166     // Restored cnt1 = cnt1 - cnt2 + int_cnt2
7167     subl(cnt1, cnt2);
7168     addl(cnt1, int_cnt2);
7169     movl(cnt2, int_cnt2); // Now restore cnt2
7170 
7171     decrementl(cnt1);     // Shift to next element
7172     cmpl(cnt1, cnt2);
7173     jcc(Assembler::negative, RET_NOT_FOUND);  // Left less then substring
7174 
7175     addptr(result, (1<<scale1));
7176 
7177   } // (int_cnt2 > 8)
7178 
7179   // Scan string for start of substr in 16-byte vectors
7180   bind(SCAN_TO_SUBSTR);
7181   pcmpestri(vec, Address(result, 0), mode);
7182   jccb(Assembler::below, FOUND_CANDIDATE);   // CF == 1
7183   subl(cnt1, stride);
7184   jccb(Assembler::lessEqual, RET_NOT_FOUND); // Scanned full string
7185   cmpl(cnt1, cnt2);
7186   jccb(Assembler::negative, RET_NOT_FOUND);  // Left less then substring
7187   addptr(result, 16);
7188   jmpb(SCAN_TO_SUBSTR);
7189 
7190   // Found a potential substr
7191   bind(FOUND_CANDIDATE);
7192   // Matched whole vector if first element matched (tmp(rcx) == 0).
7193   if (int_cnt2 == stride) {
7194     jccb(Assembler::overflow, RET_FOUND);    // OF == 1
7195   } else { // int_cnt2 > 8
7196     jccb(Assembler::overflow, FOUND_SUBSTR);
7197   }
7198   // After pcmpestri tmp(rcx) contains matched element index
7199   // Compute start addr of substr
7200   lea(result, Address(result, tmp, scale1));
7201 
7202   // Make sure string is still long enough
7203   subl(cnt1, tmp);
7204   cmpl(cnt1, cnt2);
7205   if (int_cnt2 == stride) {
7206     jccb(Assembler::greaterEqual, SCAN_TO_SUBSTR);
7207   } else { // int_cnt2 > 8
7208     jccb(Assembler::greaterEqual, MATCH_SUBSTR_HEAD);
7209   }
7210   // Left less then substring.
7211 
7212   bind(RET_NOT_FOUND);
7213   movl(result, -1);
7214   jmp(EXIT);
7215 
7216   if (int_cnt2 > stride) {
7217     // This code is optimized for the case when whole substring
7218     // is matched if its head is matched.
7219     bind(MATCH_SUBSTR_HEAD);
7220     pcmpestri(vec, Address(result, 0), mode);
7221     // Reload only string if does not match
7222     jcc(Assembler::noOverflow, RELOAD_STR); // OF == 0
7223 
7224     Label CONT_SCAN_SUBSTR;
7225     // Compare the rest of substring (> 8 chars).
7226     bind(FOUND_SUBSTR);
7227     // First 8 chars are already matched.
7228     negptr(cnt2);
7229     addptr(cnt2, stride);
7230 
7231     bind(SCAN_SUBSTR);
7232     subl(cnt1, stride);
7233     cmpl(cnt2, -stride); // Do not read beyond substring
7234     jccb(Assembler::lessEqual, CONT_SCAN_SUBSTR);
7235     // Back-up strings to avoid reading beyond substring:
7236     // cnt1 = cnt1 - cnt2 + 8
7237     addl(cnt1, cnt2); // cnt2 is negative
7238     addl(cnt1, stride);
7239     movl(cnt2, stride); negptr(cnt2);
7240     bind(CONT_SCAN_SUBSTR);
7241     if (int_cnt2 < (int)G) {
7242       int tail_off1 = int_cnt2<<scale1;
7243       int tail_off2 = int_cnt2<<scale2;
7244       if (ae == StrIntrinsicNode::UL) {
7245         pmovzxbw(vec, Address(str2, cnt2, scale2, tail_off2));
7246       } else {
7247         movdqu(vec, Address(str2, cnt2, scale2, tail_off2));
7248       }
7249       pcmpestri(vec, Address(result, cnt2, scale1, tail_off1), mode);
7250     } else {
7251       // calculate index in register to avoid integer overflow (int_cnt2*2)
7252       movl(tmp, int_cnt2);
7253       addptr(tmp, cnt2);
7254       if (ae == StrIntrinsicNode::UL) {
7255         pmovzxbw(vec, Address(str2, tmp, scale2, 0));
7256       } else {
7257         movdqu(vec, Address(str2, tmp, scale2, 0));
7258       }
7259       pcmpestri(vec, Address(result, tmp, scale1, 0), mode);
7260     }
7261     // Need to reload strings pointers if not matched whole vector
7262     jcc(Assembler::noOverflow, RELOAD_SUBSTR); // OF == 0
7263     addptr(cnt2, stride);
7264     jcc(Assembler::negative, SCAN_SUBSTR);
7265     // Fall through if found full substring
7266 
7267   } // (int_cnt2 > 8)
7268 
7269   bind(RET_FOUND);
7270   // Found result if we matched full small substring.
7271   // Compute substr offset
7272   subptr(result, str1);
7273   if (ae == StrIntrinsicNode::UU || ae == StrIntrinsicNode::UL) {
7274     shrl(result, 1); // index
7275   }
7276   bind(EXIT);
7277 
7278 } // string_indexofC8
7279 
7280 // Small strings are loaded through stack if they cross page boundary.
7281 void MacroAssembler::string_indexof(Register str1, Register str2,
7282                                     Register cnt1, Register cnt2,
7283                                     int int_cnt2,  Register result,
7284                                     XMMRegister vec, Register tmp,
7285                                     int ae) {
7286   ShortBranchVerifier sbv(this);
7287   assert(UseSSE42Intrinsics, "SSE4.2 intrinsics are required");
7288   assert(ae != StrIntrinsicNode::LU, "Invalid encoding");
7289 
7290   //
7291   // int_cnt2 is length of small (< 8 chars) constant substring
7292   // or (-1) for non constant substring in which case its length
7293   // is in cnt2 register.
7294   //
7295   // Note, inline_string_indexOf() generates checks:
7296   // if (substr.count > string.count) return -1;
7297   // if (substr.count == 0) return 0;
7298   //
7299   int stride = (ae == StrIntrinsicNode::LL) ? 16 : 8; //UU, UL -> 8
7300   assert(int_cnt2 == -1 || (0 < int_cnt2 && int_cnt2 < stride), "should be != 0");
7301   // This method uses the pcmpestri instruction with bound registers
7302   //   inputs:
7303   //     xmm - substring
7304   //     rax - substring length (elements count)
7305   //     mem - scanned string
7306   //     rdx - string length (elements count)
7307   //     0xd - mode: 1100 (substring search) + 01 (unsigned shorts)
7308   //     0xc - mode: 1100 (substring search) + 00 (unsigned bytes)
7309   //   outputs:
7310   //     rcx - matched index in string
7311   assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri");
7312   int mode = (ae == StrIntrinsicNode::LL) ? 0x0c : 0x0d; // bytes or shorts
7313   Address::ScaleFactor scale1 = (ae == StrIntrinsicNode::LL) ? Address::times_1 : Address::times_2;
7314   Address::ScaleFactor scale2 = (ae == StrIntrinsicNode::UL) ? Address::times_1 : scale1;
7315 
7316   Label RELOAD_SUBSTR, SCAN_TO_SUBSTR, SCAN_SUBSTR, ADJUST_STR,
7317         RET_FOUND, RET_NOT_FOUND, CLEANUP, FOUND_SUBSTR,
7318         FOUND_CANDIDATE;
7319 
7320   { //========================================================
7321     // We don't know where these strings are located
7322     // and we can't read beyond them. Load them through stack.
7323     Label BIG_STRINGS, CHECK_STR, COPY_SUBSTR, COPY_STR;
7324 
7325     movptr(tmp, rsp); // save old SP
7326 
7327     if (int_cnt2 > 0) {     // small (< 8 chars) constant substring
7328       if (int_cnt2 == (1>>scale2)) { // One byte
7329         assert((ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UL), "Only possible for latin1 encoding");
7330         load_unsigned_byte(result, Address(str2, 0));
7331         movdl(vec, result); // move 32 bits
7332       } else if (ae == StrIntrinsicNode::LL && int_cnt2 == 3) {  // Three bytes
7333         // Not enough header space in 32-bit VM: 12+3 = 15.
7334         movl(result, Address(str2, -1));
7335         shrl(result, 8);
7336         movdl(vec, result); // move 32 bits
7337       } else if (ae != StrIntrinsicNode::UL && int_cnt2 == (2>>scale2)) {  // One char
7338         load_unsigned_short(result, Address(str2, 0));
7339         movdl(vec, result); // move 32 bits
7340       } else if (ae != StrIntrinsicNode::UL && int_cnt2 == (4>>scale2)) { // Two chars
7341         movdl(vec, Address(str2, 0)); // move 32 bits
7342       } else if (ae != StrIntrinsicNode::UL && int_cnt2 == (8>>scale2)) { // Four chars
7343         movq(vec, Address(str2, 0));  // move 64 bits
7344       } else { // cnt2 = { 3, 5, 6, 7 } || (ae == StrIntrinsicNode::UL && cnt2 ={2, ..., 7})
7345         // Array header size is 12 bytes in 32-bit VM
7346         // + 6 bytes for 3 chars == 18 bytes,
7347         // enough space to load vec and shift.
7348         assert(HeapWordSize*TypeArrayKlass::header_size() >= 12,"sanity");
7349         if (ae == StrIntrinsicNode::UL) {
7350           int tail_off = int_cnt2-8;
7351           pmovzxbw(vec, Address(str2, tail_off));
7352           psrldq(vec, -2*tail_off);
7353         }
7354         else {
7355           int tail_off = int_cnt2*(1<<scale2);
7356           movdqu(vec, Address(str2, tail_off-16));
7357           psrldq(vec, 16-tail_off);
7358         }
7359       }
7360     } else { // not constant substring
7361       cmpl(cnt2, stride);
7362       jccb(Assembler::aboveEqual, BIG_STRINGS); // Both strings are big enough
7363 
7364       // We can read beyond string if srt+16 does not cross page boundary
7365       // since heaps are aligned and mapped by pages.
7366       assert(os::vm_page_size() < (int)G, "default page should be small");
7367       movl(result, str2); // We need only low 32 bits
7368       andl(result, (os::vm_page_size()-1));
7369       cmpl(result, (os::vm_page_size()-16));
7370       jccb(Assembler::belowEqual, CHECK_STR);
7371 
7372       // Move small strings to stack to allow load 16 bytes into vec.
7373       subptr(rsp, 16);
7374       int stk_offset = wordSize-(1<<scale2);
7375       push(cnt2);
7376 
7377       bind(COPY_SUBSTR);
7378       if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UL) {
7379         load_unsigned_byte(result, Address(str2, cnt2, scale2, -1));
7380         movb(Address(rsp, cnt2, scale2, stk_offset), result);
7381       } else if (ae == StrIntrinsicNode::UU) {
7382         load_unsigned_short(result, Address(str2, cnt2, scale2, -2));
7383         movw(Address(rsp, cnt2, scale2, stk_offset), result);
7384       }
7385       decrement(cnt2);
7386       jccb(Assembler::notZero, COPY_SUBSTR);
7387 
7388       pop(cnt2);
7389       movptr(str2, rsp);  // New substring address
7390     } // non constant
7391 
7392     bind(CHECK_STR);
7393     cmpl(cnt1, stride);
7394     jccb(Assembler::aboveEqual, BIG_STRINGS);
7395 
7396     // Check cross page boundary.
7397     movl(result, str1); // We need only low 32 bits
7398     andl(result, (os::vm_page_size()-1));
7399     cmpl(result, (os::vm_page_size()-16));
7400     jccb(Assembler::belowEqual, BIG_STRINGS);
7401 
7402     subptr(rsp, 16);
7403     int stk_offset = -(1<<scale1);
7404     if (int_cnt2 < 0) { // not constant
7405       push(cnt2);
7406       stk_offset += wordSize;
7407     }
7408     movl(cnt2, cnt1);
7409 
7410     bind(COPY_STR);
7411     if (ae == StrIntrinsicNode::LL) {
7412       load_unsigned_byte(result, Address(str1, cnt2, scale1, -1));
7413       movb(Address(rsp, cnt2, scale1, stk_offset), result);
7414     } else {
7415       load_unsigned_short(result, Address(str1, cnt2, scale1, -2));
7416       movw(Address(rsp, cnt2, scale1, stk_offset), result);
7417     }
7418     decrement(cnt2);
7419     jccb(Assembler::notZero, COPY_STR);
7420 
7421     if (int_cnt2 < 0) { // not constant
7422       pop(cnt2);
7423     }
7424     movptr(str1, rsp);  // New string address
7425 
7426     bind(BIG_STRINGS);
7427     // Load substring.
7428     if (int_cnt2 < 0) { // -1
7429       if (ae == StrIntrinsicNode::UL) {
7430         pmovzxbw(vec, Address(str2, 0));
7431       } else {
7432         movdqu(vec, Address(str2, 0));
7433       }
7434       push(cnt2);       // substr count
7435       push(str2);       // substr addr
7436       push(str1);       // string addr
7437     } else {
7438       // Small (< 8 chars) constant substrings are loaded already.
7439       movl(cnt2, int_cnt2);
7440     }
7441     push(tmp);  // original SP
7442 
7443   } // Finished loading
7444 
7445   //========================================================
7446   // Start search
7447   //
7448 
7449   movptr(result, str1); // string addr
7450 
7451   if (int_cnt2  < 0) {  // Only for non constant substring
7452     jmpb(SCAN_TO_SUBSTR);
7453 
7454     // SP saved at sp+0
7455     // String saved at sp+1*wordSize
7456     // Substr saved at sp+2*wordSize
7457     // Substr count saved at sp+3*wordSize
7458 
7459     // Reload substr for rescan, this code
7460     // is executed only for large substrings (> 8 chars)
7461     bind(RELOAD_SUBSTR);
7462     movptr(str2, Address(rsp, 2*wordSize));
7463     movl(cnt2, Address(rsp, 3*wordSize));
7464     if (ae == StrIntrinsicNode::UL) {
7465       pmovzxbw(vec, Address(str2, 0));
7466     } else {
7467       movdqu(vec, Address(str2, 0));
7468     }
7469     // We came here after the beginning of the substring was
7470     // matched but the rest of it was not so we need to search
7471     // again. Start from the next element after the previous match.
7472     subptr(str1, result); // Restore counter
7473     if (ae == StrIntrinsicNode::UU || ae == StrIntrinsicNode::UL) {
7474       shrl(str1, 1);
7475     }
7476     addl(cnt1, str1);
7477     decrementl(cnt1);   // Shift to next element
7478     cmpl(cnt1, cnt2);
7479     jcc(Assembler::negative, RET_NOT_FOUND);  // Left less then substring
7480 
7481     addptr(result, (1<<scale1));
7482   } // non constant
7483 
7484   // Scan string for start of substr in 16-byte vectors
7485   bind(SCAN_TO_SUBSTR);
7486   assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri");
7487   pcmpestri(vec, Address(result, 0), mode);
7488   jccb(Assembler::below, FOUND_CANDIDATE);   // CF == 1
7489   subl(cnt1, stride);
7490   jccb(Assembler::lessEqual, RET_NOT_FOUND); // Scanned full string
7491   cmpl(cnt1, cnt2);
7492   jccb(Assembler::negative, RET_NOT_FOUND);  // Left less then substring
7493   addptr(result, 16);
7494 
7495   bind(ADJUST_STR);
7496   cmpl(cnt1, stride); // Do not read beyond string
7497   jccb(Assembler::greaterEqual, SCAN_TO_SUBSTR);
7498   // Back-up string to avoid reading beyond string.
7499   lea(result, Address(result, cnt1, scale1, -16));
7500   movl(cnt1, stride);
7501   jmpb(SCAN_TO_SUBSTR);
7502 
7503   // Found a potential substr
7504   bind(FOUND_CANDIDATE);
7505   // After pcmpestri tmp(rcx) contains matched element index
7506 
7507   // Make sure string is still long enough
7508   subl(cnt1, tmp);
7509   cmpl(cnt1, cnt2);
7510   jccb(Assembler::greaterEqual, FOUND_SUBSTR);
7511   // Left less then substring.
7512 
7513   bind(RET_NOT_FOUND);
7514   movl(result, -1);
7515   jmpb(CLEANUP);
7516 
7517   bind(FOUND_SUBSTR);
7518   // Compute start addr of substr
7519   lea(result, Address(result, tmp, scale1));
7520   if (int_cnt2 > 0) { // Constant substring
7521     // Repeat search for small substring (< 8 chars)
7522     // from new point without reloading substring.
7523     // Have to check that we don't read beyond string.
7524     cmpl(tmp, stride-int_cnt2);
7525     jccb(Assembler::greater, ADJUST_STR);
7526     // Fall through if matched whole substring.
7527   } else { // non constant
7528     assert(int_cnt2 == -1, "should be != 0");
7529 
7530     addl(tmp, cnt2);
7531     // Found result if we matched whole substring.
7532     cmpl(tmp, stride);
7533     jccb(Assembler::lessEqual, RET_FOUND);
7534 
7535     // Repeat search for small substring (<= 8 chars)
7536     // from new point 'str1' without reloading substring.
7537     cmpl(cnt2, stride);
7538     // Have to check that we don't read beyond string.
7539     jccb(Assembler::lessEqual, ADJUST_STR);
7540 
7541     Label CHECK_NEXT, CONT_SCAN_SUBSTR, RET_FOUND_LONG;
7542     // Compare the rest of substring (> 8 chars).
7543     movptr(str1, result);
7544 
7545     cmpl(tmp, cnt2);
7546     // First 8 chars are already matched.
7547     jccb(Assembler::equal, CHECK_NEXT);
7548 
7549     bind(SCAN_SUBSTR);
7550     pcmpestri(vec, Address(str1, 0), mode);
7551     // Need to reload strings pointers if not matched whole vector
7552     jcc(Assembler::noOverflow, RELOAD_SUBSTR); // OF == 0
7553 
7554     bind(CHECK_NEXT);
7555     subl(cnt2, stride);
7556     jccb(Assembler::lessEqual, RET_FOUND_LONG); // Found full substring
7557     addptr(str1, 16);
7558     if (ae == StrIntrinsicNode::UL) {
7559       addptr(str2, 8);
7560     } else {
7561       addptr(str2, 16);
7562     }
7563     subl(cnt1, stride);
7564     cmpl(cnt2, stride); // Do not read beyond substring
7565     jccb(Assembler::greaterEqual, CONT_SCAN_SUBSTR);
7566     // Back-up strings to avoid reading beyond substring.
7567 
7568     if (ae == StrIntrinsicNode::UL) {
7569       lea(str2, Address(str2, cnt2, scale2, -8));
7570       lea(str1, Address(str1, cnt2, scale1, -16));
7571     } else {
7572       lea(str2, Address(str2, cnt2, scale2, -16));
7573       lea(str1, Address(str1, cnt2, scale1, -16));
7574     }
7575     subl(cnt1, cnt2);
7576     movl(cnt2, stride);
7577     addl(cnt1, stride);
7578     bind(CONT_SCAN_SUBSTR);
7579     if (ae == StrIntrinsicNode::UL) {
7580       pmovzxbw(vec, Address(str2, 0));
7581     } else {
7582       movdqu(vec, Address(str2, 0));
7583     }
7584     jmp(SCAN_SUBSTR);
7585 
7586     bind(RET_FOUND_LONG);
7587     movptr(str1, Address(rsp, wordSize));
7588   } // non constant
7589 
7590   bind(RET_FOUND);
7591   // Compute substr offset
7592   subptr(result, str1);
7593   if (ae == StrIntrinsicNode::UU || ae == StrIntrinsicNode::UL) {
7594     shrl(result, 1); // index
7595   }
7596   bind(CLEANUP);
7597   pop(rsp); // restore SP
7598 
7599 } // string_indexof
7600 
7601 void MacroAssembler::string_indexof_char(Register str1, Register cnt1, Register ch, Register result,
7602                                          XMMRegister vec1, XMMRegister vec2, XMMRegister vec3, Register tmp) {
7603   ShortBranchVerifier sbv(this);
7604   assert(UseSSE42Intrinsics, "SSE4.2 intrinsics are required");
7605 
7606   int stride = 8;
7607 
7608   Label FOUND_CHAR, SCAN_TO_CHAR, SCAN_TO_CHAR_LOOP,
7609         SCAN_TO_8_CHAR, SCAN_TO_8_CHAR_LOOP, SCAN_TO_16_CHAR_LOOP,
7610         RET_NOT_FOUND, SCAN_TO_8_CHAR_INIT,
7611         FOUND_SEQ_CHAR, DONE_LABEL;
7612 
7613   movptr(result, str1);
7614   if (UseAVX >= 2) {
7615     cmpl(cnt1, stride);
7616     jcc(Assembler::less, SCAN_TO_CHAR_LOOP);
7617     cmpl(cnt1, 2*stride);
7618     jcc(Assembler::less, SCAN_TO_8_CHAR_INIT);
7619     movdl(vec1, ch);
7620     vpbroadcastw(vec1, vec1);
7621     vpxor(vec2, vec2);
7622     movl(tmp, cnt1);
7623     andl(tmp, 0xFFFFFFF0);  //vector count (in chars)
7624     andl(cnt1,0x0000000F);  //tail count (in chars)
7625 
7626     bind(SCAN_TO_16_CHAR_LOOP);
7627     vmovdqu(vec3, Address(result, 0));
7628     vpcmpeqw(vec3, vec3, vec1, 1);
7629     vptest(vec2, vec3);
7630     jcc(Assembler::carryClear, FOUND_CHAR);
7631     addptr(result, 32);
7632     subl(tmp, 2*stride);
7633     jccb(Assembler::notZero, SCAN_TO_16_CHAR_LOOP);
7634     jmp(SCAN_TO_8_CHAR);
7635     bind(SCAN_TO_8_CHAR_INIT);
7636     movdl(vec1, ch);
7637     pshuflw(vec1, vec1, 0x00);
7638     pshufd(vec1, vec1, 0);
7639     pxor(vec2, vec2);
7640   }
7641   bind(SCAN_TO_8_CHAR);
7642   cmpl(cnt1, stride);
7643   if (UseAVX >= 2) {
7644     jcc(Assembler::less, SCAN_TO_CHAR);
7645   } else {
7646     jcc(Assembler::less, SCAN_TO_CHAR_LOOP);
7647     movdl(vec1, ch);
7648     pshuflw(vec1, vec1, 0x00);
7649     pshufd(vec1, vec1, 0);
7650     pxor(vec2, vec2);
7651   }
7652   movl(tmp, cnt1);
7653   andl(tmp, 0xFFFFFFF8);  //vector count (in chars)
7654   andl(cnt1,0x00000007);  //tail count (in chars)
7655 
7656   bind(SCAN_TO_8_CHAR_LOOP);
7657   movdqu(vec3, Address(result, 0));
7658   pcmpeqw(vec3, vec1);
7659   ptest(vec2, vec3);
7660   jcc(Assembler::carryClear, FOUND_CHAR);
7661   addptr(result, 16);
7662   subl(tmp, stride);
7663   jccb(Assembler::notZero, SCAN_TO_8_CHAR_LOOP);
7664   bind(SCAN_TO_CHAR);
7665   testl(cnt1, cnt1);
7666   jcc(Assembler::zero, RET_NOT_FOUND);
7667   bind(SCAN_TO_CHAR_LOOP);
7668   load_unsigned_short(tmp, Address(result, 0));
7669   cmpl(ch, tmp);
7670   jccb(Assembler::equal, FOUND_SEQ_CHAR);
7671   addptr(result, 2);
7672   subl(cnt1, 1);
7673   jccb(Assembler::zero, RET_NOT_FOUND);
7674   jmp(SCAN_TO_CHAR_LOOP);
7675 
7676   bind(RET_NOT_FOUND);
7677   movl(result, -1);
7678   jmpb(DONE_LABEL);
7679 
7680   bind(FOUND_CHAR);
7681   if (UseAVX >= 2) {
7682     vpmovmskb(tmp, vec3);
7683   } else {
7684     pmovmskb(tmp, vec3);
7685   }
7686   bsfl(ch, tmp);
7687   addl(result, ch);
7688 
7689   bind(FOUND_SEQ_CHAR);
7690   subptr(result, str1);
7691   shrl(result, 1);
7692 
7693   bind(DONE_LABEL);
7694 } // string_indexof_char
7695 
7696 // helper function for string_compare
7697 void MacroAssembler::load_next_elements(Register elem1, Register elem2, Register str1, Register str2,
7698                                         Address::ScaleFactor scale, Address::ScaleFactor scale1,
7699                                         Address::ScaleFactor scale2, Register index, int ae) {
7700   if (ae == StrIntrinsicNode::LL) {
7701     load_unsigned_byte(elem1, Address(str1, index, scale, 0));
7702     load_unsigned_byte(elem2, Address(str2, index, scale, 0));
7703   } else if (ae == StrIntrinsicNode::UU) {
7704     load_unsigned_short(elem1, Address(str1, index, scale, 0));
7705     load_unsigned_short(elem2, Address(str2, index, scale, 0));
7706   } else {
7707     load_unsigned_byte(elem1, Address(str1, index, scale1, 0));
7708     load_unsigned_short(elem2, Address(str2, index, scale2, 0));
7709   }
7710 }
7711 
7712 // Compare strings, used for char[] and byte[].
7713 void MacroAssembler::string_compare(Register str1, Register str2,
7714                                     Register cnt1, Register cnt2, Register result,
7715                                     XMMRegister vec1, int ae) {
7716   ShortBranchVerifier sbv(this);
7717   Label LENGTH_DIFF_LABEL, POP_LABEL, DONE_LABEL, WHILE_HEAD_LABEL;
7718   Label COMPARE_WIDE_VECTORS_LOOP_FAILED;  // used only _LP64 && AVX3
7719   int stride, stride2, adr_stride, adr_stride1, adr_stride2;
7720   int stride2x2 = 0x40;
7721   Address::ScaleFactor scale = Address::no_scale;
7722   Address::ScaleFactor scale1 = Address::no_scale;
7723   Address::ScaleFactor scale2 = Address::no_scale;
7724 
7725   if (ae != StrIntrinsicNode::LL) {
7726     stride2x2 = 0x20;
7727   }
7728 
7729   if (ae == StrIntrinsicNode::LU || ae == StrIntrinsicNode::UL) {
7730     shrl(cnt2, 1);
7731   }
7732   // Compute the minimum of the string lengths and the
7733   // difference of the string lengths (stack).
7734   // Do the conditional move stuff
7735   movl(result, cnt1);
7736   subl(cnt1, cnt2);
7737   push(cnt1);
7738   cmov32(Assembler::lessEqual, cnt2, result);    // cnt2 = min(cnt1, cnt2)
7739 
7740   // Is the minimum length zero?
7741   testl(cnt2, cnt2);
7742   jcc(Assembler::zero, LENGTH_DIFF_LABEL);
7743   if (ae == StrIntrinsicNode::LL) {
7744     // Load first bytes
7745     load_unsigned_byte(result, Address(str1, 0));  // result = str1[0]
7746     load_unsigned_byte(cnt1, Address(str2, 0));    // cnt1   = str2[0]
7747   } else if (ae == StrIntrinsicNode::UU) {
7748     // Load first characters
7749     load_unsigned_short(result, Address(str1, 0));
7750     load_unsigned_short(cnt1, Address(str2, 0));
7751   } else {
7752     load_unsigned_byte(result, Address(str1, 0));
7753     load_unsigned_short(cnt1, Address(str2, 0));
7754   }
7755   subl(result, cnt1);
7756   jcc(Assembler::notZero,  POP_LABEL);
7757 
7758   if (ae == StrIntrinsicNode::UU) {
7759     // Divide length by 2 to get number of chars
7760     shrl(cnt2, 1);
7761   }
7762   cmpl(cnt2, 1);
7763   jcc(Assembler::equal, LENGTH_DIFF_LABEL);
7764 
7765   // Check if the strings start at the same location and setup scale and stride
7766   if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7767     cmpptr(str1, str2);
7768     jcc(Assembler::equal, LENGTH_DIFF_LABEL);
7769     if (ae == StrIntrinsicNode::LL) {
7770       scale = Address::times_1;
7771       stride = 16;
7772     } else {
7773       scale = Address::times_2;
7774       stride = 8;
7775     }
7776   } else {
7777     scale1 = Address::times_1;
7778     scale2 = Address::times_2;
7779     // scale not used
7780     stride = 8;
7781   }
7782 
7783   if (UseAVX >= 2 && UseSSE42Intrinsics) {
7784     Label COMPARE_WIDE_VECTORS, VECTOR_NOT_EQUAL, COMPARE_WIDE_TAIL, COMPARE_SMALL_STR;
7785     Label COMPARE_WIDE_VECTORS_LOOP, COMPARE_16_CHARS, COMPARE_INDEX_CHAR;
7786     Label COMPARE_WIDE_VECTORS_LOOP_AVX2;
7787     Label COMPARE_TAIL_LONG;
7788     Label COMPARE_WIDE_VECTORS_LOOP_AVX3;  // used only _LP64 && AVX3
7789 
7790     int pcmpmask = 0x19;
7791     if (ae == StrIntrinsicNode::LL) {
7792       pcmpmask &= ~0x01;
7793     }
7794 
7795     // Setup to compare 16-chars (32-bytes) vectors,
7796     // start from first character again because it has aligned address.
7797     if (ae == StrIntrinsicNode::LL) {
7798       stride2 = 32;
7799     } else {
7800       stride2 = 16;
7801     }
7802     if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7803       adr_stride = stride << scale;
7804     } else {
7805       adr_stride1 = 8;  //stride << scale1;
7806       adr_stride2 = 16; //stride << scale2;
7807     }
7808 
7809     assert(result == rax && cnt2 == rdx && cnt1 == rcx, "pcmpestri");
7810     // rax and rdx are used by pcmpestri as elements counters
7811     movl(result, cnt2);
7812     andl(cnt2, ~(stride2-1));   // cnt2 holds the vector count
7813     jcc(Assembler::zero, COMPARE_TAIL_LONG);
7814 
7815     // fast path : compare first 2 8-char vectors.
7816     bind(COMPARE_16_CHARS);
7817     if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7818       movdqu(vec1, Address(str1, 0));
7819     } else {
7820       pmovzxbw(vec1, Address(str1, 0));
7821     }
7822     pcmpestri(vec1, Address(str2, 0), pcmpmask);
7823     jccb(Assembler::below, COMPARE_INDEX_CHAR);
7824 
7825     if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7826       movdqu(vec1, Address(str1, adr_stride));
7827       pcmpestri(vec1, Address(str2, adr_stride), pcmpmask);
7828     } else {
7829       pmovzxbw(vec1, Address(str1, adr_stride1));
7830       pcmpestri(vec1, Address(str2, adr_stride2), pcmpmask);
7831     }
7832     jccb(Assembler::aboveEqual, COMPARE_WIDE_VECTORS);
7833     addl(cnt1, stride);
7834 
7835     // Compare the characters at index in cnt1
7836     bind(COMPARE_INDEX_CHAR); // cnt1 has the offset of the mismatching character
7837     load_next_elements(result, cnt2, str1, str2, scale, scale1, scale2, cnt1, ae);
7838     subl(result, cnt2);
7839     jmp(POP_LABEL);
7840 
7841     // Setup the registers to start vector comparison loop
7842     bind(COMPARE_WIDE_VECTORS);
7843     if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7844       lea(str1, Address(str1, result, scale));
7845       lea(str2, Address(str2, result, scale));
7846     } else {
7847       lea(str1, Address(str1, result, scale1));
7848       lea(str2, Address(str2, result, scale2));
7849     }
7850     subl(result, stride2);
7851     subl(cnt2, stride2);
7852     jcc(Assembler::zero, COMPARE_WIDE_TAIL);
7853     negptr(result);
7854 
7855     //  In a loop, compare 16-chars (32-bytes) at once using (vpxor+vptest)
7856     bind(COMPARE_WIDE_VECTORS_LOOP);
7857 
7858 #ifdef _LP64
7859     if (VM_Version::supports_avx512vlbw()) { // trying 64 bytes fast loop
7860       cmpl(cnt2, stride2x2);
7861       jccb(Assembler::below, COMPARE_WIDE_VECTORS_LOOP_AVX2);
7862       testl(cnt2, stride2x2-1);   // cnt2 holds the vector count
7863       jccb(Assembler::notZero, COMPARE_WIDE_VECTORS_LOOP_AVX2);   // means we cannot subtract by 0x40
7864 
7865       bind(COMPARE_WIDE_VECTORS_LOOP_AVX3); // the hottest loop
7866       if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7867         evmovdquq(vec1, Address(str1, result, scale), Assembler::AVX_512bit);
7868         evpcmpeqb(k7, vec1, Address(str2, result, scale), Assembler::AVX_512bit); // k7 == 11..11, if operands equal, otherwise k7 has some 0
7869       } else {
7870         vpmovzxbw(vec1, Address(str1, result, scale1), Assembler::AVX_512bit);
7871         evpcmpeqb(k7, vec1, Address(str2, result, scale2), Assembler::AVX_512bit); // k7 == 11..11, if operands equal, otherwise k7 has some 0
7872       }
7873       kortestql(k7, k7);
7874       jcc(Assembler::aboveEqual, COMPARE_WIDE_VECTORS_LOOP_FAILED);     // miscompare
7875       addptr(result, stride2x2);  // update since we already compared at this addr
7876       subl(cnt2, stride2x2);      // and sub the size too
7877       jccb(Assembler::notZero, COMPARE_WIDE_VECTORS_LOOP_AVX3);
7878 
7879       vpxor(vec1, vec1);
7880       jmpb(COMPARE_WIDE_TAIL);
7881     }//if (VM_Version::supports_avx512vlbw())
7882 #endif // _LP64
7883 
7884 
7885     bind(COMPARE_WIDE_VECTORS_LOOP_AVX2);
7886     if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7887       vmovdqu(vec1, Address(str1, result, scale));
7888       vpxor(vec1, Address(str2, result, scale));
7889     } else {
7890       vpmovzxbw(vec1, Address(str1, result, scale1), Assembler::AVX_256bit);
7891       vpxor(vec1, Address(str2, result, scale2));
7892     }
7893     vptest(vec1, vec1);
7894     jcc(Assembler::notZero, VECTOR_NOT_EQUAL);
7895     addptr(result, stride2);
7896     subl(cnt2, stride2);
7897     jcc(Assembler::notZero, COMPARE_WIDE_VECTORS_LOOP);
7898     // clean upper bits of YMM registers
7899     vpxor(vec1, vec1);
7900 
7901     // compare wide vectors tail
7902     bind(COMPARE_WIDE_TAIL);
7903     testptr(result, result);
7904     jcc(Assembler::zero, LENGTH_DIFF_LABEL);
7905 
7906     movl(result, stride2);
7907     movl(cnt2, result);
7908     negptr(result);
7909     jmp(COMPARE_WIDE_VECTORS_LOOP_AVX2);
7910 
7911     // Identifies the mismatching (higher or lower)16-bytes in the 32-byte vectors.
7912     bind(VECTOR_NOT_EQUAL);
7913     // clean upper bits of YMM registers
7914     vpxor(vec1, vec1);
7915     if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7916       lea(str1, Address(str1, result, scale));
7917       lea(str2, Address(str2, result, scale));
7918     } else {
7919       lea(str1, Address(str1, result, scale1));
7920       lea(str2, Address(str2, result, scale2));
7921     }
7922     jmp(COMPARE_16_CHARS);
7923 
7924     // Compare tail chars, length between 1 to 15 chars
7925     bind(COMPARE_TAIL_LONG);
7926     movl(cnt2, result);
7927     cmpl(cnt2, stride);
7928     jcc(Assembler::less, COMPARE_SMALL_STR);
7929 
7930     if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7931       movdqu(vec1, Address(str1, 0));
7932     } else {
7933       pmovzxbw(vec1, Address(str1, 0));
7934     }
7935     pcmpestri(vec1, Address(str2, 0), pcmpmask);
7936     jcc(Assembler::below, COMPARE_INDEX_CHAR);
7937     subptr(cnt2, stride);
7938     jcc(Assembler::zero, LENGTH_DIFF_LABEL);
7939     if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7940       lea(str1, Address(str1, result, scale));
7941       lea(str2, Address(str2, result, scale));
7942     } else {
7943       lea(str1, Address(str1, result, scale1));
7944       lea(str2, Address(str2, result, scale2));
7945     }
7946     negptr(cnt2);
7947     jmpb(WHILE_HEAD_LABEL);
7948 
7949     bind(COMPARE_SMALL_STR);
7950   } else if (UseSSE42Intrinsics) {
7951     Label COMPARE_WIDE_VECTORS, VECTOR_NOT_EQUAL, COMPARE_TAIL;
7952     int pcmpmask = 0x19;
7953     // Setup to compare 8-char (16-byte) vectors,
7954     // start from first character again because it has aligned address.
7955     movl(result, cnt2);
7956     andl(cnt2, ~(stride - 1));   // cnt2 holds the vector count
7957     if (ae == StrIntrinsicNode::LL) {
7958       pcmpmask &= ~0x01;
7959     }
7960     jcc(Assembler::zero, COMPARE_TAIL);
7961     if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7962       lea(str1, Address(str1, result, scale));
7963       lea(str2, Address(str2, result, scale));
7964     } else {
7965       lea(str1, Address(str1, result, scale1));
7966       lea(str2, Address(str2, result, scale2));
7967     }
7968     negptr(result);
7969 
7970     // pcmpestri
7971     //   inputs:
7972     //     vec1- substring
7973     //     rax - negative string length (elements count)
7974     //     mem - scanned string
7975     //     rdx - string length (elements count)
7976     //     pcmpmask - cmp mode: 11000 (string compare with negated result)
7977     //               + 00 (unsigned bytes) or  + 01 (unsigned shorts)
7978     //   outputs:
7979     //     rcx - first mismatched element index
7980     assert(result == rax && cnt2 == rdx && cnt1 == rcx, "pcmpestri");
7981 
7982     bind(COMPARE_WIDE_VECTORS);
7983     if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7984       movdqu(vec1, Address(str1, result, scale));
7985       pcmpestri(vec1, Address(str2, result, scale), pcmpmask);
7986     } else {
7987       pmovzxbw(vec1, Address(str1, result, scale1));
7988       pcmpestri(vec1, Address(str2, result, scale2), pcmpmask);
7989     }
7990     // After pcmpestri cnt1(rcx) contains mismatched element index
7991 
7992     jccb(Assembler::below, VECTOR_NOT_EQUAL);  // CF==1
7993     addptr(result, stride);
7994     subptr(cnt2, stride);
7995     jccb(Assembler::notZero, COMPARE_WIDE_VECTORS);
7996 
7997     // compare wide vectors tail
7998     testptr(result, result);
7999     jcc(Assembler::zero, LENGTH_DIFF_LABEL);
8000 
8001     movl(cnt2, stride);
8002     movl(result, stride);
8003     negptr(result);
8004     if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
8005       movdqu(vec1, Address(str1, result, scale));
8006       pcmpestri(vec1, Address(str2, result, scale), pcmpmask);
8007     } else {
8008       pmovzxbw(vec1, Address(str1, result, scale1));
8009       pcmpestri(vec1, Address(str2, result, scale2), pcmpmask);
8010     }
8011     jccb(Assembler::aboveEqual, LENGTH_DIFF_LABEL);
8012 
8013     // Mismatched characters in the vectors
8014     bind(VECTOR_NOT_EQUAL);
8015     addptr(cnt1, result);
8016     load_next_elements(result, cnt2, str1, str2, scale, scale1, scale2, cnt1, ae);
8017     subl(result, cnt2);
8018     jmpb(POP_LABEL);
8019 
8020     bind(COMPARE_TAIL); // limit is zero
8021     movl(cnt2, result);
8022     // Fallthru to tail compare
8023   }
8024   // Shift str2 and str1 to the end of the arrays, negate min
8025   if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
8026     lea(str1, Address(str1, cnt2, scale));
8027     lea(str2, Address(str2, cnt2, scale));
8028   } else {
8029     lea(str1, Address(str1, cnt2, scale1));
8030     lea(str2, Address(str2, cnt2, scale2));
8031   }
8032   decrementl(cnt2);  // first character was compared already
8033   negptr(cnt2);
8034 
8035   // Compare the rest of the elements
8036   bind(WHILE_HEAD_LABEL);
8037   load_next_elements(result, cnt1, str1, str2, scale, scale1, scale2, cnt2, ae);
8038   subl(result, cnt1);
8039   jccb(Assembler::notZero, POP_LABEL);
8040   increment(cnt2);
8041   jccb(Assembler::notZero, WHILE_HEAD_LABEL);
8042 
8043   // Strings are equal up to min length.  Return the length difference.
8044   bind(LENGTH_DIFF_LABEL);
8045   pop(result);
8046   if (ae == StrIntrinsicNode::UU) {
8047     // Divide diff by 2 to get number of chars
8048     sarl(result, 1);
8049   }
8050   jmpb(DONE_LABEL);
8051 
8052 #ifdef _LP64
8053   if (VM_Version::supports_avx512vlbw()) {
8054 
8055     bind(COMPARE_WIDE_VECTORS_LOOP_FAILED);
8056 
8057     kmovql(cnt1, k7);
8058     notq(cnt1);
8059     bsfq(cnt2, cnt1);
8060     if (ae != StrIntrinsicNode::LL) {
8061       // Divide diff by 2 to get number of chars
8062       sarl(cnt2, 1);
8063     }
8064     addq(result, cnt2);
8065     if (ae == StrIntrinsicNode::LL) {
8066       load_unsigned_byte(cnt1, Address(str2, result));
8067       load_unsigned_byte(result, Address(str1, result));
8068     } else if (ae == StrIntrinsicNode::UU) {
8069       load_unsigned_short(cnt1, Address(str2, result, scale));
8070       load_unsigned_short(result, Address(str1, result, scale));
8071     } else {
8072       load_unsigned_short(cnt1, Address(str2, result, scale2));
8073       load_unsigned_byte(result, Address(str1, result, scale1));
8074     }
8075     subl(result, cnt1);
8076     jmpb(POP_LABEL);
8077   }//if (VM_Version::supports_avx512vlbw())
8078 #endif // _LP64
8079 
8080   // Discard the stored length difference
8081   bind(POP_LABEL);
8082   pop(cnt1);
8083 
8084   // That's it
8085   bind(DONE_LABEL);
8086   if(ae == StrIntrinsicNode::UL) {
8087     negl(result);
8088   }
8089 
8090 }
8091 
8092 // Search for Non-ASCII character (Negative byte value) in a byte array,
8093 // return true if it has any and false otherwise.
8094 //   ..\jdk\src\java.base\share\classes\java\lang\StringCoding.java
8095 //   @HotSpotIntrinsicCandidate
8096 //   private static boolean hasNegatives(byte[] ba, int off, int len) {
8097 //     for (int i = off; i < off + len; i++) {
8098 //       if (ba[i] < 0) {
8099 //         return true;
8100 //       }
8101 //     }
8102 //     return false;
8103 //   }
8104 void MacroAssembler::has_negatives(Register ary1, Register len,
8105   Register result, Register tmp1,
8106   XMMRegister vec1, XMMRegister vec2) {
8107   // rsi: byte array
8108   // rcx: len
8109   // rax: result
8110   ShortBranchVerifier sbv(this);
8111   assert_different_registers(ary1, len, result, tmp1);
8112   assert_different_registers(vec1, vec2);
8113   Label TRUE_LABEL, FALSE_LABEL, DONE, COMPARE_CHAR, COMPARE_VECTORS, COMPARE_BYTE;
8114 
8115   // len == 0
8116   testl(len, len);
8117   jcc(Assembler::zero, FALSE_LABEL);
8118 
8119   if ((UseAVX > 2) && // AVX512
8120     VM_Version::supports_avx512vlbw() &&
8121     VM_Version::supports_bmi2()) {
8122 
8123     set_vector_masking();  // opening of the stub context for programming mask registers
8124 
8125     Label test_64_loop, test_tail;
8126     Register tmp3_aliased = len;
8127 
8128     movl(tmp1, len);
8129     vpxor(vec2, vec2, vec2, Assembler::AVX_512bit);
8130 
8131     andl(tmp1, 64 - 1);   // tail count (in chars) 0x3F
8132     andl(len, ~(64 - 1));    // vector count (in chars)
8133     jccb(Assembler::zero, test_tail);
8134 
8135     lea(ary1, Address(ary1, len, Address::times_1));
8136     negptr(len);
8137 
8138     bind(test_64_loop);
8139     // Check whether our 64 elements of size byte contain negatives
8140     evpcmpgtb(k2, vec2, Address(ary1, len, Address::times_1), Assembler::AVX_512bit);
8141     kortestql(k2, k2);
8142     jcc(Assembler::notZero, TRUE_LABEL);
8143 
8144     addptr(len, 64);
8145     jccb(Assembler::notZero, test_64_loop);
8146 
8147 
8148     bind(test_tail);
8149     // bail out when there is nothing to be done
8150     testl(tmp1, -1);
8151     jcc(Assembler::zero, FALSE_LABEL);
8152 
8153     // Save k1
8154     kmovql(k3, k1);
8155 
8156     // ~(~0 << len) applied up to two times (for 32-bit scenario)
8157 #ifdef _LP64
8158     mov64(tmp3_aliased, 0xFFFFFFFFFFFFFFFF);
8159     shlxq(tmp3_aliased, tmp3_aliased, tmp1);
8160     notq(tmp3_aliased);
8161     kmovql(k1, tmp3_aliased);
8162 #else
8163     Label k_init;
8164     jmp(k_init);
8165 
8166     // We could not read 64-bits from a general purpose register thus we move
8167     // data required to compose 64 1's to the instruction stream
8168     // We emit 64 byte wide series of elements from 0..63 which later on would
8169     // be used as a compare targets with tail count contained in tmp1 register.
8170     // Result would be a k1 register having tmp1 consecutive number or 1
8171     // counting from least significant bit.
8172     address tmp = pc();
8173     emit_int64(0x0706050403020100);
8174     emit_int64(0x0F0E0D0C0B0A0908);
8175     emit_int64(0x1716151413121110);
8176     emit_int64(0x1F1E1D1C1B1A1918);
8177     emit_int64(0x2726252423222120);
8178     emit_int64(0x2F2E2D2C2B2A2928);
8179     emit_int64(0x3736353433323130);
8180     emit_int64(0x3F3E3D3C3B3A3938);
8181 
8182     bind(k_init);
8183     lea(len, InternalAddress(tmp));
8184     // create mask to test for negative byte inside a vector
8185     evpbroadcastb(vec1, tmp1, Assembler::AVX_512bit);
8186     evpcmpgtb(k1, vec1, Address(len, 0), Assembler::AVX_512bit);
8187 
8188 #endif
8189     evpcmpgtb(k2, k1, vec2, Address(ary1, 0), Assembler::AVX_512bit);
8190     ktestq(k2, k1);
8191     // Restore k1
8192     kmovql(k1, k3);
8193     jcc(Assembler::notZero, TRUE_LABEL);
8194 
8195     jmp(FALSE_LABEL);
8196 
8197     clear_vector_masking();   // closing of the stub context for programming mask registers
8198   } else {
8199     movl(result, len); // copy
8200 
8201     if (UseAVX == 2 && UseSSE >= 2) {
8202       // With AVX2, use 32-byte vector compare
8203       Label COMPARE_WIDE_VECTORS, COMPARE_TAIL;
8204 
8205       // Compare 32-byte vectors
8206       andl(result, 0x0000001f);  //   tail count (in bytes)
8207       andl(len, 0xffffffe0);   // vector count (in bytes)
8208       jccb(Assembler::zero, COMPARE_TAIL);
8209 
8210       lea(ary1, Address(ary1, len, Address::times_1));
8211       negptr(len);
8212 
8213       movl(tmp1, 0x80808080);   // create mask to test for Unicode chars in vector
8214       movdl(vec2, tmp1);
8215       vpbroadcastd(vec2, vec2);
8216 
8217       bind(COMPARE_WIDE_VECTORS);
8218       vmovdqu(vec1, Address(ary1, len, Address::times_1));
8219       vptest(vec1, vec2);
8220       jccb(Assembler::notZero, TRUE_LABEL);
8221       addptr(len, 32);
8222       jcc(Assembler::notZero, COMPARE_WIDE_VECTORS);
8223 
8224       testl(result, result);
8225       jccb(Assembler::zero, FALSE_LABEL);
8226 
8227       vmovdqu(vec1, Address(ary1, result, Address::times_1, -32));
8228       vptest(vec1, vec2);
8229       jccb(Assembler::notZero, TRUE_LABEL);
8230       jmpb(FALSE_LABEL);
8231 
8232       bind(COMPARE_TAIL); // len is zero
8233       movl(len, result);
8234       // Fallthru to tail compare
8235     } else if (UseSSE42Intrinsics) {
8236       // With SSE4.2, use double quad vector compare
8237       Label COMPARE_WIDE_VECTORS, COMPARE_TAIL;
8238 
8239       // Compare 16-byte vectors
8240       andl(result, 0x0000000f);  //   tail count (in bytes)
8241       andl(len, 0xfffffff0);   // vector count (in bytes)
8242       jccb(Assembler::zero, COMPARE_TAIL);
8243 
8244       lea(ary1, Address(ary1, len, Address::times_1));
8245       negptr(len);
8246 
8247       movl(tmp1, 0x80808080);
8248       movdl(vec2, tmp1);
8249       pshufd(vec2, vec2, 0);
8250 
8251       bind(COMPARE_WIDE_VECTORS);
8252       movdqu(vec1, Address(ary1, len, Address::times_1));
8253       ptest(vec1, vec2);
8254       jccb(Assembler::notZero, TRUE_LABEL);
8255       addptr(len, 16);
8256       jcc(Assembler::notZero, COMPARE_WIDE_VECTORS);
8257 
8258       testl(result, result);
8259       jccb(Assembler::zero, FALSE_LABEL);
8260 
8261       movdqu(vec1, Address(ary1, result, Address::times_1, -16));
8262       ptest(vec1, vec2);
8263       jccb(Assembler::notZero, TRUE_LABEL);
8264       jmpb(FALSE_LABEL);
8265 
8266       bind(COMPARE_TAIL); // len is zero
8267       movl(len, result);
8268       // Fallthru to tail compare
8269     }
8270   }
8271   // Compare 4-byte vectors
8272   andl(len, 0xfffffffc); // vector count (in bytes)
8273   jccb(Assembler::zero, COMPARE_CHAR);
8274 
8275   lea(ary1, Address(ary1, len, Address::times_1));
8276   negptr(len);
8277 
8278   bind(COMPARE_VECTORS);
8279   movl(tmp1, Address(ary1, len, Address::times_1));
8280   andl(tmp1, 0x80808080);
8281   jccb(Assembler::notZero, TRUE_LABEL);
8282   addptr(len, 4);
8283   jcc(Assembler::notZero, COMPARE_VECTORS);
8284 
8285   // Compare trailing char (final 2 bytes), if any
8286   bind(COMPARE_CHAR);
8287   testl(result, 0x2);   // tail  char
8288   jccb(Assembler::zero, COMPARE_BYTE);
8289   load_unsigned_short(tmp1, Address(ary1, 0));
8290   andl(tmp1, 0x00008080);
8291   jccb(Assembler::notZero, TRUE_LABEL);
8292   subptr(result, 2);
8293   lea(ary1, Address(ary1, 2));
8294 
8295   bind(COMPARE_BYTE);
8296   testl(result, 0x1);   // tail  byte
8297   jccb(Assembler::zero, FALSE_LABEL);
8298   load_unsigned_byte(tmp1, Address(ary1, 0));
8299   andl(tmp1, 0x00000080);
8300   jccb(Assembler::notEqual, TRUE_LABEL);
8301   jmpb(FALSE_LABEL);
8302 
8303   bind(TRUE_LABEL);
8304   movl(result, 1);   // return true
8305   jmpb(DONE);
8306 
8307   bind(FALSE_LABEL);
8308   xorl(result, result); // return false
8309 
8310   // That's it
8311   bind(DONE);
8312   if (UseAVX >= 2 && UseSSE >= 2) {
8313     // clean upper bits of YMM registers
8314     vpxor(vec1, vec1);
8315     vpxor(vec2, vec2);
8316   }
8317 }
8318 // Compare char[] or byte[] arrays aligned to 4 bytes or substrings.
8319 void MacroAssembler::arrays_equals(bool is_array_equ, Register ary1, Register ary2,
8320                                    Register limit, Register result, Register chr,
8321                                    XMMRegister vec1, XMMRegister vec2, bool is_char) {
8322   ShortBranchVerifier sbv(this);
8323   Label TRUE_LABEL, FALSE_LABEL, DONE, COMPARE_VECTORS, COMPARE_CHAR, COMPARE_BYTE;
8324 
8325   int length_offset  = arrayOopDesc::length_offset_in_bytes();
8326   int base_offset    = arrayOopDesc::base_offset_in_bytes(is_char ? T_CHAR : T_BYTE);
8327 
8328   if (is_array_equ) {
8329     // Check the input args
8330     cmpptr(ary1, ary2);
8331     jcc(Assembler::equal, TRUE_LABEL);
8332 
8333     // Need additional checks for arrays_equals.
8334     testptr(ary1, ary1);
8335     jcc(Assembler::zero, FALSE_LABEL);
8336     testptr(ary2, ary2);
8337     jcc(Assembler::zero, FALSE_LABEL);
8338 
8339     // Check the lengths
8340     movl(limit, Address(ary1, length_offset));
8341     cmpl(limit, Address(ary2, length_offset));
8342     jcc(Assembler::notEqual, FALSE_LABEL);
8343   }
8344 
8345   // count == 0
8346   testl(limit, limit);
8347   jcc(Assembler::zero, TRUE_LABEL);
8348 
8349   if (is_array_equ) {
8350     // Load array address
8351     lea(ary1, Address(ary1, base_offset));
8352     lea(ary2, Address(ary2, base_offset));
8353   }
8354 
8355   if (is_array_equ && is_char) {
8356     // arrays_equals when used for char[].
8357     shll(limit, 1);      // byte count != 0
8358   }
8359   movl(result, limit); // copy
8360 
8361   if (UseAVX >= 2) {
8362     // With AVX2, use 32-byte vector compare
8363     Label COMPARE_WIDE_VECTORS, COMPARE_TAIL;
8364 
8365     // Compare 32-byte vectors
8366     andl(result, 0x0000001f);  //   tail count (in bytes)
8367     andl(limit, 0xffffffe0);   // vector count (in bytes)
8368     jcc(Assembler::zero, COMPARE_TAIL);
8369 
8370     lea(ary1, Address(ary1, limit, Address::times_1));
8371     lea(ary2, Address(ary2, limit, Address::times_1));
8372     negptr(limit);
8373 
8374     bind(COMPARE_WIDE_VECTORS);
8375 
8376 #ifdef _LP64
8377     if (VM_Version::supports_avx512vlbw()) { // trying 64 bytes fast loop
8378       Label COMPARE_WIDE_VECTORS_LOOP_AVX2, COMPARE_WIDE_VECTORS_LOOP_AVX3;
8379 
8380       cmpl(limit, -64);
8381       jccb(Assembler::greater, COMPARE_WIDE_VECTORS_LOOP_AVX2);
8382 
8383       bind(COMPARE_WIDE_VECTORS_LOOP_AVX3); // the hottest loop
8384 
8385       evmovdquq(vec1, Address(ary1, limit, Address::times_1), Assembler::AVX_512bit);
8386       evpcmpeqb(k7, vec1, Address(ary2, limit, Address::times_1), Assembler::AVX_512bit);
8387       kortestql(k7, k7);
8388       jcc(Assembler::aboveEqual, FALSE_LABEL);     // miscompare
8389       addptr(limit, 64);  // update since we already compared at this addr
8390       cmpl(limit, -64);
8391       jccb(Assembler::lessEqual, COMPARE_WIDE_VECTORS_LOOP_AVX3);
8392 
8393       // At this point we may still need to compare -limit+result bytes.
8394       // We could execute the next two instruction and just continue via non-wide path:
8395       //  cmpl(limit, 0);
8396       //  jcc(Assembler::equal, COMPARE_TAIL);  // true
8397       // But since we stopped at the points ary{1,2}+limit which are
8398       // not farther than 64 bytes from the ends of arrays ary{1,2}+result
8399       // (|limit| <= 32 and result < 32),
8400       // we may just compare the last 64 bytes.
8401       //
8402       addptr(result, -64);   // it is safe, bc we just came from this area
8403       evmovdquq(vec1, Address(ary1, result, Address::times_1), Assembler::AVX_512bit);
8404       evpcmpeqb(k7, vec1, Address(ary2, result, Address::times_1), Assembler::AVX_512bit);
8405       kortestql(k7, k7);
8406       jcc(Assembler::aboveEqual, FALSE_LABEL);     // miscompare
8407 
8408       jmp(TRUE_LABEL);
8409 
8410       bind(COMPARE_WIDE_VECTORS_LOOP_AVX2);
8411 
8412     }//if (VM_Version::supports_avx512vlbw())
8413 #endif //_LP64
8414 
8415     vmovdqu(vec1, Address(ary1, limit, Address::times_1));
8416     vmovdqu(vec2, Address(ary2, limit, Address::times_1));
8417     vpxor(vec1, vec2);
8418 
8419     vptest(vec1, vec1);
8420     jcc(Assembler::notZero, FALSE_LABEL);
8421     addptr(limit, 32);
8422     jcc(Assembler::notZero, COMPARE_WIDE_VECTORS);
8423 
8424     testl(result, result);
8425     jcc(Assembler::zero, TRUE_LABEL);
8426 
8427     vmovdqu(vec1, Address(ary1, result, Address::times_1, -32));
8428     vmovdqu(vec2, Address(ary2, result, Address::times_1, -32));
8429     vpxor(vec1, vec2);
8430 
8431     vptest(vec1, vec1);
8432     jccb(Assembler::notZero, FALSE_LABEL);
8433     jmpb(TRUE_LABEL);
8434 
8435     bind(COMPARE_TAIL); // limit is zero
8436     movl(limit, result);
8437     // Fallthru to tail compare
8438   } else if (UseSSE42Intrinsics) {
8439     // With SSE4.2, use double quad vector compare
8440     Label COMPARE_WIDE_VECTORS, COMPARE_TAIL;
8441 
8442     // Compare 16-byte vectors
8443     andl(result, 0x0000000f);  //   tail count (in bytes)
8444     andl(limit, 0xfffffff0);   // vector count (in bytes)
8445     jcc(Assembler::zero, COMPARE_TAIL);
8446 
8447     lea(ary1, Address(ary1, limit, Address::times_1));
8448     lea(ary2, Address(ary2, limit, Address::times_1));
8449     negptr(limit);
8450 
8451     bind(COMPARE_WIDE_VECTORS);
8452     movdqu(vec1, Address(ary1, limit, Address::times_1));
8453     movdqu(vec2, Address(ary2, limit, Address::times_1));
8454     pxor(vec1, vec2);
8455 
8456     ptest(vec1, vec1);
8457     jcc(Assembler::notZero, FALSE_LABEL);
8458     addptr(limit, 16);
8459     jcc(Assembler::notZero, COMPARE_WIDE_VECTORS);
8460 
8461     testl(result, result);
8462     jcc(Assembler::zero, TRUE_LABEL);
8463 
8464     movdqu(vec1, Address(ary1, result, Address::times_1, -16));
8465     movdqu(vec2, Address(ary2, result, Address::times_1, -16));
8466     pxor(vec1, vec2);
8467 
8468     ptest(vec1, vec1);
8469     jccb(Assembler::notZero, FALSE_LABEL);
8470     jmpb(TRUE_LABEL);
8471 
8472     bind(COMPARE_TAIL); // limit is zero
8473     movl(limit, result);
8474     // Fallthru to tail compare
8475   }
8476 
8477   // Compare 4-byte vectors
8478   andl(limit, 0xfffffffc); // vector count (in bytes)
8479   jccb(Assembler::zero, COMPARE_CHAR);
8480 
8481   lea(ary1, Address(ary1, limit, Address::times_1));
8482   lea(ary2, Address(ary2, limit, Address::times_1));
8483   negptr(limit);
8484 
8485   bind(COMPARE_VECTORS);
8486   movl(chr, Address(ary1, limit, Address::times_1));
8487   cmpl(chr, Address(ary2, limit, Address::times_1));
8488   jccb(Assembler::notEqual, FALSE_LABEL);
8489   addptr(limit, 4);
8490   jcc(Assembler::notZero, COMPARE_VECTORS);
8491 
8492   // Compare trailing char (final 2 bytes), if any
8493   bind(COMPARE_CHAR);
8494   testl(result, 0x2);   // tail  char
8495   jccb(Assembler::zero, COMPARE_BYTE);
8496   load_unsigned_short(chr, Address(ary1, 0));
8497   load_unsigned_short(limit, Address(ary2, 0));
8498   cmpl(chr, limit);
8499   jccb(Assembler::notEqual, FALSE_LABEL);
8500 
8501   if (is_array_equ && is_char) {
8502     bind(COMPARE_BYTE);
8503   } else {
8504     lea(ary1, Address(ary1, 2));
8505     lea(ary2, Address(ary2, 2));
8506 
8507     bind(COMPARE_BYTE);
8508     testl(result, 0x1);   // tail  byte
8509     jccb(Assembler::zero, TRUE_LABEL);
8510     load_unsigned_byte(chr, Address(ary1, 0));
8511     load_unsigned_byte(limit, Address(ary2, 0));
8512     cmpl(chr, limit);
8513     jccb(Assembler::notEqual, FALSE_LABEL);
8514   }
8515   bind(TRUE_LABEL);
8516   movl(result, 1);   // return true
8517   jmpb(DONE);
8518 
8519   bind(FALSE_LABEL);
8520   xorl(result, result); // return false
8521 
8522   // That's it
8523   bind(DONE);
8524   if (UseAVX >= 2) {
8525     // clean upper bits of YMM registers
8526     vpxor(vec1, vec1);
8527     vpxor(vec2, vec2);
8528   }
8529 }
8530 
8531 #endif
8532 
8533 void MacroAssembler::generate_fill(BasicType t, bool aligned,
8534                                    Register to, Register value, Register count,
8535                                    Register rtmp, XMMRegister xtmp) {
8536   ShortBranchVerifier sbv(this);
8537   assert_different_registers(to, value, count, rtmp);
8538   Label L_exit, L_skip_align1, L_skip_align2, L_fill_byte;
8539   Label L_fill_2_bytes, L_fill_4_bytes;
8540 
8541   int shift = -1;
8542   switch (t) {
8543     case T_BYTE:
8544       shift = 2;
8545       break;
8546     case T_SHORT:
8547       shift = 1;
8548       break;
8549     case T_INT:
8550       shift = 0;
8551       break;
8552     default: ShouldNotReachHere();
8553   }
8554 
8555   if (t == T_BYTE) {
8556     andl(value, 0xff);
8557     movl(rtmp, value);
8558     shll(rtmp, 8);
8559     orl(value, rtmp);
8560   }
8561   if (t == T_SHORT) {
8562     andl(value, 0xffff);
8563   }
8564   if (t == T_BYTE || t == T_SHORT) {
8565     movl(rtmp, value);
8566     shll(rtmp, 16);
8567     orl(value, rtmp);
8568   }
8569 
8570   cmpl(count, 2<<shift); // Short arrays (< 8 bytes) fill by element
8571   jcc(Assembler::below, L_fill_4_bytes); // use unsigned cmp
8572   if (!UseUnalignedLoadStores && !aligned && (t == T_BYTE || t == T_SHORT)) {
8573     // align source address at 4 bytes address boundary
8574     if (t == T_BYTE) {
8575       // One byte misalignment happens only for byte arrays
8576       testptr(to, 1);
8577       jccb(Assembler::zero, L_skip_align1);
8578       movb(Address(to, 0), value);
8579       increment(to);
8580       decrement(count);
8581       BIND(L_skip_align1);
8582     }
8583     // Two bytes misalignment happens only for byte and short (char) arrays
8584     testptr(to, 2);
8585     jccb(Assembler::zero, L_skip_align2);
8586     movw(Address(to, 0), value);
8587     addptr(to, 2);
8588     subl(count, 1<<(shift-1));
8589     BIND(L_skip_align2);
8590   }
8591   if (UseSSE < 2) {
8592     Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes;
8593     // Fill 32-byte chunks
8594     subl(count, 8 << shift);
8595     jcc(Assembler::less, L_check_fill_8_bytes);
8596     align(16);
8597 
8598     BIND(L_fill_32_bytes_loop);
8599 
8600     for (int i = 0; i < 32; i += 4) {
8601       movl(Address(to, i), value);
8602     }
8603 
8604     addptr(to, 32);
8605     subl(count, 8 << shift);
8606     jcc(Assembler::greaterEqual, L_fill_32_bytes_loop);
8607     BIND(L_check_fill_8_bytes);
8608     addl(count, 8 << shift);
8609     jccb(Assembler::zero, L_exit);
8610     jmpb(L_fill_8_bytes);
8611 
8612     //
8613     // length is too short, just fill qwords
8614     //
8615     BIND(L_fill_8_bytes_loop);
8616     movl(Address(to, 0), value);
8617     movl(Address(to, 4), value);
8618     addptr(to, 8);
8619     BIND(L_fill_8_bytes);
8620     subl(count, 1 << (shift + 1));
8621     jcc(Assembler::greaterEqual, L_fill_8_bytes_loop);
8622     // fall through to fill 4 bytes
8623   } else {
8624     Label L_fill_32_bytes;
8625     if (!UseUnalignedLoadStores) {
8626       // align to 8 bytes, we know we are 4 byte aligned to start
8627       testptr(to, 4);
8628       jccb(Assembler::zero, L_fill_32_bytes);
8629       movl(Address(to, 0), value);
8630       addptr(to, 4);
8631       subl(count, 1<<shift);
8632     }
8633     BIND(L_fill_32_bytes);
8634     {
8635       assert( UseSSE >= 2, "supported cpu only" );
8636       Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes;
8637       if (UseAVX > 2) {
8638         movl(rtmp, 0xffff);
8639         kmovwl(k1, rtmp);
8640       }
8641       movdl(xtmp, value);
8642       if (UseAVX > 2 && UseUnalignedLoadStores) {
8643         // Fill 64-byte chunks
8644         Label L_fill_64_bytes_loop, L_check_fill_32_bytes;
8645         evpbroadcastd(xtmp, xtmp, Assembler::AVX_512bit);
8646 
8647         subl(count, 16 << shift);
8648         jcc(Assembler::less, L_check_fill_32_bytes);
8649         align(16);
8650 
8651         BIND(L_fill_64_bytes_loop);
8652         evmovdqul(Address(to, 0), xtmp, Assembler::AVX_512bit);
8653         addptr(to, 64);
8654         subl(count, 16 << shift);
8655         jcc(Assembler::greaterEqual, L_fill_64_bytes_loop);
8656 
8657         BIND(L_check_fill_32_bytes);
8658         addl(count, 8 << shift);
8659         jccb(Assembler::less, L_check_fill_8_bytes);
8660         vmovdqu(Address(to, 0), xtmp);
8661         addptr(to, 32);
8662         subl(count, 8 << shift);
8663 
8664         BIND(L_check_fill_8_bytes);
8665       } else if (UseAVX == 2 && UseUnalignedLoadStores) {
8666         // Fill 64-byte chunks
8667         Label L_fill_64_bytes_loop, L_check_fill_32_bytes;
8668         vpbroadcastd(xtmp, xtmp);
8669 
8670         subl(count, 16 << shift);
8671         jcc(Assembler::less, L_check_fill_32_bytes);
8672         align(16);
8673 
8674         BIND(L_fill_64_bytes_loop);
8675         vmovdqu(Address(to, 0), xtmp);
8676         vmovdqu(Address(to, 32), xtmp);
8677         addptr(to, 64);
8678         subl(count, 16 << shift);
8679         jcc(Assembler::greaterEqual, L_fill_64_bytes_loop);
8680 
8681         BIND(L_check_fill_32_bytes);
8682         addl(count, 8 << shift);
8683         jccb(Assembler::less, L_check_fill_8_bytes);
8684         vmovdqu(Address(to, 0), xtmp);
8685         addptr(to, 32);
8686         subl(count, 8 << shift);
8687 
8688         BIND(L_check_fill_8_bytes);
8689         // clean upper bits of YMM registers
8690         movdl(xtmp, value);
8691         pshufd(xtmp, xtmp, 0);
8692       } else {
8693         // Fill 32-byte chunks
8694         pshufd(xtmp, xtmp, 0);
8695 
8696         subl(count, 8 << shift);
8697         jcc(Assembler::less, L_check_fill_8_bytes);
8698         align(16);
8699 
8700         BIND(L_fill_32_bytes_loop);
8701 
8702         if (UseUnalignedLoadStores) {
8703           movdqu(Address(to, 0), xtmp);
8704           movdqu(Address(to, 16), xtmp);
8705         } else {
8706           movq(Address(to, 0), xtmp);
8707           movq(Address(to, 8), xtmp);
8708           movq(Address(to, 16), xtmp);
8709           movq(Address(to, 24), xtmp);
8710         }
8711 
8712         addptr(to, 32);
8713         subl(count, 8 << shift);
8714         jcc(Assembler::greaterEqual, L_fill_32_bytes_loop);
8715 
8716         BIND(L_check_fill_8_bytes);
8717       }
8718       addl(count, 8 << shift);
8719       jccb(Assembler::zero, L_exit);
8720       jmpb(L_fill_8_bytes);
8721 
8722       //
8723       // length is too short, just fill qwords
8724       //
8725       BIND(L_fill_8_bytes_loop);
8726       movq(Address(to, 0), xtmp);
8727       addptr(to, 8);
8728       BIND(L_fill_8_bytes);
8729       subl(count, 1 << (shift + 1));
8730       jcc(Assembler::greaterEqual, L_fill_8_bytes_loop);
8731     }
8732   }
8733   // fill trailing 4 bytes
8734   BIND(L_fill_4_bytes);
8735   testl(count, 1<<shift);
8736   jccb(Assembler::zero, L_fill_2_bytes);
8737   movl(Address(to, 0), value);
8738   if (t == T_BYTE || t == T_SHORT) {
8739     addptr(to, 4);
8740     BIND(L_fill_2_bytes);
8741     // fill trailing 2 bytes
8742     testl(count, 1<<(shift-1));
8743     jccb(Assembler::zero, L_fill_byte);
8744     movw(Address(to, 0), value);
8745     if (t == T_BYTE) {
8746       addptr(to, 2);
8747       BIND(L_fill_byte);
8748       // fill trailing byte
8749       testl(count, 1);
8750       jccb(Assembler::zero, L_exit);
8751       movb(Address(to, 0), value);
8752     } else {
8753       BIND(L_fill_byte);
8754     }
8755   } else {
8756     BIND(L_fill_2_bytes);
8757   }
8758   BIND(L_exit);
8759 }
8760 
8761 // encode char[] to byte[] in ISO_8859_1
8762    //@HotSpotIntrinsicCandidate
8763    //private static int implEncodeISOArray(byte[] sa, int sp,
8764    //byte[] da, int dp, int len) {
8765    //  int i = 0;
8766    //  for (; i < len; i++) {
8767    //    char c = StringUTF16.getChar(sa, sp++);
8768    //    if (c > '\u00FF')
8769    //      break;
8770    //    da[dp++] = (byte)c;
8771    //  }
8772    //  return i;
8773    //}
8774 void MacroAssembler::encode_iso_array(Register src, Register dst, Register len,
8775   XMMRegister tmp1Reg, XMMRegister tmp2Reg,
8776   XMMRegister tmp3Reg, XMMRegister tmp4Reg,
8777   Register tmp5, Register result) {
8778 
8779   // rsi: src
8780   // rdi: dst
8781   // rdx: len
8782   // rcx: tmp5
8783   // rax: result
8784   ShortBranchVerifier sbv(this);
8785   assert_different_registers(src, dst, len, tmp5, result);
8786   Label L_done, L_copy_1_char, L_copy_1_char_exit;
8787 
8788   // set result
8789   xorl(result, result);
8790   // check for zero length
8791   testl(len, len);
8792   jcc(Assembler::zero, L_done);
8793 
8794   movl(result, len);
8795 
8796   // Setup pointers
8797   lea(src, Address(src, len, Address::times_2)); // char[]
8798   lea(dst, Address(dst, len, Address::times_1)); // byte[]
8799   negptr(len);
8800 
8801   if (UseSSE42Intrinsics || UseAVX >= 2) {
8802     Label L_chars_8_check, L_copy_8_chars, L_copy_8_chars_exit;
8803     Label L_chars_16_check, L_copy_16_chars, L_copy_16_chars_exit;
8804 
8805     if (UseAVX >= 2) {
8806       Label L_chars_32_check, L_copy_32_chars, L_copy_32_chars_exit;
8807       movl(tmp5, 0xff00ff00);   // create mask to test for Unicode chars in vector
8808       movdl(tmp1Reg, tmp5);
8809       vpbroadcastd(tmp1Reg, tmp1Reg);
8810       jmp(L_chars_32_check);
8811 
8812       bind(L_copy_32_chars);
8813       vmovdqu(tmp3Reg, Address(src, len, Address::times_2, -64));
8814       vmovdqu(tmp4Reg, Address(src, len, Address::times_2, -32));
8815       vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector_len */ 1);
8816       vptest(tmp2Reg, tmp1Reg);       // check for Unicode chars in  vector
8817       jccb(Assembler::notZero, L_copy_32_chars_exit);
8818       vpackuswb(tmp3Reg, tmp3Reg, tmp4Reg, /* vector_len */ 1);
8819       vpermq(tmp4Reg, tmp3Reg, 0xD8, /* vector_len */ 1);
8820       vmovdqu(Address(dst, len, Address::times_1, -32), tmp4Reg);
8821 
8822       bind(L_chars_32_check);
8823       addptr(len, 32);
8824       jcc(Assembler::lessEqual, L_copy_32_chars);
8825 
8826       bind(L_copy_32_chars_exit);
8827       subptr(len, 16);
8828       jccb(Assembler::greater, L_copy_16_chars_exit);
8829 
8830     } else if (UseSSE42Intrinsics) {
8831       movl(tmp5, 0xff00ff00);   // create mask to test for Unicode chars in vector
8832       movdl(tmp1Reg, tmp5);
8833       pshufd(tmp1Reg, tmp1Reg, 0);
8834       jmpb(L_chars_16_check);
8835     }
8836 
8837     bind(L_copy_16_chars);
8838     if (UseAVX >= 2) {
8839       vmovdqu(tmp2Reg, Address(src, len, Address::times_2, -32));
8840       vptest(tmp2Reg, tmp1Reg);
8841       jcc(Assembler::notZero, L_copy_16_chars_exit);
8842       vpackuswb(tmp2Reg, tmp2Reg, tmp1Reg, /* vector_len */ 1);
8843       vpermq(tmp3Reg, tmp2Reg, 0xD8, /* vector_len */ 1);
8844     } else {
8845       if (UseAVX > 0) {
8846         movdqu(tmp3Reg, Address(src, len, Address::times_2, -32));
8847         movdqu(tmp4Reg, Address(src, len, Address::times_2, -16));
8848         vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector_len */ 0);
8849       } else {
8850         movdqu(tmp3Reg, Address(src, len, Address::times_2, -32));
8851         por(tmp2Reg, tmp3Reg);
8852         movdqu(tmp4Reg, Address(src, len, Address::times_2, -16));
8853         por(tmp2Reg, tmp4Reg);
8854       }
8855       ptest(tmp2Reg, tmp1Reg);       // check for Unicode chars in  vector
8856       jccb(Assembler::notZero, L_copy_16_chars_exit);
8857       packuswb(tmp3Reg, tmp4Reg);
8858     }
8859     movdqu(Address(dst, len, Address::times_1, -16), tmp3Reg);
8860 
8861     bind(L_chars_16_check);
8862     addptr(len, 16);
8863     jcc(Assembler::lessEqual, L_copy_16_chars);
8864 
8865     bind(L_copy_16_chars_exit);
8866     if (UseAVX >= 2) {
8867       // clean upper bits of YMM registers
8868       vpxor(tmp2Reg, tmp2Reg);
8869       vpxor(tmp3Reg, tmp3Reg);
8870       vpxor(tmp4Reg, tmp4Reg);
8871       movdl(tmp1Reg, tmp5);
8872       pshufd(tmp1Reg, tmp1Reg, 0);
8873     }
8874     subptr(len, 8);
8875     jccb(Assembler::greater, L_copy_8_chars_exit);
8876 
8877     bind(L_copy_8_chars);
8878     movdqu(tmp3Reg, Address(src, len, Address::times_2, -16));
8879     ptest(tmp3Reg, tmp1Reg);
8880     jccb(Assembler::notZero, L_copy_8_chars_exit);
8881     packuswb(tmp3Reg, tmp1Reg);
8882     movq(Address(dst, len, Address::times_1, -8), tmp3Reg);
8883     addptr(len, 8);
8884     jccb(Assembler::lessEqual, L_copy_8_chars);
8885 
8886     bind(L_copy_8_chars_exit);
8887     subptr(len, 8);
8888     jccb(Assembler::zero, L_done);
8889   }
8890 
8891   bind(L_copy_1_char);
8892   load_unsigned_short(tmp5, Address(src, len, Address::times_2, 0));
8893   testl(tmp5, 0xff00);      // check if Unicode char
8894   jccb(Assembler::notZero, L_copy_1_char_exit);
8895   movb(Address(dst, len, Address::times_1, 0), tmp5);
8896   addptr(len, 1);
8897   jccb(Assembler::less, L_copy_1_char);
8898 
8899   bind(L_copy_1_char_exit);
8900   addptr(result, len); // len is negative count of not processed elements
8901 
8902   bind(L_done);
8903 }
8904 
8905 #ifdef _LP64
8906 /**
8907  * Helper for multiply_to_len().
8908  */
8909 void MacroAssembler::add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2) {
8910   addq(dest_lo, src1);
8911   adcq(dest_hi, 0);
8912   addq(dest_lo, src2);
8913   adcq(dest_hi, 0);
8914 }
8915 
8916 /**
8917  * Multiply 64 bit by 64 bit first loop.
8918  */
8919 void MacroAssembler::multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
8920                                            Register y, Register y_idx, Register z,
8921                                            Register carry, Register product,
8922                                            Register idx, Register kdx) {
8923   //
8924   //  jlong carry, x[], y[], z[];
8925   //  for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
8926   //    huge_128 product = y[idx] * x[xstart] + carry;
8927   //    z[kdx] = (jlong)product;
8928   //    carry  = (jlong)(product >>> 64);
8929   //  }
8930   //  z[xstart] = carry;
8931   //
8932 
8933   Label L_first_loop, L_first_loop_exit;
8934   Label L_one_x, L_one_y, L_multiply;
8935 
8936   decrementl(xstart);
8937   jcc(Assembler::negative, L_one_x);
8938 
8939   movq(x_xstart, Address(x, xstart, Address::times_4,  0));
8940   rorq(x_xstart, 32); // convert big-endian to little-endian
8941 
8942   bind(L_first_loop);
8943   decrementl(idx);
8944   jcc(Assembler::negative, L_first_loop_exit);
8945   decrementl(idx);
8946   jcc(Assembler::negative, L_one_y);
8947   movq(y_idx, Address(y, idx, Address::times_4,  0));
8948   rorq(y_idx, 32); // convert big-endian to little-endian
8949   bind(L_multiply);
8950   movq(product, x_xstart);
8951   mulq(y_idx); // product(rax) * y_idx -> rdx:rax
8952   addq(product, carry);
8953   adcq(rdx, 0);
8954   subl(kdx, 2);
8955   movl(Address(z, kdx, Address::times_4,  4), product);
8956   shrq(product, 32);
8957   movl(Address(z, kdx, Address::times_4,  0), product);
8958   movq(carry, rdx);
8959   jmp(L_first_loop);
8960 
8961   bind(L_one_y);
8962   movl(y_idx, Address(y,  0));
8963   jmp(L_multiply);
8964 
8965   bind(L_one_x);
8966   movl(x_xstart, Address(x,  0));
8967   jmp(L_first_loop);
8968 
8969   bind(L_first_loop_exit);
8970 }
8971 
8972 /**
8973  * Multiply 64 bit by 64 bit and add 128 bit.
8974  */
8975 void MacroAssembler::multiply_add_128_x_128(Register x_xstart, Register y, Register z,
8976                                             Register yz_idx, Register idx,
8977                                             Register carry, Register product, int offset) {
8978   //     huge_128 product = (y[idx] * x_xstart) + z[kdx] + carry;
8979   //     z[kdx] = (jlong)product;
8980 
8981   movq(yz_idx, Address(y, idx, Address::times_4,  offset));
8982   rorq(yz_idx, 32); // convert big-endian to little-endian
8983   movq(product, x_xstart);
8984   mulq(yz_idx);     // product(rax) * yz_idx -> rdx:product(rax)
8985   movq(yz_idx, Address(z, idx, Address::times_4,  offset));
8986   rorq(yz_idx, 32); // convert big-endian to little-endian
8987 
8988   add2_with_carry(rdx, product, carry, yz_idx);
8989 
8990   movl(Address(z, idx, Address::times_4,  offset+4), product);
8991   shrq(product, 32);
8992   movl(Address(z, idx, Address::times_4,  offset), product);
8993 
8994 }
8995 
8996 /**
8997  * Multiply 128 bit by 128 bit. Unrolled inner loop.
8998  */
8999 void MacroAssembler::multiply_128_x_128_loop(Register x_xstart, Register y, Register z,
9000                                              Register yz_idx, Register idx, Register jdx,
9001                                              Register carry, Register product,
9002                                              Register carry2) {
9003   //   jlong carry, x[], y[], z[];
9004   //   int kdx = ystart+1;
9005   //   for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop
9006   //     huge_128 product = (y[idx+1] * x_xstart) + z[kdx+idx+1] + carry;
9007   //     z[kdx+idx+1] = (jlong)product;
9008   //     jlong carry2  = (jlong)(product >>> 64);
9009   //     product = (y[idx] * x_xstart) + z[kdx+idx] + carry2;
9010   //     z[kdx+idx] = (jlong)product;
9011   //     carry  = (jlong)(product >>> 64);
9012   //   }
9013   //   idx += 2;
9014   //   if (idx > 0) {
9015   //     product = (y[idx] * x_xstart) + z[kdx+idx] + carry;
9016   //     z[kdx+idx] = (jlong)product;
9017   //     carry  = (jlong)(product >>> 64);
9018   //   }
9019   //
9020 
9021   Label L_third_loop, L_third_loop_exit, L_post_third_loop_done;
9022 
9023   movl(jdx, idx);
9024   andl(jdx, 0xFFFFFFFC);
9025   shrl(jdx, 2);
9026 
9027   bind(L_third_loop);
9028   subl(jdx, 1);
9029   jcc(Assembler::negative, L_third_loop_exit);
9030   subl(idx, 4);
9031 
9032   multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry, product, 8);
9033   movq(carry2, rdx);
9034 
9035   multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry2, product, 0);
9036   movq(carry, rdx);
9037   jmp(L_third_loop);
9038 
9039   bind (L_third_loop_exit);
9040 
9041   andl (idx, 0x3);
9042   jcc(Assembler::zero, L_post_third_loop_done);
9043 
9044   Label L_check_1;
9045   subl(idx, 2);
9046   jcc(Assembler::negative, L_check_1);
9047 
9048   multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry, product, 0);
9049   movq(carry, rdx);
9050 
9051   bind (L_check_1);
9052   addl (idx, 0x2);
9053   andl (idx, 0x1);
9054   subl(idx, 1);
9055   jcc(Assembler::negative, L_post_third_loop_done);
9056 
9057   movl(yz_idx, Address(y, idx, Address::times_4,  0));
9058   movq(product, x_xstart);
9059   mulq(yz_idx); // product(rax) * yz_idx -> rdx:product(rax)
9060   movl(yz_idx, Address(z, idx, Address::times_4,  0));
9061 
9062   add2_with_carry(rdx, product, yz_idx, carry);
9063 
9064   movl(Address(z, idx, Address::times_4,  0), product);
9065   shrq(product, 32);
9066 
9067   shlq(rdx, 32);
9068   orq(product, rdx);
9069   movq(carry, product);
9070 
9071   bind(L_post_third_loop_done);
9072 }
9073 
9074 /**
9075  * Multiply 128 bit by 128 bit using BMI2. Unrolled inner loop.
9076  *
9077  */
9078 void MacroAssembler::multiply_128_x_128_bmi2_loop(Register y, Register z,
9079                                                   Register carry, Register carry2,
9080                                                   Register idx, Register jdx,
9081                                                   Register yz_idx1, Register yz_idx2,
9082                                                   Register tmp, Register tmp3, Register tmp4) {
9083   assert(UseBMI2Instructions, "should be used only when BMI2 is available");
9084 
9085   //   jlong carry, x[], y[], z[];
9086   //   int kdx = ystart+1;
9087   //   for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop
9088   //     huge_128 tmp3 = (y[idx+1] * rdx) + z[kdx+idx+1] + carry;
9089   //     jlong carry2  = (jlong)(tmp3 >>> 64);
9090   //     huge_128 tmp4 = (y[idx]   * rdx) + z[kdx+idx] + carry2;
9091   //     carry  = (jlong)(tmp4 >>> 64);
9092   //     z[kdx+idx+1] = (jlong)tmp3;
9093   //     z[kdx+idx] = (jlong)tmp4;
9094   //   }
9095   //   idx += 2;
9096   //   if (idx > 0) {
9097   //     yz_idx1 = (y[idx] * rdx) + z[kdx+idx] + carry;
9098   //     z[kdx+idx] = (jlong)yz_idx1;
9099   //     carry  = (jlong)(yz_idx1 >>> 64);
9100   //   }
9101   //
9102 
9103   Label L_third_loop, L_third_loop_exit, L_post_third_loop_done;
9104 
9105   movl(jdx, idx);
9106   andl(jdx, 0xFFFFFFFC);
9107   shrl(jdx, 2);
9108 
9109   bind(L_third_loop);
9110   subl(jdx, 1);
9111   jcc(Assembler::negative, L_third_loop_exit);
9112   subl(idx, 4);
9113 
9114   movq(yz_idx1,  Address(y, idx, Address::times_4,  8));
9115   rorxq(yz_idx1, yz_idx1, 32); // convert big-endian to little-endian
9116   movq(yz_idx2, Address(y, idx, Address::times_4,  0));
9117   rorxq(yz_idx2, yz_idx2, 32);
9118 
9119   mulxq(tmp4, tmp3, yz_idx1);  //  yz_idx1 * rdx -> tmp4:tmp3
9120   mulxq(carry2, tmp, yz_idx2); //  yz_idx2 * rdx -> carry2:tmp
9121 
9122   movq(yz_idx1,  Address(z, idx, Address::times_4,  8));
9123   rorxq(yz_idx1, yz_idx1, 32);
9124   movq(yz_idx2, Address(z, idx, Address::times_4,  0));
9125   rorxq(yz_idx2, yz_idx2, 32);
9126 
9127   if (VM_Version::supports_adx()) {
9128     adcxq(tmp3, carry);
9129     adoxq(tmp3, yz_idx1);
9130 
9131     adcxq(tmp4, tmp);
9132     adoxq(tmp4, yz_idx2);
9133 
9134     movl(carry, 0); // does not affect flags
9135     adcxq(carry2, carry);
9136     adoxq(carry2, carry);
9137   } else {
9138     add2_with_carry(tmp4, tmp3, carry, yz_idx1);
9139     add2_with_carry(carry2, tmp4, tmp, yz_idx2);
9140   }
9141   movq(carry, carry2);
9142 
9143   movl(Address(z, idx, Address::times_4, 12), tmp3);
9144   shrq(tmp3, 32);
9145   movl(Address(z, idx, Address::times_4,  8), tmp3);
9146 
9147   movl(Address(z, idx, Address::times_4,  4), tmp4);
9148   shrq(tmp4, 32);
9149   movl(Address(z, idx, Address::times_4,  0), tmp4);
9150 
9151   jmp(L_third_loop);
9152 
9153   bind (L_third_loop_exit);
9154 
9155   andl (idx, 0x3);
9156   jcc(Assembler::zero, L_post_third_loop_done);
9157 
9158   Label L_check_1;
9159   subl(idx, 2);
9160   jcc(Assembler::negative, L_check_1);
9161 
9162   movq(yz_idx1, Address(y, idx, Address::times_4,  0));
9163   rorxq(yz_idx1, yz_idx1, 32);
9164   mulxq(tmp4, tmp3, yz_idx1); //  yz_idx1 * rdx -> tmp4:tmp3
9165   movq(yz_idx2, Address(z, idx, Address::times_4,  0));
9166   rorxq(yz_idx2, yz_idx2, 32);
9167 
9168   add2_with_carry(tmp4, tmp3, carry, yz_idx2);
9169 
9170   movl(Address(z, idx, Address::times_4,  4), tmp3);
9171   shrq(tmp3, 32);
9172   movl(Address(z, idx, Address::times_4,  0), tmp3);
9173   movq(carry, tmp4);
9174 
9175   bind (L_check_1);
9176   addl (idx, 0x2);
9177   andl (idx, 0x1);
9178   subl(idx, 1);
9179   jcc(Assembler::negative, L_post_third_loop_done);
9180   movl(tmp4, Address(y, idx, Address::times_4,  0));
9181   mulxq(carry2, tmp3, tmp4);  //  tmp4 * rdx -> carry2:tmp3
9182   movl(tmp4, Address(z, idx, Address::times_4,  0));
9183 
9184   add2_with_carry(carry2, tmp3, tmp4, carry);
9185 
9186   movl(Address(z, idx, Address::times_4,  0), tmp3);
9187   shrq(tmp3, 32);
9188 
9189   shlq(carry2, 32);
9190   orq(tmp3, carry2);
9191   movq(carry, tmp3);
9192 
9193   bind(L_post_third_loop_done);
9194 }
9195 
9196 /**
9197  * Code for BigInteger::multiplyToLen() instrinsic.
9198  *
9199  * rdi: x
9200  * rax: xlen
9201  * rsi: y
9202  * rcx: ylen
9203  * r8:  z
9204  * r11: zlen
9205  * r12: tmp1
9206  * r13: tmp2
9207  * r14: tmp3
9208  * r15: tmp4
9209  * rbx: tmp5
9210  *
9211  */
9212 void MacroAssembler::multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z, Register zlen,
9213                                      Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5) {
9214   ShortBranchVerifier sbv(this);
9215   assert_different_registers(x, xlen, y, ylen, z, zlen, tmp1, tmp2, tmp3, tmp4, tmp5, rdx);
9216 
9217   push(tmp1);
9218   push(tmp2);
9219   push(tmp3);
9220   push(tmp4);
9221   push(tmp5);
9222 
9223   push(xlen);
9224   push(zlen);
9225 
9226   const Register idx = tmp1;
9227   const Register kdx = tmp2;
9228   const Register xstart = tmp3;
9229 
9230   const Register y_idx = tmp4;
9231   const Register carry = tmp5;
9232   const Register product  = xlen;
9233   const Register x_xstart = zlen;  // reuse register
9234 
9235   // First Loop.
9236   //
9237   //  final static long LONG_MASK = 0xffffffffL;
9238   //  int xstart = xlen - 1;
9239   //  int ystart = ylen - 1;
9240   //  long carry = 0;
9241   //  for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
9242   //    long product = (y[idx] & LONG_MASK) * (x[xstart] & LONG_MASK) + carry;
9243   //    z[kdx] = (int)product;
9244   //    carry = product >>> 32;
9245   //  }
9246   //  z[xstart] = (int)carry;
9247   //
9248 
9249   movl(idx, ylen);      // idx = ylen;
9250   movl(kdx, zlen);      // kdx = xlen+ylen;
9251   xorq(carry, carry);   // carry = 0;
9252 
9253   Label L_done;
9254 
9255   movl(xstart, xlen);
9256   decrementl(xstart);
9257   jcc(Assembler::negative, L_done);
9258 
9259   multiply_64_x_64_loop(x, xstart, x_xstart, y, y_idx, z, carry, product, idx, kdx);
9260 
9261   Label L_second_loop;
9262   testl(kdx, kdx);
9263   jcc(Assembler::zero, L_second_loop);
9264 
9265   Label L_carry;
9266   subl(kdx, 1);
9267   jcc(Assembler::zero, L_carry);
9268 
9269   movl(Address(z, kdx, Address::times_4,  0), carry);
9270   shrq(carry, 32);
9271   subl(kdx, 1);
9272 
9273   bind(L_carry);
9274   movl(Address(z, kdx, Address::times_4,  0), carry);
9275 
9276   // Second and third (nested) loops.
9277   //
9278   // for (int i = xstart-1; i >= 0; i--) { // Second loop
9279   //   carry = 0;
9280   //   for (int jdx=ystart, k=ystart+1+i; jdx >= 0; jdx--, k--) { // Third loop
9281   //     long product = (y[jdx] & LONG_MASK) * (x[i] & LONG_MASK) +
9282   //                    (z[k] & LONG_MASK) + carry;
9283   //     z[k] = (int)product;
9284   //     carry = product >>> 32;
9285   //   }
9286   //   z[i] = (int)carry;
9287   // }
9288   //
9289   // i = xlen, j = tmp1, k = tmp2, carry = tmp5, x[i] = rdx
9290 
9291   const Register jdx = tmp1;
9292 
9293   bind(L_second_loop);
9294   xorl(carry, carry);    // carry = 0;
9295   movl(jdx, ylen);       // j = ystart+1
9296 
9297   subl(xstart, 1);       // i = xstart-1;
9298   jcc(Assembler::negative, L_done);
9299 
9300   push (z);
9301 
9302   Label L_last_x;
9303   lea(z, Address(z, xstart, Address::times_4, 4)); // z = z + k - j
9304   subl(xstart, 1);       // i = xstart-1;
9305   jcc(Assembler::negative, L_last_x);
9306 
9307   if (UseBMI2Instructions) {
9308     movq(rdx,  Address(x, xstart, Address::times_4,  0));
9309     rorxq(rdx, rdx, 32); // convert big-endian to little-endian
9310   } else {
9311     movq(x_xstart, Address(x, xstart, Address::times_4,  0));
9312     rorq(x_xstart, 32);  // convert big-endian to little-endian
9313   }
9314 
9315   Label L_third_loop_prologue;
9316   bind(L_third_loop_prologue);
9317 
9318   push (x);
9319   push (xstart);
9320   push (ylen);
9321 
9322 
9323   if (UseBMI2Instructions) {
9324     multiply_128_x_128_bmi2_loop(y, z, carry, x, jdx, ylen, product, tmp2, x_xstart, tmp3, tmp4);
9325   } else { // !UseBMI2Instructions
9326     multiply_128_x_128_loop(x_xstart, y, z, y_idx, jdx, ylen, carry, product, x);
9327   }
9328 
9329   pop(ylen);
9330   pop(xlen);
9331   pop(x);
9332   pop(z);
9333 
9334   movl(tmp3, xlen);
9335   addl(tmp3, 1);
9336   movl(Address(z, tmp3, Address::times_4,  0), carry);
9337   subl(tmp3, 1);
9338   jccb(Assembler::negative, L_done);
9339 
9340   shrq(carry, 32);
9341   movl(Address(z, tmp3, Address::times_4,  0), carry);
9342   jmp(L_second_loop);
9343 
9344   // Next infrequent code is moved outside loops.
9345   bind(L_last_x);
9346   if (UseBMI2Instructions) {
9347     movl(rdx, Address(x,  0));
9348   } else {
9349     movl(x_xstart, Address(x,  0));
9350   }
9351   jmp(L_third_loop_prologue);
9352 
9353   bind(L_done);
9354 
9355   pop(zlen);
9356   pop(xlen);
9357 
9358   pop(tmp5);
9359   pop(tmp4);
9360   pop(tmp3);
9361   pop(tmp2);
9362   pop(tmp1);
9363 }
9364 
9365 void MacroAssembler::vectorized_mismatch(Register obja, Register objb, Register length, Register log2_array_indxscale,
9366   Register result, Register tmp1, Register tmp2, XMMRegister rymm0, XMMRegister rymm1, XMMRegister rymm2){
9367   assert(UseSSE42Intrinsics, "SSE4.2 must be enabled.");
9368   Label VECTOR64_LOOP, VECTOR64_TAIL, VECTOR64_NOT_EQUAL, VECTOR32_TAIL;
9369   Label VECTOR32_LOOP, VECTOR16_LOOP, VECTOR8_LOOP, VECTOR4_LOOP;
9370   Label VECTOR16_TAIL, VECTOR8_TAIL, VECTOR4_TAIL;
9371   Label VECTOR32_NOT_EQUAL, VECTOR16_NOT_EQUAL, VECTOR8_NOT_EQUAL, VECTOR4_NOT_EQUAL;
9372   Label SAME_TILL_END, DONE;
9373   Label BYTES_LOOP, BYTES_TAIL, BYTES_NOT_EQUAL;
9374 
9375   //scale is in rcx in both Win64 and Unix
9376   ShortBranchVerifier sbv(this);
9377 
9378   shlq(length);
9379   xorq(result, result);
9380 
9381   if ((UseAVX > 2) &&
9382       VM_Version::supports_avx512vlbw()) {
9383     set_vector_masking();  // opening of the stub context for programming mask registers
9384     cmpq(length, 64);
9385     jcc(Assembler::less, VECTOR32_TAIL);
9386     movq(tmp1, length);
9387     andq(tmp1, 0x3F);      // tail count
9388     andq(length, ~(0x3F)); //vector count
9389 
9390     bind(VECTOR64_LOOP);
9391     // AVX512 code to compare 64 byte vectors.
9392     evmovdqub(rymm0, Address(obja, result), Assembler::AVX_512bit);
9393     evpcmpeqb(k7, rymm0, Address(objb, result), Assembler::AVX_512bit);
9394     kortestql(k7, k7);
9395     jcc(Assembler::aboveEqual, VECTOR64_NOT_EQUAL);     // mismatch
9396     addq(result, 64);
9397     subq(length, 64);
9398     jccb(Assembler::notZero, VECTOR64_LOOP);
9399 
9400     //bind(VECTOR64_TAIL);
9401     testq(tmp1, tmp1);
9402     jcc(Assembler::zero, SAME_TILL_END);
9403 
9404     bind(VECTOR64_TAIL);
9405     // AVX512 code to compare upto 63 byte vectors.
9406     // Save k1
9407     kmovql(k3, k1);
9408     mov64(tmp2, 0xFFFFFFFFFFFFFFFF);
9409     shlxq(tmp2, tmp2, tmp1);
9410     notq(tmp2);
9411     kmovql(k1, tmp2);
9412 
9413     evmovdqub(rymm0, k1, Address(obja, result), Assembler::AVX_512bit);
9414     evpcmpeqb(k7, k1, rymm0, Address(objb, result), Assembler::AVX_512bit);
9415 
9416     ktestql(k7, k1);
9417     // Restore k1
9418     kmovql(k1, k3);
9419     jcc(Assembler::below, SAME_TILL_END);     // not mismatch
9420 
9421     bind(VECTOR64_NOT_EQUAL);
9422     kmovql(tmp1, k7);
9423     notq(tmp1);
9424     tzcntq(tmp1, tmp1);
9425     addq(result, tmp1);
9426     shrq(result);
9427     jmp(DONE);
9428     bind(VECTOR32_TAIL);
9429     clear_vector_masking();   // closing of the stub context for programming mask registers
9430   }
9431 
9432   cmpq(length, 8);
9433   jcc(Assembler::equal, VECTOR8_LOOP);
9434   jcc(Assembler::less, VECTOR4_TAIL);
9435 
9436   if (UseAVX >= 2) {
9437 
9438     cmpq(length, 16);
9439     jcc(Assembler::equal, VECTOR16_LOOP);
9440     jcc(Assembler::less, VECTOR8_LOOP);
9441 
9442     cmpq(length, 32);
9443     jccb(Assembler::less, VECTOR16_TAIL);
9444 
9445     subq(length, 32);
9446     bind(VECTOR32_LOOP);
9447     vmovdqu(rymm0, Address(obja, result));
9448     vmovdqu(rymm1, Address(objb, result));
9449     vpxor(rymm2, rymm0, rymm1, Assembler::AVX_256bit);
9450     vptest(rymm2, rymm2);
9451     jcc(Assembler::notZero, VECTOR32_NOT_EQUAL);//mismatch found
9452     addq(result, 32);
9453     subq(length, 32);
9454     jccb(Assembler::greaterEqual, VECTOR32_LOOP);
9455     addq(length, 32);
9456     jcc(Assembler::equal, SAME_TILL_END);
9457     //falling through if less than 32 bytes left //close the branch here.
9458 
9459     bind(VECTOR16_TAIL);
9460     cmpq(length, 16);
9461     jccb(Assembler::less, VECTOR8_TAIL);
9462     bind(VECTOR16_LOOP);
9463     movdqu(rymm0, Address(obja, result));
9464     movdqu(rymm1, Address(objb, result));
9465     vpxor(rymm2, rymm0, rymm1, Assembler::AVX_128bit);
9466     ptest(rymm2, rymm2);
9467     jcc(Assembler::notZero, VECTOR16_NOT_EQUAL);//mismatch found
9468     addq(result, 16);
9469     subq(length, 16);
9470     jcc(Assembler::equal, SAME_TILL_END);
9471     //falling through if less than 16 bytes left
9472   } else {//regular intrinsics
9473 
9474     cmpq(length, 16);
9475     jccb(Assembler::less, VECTOR8_TAIL);
9476 
9477     subq(length, 16);
9478     bind(VECTOR16_LOOP);
9479     movdqu(rymm0, Address(obja, result));
9480     movdqu(rymm1, Address(objb, result));
9481     pxor(rymm0, rymm1);
9482     ptest(rymm0, rymm0);
9483     jcc(Assembler::notZero, VECTOR16_NOT_EQUAL);//mismatch found
9484     addq(result, 16);
9485     subq(length, 16);
9486     jccb(Assembler::greaterEqual, VECTOR16_LOOP);
9487     addq(length, 16);
9488     jcc(Assembler::equal, SAME_TILL_END);
9489     //falling through if less than 16 bytes left
9490   }
9491 
9492   bind(VECTOR8_TAIL);
9493   cmpq(length, 8);
9494   jccb(Assembler::less, VECTOR4_TAIL);
9495   bind(VECTOR8_LOOP);
9496   movq(tmp1, Address(obja, result));
9497   movq(tmp2, Address(objb, result));
9498   xorq(tmp1, tmp2);
9499   testq(tmp1, tmp1);
9500   jcc(Assembler::notZero, VECTOR8_NOT_EQUAL);//mismatch found
9501   addq(result, 8);
9502   subq(length, 8);
9503   jcc(Assembler::equal, SAME_TILL_END);
9504   //falling through if less than 8 bytes left
9505 
9506   bind(VECTOR4_TAIL);
9507   cmpq(length, 4);
9508   jccb(Assembler::less, BYTES_TAIL);
9509   bind(VECTOR4_LOOP);
9510   movl(tmp1, Address(obja, result));
9511   xorl(tmp1, Address(objb, result));
9512   testl(tmp1, tmp1);
9513   jcc(Assembler::notZero, VECTOR4_NOT_EQUAL);//mismatch found
9514   addq(result, 4);
9515   subq(length, 4);
9516   jcc(Assembler::equal, SAME_TILL_END);
9517   //falling through if less than 4 bytes left
9518 
9519   bind(BYTES_TAIL);
9520   bind(BYTES_LOOP);
9521   load_unsigned_byte(tmp1, Address(obja, result));
9522   load_unsigned_byte(tmp2, Address(objb, result));
9523   xorl(tmp1, tmp2);
9524   testl(tmp1, tmp1);
9525   jccb(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found
9526   decq(length);
9527   jccb(Assembler::zero, SAME_TILL_END);
9528   incq(result);
9529   load_unsigned_byte(tmp1, Address(obja, result));
9530   load_unsigned_byte(tmp2, Address(objb, result));
9531   xorl(tmp1, tmp2);
9532   testl(tmp1, tmp1);
9533   jccb(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found
9534   decq(length);
9535   jccb(Assembler::zero, SAME_TILL_END);
9536   incq(result);
9537   load_unsigned_byte(tmp1, Address(obja, result));
9538   load_unsigned_byte(tmp2, Address(objb, result));
9539   xorl(tmp1, tmp2);
9540   testl(tmp1, tmp1);
9541   jccb(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found
9542   jmpb(SAME_TILL_END);
9543 
9544   if (UseAVX >= 2) {
9545     bind(VECTOR32_NOT_EQUAL);
9546     vpcmpeqb(rymm2, rymm2, rymm2, Assembler::AVX_256bit);
9547     vpcmpeqb(rymm0, rymm0, rymm1, Assembler::AVX_256bit);
9548     vpxor(rymm0, rymm0, rymm2, Assembler::AVX_256bit);
9549     vpmovmskb(tmp1, rymm0);
9550     bsfq(tmp1, tmp1);
9551     addq(result, tmp1);
9552     shrq(result);
9553     jmpb(DONE);
9554   }
9555 
9556   bind(VECTOR16_NOT_EQUAL);
9557   if (UseAVX >= 2) {
9558     vpcmpeqb(rymm2, rymm2, rymm2, Assembler::AVX_128bit);
9559     vpcmpeqb(rymm0, rymm0, rymm1, Assembler::AVX_128bit);
9560     pxor(rymm0, rymm2);
9561   } else {
9562     pcmpeqb(rymm2, rymm2);
9563     pxor(rymm0, rymm1);
9564     pcmpeqb(rymm0, rymm1);
9565     pxor(rymm0, rymm2);
9566   }
9567   pmovmskb(tmp1, rymm0);
9568   bsfq(tmp1, tmp1);
9569   addq(result, tmp1);
9570   shrq(result);
9571   jmpb(DONE);
9572 
9573   bind(VECTOR8_NOT_EQUAL);
9574   bind(VECTOR4_NOT_EQUAL);
9575   bsfq(tmp1, tmp1);
9576   shrq(tmp1, 3);
9577   addq(result, tmp1);
9578   bind(BYTES_NOT_EQUAL);
9579   shrq(result);
9580   jmpb(DONE);
9581 
9582   bind(SAME_TILL_END);
9583   mov64(result, -1);
9584 
9585   bind(DONE);
9586 }
9587 
9588 //Helper functions for square_to_len()
9589 
9590 /**
9591  * Store the squares of x[], right shifted one bit (divided by 2) into z[]
9592  * Preserves x and z and modifies rest of the registers.
9593  */
9594 void MacroAssembler::square_rshift(Register x, Register xlen, Register z, Register tmp1, Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
9595   // Perform square and right shift by 1
9596   // Handle odd xlen case first, then for even xlen do the following
9597   // jlong carry = 0;
9598   // for (int j=0, i=0; j < xlen; j+=2, i+=4) {
9599   //     huge_128 product = x[j:j+1] * x[j:j+1];
9600   //     z[i:i+1] = (carry << 63) | (jlong)(product >>> 65);
9601   //     z[i+2:i+3] = (jlong)(product >>> 1);
9602   //     carry = (jlong)product;
9603   // }
9604 
9605   xorq(tmp5, tmp5);     // carry
9606   xorq(rdxReg, rdxReg);
9607   xorl(tmp1, tmp1);     // index for x
9608   xorl(tmp4, tmp4);     // index for z
9609 
9610   Label L_first_loop, L_first_loop_exit;
9611 
9612   testl(xlen, 1);
9613   jccb(Assembler::zero, L_first_loop); //jump if xlen is even
9614 
9615   // Square and right shift by 1 the odd element using 32 bit multiply
9616   movl(raxReg, Address(x, tmp1, Address::times_4, 0));
9617   imulq(raxReg, raxReg);
9618   shrq(raxReg, 1);
9619   adcq(tmp5, 0);
9620   movq(Address(z, tmp4, Address::times_4, 0), raxReg);
9621   incrementl(tmp1);
9622   addl(tmp4, 2);
9623 
9624   // Square and  right shift by 1 the rest using 64 bit multiply
9625   bind(L_first_loop);
9626   cmpptr(tmp1, xlen);
9627   jccb(Assembler::equal, L_first_loop_exit);
9628 
9629   // Square
9630   movq(raxReg, Address(x, tmp1, Address::times_4,  0));
9631   rorq(raxReg, 32);    // convert big-endian to little-endian
9632   mulq(raxReg);        // 64-bit multiply rax * rax -> rdx:rax
9633 
9634   // Right shift by 1 and save carry
9635   shrq(tmp5, 1);       // rdx:rax:tmp5 = (tmp5:rdx:rax) >>> 1
9636   rcrq(rdxReg, 1);
9637   rcrq(raxReg, 1);
9638   adcq(tmp5, 0);
9639 
9640   // Store result in z
9641   movq(Address(z, tmp4, Address::times_4, 0), rdxReg);
9642   movq(Address(z, tmp4, Address::times_4, 8), raxReg);
9643 
9644   // Update indices for x and z
9645   addl(tmp1, 2);
9646   addl(tmp4, 4);
9647   jmp(L_first_loop);
9648 
9649   bind(L_first_loop_exit);
9650 }
9651 
9652 
9653 /**
9654  * Perform the following multiply add operation using BMI2 instructions
9655  * carry:sum = sum + op1*op2 + carry
9656  * op2 should be in rdx
9657  * op2 is preserved, all other registers are modified
9658  */
9659 void MacroAssembler::multiply_add_64_bmi2(Register sum, Register op1, Register op2, Register carry, Register tmp2) {
9660   // assert op2 is rdx
9661   mulxq(tmp2, op1, op1);  //  op1 * op2 -> tmp2:op1
9662   addq(sum, carry);
9663   adcq(tmp2, 0);
9664   addq(sum, op1);
9665   adcq(tmp2, 0);
9666   movq(carry, tmp2);
9667 }
9668 
9669 /**
9670  * Perform the following multiply add operation:
9671  * carry:sum = sum + op1*op2 + carry
9672  * Preserves op1, op2 and modifies rest of registers
9673  */
9674 void MacroAssembler::multiply_add_64(Register sum, Register op1, Register op2, Register carry, Register rdxReg, Register raxReg) {
9675   // rdx:rax = op1 * op2
9676   movq(raxReg, op2);
9677   mulq(op1);
9678 
9679   //  rdx:rax = sum + carry + rdx:rax
9680   addq(sum, carry);
9681   adcq(rdxReg, 0);
9682   addq(sum, raxReg);
9683   adcq(rdxReg, 0);
9684 
9685   // carry:sum = rdx:sum
9686   movq(carry, rdxReg);
9687 }
9688 
9689 /**
9690  * Add 64 bit long carry into z[] with carry propogation.
9691  * Preserves z and carry register values and modifies rest of registers.
9692  *
9693  */
9694 void MacroAssembler::add_one_64(Register z, Register zlen, Register carry, Register tmp1) {
9695   Label L_fourth_loop, L_fourth_loop_exit;
9696 
9697   movl(tmp1, 1);
9698   subl(zlen, 2);
9699   addq(Address(z, zlen, Address::times_4, 0), carry);
9700 
9701   bind(L_fourth_loop);
9702   jccb(Assembler::carryClear, L_fourth_loop_exit);
9703   subl(zlen, 2);
9704   jccb(Assembler::negative, L_fourth_loop_exit);
9705   addq(Address(z, zlen, Address::times_4, 0), tmp1);
9706   jmp(L_fourth_loop);
9707   bind(L_fourth_loop_exit);
9708 }
9709 
9710 /**
9711  * Shift z[] left by 1 bit.
9712  * Preserves x, len, z and zlen registers and modifies rest of the registers.
9713  *
9714  */
9715 void MacroAssembler::lshift_by_1(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2, Register tmp3, Register tmp4) {
9716 
9717   Label L_fifth_loop, L_fifth_loop_exit;
9718 
9719   // Fifth loop
9720   // Perform primitiveLeftShift(z, zlen, 1)
9721 
9722   const Register prev_carry = tmp1;
9723   const Register new_carry = tmp4;
9724   const Register value = tmp2;
9725   const Register zidx = tmp3;
9726 
9727   // int zidx, carry;
9728   // long value;
9729   // carry = 0;
9730   // for (zidx = zlen-2; zidx >=0; zidx -= 2) {
9731   //    (carry:value)  = (z[i] << 1) | carry ;
9732   //    z[i] = value;
9733   // }
9734 
9735   movl(zidx, zlen);
9736   xorl(prev_carry, prev_carry); // clear carry flag and prev_carry register
9737 
9738   bind(L_fifth_loop);
9739   decl(zidx);  // Use decl to preserve carry flag
9740   decl(zidx);
9741   jccb(Assembler::negative, L_fifth_loop_exit);
9742 
9743   if (UseBMI2Instructions) {
9744      movq(value, Address(z, zidx, Address::times_4, 0));
9745      rclq(value, 1);
9746      rorxq(value, value, 32);
9747      movq(Address(z, zidx, Address::times_4,  0), value);  // Store back in big endian form
9748   }
9749   else {
9750     // clear new_carry
9751     xorl(new_carry, new_carry);
9752 
9753     // Shift z[i] by 1, or in previous carry and save new carry
9754     movq(value, Address(z, zidx, Address::times_4, 0));
9755     shlq(value, 1);
9756     adcl(new_carry, 0);
9757 
9758     orq(value, prev_carry);
9759     rorq(value, 0x20);
9760     movq(Address(z, zidx, Address::times_4,  0), value);  // Store back in big endian form
9761 
9762     // Set previous carry = new carry
9763     movl(prev_carry, new_carry);
9764   }
9765   jmp(L_fifth_loop);
9766 
9767   bind(L_fifth_loop_exit);
9768 }
9769 
9770 
9771 /**
9772  * Code for BigInteger::squareToLen() intrinsic
9773  *
9774  * rdi: x
9775  * rsi: len
9776  * r8:  z
9777  * rcx: zlen
9778  * r12: tmp1
9779  * r13: tmp2
9780  * r14: tmp3
9781  * r15: tmp4
9782  * rbx: tmp5
9783  *
9784  */
9785 void MacroAssembler::square_to_len(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
9786 
9787   Label L_second_loop, L_second_loop_exit, L_third_loop, L_third_loop_exit, fifth_loop, fifth_loop_exit, L_last_x, L_multiply;
9788   push(tmp1);
9789   push(tmp2);
9790   push(tmp3);
9791   push(tmp4);
9792   push(tmp5);
9793 
9794   // First loop
9795   // Store the squares, right shifted one bit (i.e., divided by 2).
9796   square_rshift(x, len, z, tmp1, tmp3, tmp4, tmp5, rdxReg, raxReg);
9797 
9798   // Add in off-diagonal sums.
9799   //
9800   // Second, third (nested) and fourth loops.
9801   // zlen +=2;
9802   // for (int xidx=len-2,zidx=zlen-4; xidx > 0; xidx-=2,zidx-=4) {
9803   //    carry = 0;
9804   //    long op2 = x[xidx:xidx+1];
9805   //    for (int j=xidx-2,k=zidx; j >= 0; j-=2) {
9806   //       k -= 2;
9807   //       long op1 = x[j:j+1];
9808   //       long sum = z[k:k+1];
9809   //       carry:sum = multiply_add_64(sum, op1, op2, carry, tmp_regs);
9810   //       z[k:k+1] = sum;
9811   //    }
9812   //    add_one_64(z, k, carry, tmp_regs);
9813   // }
9814 
9815   const Register carry = tmp5;
9816   const Register sum = tmp3;
9817   const Register op1 = tmp4;
9818   Register op2 = tmp2;
9819 
9820   push(zlen);
9821   push(len);
9822   addl(zlen,2);
9823   bind(L_second_loop);
9824   xorq(carry, carry);
9825   subl(zlen, 4);
9826   subl(len, 2);
9827   push(zlen);
9828   push(len);
9829   cmpl(len, 0);
9830   jccb(Assembler::lessEqual, L_second_loop_exit);
9831 
9832   // Multiply an array by one 64 bit long.
9833   if (UseBMI2Instructions) {
9834     op2 = rdxReg;
9835     movq(op2, Address(x, len, Address::times_4,  0));
9836     rorxq(op2, op2, 32);
9837   }
9838   else {
9839     movq(op2, Address(x, len, Address::times_4,  0));
9840     rorq(op2, 32);
9841   }
9842 
9843   bind(L_third_loop);
9844   decrementl(len);
9845   jccb(Assembler::negative, L_third_loop_exit);
9846   decrementl(len);
9847   jccb(Assembler::negative, L_last_x);
9848 
9849   movq(op1, Address(x, len, Address::times_4,  0));
9850   rorq(op1, 32);
9851 
9852   bind(L_multiply);
9853   subl(zlen, 2);
9854   movq(sum, Address(z, zlen, Address::times_4,  0));
9855 
9856   // Multiply 64 bit by 64 bit and add 64 bits lower half and upper 64 bits as carry.
9857   if (UseBMI2Instructions) {
9858     multiply_add_64_bmi2(sum, op1, op2, carry, tmp2);
9859   }
9860   else {
9861     multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
9862   }
9863 
9864   movq(Address(z, zlen, Address::times_4, 0), sum);
9865 
9866   jmp(L_third_loop);
9867   bind(L_third_loop_exit);
9868 
9869   // Fourth loop
9870   // Add 64 bit long carry into z with carry propogation.
9871   // Uses offsetted zlen.
9872   add_one_64(z, zlen, carry, tmp1);
9873 
9874   pop(len);
9875   pop(zlen);
9876   jmp(L_second_loop);
9877 
9878   // Next infrequent code is moved outside loops.
9879   bind(L_last_x);
9880   movl(op1, Address(x, 0));
9881   jmp(L_multiply);
9882 
9883   bind(L_second_loop_exit);
9884   pop(len);
9885   pop(zlen);
9886   pop(len);
9887   pop(zlen);
9888 
9889   // Fifth loop
9890   // Shift z left 1 bit.
9891   lshift_by_1(x, len, z, zlen, tmp1, tmp2, tmp3, tmp4);
9892 
9893   // z[zlen-1] |= x[len-1] & 1;
9894   movl(tmp3, Address(x, len, Address::times_4, -4));
9895   andl(tmp3, 1);
9896   orl(Address(z, zlen, Address::times_4,  -4), tmp3);
9897 
9898   pop(tmp5);
9899   pop(tmp4);
9900   pop(tmp3);
9901   pop(tmp2);
9902   pop(tmp1);
9903 }
9904 
9905 /**
9906  * Helper function for mul_add()
9907  * Multiply the in[] by int k and add to out[] starting at offset offs using
9908  * 128 bit by 32 bit multiply and return the carry in tmp5.
9909  * Only quad int aligned length of in[] is operated on in this function.
9910  * k is in rdxReg for BMI2Instructions, for others it is in tmp2.
9911  * This function preserves out, in and k registers.
9912  * len and offset point to the appropriate index in "in" & "out" correspondingly
9913  * tmp5 has the carry.
9914  * other registers are temporary and are modified.
9915  *
9916  */
9917 void MacroAssembler::mul_add_128_x_32_loop(Register out, Register in,
9918   Register offset, Register len, Register tmp1, Register tmp2, Register tmp3,
9919   Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
9920 
9921   Label L_first_loop, L_first_loop_exit;
9922 
9923   movl(tmp1, len);
9924   shrl(tmp1, 2);
9925 
9926   bind(L_first_loop);
9927   subl(tmp1, 1);
9928   jccb(Assembler::negative, L_first_loop_exit);
9929 
9930   subl(len, 4);
9931   subl(offset, 4);
9932 
9933   Register op2 = tmp2;
9934   const Register sum = tmp3;
9935   const Register op1 = tmp4;
9936   const Register carry = tmp5;
9937 
9938   if (UseBMI2Instructions) {
9939     op2 = rdxReg;
9940   }
9941 
9942   movq(op1, Address(in, len, Address::times_4,  8));
9943   rorq(op1, 32);
9944   movq(sum, Address(out, offset, Address::times_4,  8));
9945   rorq(sum, 32);
9946   if (UseBMI2Instructions) {
9947     multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
9948   }
9949   else {
9950     multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
9951   }
9952   // Store back in big endian from little endian
9953   rorq(sum, 0x20);
9954   movq(Address(out, offset, Address::times_4,  8), sum);
9955 
9956   movq(op1, Address(in, len, Address::times_4,  0));
9957   rorq(op1, 32);
9958   movq(sum, Address(out, offset, Address::times_4,  0));
9959   rorq(sum, 32);
9960   if (UseBMI2Instructions) {
9961     multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
9962   }
9963   else {
9964     multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
9965   }
9966   // Store back in big endian from little endian
9967   rorq(sum, 0x20);
9968   movq(Address(out, offset, Address::times_4,  0), sum);
9969 
9970   jmp(L_first_loop);
9971   bind(L_first_loop_exit);
9972 }
9973 
9974 /**
9975  * Code for BigInteger::mulAdd() intrinsic
9976  *
9977  * rdi: out
9978  * rsi: in
9979  * r11: offs (out.length - offset)
9980  * rcx: len
9981  * r8:  k
9982  * r12: tmp1
9983  * r13: tmp2
9984  * r14: tmp3
9985  * r15: tmp4
9986  * rbx: tmp5
9987  * Multiply the in[] by word k and add to out[], return the carry in rax
9988  */
9989 void MacroAssembler::mul_add(Register out, Register in, Register offs,
9990    Register len, Register k, Register tmp1, Register tmp2, Register tmp3,
9991    Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
9992 
9993   Label L_carry, L_last_in, L_done;
9994 
9995 // carry = 0;
9996 // for (int j=len-1; j >= 0; j--) {
9997 //    long product = (in[j] & LONG_MASK) * kLong +
9998 //                   (out[offs] & LONG_MASK) + carry;
9999 //    out[offs--] = (int)product;
10000 //    carry = product >>> 32;
10001 // }
10002 //
10003   push(tmp1);
10004   push(tmp2);
10005   push(tmp3);
10006   push(tmp4);
10007   push(tmp5);
10008 
10009   Register op2 = tmp2;
10010   const Register sum = tmp3;
10011   const Register op1 = tmp4;
10012   const Register carry =  tmp5;
10013 
10014   if (UseBMI2Instructions) {
10015     op2 = rdxReg;
10016     movl(op2, k);
10017   }
10018   else {
10019     movl(op2, k);
10020   }
10021 
10022   xorq(carry, carry);
10023 
10024   //First loop
10025 
10026   //Multiply in[] by k in a 4 way unrolled loop using 128 bit by 32 bit multiply
10027   //The carry is in tmp5
10028   mul_add_128_x_32_loop(out, in, offs, len, tmp1, tmp2, tmp3, tmp4, tmp5, rdxReg, raxReg);
10029 
10030   //Multiply the trailing in[] entry using 64 bit by 32 bit, if any
10031   decrementl(len);
10032   jccb(Assembler::negative, L_carry);
10033   decrementl(len);
10034   jccb(Assembler::negative, L_last_in);
10035 
10036   movq(op1, Address(in, len, Address::times_4,  0));
10037   rorq(op1, 32);
10038 
10039   subl(offs, 2);
10040   movq(sum, Address(out, offs, Address::times_4,  0));
10041   rorq(sum, 32);
10042 
10043   if (UseBMI2Instructions) {
10044     multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
10045   }
10046   else {
10047     multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
10048   }
10049 
10050   // Store back in big endian from little endian
10051   rorq(sum, 0x20);
10052   movq(Address(out, offs, Address::times_4,  0), sum);
10053 
10054   testl(len, len);
10055   jccb(Assembler::zero, L_carry);
10056 
10057   //Multiply the last in[] entry, if any
10058   bind(L_last_in);
10059   movl(op1, Address(in, 0));
10060   movl(sum, Address(out, offs, Address::times_4,  -4));
10061 
10062   movl(raxReg, k);
10063   mull(op1); //tmp4 * eax -> edx:eax
10064   addl(sum, carry);
10065   adcl(rdxReg, 0);
10066   addl(sum, raxReg);
10067   adcl(rdxReg, 0);
10068   movl(carry, rdxReg);
10069 
10070   movl(Address(out, offs, Address::times_4,  -4), sum);
10071 
10072   bind(L_carry);
10073   //return tmp5/carry as carry in rax
10074   movl(rax, carry);
10075 
10076   bind(L_done);
10077   pop(tmp5);
10078   pop(tmp4);
10079   pop(tmp3);
10080   pop(tmp2);
10081   pop(tmp1);
10082 }
10083 #endif
10084 
10085 /**
10086  * Emits code to update CRC-32 with a byte value according to constants in table
10087  *
10088  * @param [in,out]crc   Register containing the crc.
10089  * @param [in]val       Register containing the byte to fold into the CRC.
10090  * @param [in]table     Register containing the table of crc constants.
10091  *
10092  * uint32_t crc;
10093  * val = crc_table[(val ^ crc) & 0xFF];
10094  * crc = val ^ (crc >> 8);
10095  *
10096  */
10097 void MacroAssembler::update_byte_crc32(Register crc, Register val, Register table) {
10098   xorl(val, crc);
10099   andl(val, 0xFF);
10100   shrl(crc, 8); // unsigned shift
10101   xorl(crc, Address(table, val, Address::times_4, 0));
10102 }
10103 
10104 /**
10105  * Fold 128-bit data chunk
10106  */
10107 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset) {
10108   if (UseAVX > 0) {
10109     vpclmulhdq(xtmp, xK, xcrc); // [123:64]
10110     vpclmulldq(xcrc, xK, xcrc); // [63:0]
10111     vpxor(xcrc, xcrc, Address(buf, offset), 0 /* vector_len */);
10112     pxor(xcrc, xtmp);
10113   } else {
10114     movdqa(xtmp, xcrc);
10115     pclmulhdq(xtmp, xK);   // [123:64]
10116     pclmulldq(xcrc, xK);   // [63:0]
10117     pxor(xcrc, xtmp);
10118     movdqu(xtmp, Address(buf, offset));
10119     pxor(xcrc, xtmp);
10120   }
10121 }
10122 
10123 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, XMMRegister xbuf) {
10124   if (UseAVX > 0) {
10125     vpclmulhdq(xtmp, xK, xcrc);
10126     vpclmulldq(xcrc, xK, xcrc);
10127     pxor(xcrc, xbuf);
10128     pxor(xcrc, xtmp);
10129   } else {
10130     movdqa(xtmp, xcrc);
10131     pclmulhdq(xtmp, xK);
10132     pclmulldq(xcrc, xK);
10133     pxor(xcrc, xbuf);
10134     pxor(xcrc, xtmp);
10135   }
10136 }
10137 
10138 /**
10139  * 8-bit folds to compute 32-bit CRC
10140  *
10141  * uint64_t xcrc;
10142  * timesXtoThe32[xcrc & 0xFF] ^ (xcrc >> 8);
10143  */
10144 void MacroAssembler::fold_8bit_crc32(XMMRegister xcrc, Register table, XMMRegister xtmp, Register tmp) {
10145   movdl(tmp, xcrc);
10146   andl(tmp, 0xFF);
10147   movdl(xtmp, Address(table, tmp, Address::times_4, 0));
10148   psrldq(xcrc, 1); // unsigned shift one byte
10149   pxor(xcrc, xtmp);
10150 }
10151 
10152 /**
10153  * uint32_t crc;
10154  * timesXtoThe32[crc & 0xFF] ^ (crc >> 8);
10155  */
10156 void MacroAssembler::fold_8bit_crc32(Register crc, Register table, Register tmp) {
10157   movl(tmp, crc);
10158   andl(tmp, 0xFF);
10159   shrl(crc, 8);
10160   xorl(crc, Address(table, tmp, Address::times_4, 0));
10161 }
10162 
10163 /**
10164  * @param crc   register containing existing CRC (32-bit)
10165  * @param buf   register pointing to input byte buffer (byte*)
10166  * @param len   register containing number of bytes
10167  * @param table register that will contain address of CRC table
10168  * @param tmp   scratch register
10169  */
10170 void MacroAssembler::kernel_crc32(Register crc, Register buf, Register len, Register table, Register tmp) {
10171   assert_different_registers(crc, buf, len, table, tmp, rax);
10172 
10173   Label L_tail, L_tail_restore, L_tail_loop, L_exit, L_align_loop, L_aligned;
10174   Label L_fold_tail, L_fold_128b, L_fold_512b, L_fold_512b_loop, L_fold_tail_loop;
10175 
10176   // For EVEX with VL and BW, provide a standard mask, VL = 128 will guide the merge
10177   // context for the registers used, where all instructions below are using 128-bit mode
10178   // On EVEX without VL and BW, these instructions will all be AVX.
10179   if (VM_Version::supports_avx512vlbw()) {
10180     movl(tmp, 0xffff);
10181     kmovwl(k1, tmp);
10182   }
10183 
10184   lea(table, ExternalAddress(StubRoutines::crc_table_addr()));
10185   notl(crc); // ~crc
10186   cmpl(len, 16);
10187   jcc(Assembler::less, L_tail);
10188 
10189   // Align buffer to 16 bytes
10190   movl(tmp, buf);
10191   andl(tmp, 0xF);
10192   jccb(Assembler::zero, L_aligned);
10193   subl(tmp,  16);
10194   addl(len, tmp);
10195 
10196   align(4);
10197   BIND(L_align_loop);
10198   movsbl(rax, Address(buf, 0)); // load byte with sign extension
10199   update_byte_crc32(crc, rax, table);
10200   increment(buf);
10201   incrementl(tmp);
10202   jccb(Assembler::less, L_align_loop);
10203 
10204   BIND(L_aligned);
10205   movl(tmp, len); // save
10206   shrl(len, 4);
10207   jcc(Assembler::zero, L_tail_restore);
10208 
10209   // Fold crc into first bytes of vector
10210   movdqa(xmm1, Address(buf, 0));
10211   movdl(rax, xmm1);
10212   xorl(crc, rax);
10213   if (VM_Version::supports_sse4_1()) {
10214     pinsrd(xmm1, crc, 0);
10215   } else {
10216     pinsrw(xmm1, crc, 0);
10217     shrl(crc, 16);
10218     pinsrw(xmm1, crc, 1);
10219   }
10220   addptr(buf, 16);
10221   subl(len, 4); // len > 0
10222   jcc(Assembler::less, L_fold_tail);
10223 
10224   movdqa(xmm2, Address(buf,  0));
10225   movdqa(xmm3, Address(buf, 16));
10226   movdqa(xmm4, Address(buf, 32));
10227   addptr(buf, 48);
10228   subl(len, 3);
10229   jcc(Assembler::lessEqual, L_fold_512b);
10230 
10231   // Fold total 512 bits of polynomial on each iteration,
10232   // 128 bits per each of 4 parallel streams.
10233   movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 32));
10234 
10235   align(32);
10236   BIND(L_fold_512b_loop);
10237   fold_128bit_crc32(xmm1, xmm0, xmm5, buf,  0);
10238   fold_128bit_crc32(xmm2, xmm0, xmm5, buf, 16);
10239   fold_128bit_crc32(xmm3, xmm0, xmm5, buf, 32);
10240   fold_128bit_crc32(xmm4, xmm0, xmm5, buf, 48);
10241   addptr(buf, 64);
10242   subl(len, 4);
10243   jcc(Assembler::greater, L_fold_512b_loop);
10244 
10245   // Fold 512 bits to 128 bits.
10246   BIND(L_fold_512b);
10247   movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16));
10248   fold_128bit_crc32(xmm1, xmm0, xmm5, xmm2);
10249   fold_128bit_crc32(xmm1, xmm0, xmm5, xmm3);
10250   fold_128bit_crc32(xmm1, xmm0, xmm5, xmm4);
10251 
10252   // Fold the rest of 128 bits data chunks
10253   BIND(L_fold_tail);
10254   addl(len, 3);
10255   jccb(Assembler::lessEqual, L_fold_128b);
10256   movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16));
10257 
10258   BIND(L_fold_tail_loop);
10259   fold_128bit_crc32(xmm1, xmm0, xmm5, buf,  0);
10260   addptr(buf, 16);
10261   decrementl(len);
10262   jccb(Assembler::greater, L_fold_tail_loop);
10263 
10264   // Fold 128 bits in xmm1 down into 32 bits in crc register.
10265   BIND(L_fold_128b);
10266   movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr()));
10267   if (UseAVX > 0) {
10268     vpclmulqdq(xmm2, xmm0, xmm1, 0x1);
10269     vpand(xmm3, xmm0, xmm2, 0 /* vector_len */);
10270     vpclmulqdq(xmm0, xmm0, xmm3, 0x1);
10271   } else {
10272     movdqa(xmm2, xmm0);
10273     pclmulqdq(xmm2, xmm1, 0x1);
10274     movdqa(xmm3, xmm0);
10275     pand(xmm3, xmm2);
10276     pclmulqdq(xmm0, xmm3, 0x1);
10277   }
10278   psrldq(xmm1, 8);
10279   psrldq(xmm2, 4);
10280   pxor(xmm0, xmm1);
10281   pxor(xmm0, xmm2);
10282 
10283   // 8 8-bit folds to compute 32-bit CRC.
10284   for (int j = 0; j < 4; j++) {
10285     fold_8bit_crc32(xmm0, table, xmm1, rax);
10286   }
10287   movdl(crc, xmm0); // mov 32 bits to general register
10288   for (int j = 0; j < 4; j++) {
10289     fold_8bit_crc32(crc, table, rax);
10290   }
10291 
10292   BIND(L_tail_restore);
10293   movl(len, tmp); // restore
10294   BIND(L_tail);
10295   andl(len, 0xf);
10296   jccb(Assembler::zero, L_exit);
10297 
10298   // Fold the rest of bytes
10299   align(4);
10300   BIND(L_tail_loop);
10301   movsbl(rax, Address(buf, 0)); // load byte with sign extension
10302   update_byte_crc32(crc, rax, table);
10303   increment(buf);
10304   decrementl(len);
10305   jccb(Assembler::greater, L_tail_loop);
10306 
10307   BIND(L_exit);
10308   notl(crc); // ~c
10309 }
10310 
10311 #ifdef _LP64
10312 // S. Gueron / Information Processing Letters 112 (2012) 184
10313 // Algorithm 4: Computing carry-less multiplication using a precomputed lookup table.
10314 // Input: A 32 bit value B = [byte3, byte2, byte1, byte0].
10315 // Output: the 64-bit carry-less product of B * CONST
10316 void MacroAssembler::crc32c_ipl_alg4(Register in, uint32_t n,
10317                                      Register tmp1, Register tmp2, Register tmp3) {
10318   lea(tmp3, ExternalAddress(StubRoutines::crc32c_table_addr()));
10319   if (n > 0) {
10320     addq(tmp3, n * 256 * 8);
10321   }
10322   //    Q1 = TABLEExt[n][B & 0xFF];
10323   movl(tmp1, in);
10324   andl(tmp1, 0x000000FF);
10325   shll(tmp1, 3);
10326   addq(tmp1, tmp3);
10327   movq(tmp1, Address(tmp1, 0));
10328 
10329   //    Q2 = TABLEExt[n][B >> 8 & 0xFF];
10330   movl(tmp2, in);
10331   shrl(tmp2, 8);
10332   andl(tmp2, 0x000000FF);
10333   shll(tmp2, 3);
10334   addq(tmp2, tmp3);
10335   movq(tmp2, Address(tmp2, 0));
10336 
10337   shlq(tmp2, 8);
10338   xorq(tmp1, tmp2);
10339 
10340   //    Q3 = TABLEExt[n][B >> 16 & 0xFF];
10341   movl(tmp2, in);
10342   shrl(tmp2, 16);
10343   andl(tmp2, 0x000000FF);
10344   shll(tmp2, 3);
10345   addq(tmp2, tmp3);
10346   movq(tmp2, Address(tmp2, 0));
10347 
10348   shlq(tmp2, 16);
10349   xorq(tmp1, tmp2);
10350 
10351   //    Q4 = TABLEExt[n][B >> 24 & 0xFF];
10352   shrl(in, 24);
10353   andl(in, 0x000000FF);
10354   shll(in, 3);
10355   addq(in, tmp3);
10356   movq(in, Address(in, 0));
10357 
10358   shlq(in, 24);
10359   xorq(in, tmp1);
10360   //    return Q1 ^ Q2 << 8 ^ Q3 << 16 ^ Q4 << 24;
10361 }
10362 
10363 void MacroAssembler::crc32c_pclmulqdq(XMMRegister w_xtmp1,
10364                                       Register in_out,
10365                                       uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported,
10366                                       XMMRegister w_xtmp2,
10367                                       Register tmp1,
10368                                       Register n_tmp2, Register n_tmp3) {
10369   if (is_pclmulqdq_supported) {
10370     movdl(w_xtmp1, in_out); // modified blindly
10371 
10372     movl(tmp1, const_or_pre_comp_const_index);
10373     movdl(w_xtmp2, tmp1);
10374     pclmulqdq(w_xtmp1, w_xtmp2, 0);
10375 
10376     movdq(in_out, w_xtmp1);
10377   } else {
10378     crc32c_ipl_alg4(in_out, const_or_pre_comp_const_index, tmp1, n_tmp2, n_tmp3);
10379   }
10380 }
10381 
10382 // Recombination Alternative 2: No bit-reflections
10383 // T1 = (CRC_A * U1) << 1
10384 // T2 = (CRC_B * U2) << 1
10385 // C1 = T1 >> 32
10386 // C2 = T2 >> 32
10387 // T1 = T1 & 0xFFFFFFFF
10388 // T2 = T2 & 0xFFFFFFFF
10389 // T1 = CRC32(0, T1)
10390 // T2 = CRC32(0, T2)
10391 // C1 = C1 ^ T1
10392 // C2 = C2 ^ T2
10393 // CRC = C1 ^ C2 ^ CRC_C
10394 void MacroAssembler::crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2,
10395                                      XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
10396                                      Register tmp1, Register tmp2,
10397                                      Register n_tmp3) {
10398   crc32c_pclmulqdq(w_xtmp1, in_out, const_or_pre_comp_const_index_u1, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
10399   crc32c_pclmulqdq(w_xtmp2, in1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
10400   shlq(in_out, 1);
10401   movl(tmp1, in_out);
10402   shrq(in_out, 32);
10403   xorl(tmp2, tmp2);
10404   crc32(tmp2, tmp1, 4);
10405   xorl(in_out, tmp2); // we don't care about upper 32 bit contents here
10406   shlq(in1, 1);
10407   movl(tmp1, in1);
10408   shrq(in1, 32);
10409   xorl(tmp2, tmp2);
10410   crc32(tmp2, tmp1, 4);
10411   xorl(in1, tmp2);
10412   xorl(in_out, in1);
10413   xorl(in_out, in2);
10414 }
10415 
10416 // Set N to predefined value
10417 // Subtract from a lenght of a buffer
10418 // execute in a loop:
10419 // CRC_A = 0xFFFFFFFF, CRC_B = 0, CRC_C = 0
10420 // for i = 1 to N do
10421 //  CRC_A = CRC32(CRC_A, A[i])
10422 //  CRC_B = CRC32(CRC_B, B[i])
10423 //  CRC_C = CRC32(CRC_C, C[i])
10424 // end for
10425 // Recombine
10426 void MacroAssembler::crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported,
10427                                        Register in_out1, Register in_out2, Register in_out3,
10428                                        Register tmp1, Register tmp2, Register tmp3,
10429                                        XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
10430                                        Register tmp4, Register tmp5,
10431                                        Register n_tmp6) {
10432   Label L_processPartitions;
10433   Label L_processPartition;
10434   Label L_exit;
10435 
10436   bind(L_processPartitions);
10437   cmpl(in_out1, 3 * size);
10438   jcc(Assembler::less, L_exit);
10439     xorl(tmp1, tmp1);
10440     xorl(tmp2, tmp2);
10441     movq(tmp3, in_out2);
10442     addq(tmp3, size);
10443 
10444     bind(L_processPartition);
10445       crc32(in_out3, Address(in_out2, 0), 8);
10446       crc32(tmp1, Address(in_out2, size), 8);
10447       crc32(tmp2, Address(in_out2, size * 2), 8);
10448       addq(in_out2, 8);
10449       cmpq(in_out2, tmp3);
10450       jcc(Assembler::less, L_processPartition);
10451     crc32c_rec_alt2(const_or_pre_comp_const_index_u1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, in_out3, tmp1, tmp2,
10452             w_xtmp1, w_xtmp2, w_xtmp3,
10453             tmp4, tmp5,
10454             n_tmp6);
10455     addq(in_out2, 2 * size);
10456     subl(in_out1, 3 * size);
10457     jmp(L_processPartitions);
10458 
10459   bind(L_exit);
10460 }
10461 #else
10462 void MacroAssembler::crc32c_ipl_alg4(Register in_out, uint32_t n,
10463                                      Register tmp1, Register tmp2, Register tmp3,
10464                                      XMMRegister xtmp1, XMMRegister xtmp2) {
10465   lea(tmp3, ExternalAddress(StubRoutines::crc32c_table_addr()));
10466   if (n > 0) {
10467     addl(tmp3, n * 256 * 8);
10468   }
10469   //    Q1 = TABLEExt[n][B & 0xFF];
10470   movl(tmp1, in_out);
10471   andl(tmp1, 0x000000FF);
10472   shll(tmp1, 3);
10473   addl(tmp1, tmp3);
10474   movq(xtmp1, Address(tmp1, 0));
10475 
10476   //    Q2 = TABLEExt[n][B >> 8 & 0xFF];
10477   movl(tmp2, in_out);
10478   shrl(tmp2, 8);
10479   andl(tmp2, 0x000000FF);
10480   shll(tmp2, 3);
10481   addl(tmp2, tmp3);
10482   movq(xtmp2, Address(tmp2, 0));
10483 
10484   psllq(xtmp2, 8);
10485   pxor(xtmp1, xtmp2);
10486 
10487   //    Q3 = TABLEExt[n][B >> 16 & 0xFF];
10488   movl(tmp2, in_out);
10489   shrl(tmp2, 16);
10490   andl(tmp2, 0x000000FF);
10491   shll(tmp2, 3);
10492   addl(tmp2, tmp3);
10493   movq(xtmp2, Address(tmp2, 0));
10494 
10495   psllq(xtmp2, 16);
10496   pxor(xtmp1, xtmp2);
10497 
10498   //    Q4 = TABLEExt[n][B >> 24 & 0xFF];
10499   shrl(in_out, 24);
10500   andl(in_out, 0x000000FF);
10501   shll(in_out, 3);
10502   addl(in_out, tmp3);
10503   movq(xtmp2, Address(in_out, 0));
10504 
10505   psllq(xtmp2, 24);
10506   pxor(xtmp1, xtmp2); // Result in CXMM
10507   //    return Q1 ^ Q2 << 8 ^ Q3 << 16 ^ Q4 << 24;
10508 }
10509 
10510 void MacroAssembler::crc32c_pclmulqdq(XMMRegister w_xtmp1,
10511                                       Register in_out,
10512                                       uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported,
10513                                       XMMRegister w_xtmp2,
10514                                       Register tmp1,
10515                                       Register n_tmp2, Register n_tmp3) {
10516   if (is_pclmulqdq_supported) {
10517     movdl(w_xtmp1, in_out);
10518 
10519     movl(tmp1, const_or_pre_comp_const_index);
10520     movdl(w_xtmp2, tmp1);
10521     pclmulqdq(w_xtmp1, w_xtmp2, 0);
10522     // Keep result in XMM since GPR is 32 bit in length
10523   } else {
10524     crc32c_ipl_alg4(in_out, const_or_pre_comp_const_index, tmp1, n_tmp2, n_tmp3, w_xtmp1, w_xtmp2);
10525   }
10526 }
10527 
10528 void MacroAssembler::crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2,
10529                                      XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
10530                                      Register tmp1, Register tmp2,
10531                                      Register n_tmp3) {
10532   crc32c_pclmulqdq(w_xtmp1, in_out, const_or_pre_comp_const_index_u1, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
10533   crc32c_pclmulqdq(w_xtmp2, in1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
10534 
10535   psllq(w_xtmp1, 1);
10536   movdl(tmp1, w_xtmp1);
10537   psrlq(w_xtmp1, 32);
10538   movdl(in_out, w_xtmp1);
10539 
10540   xorl(tmp2, tmp2);
10541   crc32(tmp2, tmp1, 4);
10542   xorl(in_out, tmp2);
10543 
10544   psllq(w_xtmp2, 1);
10545   movdl(tmp1, w_xtmp2);
10546   psrlq(w_xtmp2, 32);
10547   movdl(in1, w_xtmp2);
10548 
10549   xorl(tmp2, tmp2);
10550   crc32(tmp2, tmp1, 4);
10551   xorl(in1, tmp2);
10552   xorl(in_out, in1);
10553   xorl(in_out, in2);
10554 }
10555 
10556 void MacroAssembler::crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported,
10557                                        Register in_out1, Register in_out2, Register in_out3,
10558                                        Register tmp1, Register tmp2, Register tmp3,
10559                                        XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
10560                                        Register tmp4, Register tmp5,
10561                                        Register n_tmp6) {
10562   Label L_processPartitions;
10563   Label L_processPartition;
10564   Label L_exit;
10565 
10566   bind(L_processPartitions);
10567   cmpl(in_out1, 3 * size);
10568   jcc(Assembler::less, L_exit);
10569     xorl(tmp1, tmp1);
10570     xorl(tmp2, tmp2);
10571     movl(tmp3, in_out2);
10572     addl(tmp3, size);
10573 
10574     bind(L_processPartition);
10575       crc32(in_out3, Address(in_out2, 0), 4);
10576       crc32(tmp1, Address(in_out2, size), 4);
10577       crc32(tmp2, Address(in_out2, size*2), 4);
10578       crc32(in_out3, Address(in_out2, 0+4), 4);
10579       crc32(tmp1, Address(in_out2, size+4), 4);
10580       crc32(tmp2, Address(in_out2, size*2+4), 4);
10581       addl(in_out2, 8);
10582       cmpl(in_out2, tmp3);
10583       jcc(Assembler::less, L_processPartition);
10584 
10585         push(tmp3);
10586         push(in_out1);
10587         push(in_out2);
10588         tmp4 = tmp3;
10589         tmp5 = in_out1;
10590         n_tmp6 = in_out2;
10591 
10592       crc32c_rec_alt2(const_or_pre_comp_const_index_u1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, in_out3, tmp1, tmp2,
10593             w_xtmp1, w_xtmp2, w_xtmp3,
10594             tmp4, tmp5,
10595             n_tmp6);
10596 
10597         pop(in_out2);
10598         pop(in_out1);
10599         pop(tmp3);
10600 
10601     addl(in_out2, 2 * size);
10602     subl(in_out1, 3 * size);
10603     jmp(L_processPartitions);
10604 
10605   bind(L_exit);
10606 }
10607 #endif //LP64
10608 
10609 #ifdef _LP64
10610 // Algorithm 2: Pipelined usage of the CRC32 instruction.
10611 // Input: A buffer I of L bytes.
10612 // Output: the CRC32C value of the buffer.
10613 // Notations:
10614 // Write L = 24N + r, with N = floor (L/24).
10615 // r = L mod 24 (0 <= r < 24).
10616 // Consider I as the concatenation of A|B|C|R, where A, B, C, each,
10617 // N quadwords, and R consists of r bytes.
10618 // A[j] = I [8j+7:8j], j= 0, 1, ..., N-1
10619 // B[j] = I [N + 8j+7:N + 8j], j= 0, 1, ..., N-1
10620 // C[j] = I [2N + 8j+7:2N + 8j], j= 0, 1, ..., N-1
10621 // if r > 0 R[j] = I [3N +j], j= 0, 1, ...,r-1
10622 void MacroAssembler::crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2,
10623                                           Register tmp1, Register tmp2, Register tmp3,
10624                                           Register tmp4, Register tmp5, Register tmp6,
10625                                           XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
10626                                           bool is_pclmulqdq_supported) {
10627   uint32_t const_or_pre_comp_const_index[CRC32C_NUM_PRECOMPUTED_CONSTANTS];
10628   Label L_wordByWord;
10629   Label L_byteByByteProlog;
10630   Label L_byteByByte;
10631   Label L_exit;
10632 
10633   if (is_pclmulqdq_supported ) {
10634     const_or_pre_comp_const_index[1] = *(uint32_t *)StubRoutines::_crc32c_table_addr;
10635     const_or_pre_comp_const_index[0] = *((uint32_t *)StubRoutines::_crc32c_table_addr+1);
10636 
10637     const_or_pre_comp_const_index[3] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 2);
10638     const_or_pre_comp_const_index[2] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 3);
10639 
10640     const_or_pre_comp_const_index[5] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 4);
10641     const_or_pre_comp_const_index[4] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 5);
10642     assert((CRC32C_NUM_PRECOMPUTED_CONSTANTS - 1 ) == 5, "Checking whether you declared all of the constants based on the number of \"chunks\"");
10643   } else {
10644     const_or_pre_comp_const_index[0] = 1;
10645     const_or_pre_comp_const_index[1] = 0;
10646 
10647     const_or_pre_comp_const_index[2] = 3;
10648     const_or_pre_comp_const_index[3] = 2;
10649 
10650     const_or_pre_comp_const_index[4] = 5;
10651     const_or_pre_comp_const_index[5] = 4;
10652    }
10653   crc32c_proc_chunk(CRC32C_HIGH, const_or_pre_comp_const_index[0], const_or_pre_comp_const_index[1], is_pclmulqdq_supported,
10654                     in2, in1, in_out,
10655                     tmp1, tmp2, tmp3,
10656                     w_xtmp1, w_xtmp2, w_xtmp3,
10657                     tmp4, tmp5,
10658                     tmp6);
10659   crc32c_proc_chunk(CRC32C_MIDDLE, const_or_pre_comp_const_index[2], const_or_pre_comp_const_index[3], is_pclmulqdq_supported,
10660                     in2, in1, in_out,
10661                     tmp1, tmp2, tmp3,
10662                     w_xtmp1, w_xtmp2, w_xtmp3,
10663                     tmp4, tmp5,
10664                     tmp6);
10665   crc32c_proc_chunk(CRC32C_LOW, const_or_pre_comp_const_index[4], const_or_pre_comp_const_index[5], is_pclmulqdq_supported,
10666                     in2, in1, in_out,
10667                     tmp1, tmp2, tmp3,
10668                     w_xtmp1, w_xtmp2, w_xtmp3,
10669                     tmp4, tmp5,
10670                     tmp6);
10671   movl(tmp1, in2);
10672   andl(tmp1, 0x00000007);
10673   negl(tmp1);
10674   addl(tmp1, in2);
10675   addq(tmp1, in1);
10676 
10677   BIND(L_wordByWord);
10678   cmpq(in1, tmp1);
10679   jcc(Assembler::greaterEqual, L_byteByByteProlog);
10680     crc32(in_out, Address(in1, 0), 4);
10681     addq(in1, 4);
10682     jmp(L_wordByWord);
10683 
10684   BIND(L_byteByByteProlog);
10685   andl(in2, 0x00000007);
10686   movl(tmp2, 1);
10687 
10688   BIND(L_byteByByte);
10689   cmpl(tmp2, in2);
10690   jccb(Assembler::greater, L_exit);
10691     crc32(in_out, Address(in1, 0), 1);
10692     incq(in1);
10693     incl(tmp2);
10694     jmp(L_byteByByte);
10695 
10696   BIND(L_exit);
10697 }
10698 #else
10699 void MacroAssembler::crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2,
10700                                           Register tmp1, Register  tmp2, Register tmp3,
10701                                           Register tmp4, Register  tmp5, Register tmp6,
10702                                           XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
10703                                           bool is_pclmulqdq_supported) {
10704   uint32_t const_or_pre_comp_const_index[CRC32C_NUM_PRECOMPUTED_CONSTANTS];
10705   Label L_wordByWord;
10706   Label L_byteByByteProlog;
10707   Label L_byteByByte;
10708   Label L_exit;
10709 
10710   if (is_pclmulqdq_supported) {
10711     const_or_pre_comp_const_index[1] = *(uint32_t *)StubRoutines::_crc32c_table_addr;
10712     const_or_pre_comp_const_index[0] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 1);
10713 
10714     const_or_pre_comp_const_index[3] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 2);
10715     const_or_pre_comp_const_index[2] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 3);
10716 
10717     const_or_pre_comp_const_index[5] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 4);
10718     const_or_pre_comp_const_index[4] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 5);
10719   } else {
10720     const_or_pre_comp_const_index[0] = 1;
10721     const_or_pre_comp_const_index[1] = 0;
10722 
10723     const_or_pre_comp_const_index[2] = 3;
10724     const_or_pre_comp_const_index[3] = 2;
10725 
10726     const_or_pre_comp_const_index[4] = 5;
10727     const_or_pre_comp_const_index[5] = 4;
10728   }
10729   crc32c_proc_chunk(CRC32C_HIGH, const_or_pre_comp_const_index[0], const_or_pre_comp_const_index[1], is_pclmulqdq_supported,
10730                     in2, in1, in_out,
10731                     tmp1, tmp2, tmp3,
10732                     w_xtmp1, w_xtmp2, w_xtmp3,
10733                     tmp4, tmp5,
10734                     tmp6);
10735   crc32c_proc_chunk(CRC32C_MIDDLE, const_or_pre_comp_const_index[2], const_or_pre_comp_const_index[3], is_pclmulqdq_supported,
10736                     in2, in1, in_out,
10737                     tmp1, tmp2, tmp3,
10738                     w_xtmp1, w_xtmp2, w_xtmp3,
10739                     tmp4, tmp5,
10740                     tmp6);
10741   crc32c_proc_chunk(CRC32C_LOW, const_or_pre_comp_const_index[4], const_or_pre_comp_const_index[5], is_pclmulqdq_supported,
10742                     in2, in1, in_out,
10743                     tmp1, tmp2, tmp3,
10744                     w_xtmp1, w_xtmp2, w_xtmp3,
10745                     tmp4, tmp5,
10746                     tmp6);
10747   movl(tmp1, in2);
10748   andl(tmp1, 0x00000007);
10749   negl(tmp1);
10750   addl(tmp1, in2);
10751   addl(tmp1, in1);
10752 
10753   BIND(L_wordByWord);
10754   cmpl(in1, tmp1);
10755   jcc(Assembler::greaterEqual, L_byteByByteProlog);
10756     crc32(in_out, Address(in1,0), 4);
10757     addl(in1, 4);
10758     jmp(L_wordByWord);
10759 
10760   BIND(L_byteByByteProlog);
10761   andl(in2, 0x00000007);
10762   movl(tmp2, 1);
10763 
10764   BIND(L_byteByByte);
10765   cmpl(tmp2, in2);
10766   jccb(Assembler::greater, L_exit);
10767     movb(tmp1, Address(in1, 0));
10768     crc32(in_out, tmp1, 1);
10769     incl(in1);
10770     incl(tmp2);
10771     jmp(L_byteByByte);
10772 
10773   BIND(L_exit);
10774 }
10775 #endif // LP64
10776 #undef BIND
10777 #undef BLOCK_COMMENT
10778 
10779 // Compress char[] array to byte[].
10780 //   ..\jdk\src\java.base\share\classes\java\lang\StringUTF16.java
10781 //   @HotSpotIntrinsicCandidate
10782 //   private static int compress(char[] src, int srcOff, byte[] dst, int dstOff, int len) {
10783 //     for (int i = 0; i < len; i++) {
10784 //       int c = src[srcOff++];
10785 //       if (c >>> 8 != 0) {
10786 //         return 0;
10787 //       }
10788 //       dst[dstOff++] = (byte)c;
10789 //     }
10790 //     return len;
10791 //   }
10792 void MacroAssembler::char_array_compress(Register src, Register dst, Register len,
10793   XMMRegister tmp1Reg, XMMRegister tmp2Reg,
10794   XMMRegister tmp3Reg, XMMRegister tmp4Reg,
10795   Register tmp5, Register result) {
10796   Label copy_chars_loop, return_length, return_zero, done, below_threshold;
10797 
10798   // rsi: src
10799   // rdi: dst
10800   // rdx: len
10801   // rcx: tmp5
10802   // rax: result
10803 
10804   // rsi holds start addr of source char[] to be compressed
10805   // rdi holds start addr of destination byte[]
10806   // rdx holds length
10807 
10808   assert(len != result, "");
10809 
10810   // save length for return
10811   push(len);
10812 
10813   if ((UseAVX > 2) && // AVX512
10814     VM_Version::supports_avx512vlbw() &&
10815     VM_Version::supports_bmi2()) {
10816 
10817     set_vector_masking();  // opening of the stub context for programming mask registers
10818 
10819     Label copy_32_loop, copy_loop_tail, restore_k1_return_zero;
10820 
10821     // alignement
10822     Label post_alignement;
10823 
10824     // if length of the string is less than 16, handle it in an old fashioned
10825     // way
10826     testl(len, -32);
10827     jcc(Assembler::zero, below_threshold);
10828 
10829     // First check whether a character is compressable ( <= 0xFF).
10830     // Create mask to test for Unicode chars inside zmm vector
10831     movl(result, 0x00FF);
10832     evpbroadcastw(tmp2Reg, result, Assembler::AVX_512bit);
10833 
10834     // Save k1
10835     kmovql(k3, k1);
10836 
10837     testl(len, -64);
10838     jcc(Assembler::zero, post_alignement);
10839 
10840     movl(tmp5, dst);
10841     andl(tmp5, (32 - 1));
10842     negl(tmp5);
10843     andl(tmp5, (32 - 1));
10844 
10845     // bail out when there is nothing to be done
10846     testl(tmp5, 0xFFFFFFFF);
10847     jcc(Assembler::zero, post_alignement);
10848 
10849     // ~(~0 << len), where len is the # of remaining elements to process
10850     movl(result, 0xFFFFFFFF);
10851     shlxl(result, result, tmp5);
10852     notl(result);
10853     kmovdl(k1, result);
10854 
10855     evmovdquw(tmp1Reg, k1, Address(src, 0), Assembler::AVX_512bit);
10856     evpcmpuw(k2, k1, tmp1Reg, tmp2Reg, Assembler::le, Assembler::AVX_512bit);
10857     ktestd(k2, k1);
10858     jcc(Assembler::carryClear, restore_k1_return_zero);
10859 
10860     evpmovwb(Address(dst, 0), k1, tmp1Reg, Assembler::AVX_512bit);
10861 
10862     addptr(src, tmp5);
10863     addptr(src, tmp5);
10864     addptr(dst, tmp5);
10865     subl(len, tmp5);
10866 
10867     bind(post_alignement);
10868     // end of alignement
10869 
10870     movl(tmp5, len);
10871     andl(tmp5, (32 - 1));    // tail count (in chars)
10872     andl(len, ~(32 - 1));    // vector count (in chars)
10873     jcc(Assembler::zero, copy_loop_tail);
10874 
10875     lea(src, Address(src, len, Address::times_2));
10876     lea(dst, Address(dst, len, Address::times_1));
10877     negptr(len);
10878 
10879     bind(copy_32_loop);
10880     evmovdquw(tmp1Reg, Address(src, len, Address::times_2), Assembler::AVX_512bit);
10881     evpcmpuw(k2, tmp1Reg, tmp2Reg, Assembler::le, Assembler::AVX_512bit);
10882     kortestdl(k2, k2);
10883     jcc(Assembler::carryClear, restore_k1_return_zero);
10884 
10885     // All elements in current processed chunk are valid candidates for
10886     // compression. Write a truncated byte elements to the memory.
10887     evpmovwb(Address(dst, len, Address::times_1), tmp1Reg, Assembler::AVX_512bit);
10888     addptr(len, 32);
10889     jcc(Assembler::notZero, copy_32_loop);
10890 
10891     bind(copy_loop_tail);
10892     // bail out when there is nothing to be done
10893     testl(tmp5, 0xFFFFFFFF);
10894     // Restore k1
10895     kmovql(k1, k3);
10896     jcc(Assembler::zero, return_length);
10897 
10898     movl(len, tmp5);
10899 
10900     // ~(~0 << len), where len is the # of remaining elements to process
10901     movl(result, 0xFFFFFFFF);
10902     shlxl(result, result, len);
10903     notl(result);
10904 
10905     kmovdl(k1, result);
10906 
10907     evmovdquw(tmp1Reg, k1, Address(src, 0), Assembler::AVX_512bit);
10908     evpcmpuw(k2, k1, tmp1Reg, tmp2Reg, Assembler::le, Assembler::AVX_512bit);
10909     ktestd(k2, k1);
10910     jcc(Assembler::carryClear, restore_k1_return_zero);
10911 
10912     evpmovwb(Address(dst, 0), k1, tmp1Reg, Assembler::AVX_512bit);
10913     // Restore k1
10914     kmovql(k1, k3);
10915     jmp(return_length);
10916 
10917     bind(restore_k1_return_zero);
10918     // Restore k1
10919     kmovql(k1, k3);
10920     jmp(return_zero);
10921 
10922     clear_vector_masking();   // closing of the stub context for programming mask registers
10923   }
10924   if (UseSSE42Intrinsics) {
10925     Label copy_32_loop, copy_16, copy_tail;
10926 
10927     bind(below_threshold);
10928 
10929     movl(result, len);
10930 
10931     movl(tmp5, 0xff00ff00);   // create mask to test for Unicode chars in vectors
10932 
10933     // vectored compression
10934     andl(len, 0xfffffff0);    // vector count (in chars)
10935     andl(result, 0x0000000f);    // tail count (in chars)
10936     testl(len, len);
10937     jccb(Assembler::zero, copy_16);
10938 
10939     // compress 16 chars per iter
10940     movdl(tmp1Reg, tmp5);
10941     pshufd(tmp1Reg, tmp1Reg, 0);   // store Unicode mask in tmp1Reg
10942     pxor(tmp4Reg, tmp4Reg);
10943 
10944     lea(src, Address(src, len, Address::times_2));
10945     lea(dst, Address(dst, len, Address::times_1));
10946     negptr(len);
10947 
10948     bind(copy_32_loop);
10949     movdqu(tmp2Reg, Address(src, len, Address::times_2));     // load 1st 8 characters
10950     por(tmp4Reg, tmp2Reg);
10951     movdqu(tmp3Reg, Address(src, len, Address::times_2, 16)); // load next 8 characters
10952     por(tmp4Reg, tmp3Reg);
10953     ptest(tmp4Reg, tmp1Reg);       // check for Unicode chars in next vector
10954     jcc(Assembler::notZero, return_zero);
10955     packuswb(tmp2Reg, tmp3Reg);    // only ASCII chars; compress each to 1 byte
10956     movdqu(Address(dst, len, Address::times_1), tmp2Reg);
10957     addptr(len, 16);
10958     jcc(Assembler::notZero, copy_32_loop);
10959 
10960     // compress next vector of 8 chars (if any)
10961     bind(copy_16);
10962     movl(len, result);
10963     andl(len, 0xfffffff8);    // vector count (in chars)
10964     andl(result, 0x00000007);    // tail count (in chars)
10965     testl(len, len);
10966     jccb(Assembler::zero, copy_tail);
10967 
10968     movdl(tmp1Reg, tmp5);
10969     pshufd(tmp1Reg, tmp1Reg, 0);   // store Unicode mask in tmp1Reg
10970     pxor(tmp3Reg, tmp3Reg);
10971 
10972     movdqu(tmp2Reg, Address(src, 0));
10973     ptest(tmp2Reg, tmp1Reg);       // check for Unicode chars in vector
10974     jccb(Assembler::notZero, return_zero);
10975     packuswb(tmp2Reg, tmp3Reg);    // only LATIN1 chars; compress each to 1 byte
10976     movq(Address(dst, 0), tmp2Reg);
10977     addptr(src, 16);
10978     addptr(dst, 8);
10979 
10980     bind(copy_tail);
10981     movl(len, result);
10982   }
10983   // compress 1 char per iter
10984   testl(len, len);
10985   jccb(Assembler::zero, return_length);
10986   lea(src, Address(src, len, Address::times_2));
10987   lea(dst, Address(dst, len, Address::times_1));
10988   negptr(len);
10989 
10990   bind(copy_chars_loop);
10991   load_unsigned_short(result, Address(src, len, Address::times_2));
10992   testl(result, 0xff00);      // check if Unicode char
10993   jccb(Assembler::notZero, return_zero);
10994   movb(Address(dst, len, Address::times_1), result);  // ASCII char; compress to 1 byte
10995   increment(len);
10996   jcc(Assembler::notZero, copy_chars_loop);
10997 
10998   // if compression succeeded, return length
10999   bind(return_length);
11000   pop(result);
11001   jmpb(done);
11002 
11003   // if compression failed, return 0
11004   bind(return_zero);
11005   xorl(result, result);
11006   addptr(rsp, wordSize);
11007 
11008   bind(done);
11009 }
11010 
11011 // Inflate byte[] array to char[].
11012 //   ..\jdk\src\java.base\share\classes\java\lang\StringLatin1.java
11013 //   @HotSpotIntrinsicCandidate
11014 //   private static void inflate(byte[] src, int srcOff, char[] dst, int dstOff, int len) {
11015 //     for (int i = 0; i < len; i++) {
11016 //       dst[dstOff++] = (char)(src[srcOff++] & 0xff);
11017 //     }
11018 //   }
11019 void MacroAssembler::byte_array_inflate(Register src, Register dst, Register len,
11020   XMMRegister tmp1, Register tmp2) {
11021   Label copy_chars_loop, done, below_threshold;
11022   // rsi: src
11023   // rdi: dst
11024   // rdx: len
11025   // rcx: tmp2
11026 
11027   // rsi holds start addr of source byte[] to be inflated
11028   // rdi holds start addr of destination char[]
11029   // rdx holds length
11030   assert_different_registers(src, dst, len, tmp2);
11031 
11032   if ((UseAVX > 2) && // AVX512
11033     VM_Version::supports_avx512vlbw() &&
11034     VM_Version::supports_bmi2()) {
11035 
11036     set_vector_masking();  // opening of the stub context for programming mask registers
11037 
11038     Label copy_32_loop, copy_tail;
11039     Register tmp3_aliased = len;
11040 
11041     // if length of the string is less than 16, handle it in an old fashioned
11042     // way
11043     testl(len, -16);
11044     jcc(Assembler::zero, below_threshold);
11045 
11046     // In order to use only one arithmetic operation for the main loop we use
11047     // this pre-calculation
11048     movl(tmp2, len);
11049     andl(tmp2, (32 - 1)); // tail count (in chars), 32 element wide loop
11050     andl(len, -32);     // vector count
11051     jccb(Assembler::zero, copy_tail);
11052 
11053     lea(src, Address(src, len, Address::times_1));
11054     lea(dst, Address(dst, len, Address::times_2));
11055     negptr(len);
11056 
11057 
11058     // inflate 32 chars per iter
11059     bind(copy_32_loop);
11060     vpmovzxbw(tmp1, Address(src, len, Address::times_1), Assembler::AVX_512bit);
11061     evmovdquw(Address(dst, len, Address::times_2), tmp1, Assembler::AVX_512bit);
11062     addptr(len, 32);
11063     jcc(Assembler::notZero, copy_32_loop);
11064 
11065     bind(copy_tail);
11066     // bail out when there is nothing to be done
11067     testl(tmp2, -1); // we don't destroy the contents of tmp2 here
11068     jcc(Assembler::zero, done);
11069 
11070     // Save k1
11071     kmovql(k2, k1);
11072 
11073     // ~(~0 << length), where length is the # of remaining elements to process
11074     movl(tmp3_aliased, -1);
11075     shlxl(tmp3_aliased, tmp3_aliased, tmp2);
11076     notl(tmp3_aliased);
11077     kmovdl(k1, tmp3_aliased);
11078     evpmovzxbw(tmp1, k1, Address(src, 0), Assembler::AVX_512bit);
11079     evmovdquw(Address(dst, 0), k1, tmp1, Assembler::AVX_512bit);
11080 
11081     // Restore k1
11082     kmovql(k1, k2);
11083     jmp(done);
11084 
11085     clear_vector_masking();   // closing of the stub context for programming mask registers
11086   }
11087   if (UseSSE42Intrinsics) {
11088     Label copy_16_loop, copy_8_loop, copy_bytes, copy_new_tail, copy_tail;
11089 
11090     movl(tmp2, len);
11091 
11092     if (UseAVX > 1) {
11093       andl(tmp2, (16 - 1));
11094       andl(len, -16);
11095       jccb(Assembler::zero, copy_new_tail);
11096     } else {
11097       andl(tmp2, 0x00000007);   // tail count (in chars)
11098       andl(len, 0xfffffff8);    // vector count (in chars)
11099       jccb(Assembler::zero, copy_tail);
11100     }
11101 
11102     // vectored inflation
11103     lea(src, Address(src, len, Address::times_1));
11104     lea(dst, Address(dst, len, Address::times_2));
11105     negptr(len);
11106 
11107     if (UseAVX > 1) {
11108       bind(copy_16_loop);
11109       vpmovzxbw(tmp1, Address(src, len, Address::times_1), Assembler::AVX_256bit);
11110       vmovdqu(Address(dst, len, Address::times_2), tmp1);
11111       addptr(len, 16);
11112       jcc(Assembler::notZero, copy_16_loop);
11113 
11114       bind(below_threshold);
11115       bind(copy_new_tail);
11116       if ((UseAVX > 2) &&
11117         VM_Version::supports_avx512vlbw() &&
11118         VM_Version::supports_bmi2()) {
11119         movl(tmp2, len);
11120       } else {
11121         movl(len, tmp2);
11122       }
11123       andl(tmp2, 0x00000007);
11124       andl(len, 0xFFFFFFF8);
11125       jccb(Assembler::zero, copy_tail);
11126 
11127       pmovzxbw(tmp1, Address(src, 0));
11128       movdqu(Address(dst, 0), tmp1);
11129       addptr(src, 8);
11130       addptr(dst, 2 * 8);
11131 
11132       jmp(copy_tail, true);
11133     }
11134 
11135     // inflate 8 chars per iter
11136     bind(copy_8_loop);
11137     pmovzxbw(tmp1, Address(src, len, Address::times_1));  // unpack to 8 words
11138     movdqu(Address(dst, len, Address::times_2), tmp1);
11139     addptr(len, 8);
11140     jcc(Assembler::notZero, copy_8_loop);
11141 
11142     bind(copy_tail);
11143     movl(len, tmp2);
11144 
11145     cmpl(len, 4);
11146     jccb(Assembler::less, copy_bytes);
11147 
11148     movdl(tmp1, Address(src, 0));  // load 4 byte chars
11149     pmovzxbw(tmp1, tmp1);
11150     movq(Address(dst, 0), tmp1);
11151     subptr(len, 4);
11152     addptr(src, 4);
11153     addptr(dst, 8);
11154 
11155     bind(copy_bytes);
11156   }
11157   testl(len, len);
11158   jccb(Assembler::zero, done);
11159   lea(src, Address(src, len, Address::times_1));
11160   lea(dst, Address(dst, len, Address::times_2));
11161   negptr(len);
11162 
11163   // inflate 1 char per iter
11164   bind(copy_chars_loop);
11165   load_unsigned_byte(tmp2, Address(src, len, Address::times_1));  // load byte char
11166   movw(Address(dst, len, Address::times_2), tmp2);  // inflate byte char to word
11167   increment(len);
11168   jcc(Assembler::notZero, copy_chars_loop);
11169 
11170   bind(done);
11171 }
11172 
11173 Assembler::Condition MacroAssembler::negate_condition(Assembler::Condition cond) {
11174   switch (cond) {
11175     // Note some conditions are synonyms for others
11176     case Assembler::zero:         return Assembler::notZero;
11177     case Assembler::notZero:      return Assembler::zero;
11178     case Assembler::less:         return Assembler::greaterEqual;
11179     case Assembler::lessEqual:    return Assembler::greater;
11180     case Assembler::greater:      return Assembler::lessEqual;
11181     case Assembler::greaterEqual: return Assembler::less;
11182     case Assembler::below:        return Assembler::aboveEqual;
11183     case Assembler::belowEqual:   return Assembler::above;
11184     case Assembler::above:        return Assembler::belowEqual;
11185     case Assembler::aboveEqual:   return Assembler::below;
11186     case Assembler::overflow:     return Assembler::noOverflow;
11187     case Assembler::noOverflow:   return Assembler::overflow;
11188     case Assembler::negative:     return Assembler::positive;
11189     case Assembler::positive:     return Assembler::negative;
11190     case Assembler::parity:       return Assembler::noParity;
11191     case Assembler::noParity:     return Assembler::parity;
11192   }
11193   ShouldNotReachHere(); return Assembler::overflow;
11194 }
11195 
11196 SkipIfEqual::SkipIfEqual(
11197     MacroAssembler* masm, const bool* flag_addr, bool value) {
11198   _masm = masm;
11199   _masm->cmp8(ExternalAddress((address)flag_addr), value);
11200   _masm->jcc(Assembler::equal, _label);
11201 }
11202 
11203 SkipIfEqual::~SkipIfEqual() {
11204   _masm->bind(_label);
11205 }
11206 
11207 // 32-bit Windows has its own fast-path implementation
11208 // of get_thread
11209 #if !defined(WIN32) || defined(_LP64)
11210 
11211 // This is simply a call to Thread::current()
11212 void MacroAssembler::get_thread(Register thread) {
11213   if (thread != rax) {
11214     push(rax);
11215   }
11216   LP64_ONLY(push(rdi);)
11217   LP64_ONLY(push(rsi);)
11218   push(rdx);
11219   push(rcx);
11220 #ifdef _LP64
11221   push(r8);
11222   push(r9);
11223   push(r10);
11224   push(r11);
11225 #endif
11226 
11227   MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, Thread::current), 0);
11228 
11229 #ifdef _LP64
11230   pop(r11);
11231   pop(r10);
11232   pop(r9);
11233   pop(r8);
11234 #endif
11235   pop(rcx);
11236   pop(rdx);
11237   LP64_ONLY(pop(rsi);)
11238   LP64_ONLY(pop(rdi);)
11239   if (thread != rax) {
11240     mov(thread, rax);
11241     pop(rax);
11242   }
11243 }
11244 
11245 #endif