1 //
2 // Copyright (c) 2003, 2015, Oracle and/or its affiliates. All rights reserved.
3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 //
5 // This code is free software; you can redistribute it and/or modify it
6 // under the terms of the GNU General Public License version 2 only, as
7 // published by the Free Software Foundation.
8 //
9 // This code is distributed in the hope that it will be useful, but WITHOUT
10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 // version 2 for more details (a copy is included in the LICENSE file that
13 // accompanied this code).
14 //
15 // You should have received a copy of the GNU General Public License version
16 // 2 along with this work; if not, write to the Free Software Foundation,
17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 //
19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 // or visit www.oracle.com if you need additional information or have any
21 // questions.
22 //
23 //
24
25 // AMD64 Architecture Description File
26
27 //----------REGISTER DEFINITION BLOCK------------------------------------------
28 // This information is used by the matcher and the register allocator to
29 // describe individual registers and classes of registers within the target
30 // archtecture.
31
32 register %{
33 //----------Architecture Description Register Definitions----------------------
34 // General Registers
35 // "reg_def" name ( register save type, C convention save type,
36 // ideal register type, encoding );
37 // Register Save Types:
38 //
39 // NS = No-Save: The register allocator assumes that these registers
40 // can be used without saving upon entry to the method, &
41 // that they do not need to be saved at call sites.
42 //
43 // SOC = Save-On-Call: The register allocator assumes that these registers
44 // can be used without saving upon entry to the method,
45 // but that they must be saved at call sites.
46 //
47 // SOE = Save-On-Entry: The register allocator assumes that these registers
48 // must be saved before using them upon entry to the
49 // method, but they do not need to be saved at call
50 // sites.
51 //
52 // AS = Always-Save: The register allocator assumes that these registers
53 // must be saved before using them upon entry to the
54 // method, & that they must be saved at call sites.
55 //
56 // Ideal Register Type is used to determine how to save & restore a
57 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
58 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
59 //
60 // The encoding number is the actual bit-pattern placed into the opcodes.
61
62 // General Registers
63 // R8-R15 must be encoded with REX. (RSP, RBP, RSI, RDI need REX when
64 // used as byte registers)
65
66 // Previously set RBX, RSI, and RDI as save-on-entry for java code
67 // Turn off SOE in java-code due to frequent use of uncommon-traps.
68 // Now that allocator is better, turn on RSI and RDI as SOE registers.
69
70 reg_def RAX (SOC, SOC, Op_RegI, 0, rax->as_VMReg());
71 reg_def RAX_H(SOC, SOC, Op_RegI, 0, rax->as_VMReg()->next());
72
73 reg_def RCX (SOC, SOC, Op_RegI, 1, rcx->as_VMReg());
74 reg_def RCX_H(SOC, SOC, Op_RegI, 1, rcx->as_VMReg()->next());
75
76 reg_def RDX (SOC, SOC, Op_RegI, 2, rdx->as_VMReg());
77 reg_def RDX_H(SOC, SOC, Op_RegI, 2, rdx->as_VMReg()->next());
78
79 reg_def RBX (SOC, SOE, Op_RegI, 3, rbx->as_VMReg());
80 reg_def RBX_H(SOC, SOE, Op_RegI, 3, rbx->as_VMReg()->next());
81
82 reg_def RSP (NS, NS, Op_RegI, 4, rsp->as_VMReg());
83 reg_def RSP_H(NS, NS, Op_RegI, 4, rsp->as_VMReg()->next());
84
85 // now that adapter frames are gone RBP is always saved and restored by the prolog/epilog code
86 reg_def RBP (NS, SOE, Op_RegI, 5, rbp->as_VMReg());
87 reg_def RBP_H(NS, SOE, Op_RegI, 5, rbp->as_VMReg()->next());
88
89 #ifdef _WIN64
90
91 reg_def RSI (SOC, SOE, Op_RegI, 6, rsi->as_VMReg());
92 reg_def RSI_H(SOC, SOE, Op_RegI, 6, rsi->as_VMReg()->next());
93
94 reg_def RDI (SOC, SOE, Op_RegI, 7, rdi->as_VMReg());
95 reg_def RDI_H(SOC, SOE, Op_RegI, 7, rdi->as_VMReg()->next());
96
97 #else
98
99 reg_def RSI (SOC, SOC, Op_RegI, 6, rsi->as_VMReg());
100 reg_def RSI_H(SOC, SOC, Op_RegI, 6, rsi->as_VMReg()->next());
101
102 reg_def RDI (SOC, SOC, Op_RegI, 7, rdi->as_VMReg());
103 reg_def RDI_H(SOC, SOC, Op_RegI, 7, rdi->as_VMReg()->next());
104
105 #endif
106
107 reg_def R8 (SOC, SOC, Op_RegI, 8, r8->as_VMReg());
108 reg_def R8_H (SOC, SOC, Op_RegI, 8, r8->as_VMReg()->next());
109
110 reg_def R9 (SOC, SOC, Op_RegI, 9, r9->as_VMReg());
111 reg_def R9_H (SOC, SOC, Op_RegI, 9, r9->as_VMReg()->next());
112
113 reg_def R10 (SOC, SOC, Op_RegI, 10, r10->as_VMReg());
114 reg_def R10_H(SOC, SOC, Op_RegI, 10, r10->as_VMReg()->next());
115
116 reg_def R11 (SOC, SOC, Op_RegI, 11, r11->as_VMReg());
117 reg_def R11_H(SOC, SOC, Op_RegI, 11, r11->as_VMReg()->next());
118
119 reg_def R12 (SOC, SOE, Op_RegI, 12, r12->as_VMReg());
120 reg_def R12_H(SOC, SOE, Op_RegI, 12, r12->as_VMReg()->next());
121
122 reg_def R13 (SOC, SOE, Op_RegI, 13, r13->as_VMReg());
123 reg_def R13_H(SOC, SOE, Op_RegI, 13, r13->as_VMReg()->next());
124
125 reg_def R14 (SOC, SOE, Op_RegI, 14, r14->as_VMReg());
126 reg_def R14_H(SOC, SOE, Op_RegI, 14, r14->as_VMReg()->next());
127
128 reg_def R15 (SOC, SOE, Op_RegI, 15, r15->as_VMReg());
129 reg_def R15_H(SOC, SOE, Op_RegI, 15, r15->as_VMReg()->next());
130
131
132 // Floating Point Registers
133
134 // Specify priority of register selection within phases of register
135 // allocation. Highest priority is first. A useful heuristic is to
136 // give registers a low priority when they are required by machine
137 // instructions, like EAX and EDX on I486, and choose no-save registers
138 // before save-on-call, & save-on-call before save-on-entry. Registers
139 // which participate in fixed calling sequences should come last.
140 // Registers which are used as pairs must fall on an even boundary.
141
142 alloc_class chunk0(R10, R10_H,
143 R11, R11_H,
144 R8, R8_H,
145 R9, R9_H,
146 R12, R12_H,
147 RCX, RCX_H,
148 RBX, RBX_H,
149 RDI, RDI_H,
150 RDX, RDX_H,
151 RSI, RSI_H,
152 RAX, RAX_H,
153 RBP, RBP_H,
154 R13, R13_H,
155 R14, R14_H,
156 R15, R15_H,
157 RSP, RSP_H);
158
159
160 //----------Architecture Description Register Classes--------------------------
161 // Several register classes are automatically defined based upon information in
162 // this architecture description.
163 // 1) reg_class inline_cache_reg ( /* as def'd in frame section */ )
164 // 2) reg_class compiler_method_oop_reg ( /* as def'd in frame section */ )
165 // 2) reg_class interpreter_method_oop_reg ( /* as def'd in frame section */ )
166 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
167 //
168
169 // Empty register class.
170 reg_class no_reg();
171
172 // Class for all pointer registers (including RSP and RBP)
173 reg_class any_reg_with_rbp(RAX, RAX_H,
174 RDX, RDX_H,
175 RBP, RBP_H,
176 RDI, RDI_H,
177 RSI, RSI_H,
178 RCX, RCX_H,
179 RBX, RBX_H,
180 RSP, RSP_H,
181 R8, R8_H,
182 R9, R9_H,
183 R10, R10_H,
184 R11, R11_H,
185 R12, R12_H,
186 R13, R13_H,
187 R14, R14_H,
188 R15, R15_H);
189
190 // Class for all pointer registers (including RSP, but excluding RBP)
191 reg_class any_reg_no_rbp(RAX, RAX_H,
192 RDX, RDX_H,
193 RDI, RDI_H,
194 RSI, RSI_H,
195 RCX, RCX_H,
196 RBX, RBX_H,
197 RSP, RSP_H,
198 R8, R8_H,
199 R9, R9_H,
200 R10, R10_H,
201 R11, R11_H,
202 R12, R12_H,
203 R13, R13_H,
204 R14, R14_H,
205 R15, R15_H);
206
207 // Dynamic register class that selects at runtime between register classes
208 // any_reg_no_rbp and any_reg_with_rbp (depending on the value of the flag PreserveFramePointer).
209 // Equivalent to: return PreserveFramePointer ? any_reg_no_rbp : any_reg_with_rbp;
210 reg_class_dynamic any_reg(any_reg_no_rbp, any_reg_with_rbp, %{ PreserveFramePointer %});
211
212 // Class for all pointer registers (excluding RSP)
213 reg_class ptr_reg_with_rbp(RAX, RAX_H,
214 RDX, RDX_H,
215 RBP, RBP_H,
216 RDI, RDI_H,
217 RSI, RSI_H,
218 RCX, RCX_H,
219 RBX, RBX_H,
220 R8, R8_H,
221 R9, R9_H,
222 R10, R10_H,
223 R11, R11_H,
224 R13, R13_H,
225 R14, R14_H);
226
227 // Class for all pointer registers (excluding RSP and RBP)
228 reg_class ptr_reg_no_rbp(RAX, RAX_H,
229 RDX, RDX_H,
230 RDI, RDI_H,
231 RSI, RSI_H,
232 RCX, RCX_H,
233 RBX, RBX_H,
234 R8, R8_H,
235 R9, R9_H,
236 R10, R10_H,
237 R11, R11_H,
238 R13, R13_H,
239 R14, R14_H);
240
241 // Dynamic register class that selects between ptr_reg_no_rbp and ptr_reg_with_rbp.
242 reg_class_dynamic ptr_reg(ptr_reg_no_rbp, ptr_reg_with_rbp, %{ PreserveFramePointer %});
243
244 // Class for all pointer registers (excluding RAX and RSP)
245 reg_class ptr_no_rax_reg_with_rbp(RDX, RDX_H,
246 RBP, RBP_H,
247 RDI, RDI_H,
248 RSI, RSI_H,
249 RCX, RCX_H,
250 RBX, RBX_H,
251 R8, R8_H,
252 R9, R9_H,
253 R10, R10_H,
254 R11, R11_H,
255 R13, R13_H,
256 R14, R14_H);
257
258 // Class for all pointer registers (excluding RAX, RSP, and RBP)
259 reg_class ptr_no_rax_reg_no_rbp(RDX, RDX_H,
260 RDI, RDI_H,
261 RSI, RSI_H,
262 RCX, RCX_H,
263 RBX, RBX_H,
264 R8, R8_H,
265 R9, R9_H,
266 R10, R10_H,
267 R11, R11_H,
268 R13, R13_H,
269 R14, R14_H);
270
271 // Dynamic register class that selects between ptr_no_rax_reg_no_rbp and ptr_no_rax_reg_with_rbp.
272 reg_class_dynamic ptr_no_rax_reg(ptr_no_rax_reg_no_rbp, ptr_no_rax_reg_with_rbp, %{ PreserveFramePointer %});
273
274 // Class for all pointer registers (excluding RAX, RBX, and RSP)
275 reg_class ptr_no_rax_rbx_reg_with_rbp(RDX, RDX_H,
276 RBP, RBP_H,
277 RDI, RDI_H,
278 RSI, RSI_H,
279 RCX, RCX_H,
280 R8, R8_H,
281 R9, R9_H,
282 R10, R10_H,
283 R11, R11_H,
284 R13, R13_H,
285 R14, R14_H);
286
287 // Class for all pointer registers (excluding RAX, RBX, RSP, and RBP)
288 reg_class ptr_no_rax_rbx_reg_no_rbp(RDX, RDX_H,
289 RDI, RDI_H,
290 RSI, RSI_H,
291 RCX, RCX_H,
292 R8, R8_H,
293 R9, R9_H,
294 R10, R10_H,
295 R11, R11_H,
296 R13, R13_H,
297 R14, R14_H);
298
299 // Dynamic register class that selects between ptr_no_rax_rbx_reg_no_rbp and ptr_no_rax_rbx_reg_with_rbp.
300 reg_class_dynamic ptr_no_rax_rbx_reg(ptr_no_rax_rbx_reg_no_rbp, ptr_no_rax_rbx_reg_with_rbp, %{ PreserveFramePointer %});
301
302 // Singleton class for RAX pointer register
303 reg_class ptr_rax_reg(RAX, RAX_H);
304
305 // Singleton class for RBX pointer register
306 reg_class ptr_rbx_reg(RBX, RBX_H);
307
308 // Singleton class for RSI pointer register
309 reg_class ptr_rsi_reg(RSI, RSI_H);
310
311 // Singleton class for RDI pointer register
312 reg_class ptr_rdi_reg(RDI, RDI_H);
313
314 // Singleton class for stack pointer
315 reg_class ptr_rsp_reg(RSP, RSP_H);
316
317 // Singleton class for TLS pointer
318 reg_class ptr_r15_reg(R15, R15_H);
319
320 // Class for all long registers (excluding RSP)
321 reg_class long_reg_with_rbp(RAX, RAX_H,
322 RDX, RDX_H,
323 RBP, RBP_H,
324 RDI, RDI_H,
325 RSI, RSI_H,
326 RCX, RCX_H,
327 RBX, RBX_H,
328 R8, R8_H,
329 R9, R9_H,
330 R10, R10_H,
331 R11, R11_H,
332 R13, R13_H,
333 R14, R14_H);
334
335 // Class for all long registers (excluding RSP and RBP)
336 reg_class long_reg_no_rbp(RAX, RAX_H,
337 RDX, RDX_H,
338 RDI, RDI_H,
339 RSI, RSI_H,
340 RCX, RCX_H,
341 RBX, RBX_H,
342 R8, R8_H,
343 R9, R9_H,
344 R10, R10_H,
345 R11, R11_H,
346 R13, R13_H,
347 R14, R14_H);
348
349 // Dynamic register class that selects between long_reg_no_rbp and long_reg_with_rbp.
350 reg_class_dynamic long_reg(long_reg_no_rbp, long_reg_with_rbp, %{ PreserveFramePointer %});
351
352 // Class for all long registers (excluding RAX, RDX and RSP)
353 reg_class long_no_rax_rdx_reg_with_rbp(RBP, RBP_H,
354 RDI, RDI_H,
355 RSI, RSI_H,
356 RCX, RCX_H,
357 RBX, RBX_H,
358 R8, R8_H,
359 R9, R9_H,
360 R10, R10_H,
361 R11, R11_H,
362 R13, R13_H,
363 R14, R14_H);
364
365 // Class for all long registers (excluding RAX, RDX, RSP, and RBP)
366 reg_class long_no_rax_rdx_reg_no_rbp(RDI, RDI_H,
367 RSI, RSI_H,
368 RCX, RCX_H,
369 RBX, RBX_H,
370 R8, R8_H,
371 R9, R9_H,
372 R10, R10_H,
373 R11, R11_H,
374 R13, R13_H,
375 R14, R14_H);
376
377 // Dynamic register class that selects between long_no_rax_rdx_reg_no_rbp and long_no_rax_rdx_reg_with_rbp.
378 reg_class_dynamic long_no_rax_rdx_reg(long_no_rax_rdx_reg_no_rbp, long_no_rax_rdx_reg_with_rbp, %{ PreserveFramePointer %});
379
380 // Class for all long registers (excluding RCX and RSP)
381 reg_class long_no_rcx_reg_with_rbp(RBP, RBP_H,
382 RDI, RDI_H,
383 RSI, RSI_H,
384 RAX, RAX_H,
385 RDX, RDX_H,
386 RBX, RBX_H,
387 R8, R8_H,
388 R9, R9_H,
389 R10, R10_H,
390 R11, R11_H,
391 R13, R13_H,
392 R14, R14_H);
393
394 // Class for all long registers (excluding RCX, RSP, and RBP)
395 reg_class long_no_rcx_reg_no_rbp(RDI, RDI_H,
396 RSI, RSI_H,
397 RAX, RAX_H,
398 RDX, RDX_H,
399 RBX, RBX_H,
400 R8, R8_H,
401 R9, R9_H,
402 R10, R10_H,
403 R11, R11_H,
404 R13, R13_H,
405 R14, R14_H);
406
407 // Dynamic register class that selects between long_no_rcx_reg_no_rbp and long_no_rcx_reg_with_rbp.
408 reg_class_dynamic long_no_rcx_reg(long_no_rcx_reg_no_rbp, long_no_rcx_reg_with_rbp, %{ PreserveFramePointer %});
409
410 // Singleton class for RAX long register
411 reg_class long_rax_reg(RAX, RAX_H);
412
413 // Singleton class for RCX long register
414 reg_class long_rcx_reg(RCX, RCX_H);
415
416 // Singleton class for RDX long register
417 reg_class long_rdx_reg(RDX, RDX_H);
418
419 // Class for all int registers (excluding RSP)
420 reg_class int_reg_with_rbp(RAX,
421 RDX,
422 RBP,
423 RDI,
424 RSI,
425 RCX,
426 RBX,
427 R8,
428 R9,
429 R10,
430 R11,
431 R13,
432 R14);
433
434 // Class for all int registers (excluding RSP and RBP)
435 reg_class int_reg_no_rbp(RAX,
436 RDX,
437 RDI,
438 RSI,
439 RCX,
440 RBX,
441 R8,
442 R9,
443 R10,
444 R11,
445 R13,
446 R14);
447
448 // Dynamic register class that selects between int_reg_no_rbp and int_reg_with_rbp.
449 reg_class_dynamic int_reg(int_reg_no_rbp, int_reg_with_rbp, %{ PreserveFramePointer %});
450
451 // Class for all int registers (excluding RCX and RSP)
452 reg_class int_no_rcx_reg_with_rbp(RAX,
453 RDX,
454 RBP,
455 RDI,
456 RSI,
457 RBX,
458 R8,
459 R9,
460 R10,
461 R11,
462 R13,
463 R14);
464
465 // Class for all int registers (excluding RCX, RSP, and RBP)
466 reg_class int_no_rcx_reg_no_rbp(RAX,
467 RDX,
468 RDI,
469 RSI,
470 RBX,
471 R8,
472 R9,
473 R10,
474 R11,
475 R13,
476 R14);
477
478 // Dynamic register class that selects between int_no_rcx_reg_no_rbp and int_no_rcx_reg_with_rbp.
479 reg_class_dynamic int_no_rcx_reg(int_no_rcx_reg_no_rbp, int_no_rcx_reg_with_rbp, %{ PreserveFramePointer %});
480
481 // Class for all int registers (excluding RAX, RDX, and RSP)
482 reg_class int_no_rax_rdx_reg_with_rbp(RBP,
483 RDI,
484 RSI,
485 RCX,
486 RBX,
487 R8,
488 R9,
489 R10,
490 R11,
491 R13,
492 R14);
493
494 // Class for all int registers (excluding RAX, RDX, RSP, and RBP)
495 reg_class int_no_rax_rdx_reg_no_rbp(RDI,
496 RSI,
497 RCX,
498 RBX,
499 R8,
500 R9,
501 R10,
502 R11,
503 R13,
504 R14);
505
506 // Dynamic register class that selects between int_no_rax_rdx_reg_no_rbp and int_no_rax_rdx_reg_with_rbp.
507 reg_class_dynamic int_no_rax_rdx_reg(int_no_rax_rdx_reg_no_rbp, int_no_rax_rdx_reg_with_rbp, %{ PreserveFramePointer %});
508
509 // Singleton class for RAX int register
510 reg_class int_rax_reg(RAX);
511
512 // Singleton class for RBX int register
513 reg_class int_rbx_reg(RBX);
514
515 // Singleton class for RCX int register
516 reg_class int_rcx_reg(RCX);
517
518 // Singleton class for RCX int register
519 reg_class int_rdx_reg(RDX);
520
521 // Singleton class for RCX int register
522 reg_class int_rdi_reg(RDI);
523
524 // Singleton class for instruction pointer
525 // reg_class ip_reg(RIP);
526
527 %}
528
529 //----------SOURCE BLOCK-------------------------------------------------------
530 // This is a block of C++ code which provides values, functions, and
531 // definitions necessary in the rest of the architecture description
532 source %{
533 #define RELOC_IMM64 Assembler::imm_operand
534 #define RELOC_DISP32 Assembler::disp32_operand
535
536 #define __ _masm.
537
538 static int clear_avx_size() {
539 return (Compile::current()->max_vector_size() > 16) ? 3 : 0; // vzeroupper
540 }
541
542 // !!!!! Special hack to get all types of calls to specify the byte offset
543 // from the start of the call to the point where the return address
544 // will point.
545 int MachCallStaticJavaNode::ret_addr_offset()
546 {
547 int offset = 5; // 5 bytes from start of call to where return address points
548 offset += clear_avx_size();
549 return offset;
550 }
551
552 int MachCallDynamicJavaNode::ret_addr_offset()
553 {
554 int offset = 15; // 15 bytes from start of call to where return address points
555 offset += clear_avx_size();
556 return offset;
557 }
558
559 int MachCallRuntimeNode::ret_addr_offset() {
560 int offset = 13; // movq r10,#addr; callq (r10)
561 offset += clear_avx_size();
562 return offset;
563 }
564
565 // Indicate if the safepoint node needs the polling page as an input,
566 // it does if the polling page is more than disp32 away.
567 bool SafePointNode::needs_polling_address_input()
568 {
569 return Assembler::is_polling_page_far();
570 }
571
572 //
573 // Compute padding required for nodes which need alignment
574 //
575
576 // The address of the call instruction needs to be 4-byte aligned to
577 // ensure that it does not span a cache line so that it can be patched.
578 int CallStaticJavaDirectNode::compute_padding(int current_offset) const
579 {
580 current_offset += clear_avx_size(); // skip vzeroupper
581 current_offset += 1; // skip call opcode byte
582 return round_to(current_offset, alignment_required()) - current_offset;
583 }
584
585 // The address of the call instruction needs to be 4-byte aligned to
586 // ensure that it does not span a cache line so that it can be patched.
587 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const
588 {
589 current_offset += clear_avx_size(); // skip vzeroupper
590 current_offset += 11; // skip movq instruction + call opcode byte
591 return round_to(current_offset, alignment_required()) - current_offset;
592 }
593
594 // EMIT_RM()
595 void emit_rm(CodeBuffer &cbuf, int f1, int f2, int f3) {
596 unsigned char c = (unsigned char) ((f1 << 6) | (f2 << 3) | f3);
597 cbuf.insts()->emit_int8(c);
598 }
599
600 // EMIT_CC()
601 void emit_cc(CodeBuffer &cbuf, int f1, int f2) {
602 unsigned char c = (unsigned char) (f1 | f2);
603 cbuf.insts()->emit_int8(c);
604 }
605
606 // EMIT_OPCODE()
607 void emit_opcode(CodeBuffer &cbuf, int code) {
608 cbuf.insts()->emit_int8((unsigned char) code);
609 }
610
611 // EMIT_OPCODE() w/ relocation information
612 void emit_opcode(CodeBuffer &cbuf,
613 int code, relocInfo::relocType reloc, int offset, int format)
614 {
615 cbuf.relocate(cbuf.insts_mark() + offset, reloc, format);
616 emit_opcode(cbuf, code);
617 }
618
619 // EMIT_D8()
620 void emit_d8(CodeBuffer &cbuf, int d8) {
621 cbuf.insts()->emit_int8((unsigned char) d8);
622 }
623
624 // EMIT_D16()
625 void emit_d16(CodeBuffer &cbuf, int d16) {
626 cbuf.insts()->emit_int16(d16);
627 }
628
629 // EMIT_D32()
630 void emit_d32(CodeBuffer &cbuf, int d32) {
631 cbuf.insts()->emit_int32(d32);
632 }
633
634 // EMIT_D64()
635 void emit_d64(CodeBuffer &cbuf, int64_t d64) {
636 cbuf.insts()->emit_int64(d64);
637 }
638
639 // emit 32 bit value and construct relocation entry from relocInfo::relocType
640 void emit_d32_reloc(CodeBuffer& cbuf,
641 int d32,
642 relocInfo::relocType reloc,
643 int format)
644 {
645 assert(reloc != relocInfo::external_word_type, "use 2-arg emit_d32_reloc");
646 cbuf.relocate(cbuf.insts_mark(), reloc, format);
647 cbuf.insts()->emit_int32(d32);
648 }
649
650 // emit 32 bit value and construct relocation entry from RelocationHolder
651 void emit_d32_reloc(CodeBuffer& cbuf, int d32, RelocationHolder const& rspec, int format) {
652 #ifdef ASSERT
653 if (rspec.reloc()->type() == relocInfo::oop_type &&
654 d32 != 0 && d32 != (intptr_t) Universe::non_oop_word()) {
655 assert(Universe::heap()->is_in_reserved((address)(intptr_t)d32), "should be real oop");
656 assert(cast_to_oop((intptr_t)d32)->is_oop() && (ScavengeRootsInCode || !cast_to_oop((intptr_t)d32)->is_scavengable()), "cannot embed scavengable oops in code");
657 }
658 #endif
659 cbuf.relocate(cbuf.insts_mark(), rspec, format);
660 cbuf.insts()->emit_int32(d32);
661 }
662
663 void emit_d32_reloc(CodeBuffer& cbuf, address addr) {
664 address next_ip = cbuf.insts_end() + 4;
665 emit_d32_reloc(cbuf, (int) (addr - next_ip),
666 external_word_Relocation::spec(addr),
667 RELOC_DISP32);
668 }
669
670
671 // emit 64 bit value and construct relocation entry from relocInfo::relocType
672 void emit_d64_reloc(CodeBuffer& cbuf, int64_t d64, relocInfo::relocType reloc, int format) {
673 cbuf.relocate(cbuf.insts_mark(), reloc, format);
674 cbuf.insts()->emit_int64(d64);
675 }
676
677 // emit 64 bit value and construct relocation entry from RelocationHolder
678 void emit_d64_reloc(CodeBuffer& cbuf, int64_t d64, RelocationHolder const& rspec, int format) {
679 #ifdef ASSERT
680 if (rspec.reloc()->type() == relocInfo::oop_type &&
681 d64 != 0 && d64 != (int64_t) Universe::non_oop_word()) {
682 assert(Universe::heap()->is_in_reserved((address)d64), "should be real oop");
683 assert(cast_to_oop(d64)->is_oop() && (ScavengeRootsInCode || !cast_to_oop(d64)->is_scavengable()),
684 "cannot embed scavengable oops in code");
685 }
686 #endif
687 cbuf.relocate(cbuf.insts_mark(), rspec, format);
688 cbuf.insts()->emit_int64(d64);
689 }
690
691 // Access stack slot for load or store
692 void store_to_stackslot(CodeBuffer &cbuf, int opcode, int rm_field, int disp)
693 {
694 emit_opcode(cbuf, opcode); // (e.g., FILD [RSP+src])
695 if (-0x80 <= disp && disp < 0x80) {
696 emit_rm(cbuf, 0x01, rm_field, RSP_enc); // R/M byte
697 emit_rm(cbuf, 0x00, RSP_enc, RSP_enc); // SIB byte
698 emit_d8(cbuf, disp); // Displacement // R/M byte
699 } else {
700 emit_rm(cbuf, 0x02, rm_field, RSP_enc); // R/M byte
701 emit_rm(cbuf, 0x00, RSP_enc, RSP_enc); // SIB byte
702 emit_d32(cbuf, disp); // Displacement // R/M byte
703 }
704 }
705
706 // rRegI ereg, memory mem) %{ // emit_reg_mem
707 void encode_RegMem(CodeBuffer &cbuf,
708 int reg,
709 int base, int index, int scale, int disp, relocInfo::relocType disp_reloc)
710 {
711 assert(disp_reloc == relocInfo::none, "cannot have disp");
712 int regenc = reg & 7;
713 int baseenc = base & 7;
714 int indexenc = index & 7;
715
716 // There is no index & no scale, use form without SIB byte
717 if (index == 0x4 && scale == 0 && base != RSP_enc && base != R12_enc) {
718 // If no displacement, mode is 0x0; unless base is [RBP] or [R13]
719 if (disp == 0 && base != RBP_enc && base != R13_enc) {
720 emit_rm(cbuf, 0x0, regenc, baseenc); // *
721 } else if (-0x80 <= disp && disp < 0x80 && disp_reloc == relocInfo::none) {
722 // If 8-bit displacement, mode 0x1
723 emit_rm(cbuf, 0x1, regenc, baseenc); // *
724 emit_d8(cbuf, disp);
725 } else {
726 // If 32-bit displacement
727 if (base == -1) { // Special flag for absolute address
728 emit_rm(cbuf, 0x0, regenc, 0x5); // *
729 if (disp_reloc != relocInfo::none) {
730 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);
731 } else {
732 emit_d32(cbuf, disp);
733 }
734 } else {
735 // Normal base + offset
736 emit_rm(cbuf, 0x2, regenc, baseenc); // *
737 if (disp_reloc != relocInfo::none) {
738 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);
739 } else {
740 emit_d32(cbuf, disp);
741 }
742 }
743 }
744 } else {
745 // Else, encode with the SIB byte
746 // If no displacement, mode is 0x0; unless base is [RBP] or [R13]
747 if (disp == 0 && base != RBP_enc && base != R13_enc) {
748 // If no displacement
749 emit_rm(cbuf, 0x0, regenc, 0x4); // *
750 emit_rm(cbuf, scale, indexenc, baseenc);
751 } else {
752 if (-0x80 <= disp && disp < 0x80 && disp_reloc == relocInfo::none) {
753 // If 8-bit displacement, mode 0x1
754 emit_rm(cbuf, 0x1, regenc, 0x4); // *
755 emit_rm(cbuf, scale, indexenc, baseenc);
756 emit_d8(cbuf, disp);
757 } else {
758 // If 32-bit displacement
759 if (base == 0x04 ) {
760 emit_rm(cbuf, 0x2, regenc, 0x4);
761 emit_rm(cbuf, scale, indexenc, 0x04); // XXX is this valid???
762 } else {
763 emit_rm(cbuf, 0x2, regenc, 0x4);
764 emit_rm(cbuf, scale, indexenc, baseenc); // *
765 }
766 if (disp_reloc != relocInfo::none) {
767 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);
768 } else {
769 emit_d32(cbuf, disp);
770 }
771 }
772 }
773 }
774 }
775
776 // This could be in MacroAssembler but it's fairly C2 specific
777 void emit_cmpfp_fixup(MacroAssembler& _masm) {
778 Label exit;
779 __ jccb(Assembler::noParity, exit);
780 __ pushf();
781 //
782 // comiss/ucomiss instructions set ZF,PF,CF flags and
783 // zero OF,AF,SF for NaN values.
784 // Fixup flags by zeroing ZF,PF so that compare of NaN
785 // values returns 'less than' result (CF is set).
786 // Leave the rest of flags unchanged.
787 //
788 // 7 6 5 4 3 2 1 0
789 // |S|Z|r|A|r|P|r|C| (r - reserved bit)
790 // 0 0 1 0 1 0 1 1 (0x2B)
791 //
792 __ andq(Address(rsp, 0), 0xffffff2b);
793 __ popf();
794 __ bind(exit);
795 }
796
797 void emit_cmpfp3(MacroAssembler& _masm, Register dst) {
798 Label done;
799 __ movl(dst, -1);
800 __ jcc(Assembler::parity, done);
801 __ jcc(Assembler::below, done);
802 __ setb(Assembler::notEqual, dst);
803 __ movzbl(dst, dst);
804 __ bind(done);
805 }
806
807
808 //=============================================================================
809 const RegMask& MachConstantBaseNode::_out_RegMask = RegMask::Empty;
810
811 int Compile::ConstantTable::calculate_table_base_offset() const {
812 return 0; // absolute addressing, no offset
813 }
814
815 bool MachConstantBaseNode::requires_postalloc_expand() const { return false; }
816 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) {
817 ShouldNotReachHere();
818 }
819
820 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
821 // Empty encoding
822 }
823
824 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {
825 return 0;
826 }
827
828 #ifndef PRODUCT
829 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
830 st->print("# MachConstantBaseNode (empty encoding)");
831 }
832 #endif
833
834
835 //=============================================================================
836 #ifndef PRODUCT
837 void MachPrologNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
838 Compile* C = ra_->C;
839
840 int framesize = C->frame_size_in_bytes();
841 int bangsize = C->bang_size_in_bytes();
842 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
843 // Remove wordSize for return addr which is already pushed.
844 framesize -= wordSize;
845
846 if (C->need_stack_bang(bangsize)) {
847 framesize -= wordSize;
848 st->print("# stack bang (%d bytes)", bangsize);
849 st->print("\n\t");
850 st->print("pushq rbp\t# Save rbp");
851 if (PreserveFramePointer) {
852 st->print("\n\t");
853 st->print("movq rbp, rsp\t# Save the caller's SP into rbp");
854 }
855 if (framesize) {
856 st->print("\n\t");
857 st->print("subq rsp, #%d\t# Create frame",framesize);
858 }
859 } else {
860 st->print("subq rsp, #%d\t# Create frame",framesize);
861 st->print("\n\t");
862 framesize -= wordSize;
863 st->print("movq [rsp + #%d], rbp\t# Save rbp",framesize);
864 if (PreserveFramePointer) {
865 st->print("\n\t");
866 st->print("movq rbp, rsp\t# Save the caller's SP into rbp");
867 if (framesize > 0) {
868 st->print("\n\t");
869 st->print("addq rbp, #%d", framesize);
870 }
871 }
872 }
873
874 if (VerifyStackAtCalls) {
875 st->print("\n\t");
876 framesize -= wordSize;
877 st->print("movq [rsp + #%d], 0xbadb100d\t# Majik cookie for stack depth check",framesize);
878 #ifdef ASSERT
879 st->print("\n\t");
880 st->print("# stack alignment check");
881 #endif
882 }
883 st->cr();
884 }
885 #endif
886
887 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
888 Compile* C = ra_->C;
889 MacroAssembler _masm(&cbuf);
890
891 int framesize = C->frame_size_in_bytes();
892 int bangsize = C->bang_size_in_bytes();
893
894 __ verified_entry(framesize, C->need_stack_bang(bangsize)?bangsize:0, false);
895
896 C->set_frame_complete(cbuf.insts_size());
897
898 if (C->has_mach_constant_base_node()) {
899 // NOTE: We set the table base offset here because users might be
900 // emitted before MachConstantBaseNode.
901 Compile::ConstantTable& constant_table = C->constant_table();
902 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset());
903 }
904 }
905
906 uint MachPrologNode::size(PhaseRegAlloc* ra_) const
907 {
908 return MachNode::size(ra_); // too many variables; just compute it
909 // the hard way
910 }
911
912 int MachPrologNode::reloc() const
913 {
914 return 0; // a large enough number
915 }
916
917 //=============================================================================
918 #ifndef PRODUCT
919 void MachEpilogNode::format(PhaseRegAlloc* ra_, outputStream* st) const
920 {
921 Compile* C = ra_->C;
922 if (C->max_vector_size() > 16) {
923 st->print("vzeroupper");
924 st->cr(); st->print("\t");
925 }
926
927 int framesize = C->frame_size_in_bytes();
928 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
929 // Remove word for return adr already pushed
930 // and RBP
931 framesize -= 2*wordSize;
932
933 if (framesize) {
934 st->print_cr("addq rsp, %d\t# Destroy frame", framesize);
935 st->print("\t");
936 }
937
938 st->print_cr("popq rbp");
939 if (do_polling() && C->is_method_compilation()) {
940 st->print("\t");
941 if (Assembler::is_polling_page_far()) {
942 st->print_cr("movq rscratch1, #polling_page_address\n\t"
943 "testl rax, [rscratch1]\t"
944 "# Safepoint: poll for GC");
945 } else {
946 st->print_cr("testl rax, [rip + #offset_to_poll_page]\t"
947 "# Safepoint: poll for GC");
948 }
949 }
950 }
951 #endif
952
953 void MachEpilogNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
954 {
955 Compile* C = ra_->C;
956 MacroAssembler _masm(&cbuf);
957
958 if (C->max_vector_size() > 16) {
959 // Clear upper bits of YMM registers when current compiled code uses
960 // wide vectors to avoid AVX <-> SSE transition penalty during call.
961 __ vzeroupper();
962 }
963
964 int framesize = C->frame_size_in_bytes();
965 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
966 // Remove word for return adr already pushed
967 // and RBP
968 framesize -= 2*wordSize;
969
970 // Note that VerifyStackAtCalls' Majik cookie does not change the frame size popped here
971
972 if (framesize) {
973 emit_opcode(cbuf, Assembler::REX_W);
974 if (framesize < 0x80) {
975 emit_opcode(cbuf, 0x83); // addq rsp, #framesize
976 emit_rm(cbuf, 0x3, 0x00, RSP_enc);
977 emit_d8(cbuf, framesize);
978 } else {
979 emit_opcode(cbuf, 0x81); // addq rsp, #framesize
980 emit_rm(cbuf, 0x3, 0x00, RSP_enc);
981 emit_d32(cbuf, framesize);
982 }
983 }
984
985 // popq rbp
986 emit_opcode(cbuf, 0x58 | RBP_enc);
987
988 if (StackReservedPages > 0 && C->has_reserved_stack_access()) {
989 __ reserved_stack_check();
990 }
991
992 if (do_polling() && C->is_method_compilation()) {
993 MacroAssembler _masm(&cbuf);
994 AddressLiteral polling_page(os::get_polling_page(), relocInfo::poll_return_type);
995 if (Assembler::is_polling_page_far()) {
996 __ lea(rscratch1, polling_page);
997 __ relocate(relocInfo::poll_return_type);
998 __ testl(rax, Address(rscratch1, 0));
999 } else {
1000 __ testl(rax, polling_page);
1001 }
1002 }
1003 }
1004
1005 uint MachEpilogNode::size(PhaseRegAlloc* ra_) const
1006 {
1007 return MachNode::size(ra_); // too many variables; just compute it
1008 // the hard way
1009 }
1010
1011 int MachEpilogNode::reloc() const
1012 {
1013 return 2; // a large enough number
1014 }
1015
1016 const Pipeline* MachEpilogNode::pipeline() const
1017 {
1018 return MachNode::pipeline_class();
1019 }
1020
1021 int MachEpilogNode::safepoint_offset() const
1022 {
1023 return 0;
1024 }
1025
1026 //=============================================================================
1027
1028 enum RC {
1029 rc_bad,
1030 rc_int,
1031 rc_float,
1032 rc_stack
1033 };
1034
1035 static enum RC rc_class(OptoReg::Name reg)
1036 {
1037 if( !OptoReg::is_valid(reg) ) return rc_bad;
1038
1039 if (OptoReg::is_stack(reg)) return rc_stack;
1040
1041 VMReg r = OptoReg::as_VMReg(reg);
1042
1043 if (r->is_Register()) return rc_int;
1044
1045 assert(r->is_XMMRegister(), "must be");
1046 return rc_float;
1047 }
1048
1049 // Next two methods are shared by 32- and 64-bit VM. They are defined in x86.ad.
1050 static int vec_mov_helper(CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
1051 int src_hi, int dst_hi, uint ireg, outputStream* st);
1052
1053 static int vec_spill_helper(CodeBuffer *cbuf, bool do_size, bool is_load,
1054 int stack_offset, int reg, uint ireg, outputStream* st);
1055
1056 static void vec_stack_to_stack_helper(CodeBuffer *cbuf, int src_offset,
1057 int dst_offset, uint ireg, outputStream* st) {
1058 if (cbuf) {
1059 MacroAssembler _masm(cbuf);
1060 switch (ireg) {
1061 case Op_VecS:
1062 __ movq(Address(rsp, -8), rax);
1063 __ movl(rax, Address(rsp, src_offset));
1064 __ movl(Address(rsp, dst_offset), rax);
1065 __ movq(rax, Address(rsp, -8));
1066 break;
1067 case Op_VecD:
1068 __ pushq(Address(rsp, src_offset));
1069 __ popq (Address(rsp, dst_offset));
1070 break;
1071 case Op_VecX:
1072 __ pushq(Address(rsp, src_offset));
1073 __ popq (Address(rsp, dst_offset));
1074 __ pushq(Address(rsp, src_offset+8));
1075 __ popq (Address(rsp, dst_offset+8));
1076 break;
1077 case Op_VecY:
1078 __ vmovdqu(Address(rsp, -32), xmm0);
1079 __ vmovdqu(xmm0, Address(rsp, src_offset));
1080 __ vmovdqu(Address(rsp, dst_offset), xmm0);
1081 __ vmovdqu(xmm0, Address(rsp, -32));
1082 break;
1083 case Op_VecZ:
1084 __ evmovdquq(Address(rsp, -64), xmm0, 2);
1085 __ evmovdquq(xmm0, Address(rsp, src_offset), 2);
1086 __ evmovdquq(Address(rsp, dst_offset), xmm0, 2);
1087 __ evmovdquq(xmm0, Address(rsp, -64), 2);
1088 break;
1089 default:
1090 ShouldNotReachHere();
1091 }
1092 #ifndef PRODUCT
1093 } else {
1094 switch (ireg) {
1095 case Op_VecS:
1096 st->print("movq [rsp - #8], rax\t# 32-bit mem-mem spill\n\t"
1097 "movl rax, [rsp + #%d]\n\t"
1098 "movl [rsp + #%d], rax\n\t"
1099 "movq rax, [rsp - #8]",
1100 src_offset, dst_offset);
1101 break;
1102 case Op_VecD:
1103 st->print("pushq [rsp + #%d]\t# 64-bit mem-mem spill\n\t"
1104 "popq [rsp + #%d]",
1105 src_offset, dst_offset);
1106 break;
1107 case Op_VecX:
1108 st->print("pushq [rsp + #%d]\t# 128-bit mem-mem spill\n\t"
1109 "popq [rsp + #%d]\n\t"
1110 "pushq [rsp + #%d]\n\t"
1111 "popq [rsp + #%d]",
1112 src_offset, dst_offset, src_offset+8, dst_offset+8);
1113 break;
1114 case Op_VecY:
1115 st->print("vmovdqu [rsp - #32], xmm0\t# 256-bit mem-mem spill\n\t"
1116 "vmovdqu xmm0, [rsp + #%d]\n\t"
1117 "vmovdqu [rsp + #%d], xmm0\n\t"
1118 "vmovdqu xmm0, [rsp - #32]",
1119 src_offset, dst_offset);
1120 break;
1121 case Op_VecZ:
1122 st->print("vmovdqu [rsp - #64], xmm0\t# 512-bit mem-mem spill\n\t"
1123 "vmovdqu xmm0, [rsp + #%d]\n\t"
1124 "vmovdqu [rsp + #%d], xmm0\n\t"
1125 "vmovdqu xmm0, [rsp - #64]",
1126 src_offset, dst_offset);
1127 break;
1128 default:
1129 ShouldNotReachHere();
1130 }
1131 #endif
1132 }
1133 }
1134
1135 uint MachSpillCopyNode::implementation(CodeBuffer* cbuf,
1136 PhaseRegAlloc* ra_,
1137 bool do_size,
1138 outputStream* st) const {
1139 assert(cbuf != NULL || st != NULL, "sanity");
1140 // Get registers to move
1141 OptoReg::Name src_second = ra_->get_reg_second(in(1));
1142 OptoReg::Name src_first = ra_->get_reg_first(in(1));
1143 OptoReg::Name dst_second = ra_->get_reg_second(this);
1144 OptoReg::Name dst_first = ra_->get_reg_first(this);
1145
1146 enum RC src_second_rc = rc_class(src_second);
1147 enum RC src_first_rc = rc_class(src_first);
1148 enum RC dst_second_rc = rc_class(dst_second);
1149 enum RC dst_first_rc = rc_class(dst_first);
1150
1151 assert(OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first),
1152 "must move at least 1 register" );
1153
1154 if (src_first == dst_first && src_second == dst_second) {
1155 // Self copy, no move
1156 return 0;
1157 }
1158 if (bottom_type()->isa_vect() != NULL) {
1159 uint ireg = ideal_reg();
1160 assert((src_first_rc != rc_int && dst_first_rc != rc_int), "sanity");
1161 assert((ireg == Op_VecS || ireg == Op_VecD || ireg == Op_VecX || ireg == Op_VecY || ireg == Op_VecZ ), "sanity");
1162 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
1163 // mem -> mem
1164 int src_offset = ra_->reg2offset(src_first);
1165 int dst_offset = ra_->reg2offset(dst_first);
1166 vec_stack_to_stack_helper(cbuf, src_offset, dst_offset, ireg, st);
1167 } else if (src_first_rc == rc_float && dst_first_rc == rc_float ) {
1168 vec_mov_helper(cbuf, false, src_first, dst_first, src_second, dst_second, ireg, st);
1169 } else if (src_first_rc == rc_float && dst_first_rc == rc_stack ) {
1170 int stack_offset = ra_->reg2offset(dst_first);
1171 vec_spill_helper(cbuf, false, false, stack_offset, src_first, ireg, st);
1172 } else if (src_first_rc == rc_stack && dst_first_rc == rc_float ) {
1173 int stack_offset = ra_->reg2offset(src_first);
1174 vec_spill_helper(cbuf, false, true, stack_offset, dst_first, ireg, st);
1175 } else {
1176 ShouldNotReachHere();
1177 }
1178 return 0;
1179 }
1180 if (src_first_rc == rc_stack) {
1181 // mem ->
1182 if (dst_first_rc == rc_stack) {
1183 // mem -> mem
1184 assert(src_second != dst_first, "overlap");
1185 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1186 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1187 // 64-bit
1188 int src_offset = ra_->reg2offset(src_first);
1189 int dst_offset = ra_->reg2offset(dst_first);
1190 if (cbuf) {
1191 MacroAssembler _masm(cbuf);
1192 __ pushq(Address(rsp, src_offset));
1193 __ popq (Address(rsp, dst_offset));
1194 #ifndef PRODUCT
1195 } else {
1196 st->print("pushq [rsp + #%d]\t# 64-bit mem-mem spill\n\t"
1197 "popq [rsp + #%d]",
1198 src_offset, dst_offset);
1199 #endif
1200 }
1201 } else {
1202 // 32-bit
1203 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1204 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1205 // No pushl/popl, so:
1206 int src_offset = ra_->reg2offset(src_first);
1207 int dst_offset = ra_->reg2offset(dst_first);
1208 if (cbuf) {
1209 MacroAssembler _masm(cbuf);
1210 __ movq(Address(rsp, -8), rax);
1211 __ movl(rax, Address(rsp, src_offset));
1212 __ movl(Address(rsp, dst_offset), rax);
1213 __ movq(rax, Address(rsp, -8));
1214 #ifndef PRODUCT
1215 } else {
1216 st->print("movq [rsp - #8], rax\t# 32-bit mem-mem spill\n\t"
1217 "movl rax, [rsp + #%d]\n\t"
1218 "movl [rsp + #%d], rax\n\t"
1219 "movq rax, [rsp - #8]",
1220 src_offset, dst_offset);
1221 #endif
1222 }
1223 }
1224 return 0;
1225 } else if (dst_first_rc == rc_int) {
1226 // mem -> gpr
1227 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1228 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1229 // 64-bit
1230 int offset = ra_->reg2offset(src_first);
1231 if (cbuf) {
1232 MacroAssembler _masm(cbuf);
1233 __ movq(as_Register(Matcher::_regEncode[dst_first]), Address(rsp, offset));
1234 #ifndef PRODUCT
1235 } else {
1236 st->print("movq %s, [rsp + #%d]\t# spill",
1237 Matcher::regName[dst_first],
1238 offset);
1239 #endif
1240 }
1241 } else {
1242 // 32-bit
1243 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1244 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1245 int offset = ra_->reg2offset(src_first);
1246 if (cbuf) {
1247 MacroAssembler _masm(cbuf);
1248 __ movl(as_Register(Matcher::_regEncode[dst_first]), Address(rsp, offset));
1249 #ifndef PRODUCT
1250 } else {
1251 st->print("movl %s, [rsp + #%d]\t# spill",
1252 Matcher::regName[dst_first],
1253 offset);
1254 #endif
1255 }
1256 }
1257 return 0;
1258 } else if (dst_first_rc == rc_float) {
1259 // mem-> xmm
1260 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1261 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1262 // 64-bit
1263 int offset = ra_->reg2offset(src_first);
1264 if (cbuf) {
1265 MacroAssembler _masm(cbuf);
1266 __ movdbl( as_XMMRegister(Matcher::_regEncode[dst_first]), Address(rsp, offset));
1267 #ifndef PRODUCT
1268 } else {
1269 st->print("%s %s, [rsp + #%d]\t# spill",
1270 UseXmmLoadAndClearUpper ? "movsd " : "movlpd",
1271 Matcher::regName[dst_first],
1272 offset);
1273 #endif
1274 }
1275 } else {
1276 // 32-bit
1277 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1278 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1279 int offset = ra_->reg2offset(src_first);
1280 if (cbuf) {
1281 MacroAssembler _masm(cbuf);
1282 __ movflt( as_XMMRegister(Matcher::_regEncode[dst_first]), Address(rsp, offset));
1283 #ifndef PRODUCT
1284 } else {
1285 st->print("movss %s, [rsp + #%d]\t# spill",
1286 Matcher::regName[dst_first],
1287 offset);
1288 #endif
1289 }
1290 }
1291 return 0;
1292 }
1293 } else if (src_first_rc == rc_int) {
1294 // gpr ->
1295 if (dst_first_rc == rc_stack) {
1296 // gpr -> mem
1297 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1298 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1299 // 64-bit
1300 int offset = ra_->reg2offset(dst_first);
1301 if (cbuf) {
1302 MacroAssembler _masm(cbuf);
1303 __ movq(Address(rsp, offset), as_Register(Matcher::_regEncode[src_first]));
1304 #ifndef PRODUCT
1305 } else {
1306 st->print("movq [rsp + #%d], %s\t# spill",
1307 offset,
1308 Matcher::regName[src_first]);
1309 #endif
1310 }
1311 } else {
1312 // 32-bit
1313 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1314 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1315 int offset = ra_->reg2offset(dst_first);
1316 if (cbuf) {
1317 MacroAssembler _masm(cbuf);
1318 __ movl(Address(rsp, offset), as_Register(Matcher::_regEncode[src_first]));
1319 #ifndef PRODUCT
1320 } else {
1321 st->print("movl [rsp + #%d], %s\t# spill",
1322 offset,
1323 Matcher::regName[src_first]);
1324 #endif
1325 }
1326 }
1327 return 0;
1328 } else if (dst_first_rc == rc_int) {
1329 // gpr -> gpr
1330 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1331 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1332 // 64-bit
1333 if (cbuf) {
1334 MacroAssembler _masm(cbuf);
1335 __ movq(as_Register(Matcher::_regEncode[dst_first]),
1336 as_Register(Matcher::_regEncode[src_first]));
1337 #ifndef PRODUCT
1338 } else {
1339 st->print("movq %s, %s\t# spill",
1340 Matcher::regName[dst_first],
1341 Matcher::regName[src_first]);
1342 #endif
1343 }
1344 return 0;
1345 } else {
1346 // 32-bit
1347 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1348 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1349 if (cbuf) {
1350 MacroAssembler _masm(cbuf);
1351 __ movl(as_Register(Matcher::_regEncode[dst_first]),
1352 as_Register(Matcher::_regEncode[src_first]));
1353 #ifndef PRODUCT
1354 } else {
1355 st->print("movl %s, %s\t# spill",
1356 Matcher::regName[dst_first],
1357 Matcher::regName[src_first]);
1358 #endif
1359 }
1360 return 0;
1361 }
1362 } else if (dst_first_rc == rc_float) {
1363 // gpr -> xmm
1364 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1365 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1366 // 64-bit
1367 if (cbuf) {
1368 MacroAssembler _masm(cbuf);
1369 __ movdq( as_XMMRegister(Matcher::_regEncode[dst_first]), as_Register(Matcher::_regEncode[src_first]));
1370 #ifndef PRODUCT
1371 } else {
1372 st->print("movdq %s, %s\t# spill",
1373 Matcher::regName[dst_first],
1374 Matcher::regName[src_first]);
1375 #endif
1376 }
1377 } else {
1378 // 32-bit
1379 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1380 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1381 if (cbuf) {
1382 MacroAssembler _masm(cbuf);
1383 __ movdl( as_XMMRegister(Matcher::_regEncode[dst_first]), as_Register(Matcher::_regEncode[src_first]));
1384 #ifndef PRODUCT
1385 } else {
1386 st->print("movdl %s, %s\t# spill",
1387 Matcher::regName[dst_first],
1388 Matcher::regName[src_first]);
1389 #endif
1390 }
1391 }
1392 return 0;
1393 }
1394 } else if (src_first_rc == rc_float) {
1395 // xmm ->
1396 if (dst_first_rc == rc_stack) {
1397 // xmm -> mem
1398 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1399 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1400 // 64-bit
1401 int offset = ra_->reg2offset(dst_first);
1402 if (cbuf) {
1403 MacroAssembler _masm(cbuf);
1404 __ movdbl( Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[src_first]));
1405 #ifndef PRODUCT
1406 } else {
1407 st->print("movsd [rsp + #%d], %s\t# spill",
1408 offset,
1409 Matcher::regName[src_first]);
1410 #endif
1411 }
1412 } else {
1413 // 32-bit
1414 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1415 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1416 int offset = ra_->reg2offset(dst_first);
1417 if (cbuf) {
1418 MacroAssembler _masm(cbuf);
1419 __ movflt(Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[src_first]));
1420 #ifndef PRODUCT
1421 } else {
1422 st->print("movss [rsp + #%d], %s\t# spill",
1423 offset,
1424 Matcher::regName[src_first]);
1425 #endif
1426 }
1427 }
1428 return 0;
1429 } else if (dst_first_rc == rc_int) {
1430 // xmm -> gpr
1431 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1432 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1433 // 64-bit
1434 if (cbuf) {
1435 MacroAssembler _masm(cbuf);
1436 __ movdq( as_Register(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
1437 #ifndef PRODUCT
1438 } else {
1439 st->print("movdq %s, %s\t# spill",
1440 Matcher::regName[dst_first],
1441 Matcher::regName[src_first]);
1442 #endif
1443 }
1444 } else {
1445 // 32-bit
1446 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1447 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1448 if (cbuf) {
1449 MacroAssembler _masm(cbuf);
1450 __ movdl( as_Register(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
1451 #ifndef PRODUCT
1452 } else {
1453 st->print("movdl %s, %s\t# spill",
1454 Matcher::regName[dst_first],
1455 Matcher::regName[src_first]);
1456 #endif
1457 }
1458 }
1459 return 0;
1460 } else if (dst_first_rc == rc_float) {
1461 // xmm -> xmm
1462 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1463 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1464 // 64-bit
1465 if (cbuf) {
1466 MacroAssembler _masm(cbuf);
1467 __ movdbl( as_XMMRegister(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
1468 #ifndef PRODUCT
1469 } else {
1470 st->print("%s %s, %s\t# spill",
1471 UseXmmRegToRegMoveAll ? "movapd" : "movsd ",
1472 Matcher::regName[dst_first],
1473 Matcher::regName[src_first]);
1474 #endif
1475 }
1476 } else {
1477 // 32-bit
1478 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1479 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1480 if (cbuf) {
1481 MacroAssembler _masm(cbuf);
1482 __ movflt( as_XMMRegister(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
1483 #ifndef PRODUCT
1484 } else {
1485 st->print("%s %s, %s\t# spill",
1486 UseXmmRegToRegMoveAll ? "movaps" : "movss ",
1487 Matcher::regName[dst_first],
1488 Matcher::regName[src_first]);
1489 #endif
1490 }
1491 }
1492 return 0;
1493 }
1494 }
1495
1496 assert(0," foo ");
1497 Unimplemented();
1498 return 0;
1499 }
1500
1501 #ifndef PRODUCT
1502 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream* st) const {
1503 implementation(NULL, ra_, false, st);
1504 }
1505 #endif
1506
1507 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1508 implementation(&cbuf, ra_, false, NULL);
1509 }
1510
1511 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1512 return MachNode::size(ra_);
1513 }
1514
1515 //=============================================================================
1516 #ifndef PRODUCT
1517 void BoxLockNode::format(PhaseRegAlloc* ra_, outputStream* st) const
1518 {
1519 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1520 int reg = ra_->get_reg_first(this);
1521 st->print("leaq %s, [rsp + #%d]\t# box lock",
1522 Matcher::regName[reg], offset);
1523 }
1524 #endif
1525
1526 void BoxLockNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
1527 {
1528 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1529 int reg = ra_->get_encode(this);
1530 if (offset >= 0x80) {
1531 emit_opcode(cbuf, reg < 8 ? Assembler::REX_W : Assembler::REX_WR);
1532 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1533 emit_rm(cbuf, 0x2, reg & 7, 0x04);
1534 emit_rm(cbuf, 0x0, 0x04, RSP_enc);
1535 emit_d32(cbuf, offset);
1536 } else {
1537 emit_opcode(cbuf, reg < 8 ? Assembler::REX_W : Assembler::REX_WR);
1538 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1539 emit_rm(cbuf, 0x1, reg & 7, 0x04);
1540 emit_rm(cbuf, 0x0, 0x04, RSP_enc);
1541 emit_d8(cbuf, offset);
1542 }
1543 }
1544
1545 uint BoxLockNode::size(PhaseRegAlloc *ra_) const
1546 {
1547 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1548 return (offset < 0x80) ? 5 : 8; // REX
1549 }
1550
1551 //=============================================================================
1552 #ifndef PRODUCT
1553 void MachUEPNode::format(PhaseRegAlloc* ra_, outputStream* st) const
1554 {
1555 if (UseCompressedClassPointers) {
1556 st->print_cr("movl rscratch1, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t# compressed klass");
1557 st->print_cr("\tdecode_klass_not_null rscratch1, rscratch1");
1558 st->print_cr("\tcmpq rax, rscratch1\t # Inline cache check");
1559 } else {
1560 st->print_cr("\tcmpq rax, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t"
1561 "# Inline cache check");
1562 }
1563 st->print_cr("\tjne SharedRuntime::_ic_miss_stub");
1564 st->print_cr("\tnop\t# nops to align entry point");
1565 }
1566 #endif
1567
1568 void MachUEPNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
1569 {
1570 MacroAssembler masm(&cbuf);
1571 uint insts_size = cbuf.insts_size();
1572 if (UseCompressedClassPointers) {
1573 masm.load_klass(rscratch1, j_rarg0);
1574 masm.cmpptr(rax, rscratch1);
1575 } else {
1576 masm.cmpptr(rax, Address(j_rarg0, oopDesc::klass_offset_in_bytes()));
1577 }
1578
1579 masm.jump_cc(Assembler::notEqual, RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
1580
1581 /* WARNING these NOPs are critical so that verified entry point is properly
1582 4 bytes aligned for patching by NativeJump::patch_verified_entry() */
1583 int nops_cnt = 4 - ((cbuf.insts_size() - insts_size) & 0x3);
1584 if (OptoBreakpoint) {
1585 // Leave space for int3
1586 nops_cnt -= 1;
1587 }
1588 nops_cnt &= 0x3; // Do not add nops if code is aligned.
1589 if (nops_cnt > 0)
1590 masm.nop(nops_cnt);
1591 }
1592
1593 uint MachUEPNode::size(PhaseRegAlloc* ra_) const
1594 {
1595 return MachNode::size(ra_); // too many variables; just compute it
1596 // the hard way
1597 }
1598
1599
1600 //=============================================================================
1601
1602 int Matcher::regnum_to_fpu_offset(int regnum)
1603 {
1604 return regnum - 32; // The FP registers are in the second chunk
1605 }
1606
1607 // This is UltraSparc specific, true just means we have fast l2f conversion
1608 const bool Matcher::convL2FSupported(void) {
1609 return true;
1610 }
1611
1612 // Is this branch offset short enough that a short branch can be used?
1613 //
1614 // NOTE: If the platform does not provide any short branch variants, then
1615 // this method should return false for offset 0.
1616 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
1617 // The passed offset is relative to address of the branch.
1618 // On 86 a branch displacement is calculated relative to address
1619 // of a next instruction.
1620 offset -= br_size;
1621
1622 // the short version of jmpConUCF2 contains multiple branches,
1623 // making the reach slightly less
1624 if (rule == jmpConUCF2_rule)
1625 return (-126 <= offset && offset <= 125);
1626 return (-128 <= offset && offset <= 127);
1627 }
1628
1629 const bool Matcher::isSimpleConstant64(jlong value) {
1630 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
1631 //return value == (int) value; // Cf. storeImmL and immL32.
1632
1633 // Probably always true, even if a temp register is required.
1634 return true;
1635 }
1636
1637 // The ecx parameter to rep stosq for the ClearArray node is in words.
1638 const bool Matcher::init_array_count_is_in_bytes = false;
1639
1640 // No additional cost for CMOVL.
1641 const int Matcher::long_cmove_cost() { return 0; }
1642
1643 // No CMOVF/CMOVD with SSE2
1644 const int Matcher::float_cmove_cost() { return ConditionalMoveLimit; }
1645
1646 // Does the CPU require late expand (see block.cpp for description of late expand)?
1647 const bool Matcher::require_postalloc_expand = false;
1648
1649 // Do we need to mask the count passed to shift instructions or does
1650 // the cpu only look at the lower 5/6 bits anyway?
1651 const bool Matcher::need_masked_shift_count = false;
1652
1653 bool Matcher::narrow_oop_use_complex_address() {
1654 assert(UseCompressedOops, "only for compressed oops code");
1655 return (LogMinObjAlignmentInBytes <= 3);
1656 }
1657
1658 bool Matcher::narrow_klass_use_complex_address() {
1659 assert(UseCompressedClassPointers, "only for compressed klass code");
1660 return (LogKlassAlignmentInBytes <= 3);
1661 }
1662
1663 bool Matcher::const_oop_prefer_decode() {
1664 // Prefer ConN+DecodeN over ConP.
1665 return true;
1666 }
1667
1668 bool Matcher::const_klass_prefer_decode() {
1669 // TODO: Either support matching DecodeNKlass (heap-based) in operand
1670 // or condisider the following:
1671 // Prefer ConNKlass+DecodeNKlass over ConP in simple compressed klass mode.
1672 //return Universe::narrow_klass_base() == NULL;
1673 return true;
1674 }
1675
1676 // Is it better to copy float constants, or load them directly from
1677 // memory? Intel can load a float constant from a direct address,
1678 // requiring no extra registers. Most RISCs will have to materialize
1679 // an address into a register first, so they would do better to copy
1680 // the constant from stack.
1681 const bool Matcher::rematerialize_float_constants = true; // XXX
1682
1683 // If CPU can load and store mis-aligned doubles directly then no
1684 // fixup is needed. Else we split the double into 2 integer pieces
1685 // and move it piece-by-piece. Only happens when passing doubles into
1686 // C code as the Java calling convention forces doubles to be aligned.
1687 const bool Matcher::misaligned_doubles_ok = true;
1688
1689 // No-op on amd64
1690 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {}
1691
1692 // Advertise here if the CPU requires explicit rounding operations to
1693 // implement the UseStrictFP mode.
1694 const bool Matcher::strict_fp_requires_explicit_rounding = true;
1695
1696 // Are floats conerted to double when stored to stack during deoptimization?
1697 // On x64 it is stored without convertion so we can use normal access.
1698 bool Matcher::float_in_double() { return false; }
1699
1700 // Do ints take an entire long register or just half?
1701 const bool Matcher::int_in_long = true;
1702
1703 // Return whether or not this register is ever used as an argument.
1704 // This function is used on startup to build the trampoline stubs in
1705 // generateOptoStub. Registers not mentioned will be killed by the VM
1706 // call in the trampoline, and arguments in those registers not be
1707 // available to the callee.
1708 bool Matcher::can_be_java_arg(int reg)
1709 {
1710 return
1711 reg == RDI_num || reg == RDI_H_num ||
1712 reg == RSI_num || reg == RSI_H_num ||
1713 reg == RDX_num || reg == RDX_H_num ||
1714 reg == RCX_num || reg == RCX_H_num ||
1715 reg == R8_num || reg == R8_H_num ||
1716 reg == R9_num || reg == R9_H_num ||
1717 reg == R12_num || reg == R12_H_num ||
1718 reg == XMM0_num || reg == XMM0b_num ||
1719 reg == XMM1_num || reg == XMM1b_num ||
1720 reg == XMM2_num || reg == XMM2b_num ||
1721 reg == XMM3_num || reg == XMM3b_num ||
1722 reg == XMM4_num || reg == XMM4b_num ||
1723 reg == XMM5_num || reg == XMM5b_num ||
1724 reg == XMM6_num || reg == XMM6b_num ||
1725 reg == XMM7_num || reg == XMM7b_num;
1726 }
1727
1728 bool Matcher::is_spillable_arg(int reg)
1729 {
1730 return can_be_java_arg(reg);
1731 }
1732
1733 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) {
1734 // In 64 bit mode a code which use multiply when
1735 // devisor is constant is faster than hardware
1736 // DIV instruction (it uses MulHiL).
1737 return false;
1738 }
1739
1740 // Register for DIVI projection of divmodI
1741 RegMask Matcher::divI_proj_mask() {
1742 return INT_RAX_REG_mask();
1743 }
1744
1745 // Register for MODI projection of divmodI
1746 RegMask Matcher::modI_proj_mask() {
1747 return INT_RDX_REG_mask();
1748 }
1749
1750 // Register for DIVL projection of divmodL
1751 RegMask Matcher::divL_proj_mask() {
1752 return LONG_RAX_REG_mask();
1753 }
1754
1755 // Register for MODL projection of divmodL
1756 RegMask Matcher::modL_proj_mask() {
1757 return LONG_RDX_REG_mask();
1758 }
1759
1760 // Register for saving SP into on method handle invokes. Not used on x86_64.
1761 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
1762 return NO_REG_mask();
1763 }
1764
1765 %}
1766
1767 //----------ENCODING BLOCK-----------------------------------------------------
1768 // This block specifies the encoding classes used by the compiler to
1769 // output byte streams. Encoding classes are parameterized macros
1770 // used by Machine Instruction Nodes in order to generate the bit
1771 // encoding of the instruction. Operands specify their base encoding
1772 // interface with the interface keyword. There are currently
1773 // supported four interfaces, REG_INTER, CONST_INTER, MEMORY_INTER, &
1774 // COND_INTER. REG_INTER causes an operand to generate a function
1775 // which returns its register number when queried. CONST_INTER causes
1776 // an operand to generate a function which returns the value of the
1777 // constant when queried. MEMORY_INTER causes an operand to generate
1778 // four functions which return the Base Register, the Index Register,
1779 // the Scale Value, and the Offset Value of the operand when queried.
1780 // COND_INTER causes an operand to generate six functions which return
1781 // the encoding code (ie - encoding bits for the instruction)
1782 // associated with each basic boolean condition for a conditional
1783 // instruction.
1784 //
1785 // Instructions specify two basic values for encoding. Again, a
1786 // function is available to check if the constant displacement is an
1787 // oop. They use the ins_encode keyword to specify their encoding
1788 // classes (which must be a sequence of enc_class names, and their
1789 // parameters, specified in the encoding block), and they use the
1790 // opcode keyword to specify, in order, their primary, secondary, and
1791 // tertiary opcode. Only the opcode sections which a particular
1792 // instruction needs for encoding need to be specified.
1793 encode %{
1794 // Build emit functions for each basic byte or larger field in the
1795 // intel encoding scheme (opcode, rm, sib, immediate), and call them
1796 // from C++ code in the enc_class source block. Emit functions will
1797 // live in the main source block for now. In future, we can
1798 // generalize this by adding a syntax that specifies the sizes of
1799 // fields in an order, so that the adlc can build the emit functions
1800 // automagically
1801
1802 // Emit primary opcode
1803 enc_class OpcP
1804 %{
1805 emit_opcode(cbuf, $primary);
1806 %}
1807
1808 // Emit secondary opcode
1809 enc_class OpcS
1810 %{
1811 emit_opcode(cbuf, $secondary);
1812 %}
1813
1814 // Emit tertiary opcode
1815 enc_class OpcT
1816 %{
1817 emit_opcode(cbuf, $tertiary);
1818 %}
1819
1820 // Emit opcode directly
1821 enc_class Opcode(immI d8)
1822 %{
1823 emit_opcode(cbuf, $d8$$constant);
1824 %}
1825
1826 // Emit size prefix
1827 enc_class SizePrefix
1828 %{
1829 emit_opcode(cbuf, 0x66);
1830 %}
1831
1832 enc_class reg(rRegI reg)
1833 %{
1834 emit_rm(cbuf, 0x3, 0, $reg$$reg & 7);
1835 %}
1836
1837 enc_class reg_reg(rRegI dst, rRegI src)
1838 %{
1839 emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7);
1840 %}
1841
1842 enc_class opc_reg_reg(immI opcode, rRegI dst, rRegI src)
1843 %{
1844 emit_opcode(cbuf, $opcode$$constant);
1845 emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7);
1846 %}
1847
1848 enc_class cdql_enc(no_rax_rdx_RegI div)
1849 %{
1850 // Full implementation of Java idiv and irem; checks for
1851 // special case as described in JVM spec., p.243 & p.271.
1852 //
1853 // normal case special case
1854 //
1855 // input : rax: dividend min_int
1856 // reg: divisor -1
1857 //
1858 // output: rax: quotient (= rax idiv reg) min_int
1859 // rdx: remainder (= rax irem reg) 0
1860 //
1861 // Code sequnce:
1862 //
1863 // 0: 3d 00 00 00 80 cmp $0x80000000,%eax
1864 // 5: 75 07/08 jne e <normal>
1865 // 7: 33 d2 xor %edx,%edx
1866 // [div >= 8 -> offset + 1]
1867 // [REX_B]
1868 // 9: 83 f9 ff cmp $0xffffffffffffffff,$div
1869 // c: 74 03/04 je 11 <done>
1870 // 000000000000000e <normal>:
1871 // e: 99 cltd
1872 // [div >= 8 -> offset + 1]
1873 // [REX_B]
1874 // f: f7 f9 idiv $div
1875 // 0000000000000011 <done>:
1876
1877 // cmp $0x80000000,%eax
1878 emit_opcode(cbuf, 0x3d);
1879 emit_d8(cbuf, 0x00);
1880 emit_d8(cbuf, 0x00);
1881 emit_d8(cbuf, 0x00);
1882 emit_d8(cbuf, 0x80);
1883
1884 // jne e <normal>
1885 emit_opcode(cbuf, 0x75);
1886 emit_d8(cbuf, $div$$reg < 8 ? 0x07 : 0x08);
1887
1888 // xor %edx,%edx
1889 emit_opcode(cbuf, 0x33);
1890 emit_d8(cbuf, 0xD2);
1891
1892 // cmp $0xffffffffffffffff,%ecx
1893 if ($div$$reg >= 8) {
1894 emit_opcode(cbuf, Assembler::REX_B);
1895 }
1896 emit_opcode(cbuf, 0x83);
1897 emit_rm(cbuf, 0x3, 0x7, $div$$reg & 7);
1898 emit_d8(cbuf, 0xFF);
1899
1900 // je 11 <done>
1901 emit_opcode(cbuf, 0x74);
1902 emit_d8(cbuf, $div$$reg < 8 ? 0x03 : 0x04);
1903
1904 // <normal>
1905 // cltd
1906 emit_opcode(cbuf, 0x99);
1907
1908 // idivl (note: must be emitted by the user of this rule)
1909 // <done>
1910 %}
1911
1912 enc_class cdqq_enc(no_rax_rdx_RegL div)
1913 %{
1914 // Full implementation of Java ldiv and lrem; checks for
1915 // special case as described in JVM spec., p.243 & p.271.
1916 //
1917 // normal case special case
1918 //
1919 // input : rax: dividend min_long
1920 // reg: divisor -1
1921 //
1922 // output: rax: quotient (= rax idiv reg) min_long
1923 // rdx: remainder (= rax irem reg) 0
1924 //
1925 // Code sequnce:
1926 //
1927 // 0: 48 ba 00 00 00 00 00 mov $0x8000000000000000,%rdx
1928 // 7: 00 00 80
1929 // a: 48 39 d0 cmp %rdx,%rax
1930 // d: 75 08 jne 17 <normal>
1931 // f: 33 d2 xor %edx,%edx
1932 // 11: 48 83 f9 ff cmp $0xffffffffffffffff,$div
1933 // 15: 74 05 je 1c <done>
1934 // 0000000000000017 <normal>:
1935 // 17: 48 99 cqto
1936 // 19: 48 f7 f9 idiv $div
1937 // 000000000000001c <done>:
1938
1939 // mov $0x8000000000000000,%rdx
1940 emit_opcode(cbuf, Assembler::REX_W);
1941 emit_opcode(cbuf, 0xBA);
1942 emit_d8(cbuf, 0x00);
1943 emit_d8(cbuf, 0x00);
1944 emit_d8(cbuf, 0x00);
1945 emit_d8(cbuf, 0x00);
1946 emit_d8(cbuf, 0x00);
1947 emit_d8(cbuf, 0x00);
1948 emit_d8(cbuf, 0x00);
1949 emit_d8(cbuf, 0x80);
1950
1951 // cmp %rdx,%rax
1952 emit_opcode(cbuf, Assembler::REX_W);
1953 emit_opcode(cbuf, 0x39);
1954 emit_d8(cbuf, 0xD0);
1955
1956 // jne 17 <normal>
1957 emit_opcode(cbuf, 0x75);
1958 emit_d8(cbuf, 0x08);
1959
1960 // xor %edx,%edx
1961 emit_opcode(cbuf, 0x33);
1962 emit_d8(cbuf, 0xD2);
1963
1964 // cmp $0xffffffffffffffff,$div
1965 emit_opcode(cbuf, $div$$reg < 8 ? Assembler::REX_W : Assembler::REX_WB);
1966 emit_opcode(cbuf, 0x83);
1967 emit_rm(cbuf, 0x3, 0x7, $div$$reg & 7);
1968 emit_d8(cbuf, 0xFF);
1969
1970 // je 1e <done>
1971 emit_opcode(cbuf, 0x74);
1972 emit_d8(cbuf, 0x05);
1973
1974 // <normal>
1975 // cqto
1976 emit_opcode(cbuf, Assembler::REX_W);
1977 emit_opcode(cbuf, 0x99);
1978
1979 // idivq (note: must be emitted by the user of this rule)
1980 // <done>
1981 %}
1982
1983 // Opcde enc_class for 8/32 bit immediate instructions with sign-extension
1984 enc_class OpcSE(immI imm)
1985 %{
1986 // Emit primary opcode and set sign-extend bit
1987 // Check for 8-bit immediate, and set sign extend bit in opcode
1988 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
1989 emit_opcode(cbuf, $primary | 0x02);
1990 } else {
1991 // 32-bit immediate
1992 emit_opcode(cbuf, $primary);
1993 }
1994 %}
1995
1996 enc_class OpcSErm(rRegI dst, immI imm)
1997 %{
1998 // OpcSEr/m
1999 int dstenc = $dst$$reg;
2000 if (dstenc >= 8) {
2001 emit_opcode(cbuf, Assembler::REX_B);
2002 dstenc -= 8;
2003 }
2004 // Emit primary opcode and set sign-extend bit
2005 // Check for 8-bit immediate, and set sign extend bit in opcode
2006 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
2007 emit_opcode(cbuf, $primary | 0x02);
2008 } else {
2009 // 32-bit immediate
2010 emit_opcode(cbuf, $primary);
2011 }
2012 // Emit r/m byte with secondary opcode, after primary opcode.
2013 emit_rm(cbuf, 0x3, $secondary, dstenc);
2014 %}
2015
2016 enc_class OpcSErm_wide(rRegL dst, immI imm)
2017 %{
2018 // OpcSEr/m
2019 int dstenc = $dst$$reg;
2020 if (dstenc < 8) {
2021 emit_opcode(cbuf, Assembler::REX_W);
2022 } else {
2023 emit_opcode(cbuf, Assembler::REX_WB);
2024 dstenc -= 8;
2025 }
2026 // Emit primary opcode and set sign-extend bit
2027 // Check for 8-bit immediate, and set sign extend bit in opcode
2028 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
2029 emit_opcode(cbuf, $primary | 0x02);
2030 } else {
2031 // 32-bit immediate
2032 emit_opcode(cbuf, $primary);
2033 }
2034 // Emit r/m byte with secondary opcode, after primary opcode.
2035 emit_rm(cbuf, 0x3, $secondary, dstenc);
2036 %}
2037
2038 enc_class Con8or32(immI imm)
2039 %{
2040 // Check for 8-bit immediate, and set sign extend bit in opcode
2041 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
2042 $$$emit8$imm$$constant;
2043 } else {
2044 // 32-bit immediate
2045 $$$emit32$imm$$constant;
2046 }
2047 %}
2048
2049 enc_class opc2_reg(rRegI dst)
2050 %{
2051 // BSWAP
2052 emit_cc(cbuf, $secondary, $dst$$reg);
2053 %}
2054
2055 enc_class opc3_reg(rRegI dst)
2056 %{
2057 // BSWAP
2058 emit_cc(cbuf, $tertiary, $dst$$reg);
2059 %}
2060
2061 enc_class reg_opc(rRegI div)
2062 %{
2063 // INC, DEC, IDIV, IMOD, JMP indirect, ...
2064 emit_rm(cbuf, 0x3, $secondary, $div$$reg & 7);
2065 %}
2066
2067 enc_class enc_cmov(cmpOp cop)
2068 %{
2069 // CMOV
2070 $$$emit8$primary;
2071 emit_cc(cbuf, $secondary, $cop$$cmpcode);
2072 %}
2073
2074 enc_class enc_PartialSubtypeCheck()
2075 %{
2076 Register Rrdi = as_Register(RDI_enc); // result register
2077 Register Rrax = as_Register(RAX_enc); // super class
2078 Register Rrcx = as_Register(RCX_enc); // killed
2079 Register Rrsi = as_Register(RSI_enc); // sub class
2080 Label miss;
2081 const bool set_cond_codes = true;
2082
2083 MacroAssembler _masm(&cbuf);
2084 __ check_klass_subtype_slow_path(Rrsi, Rrax, Rrcx, Rrdi,
2085 NULL, &miss,
2086 /*set_cond_codes:*/ true);
2087 if ($primary) {
2088 __ xorptr(Rrdi, Rrdi);
2089 }
2090 __ bind(miss);
2091 %}
2092
2093 enc_class clear_avx %{
2094 debug_only(int off0 = cbuf.insts_size());
2095 if (ra_->C->max_vector_size() > 16) {
2096 // Clear upper bits of YMM registers when current compiled code uses
2097 // wide vectors to avoid AVX <-> SSE transition penalty during call.
2098 MacroAssembler _masm(&cbuf);
2099 __ vzeroupper();
2100 }
2101 debug_only(int off1 = cbuf.insts_size());
2102 assert(off1 - off0 == clear_avx_size(), "correct size prediction");
2103 %}
2104
2105 enc_class Java_To_Runtime(method meth) %{
2106 // No relocation needed
2107 MacroAssembler _masm(&cbuf);
2108 __ mov64(r10, (int64_t) $meth$$method);
2109 __ call(r10);
2110 %}
2111
2112 enc_class Java_To_Interpreter(method meth)
2113 %{
2114 // CALL Java_To_Interpreter
2115 // This is the instruction starting address for relocation info.
2116 cbuf.set_insts_mark();
2117 $$$emit8$primary;
2118 // CALL directly to the runtime
2119 emit_d32_reloc(cbuf,
2120 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
2121 runtime_call_Relocation::spec(),
2122 RELOC_DISP32);
2123 %}
2124
2125 enc_class Java_Static_Call(method meth)
2126 %{
2127 // JAVA STATIC CALL
2128 // CALL to fixup routine. Fixup routine uses ScopeDesc info to
2129 // determine who we intended to call.
2130 cbuf.set_insts_mark();
2131 $$$emit8$primary;
2132
2133 if (!_method) {
2134 emit_d32_reloc(cbuf, (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
2135 runtime_call_Relocation::spec(),
2136 RELOC_DISP32);
2137 } else {
2138 int method_index = resolved_method_index(cbuf);
2139 RelocationHolder rspec = _optimized_virtual ? opt_virtual_call_Relocation::spec(method_index)
2140 : static_call_Relocation::spec(method_index);
2141 emit_d32_reloc(cbuf, (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
2142 rspec, RELOC_DISP32);
2143 // Emit stubs for static call.
2144 address mark = cbuf.insts_mark();
2145 address stub = CompiledStaticCall::emit_to_interp_stub(cbuf, mark);
2146 if (stub == NULL) {
2147 ciEnv::current()->record_failure("CodeCache is full");
2148 return;
2149 }
2150 #if INCLUDE_AOT
2151 CompiledStaticCall::emit_to_aot_stub(cbuf, mark);
2152 #endif
2153 }
2154 %}
2155
2156 enc_class Java_Dynamic_Call(method meth) %{
2157 MacroAssembler _masm(&cbuf);
2158 __ ic_call((address)$meth$$method, resolved_method_index(cbuf));
2159 %}
2160
2161 enc_class Java_Compiled_Call(method meth)
2162 %{
2163 // JAVA COMPILED CALL
2164 int disp = in_bytes(Method:: from_compiled_offset());
2165
2166 // XXX XXX offset is 128 is 1.5 NON-PRODUCT !!!
2167 // assert(-0x80 <= disp && disp < 0x80, "compiled_code_offset isn't small");
2168
2169 // callq *disp(%rax)
2170 cbuf.set_insts_mark();
2171 $$$emit8$primary;
2172 if (disp < 0x80) {
2173 emit_rm(cbuf, 0x01, $secondary, RAX_enc); // R/M byte
2174 emit_d8(cbuf, disp); // Displacement
2175 } else {
2176 emit_rm(cbuf, 0x02, $secondary, RAX_enc); // R/M byte
2177 emit_d32(cbuf, disp); // Displacement
2178 }
2179 %}
2180
2181 enc_class reg_opc_imm(rRegI dst, immI8 shift)
2182 %{
2183 // SAL, SAR, SHR
2184 int dstenc = $dst$$reg;
2185 if (dstenc >= 8) {
2186 emit_opcode(cbuf, Assembler::REX_B);
2187 dstenc -= 8;
2188 }
2189 $$$emit8$primary;
2190 emit_rm(cbuf, 0x3, $secondary, dstenc);
2191 $$$emit8$shift$$constant;
2192 %}
2193
2194 enc_class reg_opc_imm_wide(rRegL dst, immI8 shift)
2195 %{
2196 // SAL, SAR, SHR
2197 int dstenc = $dst$$reg;
2198 if (dstenc < 8) {
2199 emit_opcode(cbuf, Assembler::REX_W);
2200 } else {
2201 emit_opcode(cbuf, Assembler::REX_WB);
2202 dstenc -= 8;
2203 }
2204 $$$emit8$primary;
2205 emit_rm(cbuf, 0x3, $secondary, dstenc);
2206 $$$emit8$shift$$constant;
2207 %}
2208
2209 enc_class load_immI(rRegI dst, immI src)
2210 %{
2211 int dstenc = $dst$$reg;
2212 if (dstenc >= 8) {
2213 emit_opcode(cbuf, Assembler::REX_B);
2214 dstenc -= 8;
2215 }
2216 emit_opcode(cbuf, 0xB8 | dstenc);
2217 $$$emit32$src$$constant;
2218 %}
2219
2220 enc_class load_immL(rRegL dst, immL src)
2221 %{
2222 int dstenc = $dst$$reg;
2223 if (dstenc < 8) {
2224 emit_opcode(cbuf, Assembler::REX_W);
2225 } else {
2226 emit_opcode(cbuf, Assembler::REX_WB);
2227 dstenc -= 8;
2228 }
2229 emit_opcode(cbuf, 0xB8 | dstenc);
2230 emit_d64(cbuf, $src$$constant);
2231 %}
2232
2233 enc_class load_immUL32(rRegL dst, immUL32 src)
2234 %{
2235 // same as load_immI, but this time we care about zeroes in the high word
2236 int dstenc = $dst$$reg;
2237 if (dstenc >= 8) {
2238 emit_opcode(cbuf, Assembler::REX_B);
2239 dstenc -= 8;
2240 }
2241 emit_opcode(cbuf, 0xB8 | dstenc);
2242 $$$emit32$src$$constant;
2243 %}
2244
2245 enc_class load_immL32(rRegL dst, immL32 src)
2246 %{
2247 int dstenc = $dst$$reg;
2248 if (dstenc < 8) {
2249 emit_opcode(cbuf, Assembler::REX_W);
2250 } else {
2251 emit_opcode(cbuf, Assembler::REX_WB);
2252 dstenc -= 8;
2253 }
2254 emit_opcode(cbuf, 0xC7);
2255 emit_rm(cbuf, 0x03, 0x00, dstenc);
2256 $$$emit32$src$$constant;
2257 %}
2258
2259 enc_class load_immP31(rRegP dst, immP32 src)
2260 %{
2261 // same as load_immI, but this time we care about zeroes in the high word
2262 int dstenc = $dst$$reg;
2263 if (dstenc >= 8) {
2264 emit_opcode(cbuf, Assembler::REX_B);
2265 dstenc -= 8;
2266 }
2267 emit_opcode(cbuf, 0xB8 | dstenc);
2268 $$$emit32$src$$constant;
2269 %}
2270
2271 enc_class load_immP(rRegP dst, immP src)
2272 %{
2273 int dstenc = $dst$$reg;
2274 if (dstenc < 8) {
2275 emit_opcode(cbuf, Assembler::REX_W);
2276 } else {
2277 emit_opcode(cbuf, Assembler::REX_WB);
2278 dstenc -= 8;
2279 }
2280 emit_opcode(cbuf, 0xB8 | dstenc);
2281 // This next line should be generated from ADLC
2282 if ($src->constant_reloc() != relocInfo::none) {
2283 emit_d64_reloc(cbuf, $src$$constant, $src->constant_reloc(), RELOC_IMM64);
2284 } else {
2285 emit_d64(cbuf, $src$$constant);
2286 }
2287 %}
2288
2289 enc_class Con32(immI src)
2290 %{
2291 // Output immediate
2292 $$$emit32$src$$constant;
2293 %}
2294
2295 enc_class Con32F_as_bits(immF src)
2296 %{
2297 // Output Float immediate bits
2298 jfloat jf = $src$$constant;
2299 jint jf_as_bits = jint_cast(jf);
2300 emit_d32(cbuf, jf_as_bits);
2301 %}
2302
2303 enc_class Con16(immI src)
2304 %{
2305 // Output immediate
2306 $$$emit16$src$$constant;
2307 %}
2308
2309 // How is this different from Con32??? XXX
2310 enc_class Con_d32(immI src)
2311 %{
2312 emit_d32(cbuf,$src$$constant);
2313 %}
2314
2315 enc_class conmemref (rRegP t1) %{ // Con32(storeImmI)
2316 // Output immediate memory reference
2317 emit_rm(cbuf, 0x00, $t1$$reg, 0x05 );
2318 emit_d32(cbuf, 0x00);
2319 %}
2320
2321 enc_class lock_prefix()
2322 %{
2323 if (os::is_MP()) {
2324 emit_opcode(cbuf, 0xF0); // lock
2325 }
2326 %}
2327
2328 enc_class REX_mem(memory mem)
2329 %{
2330 if ($mem$$base >= 8) {
2331 if ($mem$$index < 8) {
2332 emit_opcode(cbuf, Assembler::REX_B);
2333 } else {
2334 emit_opcode(cbuf, Assembler::REX_XB);
2335 }
2336 } else {
2337 if ($mem$$index >= 8) {
2338 emit_opcode(cbuf, Assembler::REX_X);
2339 }
2340 }
2341 %}
2342
2343 enc_class REX_mem_wide(memory mem)
2344 %{
2345 if ($mem$$base >= 8) {
2346 if ($mem$$index < 8) {
2347 emit_opcode(cbuf, Assembler::REX_WB);
2348 } else {
2349 emit_opcode(cbuf, Assembler::REX_WXB);
2350 }
2351 } else {
2352 if ($mem$$index < 8) {
2353 emit_opcode(cbuf, Assembler::REX_W);
2354 } else {
2355 emit_opcode(cbuf, Assembler::REX_WX);
2356 }
2357 }
2358 %}
2359
2360 // for byte regs
2361 enc_class REX_breg(rRegI reg)
2362 %{
2363 if ($reg$$reg >= 4) {
2364 emit_opcode(cbuf, $reg$$reg < 8 ? Assembler::REX : Assembler::REX_B);
2365 }
2366 %}
2367
2368 // for byte regs
2369 enc_class REX_reg_breg(rRegI dst, rRegI src)
2370 %{
2371 if ($dst$$reg < 8) {
2372 if ($src$$reg >= 4) {
2373 emit_opcode(cbuf, $src$$reg < 8 ? Assembler::REX : Assembler::REX_B);
2374 }
2375 } else {
2376 if ($src$$reg < 8) {
2377 emit_opcode(cbuf, Assembler::REX_R);
2378 } else {
2379 emit_opcode(cbuf, Assembler::REX_RB);
2380 }
2381 }
2382 %}
2383
2384 // for byte regs
2385 enc_class REX_breg_mem(rRegI reg, memory mem)
2386 %{
2387 if ($reg$$reg < 8) {
2388 if ($mem$$base < 8) {
2389 if ($mem$$index >= 8) {
2390 emit_opcode(cbuf, Assembler::REX_X);
2391 } else if ($reg$$reg >= 4) {
2392 emit_opcode(cbuf, Assembler::REX);
2393 }
2394 } else {
2395 if ($mem$$index < 8) {
2396 emit_opcode(cbuf, Assembler::REX_B);
2397 } else {
2398 emit_opcode(cbuf, Assembler::REX_XB);
2399 }
2400 }
2401 } else {
2402 if ($mem$$base < 8) {
2403 if ($mem$$index < 8) {
2404 emit_opcode(cbuf, Assembler::REX_R);
2405 } else {
2406 emit_opcode(cbuf, Assembler::REX_RX);
2407 }
2408 } else {
2409 if ($mem$$index < 8) {
2410 emit_opcode(cbuf, Assembler::REX_RB);
2411 } else {
2412 emit_opcode(cbuf, Assembler::REX_RXB);
2413 }
2414 }
2415 }
2416 %}
2417
2418 enc_class REX_reg(rRegI reg)
2419 %{
2420 if ($reg$$reg >= 8) {
2421 emit_opcode(cbuf, Assembler::REX_B);
2422 }
2423 %}
2424
2425 enc_class REX_reg_wide(rRegI reg)
2426 %{
2427 if ($reg$$reg < 8) {
2428 emit_opcode(cbuf, Assembler::REX_W);
2429 } else {
2430 emit_opcode(cbuf, Assembler::REX_WB);
2431 }
2432 %}
2433
2434 enc_class REX_reg_reg(rRegI dst, rRegI src)
2435 %{
2436 if ($dst$$reg < 8) {
2437 if ($src$$reg >= 8) {
2438 emit_opcode(cbuf, Assembler::REX_B);
2439 }
2440 } else {
2441 if ($src$$reg < 8) {
2442 emit_opcode(cbuf, Assembler::REX_R);
2443 } else {
2444 emit_opcode(cbuf, Assembler::REX_RB);
2445 }
2446 }
2447 %}
2448
2449 enc_class REX_reg_reg_wide(rRegI dst, rRegI src)
2450 %{
2451 if ($dst$$reg < 8) {
2452 if ($src$$reg < 8) {
2453 emit_opcode(cbuf, Assembler::REX_W);
2454 } else {
2455 emit_opcode(cbuf, Assembler::REX_WB);
2456 }
2457 } else {
2458 if ($src$$reg < 8) {
2459 emit_opcode(cbuf, Assembler::REX_WR);
2460 } else {
2461 emit_opcode(cbuf, Assembler::REX_WRB);
2462 }
2463 }
2464 %}
2465
2466 enc_class REX_reg_mem(rRegI reg, memory mem)
2467 %{
2468 if ($reg$$reg < 8) {
2469 if ($mem$$base < 8) {
2470 if ($mem$$index >= 8) {
2471 emit_opcode(cbuf, Assembler::REX_X);
2472 }
2473 } else {
2474 if ($mem$$index < 8) {
2475 emit_opcode(cbuf, Assembler::REX_B);
2476 } else {
2477 emit_opcode(cbuf, Assembler::REX_XB);
2478 }
2479 }
2480 } else {
2481 if ($mem$$base < 8) {
2482 if ($mem$$index < 8) {
2483 emit_opcode(cbuf, Assembler::REX_R);
2484 } else {
2485 emit_opcode(cbuf, Assembler::REX_RX);
2486 }
2487 } else {
2488 if ($mem$$index < 8) {
2489 emit_opcode(cbuf, Assembler::REX_RB);
2490 } else {
2491 emit_opcode(cbuf, Assembler::REX_RXB);
2492 }
2493 }
2494 }
2495 %}
2496
2497 enc_class REX_reg_mem_wide(rRegL reg, memory mem)
2498 %{
2499 if ($reg$$reg < 8) {
2500 if ($mem$$base < 8) {
2501 if ($mem$$index < 8) {
2502 emit_opcode(cbuf, Assembler::REX_W);
2503 } else {
2504 emit_opcode(cbuf, Assembler::REX_WX);
2505 }
2506 } else {
2507 if ($mem$$index < 8) {
2508 emit_opcode(cbuf, Assembler::REX_WB);
2509 } else {
2510 emit_opcode(cbuf, Assembler::REX_WXB);
2511 }
2512 }
2513 } else {
2514 if ($mem$$base < 8) {
2515 if ($mem$$index < 8) {
2516 emit_opcode(cbuf, Assembler::REX_WR);
2517 } else {
2518 emit_opcode(cbuf, Assembler::REX_WRX);
2519 }
2520 } else {
2521 if ($mem$$index < 8) {
2522 emit_opcode(cbuf, Assembler::REX_WRB);
2523 } else {
2524 emit_opcode(cbuf, Assembler::REX_WRXB);
2525 }
2526 }
2527 }
2528 %}
2529
2530 enc_class reg_mem(rRegI ereg, memory mem)
2531 %{
2532 // High registers handle in encode_RegMem
2533 int reg = $ereg$$reg;
2534 int base = $mem$$base;
2535 int index = $mem$$index;
2536 int scale = $mem$$scale;
2537 int disp = $mem$$disp;
2538 relocInfo::relocType disp_reloc = $mem->disp_reloc();
2539
2540 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
2541 %}
2542
2543 enc_class RM_opc_mem(immI rm_opcode, memory mem)
2544 %{
2545 int rm_byte_opcode = $rm_opcode$$constant;
2546
2547 // High registers handle in encode_RegMem
2548 int base = $mem$$base;
2549 int index = $mem$$index;
2550 int scale = $mem$$scale;
2551 int displace = $mem$$disp;
2552
2553 relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when
2554 // working with static
2555 // globals
2556 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace,
2557 disp_reloc);
2558 %}
2559
2560 enc_class reg_lea(rRegI dst, rRegI src0, immI src1)
2561 %{
2562 int reg_encoding = $dst$$reg;
2563 int base = $src0$$reg; // 0xFFFFFFFF indicates no base
2564 int index = 0x04; // 0x04 indicates no index
2565 int scale = 0x00; // 0x00 indicates no scale
2566 int displace = $src1$$constant; // 0x00 indicates no displacement
2567 relocInfo::relocType disp_reloc = relocInfo::none;
2568 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace,
2569 disp_reloc);
2570 %}
2571
2572 enc_class neg_reg(rRegI dst)
2573 %{
2574 int dstenc = $dst$$reg;
2575 if (dstenc >= 8) {
2576 emit_opcode(cbuf, Assembler::REX_B);
2577 dstenc -= 8;
2578 }
2579 // NEG $dst
2580 emit_opcode(cbuf, 0xF7);
2581 emit_rm(cbuf, 0x3, 0x03, dstenc);
2582 %}
2583
2584 enc_class neg_reg_wide(rRegI dst)
2585 %{
2586 int dstenc = $dst$$reg;
2587 if (dstenc < 8) {
2588 emit_opcode(cbuf, Assembler::REX_W);
2589 } else {
2590 emit_opcode(cbuf, Assembler::REX_WB);
2591 dstenc -= 8;
2592 }
2593 // NEG $dst
2594 emit_opcode(cbuf, 0xF7);
2595 emit_rm(cbuf, 0x3, 0x03, dstenc);
2596 %}
2597
2598 enc_class setLT_reg(rRegI dst)
2599 %{
2600 int dstenc = $dst$$reg;
2601 if (dstenc >= 8) {
2602 emit_opcode(cbuf, Assembler::REX_B);
2603 dstenc -= 8;
2604 } else if (dstenc >= 4) {
2605 emit_opcode(cbuf, Assembler::REX);
2606 }
2607 // SETLT $dst
2608 emit_opcode(cbuf, 0x0F);
2609 emit_opcode(cbuf, 0x9C);
2610 emit_rm(cbuf, 0x3, 0x0, dstenc);
2611 %}
2612
2613 enc_class setNZ_reg(rRegI dst)
2614 %{
2615 int dstenc = $dst$$reg;
2616 if (dstenc >= 8) {
2617 emit_opcode(cbuf, Assembler::REX_B);
2618 dstenc -= 8;
2619 } else if (dstenc >= 4) {
2620 emit_opcode(cbuf, Assembler::REX);
2621 }
2622 // SETNZ $dst
2623 emit_opcode(cbuf, 0x0F);
2624 emit_opcode(cbuf, 0x95);
2625 emit_rm(cbuf, 0x3, 0x0, dstenc);
2626 %}
2627
2628
2629 // Compare the lonogs and set -1, 0, or 1 into dst
2630 enc_class cmpl3_flag(rRegL src1, rRegL src2, rRegI dst)
2631 %{
2632 int src1enc = $src1$$reg;
2633 int src2enc = $src2$$reg;
2634 int dstenc = $dst$$reg;
2635
2636 // cmpq $src1, $src2
2637 if (src1enc < 8) {
2638 if (src2enc < 8) {
2639 emit_opcode(cbuf, Assembler::REX_W);
2640 } else {
2641 emit_opcode(cbuf, Assembler::REX_WB);
2642 }
2643 } else {
2644 if (src2enc < 8) {
2645 emit_opcode(cbuf, Assembler::REX_WR);
2646 } else {
2647 emit_opcode(cbuf, Assembler::REX_WRB);
2648 }
2649 }
2650 emit_opcode(cbuf, 0x3B);
2651 emit_rm(cbuf, 0x3, src1enc & 7, src2enc & 7);
2652
2653 // movl $dst, -1
2654 if (dstenc >= 8) {
2655 emit_opcode(cbuf, Assembler::REX_B);
2656 }
2657 emit_opcode(cbuf, 0xB8 | (dstenc & 7));
2658 emit_d32(cbuf, -1);
2659
2660 // jl,s done
2661 emit_opcode(cbuf, 0x7C);
2662 emit_d8(cbuf, dstenc < 4 ? 0x06 : 0x08);
2663
2664 // setne $dst
2665 if (dstenc >= 4) {
2666 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_B);
2667 }
2668 emit_opcode(cbuf, 0x0F);
2669 emit_opcode(cbuf, 0x95);
2670 emit_opcode(cbuf, 0xC0 | (dstenc & 7));
2671
2672 // movzbl $dst, $dst
2673 if (dstenc >= 4) {
2674 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_RB);
2675 }
2676 emit_opcode(cbuf, 0x0F);
2677 emit_opcode(cbuf, 0xB6);
2678 emit_rm(cbuf, 0x3, dstenc & 7, dstenc & 7);
2679 %}
2680
2681 enc_class Push_ResultXD(regD dst) %{
2682 MacroAssembler _masm(&cbuf);
2683 __ fstp_d(Address(rsp, 0));
2684 __ movdbl($dst$$XMMRegister, Address(rsp, 0));
2685 __ addptr(rsp, 8);
2686 %}
2687
2688 enc_class Push_SrcXD(regD src) %{
2689 MacroAssembler _masm(&cbuf);
2690 __ subptr(rsp, 8);
2691 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
2692 __ fld_d(Address(rsp, 0));
2693 %}
2694
2695
2696 enc_class enc_rethrow()
2697 %{
2698 cbuf.set_insts_mark();
2699 emit_opcode(cbuf, 0xE9); // jmp entry
2700 emit_d32_reloc(cbuf,
2701 (int) (OptoRuntime::rethrow_stub() - cbuf.insts_end() - 4),
2702 runtime_call_Relocation::spec(),
2703 RELOC_DISP32);
2704 %}
2705
2706 %}
2707
2708
2709
2710 //----------FRAME--------------------------------------------------------------
2711 // Definition of frame structure and management information.
2712 //
2713 // S T A C K L A Y O U T Allocators stack-slot number
2714 // | (to get allocators register number
2715 // G Owned by | | v add OptoReg::stack0())
2716 // r CALLER | |
2717 // o | +--------+ pad to even-align allocators stack-slot
2718 // w V | pad0 | numbers; owned by CALLER
2719 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
2720 // h ^ | in | 5
2721 // | | args | 4 Holes in incoming args owned by SELF
2722 // | | | | 3
2723 // | | +--------+
2724 // V | | old out| Empty on Intel, window on Sparc
2725 // | old |preserve| Must be even aligned.
2726 // | SP-+--------+----> Matcher::_old_SP, even aligned
2727 // | | in | 3 area for Intel ret address
2728 // Owned by |preserve| Empty on Sparc.
2729 // SELF +--------+
2730 // | | pad2 | 2 pad to align old SP
2731 // | +--------+ 1
2732 // | | locks | 0
2733 // | +--------+----> OptoReg::stack0(), even aligned
2734 // | | pad1 | 11 pad to align new SP
2735 // | +--------+
2736 // | | | 10
2737 // | | spills | 9 spills
2738 // V | | 8 (pad0 slot for callee)
2739 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
2740 // ^ | out | 7
2741 // | | args | 6 Holes in outgoing args owned by CALLEE
2742 // Owned by +--------+
2743 // CALLEE | new out| 6 Empty on Intel, window on Sparc
2744 // | new |preserve| Must be even-aligned.
2745 // | SP-+--------+----> Matcher::_new_SP, even aligned
2746 // | | |
2747 //
2748 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
2749 // known from SELF's arguments and the Java calling convention.
2750 // Region 6-7 is determined per call site.
2751 // Note 2: If the calling convention leaves holes in the incoming argument
2752 // area, those holes are owned by SELF. Holes in the outgoing area
2753 // are owned by the CALLEE. Holes should not be nessecary in the
2754 // incoming area, as the Java calling convention is completely under
2755 // the control of the AD file. Doubles can be sorted and packed to
2756 // avoid holes. Holes in the outgoing arguments may be nessecary for
2757 // varargs C calling conventions.
2758 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
2759 // even aligned with pad0 as needed.
2760 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
2761 // region 6-11 is even aligned; it may be padded out more so that
2762 // the region from SP to FP meets the minimum stack alignment.
2763 // Note 4: For I2C adapters, the incoming FP may not meet the minimum stack
2764 // alignment. Region 11, pad1, may be dynamically extended so that
2765 // SP meets the minimum alignment.
2766
2767 frame
2768 %{
2769 // What direction does stack grow in (assumed to be same for C & Java)
2770 stack_direction(TOWARDS_LOW);
2771
2772 // These three registers define part of the calling convention
2773 // between compiled code and the interpreter.
2774 inline_cache_reg(RAX); // Inline Cache Register
2775 interpreter_method_oop_reg(RBX); // Method Oop Register when
2776 // calling interpreter
2777
2778 // Optional: name the operand used by cisc-spilling to access
2779 // [stack_pointer + offset]
2780 cisc_spilling_operand_name(indOffset32);
2781
2782 // Number of stack slots consumed by locking an object
2783 sync_stack_slots(2);
2784
2785 // Compiled code's Frame Pointer
2786 frame_pointer(RSP);
2787
2788 // Interpreter stores its frame pointer in a register which is
2789 // stored to the stack by I2CAdaptors.
2790 // I2CAdaptors convert from interpreted java to compiled java.
2791 interpreter_frame_pointer(RBP);
2792
2793 // Stack alignment requirement
2794 stack_alignment(StackAlignmentInBytes); // Alignment size in bytes (128-bit -> 16 bytes)
2795
2796 // Number of stack slots between incoming argument block and the start of
2797 // a new frame. The PROLOG must add this many slots to the stack. The
2798 // EPILOG must remove this many slots. amd64 needs two slots for
2799 // return address.
2800 in_preserve_stack_slots(4 + 2 * VerifyStackAtCalls);
2801
2802 // Number of outgoing stack slots killed above the out_preserve_stack_slots
2803 // for calls to C. Supports the var-args backing area for register parms.
2804 varargs_C_out_slots_killed(frame::arg_reg_save_area_bytes/BytesPerInt);
2805
2806 // The after-PROLOG location of the return address. Location of
2807 // return address specifies a type (REG or STACK) and a number
2808 // representing the register number (i.e. - use a register name) or
2809 // stack slot.
2810 // Ret Addr is on stack in slot 0 if no locks or verification or alignment.
2811 // Otherwise, it is above the locks and verification slot and alignment word
2812 return_addr(STACK - 2 +
2813 round_to((Compile::current()->in_preserve_stack_slots() +
2814 Compile::current()->fixed_slots()),
2815 stack_alignment_in_slots()));
2816
2817 // Body of function which returns an integer array locating
2818 // arguments either in registers or in stack slots. Passed an array
2819 // of ideal registers called "sig" and a "length" count. Stack-slot
2820 // offsets are based on outgoing arguments, i.e. a CALLER setting up
2821 // arguments for a CALLEE. Incoming stack arguments are
2822 // automatically biased by the preserve_stack_slots field above.
2823
2824 calling_convention
2825 %{
2826 // No difference between ingoing/outgoing just pass false
2827 SharedRuntime::java_calling_convention(sig_bt, regs, length, false);
2828 %}
2829
2830 c_calling_convention
2831 %{
2832 // This is obviously always outgoing
2833 (void) SharedRuntime::c_calling_convention(sig_bt, regs, /*regs2=*/NULL, length);
2834 %}
2835
2836 // Location of compiled Java return values. Same as C for now.
2837 return_value
2838 %{
2839 assert(ideal_reg >= Op_RegI && ideal_reg <= Op_RegL,
2840 "only return normal values");
2841
2842 static const int lo[Op_RegL + 1] = {
2843 0,
2844 0,
2845 RAX_num, // Op_RegN
2846 RAX_num, // Op_RegI
2847 RAX_num, // Op_RegP
2848 XMM0_num, // Op_RegF
2849 XMM0_num, // Op_RegD
2850 RAX_num // Op_RegL
2851 };
2852 static const int hi[Op_RegL + 1] = {
2853 0,
2854 0,
2855 OptoReg::Bad, // Op_RegN
2856 OptoReg::Bad, // Op_RegI
2857 RAX_H_num, // Op_RegP
2858 OptoReg::Bad, // Op_RegF
2859 XMM0b_num, // Op_RegD
2860 RAX_H_num // Op_RegL
2861 };
2862 // Excluded flags and vector registers.
2863 assert(ARRAY_SIZE(hi) == _last_machine_leaf - 6, "missing type");
2864 return OptoRegPair(hi[ideal_reg], lo[ideal_reg]);
2865 %}
2866 %}
2867
2868 //----------ATTRIBUTES---------------------------------------------------------
2869 //----------Operand Attributes-------------------------------------------------
2870 op_attrib op_cost(0); // Required cost attribute
2871
2872 //----------Instruction Attributes---------------------------------------------
2873 ins_attrib ins_cost(100); // Required cost attribute
2874 ins_attrib ins_size(8); // Required size attribute (in bits)
2875 ins_attrib ins_short_branch(0); // Required flag: is this instruction
2876 // a non-matching short branch variant
2877 // of some long branch?
2878 ins_attrib ins_alignment(1); // Required alignment attribute (must
2879 // be a power of 2) specifies the
2880 // alignment that some part of the
2881 // instruction (not necessarily the
2882 // start) requires. If > 1, a
2883 // compute_padding() function must be
2884 // provided for the instruction
2885
2886 //----------OPERANDS-----------------------------------------------------------
2887 // Operand definitions must precede instruction definitions for correct parsing
2888 // in the ADLC because operands constitute user defined types which are used in
2889 // instruction definitions.
2890
2891 //----------Simple Operands----------------------------------------------------
2892 // Immediate Operands
2893 // Integer Immediate
2894 operand immI()
2895 %{
2896 match(ConI);
2897
2898 op_cost(10);
2899 format %{ %}
2900 interface(CONST_INTER);
2901 %}
2902
2903 // Constant for test vs zero
2904 operand immI0()
2905 %{
2906 predicate(n->get_int() == 0);
2907 match(ConI);
2908
2909 op_cost(0);
2910 format %{ %}
2911 interface(CONST_INTER);
2912 %}
2913
2914 // Constant for increment
2915 operand immI1()
2916 %{
2917 predicate(n->get_int() == 1);
2918 match(ConI);
2919
2920 op_cost(0);
2921 format %{ %}
2922 interface(CONST_INTER);
2923 %}
2924
2925 // Constant for decrement
2926 operand immI_M1()
2927 %{
2928 predicate(n->get_int() == -1);
2929 match(ConI);
2930
2931 op_cost(0);
2932 format %{ %}
2933 interface(CONST_INTER);
2934 %}
2935
2936 // Valid scale values for addressing modes
2937 operand immI2()
2938 %{
2939 predicate(0 <= n->get_int() && (n->get_int() <= 3));
2940 match(ConI);
2941
2942 format %{ %}
2943 interface(CONST_INTER);
2944 %}
2945
2946 operand immI8()
2947 %{
2948 predicate((-0x80 <= n->get_int()) && (n->get_int() < 0x80));
2949 match(ConI);
2950
2951 op_cost(5);
2952 format %{ %}
2953 interface(CONST_INTER);
2954 %}
2955
2956 operand immI16()
2957 %{
2958 predicate((-32768 <= n->get_int()) && (n->get_int() <= 32767));
2959 match(ConI);
2960
2961 op_cost(10);
2962 format %{ %}
2963 interface(CONST_INTER);
2964 %}
2965
2966 // Int Immediate non-negative
2967 operand immU31()
2968 %{
2969 predicate(n->get_int() >= 0);
2970 match(ConI);
2971
2972 op_cost(0);
2973 format %{ %}
2974 interface(CONST_INTER);
2975 %}
2976
2977 // Constant for long shifts
2978 operand immI_32()
2979 %{
2980 predicate( n->get_int() == 32 );
2981 match(ConI);
2982
2983 op_cost(0);
2984 format %{ %}
2985 interface(CONST_INTER);
2986 %}
2987
2988 // Constant for long shifts
2989 operand immI_64()
2990 %{
2991 predicate( n->get_int() == 64 );
2992 match(ConI);
2993
2994 op_cost(0);
2995 format %{ %}
2996 interface(CONST_INTER);
2997 %}
2998
2999 // Pointer Immediate
3000 operand immP()
3001 %{
3002 match(ConP);
3003
3004 op_cost(10);
3005 format %{ %}
3006 interface(CONST_INTER);
3007 %}
3008
3009 // NULL Pointer Immediate
3010 operand immP0()
3011 %{
3012 predicate(n->get_ptr() == 0);
3013 match(ConP);
3014
3015 op_cost(5);
3016 format %{ %}
3017 interface(CONST_INTER);
3018 %}
3019
3020 // Pointer Immediate
3021 operand immN() %{
3022 match(ConN);
3023
3024 op_cost(10);
3025 format %{ %}
3026 interface(CONST_INTER);
3027 %}
3028
3029 operand immNKlass() %{
3030 match(ConNKlass);
3031
3032 op_cost(10);
3033 format %{ %}
3034 interface(CONST_INTER);
3035 %}
3036
3037 // NULL Pointer Immediate
3038 operand immN0() %{
3039 predicate(n->get_narrowcon() == 0);
3040 match(ConN);
3041
3042 op_cost(5);
3043 format %{ %}
3044 interface(CONST_INTER);
3045 %}
3046
3047 operand immP31()
3048 %{
3049 predicate(n->as_Type()->type()->reloc() == relocInfo::none
3050 && (n->get_ptr() >> 31) == 0);
3051 match(ConP);
3052
3053 op_cost(5);
3054 format %{ %}
3055 interface(CONST_INTER);
3056 %}
3057
3058
3059 // Long Immediate
3060 operand immL()
3061 %{
3062 match(ConL);
3063
3064 op_cost(20);
3065 format %{ %}
3066 interface(CONST_INTER);
3067 %}
3068
3069 // Long Immediate 8-bit
3070 operand immL8()
3071 %{
3072 predicate(-0x80L <= n->get_long() && n->get_long() < 0x80L);
3073 match(ConL);
3074
3075 op_cost(5);
3076 format %{ %}
3077 interface(CONST_INTER);
3078 %}
3079
3080 // Long Immediate 32-bit unsigned
3081 operand immUL32()
3082 %{
3083 predicate(n->get_long() == (unsigned int) (n->get_long()));
3084 match(ConL);
3085
3086 op_cost(10);
3087 format %{ %}
3088 interface(CONST_INTER);
3089 %}
3090
3091 // Long Immediate 32-bit signed
3092 operand immL32()
3093 %{
3094 predicate(n->get_long() == (int) (n->get_long()));
3095 match(ConL);
3096
3097 op_cost(15);
3098 format %{ %}
3099 interface(CONST_INTER);
3100 %}
3101
3102 // Long Immediate zero
3103 operand immL0()
3104 %{
3105 predicate(n->get_long() == 0L);
3106 match(ConL);
3107
3108 op_cost(10);
3109 format %{ %}
3110 interface(CONST_INTER);
3111 %}
3112
3113 // Constant for increment
3114 operand immL1()
3115 %{
3116 predicate(n->get_long() == 1);
3117 match(ConL);
3118
3119 format %{ %}
3120 interface(CONST_INTER);
3121 %}
3122
3123 // Constant for decrement
3124 operand immL_M1()
3125 %{
3126 predicate(n->get_long() == -1);
3127 match(ConL);
3128
3129 format %{ %}
3130 interface(CONST_INTER);
3131 %}
3132
3133 // Long Immediate: the value 10
3134 operand immL10()
3135 %{
3136 predicate(n->get_long() == 10);
3137 match(ConL);
3138
3139 format %{ %}
3140 interface(CONST_INTER);
3141 %}
3142
3143 // Long immediate from 0 to 127.
3144 // Used for a shorter form of long mul by 10.
3145 operand immL_127()
3146 %{
3147 predicate(0 <= n->get_long() && n->get_long() < 0x80);
3148 match(ConL);
3149
3150 op_cost(10);
3151 format %{ %}
3152 interface(CONST_INTER);
3153 %}
3154
3155 // Long Immediate: low 32-bit mask
3156 operand immL_32bits()
3157 %{
3158 predicate(n->get_long() == 0xFFFFFFFFL);
3159 match(ConL);
3160 op_cost(20);
3161
3162 format %{ %}
3163 interface(CONST_INTER);
3164 %}
3165
3166 // Float Immediate zero
3167 operand immF0()
3168 %{
3169 predicate(jint_cast(n->getf()) == 0);
3170 match(ConF);
3171
3172 op_cost(5);
3173 format %{ %}
3174 interface(CONST_INTER);
3175 %}
3176
3177 // Float Immediate
3178 operand immF()
3179 %{
3180 match(ConF);
3181
3182 op_cost(15);
3183 format %{ %}
3184 interface(CONST_INTER);
3185 %}
3186
3187 // Double Immediate zero
3188 operand immD0()
3189 %{
3190 predicate(jlong_cast(n->getd()) == 0);
3191 match(ConD);
3192
3193 op_cost(5);
3194 format %{ %}
3195 interface(CONST_INTER);
3196 %}
3197
3198 // Double Immediate
3199 operand immD()
3200 %{
3201 match(ConD);
3202
3203 op_cost(15);
3204 format %{ %}
3205 interface(CONST_INTER);
3206 %}
3207
3208 // Immediates for special shifts (sign extend)
3209
3210 // Constants for increment
3211 operand immI_16()
3212 %{
3213 predicate(n->get_int() == 16);
3214 match(ConI);
3215
3216 format %{ %}
3217 interface(CONST_INTER);
3218 %}
3219
3220 operand immI_24()
3221 %{
3222 predicate(n->get_int() == 24);
3223 match(ConI);
3224
3225 format %{ %}
3226 interface(CONST_INTER);
3227 %}
3228
3229 // Constant for byte-wide masking
3230 operand immI_255()
3231 %{
3232 predicate(n->get_int() == 255);
3233 match(ConI);
3234
3235 format %{ %}
3236 interface(CONST_INTER);
3237 %}
3238
3239 // Constant for short-wide masking
3240 operand immI_65535()
3241 %{
3242 predicate(n->get_int() == 65535);
3243 match(ConI);
3244
3245 format %{ %}
3246 interface(CONST_INTER);
3247 %}
3248
3249 // Constant for byte-wide masking
3250 operand immL_255()
3251 %{
3252 predicate(n->get_long() == 255);
3253 match(ConL);
3254
3255 format %{ %}
3256 interface(CONST_INTER);
3257 %}
3258
3259 // Constant for short-wide masking
3260 operand immL_65535()
3261 %{
3262 predicate(n->get_long() == 65535);
3263 match(ConL);
3264
3265 format %{ %}
3266 interface(CONST_INTER);
3267 %}
3268
3269 // Register Operands
3270 // Integer Register
3271 operand rRegI()
3272 %{
3273 constraint(ALLOC_IN_RC(int_reg));
3274 match(RegI);
3275
3276 match(rax_RegI);
3277 match(rbx_RegI);
3278 match(rcx_RegI);
3279 match(rdx_RegI);
3280 match(rdi_RegI);
3281
3282 format %{ %}
3283 interface(REG_INTER);
3284 %}
3285
3286 // Special Registers
3287 operand rax_RegI()
3288 %{
3289 constraint(ALLOC_IN_RC(int_rax_reg));
3290 match(RegI);
3291 match(rRegI);
3292
3293 format %{ "RAX" %}
3294 interface(REG_INTER);
3295 %}
3296
3297 // Special Registers
3298 operand rbx_RegI()
3299 %{
3300 constraint(ALLOC_IN_RC(int_rbx_reg));
3301 match(RegI);
3302 match(rRegI);
3303
3304 format %{ "RBX" %}
3305 interface(REG_INTER);
3306 %}
3307
3308 operand rcx_RegI()
3309 %{
3310 constraint(ALLOC_IN_RC(int_rcx_reg));
3311 match(RegI);
3312 match(rRegI);
3313
3314 format %{ "RCX" %}
3315 interface(REG_INTER);
3316 %}
3317
3318 operand rdx_RegI()
3319 %{
3320 constraint(ALLOC_IN_RC(int_rdx_reg));
3321 match(RegI);
3322 match(rRegI);
3323
3324 format %{ "RDX" %}
3325 interface(REG_INTER);
3326 %}
3327
3328 operand rdi_RegI()
3329 %{
3330 constraint(ALLOC_IN_RC(int_rdi_reg));
3331 match(RegI);
3332 match(rRegI);
3333
3334 format %{ "RDI" %}
3335 interface(REG_INTER);
3336 %}
3337
3338 operand no_rcx_RegI()
3339 %{
3340 constraint(ALLOC_IN_RC(int_no_rcx_reg));
3341 match(RegI);
3342 match(rax_RegI);
3343 match(rbx_RegI);
3344 match(rdx_RegI);
3345 match(rdi_RegI);
3346
3347 format %{ %}
3348 interface(REG_INTER);
3349 %}
3350
3351 operand no_rax_rdx_RegI()
3352 %{
3353 constraint(ALLOC_IN_RC(int_no_rax_rdx_reg));
3354 match(RegI);
3355 match(rbx_RegI);
3356 match(rcx_RegI);
3357 match(rdi_RegI);
3358
3359 format %{ %}
3360 interface(REG_INTER);
3361 %}
3362
3363 // Pointer Register
3364 operand any_RegP()
3365 %{
3366 constraint(ALLOC_IN_RC(any_reg));
3367 match(RegP);
3368 match(rax_RegP);
3369 match(rbx_RegP);
3370 match(rdi_RegP);
3371 match(rsi_RegP);
3372 match(rbp_RegP);
3373 match(r15_RegP);
3374 match(rRegP);
3375
3376 format %{ %}
3377 interface(REG_INTER);
3378 %}
3379
3380 operand rRegP()
3381 %{
3382 constraint(ALLOC_IN_RC(ptr_reg));
3383 match(RegP);
3384 match(rax_RegP);
3385 match(rbx_RegP);
3386 match(rdi_RegP);
3387 match(rsi_RegP);
3388 match(rbp_RegP); // See Q&A below about
3389 match(r15_RegP); // r15_RegP and rbp_RegP.
3390
3391 format %{ %}
3392 interface(REG_INTER);
3393 %}
3394
3395 operand rRegN() %{
3396 constraint(ALLOC_IN_RC(int_reg));
3397 match(RegN);
3398
3399 format %{ %}
3400 interface(REG_INTER);
3401 %}
3402
3403 // Question: Why is r15_RegP (the read-only TLS register) a match for rRegP?
3404 // Answer: Operand match rules govern the DFA as it processes instruction inputs.
3405 // It's fine for an instruction input that expects rRegP to match a r15_RegP.
3406 // The output of an instruction is controlled by the allocator, which respects
3407 // register class masks, not match rules. Unless an instruction mentions
3408 // r15_RegP or any_RegP explicitly as its output, r15 will not be considered
3409 // by the allocator as an input.
3410 // The same logic applies to rbp_RegP being a match for rRegP: If PreserveFramePointer==true,
3411 // the RBP is used as a proper frame pointer and is not included in ptr_reg. As a
3412 // result, RBP is not included in the output of the instruction either.
3413
3414 operand no_rax_RegP()
3415 %{
3416 constraint(ALLOC_IN_RC(ptr_no_rax_reg));
3417 match(RegP);
3418 match(rbx_RegP);
3419 match(rsi_RegP);
3420 match(rdi_RegP);
3421
3422 format %{ %}
3423 interface(REG_INTER);
3424 %}
3425
3426 // This operand is not allowed to use RBP even if
3427 // RBP is not used to hold the frame pointer.
3428 operand no_rbp_RegP()
3429 %{
3430 constraint(ALLOC_IN_RC(ptr_reg_no_rbp));
3431 match(RegP);
3432 match(rbx_RegP);
3433 match(rsi_RegP);
3434 match(rdi_RegP);
3435
3436 format %{ %}
3437 interface(REG_INTER);
3438 %}
3439
3440 operand no_rax_rbx_RegP()
3441 %{
3442 constraint(ALLOC_IN_RC(ptr_no_rax_rbx_reg));
3443 match(RegP);
3444 match(rsi_RegP);
3445 match(rdi_RegP);
3446
3447 format %{ %}
3448 interface(REG_INTER);
3449 %}
3450
3451 // Special Registers
3452 // Return a pointer value
3453 operand rax_RegP()
3454 %{
3455 constraint(ALLOC_IN_RC(ptr_rax_reg));
3456 match(RegP);
3457 match(rRegP);
3458
3459 format %{ %}
3460 interface(REG_INTER);
3461 %}
3462
3463 // Special Registers
3464 // Return a compressed pointer value
3465 operand rax_RegN()
3466 %{
3467 constraint(ALLOC_IN_RC(int_rax_reg));
3468 match(RegN);
3469 match(rRegN);
3470
3471 format %{ %}
3472 interface(REG_INTER);
3473 %}
3474
3475 // Used in AtomicAdd
3476 operand rbx_RegP()
3477 %{
3478 constraint(ALLOC_IN_RC(ptr_rbx_reg));
3479 match(RegP);
3480 match(rRegP);
3481
3482 format %{ %}
3483 interface(REG_INTER);
3484 %}
3485
3486 operand rsi_RegP()
3487 %{
3488 constraint(ALLOC_IN_RC(ptr_rsi_reg));
3489 match(RegP);
3490 match(rRegP);
3491
3492 format %{ %}
3493 interface(REG_INTER);
3494 %}
3495
3496 // Used in rep stosq
3497 operand rdi_RegP()
3498 %{
3499 constraint(ALLOC_IN_RC(ptr_rdi_reg));
3500 match(RegP);
3501 match(rRegP);
3502
3503 format %{ %}
3504 interface(REG_INTER);
3505 %}
3506
3507 operand r15_RegP()
3508 %{
3509 constraint(ALLOC_IN_RC(ptr_r15_reg));
3510 match(RegP);
3511 match(rRegP);
3512
3513 format %{ %}
3514 interface(REG_INTER);
3515 %}
3516
3517 operand rRegL()
3518 %{
3519 constraint(ALLOC_IN_RC(long_reg));
3520 match(RegL);
3521 match(rax_RegL);
3522 match(rdx_RegL);
3523
3524 format %{ %}
3525 interface(REG_INTER);
3526 %}
3527
3528 // Special Registers
3529 operand no_rax_rdx_RegL()
3530 %{
3531 constraint(ALLOC_IN_RC(long_no_rax_rdx_reg));
3532 match(RegL);
3533 match(rRegL);
3534
3535 format %{ %}
3536 interface(REG_INTER);
3537 %}
3538
3539 operand no_rax_RegL()
3540 %{
3541 constraint(ALLOC_IN_RC(long_no_rax_rdx_reg));
3542 match(RegL);
3543 match(rRegL);
3544 match(rdx_RegL);
3545
3546 format %{ %}
3547 interface(REG_INTER);
3548 %}
3549
3550 operand no_rcx_RegL()
3551 %{
3552 constraint(ALLOC_IN_RC(long_no_rcx_reg));
3553 match(RegL);
3554 match(rRegL);
3555
3556 format %{ %}
3557 interface(REG_INTER);
3558 %}
3559
3560 operand rax_RegL()
3561 %{
3562 constraint(ALLOC_IN_RC(long_rax_reg));
3563 match(RegL);
3564 match(rRegL);
3565
3566 format %{ "RAX" %}
3567 interface(REG_INTER);
3568 %}
3569
3570 operand rcx_RegL()
3571 %{
3572 constraint(ALLOC_IN_RC(long_rcx_reg));
3573 match(RegL);
3574 match(rRegL);
3575
3576 format %{ %}
3577 interface(REG_INTER);
3578 %}
3579
3580 operand rdx_RegL()
3581 %{
3582 constraint(ALLOC_IN_RC(long_rdx_reg));
3583 match(RegL);
3584 match(rRegL);
3585
3586 format %{ %}
3587 interface(REG_INTER);
3588 %}
3589
3590 // Flags register, used as output of compare instructions
3591 operand rFlagsReg()
3592 %{
3593 constraint(ALLOC_IN_RC(int_flags));
3594 match(RegFlags);
3595
3596 format %{ "RFLAGS" %}
3597 interface(REG_INTER);
3598 %}
3599
3600 // Flags register, used as output of FLOATING POINT compare instructions
3601 operand rFlagsRegU()
3602 %{
3603 constraint(ALLOC_IN_RC(int_flags));
3604 match(RegFlags);
3605
3606 format %{ "RFLAGS_U" %}
3607 interface(REG_INTER);
3608 %}
3609
3610 operand rFlagsRegUCF() %{
3611 constraint(ALLOC_IN_RC(int_flags));
3612 match(RegFlags);
3613 predicate(false);
3614
3615 format %{ "RFLAGS_U_CF" %}
3616 interface(REG_INTER);
3617 %}
3618
3619 // Float register operands
3620 operand regF() %{
3621 constraint(ALLOC_IN_RC(float_reg));
3622 match(RegF);
3623
3624 format %{ %}
3625 interface(REG_INTER);
3626 %}
3627
3628 // Double register operands
3629 operand regD() %{
3630 constraint(ALLOC_IN_RC(double_reg));
3631 match(RegD);
3632
3633 format %{ %}
3634 interface(REG_INTER);
3635 %}
3636
3637 // Vectors
3638 operand vecS() %{
3639 constraint(ALLOC_IN_RC(vectors_reg));
3640 match(VecS);
3641
3642 format %{ %}
3643 interface(REG_INTER);
3644 %}
3645
3646 operand vecD() %{
3647 constraint(ALLOC_IN_RC(vectord_reg));
3648 match(VecD);
3649
3650 format %{ %}
3651 interface(REG_INTER);
3652 %}
3653
3654 operand vecX() %{
3655 constraint(ALLOC_IN_RC(vectorx_reg));
3656 match(VecX);
3657
3658 format %{ %}
3659 interface(REG_INTER);
3660 %}
3661
3662 operand vecY() %{
3663 constraint(ALLOC_IN_RC(vectory_reg));
3664 match(VecY);
3665
3666 format %{ %}
3667 interface(REG_INTER);
3668 %}
3669
3670 //----------Memory Operands----------------------------------------------------
3671 // Direct Memory Operand
3672 // operand direct(immP addr)
3673 // %{
3674 // match(addr);
3675
3676 // format %{ "[$addr]" %}
3677 // interface(MEMORY_INTER) %{
3678 // base(0xFFFFFFFF);
3679 // index(0x4);
3680 // scale(0x0);
3681 // disp($addr);
3682 // %}
3683 // %}
3684
3685 // Indirect Memory Operand
3686 operand indirect(any_RegP reg)
3687 %{
3688 constraint(ALLOC_IN_RC(ptr_reg));
3689 match(reg);
3690
3691 format %{ "[$reg]" %}
3692 interface(MEMORY_INTER) %{
3693 base($reg);
3694 index(0x4);
3695 scale(0x0);
3696 disp(0x0);
3697 %}
3698 %}
3699
3700 // Indirect Memory Plus Short Offset Operand
3701 operand indOffset8(any_RegP reg, immL8 off)
3702 %{
3703 constraint(ALLOC_IN_RC(ptr_reg));
3704 match(AddP reg off);
3705
3706 format %{ "[$reg + $off (8-bit)]" %}
3707 interface(MEMORY_INTER) %{
3708 base($reg);
3709 index(0x4);
3710 scale(0x0);
3711 disp($off);
3712 %}
3713 %}
3714
3715 // Indirect Memory Plus Long Offset Operand
3716 operand indOffset32(any_RegP reg, immL32 off)
3717 %{
3718 constraint(ALLOC_IN_RC(ptr_reg));
3719 match(AddP reg off);
3720
3721 format %{ "[$reg + $off (32-bit)]" %}
3722 interface(MEMORY_INTER) %{
3723 base($reg);
3724 index(0x4);
3725 scale(0x0);
3726 disp($off);
3727 %}
3728 %}
3729
3730 // Indirect Memory Plus Index Register Plus Offset Operand
3731 operand indIndexOffset(any_RegP reg, rRegL lreg, immL32 off)
3732 %{
3733 constraint(ALLOC_IN_RC(ptr_reg));
3734 match(AddP (AddP reg lreg) off);
3735
3736 op_cost(10);
3737 format %{"[$reg + $off + $lreg]" %}
3738 interface(MEMORY_INTER) %{
3739 base($reg);
3740 index($lreg);
3741 scale(0x0);
3742 disp($off);
3743 %}
3744 %}
3745
3746 // Indirect Memory Plus Index Register Plus Offset Operand
3747 operand indIndex(any_RegP reg, rRegL lreg)
3748 %{
3749 constraint(ALLOC_IN_RC(ptr_reg));
3750 match(AddP reg lreg);
3751
3752 op_cost(10);
3753 format %{"[$reg + $lreg]" %}
3754 interface(MEMORY_INTER) %{
3755 base($reg);
3756 index($lreg);
3757 scale(0x0);
3758 disp(0x0);
3759 %}
3760 %}
3761
3762 // Indirect Memory Times Scale Plus Index Register
3763 operand indIndexScale(any_RegP reg, rRegL lreg, immI2 scale)
3764 %{
3765 constraint(ALLOC_IN_RC(ptr_reg));
3766 match(AddP reg (LShiftL lreg scale));
3767
3768 op_cost(10);
3769 format %{"[$reg + $lreg << $scale]" %}
3770 interface(MEMORY_INTER) %{
3771 base($reg);
3772 index($lreg);
3773 scale($scale);
3774 disp(0x0);
3775 %}
3776 %}
3777
3778 operand indPosIndexScale(any_RegP reg, rRegI idx, immI2 scale)
3779 %{
3780 constraint(ALLOC_IN_RC(ptr_reg));
3781 predicate(n->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0);
3782 match(AddP reg (LShiftL (ConvI2L idx) scale));
3783
3784 op_cost(10);
3785 format %{"[$reg + pos $idx << $scale]" %}
3786 interface(MEMORY_INTER) %{
3787 base($reg);
3788 index($idx);
3789 scale($scale);
3790 disp(0x0);
3791 %}
3792 %}
3793
3794 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
3795 operand indIndexScaleOffset(any_RegP reg, immL32 off, rRegL lreg, immI2 scale)
3796 %{
3797 constraint(ALLOC_IN_RC(ptr_reg));
3798 match(AddP (AddP reg (LShiftL lreg scale)) off);
3799
3800 op_cost(10);
3801 format %{"[$reg + $off + $lreg << $scale]" %}
3802 interface(MEMORY_INTER) %{
3803 base($reg);
3804 index($lreg);
3805 scale($scale);
3806 disp($off);
3807 %}
3808 %}
3809
3810 // Indirect Memory Plus Positive Index Register Plus Offset Operand
3811 operand indPosIndexOffset(any_RegP reg, immL32 off, rRegI idx)
3812 %{
3813 constraint(ALLOC_IN_RC(ptr_reg));
3814 predicate(n->in(2)->in(3)->as_Type()->type()->is_long()->_lo >= 0);
3815 match(AddP (AddP reg (ConvI2L idx)) off);
3816
3817 op_cost(10);
3818 format %{"[$reg + $off + $idx]" %}
3819 interface(MEMORY_INTER) %{
3820 base($reg);
3821 index($idx);
3822 scale(0x0);
3823 disp($off);
3824 %}
3825 %}
3826
3827 // Indirect Memory Times Scale Plus Positive Index Register Plus Offset Operand
3828 operand indPosIndexScaleOffset(any_RegP reg, immL32 off, rRegI idx, immI2 scale)
3829 %{
3830 constraint(ALLOC_IN_RC(ptr_reg));
3831 predicate(n->in(2)->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0);
3832 match(AddP (AddP reg (LShiftL (ConvI2L idx) scale)) off);
3833
3834 op_cost(10);
3835 format %{"[$reg + $off + $idx << $scale]" %}
3836 interface(MEMORY_INTER) %{
3837 base($reg);
3838 index($idx);
3839 scale($scale);
3840 disp($off);
3841 %}
3842 %}
3843
3844 // Indirect Narrow Oop Plus Offset Operand
3845 // Note: x86 architecture doesn't support "scale * index + offset" without a base
3846 // we can't free r12 even with Universe::narrow_oop_base() == NULL.
3847 operand indCompressedOopOffset(rRegN reg, immL32 off) %{
3848 predicate(UseCompressedOops && (Universe::narrow_oop_shift() == Address::times_8));
3849 constraint(ALLOC_IN_RC(ptr_reg));
3850 match(AddP (DecodeN reg) off);
3851
3852 op_cost(10);
3853 format %{"[R12 + $reg << 3 + $off] (compressed oop addressing)" %}
3854 interface(MEMORY_INTER) %{
3855 base(0xc); // R12
3856 index($reg);
3857 scale(0x3);
3858 disp($off);
3859 %}
3860 %}
3861
3862 // Indirect Memory Operand
3863 operand indirectNarrow(rRegN reg)
3864 %{
3865 predicate(Universe::narrow_oop_shift() == 0);
3866 constraint(ALLOC_IN_RC(ptr_reg));
3867 match(DecodeN reg);
3868
3869 format %{ "[$reg]" %}
3870 interface(MEMORY_INTER) %{
3871 base($reg);
3872 index(0x4);
3873 scale(0x0);
3874 disp(0x0);
3875 %}
3876 %}
3877
3878 // Indirect Memory Plus Short Offset Operand
3879 operand indOffset8Narrow(rRegN reg, immL8 off)
3880 %{
3881 predicate(Universe::narrow_oop_shift() == 0);
3882 constraint(ALLOC_IN_RC(ptr_reg));
3883 match(AddP (DecodeN reg) off);
3884
3885 format %{ "[$reg + $off (8-bit)]" %}
3886 interface(MEMORY_INTER) %{
3887 base($reg);
3888 index(0x4);
3889 scale(0x0);
3890 disp($off);
3891 %}
3892 %}
3893
3894 // Indirect Memory Plus Long Offset Operand
3895 operand indOffset32Narrow(rRegN reg, immL32 off)
3896 %{
3897 predicate(Universe::narrow_oop_shift() == 0);
3898 constraint(ALLOC_IN_RC(ptr_reg));
3899 match(AddP (DecodeN reg) off);
3900
3901 format %{ "[$reg + $off (32-bit)]" %}
3902 interface(MEMORY_INTER) %{
3903 base($reg);
3904 index(0x4);
3905 scale(0x0);
3906 disp($off);
3907 %}
3908 %}
3909
3910 // Indirect Memory Plus Index Register Plus Offset Operand
3911 operand indIndexOffsetNarrow(rRegN reg, rRegL lreg, immL32 off)
3912 %{
3913 predicate(Universe::narrow_oop_shift() == 0);
3914 constraint(ALLOC_IN_RC(ptr_reg));
3915 match(AddP (AddP (DecodeN reg) lreg) off);
3916
3917 op_cost(10);
3918 format %{"[$reg + $off + $lreg]" %}
3919 interface(MEMORY_INTER) %{
3920 base($reg);
3921 index($lreg);
3922 scale(0x0);
3923 disp($off);
3924 %}
3925 %}
3926
3927 // Indirect Memory Plus Index Register Plus Offset Operand
3928 operand indIndexNarrow(rRegN reg, rRegL lreg)
3929 %{
3930 predicate(Universe::narrow_oop_shift() == 0);
3931 constraint(ALLOC_IN_RC(ptr_reg));
3932 match(AddP (DecodeN reg) lreg);
3933
3934 op_cost(10);
3935 format %{"[$reg + $lreg]" %}
3936 interface(MEMORY_INTER) %{
3937 base($reg);
3938 index($lreg);
3939 scale(0x0);
3940 disp(0x0);
3941 %}
3942 %}
3943
3944 // Indirect Memory Times Scale Plus Index Register
3945 operand indIndexScaleNarrow(rRegN reg, rRegL lreg, immI2 scale)
3946 %{
3947 predicate(Universe::narrow_oop_shift() == 0);
3948 constraint(ALLOC_IN_RC(ptr_reg));
3949 match(AddP (DecodeN reg) (LShiftL lreg scale));
3950
3951 op_cost(10);
3952 format %{"[$reg + $lreg << $scale]" %}
3953 interface(MEMORY_INTER) %{
3954 base($reg);
3955 index($lreg);
3956 scale($scale);
3957 disp(0x0);
3958 %}
3959 %}
3960
3961 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
3962 operand indIndexScaleOffsetNarrow(rRegN reg, immL32 off, rRegL lreg, immI2 scale)
3963 %{
3964 predicate(Universe::narrow_oop_shift() == 0);
3965 constraint(ALLOC_IN_RC(ptr_reg));
3966 match(AddP (AddP (DecodeN reg) (LShiftL lreg scale)) off);
3967
3968 op_cost(10);
3969 format %{"[$reg + $off + $lreg << $scale]" %}
3970 interface(MEMORY_INTER) %{
3971 base($reg);
3972 index($lreg);
3973 scale($scale);
3974 disp($off);
3975 %}
3976 %}
3977
3978 // Indirect Memory Times Plus Positive Index Register Plus Offset Operand
3979 operand indPosIndexOffsetNarrow(rRegN reg, immL32 off, rRegI idx)
3980 %{
3981 constraint(ALLOC_IN_RC(ptr_reg));
3982 predicate(Universe::narrow_oop_shift() == 0 && n->in(2)->in(3)->as_Type()->type()->is_long()->_lo >= 0);
3983 match(AddP (AddP (DecodeN reg) (ConvI2L idx)) off);
3984
3985 op_cost(10);
3986 format %{"[$reg + $off + $idx]" %}
3987 interface(MEMORY_INTER) %{
3988 base($reg);
3989 index($idx);
3990 scale(0x0);
3991 disp($off);
3992 %}
3993 %}
3994
3995 // Indirect Memory Times Scale Plus Positive Index Register Plus Offset Operand
3996 operand indPosIndexScaleOffsetNarrow(rRegN reg, immL32 off, rRegI idx, immI2 scale)
3997 %{
3998 constraint(ALLOC_IN_RC(ptr_reg));
3999 predicate(Universe::narrow_oop_shift() == 0 && n->in(2)->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0);
4000 match(AddP (AddP (DecodeN reg) (LShiftL (ConvI2L idx) scale)) off);
4001
4002 op_cost(10);
4003 format %{"[$reg + $off + $idx << $scale]" %}
4004 interface(MEMORY_INTER) %{
4005 base($reg);
4006 index($idx);
4007 scale($scale);
4008 disp($off);
4009 %}
4010 %}
4011
4012 //----------Special Memory Operands--------------------------------------------
4013 // Stack Slot Operand - This operand is used for loading and storing temporary
4014 // values on the stack where a match requires a value to
4015 // flow through memory.
4016 operand stackSlotP(sRegP reg)
4017 %{
4018 constraint(ALLOC_IN_RC(stack_slots));
4019 // No match rule because this operand is only generated in matching
4020
4021 format %{ "[$reg]" %}
4022 interface(MEMORY_INTER) %{
4023 base(0x4); // RSP
4024 index(0x4); // No Index
4025 scale(0x0); // No Scale
4026 disp($reg); // Stack Offset
4027 %}
4028 %}
4029
4030 operand stackSlotI(sRegI reg)
4031 %{
4032 constraint(ALLOC_IN_RC(stack_slots));
4033 // No match rule because this operand is only generated in matching
4034
4035 format %{ "[$reg]" %}
4036 interface(MEMORY_INTER) %{
4037 base(0x4); // RSP
4038 index(0x4); // No Index
4039 scale(0x0); // No Scale
4040 disp($reg); // Stack Offset
4041 %}
4042 %}
4043
4044 operand stackSlotF(sRegF reg)
4045 %{
4046 constraint(ALLOC_IN_RC(stack_slots));
4047 // No match rule because this operand is only generated in matching
4048
4049 format %{ "[$reg]" %}
4050 interface(MEMORY_INTER) %{
4051 base(0x4); // RSP
4052 index(0x4); // No Index
4053 scale(0x0); // No Scale
4054 disp($reg); // Stack Offset
4055 %}
4056 %}
4057
4058 operand stackSlotD(sRegD reg)
4059 %{
4060 constraint(ALLOC_IN_RC(stack_slots));
4061 // No match rule because this operand is only generated in matching
4062
4063 format %{ "[$reg]" %}
4064 interface(MEMORY_INTER) %{
4065 base(0x4); // RSP
4066 index(0x4); // No Index
4067 scale(0x0); // No Scale
4068 disp($reg); // Stack Offset
4069 %}
4070 %}
4071 operand stackSlotL(sRegL reg)
4072 %{
4073 constraint(ALLOC_IN_RC(stack_slots));
4074 // No match rule because this operand is only generated in matching
4075
4076 format %{ "[$reg]" %}
4077 interface(MEMORY_INTER) %{
4078 base(0x4); // RSP
4079 index(0x4); // No Index
4080 scale(0x0); // No Scale
4081 disp($reg); // Stack Offset
4082 %}
4083 %}
4084
4085 //----------Conditional Branch Operands----------------------------------------
4086 // Comparison Op - This is the operation of the comparison, and is limited to
4087 // the following set of codes:
4088 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
4089 //
4090 // Other attributes of the comparison, such as unsignedness, are specified
4091 // by the comparison instruction that sets a condition code flags register.
4092 // That result is represented by a flags operand whose subtype is appropriate
4093 // to the unsignedness (etc.) of the comparison.
4094 //
4095 // Later, the instruction which matches both the Comparison Op (a Bool) and
4096 // the flags (produced by the Cmp) specifies the coding of the comparison op
4097 // by matching a specific subtype of Bool operand below, such as cmpOpU.
4098
4099 // Comparision Code
4100 operand cmpOp()
4101 %{
4102 match(Bool);
4103
4104 format %{ "" %}
4105 interface(COND_INTER) %{
4106 equal(0x4, "e");
4107 not_equal(0x5, "ne");
4108 less(0xC, "l");
4109 greater_equal(0xD, "ge");
4110 less_equal(0xE, "le");
4111 greater(0xF, "g");
4112 overflow(0x0, "o");
4113 no_overflow(0x1, "no");
4114 %}
4115 %}
4116
4117 // Comparison Code, unsigned compare. Used by FP also, with
4118 // C2 (unordered) turned into GT or LT already. The other bits
4119 // C0 and C3 are turned into Carry & Zero flags.
4120 operand cmpOpU()
4121 %{
4122 match(Bool);
4123
4124 format %{ "" %}
4125 interface(COND_INTER) %{
4126 equal(0x4, "e");
4127 not_equal(0x5, "ne");
4128 less(0x2, "b");
4129 greater_equal(0x3, "nb");
4130 less_equal(0x6, "be");
4131 greater(0x7, "nbe");
4132 overflow(0x0, "o");
4133 no_overflow(0x1, "no");
4134 %}
4135 %}
4136
4137
4138 // Floating comparisons that don't require any fixup for the unordered case
4139 operand cmpOpUCF() %{
4140 match(Bool);
4141 predicate(n->as_Bool()->_test._test == BoolTest::lt ||
4142 n->as_Bool()->_test._test == BoolTest::ge ||
4143 n->as_Bool()->_test._test == BoolTest::le ||
4144 n->as_Bool()->_test._test == BoolTest::gt);
4145 format %{ "" %}
4146 interface(COND_INTER) %{
4147 equal(0x4, "e");
4148 not_equal(0x5, "ne");
4149 less(0x2, "b");
4150 greater_equal(0x3, "nb");
4151 less_equal(0x6, "be");
4152 greater(0x7, "nbe");
4153 overflow(0x0, "o");
4154 no_overflow(0x1, "no");
4155 %}
4156 %}
4157
4158
4159 // Floating comparisons that can be fixed up with extra conditional jumps
4160 operand cmpOpUCF2() %{
4161 match(Bool);
4162 predicate(n->as_Bool()->_test._test == BoolTest::ne ||
4163 n->as_Bool()->_test._test == BoolTest::eq);
4164 format %{ "" %}
4165 interface(COND_INTER) %{
4166 equal(0x4, "e");
4167 not_equal(0x5, "ne");
4168 less(0x2, "b");
4169 greater_equal(0x3, "nb");
4170 less_equal(0x6, "be");
4171 greater(0x7, "nbe");
4172 overflow(0x0, "o");
4173 no_overflow(0x1, "no");
4174 %}
4175 %}
4176
4177
4178 //----------OPERAND CLASSES----------------------------------------------------
4179 // Operand Classes are groups of operands that are used as to simplify
4180 // instruction definitions by not requiring the AD writer to specify separate
4181 // instructions for every form of operand when the instruction accepts
4182 // multiple operand types with the same basic encoding and format. The classic
4183 // case of this is memory operands.
4184
4185 opclass memory(indirect, indOffset8, indOffset32, indIndexOffset, indIndex,
4186 indIndexScale, indPosIndexScale, indIndexScaleOffset, indPosIndexOffset, indPosIndexScaleOffset,
4187 indCompressedOopOffset,
4188 indirectNarrow, indOffset8Narrow, indOffset32Narrow,
4189 indIndexOffsetNarrow, indIndexNarrow, indIndexScaleNarrow,
4190 indIndexScaleOffsetNarrow, indPosIndexOffsetNarrow, indPosIndexScaleOffsetNarrow);
4191
4192 //----------PIPELINE-----------------------------------------------------------
4193 // Rules which define the behavior of the target architectures pipeline.
4194 pipeline %{
4195
4196 //----------ATTRIBUTES---------------------------------------------------------
4197 attributes %{
4198 variable_size_instructions; // Fixed size instructions
4199 max_instructions_per_bundle = 3; // Up to 3 instructions per bundle
4200 instruction_unit_size = 1; // An instruction is 1 bytes long
4201 instruction_fetch_unit_size = 16; // The processor fetches one line
4202 instruction_fetch_units = 1; // of 16 bytes
4203
4204 // List of nop instructions
4205 nops( MachNop );
4206 %}
4207
4208 //----------RESOURCES----------------------------------------------------------
4209 // Resources are the functional units available to the machine
4210
4211 // Generic P2/P3 pipeline
4212 // 3 decoders, only D0 handles big operands; a "bundle" is the limit of
4213 // 3 instructions decoded per cycle.
4214 // 2 load/store ops per cycle, 1 branch, 1 FPU,
4215 // 3 ALU op, only ALU0 handles mul instructions.
4216 resources( D0, D1, D2, DECODE = D0 | D1 | D2,
4217 MS0, MS1, MS2, MEM = MS0 | MS1 | MS2,
4218 BR, FPU,
4219 ALU0, ALU1, ALU2, ALU = ALU0 | ALU1 | ALU2);
4220
4221 //----------PIPELINE DESCRIPTION-----------------------------------------------
4222 // Pipeline Description specifies the stages in the machine's pipeline
4223
4224 // Generic P2/P3 pipeline
4225 pipe_desc(S0, S1, S2, S3, S4, S5);
4226
4227 //----------PIPELINE CLASSES---------------------------------------------------
4228 // Pipeline Classes describe the stages in which input and output are
4229 // referenced by the hardware pipeline.
4230
4231 // Naming convention: ialu or fpu
4232 // Then: _reg
4233 // Then: _reg if there is a 2nd register
4234 // Then: _long if it's a pair of instructions implementing a long
4235 // Then: _fat if it requires the big decoder
4236 // Or: _mem if it requires the big decoder and a memory unit.
4237
4238 // Integer ALU reg operation
4239 pipe_class ialu_reg(rRegI dst)
4240 %{
4241 single_instruction;
4242 dst : S4(write);
4243 dst : S3(read);
4244 DECODE : S0; // any decoder
4245 ALU : S3; // any alu
4246 %}
4247
4248 // Long ALU reg operation
4249 pipe_class ialu_reg_long(rRegL dst)
4250 %{
4251 instruction_count(2);
4252 dst : S4(write);
4253 dst : S3(read);
4254 DECODE : S0(2); // any 2 decoders
4255 ALU : S3(2); // both alus
4256 %}
4257
4258 // Integer ALU reg operation using big decoder
4259 pipe_class ialu_reg_fat(rRegI dst)
4260 %{
4261 single_instruction;
4262 dst : S4(write);
4263 dst : S3(read);
4264 D0 : S0; // big decoder only
4265 ALU : S3; // any alu
4266 %}
4267
4268 // Long ALU reg operation using big decoder
4269 pipe_class ialu_reg_long_fat(rRegL dst)
4270 %{
4271 instruction_count(2);
4272 dst : S4(write);
4273 dst : S3(read);
4274 D0 : S0(2); // big decoder only; twice
4275 ALU : S3(2); // any 2 alus
4276 %}
4277
4278 // Integer ALU reg-reg operation
4279 pipe_class ialu_reg_reg(rRegI dst, rRegI src)
4280 %{
4281 single_instruction;
4282 dst : S4(write);
4283 src : S3(read);
4284 DECODE : S0; // any decoder
4285 ALU : S3; // any alu
4286 %}
4287
4288 // Long ALU reg-reg operation
4289 pipe_class ialu_reg_reg_long(rRegL dst, rRegL src)
4290 %{
4291 instruction_count(2);
4292 dst : S4(write);
4293 src : S3(read);
4294 DECODE : S0(2); // any 2 decoders
4295 ALU : S3(2); // both alus
4296 %}
4297
4298 // Integer ALU reg-reg operation
4299 pipe_class ialu_reg_reg_fat(rRegI dst, memory src)
4300 %{
4301 single_instruction;
4302 dst : S4(write);
4303 src : S3(read);
4304 D0 : S0; // big decoder only
4305 ALU : S3; // any alu
4306 %}
4307
4308 // Long ALU reg-reg operation
4309 pipe_class ialu_reg_reg_long_fat(rRegL dst, rRegL src)
4310 %{
4311 instruction_count(2);
4312 dst : S4(write);
4313 src : S3(read);
4314 D0 : S0(2); // big decoder only; twice
4315 ALU : S3(2); // both alus
4316 %}
4317
4318 // Integer ALU reg-mem operation
4319 pipe_class ialu_reg_mem(rRegI dst, memory mem)
4320 %{
4321 single_instruction;
4322 dst : S5(write);
4323 mem : S3(read);
4324 D0 : S0; // big decoder only
4325 ALU : S4; // any alu
4326 MEM : S3; // any mem
4327 %}
4328
4329 // Integer mem operation (prefetch)
4330 pipe_class ialu_mem(memory mem)
4331 %{
4332 single_instruction;
4333 mem : S3(read);
4334 D0 : S0; // big decoder only
4335 MEM : S3; // any mem
4336 %}
4337
4338 // Integer Store to Memory
4339 pipe_class ialu_mem_reg(memory mem, rRegI src)
4340 %{
4341 single_instruction;
4342 mem : S3(read);
4343 src : S5(read);
4344 D0 : S0; // big decoder only
4345 ALU : S4; // any alu
4346 MEM : S3;
4347 %}
4348
4349 // // Long Store to Memory
4350 // pipe_class ialu_mem_long_reg(memory mem, rRegL src)
4351 // %{
4352 // instruction_count(2);
4353 // mem : S3(read);
4354 // src : S5(read);
4355 // D0 : S0(2); // big decoder only; twice
4356 // ALU : S4(2); // any 2 alus
4357 // MEM : S3(2); // Both mems
4358 // %}
4359
4360 // Integer Store to Memory
4361 pipe_class ialu_mem_imm(memory mem)
4362 %{
4363 single_instruction;
4364 mem : S3(read);
4365 D0 : S0; // big decoder only
4366 ALU : S4; // any alu
4367 MEM : S3;
4368 %}
4369
4370 // Integer ALU0 reg-reg operation
4371 pipe_class ialu_reg_reg_alu0(rRegI dst, rRegI src)
4372 %{
4373 single_instruction;
4374 dst : S4(write);
4375 src : S3(read);
4376 D0 : S0; // Big decoder only
4377 ALU0 : S3; // only alu0
4378 %}
4379
4380 // Integer ALU0 reg-mem operation
4381 pipe_class ialu_reg_mem_alu0(rRegI dst, memory mem)
4382 %{
4383 single_instruction;
4384 dst : S5(write);
4385 mem : S3(read);
4386 D0 : S0; // big decoder only
4387 ALU0 : S4; // ALU0 only
4388 MEM : S3; // any mem
4389 %}
4390
4391 // Integer ALU reg-reg operation
4392 pipe_class ialu_cr_reg_reg(rFlagsReg cr, rRegI src1, rRegI src2)
4393 %{
4394 single_instruction;
4395 cr : S4(write);
4396 src1 : S3(read);
4397 src2 : S3(read);
4398 DECODE : S0; // any decoder
4399 ALU : S3; // any alu
4400 %}
4401
4402 // Integer ALU reg-imm operation
4403 pipe_class ialu_cr_reg_imm(rFlagsReg cr, rRegI src1)
4404 %{
4405 single_instruction;
4406 cr : S4(write);
4407 src1 : S3(read);
4408 DECODE : S0; // any decoder
4409 ALU : S3; // any alu
4410 %}
4411
4412 // Integer ALU reg-mem operation
4413 pipe_class ialu_cr_reg_mem(rFlagsReg cr, rRegI src1, memory src2)
4414 %{
4415 single_instruction;
4416 cr : S4(write);
4417 src1 : S3(read);
4418 src2 : S3(read);
4419 D0 : S0; // big decoder only
4420 ALU : S4; // any alu
4421 MEM : S3;
4422 %}
4423
4424 // Conditional move reg-reg
4425 pipe_class pipe_cmplt( rRegI p, rRegI q, rRegI y)
4426 %{
4427 instruction_count(4);
4428 y : S4(read);
4429 q : S3(read);
4430 p : S3(read);
4431 DECODE : S0(4); // any decoder
4432 %}
4433
4434 // Conditional move reg-reg
4435 pipe_class pipe_cmov_reg( rRegI dst, rRegI src, rFlagsReg cr)
4436 %{
4437 single_instruction;
4438 dst : S4(write);
4439 src : S3(read);
4440 cr : S3(read);
4441 DECODE : S0; // any decoder
4442 %}
4443
4444 // Conditional move reg-mem
4445 pipe_class pipe_cmov_mem( rFlagsReg cr, rRegI dst, memory src)
4446 %{
4447 single_instruction;
4448 dst : S4(write);
4449 src : S3(read);
4450 cr : S3(read);
4451 DECODE : S0; // any decoder
4452 MEM : S3;
4453 %}
4454
4455 // Conditional move reg-reg long
4456 pipe_class pipe_cmov_reg_long( rFlagsReg cr, rRegL dst, rRegL src)
4457 %{
4458 single_instruction;
4459 dst : S4(write);
4460 src : S3(read);
4461 cr : S3(read);
4462 DECODE : S0(2); // any 2 decoders
4463 %}
4464
4465 // XXX
4466 // // Conditional move double reg-reg
4467 // pipe_class pipe_cmovD_reg( rFlagsReg cr, regDPR1 dst, regD src)
4468 // %{
4469 // single_instruction;
4470 // dst : S4(write);
4471 // src : S3(read);
4472 // cr : S3(read);
4473 // DECODE : S0; // any decoder
4474 // %}
4475
4476 // Float reg-reg operation
4477 pipe_class fpu_reg(regD dst)
4478 %{
4479 instruction_count(2);
4480 dst : S3(read);
4481 DECODE : S0(2); // any 2 decoders
4482 FPU : S3;
4483 %}
4484
4485 // Float reg-reg operation
4486 pipe_class fpu_reg_reg(regD dst, regD src)
4487 %{
4488 instruction_count(2);
4489 dst : S4(write);
4490 src : S3(read);
4491 DECODE : S0(2); // any 2 decoders
4492 FPU : S3;
4493 %}
4494
4495 // Float reg-reg operation
4496 pipe_class fpu_reg_reg_reg(regD dst, regD src1, regD src2)
4497 %{
4498 instruction_count(3);
4499 dst : S4(write);
4500 src1 : S3(read);
4501 src2 : S3(read);
4502 DECODE : S0(3); // any 3 decoders
4503 FPU : S3(2);
4504 %}
4505
4506 // Float reg-reg operation
4507 pipe_class fpu_reg_reg_reg_reg(regD dst, regD src1, regD src2, regD src3)
4508 %{
4509 instruction_count(4);
4510 dst : S4(write);
4511 src1 : S3(read);
4512 src2 : S3(read);
4513 src3 : S3(read);
4514 DECODE : S0(4); // any 3 decoders
4515 FPU : S3(2);
4516 %}
4517
4518 // Float reg-reg operation
4519 pipe_class fpu_reg_mem_reg_reg(regD dst, memory src1, regD src2, regD src3)
4520 %{
4521 instruction_count(4);
4522 dst : S4(write);
4523 src1 : S3(read);
4524 src2 : S3(read);
4525 src3 : S3(read);
4526 DECODE : S1(3); // any 3 decoders
4527 D0 : S0; // Big decoder only
4528 FPU : S3(2);
4529 MEM : S3;
4530 %}
4531
4532 // Float reg-mem operation
4533 pipe_class fpu_reg_mem(regD dst, memory mem)
4534 %{
4535 instruction_count(2);
4536 dst : S5(write);
4537 mem : S3(read);
4538 D0 : S0; // big decoder only
4539 DECODE : S1; // any decoder for FPU POP
4540 FPU : S4;
4541 MEM : S3; // any mem
4542 %}
4543
4544 // Float reg-mem operation
4545 pipe_class fpu_reg_reg_mem(regD dst, regD src1, memory mem)
4546 %{
4547 instruction_count(3);
4548 dst : S5(write);
4549 src1 : S3(read);
4550 mem : S3(read);
4551 D0 : S0; // big decoder only
4552 DECODE : S1(2); // any decoder for FPU POP
4553 FPU : S4;
4554 MEM : S3; // any mem
4555 %}
4556
4557 // Float mem-reg operation
4558 pipe_class fpu_mem_reg(memory mem, regD src)
4559 %{
4560 instruction_count(2);
4561 src : S5(read);
4562 mem : S3(read);
4563 DECODE : S0; // any decoder for FPU PUSH
4564 D0 : S1; // big decoder only
4565 FPU : S4;
4566 MEM : S3; // any mem
4567 %}
4568
4569 pipe_class fpu_mem_reg_reg(memory mem, regD src1, regD src2)
4570 %{
4571 instruction_count(3);
4572 src1 : S3(read);
4573 src2 : S3(read);
4574 mem : S3(read);
4575 DECODE : S0(2); // any decoder for FPU PUSH
4576 D0 : S1; // big decoder only
4577 FPU : S4;
4578 MEM : S3; // any mem
4579 %}
4580
4581 pipe_class fpu_mem_reg_mem(memory mem, regD src1, memory src2)
4582 %{
4583 instruction_count(3);
4584 src1 : S3(read);
4585 src2 : S3(read);
4586 mem : S4(read);
4587 DECODE : S0; // any decoder for FPU PUSH
4588 D0 : S0(2); // big decoder only
4589 FPU : S4;
4590 MEM : S3(2); // any mem
4591 %}
4592
4593 pipe_class fpu_mem_mem(memory dst, memory src1)
4594 %{
4595 instruction_count(2);
4596 src1 : S3(read);
4597 dst : S4(read);
4598 D0 : S0(2); // big decoder only
4599 MEM : S3(2); // any mem
4600 %}
4601
4602 pipe_class fpu_mem_mem_mem(memory dst, memory src1, memory src2)
4603 %{
4604 instruction_count(3);
4605 src1 : S3(read);
4606 src2 : S3(read);
4607 dst : S4(read);
4608 D0 : S0(3); // big decoder only
4609 FPU : S4;
4610 MEM : S3(3); // any mem
4611 %}
4612
4613 pipe_class fpu_mem_reg_con(memory mem, regD src1)
4614 %{
4615 instruction_count(3);
4616 src1 : S4(read);
4617 mem : S4(read);
4618 DECODE : S0; // any decoder for FPU PUSH
4619 D0 : S0(2); // big decoder only
4620 FPU : S4;
4621 MEM : S3(2); // any mem
4622 %}
4623
4624 // Float load constant
4625 pipe_class fpu_reg_con(regD dst)
4626 %{
4627 instruction_count(2);
4628 dst : S5(write);
4629 D0 : S0; // big decoder only for the load
4630 DECODE : S1; // any decoder for FPU POP
4631 FPU : S4;
4632 MEM : S3; // any mem
4633 %}
4634
4635 // Float load constant
4636 pipe_class fpu_reg_reg_con(regD dst, regD src)
4637 %{
4638 instruction_count(3);
4639 dst : S5(write);
4640 src : S3(read);
4641 D0 : S0; // big decoder only for the load
4642 DECODE : S1(2); // any decoder for FPU POP
4643 FPU : S4;
4644 MEM : S3; // any mem
4645 %}
4646
4647 // UnConditional branch
4648 pipe_class pipe_jmp(label labl)
4649 %{
4650 single_instruction;
4651 BR : S3;
4652 %}
4653
4654 // Conditional branch
4655 pipe_class pipe_jcc(cmpOp cmp, rFlagsReg cr, label labl)
4656 %{
4657 single_instruction;
4658 cr : S1(read);
4659 BR : S3;
4660 %}
4661
4662 // Allocation idiom
4663 pipe_class pipe_cmpxchg(rRegP dst, rRegP heap_ptr)
4664 %{
4665 instruction_count(1); force_serialization;
4666 fixed_latency(6);
4667 heap_ptr : S3(read);
4668 DECODE : S0(3);
4669 D0 : S2;
4670 MEM : S3;
4671 ALU : S3(2);
4672 dst : S5(write);
4673 BR : S5;
4674 %}
4675
4676 // Generic big/slow expanded idiom
4677 pipe_class pipe_slow()
4678 %{
4679 instruction_count(10); multiple_bundles; force_serialization;
4680 fixed_latency(100);
4681 D0 : S0(2);
4682 MEM : S3(2);
4683 %}
4684
4685 // The real do-nothing guy
4686 pipe_class empty()
4687 %{
4688 instruction_count(0);
4689 %}
4690
4691 // Define the class for the Nop node
4692 define
4693 %{
4694 MachNop = empty;
4695 %}
4696
4697 %}
4698
4699 //----------INSTRUCTIONS-------------------------------------------------------
4700 //
4701 // match -- States which machine-independent subtree may be replaced
4702 // by this instruction.
4703 // ins_cost -- The estimated cost of this instruction is used by instruction
4704 // selection to identify a minimum cost tree of machine
4705 // instructions that matches a tree of machine-independent
4706 // instructions.
4707 // format -- A string providing the disassembly for this instruction.
4708 // The value of an instruction's operand may be inserted
4709 // by referring to it with a '$' prefix.
4710 // opcode -- Three instruction opcodes may be provided. These are referred
4711 // to within an encode class as $primary, $secondary, and $tertiary
4712 // rrspectively. The primary opcode is commonly used to
4713 // indicate the type of machine instruction, while secondary
4714 // and tertiary are often used for prefix options or addressing
4715 // modes.
4716 // ins_encode -- A list of encode classes with parameters. The encode class
4717 // name must have been defined in an 'enc_class' specification
4718 // in the encode section of the architecture description.
4719
4720
4721 //----------Load/Store/Move Instructions---------------------------------------
4722 //----------Load Instructions--------------------------------------------------
4723
4724 // Load Byte (8 bit signed)
4725 instruct loadB(rRegI dst, memory mem)
4726 %{
4727 match(Set dst (LoadB mem));
4728
4729 ins_cost(125);
4730 format %{ "movsbl $dst, $mem\t# byte" %}
4731
4732 ins_encode %{
4733 __ movsbl($dst$$Register, $mem$$Address);
4734 %}
4735
4736 ins_pipe(ialu_reg_mem);
4737 %}
4738
4739 // Load Byte (8 bit signed) into Long Register
4740 instruct loadB2L(rRegL dst, memory mem)
4741 %{
4742 match(Set dst (ConvI2L (LoadB mem)));
4743
4744 ins_cost(125);
4745 format %{ "movsbq $dst, $mem\t# byte -> long" %}
4746
4747 ins_encode %{
4748 __ movsbq($dst$$Register, $mem$$Address);
4749 %}
4750
4751 ins_pipe(ialu_reg_mem);
4752 %}
4753
4754 // Load Unsigned Byte (8 bit UNsigned)
4755 instruct loadUB(rRegI dst, memory mem)
4756 %{
4757 match(Set dst (LoadUB mem));
4758
4759 ins_cost(125);
4760 format %{ "movzbl $dst, $mem\t# ubyte" %}
4761
4762 ins_encode %{
4763 __ movzbl($dst$$Register, $mem$$Address);
4764 %}
4765
4766 ins_pipe(ialu_reg_mem);
4767 %}
4768
4769 // Load Unsigned Byte (8 bit UNsigned) into Long Register
4770 instruct loadUB2L(rRegL dst, memory mem)
4771 %{
4772 match(Set dst (ConvI2L (LoadUB mem)));
4773
4774 ins_cost(125);
4775 format %{ "movzbq $dst, $mem\t# ubyte -> long" %}
4776
4777 ins_encode %{
4778 __ movzbq($dst$$Register, $mem$$Address);
4779 %}
4780
4781 ins_pipe(ialu_reg_mem);
4782 %}
4783
4784 // Load Unsigned Byte (8 bit UNsigned) with 32-bit mask into Long Register
4785 instruct loadUB2L_immI(rRegL dst, memory mem, immI mask, rFlagsReg cr) %{
4786 match(Set dst (ConvI2L (AndI (LoadUB mem) mask)));
4787 effect(KILL cr);
4788
4789 format %{ "movzbq $dst, $mem\t# ubyte & 32-bit mask -> long\n\t"
4790 "andl $dst, right_n_bits($mask, 8)" %}
4791 ins_encode %{
4792 Register Rdst = $dst$$Register;
4793 __ movzbq(Rdst, $mem$$Address);
4794 __ andl(Rdst, $mask$$constant & right_n_bits(8));
4795 %}
4796 ins_pipe(ialu_reg_mem);
4797 %}
4798
4799 // Load Short (16 bit signed)
4800 instruct loadS(rRegI dst, memory mem)
4801 %{
4802 match(Set dst (LoadS mem));
4803
4804 ins_cost(125);
4805 format %{ "movswl $dst, $mem\t# short" %}
4806
4807 ins_encode %{
4808 __ movswl($dst$$Register, $mem$$Address);
4809 %}
4810
4811 ins_pipe(ialu_reg_mem);
4812 %}
4813
4814 // Load Short (16 bit signed) to Byte (8 bit signed)
4815 instruct loadS2B(rRegI dst, memory mem, immI_24 twentyfour) %{
4816 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour));
4817
4818 ins_cost(125);
4819 format %{ "movsbl $dst, $mem\t# short -> byte" %}
4820 ins_encode %{
4821 __ movsbl($dst$$Register, $mem$$Address);
4822 %}
4823 ins_pipe(ialu_reg_mem);
4824 %}
4825
4826 // Load Short (16 bit signed) into Long Register
4827 instruct loadS2L(rRegL dst, memory mem)
4828 %{
4829 match(Set dst (ConvI2L (LoadS mem)));
4830
4831 ins_cost(125);
4832 format %{ "movswq $dst, $mem\t# short -> long" %}
4833
4834 ins_encode %{
4835 __ movswq($dst$$Register, $mem$$Address);
4836 %}
4837
4838 ins_pipe(ialu_reg_mem);
4839 %}
4840
4841 // Load Unsigned Short/Char (16 bit UNsigned)
4842 instruct loadUS(rRegI dst, memory mem)
4843 %{
4844 match(Set dst (LoadUS mem));
4845
4846 ins_cost(125);
4847 format %{ "movzwl $dst, $mem\t# ushort/char" %}
4848
4849 ins_encode %{
4850 __ movzwl($dst$$Register, $mem$$Address);
4851 %}
4852
4853 ins_pipe(ialu_reg_mem);
4854 %}
4855
4856 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed)
4857 instruct loadUS2B(rRegI dst, memory mem, immI_24 twentyfour) %{
4858 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour));
4859
4860 ins_cost(125);
4861 format %{ "movsbl $dst, $mem\t# ushort -> byte" %}
4862 ins_encode %{
4863 __ movsbl($dst$$Register, $mem$$Address);
4864 %}
4865 ins_pipe(ialu_reg_mem);
4866 %}
4867
4868 // Load Unsigned Short/Char (16 bit UNsigned) into Long Register
4869 instruct loadUS2L(rRegL dst, memory mem)
4870 %{
4871 match(Set dst (ConvI2L (LoadUS mem)));
4872
4873 ins_cost(125);
4874 format %{ "movzwq $dst, $mem\t# ushort/char -> long" %}
4875
4876 ins_encode %{
4877 __ movzwq($dst$$Register, $mem$$Address);
4878 %}
4879
4880 ins_pipe(ialu_reg_mem);
4881 %}
4882
4883 // Load Unsigned Short/Char (16 bit UNsigned) with mask 0xFF into Long Register
4884 instruct loadUS2L_immI_255(rRegL dst, memory mem, immI_255 mask) %{
4885 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
4886
4887 format %{ "movzbq $dst, $mem\t# ushort/char & 0xFF -> long" %}
4888 ins_encode %{
4889 __ movzbq($dst$$Register, $mem$$Address);
4890 %}
4891 ins_pipe(ialu_reg_mem);
4892 %}
4893
4894 // Load Unsigned Short/Char (16 bit UNsigned) with 32-bit mask into Long Register
4895 instruct loadUS2L_immI(rRegL dst, memory mem, immI mask, rFlagsReg cr) %{
4896 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
4897 effect(KILL cr);
4898
4899 format %{ "movzwq $dst, $mem\t# ushort/char & 32-bit mask -> long\n\t"
4900 "andl $dst, right_n_bits($mask, 16)" %}
4901 ins_encode %{
4902 Register Rdst = $dst$$Register;
4903 __ movzwq(Rdst, $mem$$Address);
4904 __ andl(Rdst, $mask$$constant & right_n_bits(16));
4905 %}
4906 ins_pipe(ialu_reg_mem);
4907 %}
4908
4909 // Load Integer
4910 instruct loadI(rRegI dst, memory mem)
4911 %{
4912 match(Set dst (LoadI mem));
4913
4914 ins_cost(125);
4915 format %{ "movl $dst, $mem\t# int" %}
4916
4917 ins_encode %{
4918 __ movl($dst$$Register, $mem$$Address);
4919 %}
4920
4921 ins_pipe(ialu_reg_mem);
4922 %}
4923
4924 // Load Integer (32 bit signed) to Byte (8 bit signed)
4925 instruct loadI2B(rRegI dst, memory mem, immI_24 twentyfour) %{
4926 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour));
4927
4928 ins_cost(125);
4929 format %{ "movsbl $dst, $mem\t# int -> byte" %}
4930 ins_encode %{
4931 __ movsbl($dst$$Register, $mem$$Address);
4932 %}
4933 ins_pipe(ialu_reg_mem);
4934 %}
4935
4936 // Load Integer (32 bit signed) to Unsigned Byte (8 bit UNsigned)
4937 instruct loadI2UB(rRegI dst, memory mem, immI_255 mask) %{
4938 match(Set dst (AndI (LoadI mem) mask));
4939
4940 ins_cost(125);
4941 format %{ "movzbl $dst, $mem\t# int -> ubyte" %}
4942 ins_encode %{
4943 __ movzbl($dst$$Register, $mem$$Address);
4944 %}
4945 ins_pipe(ialu_reg_mem);
4946 %}
4947
4948 // Load Integer (32 bit signed) to Short (16 bit signed)
4949 instruct loadI2S(rRegI dst, memory mem, immI_16 sixteen) %{
4950 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen));
4951
4952 ins_cost(125);
4953 format %{ "movswl $dst, $mem\t# int -> short" %}
4954 ins_encode %{
4955 __ movswl($dst$$Register, $mem$$Address);
4956 %}
4957 ins_pipe(ialu_reg_mem);
4958 %}
4959
4960 // Load Integer (32 bit signed) to Unsigned Short/Char (16 bit UNsigned)
4961 instruct loadI2US(rRegI dst, memory mem, immI_65535 mask) %{
4962 match(Set dst (AndI (LoadI mem) mask));
4963
4964 ins_cost(125);
4965 format %{ "movzwl $dst, $mem\t# int -> ushort/char" %}
4966 ins_encode %{
4967 __ movzwl($dst$$Register, $mem$$Address);
4968 %}
4969 ins_pipe(ialu_reg_mem);
4970 %}
4971
4972 // Load Integer into Long Register
4973 instruct loadI2L(rRegL dst, memory mem)
4974 %{
4975 match(Set dst (ConvI2L (LoadI mem)));
4976
4977 ins_cost(125);
4978 format %{ "movslq $dst, $mem\t# int -> long" %}
4979
4980 ins_encode %{
4981 __ movslq($dst$$Register, $mem$$Address);
4982 %}
4983
4984 ins_pipe(ialu_reg_mem);
4985 %}
4986
4987 // Load Integer with mask 0xFF into Long Register
4988 instruct loadI2L_immI_255(rRegL dst, memory mem, immI_255 mask) %{
4989 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
4990
4991 format %{ "movzbq $dst, $mem\t# int & 0xFF -> long" %}
4992 ins_encode %{
4993 __ movzbq($dst$$Register, $mem$$Address);
4994 %}
4995 ins_pipe(ialu_reg_mem);
4996 %}
4997
4998 // Load Integer with mask 0xFFFF into Long Register
4999 instruct loadI2L_immI_65535(rRegL dst, memory mem, immI_65535 mask) %{
5000 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5001
5002 format %{ "movzwq $dst, $mem\t# int & 0xFFFF -> long" %}
5003 ins_encode %{
5004 __ movzwq($dst$$Register, $mem$$Address);
5005 %}
5006 ins_pipe(ialu_reg_mem);
5007 %}
5008
5009 // Load Integer with a 31-bit mask into Long Register
5010 instruct loadI2L_immU31(rRegL dst, memory mem, immU31 mask, rFlagsReg cr) %{
5011 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5012 effect(KILL cr);
5013
5014 format %{ "movl $dst, $mem\t# int & 31-bit mask -> long\n\t"
5015 "andl $dst, $mask" %}
5016 ins_encode %{
5017 Register Rdst = $dst$$Register;
5018 __ movl(Rdst, $mem$$Address);
5019 __ andl(Rdst, $mask$$constant);
5020 %}
5021 ins_pipe(ialu_reg_mem);
5022 %}
5023
5024 // Load Unsigned Integer into Long Register
5025 instruct loadUI2L(rRegL dst, memory mem, immL_32bits mask)
5026 %{
5027 match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
5028
5029 ins_cost(125);
5030 format %{ "movl $dst, $mem\t# uint -> long" %}
5031
5032 ins_encode %{
5033 __ movl($dst$$Register, $mem$$Address);
5034 %}
5035
5036 ins_pipe(ialu_reg_mem);
5037 %}
5038
5039 // Load Long
5040 instruct loadL(rRegL dst, memory mem)
5041 %{
5042 match(Set dst (LoadL mem));
5043
5044 ins_cost(125);
5045 format %{ "movq $dst, $mem\t# long" %}
5046
5047 ins_encode %{
5048 __ movq($dst$$Register, $mem$$Address);
5049 %}
5050
5051 ins_pipe(ialu_reg_mem); // XXX
5052 %}
5053
5054 // Load Range
5055 instruct loadRange(rRegI dst, memory mem)
5056 %{
5057 match(Set dst (LoadRange mem));
5058
5059 ins_cost(125); // XXX
5060 format %{ "movl $dst, $mem\t# range" %}
5061 opcode(0x8B);
5062 ins_encode(REX_reg_mem(dst, mem), OpcP, reg_mem(dst, mem));
5063 ins_pipe(ialu_reg_mem);
5064 %}
5065
5066 // Load Pointer
5067 instruct loadP(rRegP dst, memory mem)
5068 %{
5069 match(Set dst (LoadP mem));
5070
5071 ins_cost(125); // XXX
5072 format %{ "movq $dst, $mem\t# ptr" %}
5073 opcode(0x8B);
5074 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5075 ins_pipe(ialu_reg_mem); // XXX
5076 %}
5077
5078 // Load Compressed Pointer
5079 instruct loadN(rRegN dst, memory mem)
5080 %{
5081 match(Set dst (LoadN mem));
5082
5083 ins_cost(125); // XXX
5084 format %{ "movl $dst, $mem\t# compressed ptr" %}
5085 ins_encode %{
5086 __ movl($dst$$Register, $mem$$Address);
5087 %}
5088 ins_pipe(ialu_reg_mem); // XXX
5089 %}
5090
5091
5092 // Load Klass Pointer
5093 instruct loadKlass(rRegP dst, memory mem)
5094 %{
5095 match(Set dst (LoadKlass mem));
5096
5097 ins_cost(125); // XXX
5098 format %{ "movq $dst, $mem\t# class" %}
5099 opcode(0x8B);
5100 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5101 ins_pipe(ialu_reg_mem); // XXX
5102 %}
5103
5104 // Load narrow Klass Pointer
5105 instruct loadNKlass(rRegN dst, memory mem)
5106 %{
5107 match(Set dst (LoadNKlass mem));
5108
5109 ins_cost(125); // XXX
5110 format %{ "movl $dst, $mem\t# compressed klass ptr" %}
5111 ins_encode %{
5112 __ movl($dst$$Register, $mem$$Address);
5113 %}
5114 ins_pipe(ialu_reg_mem); // XXX
5115 %}
5116
5117 // Load Float
5118 instruct loadF(regF dst, memory mem)
5119 %{
5120 match(Set dst (LoadF mem));
5121
5122 ins_cost(145); // XXX
5123 format %{ "movss $dst, $mem\t# float" %}
5124 ins_encode %{
5125 __ movflt($dst$$XMMRegister, $mem$$Address);
5126 %}
5127 ins_pipe(pipe_slow); // XXX
5128 %}
5129
5130 // Load Double
5131 instruct loadD_partial(regD dst, memory mem)
5132 %{
5133 predicate(!UseXmmLoadAndClearUpper);
5134 match(Set dst (LoadD mem));
5135
5136 ins_cost(145); // XXX
5137 format %{ "movlpd $dst, $mem\t# double" %}
5138 ins_encode %{
5139 __ movdbl($dst$$XMMRegister, $mem$$Address);
5140 %}
5141 ins_pipe(pipe_slow); // XXX
5142 %}
5143
5144 instruct loadD(regD dst, memory mem)
5145 %{
5146 predicate(UseXmmLoadAndClearUpper);
5147 match(Set dst (LoadD mem));
5148
5149 ins_cost(145); // XXX
5150 format %{ "movsd $dst, $mem\t# double" %}
5151 ins_encode %{
5152 __ movdbl($dst$$XMMRegister, $mem$$Address);
5153 %}
5154 ins_pipe(pipe_slow); // XXX
5155 %}
5156
5157 // Load Effective Address
5158 instruct leaP8(rRegP dst, indOffset8 mem)
5159 %{
5160 match(Set dst mem);
5161
5162 ins_cost(110); // XXX
5163 format %{ "leaq $dst, $mem\t# ptr 8" %}
5164 opcode(0x8D);
5165 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5166 ins_pipe(ialu_reg_reg_fat);
5167 %}
5168
5169 instruct leaP32(rRegP dst, indOffset32 mem)
5170 %{
5171 match(Set dst mem);
5172
5173 ins_cost(110);
5174 format %{ "leaq $dst, $mem\t# ptr 32" %}
5175 opcode(0x8D);
5176 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5177 ins_pipe(ialu_reg_reg_fat);
5178 %}
5179
5180 // instruct leaPIdx(rRegP dst, indIndex mem)
5181 // %{
5182 // match(Set dst mem);
5183
5184 // ins_cost(110);
5185 // format %{ "leaq $dst, $mem\t# ptr idx" %}
5186 // opcode(0x8D);
5187 // ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5188 // ins_pipe(ialu_reg_reg_fat);
5189 // %}
5190
5191 instruct leaPIdxOff(rRegP dst, indIndexOffset mem)
5192 %{
5193 match(Set dst mem);
5194
5195 ins_cost(110);
5196 format %{ "leaq $dst, $mem\t# ptr idxoff" %}
5197 opcode(0x8D);
5198 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5199 ins_pipe(ialu_reg_reg_fat);
5200 %}
5201
5202 instruct leaPIdxScale(rRegP dst, indIndexScale mem)
5203 %{
5204 match(Set dst mem);
5205
5206 ins_cost(110);
5207 format %{ "leaq $dst, $mem\t# ptr idxscale" %}
5208 opcode(0x8D);
5209 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5210 ins_pipe(ialu_reg_reg_fat);
5211 %}
5212
5213 instruct leaPPosIdxScale(rRegP dst, indPosIndexScale mem)
5214 %{
5215 match(Set dst mem);
5216
5217 ins_cost(110);
5218 format %{ "leaq $dst, $mem\t# ptr idxscale" %}
5219 opcode(0x8D);
5220 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5221 ins_pipe(ialu_reg_reg_fat);
5222 %}
5223
5224 instruct leaPIdxScaleOff(rRegP dst, indIndexScaleOffset mem)
5225 %{
5226 match(Set dst mem);
5227
5228 ins_cost(110);
5229 format %{ "leaq $dst, $mem\t# ptr idxscaleoff" %}
5230 opcode(0x8D);
5231 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5232 ins_pipe(ialu_reg_reg_fat);
5233 %}
5234
5235 instruct leaPPosIdxOff(rRegP dst, indPosIndexOffset mem)
5236 %{
5237 match(Set dst mem);
5238
5239 ins_cost(110);
5240 format %{ "leaq $dst, $mem\t# ptr posidxoff" %}
5241 opcode(0x8D);
5242 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5243 ins_pipe(ialu_reg_reg_fat);
5244 %}
5245
5246 instruct leaPPosIdxScaleOff(rRegP dst, indPosIndexScaleOffset mem)
5247 %{
5248 match(Set dst mem);
5249
5250 ins_cost(110);
5251 format %{ "leaq $dst, $mem\t# ptr posidxscaleoff" %}
5252 opcode(0x8D);
5253 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5254 ins_pipe(ialu_reg_reg_fat);
5255 %}
5256
5257 // Load Effective Address which uses Narrow (32-bits) oop
5258 instruct leaPCompressedOopOffset(rRegP dst, indCompressedOopOffset mem)
5259 %{
5260 predicate(UseCompressedOops && (Universe::narrow_oop_shift() != 0));
5261 match(Set dst mem);
5262
5263 ins_cost(110);
5264 format %{ "leaq $dst, $mem\t# ptr compressedoopoff32" %}
5265 opcode(0x8D);
5266 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5267 ins_pipe(ialu_reg_reg_fat);
5268 %}
5269
5270 instruct leaP8Narrow(rRegP dst, indOffset8Narrow mem)
5271 %{
5272 predicate(Universe::narrow_oop_shift() == 0);
5273 match(Set dst mem);
5274
5275 ins_cost(110); // XXX
5276 format %{ "leaq $dst, $mem\t# ptr off8narrow" %}
5277 opcode(0x8D);
5278 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5279 ins_pipe(ialu_reg_reg_fat);
5280 %}
5281
5282 instruct leaP32Narrow(rRegP dst, indOffset32Narrow mem)
5283 %{
5284 predicate(Universe::narrow_oop_shift() == 0);
5285 match(Set dst mem);
5286
5287 ins_cost(110);
5288 format %{ "leaq $dst, $mem\t# ptr off32narrow" %}
5289 opcode(0x8D);
5290 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5291 ins_pipe(ialu_reg_reg_fat);
5292 %}
5293
5294 instruct leaPIdxOffNarrow(rRegP dst, indIndexOffsetNarrow mem)
5295 %{
5296 predicate(Universe::narrow_oop_shift() == 0);
5297 match(Set dst mem);
5298
5299 ins_cost(110);
5300 format %{ "leaq $dst, $mem\t# ptr idxoffnarrow" %}
5301 opcode(0x8D);
5302 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5303 ins_pipe(ialu_reg_reg_fat);
5304 %}
5305
5306 instruct leaPIdxScaleNarrow(rRegP dst, indIndexScaleNarrow mem)
5307 %{
5308 predicate(Universe::narrow_oop_shift() == 0);
5309 match(Set dst mem);
5310
5311 ins_cost(110);
5312 format %{ "leaq $dst, $mem\t# ptr idxscalenarrow" %}
5313 opcode(0x8D);
5314 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5315 ins_pipe(ialu_reg_reg_fat);
5316 %}
5317
5318 instruct leaPIdxScaleOffNarrow(rRegP dst, indIndexScaleOffsetNarrow mem)
5319 %{
5320 predicate(Universe::narrow_oop_shift() == 0);
5321 match(Set dst mem);
5322
5323 ins_cost(110);
5324 format %{ "leaq $dst, $mem\t# ptr idxscaleoffnarrow" %}
5325 opcode(0x8D);
5326 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5327 ins_pipe(ialu_reg_reg_fat);
5328 %}
5329
5330 instruct leaPPosIdxOffNarrow(rRegP dst, indPosIndexOffsetNarrow mem)
5331 %{
5332 predicate(Universe::narrow_oop_shift() == 0);
5333 match(Set dst mem);
5334
5335 ins_cost(110);
5336 format %{ "leaq $dst, $mem\t# ptr posidxoffnarrow" %}
5337 opcode(0x8D);
5338 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5339 ins_pipe(ialu_reg_reg_fat);
5340 %}
5341
5342 instruct leaPPosIdxScaleOffNarrow(rRegP dst, indPosIndexScaleOffsetNarrow mem)
5343 %{
5344 predicate(Universe::narrow_oop_shift() == 0);
5345 match(Set dst mem);
5346
5347 ins_cost(110);
5348 format %{ "leaq $dst, $mem\t# ptr posidxscaleoffnarrow" %}
5349 opcode(0x8D);
5350 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5351 ins_pipe(ialu_reg_reg_fat);
5352 %}
5353
5354 instruct loadConI(rRegI dst, immI src)
5355 %{
5356 match(Set dst src);
5357
5358 format %{ "movl $dst, $src\t# int" %}
5359 ins_encode(load_immI(dst, src));
5360 ins_pipe(ialu_reg_fat); // XXX
5361 %}
5362
5363 instruct loadConI0(rRegI dst, immI0 src, rFlagsReg cr)
5364 %{
5365 match(Set dst src);
5366 effect(KILL cr);
5367
5368 ins_cost(50);
5369 format %{ "xorl $dst, $dst\t# int" %}
5370 opcode(0x33); /* + rd */
5371 ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst));
5372 ins_pipe(ialu_reg);
5373 %}
5374
5375 instruct loadConL(rRegL dst, immL src)
5376 %{
5377 match(Set dst src);
5378
5379 ins_cost(150);
5380 format %{ "movq $dst, $src\t# long" %}
5381 ins_encode(load_immL(dst, src));
5382 ins_pipe(ialu_reg);
5383 %}
5384
5385 instruct loadConL0(rRegL dst, immL0 src, rFlagsReg cr)
5386 %{
5387 match(Set dst src);
5388 effect(KILL cr);
5389
5390 ins_cost(50);
5391 format %{ "xorl $dst, $dst\t# long" %}
5392 opcode(0x33); /* + rd */
5393 ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst));
5394 ins_pipe(ialu_reg); // XXX
5395 %}
5396
5397 instruct loadConUL32(rRegL dst, immUL32 src)
5398 %{
5399 match(Set dst src);
5400
5401 ins_cost(60);
5402 format %{ "movl $dst, $src\t# long (unsigned 32-bit)" %}
5403 ins_encode(load_immUL32(dst, src));
5404 ins_pipe(ialu_reg);
5405 %}
5406
5407 instruct loadConL32(rRegL dst, immL32 src)
5408 %{
5409 match(Set dst src);
5410
5411 ins_cost(70);
5412 format %{ "movq $dst, $src\t# long (32-bit)" %}
5413 ins_encode(load_immL32(dst, src));
5414 ins_pipe(ialu_reg);
5415 %}
5416
5417 instruct loadConP(rRegP dst, immP con) %{
5418 match(Set dst con);
5419
5420 format %{ "movq $dst, $con\t# ptr" %}
5421 ins_encode(load_immP(dst, con));
5422 ins_pipe(ialu_reg_fat); // XXX
5423 %}
5424
5425 instruct loadConP0(rRegP dst, immP0 src, rFlagsReg cr)
5426 %{
5427 match(Set dst src);
5428 effect(KILL cr);
5429
5430 ins_cost(50);
5431 format %{ "xorl $dst, $dst\t# ptr" %}
5432 opcode(0x33); /* + rd */
5433 ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst));
5434 ins_pipe(ialu_reg);
5435 %}
5436
5437 instruct loadConP31(rRegP dst, immP31 src, rFlagsReg cr)
5438 %{
5439 match(Set dst src);
5440 effect(KILL cr);
5441
5442 ins_cost(60);
5443 format %{ "movl $dst, $src\t# ptr (positive 32-bit)" %}
5444 ins_encode(load_immP31(dst, src));
5445 ins_pipe(ialu_reg);
5446 %}
5447
5448 instruct loadConF(regF dst, immF con) %{
5449 match(Set dst con);
5450 ins_cost(125);
5451 format %{ "movss $dst, [$constantaddress]\t# load from constant table: float=$con" %}
5452 ins_encode %{
5453 __ movflt($dst$$XMMRegister, $constantaddress($con));
5454 %}
5455 ins_pipe(pipe_slow);
5456 %}
5457
5458 instruct loadConN0(rRegN dst, immN0 src, rFlagsReg cr) %{
5459 match(Set dst src);
5460 effect(KILL cr);
5461 format %{ "xorq $dst, $src\t# compressed NULL ptr" %}
5462 ins_encode %{
5463 __ xorq($dst$$Register, $dst$$Register);
5464 %}
5465 ins_pipe(ialu_reg);
5466 %}
5467
5468 instruct loadConN(rRegN dst, immN src) %{
5469 match(Set dst src);
5470
5471 ins_cost(125);
5472 format %{ "movl $dst, $src\t# compressed ptr" %}
5473 ins_encode %{
5474 address con = (address)$src$$constant;
5475 if (con == NULL) {
5476 ShouldNotReachHere();
5477 } else {
5478 __ set_narrow_oop($dst$$Register, (jobject)$src$$constant);
5479 }
5480 %}
5481 ins_pipe(ialu_reg_fat); // XXX
5482 %}
5483
5484 instruct loadConNKlass(rRegN dst, immNKlass src) %{
5485 match(Set dst src);
5486
5487 ins_cost(125);
5488 format %{ "movl $dst, $src\t# compressed klass ptr" %}
5489 ins_encode %{
5490 address con = (address)$src$$constant;
5491 if (con == NULL) {
5492 ShouldNotReachHere();
5493 } else {
5494 __ set_narrow_klass($dst$$Register, (Klass*)$src$$constant);
5495 }
5496 %}
5497 ins_pipe(ialu_reg_fat); // XXX
5498 %}
5499
5500 instruct loadConF0(regF dst, immF0 src)
5501 %{
5502 match(Set dst src);
5503 ins_cost(100);
5504
5505 format %{ "xorps $dst, $dst\t# float 0.0" %}
5506 ins_encode %{
5507 __ xorps($dst$$XMMRegister, $dst$$XMMRegister);
5508 %}
5509 ins_pipe(pipe_slow);
5510 %}
5511
5512 // Use the same format since predicate() can not be used here.
5513 instruct loadConD(regD dst, immD con) %{
5514 match(Set dst con);
5515 ins_cost(125);
5516 format %{ "movsd $dst, [$constantaddress]\t# load from constant table: double=$con" %}
5517 ins_encode %{
5518 __ movdbl($dst$$XMMRegister, $constantaddress($con));
5519 %}
5520 ins_pipe(pipe_slow);
5521 %}
5522
5523 instruct loadConD0(regD dst, immD0 src)
5524 %{
5525 match(Set dst src);
5526 ins_cost(100);
5527
5528 format %{ "xorpd $dst, $dst\t# double 0.0" %}
5529 ins_encode %{
5530 __ xorpd ($dst$$XMMRegister, $dst$$XMMRegister);
5531 %}
5532 ins_pipe(pipe_slow);
5533 %}
5534
5535 instruct loadSSI(rRegI dst, stackSlotI src)
5536 %{
5537 match(Set dst src);
5538
5539 ins_cost(125);
5540 format %{ "movl $dst, $src\t# int stk" %}
5541 opcode(0x8B);
5542 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
5543 ins_pipe(ialu_reg_mem);
5544 %}
5545
5546 instruct loadSSL(rRegL dst, stackSlotL src)
5547 %{
5548 match(Set dst src);
5549
5550 ins_cost(125);
5551 format %{ "movq $dst, $src\t# long stk" %}
5552 opcode(0x8B);
5553 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
5554 ins_pipe(ialu_reg_mem);
5555 %}
5556
5557 instruct loadSSP(rRegP dst, stackSlotP src)
5558 %{
5559 match(Set dst src);
5560
5561 ins_cost(125);
5562 format %{ "movq $dst, $src\t# ptr stk" %}
5563 opcode(0x8B);
5564 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
5565 ins_pipe(ialu_reg_mem);
5566 %}
5567
5568 instruct loadSSF(regF dst, stackSlotF src)
5569 %{
5570 match(Set dst src);
5571
5572 ins_cost(125);
5573 format %{ "movss $dst, $src\t# float stk" %}
5574 ins_encode %{
5575 __ movflt($dst$$XMMRegister, Address(rsp, $src$$disp));
5576 %}
5577 ins_pipe(pipe_slow); // XXX
5578 %}
5579
5580 // Use the same format since predicate() can not be used here.
5581 instruct loadSSD(regD dst, stackSlotD src)
5582 %{
5583 match(Set dst src);
5584
5585 ins_cost(125);
5586 format %{ "movsd $dst, $src\t# double stk" %}
5587 ins_encode %{
5588 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
5589 %}
5590 ins_pipe(pipe_slow); // XXX
5591 %}
5592
5593 // Prefetch instructions for allocation.
5594 // Must be safe to execute with invalid address (cannot fault).
5595
5596 instruct prefetchAlloc( memory mem ) %{
5597 predicate(AllocatePrefetchInstr==3);
5598 match(PrefetchAllocation mem);
5599 ins_cost(125);
5600
5601 format %{ "PREFETCHW $mem\t# Prefetch allocation into level 1 cache and mark modified" %}
5602 ins_encode %{
5603 __ prefetchw($mem$$Address);
5604 %}
5605 ins_pipe(ialu_mem);
5606 %}
5607
5608 instruct prefetchAllocNTA( memory mem ) %{
5609 predicate(AllocatePrefetchInstr==0);
5610 match(PrefetchAllocation mem);
5611 ins_cost(125);
5612
5613 format %{ "PREFETCHNTA $mem\t# Prefetch allocation to non-temporal cache for write" %}
5614 ins_encode %{
5615 __ prefetchnta($mem$$Address);
5616 %}
5617 ins_pipe(ialu_mem);
5618 %}
5619
5620 instruct prefetchAllocT0( memory mem ) %{
5621 predicate(AllocatePrefetchInstr==1);
5622 match(PrefetchAllocation mem);
5623 ins_cost(125);
5624
5625 format %{ "PREFETCHT0 $mem\t# Prefetch allocation to level 1 and 2 caches for write" %}
5626 ins_encode %{
5627 __ prefetcht0($mem$$Address);
5628 %}
5629 ins_pipe(ialu_mem);
5630 %}
5631
5632 instruct prefetchAllocT2( memory mem ) %{
5633 predicate(AllocatePrefetchInstr==2);
5634 match(PrefetchAllocation mem);
5635 ins_cost(125);
5636
5637 format %{ "PREFETCHT2 $mem\t# Prefetch allocation to level 2 cache for write" %}
5638 ins_encode %{
5639 __ prefetcht2($mem$$Address);
5640 %}
5641 ins_pipe(ialu_mem);
5642 %}
5643
5644 //----------Store Instructions-------------------------------------------------
5645
5646 // Store Byte
5647 instruct storeB(memory mem, rRegI src)
5648 %{
5649 match(Set mem (StoreB mem src));
5650
5651 ins_cost(125); // XXX
5652 format %{ "movb $mem, $src\t# byte" %}
5653 opcode(0x88);
5654 ins_encode(REX_breg_mem(src, mem), OpcP, reg_mem(src, mem));
5655 ins_pipe(ialu_mem_reg);
5656 %}
5657
5658 // Store Char/Short
5659 instruct storeC(memory mem, rRegI src)
5660 %{
5661 match(Set mem (StoreC mem src));
5662
5663 ins_cost(125); // XXX
5664 format %{ "movw $mem, $src\t# char/short" %}
5665 opcode(0x89);
5666 ins_encode(SizePrefix, REX_reg_mem(src, mem), OpcP, reg_mem(src, mem));
5667 ins_pipe(ialu_mem_reg);
5668 %}
5669
5670 // Store Integer
5671 instruct storeI(memory mem, rRegI src)
5672 %{
5673 match(Set mem (StoreI mem src));
5674
5675 ins_cost(125); // XXX
5676 format %{ "movl $mem, $src\t# int" %}
5677 opcode(0x89);
5678 ins_encode(REX_reg_mem(src, mem), OpcP, reg_mem(src, mem));
5679 ins_pipe(ialu_mem_reg);
5680 %}
5681
5682 // Store Long
5683 instruct storeL(memory mem, rRegL src)
5684 %{
5685 match(Set mem (StoreL mem src));
5686
5687 ins_cost(125); // XXX
5688 format %{ "movq $mem, $src\t# long" %}
5689 opcode(0x89);
5690 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem));
5691 ins_pipe(ialu_mem_reg); // XXX
5692 %}
5693
5694 // Store Pointer
5695 instruct storeP(memory mem, any_RegP src)
5696 %{
5697 match(Set mem (StoreP mem src));
5698
5699 ins_cost(125); // XXX
5700 format %{ "movq $mem, $src\t# ptr" %}
5701 opcode(0x89);
5702 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem));
5703 ins_pipe(ialu_mem_reg);
5704 %}
5705
5706 instruct storeImmP0(memory mem, immP0 zero)
5707 %{
5708 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
5709 match(Set mem (StoreP mem zero));
5710
5711 ins_cost(125); // XXX
5712 format %{ "movq $mem, R12\t# ptr (R12_heapbase==0)" %}
5713 ins_encode %{
5714 __ movq($mem$$Address, r12);
5715 %}
5716 ins_pipe(ialu_mem_reg);
5717 %}
5718
5719 // Store NULL Pointer, mark word, or other simple pointer constant.
5720 instruct storeImmP(memory mem, immP31 src)
5721 %{
5722 match(Set mem (StoreP mem src));
5723
5724 ins_cost(150); // XXX
5725 format %{ "movq $mem, $src\t# ptr" %}
5726 opcode(0xC7); /* C7 /0 */
5727 ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src));
5728 ins_pipe(ialu_mem_imm);
5729 %}
5730
5731 // Store Compressed Pointer
5732 instruct storeN(memory mem, rRegN src)
5733 %{
5734 match(Set mem (StoreN mem src));
5735
5736 ins_cost(125); // XXX
5737 format %{ "movl $mem, $src\t# compressed ptr" %}
5738 ins_encode %{
5739 __ movl($mem$$Address, $src$$Register);
5740 %}
5741 ins_pipe(ialu_mem_reg);
5742 %}
5743
5744 instruct storeNKlass(memory mem, rRegN src)
5745 %{
5746 match(Set mem (StoreNKlass mem src));
5747
5748 ins_cost(125); // XXX
5749 format %{ "movl $mem, $src\t# compressed klass ptr" %}
5750 ins_encode %{
5751 __ movl($mem$$Address, $src$$Register);
5752 %}
5753 ins_pipe(ialu_mem_reg);
5754 %}
5755
5756 instruct storeImmN0(memory mem, immN0 zero)
5757 %{
5758 predicate(Universe::narrow_oop_base() == NULL && Universe::narrow_klass_base() == NULL);
5759 match(Set mem (StoreN mem zero));
5760
5761 ins_cost(125); // XXX
5762 format %{ "movl $mem, R12\t# compressed ptr (R12_heapbase==0)" %}
5763 ins_encode %{
5764 __ movl($mem$$Address, r12);
5765 %}
5766 ins_pipe(ialu_mem_reg);
5767 %}
5768
5769 instruct storeImmN(memory mem, immN src)
5770 %{
5771 match(Set mem (StoreN mem src));
5772
5773 ins_cost(150); // XXX
5774 format %{ "movl $mem, $src\t# compressed ptr" %}
5775 ins_encode %{
5776 address con = (address)$src$$constant;
5777 if (con == NULL) {
5778 __ movl($mem$$Address, (int32_t)0);
5779 } else {
5780 __ set_narrow_oop($mem$$Address, (jobject)$src$$constant);
5781 }
5782 %}
5783 ins_pipe(ialu_mem_imm);
5784 %}
5785
5786 instruct storeImmNKlass(memory mem, immNKlass src)
5787 %{
5788 match(Set mem (StoreNKlass mem src));
5789
5790 ins_cost(150); // XXX
5791 format %{ "movl $mem, $src\t# compressed klass ptr" %}
5792 ins_encode %{
5793 __ set_narrow_klass($mem$$Address, (Klass*)$src$$constant);
5794 %}
5795 ins_pipe(ialu_mem_imm);
5796 %}
5797
5798 // Store Integer Immediate
5799 instruct storeImmI0(memory mem, immI0 zero)
5800 %{
5801 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
5802 match(Set mem (StoreI mem zero));
5803
5804 ins_cost(125); // XXX
5805 format %{ "movl $mem, R12\t# int (R12_heapbase==0)" %}
5806 ins_encode %{
5807 __ movl($mem$$Address, r12);
5808 %}
5809 ins_pipe(ialu_mem_reg);
5810 %}
5811
5812 instruct storeImmI(memory mem, immI src)
5813 %{
5814 match(Set mem (StoreI mem src));
5815
5816 ins_cost(150);
5817 format %{ "movl $mem, $src\t# int" %}
5818 opcode(0xC7); /* C7 /0 */
5819 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src));
5820 ins_pipe(ialu_mem_imm);
5821 %}
5822
5823 // Store Long Immediate
5824 instruct storeImmL0(memory mem, immL0 zero)
5825 %{
5826 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
5827 match(Set mem (StoreL mem zero));
5828
5829 ins_cost(125); // XXX
5830 format %{ "movq $mem, R12\t# long (R12_heapbase==0)" %}
5831 ins_encode %{
5832 __ movq($mem$$Address, r12);
5833 %}
5834 ins_pipe(ialu_mem_reg);
5835 %}
5836
5837 instruct storeImmL(memory mem, immL32 src)
5838 %{
5839 match(Set mem (StoreL mem src));
5840
5841 ins_cost(150);
5842 format %{ "movq $mem, $src\t# long" %}
5843 opcode(0xC7); /* C7 /0 */
5844 ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src));
5845 ins_pipe(ialu_mem_imm);
5846 %}
5847
5848 // Store Short/Char Immediate
5849 instruct storeImmC0(memory mem, immI0 zero)
5850 %{
5851 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
5852 match(Set mem (StoreC mem zero));
5853
5854 ins_cost(125); // XXX
5855 format %{ "movw $mem, R12\t# short/char (R12_heapbase==0)" %}
5856 ins_encode %{
5857 __ movw($mem$$Address, r12);
5858 %}
5859 ins_pipe(ialu_mem_reg);
5860 %}
5861
5862 instruct storeImmI16(memory mem, immI16 src)
5863 %{
5864 predicate(UseStoreImmI16);
5865 match(Set mem (StoreC mem src));
5866
5867 ins_cost(150);
5868 format %{ "movw $mem, $src\t# short/char" %}
5869 opcode(0xC7); /* C7 /0 Same as 32 store immediate with prefix */
5870 ins_encode(SizePrefix, REX_mem(mem), OpcP, RM_opc_mem(0x00, mem),Con16(src));
5871 ins_pipe(ialu_mem_imm);
5872 %}
5873
5874 // Store Byte Immediate
5875 instruct storeImmB0(memory mem, immI0 zero)
5876 %{
5877 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
5878 match(Set mem (StoreB mem zero));
5879
5880 ins_cost(125); // XXX
5881 format %{ "movb $mem, R12\t# short/char (R12_heapbase==0)" %}
5882 ins_encode %{
5883 __ movb($mem$$Address, r12);
5884 %}
5885 ins_pipe(ialu_mem_reg);
5886 %}
5887
5888 instruct storeImmB(memory mem, immI8 src)
5889 %{
5890 match(Set mem (StoreB mem src));
5891
5892 ins_cost(150); // XXX
5893 format %{ "movb $mem, $src\t# byte" %}
5894 opcode(0xC6); /* C6 /0 */
5895 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con8or32(src));
5896 ins_pipe(ialu_mem_imm);
5897 %}
5898
5899 // Store CMS card-mark Immediate
5900 instruct storeImmCM0_reg(memory mem, immI0 zero)
5901 %{
5902 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
5903 match(Set mem (StoreCM mem zero));
5904
5905 ins_cost(125); // XXX
5906 format %{ "movb $mem, R12\t# CMS card-mark byte 0 (R12_heapbase==0)" %}
5907 ins_encode %{
5908 __ movb($mem$$Address, r12);
5909 %}
5910 ins_pipe(ialu_mem_reg);
5911 %}
5912
5913 instruct storeImmCM0(memory mem, immI0 src)
5914 %{
5915 match(Set mem (StoreCM mem src));
5916
5917 ins_cost(150); // XXX
5918 format %{ "movb $mem, $src\t# CMS card-mark byte 0" %}
5919 opcode(0xC6); /* C6 /0 */
5920 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con8or32(src));
5921 ins_pipe(ialu_mem_imm);
5922 %}
5923
5924 // Store Float
5925 instruct storeF(memory mem, regF src)
5926 %{
5927 match(Set mem (StoreF mem src));
5928
5929 ins_cost(95); // XXX
5930 format %{ "movss $mem, $src\t# float" %}
5931 ins_encode %{
5932 __ movflt($mem$$Address, $src$$XMMRegister);
5933 %}
5934 ins_pipe(pipe_slow); // XXX
5935 %}
5936
5937 // Store immediate Float value (it is faster than store from XMM register)
5938 instruct storeF0(memory mem, immF0 zero)
5939 %{
5940 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
5941 match(Set mem (StoreF mem zero));
5942
5943 ins_cost(25); // XXX
5944 format %{ "movl $mem, R12\t# float 0. (R12_heapbase==0)" %}
5945 ins_encode %{
5946 __ movl($mem$$Address, r12);
5947 %}
5948 ins_pipe(ialu_mem_reg);
5949 %}
5950
5951 instruct storeF_imm(memory mem, immF src)
5952 %{
5953 match(Set mem (StoreF mem src));
5954
5955 ins_cost(50);
5956 format %{ "movl $mem, $src\t# float" %}
5957 opcode(0xC7); /* C7 /0 */
5958 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con32F_as_bits(src));
5959 ins_pipe(ialu_mem_imm);
5960 %}
5961
5962 // Store Double
5963 instruct storeD(memory mem, regD src)
5964 %{
5965 match(Set mem (StoreD mem src));
5966
5967 ins_cost(95); // XXX
5968 format %{ "movsd $mem, $src\t# double" %}
5969 ins_encode %{
5970 __ movdbl($mem$$Address, $src$$XMMRegister);
5971 %}
5972 ins_pipe(pipe_slow); // XXX
5973 %}
5974
5975 // Store immediate double 0.0 (it is faster than store from XMM register)
5976 instruct storeD0_imm(memory mem, immD0 src)
5977 %{
5978 predicate(!UseCompressedOops || (Universe::narrow_oop_base() != NULL));
5979 match(Set mem (StoreD mem src));
5980
5981 ins_cost(50);
5982 format %{ "movq $mem, $src\t# double 0." %}
5983 opcode(0xC7); /* C7 /0 */
5984 ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32F_as_bits(src));
5985 ins_pipe(ialu_mem_imm);
5986 %}
5987
5988 instruct storeD0(memory mem, immD0 zero)
5989 %{
5990 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
5991 match(Set mem (StoreD mem zero));
5992
5993 ins_cost(25); // XXX
5994 format %{ "movq $mem, R12\t# double 0. (R12_heapbase==0)" %}
5995 ins_encode %{
5996 __ movq($mem$$Address, r12);
5997 %}
5998 ins_pipe(ialu_mem_reg);
5999 %}
6000
6001 instruct storeSSI(stackSlotI dst, rRegI src)
6002 %{
6003 match(Set dst src);
6004
6005 ins_cost(100);
6006 format %{ "movl $dst, $src\t# int stk" %}
6007 opcode(0x89);
6008 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
6009 ins_pipe( ialu_mem_reg );
6010 %}
6011
6012 instruct storeSSL(stackSlotL dst, rRegL src)
6013 %{
6014 match(Set dst src);
6015
6016 ins_cost(100);
6017 format %{ "movq $dst, $src\t# long stk" %}
6018 opcode(0x89);
6019 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
6020 ins_pipe(ialu_mem_reg);
6021 %}
6022
6023 instruct storeSSP(stackSlotP dst, rRegP src)
6024 %{
6025 match(Set dst src);
6026
6027 ins_cost(100);
6028 format %{ "movq $dst, $src\t# ptr stk" %}
6029 opcode(0x89);
6030 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
6031 ins_pipe(ialu_mem_reg);
6032 %}
6033
6034 instruct storeSSF(stackSlotF dst, regF src)
6035 %{
6036 match(Set dst src);
6037
6038 ins_cost(95); // XXX
6039 format %{ "movss $dst, $src\t# float stk" %}
6040 ins_encode %{
6041 __ movflt(Address(rsp, $dst$$disp), $src$$XMMRegister);
6042 %}
6043 ins_pipe(pipe_slow); // XXX
6044 %}
6045
6046 instruct storeSSD(stackSlotD dst, regD src)
6047 %{
6048 match(Set dst src);
6049
6050 ins_cost(95); // XXX
6051 format %{ "movsd $dst, $src\t# double stk" %}
6052 ins_encode %{
6053 __ movdbl(Address(rsp, $dst$$disp), $src$$XMMRegister);
6054 %}
6055 ins_pipe(pipe_slow); // XXX
6056 %}
6057
6058 //----------BSWAP Instructions-------------------------------------------------
6059 instruct bytes_reverse_int(rRegI dst) %{
6060 match(Set dst (ReverseBytesI dst));
6061
6062 format %{ "bswapl $dst" %}
6063 opcode(0x0F, 0xC8); /*Opcode 0F /C8 */
6064 ins_encode( REX_reg(dst), OpcP, opc2_reg(dst) );
6065 ins_pipe( ialu_reg );
6066 %}
6067
6068 instruct bytes_reverse_long(rRegL dst) %{
6069 match(Set dst (ReverseBytesL dst));
6070
6071 format %{ "bswapq $dst" %}
6072 opcode(0x0F, 0xC8); /* Opcode 0F /C8 */
6073 ins_encode( REX_reg_wide(dst), OpcP, opc2_reg(dst) );
6074 ins_pipe( ialu_reg);
6075 %}
6076
6077 instruct bytes_reverse_unsigned_short(rRegI dst, rFlagsReg cr) %{
6078 match(Set dst (ReverseBytesUS dst));
6079 effect(KILL cr);
6080
6081 format %{ "bswapl $dst\n\t"
6082 "shrl $dst,16\n\t" %}
6083 ins_encode %{
6084 __ bswapl($dst$$Register);
6085 __ shrl($dst$$Register, 16);
6086 %}
6087 ins_pipe( ialu_reg );
6088 %}
6089
6090 instruct bytes_reverse_short(rRegI dst, rFlagsReg cr) %{
6091 match(Set dst (ReverseBytesS dst));
6092 effect(KILL cr);
6093
6094 format %{ "bswapl $dst\n\t"
6095 "sar $dst,16\n\t" %}
6096 ins_encode %{
6097 __ bswapl($dst$$Register);
6098 __ sarl($dst$$Register, 16);
6099 %}
6100 ins_pipe( ialu_reg );
6101 %}
6102
6103 //---------- Zeros Count Instructions ------------------------------------------
6104
6105 instruct countLeadingZerosI(rRegI dst, rRegI src, rFlagsReg cr) %{
6106 predicate(UseCountLeadingZerosInstruction);
6107 match(Set dst (CountLeadingZerosI src));
6108 effect(KILL cr);
6109
6110 format %{ "lzcntl $dst, $src\t# count leading zeros (int)" %}
6111 ins_encode %{
6112 __ lzcntl($dst$$Register, $src$$Register);
6113 %}
6114 ins_pipe(ialu_reg);
6115 %}
6116
6117 instruct countLeadingZerosI_bsr(rRegI dst, rRegI src, rFlagsReg cr) %{
6118 predicate(!UseCountLeadingZerosInstruction);
6119 match(Set dst (CountLeadingZerosI src));
6120 effect(KILL cr);
6121
6122 format %{ "bsrl $dst, $src\t# count leading zeros (int)\n\t"
6123 "jnz skip\n\t"
6124 "movl $dst, -1\n"
6125 "skip:\n\t"
6126 "negl $dst\n\t"
6127 "addl $dst, 31" %}
6128 ins_encode %{
6129 Register Rdst = $dst$$Register;
6130 Register Rsrc = $src$$Register;
6131 Label skip;
6132 __ bsrl(Rdst, Rsrc);
6133 __ jccb(Assembler::notZero, skip);
6134 __ movl(Rdst, -1);
6135 __ bind(skip);
6136 __ negl(Rdst);
6137 __ addl(Rdst, BitsPerInt - 1);
6138 %}
6139 ins_pipe(ialu_reg);
6140 %}
6141
6142 instruct countLeadingZerosL(rRegI dst, rRegL src, rFlagsReg cr) %{
6143 predicate(UseCountLeadingZerosInstruction);
6144 match(Set dst (CountLeadingZerosL src));
6145 effect(KILL cr);
6146
6147 format %{ "lzcntq $dst, $src\t# count leading zeros (long)" %}
6148 ins_encode %{
6149 __ lzcntq($dst$$Register, $src$$Register);
6150 %}
6151 ins_pipe(ialu_reg);
6152 %}
6153
6154 instruct countLeadingZerosL_bsr(rRegI dst, rRegL src, rFlagsReg cr) %{
6155 predicate(!UseCountLeadingZerosInstruction);
6156 match(Set dst (CountLeadingZerosL src));
6157 effect(KILL cr);
6158
6159 format %{ "bsrq $dst, $src\t# count leading zeros (long)\n\t"
6160 "jnz skip\n\t"
6161 "movl $dst, -1\n"
6162 "skip:\n\t"
6163 "negl $dst\n\t"
6164 "addl $dst, 63" %}
6165 ins_encode %{
6166 Register Rdst = $dst$$Register;
6167 Register Rsrc = $src$$Register;
6168 Label skip;
6169 __ bsrq(Rdst, Rsrc);
6170 __ jccb(Assembler::notZero, skip);
6171 __ movl(Rdst, -1);
6172 __ bind(skip);
6173 __ negl(Rdst);
6174 __ addl(Rdst, BitsPerLong - 1);
6175 %}
6176 ins_pipe(ialu_reg);
6177 %}
6178
6179 instruct countTrailingZerosI(rRegI dst, rRegI src, rFlagsReg cr) %{
6180 predicate(UseCountTrailingZerosInstruction);
6181 match(Set dst (CountTrailingZerosI src));
6182 effect(KILL cr);
6183
6184 format %{ "tzcntl $dst, $src\t# count trailing zeros (int)" %}
6185 ins_encode %{
6186 __ tzcntl($dst$$Register, $src$$Register);
6187 %}
6188 ins_pipe(ialu_reg);
6189 %}
6190
6191 instruct countTrailingZerosI_bsf(rRegI dst, rRegI src, rFlagsReg cr) %{
6192 predicate(!UseCountTrailingZerosInstruction);
6193 match(Set dst (CountTrailingZerosI src));
6194 effect(KILL cr);
6195
6196 format %{ "bsfl $dst, $src\t# count trailing zeros (int)\n\t"
6197 "jnz done\n\t"
6198 "movl $dst, 32\n"
6199 "done:" %}
6200 ins_encode %{
6201 Register Rdst = $dst$$Register;
6202 Label done;
6203 __ bsfl(Rdst, $src$$Register);
6204 __ jccb(Assembler::notZero, done);
6205 __ movl(Rdst, BitsPerInt);
6206 __ bind(done);
6207 %}
6208 ins_pipe(ialu_reg);
6209 %}
6210
6211 instruct countTrailingZerosL(rRegI dst, rRegL src, rFlagsReg cr) %{
6212 predicate(UseCountTrailingZerosInstruction);
6213 match(Set dst (CountTrailingZerosL src));
6214 effect(KILL cr);
6215
6216 format %{ "tzcntq $dst, $src\t# count trailing zeros (long)" %}
6217 ins_encode %{
6218 __ tzcntq($dst$$Register, $src$$Register);
6219 %}
6220 ins_pipe(ialu_reg);
6221 %}
6222
6223 instruct countTrailingZerosL_bsf(rRegI dst, rRegL src, rFlagsReg cr) %{
6224 predicate(!UseCountTrailingZerosInstruction);
6225 match(Set dst (CountTrailingZerosL src));
6226 effect(KILL cr);
6227
6228 format %{ "bsfq $dst, $src\t# count trailing zeros (long)\n\t"
6229 "jnz done\n\t"
6230 "movl $dst, 64\n"
6231 "done:" %}
6232 ins_encode %{
6233 Register Rdst = $dst$$Register;
6234 Label done;
6235 __ bsfq(Rdst, $src$$Register);
6236 __ jccb(Assembler::notZero, done);
6237 __ movl(Rdst, BitsPerLong);
6238 __ bind(done);
6239 %}
6240 ins_pipe(ialu_reg);
6241 %}
6242
6243
6244 //---------- Population Count Instructions -------------------------------------
6245
6246 instruct popCountI(rRegI dst, rRegI src, rFlagsReg cr) %{
6247 predicate(UsePopCountInstruction);
6248 match(Set dst (PopCountI src));
6249 effect(KILL cr);
6250
6251 format %{ "popcnt $dst, $src" %}
6252 ins_encode %{
6253 __ popcntl($dst$$Register, $src$$Register);
6254 %}
6255 ins_pipe(ialu_reg);
6256 %}
6257
6258 instruct popCountI_mem(rRegI dst, memory mem, rFlagsReg cr) %{
6259 predicate(UsePopCountInstruction);
6260 match(Set dst (PopCountI (LoadI mem)));
6261 effect(KILL cr);
6262
6263 format %{ "popcnt $dst, $mem" %}
6264 ins_encode %{
6265 __ popcntl($dst$$Register, $mem$$Address);
6266 %}
6267 ins_pipe(ialu_reg);
6268 %}
6269
6270 // Note: Long.bitCount(long) returns an int.
6271 instruct popCountL(rRegI dst, rRegL src, rFlagsReg cr) %{
6272 predicate(UsePopCountInstruction);
6273 match(Set dst (PopCountL src));
6274 effect(KILL cr);
6275
6276 format %{ "popcnt $dst, $src" %}
6277 ins_encode %{
6278 __ popcntq($dst$$Register, $src$$Register);
6279 %}
6280 ins_pipe(ialu_reg);
6281 %}
6282
6283 // Note: Long.bitCount(long) returns an int.
6284 instruct popCountL_mem(rRegI dst, memory mem, rFlagsReg cr) %{
6285 predicate(UsePopCountInstruction);
6286 match(Set dst (PopCountL (LoadL mem)));
6287 effect(KILL cr);
6288
6289 format %{ "popcnt $dst, $mem" %}
6290 ins_encode %{
6291 __ popcntq($dst$$Register, $mem$$Address);
6292 %}
6293 ins_pipe(ialu_reg);
6294 %}
6295
6296
6297 //----------MemBar Instructions-----------------------------------------------
6298 // Memory barrier flavors
6299
6300 instruct membar_acquire()
6301 %{
6302 match(MemBarAcquire);
6303 match(LoadFence);
6304 ins_cost(0);
6305
6306 size(0);
6307 format %{ "MEMBAR-acquire ! (empty encoding)" %}
6308 ins_encode();
6309 ins_pipe(empty);
6310 %}
6311
6312 instruct membar_acquire_lock()
6313 %{
6314 match(MemBarAcquireLock);
6315 ins_cost(0);
6316
6317 size(0);
6318 format %{ "MEMBAR-acquire (prior CMPXCHG in FastLock so empty encoding)" %}
6319 ins_encode();
6320 ins_pipe(empty);
6321 %}
6322
6323 instruct membar_release()
6324 %{
6325 match(MemBarRelease);
6326 match(StoreFence);
6327 ins_cost(0);
6328
6329 size(0);
6330 format %{ "MEMBAR-release ! (empty encoding)" %}
6331 ins_encode();
6332 ins_pipe(empty);
6333 %}
6334
6335 instruct membar_release_lock()
6336 %{
6337 match(MemBarReleaseLock);
6338 ins_cost(0);
6339
6340 size(0);
6341 format %{ "MEMBAR-release (a FastUnlock follows so empty encoding)" %}
6342 ins_encode();
6343 ins_pipe(empty);
6344 %}
6345
6346 instruct membar_volatile(rFlagsReg cr) %{
6347 match(MemBarVolatile);
6348 effect(KILL cr);
6349 ins_cost(400);
6350
6351 format %{
6352 $$template
6353 if (os::is_MP()) {
6354 $$emit$$"lock addl [rsp + #0], 0\t! membar_volatile"
6355 } else {
6356 $$emit$$"MEMBAR-volatile ! (empty encoding)"
6357 }
6358 %}
6359 ins_encode %{
6360 __ membar(Assembler::StoreLoad);
6361 %}
6362 ins_pipe(pipe_slow);
6363 %}
6364
6365 instruct unnecessary_membar_volatile()
6366 %{
6367 match(MemBarVolatile);
6368 predicate(Matcher::post_store_load_barrier(n));
6369 ins_cost(0);
6370
6371 size(0);
6372 format %{ "MEMBAR-volatile (unnecessary so empty encoding)" %}
6373 ins_encode();
6374 ins_pipe(empty);
6375 %}
6376
6377 instruct membar_storestore() %{
6378 match(MemBarStoreStore);
6379 ins_cost(0);
6380
6381 size(0);
6382 format %{ "MEMBAR-storestore (empty encoding)" %}
6383 ins_encode( );
6384 ins_pipe(empty);
6385 %}
6386
6387 //----------Move Instructions--------------------------------------------------
6388
6389 instruct castX2P(rRegP dst, rRegL src)
6390 %{
6391 match(Set dst (CastX2P src));
6392
6393 format %{ "movq $dst, $src\t# long->ptr" %}
6394 ins_encode %{
6395 if ($dst$$reg != $src$$reg) {
6396 __ movptr($dst$$Register, $src$$Register);
6397 }
6398 %}
6399 ins_pipe(ialu_reg_reg); // XXX
6400 %}
6401
6402 instruct castP2X(rRegL dst, rRegP src)
6403 %{
6404 match(Set dst (CastP2X src));
6405
6406 format %{ "movq $dst, $src\t# ptr -> long" %}
6407 ins_encode %{
6408 if ($dst$$reg != $src$$reg) {
6409 __ movptr($dst$$Register, $src$$Register);
6410 }
6411 %}
6412 ins_pipe(ialu_reg_reg); // XXX
6413 %}
6414
6415 // Convert oop into int for vectors alignment masking
6416 instruct convP2I(rRegI dst, rRegP src)
6417 %{
6418 match(Set dst (ConvL2I (CastP2X src)));
6419
6420 format %{ "movl $dst, $src\t# ptr -> int" %}
6421 ins_encode %{
6422 __ movl($dst$$Register, $src$$Register);
6423 %}
6424 ins_pipe(ialu_reg_reg); // XXX
6425 %}
6426
6427 // Convert compressed oop into int for vectors alignment masking
6428 // in case of 32bit oops (heap < 4Gb).
6429 instruct convN2I(rRegI dst, rRegN src)
6430 %{
6431 predicate(Universe::narrow_oop_shift() == 0);
6432 match(Set dst (ConvL2I (CastP2X (DecodeN src))));
6433
6434 format %{ "movl $dst, $src\t# compressed ptr -> int" %}
6435 ins_encode %{
6436 __ movl($dst$$Register, $src$$Register);
6437 %}
6438 ins_pipe(ialu_reg_reg); // XXX
6439 %}
6440
6441 // Convert oop pointer into compressed form
6442 instruct encodeHeapOop(rRegN dst, rRegP src, rFlagsReg cr) %{
6443 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull);
6444 match(Set dst (EncodeP src));
6445 effect(KILL cr);
6446 format %{ "encode_heap_oop $dst,$src" %}
6447 ins_encode %{
6448 Register s = $src$$Register;
6449 Register d = $dst$$Register;
6450 if (s != d) {
6451 __ movq(d, s);
6452 }
6453 __ encode_heap_oop(d);
6454 %}
6455 ins_pipe(ialu_reg_long);
6456 %}
6457
6458 instruct encodeHeapOop_not_null(rRegN dst, rRegP src, rFlagsReg cr) %{
6459 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull);
6460 match(Set dst (EncodeP src));
6461 effect(KILL cr);
6462 format %{ "encode_heap_oop_not_null $dst,$src" %}
6463 ins_encode %{
6464 __ encode_heap_oop_not_null($dst$$Register, $src$$Register);
6465 %}
6466 ins_pipe(ialu_reg_long);
6467 %}
6468
6469 instruct decodeHeapOop(rRegP dst, rRegN src, rFlagsReg cr) %{
6470 predicate(n->bottom_type()->is_ptr()->ptr() != TypePtr::NotNull &&
6471 n->bottom_type()->is_ptr()->ptr() != TypePtr::Constant);
6472 match(Set dst (DecodeN src));
6473 effect(KILL cr);
6474 format %{ "decode_heap_oop $dst,$src" %}
6475 ins_encode %{
6476 Register s = $src$$Register;
6477 Register d = $dst$$Register;
6478 if (s != d) {
6479 __ movq(d, s);
6480 }
6481 __ decode_heap_oop(d);
6482 %}
6483 ins_pipe(ialu_reg_long);
6484 %}
6485
6486 instruct decodeHeapOop_not_null(rRegP dst, rRegN src, rFlagsReg cr) %{
6487 predicate(n->bottom_type()->is_ptr()->ptr() == TypePtr::NotNull ||
6488 n->bottom_type()->is_ptr()->ptr() == TypePtr::Constant);
6489 match(Set dst (DecodeN src));
6490 effect(KILL cr);
6491 format %{ "decode_heap_oop_not_null $dst,$src" %}
6492 ins_encode %{
6493 Register s = $src$$Register;
6494 Register d = $dst$$Register;
6495 if (s != d) {
6496 __ decode_heap_oop_not_null(d, s);
6497 } else {
6498 __ decode_heap_oop_not_null(d);
6499 }
6500 %}
6501 ins_pipe(ialu_reg_long);
6502 %}
6503
6504 instruct encodeKlass_not_null(rRegN dst, rRegP src, rFlagsReg cr) %{
6505 match(Set dst (EncodePKlass src));
6506 effect(KILL cr);
6507 format %{ "encode_klass_not_null $dst,$src" %}
6508 ins_encode %{
6509 __ encode_klass_not_null($dst$$Register, $src$$Register);
6510 %}
6511 ins_pipe(ialu_reg_long);
6512 %}
6513
6514 instruct decodeKlass_not_null(rRegP dst, rRegN src, rFlagsReg cr) %{
6515 match(Set dst (DecodeNKlass src));
6516 effect(KILL cr);
6517 format %{ "decode_klass_not_null $dst,$src" %}
6518 ins_encode %{
6519 Register s = $src$$Register;
6520 Register d = $dst$$Register;
6521 if (s != d) {
6522 __ decode_klass_not_null(d, s);
6523 } else {
6524 __ decode_klass_not_null(d);
6525 }
6526 %}
6527 ins_pipe(ialu_reg_long);
6528 %}
6529
6530
6531 //----------Conditional Move---------------------------------------------------
6532 // Jump
6533 // dummy instruction for generating temp registers
6534 instruct jumpXtnd_offset(rRegL switch_val, immI2 shift, rRegI dest) %{
6535 match(Jump (LShiftL switch_val shift));
6536 ins_cost(350);
6537 predicate(false);
6538 effect(TEMP dest);
6539
6540 format %{ "leaq $dest, [$constantaddress]\n\t"
6541 "jmp [$dest + $switch_val << $shift]\n\t" %}
6542 ins_encode %{
6543 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10
6544 // to do that and the compiler is using that register as one it can allocate.
6545 // So we build it all by hand.
6546 // Address index(noreg, switch_reg, (Address::ScaleFactor)$shift$$constant);
6547 // ArrayAddress dispatch(table, index);
6548 Address dispatch($dest$$Register, $switch_val$$Register, (Address::ScaleFactor) $shift$$constant);
6549 __ lea($dest$$Register, $constantaddress);
6550 __ jmp(dispatch);
6551 %}
6552 ins_pipe(pipe_jmp);
6553 %}
6554
6555 instruct jumpXtnd_addr(rRegL switch_val, immI2 shift, immL32 offset, rRegI dest) %{
6556 match(Jump (AddL (LShiftL switch_val shift) offset));
6557 ins_cost(350);
6558 effect(TEMP dest);
6559
6560 format %{ "leaq $dest, [$constantaddress]\n\t"
6561 "jmp [$dest + $switch_val << $shift + $offset]\n\t" %}
6562 ins_encode %{
6563 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10
6564 // to do that and the compiler is using that register as one it can allocate.
6565 // So we build it all by hand.
6566 // Address index(noreg, switch_reg, (Address::ScaleFactor) $shift$$constant, (int) $offset$$constant);
6567 // ArrayAddress dispatch(table, index);
6568 Address dispatch($dest$$Register, $switch_val$$Register, (Address::ScaleFactor) $shift$$constant, (int) $offset$$constant);
6569 __ lea($dest$$Register, $constantaddress);
6570 __ jmp(dispatch);
6571 %}
6572 ins_pipe(pipe_jmp);
6573 %}
6574
6575 instruct jumpXtnd(rRegL switch_val, rRegI dest) %{
6576 match(Jump switch_val);
6577 ins_cost(350);
6578 effect(TEMP dest);
6579
6580 format %{ "leaq $dest, [$constantaddress]\n\t"
6581 "jmp [$dest + $switch_val]\n\t" %}
6582 ins_encode %{
6583 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10
6584 // to do that and the compiler is using that register as one it can allocate.
6585 // So we build it all by hand.
6586 // Address index(noreg, switch_reg, Address::times_1);
6587 // ArrayAddress dispatch(table, index);
6588 Address dispatch($dest$$Register, $switch_val$$Register, Address::times_1);
6589 __ lea($dest$$Register, $constantaddress);
6590 __ jmp(dispatch);
6591 %}
6592 ins_pipe(pipe_jmp);
6593 %}
6594
6595 // Conditional move
6596 instruct cmovI_reg(rRegI dst, rRegI src, rFlagsReg cr, cmpOp cop)
6597 %{
6598 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
6599
6600 ins_cost(200); // XXX
6601 format %{ "cmovl$cop $dst, $src\t# signed, int" %}
6602 opcode(0x0F, 0x40);
6603 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src));
6604 ins_pipe(pipe_cmov_reg);
6605 %}
6606
6607 instruct cmovI_regU(cmpOpU cop, rFlagsRegU cr, rRegI dst, rRegI src) %{
6608 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
6609
6610 ins_cost(200); // XXX
6611 format %{ "cmovl$cop $dst, $src\t# unsigned, int" %}
6612 opcode(0x0F, 0x40);
6613 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src));
6614 ins_pipe(pipe_cmov_reg);
6615 %}
6616
6617 instruct cmovI_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegI dst, rRegI src) %{
6618 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
6619 ins_cost(200);
6620 expand %{
6621 cmovI_regU(cop, cr, dst, src);
6622 %}
6623 %}
6624
6625 // Conditional move
6626 instruct cmovI_mem(cmpOp cop, rFlagsReg cr, rRegI dst, memory src) %{
6627 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
6628
6629 ins_cost(250); // XXX
6630 format %{ "cmovl$cop $dst, $src\t# signed, int" %}
6631 opcode(0x0F, 0x40);
6632 ins_encode(REX_reg_mem(dst, src), enc_cmov(cop), reg_mem(dst, src));
6633 ins_pipe(pipe_cmov_mem);
6634 %}
6635
6636 // Conditional move
6637 instruct cmovI_memU(cmpOpU cop, rFlagsRegU cr, rRegI dst, memory src)
6638 %{
6639 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
6640
6641 ins_cost(250); // XXX
6642 format %{ "cmovl$cop $dst, $src\t# unsigned, int" %}
6643 opcode(0x0F, 0x40);
6644 ins_encode(REX_reg_mem(dst, src), enc_cmov(cop), reg_mem(dst, src));
6645 ins_pipe(pipe_cmov_mem);
6646 %}
6647
6648 instruct cmovI_memUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegI dst, memory src) %{
6649 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
6650 ins_cost(250);
6651 expand %{
6652 cmovI_memU(cop, cr, dst, src);
6653 %}
6654 %}
6655
6656 // Conditional move
6657 instruct cmovN_reg(rRegN dst, rRegN src, rFlagsReg cr, cmpOp cop)
6658 %{
6659 match(Set dst (CMoveN (Binary cop cr) (Binary dst src)));
6660
6661 ins_cost(200); // XXX
6662 format %{ "cmovl$cop $dst, $src\t# signed, compressed ptr" %}
6663 opcode(0x0F, 0x40);
6664 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src));
6665 ins_pipe(pipe_cmov_reg);
6666 %}
6667
6668 // Conditional move
6669 instruct cmovN_regU(cmpOpU cop, rFlagsRegU cr, rRegN dst, rRegN src)
6670 %{
6671 match(Set dst (CMoveN (Binary cop cr) (Binary dst src)));
6672
6673 ins_cost(200); // XXX
6674 format %{ "cmovl$cop $dst, $src\t# unsigned, compressed ptr" %}
6675 opcode(0x0F, 0x40);
6676 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src));
6677 ins_pipe(pipe_cmov_reg);
6678 %}
6679
6680 instruct cmovN_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegN dst, rRegN src) %{
6681 match(Set dst (CMoveN (Binary cop cr) (Binary dst src)));
6682 ins_cost(200);
6683 expand %{
6684 cmovN_regU(cop, cr, dst, src);
6685 %}
6686 %}
6687
6688 // Conditional move
6689 instruct cmovP_reg(rRegP dst, rRegP src, rFlagsReg cr, cmpOp cop)
6690 %{
6691 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
6692
6693 ins_cost(200); // XXX
6694 format %{ "cmovq$cop $dst, $src\t# signed, ptr" %}
6695 opcode(0x0F, 0x40);
6696 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src));
6697 ins_pipe(pipe_cmov_reg); // XXX
6698 %}
6699
6700 // Conditional move
6701 instruct cmovP_regU(cmpOpU cop, rFlagsRegU cr, rRegP dst, rRegP src)
6702 %{
6703 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
6704
6705 ins_cost(200); // XXX
6706 format %{ "cmovq$cop $dst, $src\t# unsigned, ptr" %}
6707 opcode(0x0F, 0x40);
6708 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src));
6709 ins_pipe(pipe_cmov_reg); // XXX
6710 %}
6711
6712 instruct cmovP_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegP dst, rRegP src) %{
6713 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
6714 ins_cost(200);
6715 expand %{
6716 cmovP_regU(cop, cr, dst, src);
6717 %}
6718 %}
6719
6720 // DISABLED: Requires the ADLC to emit a bottom_type call that
6721 // correctly meets the two pointer arguments; one is an incoming
6722 // register but the other is a memory operand. ALSO appears to
6723 // be buggy with implicit null checks.
6724 //
6725 //// Conditional move
6726 //instruct cmovP_mem(cmpOp cop, rFlagsReg cr, rRegP dst, memory src)
6727 //%{
6728 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
6729 // ins_cost(250);
6730 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
6731 // opcode(0x0F,0x40);
6732 // ins_encode( enc_cmov(cop), reg_mem( dst, src ) );
6733 // ins_pipe( pipe_cmov_mem );
6734 //%}
6735 //
6736 //// Conditional move
6737 //instruct cmovP_memU(cmpOpU cop, rFlagsRegU cr, rRegP dst, memory src)
6738 //%{
6739 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
6740 // ins_cost(250);
6741 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
6742 // opcode(0x0F,0x40);
6743 // ins_encode( enc_cmov(cop), reg_mem( dst, src ) );
6744 // ins_pipe( pipe_cmov_mem );
6745 //%}
6746
6747 instruct cmovL_reg(cmpOp cop, rFlagsReg cr, rRegL dst, rRegL src)
6748 %{
6749 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
6750
6751 ins_cost(200); // XXX
6752 format %{ "cmovq$cop $dst, $src\t# signed, long" %}
6753 opcode(0x0F, 0x40);
6754 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src));
6755 ins_pipe(pipe_cmov_reg); // XXX
6756 %}
6757
6758 instruct cmovL_mem(cmpOp cop, rFlagsReg cr, rRegL dst, memory src)
6759 %{
6760 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src))));
6761
6762 ins_cost(200); // XXX
6763 format %{ "cmovq$cop $dst, $src\t# signed, long" %}
6764 opcode(0x0F, 0x40);
6765 ins_encode(REX_reg_mem_wide(dst, src), enc_cmov(cop), reg_mem(dst, src));
6766 ins_pipe(pipe_cmov_mem); // XXX
6767 %}
6768
6769 instruct cmovL_regU(cmpOpU cop, rFlagsRegU cr, rRegL dst, rRegL src)
6770 %{
6771 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
6772
6773 ins_cost(200); // XXX
6774 format %{ "cmovq$cop $dst, $src\t# unsigned, long" %}
6775 opcode(0x0F, 0x40);
6776 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src));
6777 ins_pipe(pipe_cmov_reg); // XXX
6778 %}
6779
6780 instruct cmovL_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegL dst, rRegL src) %{
6781 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
6782 ins_cost(200);
6783 expand %{
6784 cmovL_regU(cop, cr, dst, src);
6785 %}
6786 %}
6787
6788 instruct cmovL_memU(cmpOpU cop, rFlagsRegU cr, rRegL dst, memory src)
6789 %{
6790 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src))));
6791
6792 ins_cost(200); // XXX
6793 format %{ "cmovq$cop $dst, $src\t# unsigned, long" %}
6794 opcode(0x0F, 0x40);
6795 ins_encode(REX_reg_mem_wide(dst, src), enc_cmov(cop), reg_mem(dst, src));
6796 ins_pipe(pipe_cmov_mem); // XXX
6797 %}
6798
6799 instruct cmovL_memUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegL dst, memory src) %{
6800 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src))));
6801 ins_cost(200);
6802 expand %{
6803 cmovL_memU(cop, cr, dst, src);
6804 %}
6805 %}
6806
6807 instruct cmovF_reg(cmpOp cop, rFlagsReg cr, regF dst, regF src)
6808 %{
6809 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
6810
6811 ins_cost(200); // XXX
6812 format %{ "jn$cop skip\t# signed cmove float\n\t"
6813 "movss $dst, $src\n"
6814 "skip:" %}
6815 ins_encode %{
6816 Label Lskip;
6817 // Invert sense of branch from sense of CMOV
6818 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
6819 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
6820 __ bind(Lskip);
6821 %}
6822 ins_pipe(pipe_slow);
6823 %}
6824
6825 // instruct cmovF_mem(cmpOp cop, rFlagsReg cr, regF dst, memory src)
6826 // %{
6827 // match(Set dst (CMoveF (Binary cop cr) (Binary dst (LoadL src))));
6828
6829 // ins_cost(200); // XXX
6830 // format %{ "jn$cop skip\t# signed cmove float\n\t"
6831 // "movss $dst, $src\n"
6832 // "skip:" %}
6833 // ins_encode(enc_cmovf_mem_branch(cop, dst, src));
6834 // ins_pipe(pipe_slow);
6835 // %}
6836
6837 instruct cmovF_regU(cmpOpU cop, rFlagsRegU cr, regF dst, regF src)
6838 %{
6839 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
6840
6841 ins_cost(200); // XXX
6842 format %{ "jn$cop skip\t# unsigned cmove float\n\t"
6843 "movss $dst, $src\n"
6844 "skip:" %}
6845 ins_encode %{
6846 Label Lskip;
6847 // Invert sense of branch from sense of CMOV
6848 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
6849 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
6850 __ bind(Lskip);
6851 %}
6852 ins_pipe(pipe_slow);
6853 %}
6854
6855 instruct cmovF_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, regF dst, regF src) %{
6856 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
6857 ins_cost(200);
6858 expand %{
6859 cmovF_regU(cop, cr, dst, src);
6860 %}
6861 %}
6862
6863 instruct cmovD_reg(cmpOp cop, rFlagsReg cr, regD dst, regD src)
6864 %{
6865 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
6866
6867 ins_cost(200); // XXX
6868 format %{ "jn$cop skip\t# signed cmove double\n\t"
6869 "movsd $dst, $src\n"
6870 "skip:" %}
6871 ins_encode %{
6872 Label Lskip;
6873 // Invert sense of branch from sense of CMOV
6874 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
6875 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
6876 __ bind(Lskip);
6877 %}
6878 ins_pipe(pipe_slow);
6879 %}
6880
6881 instruct cmovD_regU(cmpOpU cop, rFlagsRegU cr, regD dst, regD src)
6882 %{
6883 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
6884
6885 ins_cost(200); // XXX
6886 format %{ "jn$cop skip\t# unsigned cmove double\n\t"
6887 "movsd $dst, $src\n"
6888 "skip:" %}
6889 ins_encode %{
6890 Label Lskip;
6891 // Invert sense of branch from sense of CMOV
6892 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
6893 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
6894 __ bind(Lskip);
6895 %}
6896 ins_pipe(pipe_slow);
6897 %}
6898
6899 instruct cmovD_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, regD dst, regD src) %{
6900 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
6901 ins_cost(200);
6902 expand %{
6903 cmovD_regU(cop, cr, dst, src);
6904 %}
6905 %}
6906
6907 //----------Arithmetic Instructions--------------------------------------------
6908 //----------Addition Instructions----------------------------------------------
6909
6910 instruct addI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
6911 %{
6912 match(Set dst (AddI dst src));
6913 effect(KILL cr);
6914
6915 format %{ "addl $dst, $src\t# int" %}
6916 opcode(0x03);
6917 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
6918 ins_pipe(ialu_reg_reg);
6919 %}
6920
6921 instruct addI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
6922 %{
6923 match(Set dst (AddI dst src));
6924 effect(KILL cr);
6925
6926 format %{ "addl $dst, $src\t# int" %}
6927 opcode(0x81, 0x00); /* /0 id */
6928 ins_encode(OpcSErm(dst, src), Con8or32(src));
6929 ins_pipe( ialu_reg );
6930 %}
6931
6932 instruct addI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
6933 %{
6934 match(Set dst (AddI dst (LoadI src)));
6935 effect(KILL cr);
6936
6937 ins_cost(125); // XXX
6938 format %{ "addl $dst, $src\t# int" %}
6939 opcode(0x03);
6940 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
6941 ins_pipe(ialu_reg_mem);
6942 %}
6943
6944 instruct addI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
6945 %{
6946 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
6947 effect(KILL cr);
6948
6949 ins_cost(150); // XXX
6950 format %{ "addl $dst, $src\t# int" %}
6951 opcode(0x01); /* Opcode 01 /r */
6952 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
6953 ins_pipe(ialu_mem_reg);
6954 %}
6955
6956 instruct addI_mem_imm(memory dst, immI src, rFlagsReg cr)
6957 %{
6958 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
6959 effect(KILL cr);
6960
6961 ins_cost(125); // XXX
6962 format %{ "addl $dst, $src\t# int" %}
6963 opcode(0x81); /* Opcode 81 /0 id */
6964 ins_encode(REX_mem(dst), OpcSE(src), RM_opc_mem(0x00, dst), Con8or32(src));
6965 ins_pipe(ialu_mem_imm);
6966 %}
6967
6968 instruct incI_rReg(rRegI dst, immI1 src, rFlagsReg cr)
6969 %{
6970 predicate(UseIncDec);
6971 match(Set dst (AddI dst src));
6972 effect(KILL cr);
6973
6974 format %{ "incl $dst\t# int" %}
6975 opcode(0xFF, 0x00); // FF /0
6976 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
6977 ins_pipe(ialu_reg);
6978 %}
6979
6980 instruct incI_mem(memory dst, immI1 src, rFlagsReg cr)
6981 %{
6982 predicate(UseIncDec);
6983 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
6984 effect(KILL cr);
6985
6986 ins_cost(125); // XXX
6987 format %{ "incl $dst\t# int" %}
6988 opcode(0xFF); /* Opcode FF /0 */
6989 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(0x00, dst));
6990 ins_pipe(ialu_mem_imm);
6991 %}
6992
6993 // XXX why does that use AddI
6994 instruct decI_rReg(rRegI dst, immI_M1 src, rFlagsReg cr)
6995 %{
6996 predicate(UseIncDec);
6997 match(Set dst (AddI dst src));
6998 effect(KILL cr);
6999
7000 format %{ "decl $dst\t# int" %}
7001 opcode(0xFF, 0x01); // FF /1
7002 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
7003 ins_pipe(ialu_reg);
7004 %}
7005
7006 // XXX why does that use AddI
7007 instruct decI_mem(memory dst, immI_M1 src, rFlagsReg cr)
7008 %{
7009 predicate(UseIncDec);
7010 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7011 effect(KILL cr);
7012
7013 ins_cost(125); // XXX
7014 format %{ "decl $dst\t# int" %}
7015 opcode(0xFF); /* Opcode FF /1 */
7016 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(0x01, dst));
7017 ins_pipe(ialu_mem_imm);
7018 %}
7019
7020 instruct leaI_rReg_immI(rRegI dst, rRegI src0, immI src1)
7021 %{
7022 match(Set dst (AddI src0 src1));
7023
7024 ins_cost(110);
7025 format %{ "addr32 leal $dst, [$src0 + $src1]\t# int" %}
7026 opcode(0x8D); /* 0x8D /r */
7027 ins_encode(Opcode(0x67), REX_reg_reg(dst, src0), OpcP, reg_lea(dst, src0, src1)); // XXX
7028 ins_pipe(ialu_reg_reg);
7029 %}
7030
7031 instruct addL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
7032 %{
7033 match(Set dst (AddL dst src));
7034 effect(KILL cr);
7035
7036 format %{ "addq $dst, $src\t# long" %}
7037 opcode(0x03);
7038 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
7039 ins_pipe(ialu_reg_reg);
7040 %}
7041
7042 instruct addL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
7043 %{
7044 match(Set dst (AddL dst src));
7045 effect(KILL cr);
7046
7047 format %{ "addq $dst, $src\t# long" %}
7048 opcode(0x81, 0x00); /* /0 id */
7049 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
7050 ins_pipe( ialu_reg );
7051 %}
7052
7053 instruct addL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
7054 %{
7055 match(Set dst (AddL dst (LoadL src)));
7056 effect(KILL cr);
7057
7058 ins_cost(125); // XXX
7059 format %{ "addq $dst, $src\t# long" %}
7060 opcode(0x03);
7061 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
7062 ins_pipe(ialu_reg_mem);
7063 %}
7064
7065 instruct addL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
7066 %{
7067 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
7068 effect(KILL cr);
7069
7070 ins_cost(150); // XXX
7071 format %{ "addq $dst, $src\t# long" %}
7072 opcode(0x01); /* Opcode 01 /r */
7073 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
7074 ins_pipe(ialu_mem_reg);
7075 %}
7076
7077 instruct addL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
7078 %{
7079 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
7080 effect(KILL cr);
7081
7082 ins_cost(125); // XXX
7083 format %{ "addq $dst, $src\t# long" %}
7084 opcode(0x81); /* Opcode 81 /0 id */
7085 ins_encode(REX_mem_wide(dst),
7086 OpcSE(src), RM_opc_mem(0x00, dst), Con8or32(src));
7087 ins_pipe(ialu_mem_imm);
7088 %}
7089
7090 instruct incL_rReg(rRegI dst, immL1 src, rFlagsReg cr)
7091 %{
7092 predicate(UseIncDec);
7093 match(Set dst (AddL dst src));
7094 effect(KILL cr);
7095
7096 format %{ "incq $dst\t# long" %}
7097 opcode(0xFF, 0x00); // FF /0
7098 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
7099 ins_pipe(ialu_reg);
7100 %}
7101
7102 instruct incL_mem(memory dst, immL1 src, rFlagsReg cr)
7103 %{
7104 predicate(UseIncDec);
7105 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
7106 effect(KILL cr);
7107
7108 ins_cost(125); // XXX
7109 format %{ "incq $dst\t# long" %}
7110 opcode(0xFF); /* Opcode FF /0 */
7111 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(0x00, dst));
7112 ins_pipe(ialu_mem_imm);
7113 %}
7114
7115 // XXX why does that use AddL
7116 instruct decL_rReg(rRegL dst, immL_M1 src, rFlagsReg cr)
7117 %{
7118 predicate(UseIncDec);
7119 match(Set dst (AddL dst src));
7120 effect(KILL cr);
7121
7122 format %{ "decq $dst\t# long" %}
7123 opcode(0xFF, 0x01); // FF /1
7124 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
7125 ins_pipe(ialu_reg);
7126 %}
7127
7128 // XXX why does that use AddL
7129 instruct decL_mem(memory dst, immL_M1 src, rFlagsReg cr)
7130 %{
7131 predicate(UseIncDec);
7132 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
7133 effect(KILL cr);
7134
7135 ins_cost(125); // XXX
7136 format %{ "decq $dst\t# long" %}
7137 opcode(0xFF); /* Opcode FF /1 */
7138 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(0x01, dst));
7139 ins_pipe(ialu_mem_imm);
7140 %}
7141
7142 instruct leaL_rReg_immL(rRegL dst, rRegL src0, immL32 src1)
7143 %{
7144 match(Set dst (AddL src0 src1));
7145
7146 ins_cost(110);
7147 format %{ "leaq $dst, [$src0 + $src1]\t# long" %}
7148 opcode(0x8D); /* 0x8D /r */
7149 ins_encode(REX_reg_reg_wide(dst, src0), OpcP, reg_lea(dst, src0, src1)); // XXX
7150 ins_pipe(ialu_reg_reg);
7151 %}
7152
7153 instruct addP_rReg(rRegP dst, rRegL src, rFlagsReg cr)
7154 %{
7155 match(Set dst (AddP dst src));
7156 effect(KILL cr);
7157
7158 format %{ "addq $dst, $src\t# ptr" %}
7159 opcode(0x03);
7160 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
7161 ins_pipe(ialu_reg_reg);
7162 %}
7163
7164 instruct addP_rReg_imm(rRegP dst, immL32 src, rFlagsReg cr)
7165 %{
7166 match(Set dst (AddP dst src));
7167 effect(KILL cr);
7168
7169 format %{ "addq $dst, $src\t# ptr" %}
7170 opcode(0x81, 0x00); /* /0 id */
7171 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
7172 ins_pipe( ialu_reg );
7173 %}
7174
7175 // XXX addP mem ops ????
7176
7177 instruct leaP_rReg_imm(rRegP dst, rRegP src0, immL32 src1)
7178 %{
7179 match(Set dst (AddP src0 src1));
7180
7181 ins_cost(110);
7182 format %{ "leaq $dst, [$src0 + $src1]\t# ptr" %}
7183 opcode(0x8D); /* 0x8D /r */
7184 ins_encode(REX_reg_reg_wide(dst, src0), OpcP, reg_lea(dst, src0, src1));// XXX
7185 ins_pipe(ialu_reg_reg);
7186 %}
7187
7188 instruct checkCastPP(rRegP dst)
7189 %{
7190 match(Set dst (CheckCastPP dst));
7191
7192 size(0);
7193 format %{ "# checkcastPP of $dst" %}
7194 ins_encode(/* empty encoding */);
7195 ins_pipe(empty);
7196 %}
7197
7198 instruct castPP(rRegP dst)
7199 %{
7200 match(Set dst (CastPP dst));
7201
7202 size(0);
7203 format %{ "# castPP of $dst" %}
7204 ins_encode(/* empty encoding */);
7205 ins_pipe(empty);
7206 %}
7207
7208 instruct castII(rRegI dst)
7209 %{
7210 match(Set dst (CastII dst));
7211
7212 size(0);
7213 format %{ "# castII of $dst" %}
7214 ins_encode(/* empty encoding */);
7215 ins_cost(0);
7216 ins_pipe(empty);
7217 %}
7218
7219 // LoadP-locked same as a regular LoadP when used with compare-swap
7220 instruct loadPLocked(rRegP dst, memory mem)
7221 %{
7222 match(Set dst (LoadPLocked mem));
7223
7224 ins_cost(125); // XXX
7225 format %{ "movq $dst, $mem\t# ptr locked" %}
7226 opcode(0x8B);
7227 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
7228 ins_pipe(ialu_reg_mem); // XXX
7229 %}
7230
7231 // Conditional-store of the updated heap-top.
7232 // Used during allocation of the shared heap.
7233 // Sets flags (EQ) on success. Implemented with a CMPXCHG on Intel.
7234
7235 instruct storePConditional(memory heap_top_ptr,
7236 rax_RegP oldval, rRegP newval,
7237 rFlagsReg cr)
7238 %{
7239 match(Set cr (StorePConditional heap_top_ptr (Binary oldval newval)));
7240
7241 format %{ "cmpxchgq $heap_top_ptr, $newval\t# (ptr) "
7242 "If rax == $heap_top_ptr then store $newval into $heap_top_ptr" %}
7243 opcode(0x0F, 0xB1);
7244 ins_encode(lock_prefix,
7245 REX_reg_mem_wide(newval, heap_top_ptr),
7246 OpcP, OpcS,
7247 reg_mem(newval, heap_top_ptr));
7248 ins_pipe(pipe_cmpxchg);
7249 %}
7250
7251 // Conditional-store of an int value.
7252 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG.
7253 instruct storeIConditional(memory mem, rax_RegI oldval, rRegI newval, rFlagsReg cr)
7254 %{
7255 match(Set cr (StoreIConditional mem (Binary oldval newval)));
7256 effect(KILL oldval);
7257
7258 format %{ "cmpxchgl $mem, $newval\t# If rax == $mem then store $newval into $mem" %}
7259 opcode(0x0F, 0xB1);
7260 ins_encode(lock_prefix,
7261 REX_reg_mem(newval, mem),
7262 OpcP, OpcS,
7263 reg_mem(newval, mem));
7264 ins_pipe(pipe_cmpxchg);
7265 %}
7266
7267 // Conditional-store of a long value.
7268 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG.
7269 instruct storeLConditional(memory mem, rax_RegL oldval, rRegL newval, rFlagsReg cr)
7270 %{
7271 match(Set cr (StoreLConditional mem (Binary oldval newval)));
7272 effect(KILL oldval);
7273
7274 format %{ "cmpxchgq $mem, $newval\t# If rax == $mem then store $newval into $mem" %}
7275 opcode(0x0F, 0xB1);
7276 ins_encode(lock_prefix,
7277 REX_reg_mem_wide(newval, mem),
7278 OpcP, OpcS,
7279 reg_mem(newval, mem));
7280 ins_pipe(pipe_cmpxchg);
7281 %}
7282
7283
7284 // XXX No flag versions for CompareAndSwap{P,I,L} because matcher can't match them
7285 instruct compareAndSwapP(rRegI res,
7286 memory mem_ptr,
7287 rax_RegP oldval, rRegP newval,
7288 rFlagsReg cr)
7289 %{
7290 predicate(VM_Version::supports_cx8());
7291 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
7292 match(Set res (WeakCompareAndSwapP mem_ptr (Binary oldval newval)));
7293 effect(KILL cr, KILL oldval);
7294
7295 format %{ "cmpxchgq $mem_ptr,$newval\t# "
7296 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7297 "sete $res\n\t"
7298 "movzbl $res, $res" %}
7299 opcode(0x0F, 0xB1);
7300 ins_encode(lock_prefix,
7301 REX_reg_mem_wide(newval, mem_ptr),
7302 OpcP, OpcS,
7303 reg_mem(newval, mem_ptr),
7304 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7305 REX_reg_breg(res, res), // movzbl
7306 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7307 ins_pipe( pipe_cmpxchg );
7308 %}
7309
7310 instruct compareAndSwapL(rRegI res,
7311 memory mem_ptr,
7312 rax_RegL oldval, rRegL newval,
7313 rFlagsReg cr)
7314 %{
7315 predicate(VM_Version::supports_cx8());
7316 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
7317 match(Set res (WeakCompareAndSwapL mem_ptr (Binary oldval newval)));
7318 effect(KILL cr, KILL oldval);
7319
7320 format %{ "cmpxchgq $mem_ptr,$newval\t# "
7321 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7322 "sete $res\n\t"
7323 "movzbl $res, $res" %}
7324 opcode(0x0F, 0xB1);
7325 ins_encode(lock_prefix,
7326 REX_reg_mem_wide(newval, mem_ptr),
7327 OpcP, OpcS,
7328 reg_mem(newval, mem_ptr),
7329 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7330 REX_reg_breg(res, res), // movzbl
7331 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7332 ins_pipe( pipe_cmpxchg );
7333 %}
7334
7335 instruct compareAndSwapI(rRegI res,
7336 memory mem_ptr,
7337 rax_RegI oldval, rRegI newval,
7338 rFlagsReg cr)
7339 %{
7340 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
7341 match(Set res (WeakCompareAndSwapI mem_ptr (Binary oldval newval)));
7342 effect(KILL cr, KILL oldval);
7343
7344 format %{ "cmpxchgl $mem_ptr,$newval\t# "
7345 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7346 "sete $res\n\t"
7347 "movzbl $res, $res" %}
7348 opcode(0x0F, 0xB1);
7349 ins_encode(lock_prefix,
7350 REX_reg_mem(newval, mem_ptr),
7351 OpcP, OpcS,
7352 reg_mem(newval, mem_ptr),
7353 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7354 REX_reg_breg(res, res), // movzbl
7355 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7356 ins_pipe( pipe_cmpxchg );
7357 %}
7358
7359 instruct compareAndSwapB(rRegI res,
7360 memory mem_ptr,
7361 rax_RegI oldval, rRegI newval,
7362 rFlagsReg cr)
7363 %{
7364 match(Set res (CompareAndSwapB mem_ptr (Binary oldval newval)));
7365 match(Set res (WeakCompareAndSwapB mem_ptr (Binary oldval newval)));
7366 effect(KILL cr, KILL oldval);
7367
7368 format %{ "cmpxchgb $mem_ptr,$newval\t# "
7369 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7370 "sete $res\n\t"
7371 "movzbl $res, $res" %}
7372 opcode(0x0F, 0xB0);
7373 ins_encode(lock_prefix,
7374 REX_breg_mem(newval, mem_ptr),
7375 OpcP, OpcS,
7376 reg_mem(newval, mem_ptr),
7377 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7378 REX_reg_breg(res, res), // movzbl
7379 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7380 ins_pipe( pipe_cmpxchg );
7381 %}
7382
7383 instruct compareAndSwapS(rRegI res,
7384 memory mem_ptr,
7385 rax_RegI oldval, rRegI newval,
7386 rFlagsReg cr)
7387 %{
7388 match(Set res (CompareAndSwapS mem_ptr (Binary oldval newval)));
7389 match(Set res (WeakCompareAndSwapS mem_ptr (Binary oldval newval)));
7390 effect(KILL cr, KILL oldval);
7391
7392 format %{ "cmpxchgw $mem_ptr,$newval\t# "
7393 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7394 "sete $res\n\t"
7395 "movzbl $res, $res" %}
7396 opcode(0x0F, 0xB1);
7397 ins_encode(lock_prefix,
7398 SizePrefix,
7399 REX_reg_mem(newval, mem_ptr),
7400 OpcP, OpcS,
7401 reg_mem(newval, mem_ptr),
7402 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7403 REX_reg_breg(res, res), // movzbl
7404 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7405 ins_pipe( pipe_cmpxchg );
7406 %}
7407
7408 instruct compareAndSwapN(rRegI res,
7409 memory mem_ptr,
7410 rax_RegN oldval, rRegN newval,
7411 rFlagsReg cr) %{
7412 match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval)));
7413 match(Set res (WeakCompareAndSwapN mem_ptr (Binary oldval newval)));
7414 effect(KILL cr, KILL oldval);
7415
7416 format %{ "cmpxchgl $mem_ptr,$newval\t# "
7417 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7418 "sete $res\n\t"
7419 "movzbl $res, $res" %}
7420 opcode(0x0F, 0xB1);
7421 ins_encode(lock_prefix,
7422 REX_reg_mem(newval, mem_ptr),
7423 OpcP, OpcS,
7424 reg_mem(newval, mem_ptr),
7425 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7426 REX_reg_breg(res, res), // movzbl
7427 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7428 ins_pipe( pipe_cmpxchg );
7429 %}
7430
7431 instruct compareAndExchangeB(
7432 memory mem_ptr,
7433 rax_RegI oldval, rRegI newval,
7434 rFlagsReg cr)
7435 %{
7436 match(Set oldval (CompareAndExchangeB mem_ptr (Binary oldval newval)));
7437 effect(KILL cr);
7438
7439 format %{ "cmpxchgb $mem_ptr,$newval\t# "
7440 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" %}
7441 opcode(0x0F, 0xB0);
7442 ins_encode(lock_prefix,
7443 REX_breg_mem(newval, mem_ptr),
7444 OpcP, OpcS,
7445 reg_mem(newval, mem_ptr) // lock cmpxchg
7446 );
7447 ins_pipe( pipe_cmpxchg );
7448 %}
7449
7450 instruct compareAndExchangeS(
7451 memory mem_ptr,
7452 rax_RegI oldval, rRegI newval,
7453 rFlagsReg cr)
7454 %{
7455 match(Set oldval (CompareAndExchangeS mem_ptr (Binary oldval newval)));
7456 effect(KILL cr);
7457
7458 format %{ "cmpxchgw $mem_ptr,$newval\t# "
7459 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" %}
7460 opcode(0x0F, 0xB1);
7461 ins_encode(lock_prefix,
7462 SizePrefix,
7463 REX_reg_mem(newval, mem_ptr),
7464 OpcP, OpcS,
7465 reg_mem(newval, mem_ptr) // lock cmpxchg
7466 );
7467 ins_pipe( pipe_cmpxchg );
7468 %}
7469
7470 instruct compareAndExchangeI(
7471 memory mem_ptr,
7472 rax_RegI oldval, rRegI newval,
7473 rFlagsReg cr)
7474 %{
7475 match(Set oldval (CompareAndExchangeI mem_ptr (Binary oldval newval)));
7476 effect(KILL cr);
7477
7478 format %{ "cmpxchgl $mem_ptr,$newval\t# "
7479 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" %}
7480 opcode(0x0F, 0xB1);
7481 ins_encode(lock_prefix,
7482 REX_reg_mem(newval, mem_ptr),
7483 OpcP, OpcS,
7484 reg_mem(newval, mem_ptr) // lock cmpxchg
7485 );
7486 ins_pipe( pipe_cmpxchg );
7487 %}
7488
7489 instruct compareAndExchangeL(
7490 memory mem_ptr,
7491 rax_RegL oldval, rRegL newval,
7492 rFlagsReg cr)
7493 %{
7494 predicate(VM_Version::supports_cx8());
7495 match(Set oldval (CompareAndExchangeL mem_ptr (Binary oldval newval)));
7496 effect(KILL cr);
7497
7498 format %{ "cmpxchgq $mem_ptr,$newval\t# "
7499 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" %}
7500 opcode(0x0F, 0xB1);
7501 ins_encode(lock_prefix,
7502 REX_reg_mem_wide(newval, mem_ptr),
7503 OpcP, OpcS,
7504 reg_mem(newval, mem_ptr) // lock cmpxchg
7505 );
7506 ins_pipe( pipe_cmpxchg );
7507 %}
7508
7509 instruct compareAndExchangeN(
7510 memory mem_ptr,
7511 rax_RegN oldval, rRegN newval,
7512 rFlagsReg cr) %{
7513 match(Set oldval (CompareAndExchangeN mem_ptr (Binary oldval newval)));
7514 effect(KILL cr);
7515
7516 format %{ "cmpxchgl $mem_ptr,$newval\t# "
7517 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" %}
7518 opcode(0x0F, 0xB1);
7519 ins_encode(lock_prefix,
7520 REX_reg_mem(newval, mem_ptr),
7521 OpcP, OpcS,
7522 reg_mem(newval, mem_ptr) // lock cmpxchg
7523 );
7524 ins_pipe( pipe_cmpxchg );
7525 %}
7526
7527 instruct compareAndExchangeP(
7528 memory mem_ptr,
7529 rax_RegP oldval, rRegP newval,
7530 rFlagsReg cr)
7531 %{
7532 predicate(VM_Version::supports_cx8());
7533 match(Set oldval (CompareAndExchangeP mem_ptr (Binary oldval newval)));
7534 effect(KILL cr);
7535
7536 format %{ "cmpxchgq $mem_ptr,$newval\t# "
7537 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" %}
7538 opcode(0x0F, 0xB1);
7539 ins_encode(lock_prefix,
7540 REX_reg_mem_wide(newval, mem_ptr),
7541 OpcP, OpcS,
7542 reg_mem(newval, mem_ptr) // lock cmpxchg
7543 );
7544 ins_pipe( pipe_cmpxchg );
7545 %}
7546
7547 instruct xaddB_no_res( memory mem, Universe dummy, immI add, rFlagsReg cr) %{
7548 predicate(n->as_LoadStore()->result_not_used());
7549 match(Set dummy (GetAndAddB mem add));
7550 effect(KILL cr);
7551 format %{ "ADDB [$mem],$add" %}
7552 ins_encode %{
7553 if (os::is_MP()) { __ lock(); }
7554 __ addb($mem$$Address, $add$$constant);
7555 %}
7556 ins_pipe( pipe_cmpxchg );
7557 %}
7558
7559 instruct xaddB( memory mem, rRegI newval, rFlagsReg cr) %{
7560 match(Set newval (GetAndAddB mem newval));
7561 effect(KILL cr);
7562 format %{ "XADDB [$mem],$newval" %}
7563 ins_encode %{
7564 if (os::is_MP()) { __ lock(); }
7565 __ xaddb($mem$$Address, $newval$$Register);
7566 %}
7567 ins_pipe( pipe_cmpxchg );
7568 %}
7569
7570 instruct xaddS_no_res( memory mem, Universe dummy, immI add, rFlagsReg cr) %{
7571 predicate(n->as_LoadStore()->result_not_used());
7572 match(Set dummy (GetAndAddS mem add));
7573 effect(KILL cr);
7574 format %{ "ADDW [$mem],$add" %}
7575 ins_encode %{
7576 if (os::is_MP()) { __ lock(); }
7577 __ addw($mem$$Address, $add$$constant);
7578 %}
7579 ins_pipe( pipe_cmpxchg );
7580 %}
7581
7582 instruct xaddS( memory mem, rRegI newval, rFlagsReg cr) %{
7583 match(Set newval (GetAndAddS mem newval));
7584 effect(KILL cr);
7585 format %{ "XADDW [$mem],$newval" %}
7586 ins_encode %{
7587 if (os::is_MP()) { __ lock(); }
7588 __ xaddw($mem$$Address, $newval$$Register);
7589 %}
7590 ins_pipe( pipe_cmpxchg );
7591 %}
7592
7593 instruct xaddI_no_res( memory mem, Universe dummy, immI add, rFlagsReg cr) %{
7594 predicate(n->as_LoadStore()->result_not_used());
7595 match(Set dummy (GetAndAddI mem add));
7596 effect(KILL cr);
7597 format %{ "ADDL [$mem],$add" %}
7598 ins_encode %{
7599 if (os::is_MP()) { __ lock(); }
7600 __ addl($mem$$Address, $add$$constant);
7601 %}
7602 ins_pipe( pipe_cmpxchg );
7603 %}
7604
7605 instruct xaddI( memory mem, rRegI newval, rFlagsReg cr) %{
7606 match(Set newval (GetAndAddI mem newval));
7607 effect(KILL cr);
7608 format %{ "XADDL [$mem],$newval" %}
7609 ins_encode %{
7610 if (os::is_MP()) { __ lock(); }
7611 __ xaddl($mem$$Address, $newval$$Register);
7612 %}
7613 ins_pipe( pipe_cmpxchg );
7614 %}
7615
7616 instruct xaddL_no_res( memory mem, Universe dummy, immL32 add, rFlagsReg cr) %{
7617 predicate(n->as_LoadStore()->result_not_used());
7618 match(Set dummy (GetAndAddL mem add));
7619 effect(KILL cr);
7620 format %{ "ADDQ [$mem],$add" %}
7621 ins_encode %{
7622 if (os::is_MP()) { __ lock(); }
7623 __ addq($mem$$Address, $add$$constant);
7624 %}
7625 ins_pipe( pipe_cmpxchg );
7626 %}
7627
7628 instruct xaddL( memory mem, rRegL newval, rFlagsReg cr) %{
7629 match(Set newval (GetAndAddL mem newval));
7630 effect(KILL cr);
7631 format %{ "XADDQ [$mem],$newval" %}
7632 ins_encode %{
7633 if (os::is_MP()) { __ lock(); }
7634 __ xaddq($mem$$Address, $newval$$Register);
7635 %}
7636 ins_pipe( pipe_cmpxchg );
7637 %}
7638
7639 instruct xchgB( memory mem, rRegI newval) %{
7640 match(Set newval (GetAndSetB mem newval));
7641 format %{ "XCHGB $newval,[$mem]" %}
7642 ins_encode %{
7643 __ xchgb($newval$$Register, $mem$$Address);
7644 %}
7645 ins_pipe( pipe_cmpxchg );
7646 %}
7647
7648 instruct xchgS( memory mem, rRegI newval) %{
7649 match(Set newval (GetAndSetS mem newval));
7650 format %{ "XCHGW $newval,[$mem]" %}
7651 ins_encode %{
7652 __ xchgw($newval$$Register, $mem$$Address);
7653 %}
7654 ins_pipe( pipe_cmpxchg );
7655 %}
7656
7657 instruct xchgI( memory mem, rRegI newval) %{
7658 match(Set newval (GetAndSetI mem newval));
7659 format %{ "XCHGL $newval,[$mem]" %}
7660 ins_encode %{
7661 __ xchgl($newval$$Register, $mem$$Address);
7662 %}
7663 ins_pipe( pipe_cmpxchg );
7664 %}
7665
7666 instruct xchgL( memory mem, rRegL newval) %{
7667 match(Set newval (GetAndSetL mem newval));
7668 format %{ "XCHGL $newval,[$mem]" %}
7669 ins_encode %{
7670 __ xchgq($newval$$Register, $mem$$Address);
7671 %}
7672 ins_pipe( pipe_cmpxchg );
7673 %}
7674
7675 instruct xchgP( memory mem, rRegP newval) %{
7676 match(Set newval (GetAndSetP mem newval));
7677 format %{ "XCHGQ $newval,[$mem]" %}
7678 ins_encode %{
7679 __ xchgq($newval$$Register, $mem$$Address);
7680 %}
7681 ins_pipe( pipe_cmpxchg );
7682 %}
7683
7684 instruct xchgN( memory mem, rRegN newval) %{
7685 match(Set newval (GetAndSetN mem newval));
7686 format %{ "XCHGL $newval,$mem]" %}
7687 ins_encode %{
7688 __ xchgl($newval$$Register, $mem$$Address);
7689 %}
7690 ins_pipe( pipe_cmpxchg );
7691 %}
7692
7693 //----------Subtraction Instructions-------------------------------------------
7694
7695 // Integer Subtraction Instructions
7696 instruct subI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
7697 %{
7698 match(Set dst (SubI dst src));
7699 effect(KILL cr);
7700
7701 format %{ "subl $dst, $src\t# int" %}
7702 opcode(0x2B);
7703 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
7704 ins_pipe(ialu_reg_reg);
7705 %}
7706
7707 instruct subI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
7708 %{
7709 match(Set dst (SubI dst src));
7710 effect(KILL cr);
7711
7712 format %{ "subl $dst, $src\t# int" %}
7713 opcode(0x81, 0x05); /* Opcode 81 /5 */
7714 ins_encode(OpcSErm(dst, src), Con8or32(src));
7715 ins_pipe(ialu_reg);
7716 %}
7717
7718 instruct subI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
7719 %{
7720 match(Set dst (SubI dst (LoadI src)));
7721 effect(KILL cr);
7722
7723 ins_cost(125);
7724 format %{ "subl $dst, $src\t# int" %}
7725 opcode(0x2B);
7726 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
7727 ins_pipe(ialu_reg_mem);
7728 %}
7729
7730 instruct subI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
7731 %{
7732 match(Set dst (StoreI dst (SubI (LoadI dst) src)));
7733 effect(KILL cr);
7734
7735 ins_cost(150);
7736 format %{ "subl $dst, $src\t# int" %}
7737 opcode(0x29); /* Opcode 29 /r */
7738 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
7739 ins_pipe(ialu_mem_reg);
7740 %}
7741
7742 instruct subI_mem_imm(memory dst, immI src, rFlagsReg cr)
7743 %{
7744 match(Set dst (StoreI dst (SubI (LoadI dst) src)));
7745 effect(KILL cr);
7746
7747 ins_cost(125); // XXX
7748 format %{ "subl $dst, $src\t# int" %}
7749 opcode(0x81); /* Opcode 81 /5 id */
7750 ins_encode(REX_mem(dst), OpcSE(src), RM_opc_mem(0x05, dst), Con8or32(src));
7751 ins_pipe(ialu_mem_imm);
7752 %}
7753
7754 instruct subL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
7755 %{
7756 match(Set dst (SubL dst src));
7757 effect(KILL cr);
7758
7759 format %{ "subq $dst, $src\t# long" %}
7760 opcode(0x2B);
7761 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
7762 ins_pipe(ialu_reg_reg);
7763 %}
7764
7765 instruct subL_rReg_imm(rRegI dst, immL32 src, rFlagsReg cr)
7766 %{
7767 match(Set dst (SubL dst src));
7768 effect(KILL cr);
7769
7770 format %{ "subq $dst, $src\t# long" %}
7771 opcode(0x81, 0x05); /* Opcode 81 /5 */
7772 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
7773 ins_pipe(ialu_reg);
7774 %}
7775
7776 instruct subL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
7777 %{
7778 match(Set dst (SubL dst (LoadL src)));
7779 effect(KILL cr);
7780
7781 ins_cost(125);
7782 format %{ "subq $dst, $src\t# long" %}
7783 opcode(0x2B);
7784 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
7785 ins_pipe(ialu_reg_mem);
7786 %}
7787
7788 instruct subL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
7789 %{
7790 match(Set dst (StoreL dst (SubL (LoadL dst) src)));
7791 effect(KILL cr);
7792
7793 ins_cost(150);
7794 format %{ "subq $dst, $src\t# long" %}
7795 opcode(0x29); /* Opcode 29 /r */
7796 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
7797 ins_pipe(ialu_mem_reg);
7798 %}
7799
7800 instruct subL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
7801 %{
7802 match(Set dst (StoreL dst (SubL (LoadL dst) src)));
7803 effect(KILL cr);
7804
7805 ins_cost(125); // XXX
7806 format %{ "subq $dst, $src\t# long" %}
7807 opcode(0x81); /* Opcode 81 /5 id */
7808 ins_encode(REX_mem_wide(dst),
7809 OpcSE(src), RM_opc_mem(0x05, dst), Con8or32(src));
7810 ins_pipe(ialu_mem_imm);
7811 %}
7812
7813 // Subtract from a pointer
7814 // XXX hmpf???
7815 instruct subP_rReg(rRegP dst, rRegI src, immI0 zero, rFlagsReg cr)
7816 %{
7817 match(Set dst (AddP dst (SubI zero src)));
7818 effect(KILL cr);
7819
7820 format %{ "subq $dst, $src\t# ptr - int" %}
7821 opcode(0x2B);
7822 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
7823 ins_pipe(ialu_reg_reg);
7824 %}
7825
7826 instruct negI_rReg(rRegI dst, immI0 zero, rFlagsReg cr)
7827 %{
7828 match(Set dst (SubI zero dst));
7829 effect(KILL cr);
7830
7831 format %{ "negl $dst\t# int" %}
7832 opcode(0xF7, 0x03); // Opcode F7 /3
7833 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
7834 ins_pipe(ialu_reg);
7835 %}
7836
7837 instruct negI_mem(memory dst, immI0 zero, rFlagsReg cr)
7838 %{
7839 match(Set dst (StoreI dst (SubI zero (LoadI dst))));
7840 effect(KILL cr);
7841
7842 format %{ "negl $dst\t# int" %}
7843 opcode(0xF7, 0x03); // Opcode F7 /3
7844 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
7845 ins_pipe(ialu_reg);
7846 %}
7847
7848 instruct negL_rReg(rRegL dst, immL0 zero, rFlagsReg cr)
7849 %{
7850 match(Set dst (SubL zero dst));
7851 effect(KILL cr);
7852
7853 format %{ "negq $dst\t# long" %}
7854 opcode(0xF7, 0x03); // Opcode F7 /3
7855 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
7856 ins_pipe(ialu_reg);
7857 %}
7858
7859 instruct negL_mem(memory dst, immL0 zero, rFlagsReg cr)
7860 %{
7861 match(Set dst (StoreL dst (SubL zero (LoadL dst))));
7862 effect(KILL cr);
7863
7864 format %{ "negq $dst\t# long" %}
7865 opcode(0xF7, 0x03); // Opcode F7 /3
7866 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
7867 ins_pipe(ialu_reg);
7868 %}
7869
7870 //----------Multiplication/Division Instructions-------------------------------
7871 // Integer Multiplication Instructions
7872 // Multiply Register
7873
7874 instruct mulI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
7875 %{
7876 match(Set dst (MulI dst src));
7877 effect(KILL cr);
7878
7879 ins_cost(300);
7880 format %{ "imull $dst, $src\t# int" %}
7881 opcode(0x0F, 0xAF);
7882 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
7883 ins_pipe(ialu_reg_reg_alu0);
7884 %}
7885
7886 instruct mulI_rReg_imm(rRegI dst, rRegI src, immI imm, rFlagsReg cr)
7887 %{
7888 match(Set dst (MulI src imm));
7889 effect(KILL cr);
7890
7891 ins_cost(300);
7892 format %{ "imull $dst, $src, $imm\t# int" %}
7893 opcode(0x69); /* 69 /r id */
7894 ins_encode(REX_reg_reg(dst, src),
7895 OpcSE(imm), reg_reg(dst, src), Con8or32(imm));
7896 ins_pipe(ialu_reg_reg_alu0);
7897 %}
7898
7899 instruct mulI_mem(rRegI dst, memory src, rFlagsReg cr)
7900 %{
7901 match(Set dst (MulI dst (LoadI src)));
7902 effect(KILL cr);
7903
7904 ins_cost(350);
7905 format %{ "imull $dst, $src\t# int" %}
7906 opcode(0x0F, 0xAF);
7907 ins_encode(REX_reg_mem(dst, src), OpcP, OpcS, reg_mem(dst, src));
7908 ins_pipe(ialu_reg_mem_alu0);
7909 %}
7910
7911 instruct mulI_mem_imm(rRegI dst, memory src, immI imm, rFlagsReg cr)
7912 %{
7913 match(Set dst (MulI (LoadI src) imm));
7914 effect(KILL cr);
7915
7916 ins_cost(300);
7917 format %{ "imull $dst, $src, $imm\t# int" %}
7918 opcode(0x69); /* 69 /r id */
7919 ins_encode(REX_reg_mem(dst, src),
7920 OpcSE(imm), reg_mem(dst, src), Con8or32(imm));
7921 ins_pipe(ialu_reg_mem_alu0);
7922 %}
7923
7924 instruct mulL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
7925 %{
7926 match(Set dst (MulL dst src));
7927 effect(KILL cr);
7928
7929 ins_cost(300);
7930 format %{ "imulq $dst, $src\t# long" %}
7931 opcode(0x0F, 0xAF);
7932 ins_encode(REX_reg_reg_wide(dst, src), OpcP, OpcS, reg_reg(dst, src));
7933 ins_pipe(ialu_reg_reg_alu0);
7934 %}
7935
7936 instruct mulL_rReg_imm(rRegL dst, rRegL src, immL32 imm, rFlagsReg cr)
7937 %{
7938 match(Set dst (MulL src imm));
7939 effect(KILL cr);
7940
7941 ins_cost(300);
7942 format %{ "imulq $dst, $src, $imm\t# long" %}
7943 opcode(0x69); /* 69 /r id */
7944 ins_encode(REX_reg_reg_wide(dst, src),
7945 OpcSE(imm), reg_reg(dst, src), Con8or32(imm));
7946 ins_pipe(ialu_reg_reg_alu0);
7947 %}
7948
7949 instruct mulL_mem(rRegL dst, memory src, rFlagsReg cr)
7950 %{
7951 match(Set dst (MulL dst (LoadL src)));
7952 effect(KILL cr);
7953
7954 ins_cost(350);
7955 format %{ "imulq $dst, $src\t# long" %}
7956 opcode(0x0F, 0xAF);
7957 ins_encode(REX_reg_mem_wide(dst, src), OpcP, OpcS, reg_mem(dst, src));
7958 ins_pipe(ialu_reg_mem_alu0);
7959 %}
7960
7961 instruct mulL_mem_imm(rRegL dst, memory src, immL32 imm, rFlagsReg cr)
7962 %{
7963 match(Set dst (MulL (LoadL src) imm));
7964 effect(KILL cr);
7965
7966 ins_cost(300);
7967 format %{ "imulq $dst, $src, $imm\t# long" %}
7968 opcode(0x69); /* 69 /r id */
7969 ins_encode(REX_reg_mem_wide(dst, src),
7970 OpcSE(imm), reg_mem(dst, src), Con8or32(imm));
7971 ins_pipe(ialu_reg_mem_alu0);
7972 %}
7973
7974 instruct mulHiL_rReg(rdx_RegL dst, no_rax_RegL src, rax_RegL rax, rFlagsReg cr)
7975 %{
7976 match(Set dst (MulHiL src rax));
7977 effect(USE_KILL rax, KILL cr);
7978
7979 ins_cost(300);
7980 format %{ "imulq RDX:RAX, RAX, $src\t# mulhi" %}
7981 opcode(0xF7, 0x5); /* Opcode F7 /5 */
7982 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src));
7983 ins_pipe(ialu_reg_reg_alu0);
7984 %}
7985
7986 instruct divI_rReg(rax_RegI rax, rdx_RegI rdx, no_rax_rdx_RegI div,
7987 rFlagsReg cr)
7988 %{
7989 match(Set rax (DivI rax div));
7990 effect(KILL rdx, KILL cr);
7991
7992 ins_cost(30*100+10*100); // XXX
7993 format %{ "cmpl rax, 0x80000000\t# idiv\n\t"
7994 "jne,s normal\n\t"
7995 "xorl rdx, rdx\n\t"
7996 "cmpl $div, -1\n\t"
7997 "je,s done\n"
7998 "normal: cdql\n\t"
7999 "idivl $div\n"
8000 "done:" %}
8001 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8002 ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div));
8003 ins_pipe(ialu_reg_reg_alu0);
8004 %}
8005
8006 instruct divL_rReg(rax_RegL rax, rdx_RegL rdx, no_rax_rdx_RegL div,
8007 rFlagsReg cr)
8008 %{
8009 match(Set rax (DivL rax div));
8010 effect(KILL rdx, KILL cr);
8011
8012 ins_cost(30*100+10*100); // XXX
8013 format %{ "movq rdx, 0x8000000000000000\t# ldiv\n\t"
8014 "cmpq rax, rdx\n\t"
8015 "jne,s normal\n\t"
8016 "xorl rdx, rdx\n\t"
8017 "cmpq $div, -1\n\t"
8018 "je,s done\n"
8019 "normal: cdqq\n\t"
8020 "idivq $div\n"
8021 "done:" %}
8022 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8023 ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div));
8024 ins_pipe(ialu_reg_reg_alu0);
8025 %}
8026
8027 // Integer DIVMOD with Register, both quotient and mod results
8028 instruct divModI_rReg_divmod(rax_RegI rax, rdx_RegI rdx, no_rax_rdx_RegI div,
8029 rFlagsReg cr)
8030 %{
8031 match(DivModI rax div);
8032 effect(KILL cr);
8033
8034 ins_cost(30*100+10*100); // XXX
8035 format %{ "cmpl rax, 0x80000000\t# idiv\n\t"
8036 "jne,s normal\n\t"
8037 "xorl rdx, rdx\n\t"
8038 "cmpl $div, -1\n\t"
8039 "je,s done\n"
8040 "normal: cdql\n\t"
8041 "idivl $div\n"
8042 "done:" %}
8043 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8044 ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div));
8045 ins_pipe(pipe_slow);
8046 %}
8047
8048 // Long DIVMOD with Register, both quotient and mod results
8049 instruct divModL_rReg_divmod(rax_RegL rax, rdx_RegL rdx, no_rax_rdx_RegL div,
8050 rFlagsReg cr)
8051 %{
8052 match(DivModL rax div);
8053 effect(KILL cr);
8054
8055 ins_cost(30*100+10*100); // XXX
8056 format %{ "movq rdx, 0x8000000000000000\t# ldiv\n\t"
8057 "cmpq rax, rdx\n\t"
8058 "jne,s normal\n\t"
8059 "xorl rdx, rdx\n\t"
8060 "cmpq $div, -1\n\t"
8061 "je,s done\n"
8062 "normal: cdqq\n\t"
8063 "idivq $div\n"
8064 "done:" %}
8065 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8066 ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div));
8067 ins_pipe(pipe_slow);
8068 %}
8069
8070 //----------- DivL-By-Constant-Expansions--------------------------------------
8071 // DivI cases are handled by the compiler
8072
8073 // Magic constant, reciprocal of 10
8074 instruct loadConL_0x6666666666666667(rRegL dst)
8075 %{
8076 effect(DEF dst);
8077
8078 format %{ "movq $dst, #0x666666666666667\t# Used in div-by-10" %}
8079 ins_encode(load_immL(dst, 0x6666666666666667));
8080 ins_pipe(ialu_reg);
8081 %}
8082
8083 instruct mul_hi(rdx_RegL dst, no_rax_RegL src, rax_RegL rax, rFlagsReg cr)
8084 %{
8085 effect(DEF dst, USE src, USE_KILL rax, KILL cr);
8086
8087 format %{ "imulq rdx:rax, rax, $src\t# Used in div-by-10" %}
8088 opcode(0xF7, 0x5); /* Opcode F7 /5 */
8089 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src));
8090 ins_pipe(ialu_reg_reg_alu0);
8091 %}
8092
8093 instruct sarL_rReg_63(rRegL dst, rFlagsReg cr)
8094 %{
8095 effect(USE_DEF dst, KILL cr);
8096
8097 format %{ "sarq $dst, #63\t# Used in div-by-10" %}
8098 opcode(0xC1, 0x7); /* C1 /7 ib */
8099 ins_encode(reg_opc_imm_wide(dst, 0x3F));
8100 ins_pipe(ialu_reg);
8101 %}
8102
8103 instruct sarL_rReg_2(rRegL dst, rFlagsReg cr)
8104 %{
8105 effect(USE_DEF dst, KILL cr);
8106
8107 format %{ "sarq $dst, #2\t# Used in div-by-10" %}
8108 opcode(0xC1, 0x7); /* C1 /7 ib */
8109 ins_encode(reg_opc_imm_wide(dst, 0x2));
8110 ins_pipe(ialu_reg);
8111 %}
8112
8113 instruct divL_10(rdx_RegL dst, no_rax_RegL src, immL10 div)
8114 %{
8115 match(Set dst (DivL src div));
8116
8117 ins_cost((5+8)*100);
8118 expand %{
8119 rax_RegL rax; // Killed temp
8120 rFlagsReg cr; // Killed
8121 loadConL_0x6666666666666667(rax); // movq rax, 0x6666666666666667
8122 mul_hi(dst, src, rax, cr); // mulq rdx:rax <= rax * $src
8123 sarL_rReg_63(src, cr); // sarq src, 63
8124 sarL_rReg_2(dst, cr); // sarq rdx, 2
8125 subL_rReg(dst, src, cr); // subl rdx, src
8126 %}
8127 %}
8128
8129 //-----------------------------------------------------------------------------
8130
8131 instruct modI_rReg(rdx_RegI rdx, rax_RegI rax, no_rax_rdx_RegI div,
8132 rFlagsReg cr)
8133 %{
8134 match(Set rdx (ModI rax div));
8135 effect(KILL rax, KILL cr);
8136
8137 ins_cost(300); // XXX
8138 format %{ "cmpl rax, 0x80000000\t# irem\n\t"
8139 "jne,s normal\n\t"
8140 "xorl rdx, rdx\n\t"
8141 "cmpl $div, -1\n\t"
8142 "je,s done\n"
8143 "normal: cdql\n\t"
8144 "idivl $div\n"
8145 "done:" %}
8146 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8147 ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div));
8148 ins_pipe(ialu_reg_reg_alu0);
8149 %}
8150
8151 instruct modL_rReg(rdx_RegL rdx, rax_RegL rax, no_rax_rdx_RegL div,
8152 rFlagsReg cr)
8153 %{
8154 match(Set rdx (ModL rax div));
8155 effect(KILL rax, KILL cr);
8156
8157 ins_cost(300); // XXX
8158 format %{ "movq rdx, 0x8000000000000000\t# lrem\n\t"
8159 "cmpq rax, rdx\n\t"
8160 "jne,s normal\n\t"
8161 "xorl rdx, rdx\n\t"
8162 "cmpq $div, -1\n\t"
8163 "je,s done\n"
8164 "normal: cdqq\n\t"
8165 "idivq $div\n"
8166 "done:" %}
8167 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8168 ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div));
8169 ins_pipe(ialu_reg_reg_alu0);
8170 %}
8171
8172 // Integer Shift Instructions
8173 // Shift Left by one
8174 instruct salI_rReg_1(rRegI dst, immI1 shift, rFlagsReg cr)
8175 %{
8176 match(Set dst (LShiftI dst shift));
8177 effect(KILL cr);
8178
8179 format %{ "sall $dst, $shift" %}
8180 opcode(0xD1, 0x4); /* D1 /4 */
8181 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8182 ins_pipe(ialu_reg);
8183 %}
8184
8185 // Shift Left by one
8186 instruct salI_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8187 %{
8188 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift)));
8189 effect(KILL cr);
8190
8191 format %{ "sall $dst, $shift\t" %}
8192 opcode(0xD1, 0x4); /* D1 /4 */
8193 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8194 ins_pipe(ialu_mem_imm);
8195 %}
8196
8197 // Shift Left by 8-bit immediate
8198 instruct salI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr)
8199 %{
8200 match(Set dst (LShiftI dst shift));
8201 effect(KILL cr);
8202
8203 format %{ "sall $dst, $shift" %}
8204 opcode(0xC1, 0x4); /* C1 /4 ib */
8205 ins_encode(reg_opc_imm(dst, shift));
8206 ins_pipe(ialu_reg);
8207 %}
8208
8209 // Shift Left by 8-bit immediate
8210 instruct salI_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8211 %{
8212 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift)));
8213 effect(KILL cr);
8214
8215 format %{ "sall $dst, $shift" %}
8216 opcode(0xC1, 0x4); /* C1 /4 ib */
8217 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst), Con8or32(shift));
8218 ins_pipe(ialu_mem_imm);
8219 %}
8220
8221 // Shift Left by variable
8222 instruct salI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr)
8223 %{
8224 match(Set dst (LShiftI dst shift));
8225 effect(KILL cr);
8226
8227 format %{ "sall $dst, $shift" %}
8228 opcode(0xD3, 0x4); /* D3 /4 */
8229 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8230 ins_pipe(ialu_reg_reg);
8231 %}
8232
8233 // Shift Left by variable
8234 instruct salI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8235 %{
8236 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift)));
8237 effect(KILL cr);
8238
8239 format %{ "sall $dst, $shift" %}
8240 opcode(0xD3, 0x4); /* D3 /4 */
8241 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8242 ins_pipe(ialu_mem_reg);
8243 %}
8244
8245 // Arithmetic shift right by one
8246 instruct sarI_rReg_1(rRegI dst, immI1 shift, rFlagsReg cr)
8247 %{
8248 match(Set dst (RShiftI dst shift));
8249 effect(KILL cr);
8250
8251 format %{ "sarl $dst, $shift" %}
8252 opcode(0xD1, 0x7); /* D1 /7 */
8253 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8254 ins_pipe(ialu_reg);
8255 %}
8256
8257 // Arithmetic shift right by one
8258 instruct sarI_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8259 %{
8260 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8261 effect(KILL cr);
8262
8263 format %{ "sarl $dst, $shift" %}
8264 opcode(0xD1, 0x7); /* D1 /7 */
8265 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8266 ins_pipe(ialu_mem_imm);
8267 %}
8268
8269 // Arithmetic Shift Right by 8-bit immediate
8270 instruct sarI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr)
8271 %{
8272 match(Set dst (RShiftI dst shift));
8273 effect(KILL cr);
8274
8275 format %{ "sarl $dst, $shift" %}
8276 opcode(0xC1, 0x7); /* C1 /7 ib */
8277 ins_encode(reg_opc_imm(dst, shift));
8278 ins_pipe(ialu_mem_imm);
8279 %}
8280
8281 // Arithmetic Shift Right by 8-bit immediate
8282 instruct sarI_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8283 %{
8284 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8285 effect(KILL cr);
8286
8287 format %{ "sarl $dst, $shift" %}
8288 opcode(0xC1, 0x7); /* C1 /7 ib */
8289 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst), Con8or32(shift));
8290 ins_pipe(ialu_mem_imm);
8291 %}
8292
8293 // Arithmetic Shift Right by variable
8294 instruct sarI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr)
8295 %{
8296 match(Set dst (RShiftI dst shift));
8297 effect(KILL cr);
8298
8299 format %{ "sarl $dst, $shift" %}
8300 opcode(0xD3, 0x7); /* D3 /7 */
8301 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8302 ins_pipe(ialu_reg_reg);
8303 %}
8304
8305 // Arithmetic Shift Right by variable
8306 instruct sarI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8307 %{
8308 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8309 effect(KILL cr);
8310
8311 format %{ "sarl $dst, $shift" %}
8312 opcode(0xD3, 0x7); /* D3 /7 */
8313 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8314 ins_pipe(ialu_mem_reg);
8315 %}
8316
8317 // Logical shift right by one
8318 instruct shrI_rReg_1(rRegI dst, immI1 shift, rFlagsReg cr)
8319 %{
8320 match(Set dst (URShiftI dst shift));
8321 effect(KILL cr);
8322
8323 format %{ "shrl $dst, $shift" %}
8324 opcode(0xD1, 0x5); /* D1 /5 */
8325 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8326 ins_pipe(ialu_reg);
8327 %}
8328
8329 // Logical shift right by one
8330 instruct shrI_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8331 %{
8332 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift)));
8333 effect(KILL cr);
8334
8335 format %{ "shrl $dst, $shift" %}
8336 opcode(0xD1, 0x5); /* D1 /5 */
8337 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8338 ins_pipe(ialu_mem_imm);
8339 %}
8340
8341 // Logical Shift Right by 8-bit immediate
8342 instruct shrI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr)
8343 %{
8344 match(Set dst (URShiftI dst shift));
8345 effect(KILL cr);
8346
8347 format %{ "shrl $dst, $shift" %}
8348 opcode(0xC1, 0x5); /* C1 /5 ib */
8349 ins_encode(reg_opc_imm(dst, shift));
8350 ins_pipe(ialu_reg);
8351 %}
8352
8353 // Logical Shift Right by 8-bit immediate
8354 instruct shrI_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8355 %{
8356 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift)));
8357 effect(KILL cr);
8358
8359 format %{ "shrl $dst, $shift" %}
8360 opcode(0xC1, 0x5); /* C1 /5 ib */
8361 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst), Con8or32(shift));
8362 ins_pipe(ialu_mem_imm);
8363 %}
8364
8365 // Logical Shift Right by variable
8366 instruct shrI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr)
8367 %{
8368 match(Set dst (URShiftI dst shift));
8369 effect(KILL cr);
8370
8371 format %{ "shrl $dst, $shift" %}
8372 opcode(0xD3, 0x5); /* D3 /5 */
8373 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8374 ins_pipe(ialu_reg_reg);
8375 %}
8376
8377 // Logical Shift Right by variable
8378 instruct shrI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8379 %{
8380 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift)));
8381 effect(KILL cr);
8382
8383 format %{ "shrl $dst, $shift" %}
8384 opcode(0xD3, 0x5); /* D3 /5 */
8385 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8386 ins_pipe(ialu_mem_reg);
8387 %}
8388
8389 // Long Shift Instructions
8390 // Shift Left by one
8391 instruct salL_rReg_1(rRegL dst, immI1 shift, rFlagsReg cr)
8392 %{
8393 match(Set dst (LShiftL dst shift));
8394 effect(KILL cr);
8395
8396 format %{ "salq $dst, $shift" %}
8397 opcode(0xD1, 0x4); /* D1 /4 */
8398 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8399 ins_pipe(ialu_reg);
8400 %}
8401
8402 // Shift Left by one
8403 instruct salL_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8404 %{
8405 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift)));
8406 effect(KILL cr);
8407
8408 format %{ "salq $dst, $shift" %}
8409 opcode(0xD1, 0x4); /* D1 /4 */
8410 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8411 ins_pipe(ialu_mem_imm);
8412 %}
8413
8414 // Shift Left by 8-bit immediate
8415 instruct salL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr)
8416 %{
8417 match(Set dst (LShiftL dst shift));
8418 effect(KILL cr);
8419
8420 format %{ "salq $dst, $shift" %}
8421 opcode(0xC1, 0x4); /* C1 /4 ib */
8422 ins_encode(reg_opc_imm_wide(dst, shift));
8423 ins_pipe(ialu_reg);
8424 %}
8425
8426 // Shift Left by 8-bit immediate
8427 instruct salL_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8428 %{
8429 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift)));
8430 effect(KILL cr);
8431
8432 format %{ "salq $dst, $shift" %}
8433 opcode(0xC1, 0x4); /* C1 /4 ib */
8434 ins_encode(REX_mem_wide(dst), OpcP,
8435 RM_opc_mem(secondary, dst), Con8or32(shift));
8436 ins_pipe(ialu_mem_imm);
8437 %}
8438
8439 // Shift Left by variable
8440 instruct salL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr)
8441 %{
8442 match(Set dst (LShiftL dst shift));
8443 effect(KILL cr);
8444
8445 format %{ "salq $dst, $shift" %}
8446 opcode(0xD3, 0x4); /* D3 /4 */
8447 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8448 ins_pipe(ialu_reg_reg);
8449 %}
8450
8451 // Shift Left by variable
8452 instruct salL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8453 %{
8454 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift)));
8455 effect(KILL cr);
8456
8457 format %{ "salq $dst, $shift" %}
8458 opcode(0xD3, 0x4); /* D3 /4 */
8459 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8460 ins_pipe(ialu_mem_reg);
8461 %}
8462
8463 // Arithmetic shift right by one
8464 instruct sarL_rReg_1(rRegL dst, immI1 shift, rFlagsReg cr)
8465 %{
8466 match(Set dst (RShiftL dst shift));
8467 effect(KILL cr);
8468
8469 format %{ "sarq $dst, $shift" %}
8470 opcode(0xD1, 0x7); /* D1 /7 */
8471 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8472 ins_pipe(ialu_reg);
8473 %}
8474
8475 // Arithmetic shift right by one
8476 instruct sarL_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8477 %{
8478 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift)));
8479 effect(KILL cr);
8480
8481 format %{ "sarq $dst, $shift" %}
8482 opcode(0xD1, 0x7); /* D1 /7 */
8483 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8484 ins_pipe(ialu_mem_imm);
8485 %}
8486
8487 // Arithmetic Shift Right by 8-bit immediate
8488 instruct sarL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr)
8489 %{
8490 match(Set dst (RShiftL dst shift));
8491 effect(KILL cr);
8492
8493 format %{ "sarq $dst, $shift" %}
8494 opcode(0xC1, 0x7); /* C1 /7 ib */
8495 ins_encode(reg_opc_imm_wide(dst, shift));
8496 ins_pipe(ialu_mem_imm);
8497 %}
8498
8499 // Arithmetic Shift Right by 8-bit immediate
8500 instruct sarL_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8501 %{
8502 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift)));
8503 effect(KILL cr);
8504
8505 format %{ "sarq $dst, $shift" %}
8506 opcode(0xC1, 0x7); /* C1 /7 ib */
8507 ins_encode(REX_mem_wide(dst), OpcP,
8508 RM_opc_mem(secondary, dst), Con8or32(shift));
8509 ins_pipe(ialu_mem_imm);
8510 %}
8511
8512 // Arithmetic Shift Right by variable
8513 instruct sarL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr)
8514 %{
8515 match(Set dst (RShiftL dst shift));
8516 effect(KILL cr);
8517
8518 format %{ "sarq $dst, $shift" %}
8519 opcode(0xD3, 0x7); /* D3 /7 */
8520 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8521 ins_pipe(ialu_reg_reg);
8522 %}
8523
8524 // Arithmetic Shift Right by variable
8525 instruct sarL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8526 %{
8527 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift)));
8528 effect(KILL cr);
8529
8530 format %{ "sarq $dst, $shift" %}
8531 opcode(0xD3, 0x7); /* D3 /7 */
8532 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8533 ins_pipe(ialu_mem_reg);
8534 %}
8535
8536 // Logical shift right by one
8537 instruct shrL_rReg_1(rRegL dst, immI1 shift, rFlagsReg cr)
8538 %{
8539 match(Set dst (URShiftL dst shift));
8540 effect(KILL cr);
8541
8542 format %{ "shrq $dst, $shift" %}
8543 opcode(0xD1, 0x5); /* D1 /5 */
8544 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst ));
8545 ins_pipe(ialu_reg);
8546 %}
8547
8548 // Logical shift right by one
8549 instruct shrL_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8550 %{
8551 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift)));
8552 effect(KILL cr);
8553
8554 format %{ "shrq $dst, $shift" %}
8555 opcode(0xD1, 0x5); /* D1 /5 */
8556 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8557 ins_pipe(ialu_mem_imm);
8558 %}
8559
8560 // Logical Shift Right by 8-bit immediate
8561 instruct shrL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr)
8562 %{
8563 match(Set dst (URShiftL dst shift));
8564 effect(KILL cr);
8565
8566 format %{ "shrq $dst, $shift" %}
8567 opcode(0xC1, 0x5); /* C1 /5 ib */
8568 ins_encode(reg_opc_imm_wide(dst, shift));
8569 ins_pipe(ialu_reg);
8570 %}
8571
8572
8573 // Logical Shift Right by 8-bit immediate
8574 instruct shrL_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8575 %{
8576 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift)));
8577 effect(KILL cr);
8578
8579 format %{ "shrq $dst, $shift" %}
8580 opcode(0xC1, 0x5); /* C1 /5 ib */
8581 ins_encode(REX_mem_wide(dst), OpcP,
8582 RM_opc_mem(secondary, dst), Con8or32(shift));
8583 ins_pipe(ialu_mem_imm);
8584 %}
8585
8586 // Logical Shift Right by variable
8587 instruct shrL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr)
8588 %{
8589 match(Set dst (URShiftL dst shift));
8590 effect(KILL cr);
8591
8592 format %{ "shrq $dst, $shift" %}
8593 opcode(0xD3, 0x5); /* D3 /5 */
8594 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8595 ins_pipe(ialu_reg_reg);
8596 %}
8597
8598 // Logical Shift Right by variable
8599 instruct shrL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8600 %{
8601 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift)));
8602 effect(KILL cr);
8603
8604 format %{ "shrq $dst, $shift" %}
8605 opcode(0xD3, 0x5); /* D3 /5 */
8606 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8607 ins_pipe(ialu_mem_reg);
8608 %}
8609
8610 // Logical Shift Right by 24, followed by Arithmetic Shift Left by 24.
8611 // This idiom is used by the compiler for the i2b bytecode.
8612 instruct i2b(rRegI dst, rRegI src, immI_24 twentyfour)
8613 %{
8614 match(Set dst (RShiftI (LShiftI src twentyfour) twentyfour));
8615
8616 format %{ "movsbl $dst, $src\t# i2b" %}
8617 opcode(0x0F, 0xBE);
8618 ins_encode(REX_reg_breg(dst, src), OpcP, OpcS, reg_reg(dst, src));
8619 ins_pipe(ialu_reg_reg);
8620 %}
8621
8622 // Logical Shift Right by 16, followed by Arithmetic Shift Left by 16.
8623 // This idiom is used by the compiler the i2s bytecode.
8624 instruct i2s(rRegI dst, rRegI src, immI_16 sixteen)
8625 %{
8626 match(Set dst (RShiftI (LShiftI src sixteen) sixteen));
8627
8628 format %{ "movswl $dst, $src\t# i2s" %}
8629 opcode(0x0F, 0xBF);
8630 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
8631 ins_pipe(ialu_reg_reg);
8632 %}
8633
8634 // ROL/ROR instructions
8635
8636 // ROL expand
8637 instruct rolI_rReg_imm1(rRegI dst, rFlagsReg cr) %{
8638 effect(KILL cr, USE_DEF dst);
8639
8640 format %{ "roll $dst" %}
8641 opcode(0xD1, 0x0); /* Opcode D1 /0 */
8642 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8643 ins_pipe(ialu_reg);
8644 %}
8645
8646 instruct rolI_rReg_imm8(rRegI dst, immI8 shift, rFlagsReg cr) %{
8647 effect(USE_DEF dst, USE shift, KILL cr);
8648
8649 format %{ "roll $dst, $shift" %}
8650 opcode(0xC1, 0x0); /* Opcode C1 /0 ib */
8651 ins_encode( reg_opc_imm(dst, shift) );
8652 ins_pipe(ialu_reg);
8653 %}
8654
8655 instruct rolI_rReg_CL(no_rcx_RegI dst, rcx_RegI shift, rFlagsReg cr)
8656 %{
8657 effect(USE_DEF dst, USE shift, KILL cr);
8658
8659 format %{ "roll $dst, $shift" %}
8660 opcode(0xD3, 0x0); /* Opcode D3 /0 */
8661 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8662 ins_pipe(ialu_reg_reg);
8663 %}
8664 // end of ROL expand
8665
8666 // Rotate Left by one
8667 instruct rolI_rReg_i1(rRegI dst, immI1 lshift, immI_M1 rshift, rFlagsReg cr)
8668 %{
8669 match(Set dst (OrI (LShiftI dst lshift) (URShiftI dst rshift)));
8670
8671 expand %{
8672 rolI_rReg_imm1(dst, cr);
8673 %}
8674 %}
8675
8676 // Rotate Left by 8-bit immediate
8677 instruct rolI_rReg_i8(rRegI dst, immI8 lshift, immI8 rshift, rFlagsReg cr)
8678 %{
8679 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8680 match(Set dst (OrI (LShiftI dst lshift) (URShiftI dst rshift)));
8681
8682 expand %{
8683 rolI_rReg_imm8(dst, lshift, cr);
8684 %}
8685 %}
8686
8687 // Rotate Left by variable
8688 instruct rolI_rReg_Var_C0(no_rcx_RegI dst, rcx_RegI shift, immI0 zero, rFlagsReg cr)
8689 %{
8690 match(Set dst (OrI (LShiftI dst shift) (URShiftI dst (SubI zero shift))));
8691
8692 expand %{
8693 rolI_rReg_CL(dst, shift, cr);
8694 %}
8695 %}
8696
8697 // Rotate Left by variable
8698 instruct rolI_rReg_Var_C32(no_rcx_RegI dst, rcx_RegI shift, immI_32 c32, rFlagsReg cr)
8699 %{
8700 match(Set dst (OrI (LShiftI dst shift) (URShiftI dst (SubI c32 shift))));
8701
8702 expand %{
8703 rolI_rReg_CL(dst, shift, cr);
8704 %}
8705 %}
8706
8707 // ROR expand
8708 instruct rorI_rReg_imm1(rRegI dst, rFlagsReg cr)
8709 %{
8710 effect(USE_DEF dst, KILL cr);
8711
8712 format %{ "rorl $dst" %}
8713 opcode(0xD1, 0x1); /* D1 /1 */
8714 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8715 ins_pipe(ialu_reg);
8716 %}
8717
8718 instruct rorI_rReg_imm8(rRegI dst, immI8 shift, rFlagsReg cr)
8719 %{
8720 effect(USE_DEF dst, USE shift, KILL cr);
8721
8722 format %{ "rorl $dst, $shift" %}
8723 opcode(0xC1, 0x1); /* C1 /1 ib */
8724 ins_encode(reg_opc_imm(dst, shift));
8725 ins_pipe(ialu_reg);
8726 %}
8727
8728 instruct rorI_rReg_CL(no_rcx_RegI dst, rcx_RegI shift, rFlagsReg cr)
8729 %{
8730 effect(USE_DEF dst, USE shift, KILL cr);
8731
8732 format %{ "rorl $dst, $shift" %}
8733 opcode(0xD3, 0x1); /* D3 /1 */
8734 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8735 ins_pipe(ialu_reg_reg);
8736 %}
8737 // end of ROR expand
8738
8739 // Rotate Right by one
8740 instruct rorI_rReg_i1(rRegI dst, immI1 rshift, immI_M1 lshift, rFlagsReg cr)
8741 %{
8742 match(Set dst (OrI (URShiftI dst rshift) (LShiftI dst lshift)));
8743
8744 expand %{
8745 rorI_rReg_imm1(dst, cr);
8746 %}
8747 %}
8748
8749 // Rotate Right by 8-bit immediate
8750 instruct rorI_rReg_i8(rRegI dst, immI8 rshift, immI8 lshift, rFlagsReg cr)
8751 %{
8752 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8753 match(Set dst (OrI (URShiftI dst rshift) (LShiftI dst lshift)));
8754
8755 expand %{
8756 rorI_rReg_imm8(dst, rshift, cr);
8757 %}
8758 %}
8759
8760 // Rotate Right by variable
8761 instruct rorI_rReg_Var_C0(no_rcx_RegI dst, rcx_RegI shift, immI0 zero, rFlagsReg cr)
8762 %{
8763 match(Set dst (OrI (URShiftI dst shift) (LShiftI dst (SubI zero shift))));
8764
8765 expand %{
8766 rorI_rReg_CL(dst, shift, cr);
8767 %}
8768 %}
8769
8770 // Rotate Right by variable
8771 instruct rorI_rReg_Var_C32(no_rcx_RegI dst, rcx_RegI shift, immI_32 c32, rFlagsReg cr)
8772 %{
8773 match(Set dst (OrI (URShiftI dst shift) (LShiftI dst (SubI c32 shift))));
8774
8775 expand %{
8776 rorI_rReg_CL(dst, shift, cr);
8777 %}
8778 %}
8779
8780 // for long rotate
8781 // ROL expand
8782 instruct rolL_rReg_imm1(rRegL dst, rFlagsReg cr) %{
8783 effect(USE_DEF dst, KILL cr);
8784
8785 format %{ "rolq $dst" %}
8786 opcode(0xD1, 0x0); /* Opcode D1 /0 */
8787 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8788 ins_pipe(ialu_reg);
8789 %}
8790
8791 instruct rolL_rReg_imm8(rRegL dst, immI8 shift, rFlagsReg cr) %{
8792 effect(USE_DEF dst, USE shift, KILL cr);
8793
8794 format %{ "rolq $dst, $shift" %}
8795 opcode(0xC1, 0x0); /* Opcode C1 /0 ib */
8796 ins_encode( reg_opc_imm_wide(dst, shift) );
8797 ins_pipe(ialu_reg);
8798 %}
8799
8800 instruct rolL_rReg_CL(no_rcx_RegL dst, rcx_RegI shift, rFlagsReg cr)
8801 %{
8802 effect(USE_DEF dst, USE shift, KILL cr);
8803
8804 format %{ "rolq $dst, $shift" %}
8805 opcode(0xD3, 0x0); /* Opcode D3 /0 */
8806 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8807 ins_pipe(ialu_reg_reg);
8808 %}
8809 // end of ROL expand
8810
8811 // Rotate Left by one
8812 instruct rolL_rReg_i1(rRegL dst, immI1 lshift, immI_M1 rshift, rFlagsReg cr)
8813 %{
8814 match(Set dst (OrL (LShiftL dst lshift) (URShiftL dst rshift)));
8815
8816 expand %{
8817 rolL_rReg_imm1(dst, cr);
8818 %}
8819 %}
8820
8821 // Rotate Left by 8-bit immediate
8822 instruct rolL_rReg_i8(rRegL dst, immI8 lshift, immI8 rshift, rFlagsReg cr)
8823 %{
8824 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f));
8825 match(Set dst (OrL (LShiftL dst lshift) (URShiftL dst rshift)));
8826
8827 expand %{
8828 rolL_rReg_imm8(dst, lshift, cr);
8829 %}
8830 %}
8831
8832 // Rotate Left by variable
8833 instruct rolL_rReg_Var_C0(no_rcx_RegL dst, rcx_RegI shift, immI0 zero, rFlagsReg cr)
8834 %{
8835 match(Set dst (OrL (LShiftL dst shift) (URShiftL dst (SubI zero shift))));
8836
8837 expand %{
8838 rolL_rReg_CL(dst, shift, cr);
8839 %}
8840 %}
8841
8842 // Rotate Left by variable
8843 instruct rolL_rReg_Var_C64(no_rcx_RegL dst, rcx_RegI shift, immI_64 c64, rFlagsReg cr)
8844 %{
8845 match(Set dst (OrL (LShiftL dst shift) (URShiftL dst (SubI c64 shift))));
8846
8847 expand %{
8848 rolL_rReg_CL(dst, shift, cr);
8849 %}
8850 %}
8851
8852 // ROR expand
8853 instruct rorL_rReg_imm1(rRegL dst, rFlagsReg cr)
8854 %{
8855 effect(USE_DEF dst, KILL cr);
8856
8857 format %{ "rorq $dst" %}
8858 opcode(0xD1, 0x1); /* D1 /1 */
8859 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8860 ins_pipe(ialu_reg);
8861 %}
8862
8863 instruct rorL_rReg_imm8(rRegL dst, immI8 shift, rFlagsReg cr)
8864 %{
8865 effect(USE_DEF dst, USE shift, KILL cr);
8866
8867 format %{ "rorq $dst, $shift" %}
8868 opcode(0xC1, 0x1); /* C1 /1 ib */
8869 ins_encode(reg_opc_imm_wide(dst, shift));
8870 ins_pipe(ialu_reg);
8871 %}
8872
8873 instruct rorL_rReg_CL(no_rcx_RegL dst, rcx_RegI shift, rFlagsReg cr)
8874 %{
8875 effect(USE_DEF dst, USE shift, KILL cr);
8876
8877 format %{ "rorq $dst, $shift" %}
8878 opcode(0xD3, 0x1); /* D3 /1 */
8879 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8880 ins_pipe(ialu_reg_reg);
8881 %}
8882 // end of ROR expand
8883
8884 // Rotate Right by one
8885 instruct rorL_rReg_i1(rRegL dst, immI1 rshift, immI_M1 lshift, rFlagsReg cr)
8886 %{
8887 match(Set dst (OrL (URShiftL dst rshift) (LShiftL dst lshift)));
8888
8889 expand %{
8890 rorL_rReg_imm1(dst, cr);
8891 %}
8892 %}
8893
8894 // Rotate Right by 8-bit immediate
8895 instruct rorL_rReg_i8(rRegL dst, immI8 rshift, immI8 lshift, rFlagsReg cr)
8896 %{
8897 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f));
8898 match(Set dst (OrL (URShiftL dst rshift) (LShiftL dst lshift)));
8899
8900 expand %{
8901 rorL_rReg_imm8(dst, rshift, cr);
8902 %}
8903 %}
8904
8905 // Rotate Right by variable
8906 instruct rorL_rReg_Var_C0(no_rcx_RegL dst, rcx_RegI shift, immI0 zero, rFlagsReg cr)
8907 %{
8908 match(Set dst (OrL (URShiftL dst shift) (LShiftL dst (SubI zero shift))));
8909
8910 expand %{
8911 rorL_rReg_CL(dst, shift, cr);
8912 %}
8913 %}
8914
8915 // Rotate Right by variable
8916 instruct rorL_rReg_Var_C64(no_rcx_RegL dst, rcx_RegI shift, immI_64 c64, rFlagsReg cr)
8917 %{
8918 match(Set dst (OrL (URShiftL dst shift) (LShiftL dst (SubI c64 shift))));
8919
8920 expand %{
8921 rorL_rReg_CL(dst, shift, cr);
8922 %}
8923 %}
8924
8925 // Logical Instructions
8926
8927 // Integer Logical Instructions
8928
8929 // And Instructions
8930 // And Register with Register
8931 instruct andI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
8932 %{
8933 match(Set dst (AndI dst src));
8934 effect(KILL cr);
8935
8936 format %{ "andl $dst, $src\t# int" %}
8937 opcode(0x23);
8938 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
8939 ins_pipe(ialu_reg_reg);
8940 %}
8941
8942 // And Register with Immediate 255
8943 instruct andI_rReg_imm255(rRegI dst, immI_255 src)
8944 %{
8945 match(Set dst (AndI dst src));
8946
8947 format %{ "movzbl $dst, $dst\t# int & 0xFF" %}
8948 opcode(0x0F, 0xB6);
8949 ins_encode(REX_reg_breg(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
8950 ins_pipe(ialu_reg);
8951 %}
8952
8953 // And Register with Immediate 255 and promote to long
8954 instruct andI2L_rReg_imm255(rRegL dst, rRegI src, immI_255 mask)
8955 %{
8956 match(Set dst (ConvI2L (AndI src mask)));
8957
8958 format %{ "movzbl $dst, $src\t# int & 0xFF -> long" %}
8959 opcode(0x0F, 0xB6);
8960 ins_encode(REX_reg_breg(dst, src), OpcP, OpcS, reg_reg(dst, src));
8961 ins_pipe(ialu_reg);
8962 %}
8963
8964 // And Register with Immediate 65535
8965 instruct andI_rReg_imm65535(rRegI dst, immI_65535 src)
8966 %{
8967 match(Set dst (AndI dst src));
8968
8969 format %{ "movzwl $dst, $dst\t# int & 0xFFFF" %}
8970 opcode(0x0F, 0xB7);
8971 ins_encode(REX_reg_reg(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
8972 ins_pipe(ialu_reg);
8973 %}
8974
8975 // And Register with Immediate 65535 and promote to long
8976 instruct andI2L_rReg_imm65535(rRegL dst, rRegI src, immI_65535 mask)
8977 %{
8978 match(Set dst (ConvI2L (AndI src mask)));
8979
8980 format %{ "movzwl $dst, $src\t# int & 0xFFFF -> long" %}
8981 opcode(0x0F, 0xB7);
8982 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
8983 ins_pipe(ialu_reg);
8984 %}
8985
8986 // And Register with Immediate
8987 instruct andI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
8988 %{
8989 match(Set dst (AndI dst src));
8990 effect(KILL cr);
8991
8992 format %{ "andl $dst, $src\t# int" %}
8993 opcode(0x81, 0x04); /* Opcode 81 /4 */
8994 ins_encode(OpcSErm(dst, src), Con8or32(src));
8995 ins_pipe(ialu_reg);
8996 %}
8997
8998 // And Register with Memory
8999 instruct andI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
9000 %{
9001 match(Set dst (AndI dst (LoadI src)));
9002 effect(KILL cr);
9003
9004 ins_cost(125);
9005 format %{ "andl $dst, $src\t# int" %}
9006 opcode(0x23);
9007 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
9008 ins_pipe(ialu_reg_mem);
9009 %}
9010
9011 // And Memory with Register
9012 instruct andI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
9013 %{
9014 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
9015 effect(KILL cr);
9016
9017 ins_cost(150);
9018 format %{ "andl $dst, $src\t# int" %}
9019 opcode(0x21); /* Opcode 21 /r */
9020 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
9021 ins_pipe(ialu_mem_reg);
9022 %}
9023
9024 // And Memory with Immediate
9025 instruct andI_mem_imm(memory dst, immI src, rFlagsReg cr)
9026 %{
9027 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
9028 effect(KILL cr);
9029
9030 ins_cost(125);
9031 format %{ "andl $dst, $src\t# int" %}
9032 opcode(0x81, 0x4); /* Opcode 81 /4 id */
9033 ins_encode(REX_mem(dst), OpcSE(src),
9034 RM_opc_mem(secondary, dst), Con8or32(src));
9035 ins_pipe(ialu_mem_imm);
9036 %}
9037
9038 // BMI1 instructions
9039 instruct andnI_rReg_rReg_mem(rRegI dst, rRegI src1, memory src2, immI_M1 minus_1, rFlagsReg cr) %{
9040 match(Set dst (AndI (XorI src1 minus_1) (LoadI src2)));
9041 predicate(UseBMI1Instructions);
9042 effect(KILL cr);
9043
9044 ins_cost(125);
9045 format %{ "andnl $dst, $src1, $src2" %}
9046
9047 ins_encode %{
9048 __ andnl($dst$$Register, $src1$$Register, $src2$$Address);
9049 %}
9050 ins_pipe(ialu_reg_mem);
9051 %}
9052
9053 instruct andnI_rReg_rReg_rReg(rRegI dst, rRegI src1, rRegI src2, immI_M1 minus_1, rFlagsReg cr) %{
9054 match(Set dst (AndI (XorI src1 minus_1) src2));
9055 predicate(UseBMI1Instructions);
9056 effect(KILL cr);
9057
9058 format %{ "andnl $dst, $src1, $src2" %}
9059
9060 ins_encode %{
9061 __ andnl($dst$$Register, $src1$$Register, $src2$$Register);
9062 %}
9063 ins_pipe(ialu_reg);
9064 %}
9065
9066 instruct blsiI_rReg_rReg(rRegI dst, rRegI src, immI0 imm_zero, rFlagsReg cr) %{
9067 match(Set dst (AndI (SubI imm_zero src) src));
9068 predicate(UseBMI1Instructions);
9069 effect(KILL cr);
9070
9071 format %{ "blsil $dst, $src" %}
9072
9073 ins_encode %{
9074 __ blsil($dst$$Register, $src$$Register);
9075 %}
9076 ins_pipe(ialu_reg);
9077 %}
9078
9079 instruct blsiI_rReg_mem(rRegI dst, memory src, immI0 imm_zero, rFlagsReg cr) %{
9080 match(Set dst (AndI (SubI imm_zero (LoadI src) ) (LoadI src) ));
9081 predicate(UseBMI1Instructions);
9082 effect(KILL cr);
9083
9084 ins_cost(125);
9085 format %{ "blsil $dst, $src" %}
9086
9087 ins_encode %{
9088 __ blsil($dst$$Register, $src$$Address);
9089 %}
9090 ins_pipe(ialu_reg_mem);
9091 %}
9092
9093 instruct blsmskI_rReg_mem(rRegI dst, memory src, immI_M1 minus_1, rFlagsReg cr)
9094 %{
9095 match(Set dst (XorI (AddI (LoadI src) minus_1) (LoadI src) ) );
9096 predicate(UseBMI1Instructions);
9097 effect(KILL cr);
9098
9099 ins_cost(125);
9100 format %{ "blsmskl $dst, $src" %}
9101
9102 ins_encode %{
9103 __ blsmskl($dst$$Register, $src$$Address);
9104 %}
9105 ins_pipe(ialu_reg_mem);
9106 %}
9107
9108 instruct blsmskI_rReg_rReg(rRegI dst, rRegI src, immI_M1 minus_1, rFlagsReg cr)
9109 %{
9110 match(Set dst (XorI (AddI src minus_1) src));
9111 predicate(UseBMI1Instructions);
9112 effect(KILL cr);
9113
9114 format %{ "blsmskl $dst, $src" %}
9115
9116 ins_encode %{
9117 __ blsmskl($dst$$Register, $src$$Register);
9118 %}
9119
9120 ins_pipe(ialu_reg);
9121 %}
9122
9123 instruct blsrI_rReg_rReg(rRegI dst, rRegI src, immI_M1 minus_1, rFlagsReg cr)
9124 %{
9125 match(Set dst (AndI (AddI src minus_1) src) );
9126 predicate(UseBMI1Instructions);
9127 effect(KILL cr);
9128
9129 format %{ "blsrl $dst, $src" %}
9130
9131 ins_encode %{
9132 __ blsrl($dst$$Register, $src$$Register);
9133 %}
9134
9135 ins_pipe(ialu_reg_mem);
9136 %}
9137
9138 instruct blsrI_rReg_mem(rRegI dst, memory src, immI_M1 minus_1, rFlagsReg cr)
9139 %{
9140 match(Set dst (AndI (AddI (LoadI src) minus_1) (LoadI src) ) );
9141 predicate(UseBMI1Instructions);
9142 effect(KILL cr);
9143
9144 ins_cost(125);
9145 format %{ "blsrl $dst, $src" %}
9146
9147 ins_encode %{
9148 __ blsrl($dst$$Register, $src$$Address);
9149 %}
9150
9151 ins_pipe(ialu_reg);
9152 %}
9153
9154 // Or Instructions
9155 // Or Register with Register
9156 instruct orI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
9157 %{
9158 match(Set dst (OrI dst src));
9159 effect(KILL cr);
9160
9161 format %{ "orl $dst, $src\t# int" %}
9162 opcode(0x0B);
9163 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
9164 ins_pipe(ialu_reg_reg);
9165 %}
9166
9167 // Or Register with Immediate
9168 instruct orI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
9169 %{
9170 match(Set dst (OrI dst src));
9171 effect(KILL cr);
9172
9173 format %{ "orl $dst, $src\t# int" %}
9174 opcode(0x81, 0x01); /* Opcode 81 /1 id */
9175 ins_encode(OpcSErm(dst, src), Con8or32(src));
9176 ins_pipe(ialu_reg);
9177 %}
9178
9179 // Or Register with Memory
9180 instruct orI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
9181 %{
9182 match(Set dst (OrI dst (LoadI src)));
9183 effect(KILL cr);
9184
9185 ins_cost(125);
9186 format %{ "orl $dst, $src\t# int" %}
9187 opcode(0x0B);
9188 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
9189 ins_pipe(ialu_reg_mem);
9190 %}
9191
9192 // Or Memory with Register
9193 instruct orI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
9194 %{
9195 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
9196 effect(KILL cr);
9197
9198 ins_cost(150);
9199 format %{ "orl $dst, $src\t# int" %}
9200 opcode(0x09); /* Opcode 09 /r */
9201 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
9202 ins_pipe(ialu_mem_reg);
9203 %}
9204
9205 // Or Memory with Immediate
9206 instruct orI_mem_imm(memory dst, immI src, rFlagsReg cr)
9207 %{
9208 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
9209 effect(KILL cr);
9210
9211 ins_cost(125);
9212 format %{ "orl $dst, $src\t# int" %}
9213 opcode(0x81, 0x1); /* Opcode 81 /1 id */
9214 ins_encode(REX_mem(dst), OpcSE(src),
9215 RM_opc_mem(secondary, dst), Con8or32(src));
9216 ins_pipe(ialu_mem_imm);
9217 %}
9218
9219 // Xor Instructions
9220 // Xor Register with Register
9221 instruct xorI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
9222 %{
9223 match(Set dst (XorI dst src));
9224 effect(KILL cr);
9225
9226 format %{ "xorl $dst, $src\t# int" %}
9227 opcode(0x33);
9228 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
9229 ins_pipe(ialu_reg_reg);
9230 %}
9231
9232 // Xor Register with Immediate -1
9233 instruct xorI_rReg_im1(rRegI dst, immI_M1 imm) %{
9234 match(Set dst (XorI dst imm));
9235
9236 format %{ "not $dst" %}
9237 ins_encode %{
9238 __ notl($dst$$Register);
9239 %}
9240 ins_pipe(ialu_reg);
9241 %}
9242
9243 // Xor Register with Immediate
9244 instruct xorI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
9245 %{
9246 match(Set dst (XorI dst src));
9247 effect(KILL cr);
9248
9249 format %{ "xorl $dst, $src\t# int" %}
9250 opcode(0x81, 0x06); /* Opcode 81 /6 id */
9251 ins_encode(OpcSErm(dst, src), Con8or32(src));
9252 ins_pipe(ialu_reg);
9253 %}
9254
9255 // Xor Register with Memory
9256 instruct xorI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
9257 %{
9258 match(Set dst (XorI dst (LoadI src)));
9259 effect(KILL cr);
9260
9261 ins_cost(125);
9262 format %{ "xorl $dst, $src\t# int" %}
9263 opcode(0x33);
9264 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
9265 ins_pipe(ialu_reg_mem);
9266 %}
9267
9268 // Xor Memory with Register
9269 instruct xorI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
9270 %{
9271 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
9272 effect(KILL cr);
9273
9274 ins_cost(150);
9275 format %{ "xorl $dst, $src\t# int" %}
9276 opcode(0x31); /* Opcode 31 /r */
9277 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
9278 ins_pipe(ialu_mem_reg);
9279 %}
9280
9281 // Xor Memory with Immediate
9282 instruct xorI_mem_imm(memory dst, immI src, rFlagsReg cr)
9283 %{
9284 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
9285 effect(KILL cr);
9286
9287 ins_cost(125);
9288 format %{ "xorl $dst, $src\t# int" %}
9289 opcode(0x81, 0x6); /* Opcode 81 /6 id */
9290 ins_encode(REX_mem(dst), OpcSE(src),
9291 RM_opc_mem(secondary, dst), Con8or32(src));
9292 ins_pipe(ialu_mem_imm);
9293 %}
9294
9295
9296 // Long Logical Instructions
9297
9298 // And Instructions
9299 // And Register with Register
9300 instruct andL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
9301 %{
9302 match(Set dst (AndL dst src));
9303 effect(KILL cr);
9304
9305 format %{ "andq $dst, $src\t# long" %}
9306 opcode(0x23);
9307 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
9308 ins_pipe(ialu_reg_reg);
9309 %}
9310
9311 // And Register with Immediate 255
9312 instruct andL_rReg_imm255(rRegL dst, immL_255 src)
9313 %{
9314 match(Set dst (AndL dst src));
9315
9316 format %{ "movzbq $dst, $dst\t# long & 0xFF" %}
9317 opcode(0x0F, 0xB6);
9318 ins_encode(REX_reg_reg_wide(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
9319 ins_pipe(ialu_reg);
9320 %}
9321
9322 // And Register with Immediate 65535
9323 instruct andL_rReg_imm65535(rRegL dst, immL_65535 src)
9324 %{
9325 match(Set dst (AndL dst src));
9326
9327 format %{ "movzwq $dst, $dst\t# long & 0xFFFF" %}
9328 opcode(0x0F, 0xB7);
9329 ins_encode(REX_reg_reg_wide(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
9330 ins_pipe(ialu_reg);
9331 %}
9332
9333 // And Register with Immediate
9334 instruct andL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
9335 %{
9336 match(Set dst (AndL dst src));
9337 effect(KILL cr);
9338
9339 format %{ "andq $dst, $src\t# long" %}
9340 opcode(0x81, 0x04); /* Opcode 81 /4 */
9341 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
9342 ins_pipe(ialu_reg);
9343 %}
9344
9345 // And Register with Memory
9346 instruct andL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
9347 %{
9348 match(Set dst (AndL dst (LoadL src)));
9349 effect(KILL cr);
9350
9351 ins_cost(125);
9352 format %{ "andq $dst, $src\t# long" %}
9353 opcode(0x23);
9354 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
9355 ins_pipe(ialu_reg_mem);
9356 %}
9357
9358 // And Memory with Register
9359 instruct andL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
9360 %{
9361 match(Set dst (StoreL dst (AndL (LoadL dst) src)));
9362 effect(KILL cr);
9363
9364 ins_cost(150);
9365 format %{ "andq $dst, $src\t# long" %}
9366 opcode(0x21); /* Opcode 21 /r */
9367 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
9368 ins_pipe(ialu_mem_reg);
9369 %}
9370
9371 // And Memory with Immediate
9372 instruct andL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
9373 %{
9374 match(Set dst (StoreL dst (AndL (LoadL dst) src)));
9375 effect(KILL cr);
9376
9377 ins_cost(125);
9378 format %{ "andq $dst, $src\t# long" %}
9379 opcode(0x81, 0x4); /* Opcode 81 /4 id */
9380 ins_encode(REX_mem_wide(dst), OpcSE(src),
9381 RM_opc_mem(secondary, dst), Con8or32(src));
9382 ins_pipe(ialu_mem_imm);
9383 %}
9384
9385 // BMI1 instructions
9386 instruct andnL_rReg_rReg_mem(rRegL dst, rRegL src1, memory src2, immL_M1 minus_1, rFlagsReg cr) %{
9387 match(Set dst (AndL (XorL src1 minus_1) (LoadL src2)));
9388 predicate(UseBMI1Instructions);
9389 effect(KILL cr);
9390
9391 ins_cost(125);
9392 format %{ "andnq $dst, $src1, $src2" %}
9393
9394 ins_encode %{
9395 __ andnq($dst$$Register, $src1$$Register, $src2$$Address);
9396 %}
9397 ins_pipe(ialu_reg_mem);
9398 %}
9399
9400 instruct andnL_rReg_rReg_rReg(rRegL dst, rRegL src1, rRegL src2, immL_M1 minus_1, rFlagsReg cr) %{
9401 match(Set dst (AndL (XorL src1 minus_1) src2));
9402 predicate(UseBMI1Instructions);
9403 effect(KILL cr);
9404
9405 format %{ "andnq $dst, $src1, $src2" %}
9406
9407 ins_encode %{
9408 __ andnq($dst$$Register, $src1$$Register, $src2$$Register);
9409 %}
9410 ins_pipe(ialu_reg_mem);
9411 %}
9412
9413 instruct blsiL_rReg_rReg(rRegL dst, rRegL src, immL0 imm_zero, rFlagsReg cr) %{
9414 match(Set dst (AndL (SubL imm_zero src) src));
9415 predicate(UseBMI1Instructions);
9416 effect(KILL cr);
9417
9418 format %{ "blsiq $dst, $src" %}
9419
9420 ins_encode %{
9421 __ blsiq($dst$$Register, $src$$Register);
9422 %}
9423 ins_pipe(ialu_reg);
9424 %}
9425
9426 instruct blsiL_rReg_mem(rRegL dst, memory src, immL0 imm_zero, rFlagsReg cr) %{
9427 match(Set dst (AndL (SubL imm_zero (LoadL src) ) (LoadL src) ));
9428 predicate(UseBMI1Instructions);
9429 effect(KILL cr);
9430
9431 ins_cost(125);
9432 format %{ "blsiq $dst, $src" %}
9433
9434 ins_encode %{
9435 __ blsiq($dst$$Register, $src$$Address);
9436 %}
9437 ins_pipe(ialu_reg_mem);
9438 %}
9439
9440 instruct blsmskL_rReg_mem(rRegL dst, memory src, immL_M1 minus_1, rFlagsReg cr)
9441 %{
9442 match(Set dst (XorL (AddL (LoadL src) minus_1) (LoadL src) ) );
9443 predicate(UseBMI1Instructions);
9444 effect(KILL cr);
9445
9446 ins_cost(125);
9447 format %{ "blsmskq $dst, $src" %}
9448
9449 ins_encode %{
9450 __ blsmskq($dst$$Register, $src$$Address);
9451 %}
9452 ins_pipe(ialu_reg_mem);
9453 %}
9454
9455 instruct blsmskL_rReg_rReg(rRegL dst, rRegL src, immL_M1 minus_1, rFlagsReg cr)
9456 %{
9457 match(Set dst (XorL (AddL src minus_1) src));
9458 predicate(UseBMI1Instructions);
9459 effect(KILL cr);
9460
9461 format %{ "blsmskq $dst, $src" %}
9462
9463 ins_encode %{
9464 __ blsmskq($dst$$Register, $src$$Register);
9465 %}
9466
9467 ins_pipe(ialu_reg);
9468 %}
9469
9470 instruct blsrL_rReg_rReg(rRegL dst, rRegL src, immL_M1 minus_1, rFlagsReg cr)
9471 %{
9472 match(Set dst (AndL (AddL src minus_1) src) );
9473 predicate(UseBMI1Instructions);
9474 effect(KILL cr);
9475
9476 format %{ "blsrq $dst, $src" %}
9477
9478 ins_encode %{
9479 __ blsrq($dst$$Register, $src$$Register);
9480 %}
9481
9482 ins_pipe(ialu_reg);
9483 %}
9484
9485 instruct blsrL_rReg_mem(rRegL dst, memory src, immL_M1 minus_1, rFlagsReg cr)
9486 %{
9487 match(Set dst (AndL (AddL (LoadL src) minus_1) (LoadL src)) );
9488 predicate(UseBMI1Instructions);
9489 effect(KILL cr);
9490
9491 ins_cost(125);
9492 format %{ "blsrq $dst, $src" %}
9493
9494 ins_encode %{
9495 __ blsrq($dst$$Register, $src$$Address);
9496 %}
9497
9498 ins_pipe(ialu_reg);
9499 %}
9500
9501 // Or Instructions
9502 // Or Register with Register
9503 instruct orL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
9504 %{
9505 match(Set dst (OrL dst src));
9506 effect(KILL cr);
9507
9508 format %{ "orq $dst, $src\t# long" %}
9509 opcode(0x0B);
9510 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
9511 ins_pipe(ialu_reg_reg);
9512 %}
9513
9514 // Use any_RegP to match R15 (TLS register) without spilling.
9515 instruct orL_rReg_castP2X(rRegL dst, any_RegP src, rFlagsReg cr) %{
9516 match(Set dst (OrL dst (CastP2X src)));
9517 effect(KILL cr);
9518
9519 format %{ "orq $dst, $src\t# long" %}
9520 opcode(0x0B);
9521 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
9522 ins_pipe(ialu_reg_reg);
9523 %}
9524
9525
9526 // Or Register with Immediate
9527 instruct orL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
9528 %{
9529 match(Set dst (OrL dst src));
9530 effect(KILL cr);
9531
9532 format %{ "orq $dst, $src\t# long" %}
9533 opcode(0x81, 0x01); /* Opcode 81 /1 id */
9534 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
9535 ins_pipe(ialu_reg);
9536 %}
9537
9538 // Or Register with Memory
9539 instruct orL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
9540 %{
9541 match(Set dst (OrL dst (LoadL src)));
9542 effect(KILL cr);
9543
9544 ins_cost(125);
9545 format %{ "orq $dst, $src\t# long" %}
9546 opcode(0x0B);
9547 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
9548 ins_pipe(ialu_reg_mem);
9549 %}
9550
9551 // Or Memory with Register
9552 instruct orL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
9553 %{
9554 match(Set dst (StoreL dst (OrL (LoadL dst) src)));
9555 effect(KILL cr);
9556
9557 ins_cost(150);
9558 format %{ "orq $dst, $src\t# long" %}
9559 opcode(0x09); /* Opcode 09 /r */
9560 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
9561 ins_pipe(ialu_mem_reg);
9562 %}
9563
9564 // Or Memory with Immediate
9565 instruct orL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
9566 %{
9567 match(Set dst (StoreL dst (OrL (LoadL dst) src)));
9568 effect(KILL cr);
9569
9570 ins_cost(125);
9571 format %{ "orq $dst, $src\t# long" %}
9572 opcode(0x81, 0x1); /* Opcode 81 /1 id */
9573 ins_encode(REX_mem_wide(dst), OpcSE(src),
9574 RM_opc_mem(secondary, dst), Con8or32(src));
9575 ins_pipe(ialu_mem_imm);
9576 %}
9577
9578 // Xor Instructions
9579 // Xor Register with Register
9580 instruct xorL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
9581 %{
9582 match(Set dst (XorL dst src));
9583 effect(KILL cr);
9584
9585 format %{ "xorq $dst, $src\t# long" %}
9586 opcode(0x33);
9587 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
9588 ins_pipe(ialu_reg_reg);
9589 %}
9590
9591 // Xor Register with Immediate -1
9592 instruct xorL_rReg_im1(rRegL dst, immL_M1 imm) %{
9593 match(Set dst (XorL dst imm));
9594
9595 format %{ "notq $dst" %}
9596 ins_encode %{
9597 __ notq($dst$$Register);
9598 %}
9599 ins_pipe(ialu_reg);
9600 %}
9601
9602 // Xor Register with Immediate
9603 instruct xorL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
9604 %{
9605 match(Set dst (XorL dst src));
9606 effect(KILL cr);
9607
9608 format %{ "xorq $dst, $src\t# long" %}
9609 opcode(0x81, 0x06); /* Opcode 81 /6 id */
9610 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
9611 ins_pipe(ialu_reg);
9612 %}
9613
9614 // Xor Register with Memory
9615 instruct xorL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
9616 %{
9617 match(Set dst (XorL dst (LoadL src)));
9618 effect(KILL cr);
9619
9620 ins_cost(125);
9621 format %{ "xorq $dst, $src\t# long" %}
9622 opcode(0x33);
9623 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
9624 ins_pipe(ialu_reg_mem);
9625 %}
9626
9627 // Xor Memory with Register
9628 instruct xorL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
9629 %{
9630 match(Set dst (StoreL dst (XorL (LoadL dst) src)));
9631 effect(KILL cr);
9632
9633 ins_cost(150);
9634 format %{ "xorq $dst, $src\t# long" %}
9635 opcode(0x31); /* Opcode 31 /r */
9636 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
9637 ins_pipe(ialu_mem_reg);
9638 %}
9639
9640 // Xor Memory with Immediate
9641 instruct xorL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
9642 %{
9643 match(Set dst (StoreL dst (XorL (LoadL dst) src)));
9644 effect(KILL cr);
9645
9646 ins_cost(125);
9647 format %{ "xorq $dst, $src\t# long" %}
9648 opcode(0x81, 0x6); /* Opcode 81 /6 id */
9649 ins_encode(REX_mem_wide(dst), OpcSE(src),
9650 RM_opc_mem(secondary, dst), Con8or32(src));
9651 ins_pipe(ialu_mem_imm);
9652 %}
9653
9654 // Convert Int to Boolean
9655 instruct convI2B(rRegI dst, rRegI src, rFlagsReg cr)
9656 %{
9657 match(Set dst (Conv2B src));
9658 effect(KILL cr);
9659
9660 format %{ "testl $src, $src\t# ci2b\n\t"
9661 "setnz $dst\n\t"
9662 "movzbl $dst, $dst" %}
9663 ins_encode(REX_reg_reg(src, src), opc_reg_reg(0x85, src, src), // testl
9664 setNZ_reg(dst),
9665 REX_reg_breg(dst, dst), // movzbl
9666 Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst));
9667 ins_pipe(pipe_slow); // XXX
9668 %}
9669
9670 // Convert Pointer to Boolean
9671 instruct convP2B(rRegI dst, rRegP src, rFlagsReg cr)
9672 %{
9673 match(Set dst (Conv2B src));
9674 effect(KILL cr);
9675
9676 format %{ "testq $src, $src\t# cp2b\n\t"
9677 "setnz $dst\n\t"
9678 "movzbl $dst, $dst" %}
9679 ins_encode(REX_reg_reg_wide(src, src), opc_reg_reg(0x85, src, src), // testq
9680 setNZ_reg(dst),
9681 REX_reg_breg(dst, dst), // movzbl
9682 Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst));
9683 ins_pipe(pipe_slow); // XXX
9684 %}
9685
9686 instruct cmpLTMask(rRegI dst, rRegI p, rRegI q, rFlagsReg cr)
9687 %{
9688 match(Set dst (CmpLTMask p q));
9689 effect(KILL cr);
9690
9691 ins_cost(400);
9692 format %{ "cmpl $p, $q\t# cmpLTMask\n\t"
9693 "setlt $dst\n\t"
9694 "movzbl $dst, $dst\n\t"
9695 "negl $dst" %}
9696 ins_encode(REX_reg_reg(p, q), opc_reg_reg(0x3B, p, q), // cmpl
9697 setLT_reg(dst),
9698 REX_reg_breg(dst, dst), // movzbl
9699 Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst),
9700 neg_reg(dst));
9701 ins_pipe(pipe_slow);
9702 %}
9703
9704 instruct cmpLTMask0(rRegI dst, immI0 zero, rFlagsReg cr)
9705 %{
9706 match(Set dst (CmpLTMask dst zero));
9707 effect(KILL cr);
9708
9709 ins_cost(100);
9710 format %{ "sarl $dst, #31\t# cmpLTMask0" %}
9711 ins_encode %{
9712 __ sarl($dst$$Register, 31);
9713 %}
9714 ins_pipe(ialu_reg);
9715 %}
9716
9717 /* Better to save a register than avoid a branch */
9718 instruct cadd_cmpLTMask(rRegI p, rRegI q, rRegI y, rFlagsReg cr)
9719 %{
9720 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)));
9721 effect(KILL cr);
9722 ins_cost(300);
9723 format %{ "subl $p,$q\t# cadd_cmpLTMask\n\t"
9724 "jge done\n\t"
9725 "addl $p,$y\n"
9726 "done: " %}
9727 ins_encode %{
9728 Register Rp = $p$$Register;
9729 Register Rq = $q$$Register;
9730 Register Ry = $y$$Register;
9731 Label done;
9732 __ subl(Rp, Rq);
9733 __ jccb(Assembler::greaterEqual, done);
9734 __ addl(Rp, Ry);
9735 __ bind(done);
9736 %}
9737 ins_pipe(pipe_cmplt);
9738 %}
9739
9740 /* Better to save a register than avoid a branch */
9741 instruct and_cmpLTMask(rRegI p, rRegI q, rRegI y, rFlagsReg cr)
9742 %{
9743 match(Set y (AndI (CmpLTMask p q) y));
9744 effect(KILL cr);
9745
9746 ins_cost(300);
9747
9748 format %{ "cmpl $p, $q\t# and_cmpLTMask\n\t"
9749 "jlt done\n\t"
9750 "xorl $y, $y\n"
9751 "done: " %}
9752 ins_encode %{
9753 Register Rp = $p$$Register;
9754 Register Rq = $q$$Register;
9755 Register Ry = $y$$Register;
9756 Label done;
9757 __ cmpl(Rp, Rq);
9758 __ jccb(Assembler::less, done);
9759 __ xorl(Ry, Ry);
9760 __ bind(done);
9761 %}
9762 ins_pipe(pipe_cmplt);
9763 %}
9764
9765
9766 //---------- FP Instructions------------------------------------------------
9767
9768 instruct cmpF_cc_reg(rFlagsRegU cr, regF src1, regF src2)
9769 %{
9770 match(Set cr (CmpF src1 src2));
9771
9772 ins_cost(145);
9773 format %{ "ucomiss $src1, $src2\n\t"
9774 "jnp,s exit\n\t"
9775 "pushfq\t# saw NaN, set CF\n\t"
9776 "andq [rsp], #0xffffff2b\n\t"
9777 "popfq\n"
9778 "exit:" %}
9779 ins_encode %{
9780 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
9781 emit_cmpfp_fixup(_masm);
9782 %}
9783 ins_pipe(pipe_slow);
9784 %}
9785
9786 instruct cmpF_cc_reg_CF(rFlagsRegUCF cr, regF src1, regF src2) %{
9787 match(Set cr (CmpF src1 src2));
9788
9789 ins_cost(100);
9790 format %{ "ucomiss $src1, $src2" %}
9791 ins_encode %{
9792 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
9793 %}
9794 ins_pipe(pipe_slow);
9795 %}
9796
9797 instruct cmpF_cc_mem(rFlagsRegU cr, regF src1, memory src2)
9798 %{
9799 match(Set cr (CmpF src1 (LoadF src2)));
9800
9801 ins_cost(145);
9802 format %{ "ucomiss $src1, $src2\n\t"
9803 "jnp,s exit\n\t"
9804 "pushfq\t# saw NaN, set CF\n\t"
9805 "andq [rsp], #0xffffff2b\n\t"
9806 "popfq\n"
9807 "exit:" %}
9808 ins_encode %{
9809 __ ucomiss($src1$$XMMRegister, $src2$$Address);
9810 emit_cmpfp_fixup(_masm);
9811 %}
9812 ins_pipe(pipe_slow);
9813 %}
9814
9815 instruct cmpF_cc_memCF(rFlagsRegUCF cr, regF src1, memory src2) %{
9816 match(Set cr (CmpF src1 (LoadF src2)));
9817
9818 ins_cost(100);
9819 format %{ "ucomiss $src1, $src2" %}
9820 ins_encode %{
9821 __ ucomiss($src1$$XMMRegister, $src2$$Address);
9822 %}
9823 ins_pipe(pipe_slow);
9824 %}
9825
9826 instruct cmpF_cc_imm(rFlagsRegU cr, regF src, immF con) %{
9827 match(Set cr (CmpF src con));
9828
9829 ins_cost(145);
9830 format %{ "ucomiss $src, [$constantaddress]\t# load from constant table: float=$con\n\t"
9831 "jnp,s exit\n\t"
9832 "pushfq\t# saw NaN, set CF\n\t"
9833 "andq [rsp], #0xffffff2b\n\t"
9834 "popfq\n"
9835 "exit:" %}
9836 ins_encode %{
9837 __ ucomiss($src$$XMMRegister, $constantaddress($con));
9838 emit_cmpfp_fixup(_masm);
9839 %}
9840 ins_pipe(pipe_slow);
9841 %}
9842
9843 instruct cmpF_cc_immCF(rFlagsRegUCF cr, regF src, immF con) %{
9844 match(Set cr (CmpF src con));
9845 ins_cost(100);
9846 format %{ "ucomiss $src, [$constantaddress]\t# load from constant table: float=$con" %}
9847 ins_encode %{
9848 __ ucomiss($src$$XMMRegister, $constantaddress($con));
9849 %}
9850 ins_pipe(pipe_slow);
9851 %}
9852
9853 instruct cmpD_cc_reg(rFlagsRegU cr, regD src1, regD src2)
9854 %{
9855 match(Set cr (CmpD src1 src2));
9856
9857 ins_cost(145);
9858 format %{ "ucomisd $src1, $src2\n\t"
9859 "jnp,s exit\n\t"
9860 "pushfq\t# saw NaN, set CF\n\t"
9861 "andq [rsp], #0xffffff2b\n\t"
9862 "popfq\n"
9863 "exit:" %}
9864 ins_encode %{
9865 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
9866 emit_cmpfp_fixup(_masm);
9867 %}
9868 ins_pipe(pipe_slow);
9869 %}
9870
9871 instruct cmpD_cc_reg_CF(rFlagsRegUCF cr, regD src1, regD src2) %{
9872 match(Set cr (CmpD src1 src2));
9873
9874 ins_cost(100);
9875 format %{ "ucomisd $src1, $src2 test" %}
9876 ins_encode %{
9877 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
9878 %}
9879 ins_pipe(pipe_slow);
9880 %}
9881
9882 instruct cmpD_cc_mem(rFlagsRegU cr, regD src1, memory src2)
9883 %{
9884 match(Set cr (CmpD src1 (LoadD src2)));
9885
9886 ins_cost(145);
9887 format %{ "ucomisd $src1, $src2\n\t"
9888 "jnp,s exit\n\t"
9889 "pushfq\t# saw NaN, set CF\n\t"
9890 "andq [rsp], #0xffffff2b\n\t"
9891 "popfq\n"
9892 "exit:" %}
9893 ins_encode %{
9894 __ ucomisd($src1$$XMMRegister, $src2$$Address);
9895 emit_cmpfp_fixup(_masm);
9896 %}
9897 ins_pipe(pipe_slow);
9898 %}
9899
9900 instruct cmpD_cc_memCF(rFlagsRegUCF cr, regD src1, memory src2) %{
9901 match(Set cr (CmpD src1 (LoadD src2)));
9902
9903 ins_cost(100);
9904 format %{ "ucomisd $src1, $src2" %}
9905 ins_encode %{
9906 __ ucomisd($src1$$XMMRegister, $src2$$Address);
9907 %}
9908 ins_pipe(pipe_slow);
9909 %}
9910
9911 instruct cmpD_cc_imm(rFlagsRegU cr, regD src, immD con) %{
9912 match(Set cr (CmpD src con));
9913
9914 ins_cost(145);
9915 format %{ "ucomisd $src, [$constantaddress]\t# load from constant table: double=$con\n\t"
9916 "jnp,s exit\n\t"
9917 "pushfq\t# saw NaN, set CF\n\t"
9918 "andq [rsp], #0xffffff2b\n\t"
9919 "popfq\n"
9920 "exit:" %}
9921 ins_encode %{
9922 __ ucomisd($src$$XMMRegister, $constantaddress($con));
9923 emit_cmpfp_fixup(_masm);
9924 %}
9925 ins_pipe(pipe_slow);
9926 %}
9927
9928 instruct cmpD_cc_immCF(rFlagsRegUCF cr, regD src, immD con) %{
9929 match(Set cr (CmpD src con));
9930 ins_cost(100);
9931 format %{ "ucomisd $src, [$constantaddress]\t# load from constant table: double=$con" %}
9932 ins_encode %{
9933 __ ucomisd($src$$XMMRegister, $constantaddress($con));
9934 %}
9935 ins_pipe(pipe_slow);
9936 %}
9937
9938 // Compare into -1,0,1
9939 instruct cmpF_reg(rRegI dst, regF src1, regF src2, rFlagsReg cr)
9940 %{
9941 match(Set dst (CmpF3 src1 src2));
9942 effect(KILL cr);
9943
9944 ins_cost(275);
9945 format %{ "ucomiss $src1, $src2\n\t"
9946 "movl $dst, #-1\n\t"
9947 "jp,s done\n\t"
9948 "jb,s done\n\t"
9949 "setne $dst\n\t"
9950 "movzbl $dst, $dst\n"
9951 "done:" %}
9952 ins_encode %{
9953 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
9954 emit_cmpfp3(_masm, $dst$$Register);
9955 %}
9956 ins_pipe(pipe_slow);
9957 %}
9958
9959 // Compare into -1,0,1
9960 instruct cmpF_mem(rRegI dst, regF src1, memory src2, rFlagsReg cr)
9961 %{
9962 match(Set dst (CmpF3 src1 (LoadF src2)));
9963 effect(KILL cr);
9964
9965 ins_cost(275);
9966 format %{ "ucomiss $src1, $src2\n\t"
9967 "movl $dst, #-1\n\t"
9968 "jp,s done\n\t"
9969 "jb,s done\n\t"
9970 "setne $dst\n\t"
9971 "movzbl $dst, $dst\n"
9972 "done:" %}
9973 ins_encode %{
9974 __ ucomiss($src1$$XMMRegister, $src2$$Address);
9975 emit_cmpfp3(_masm, $dst$$Register);
9976 %}
9977 ins_pipe(pipe_slow);
9978 %}
9979
9980 // Compare into -1,0,1
9981 instruct cmpF_imm(rRegI dst, regF src, immF con, rFlagsReg cr) %{
9982 match(Set dst (CmpF3 src con));
9983 effect(KILL cr);
9984
9985 ins_cost(275);
9986 format %{ "ucomiss $src, [$constantaddress]\t# load from constant table: float=$con\n\t"
9987 "movl $dst, #-1\n\t"
9988 "jp,s done\n\t"
9989 "jb,s done\n\t"
9990 "setne $dst\n\t"
9991 "movzbl $dst, $dst\n"
9992 "done:" %}
9993 ins_encode %{
9994 __ ucomiss($src$$XMMRegister, $constantaddress($con));
9995 emit_cmpfp3(_masm, $dst$$Register);
9996 %}
9997 ins_pipe(pipe_slow);
9998 %}
9999
10000 // Compare into -1,0,1
10001 instruct cmpD_reg(rRegI dst, regD src1, regD src2, rFlagsReg cr)
10002 %{
10003 match(Set dst (CmpD3 src1 src2));
10004 effect(KILL cr);
10005
10006 ins_cost(275);
10007 format %{ "ucomisd $src1, $src2\n\t"
10008 "movl $dst, #-1\n\t"
10009 "jp,s done\n\t"
10010 "jb,s done\n\t"
10011 "setne $dst\n\t"
10012 "movzbl $dst, $dst\n"
10013 "done:" %}
10014 ins_encode %{
10015 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
10016 emit_cmpfp3(_masm, $dst$$Register);
10017 %}
10018 ins_pipe(pipe_slow);
10019 %}
10020
10021 // Compare into -1,0,1
10022 instruct cmpD_mem(rRegI dst, regD src1, memory src2, rFlagsReg cr)
10023 %{
10024 match(Set dst (CmpD3 src1 (LoadD src2)));
10025 effect(KILL cr);
10026
10027 ins_cost(275);
10028 format %{ "ucomisd $src1, $src2\n\t"
10029 "movl $dst, #-1\n\t"
10030 "jp,s done\n\t"
10031 "jb,s done\n\t"
10032 "setne $dst\n\t"
10033 "movzbl $dst, $dst\n"
10034 "done:" %}
10035 ins_encode %{
10036 __ ucomisd($src1$$XMMRegister, $src2$$Address);
10037 emit_cmpfp3(_masm, $dst$$Register);
10038 %}
10039 ins_pipe(pipe_slow);
10040 %}
10041
10042 // Compare into -1,0,1
10043 instruct cmpD_imm(rRegI dst, regD src, immD con, rFlagsReg cr) %{
10044 match(Set dst (CmpD3 src con));
10045 effect(KILL cr);
10046
10047 ins_cost(275);
10048 format %{ "ucomisd $src, [$constantaddress]\t# load from constant table: double=$con\n\t"
10049 "movl $dst, #-1\n\t"
10050 "jp,s done\n\t"
10051 "jb,s done\n\t"
10052 "setne $dst\n\t"
10053 "movzbl $dst, $dst\n"
10054 "done:" %}
10055 ins_encode %{
10056 __ ucomisd($src$$XMMRegister, $constantaddress($con));
10057 emit_cmpfp3(_masm, $dst$$Register);
10058 %}
10059 ins_pipe(pipe_slow);
10060 %}
10061
10062 //----------Arithmetic Conversion Instructions---------------------------------
10063
10064 instruct roundFloat_nop(regF dst)
10065 %{
10066 match(Set dst (RoundFloat dst));
10067
10068 ins_cost(0);
10069 ins_encode();
10070 ins_pipe(empty);
10071 %}
10072
10073 instruct roundDouble_nop(regD dst)
10074 %{
10075 match(Set dst (RoundDouble dst));
10076
10077 ins_cost(0);
10078 ins_encode();
10079 ins_pipe(empty);
10080 %}
10081
10082 instruct convF2D_reg_reg(regD dst, regF src)
10083 %{
10084 match(Set dst (ConvF2D src));
10085
10086 format %{ "cvtss2sd $dst, $src" %}
10087 ins_encode %{
10088 __ cvtss2sd ($dst$$XMMRegister, $src$$XMMRegister);
10089 %}
10090 ins_pipe(pipe_slow); // XXX
10091 %}
10092
10093 instruct convF2D_reg_mem(regD dst, memory src)
10094 %{
10095 match(Set dst (ConvF2D (LoadF src)));
10096
10097 format %{ "cvtss2sd $dst, $src" %}
10098 ins_encode %{
10099 __ cvtss2sd ($dst$$XMMRegister, $src$$Address);
10100 %}
10101 ins_pipe(pipe_slow); // XXX
10102 %}
10103
10104 instruct convD2F_reg_reg(regF dst, regD src)
10105 %{
10106 match(Set dst (ConvD2F src));
10107
10108 format %{ "cvtsd2ss $dst, $src" %}
10109 ins_encode %{
10110 __ cvtsd2ss ($dst$$XMMRegister, $src$$XMMRegister);
10111 %}
10112 ins_pipe(pipe_slow); // XXX
10113 %}
10114
10115 instruct convD2F_reg_mem(regF dst, memory src)
10116 %{
10117 match(Set dst (ConvD2F (LoadD src)));
10118
10119 format %{ "cvtsd2ss $dst, $src" %}
10120 ins_encode %{
10121 __ cvtsd2ss ($dst$$XMMRegister, $src$$Address);
10122 %}
10123 ins_pipe(pipe_slow); // XXX
10124 %}
10125
10126 // XXX do mem variants
10127 instruct convF2I_reg_reg(rRegI dst, regF src, rFlagsReg cr)
10128 %{
10129 match(Set dst (ConvF2I src));
10130 effect(KILL cr);
10131
10132 format %{ "cvttss2sil $dst, $src\t# f2i\n\t"
10133 "cmpl $dst, #0x80000000\n\t"
10134 "jne,s done\n\t"
10135 "subq rsp, #8\n\t"
10136 "movss [rsp], $src\n\t"
10137 "call f2i_fixup\n\t"
10138 "popq $dst\n"
10139 "done: "%}
10140 ins_encode %{
10141 Label done;
10142 __ cvttss2sil($dst$$Register, $src$$XMMRegister);
10143 __ cmpl($dst$$Register, 0x80000000);
10144 __ jccb(Assembler::notEqual, done);
10145 __ subptr(rsp, 8);
10146 __ movflt(Address(rsp, 0), $src$$XMMRegister);
10147 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::f2i_fixup())));
10148 __ pop($dst$$Register);
10149 __ bind(done);
10150 %}
10151 ins_pipe(pipe_slow);
10152 %}
10153
10154 instruct convF2L_reg_reg(rRegL dst, regF src, rFlagsReg cr)
10155 %{
10156 match(Set dst (ConvF2L src));
10157 effect(KILL cr);
10158
10159 format %{ "cvttss2siq $dst, $src\t# f2l\n\t"
10160 "cmpq $dst, [0x8000000000000000]\n\t"
10161 "jne,s done\n\t"
10162 "subq rsp, #8\n\t"
10163 "movss [rsp], $src\n\t"
10164 "call f2l_fixup\n\t"
10165 "popq $dst\n"
10166 "done: "%}
10167 ins_encode %{
10168 Label done;
10169 __ cvttss2siq($dst$$Register, $src$$XMMRegister);
10170 __ cmp64($dst$$Register,
10171 ExternalAddress((address) StubRoutines::x86::double_sign_flip()));
10172 __ jccb(Assembler::notEqual, done);
10173 __ subptr(rsp, 8);
10174 __ movflt(Address(rsp, 0), $src$$XMMRegister);
10175 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::f2l_fixup())));
10176 __ pop($dst$$Register);
10177 __ bind(done);
10178 %}
10179 ins_pipe(pipe_slow);
10180 %}
10181
10182 instruct convD2I_reg_reg(rRegI dst, regD src, rFlagsReg cr)
10183 %{
10184 match(Set dst (ConvD2I src));
10185 effect(KILL cr);
10186
10187 format %{ "cvttsd2sil $dst, $src\t# d2i\n\t"
10188 "cmpl $dst, #0x80000000\n\t"
10189 "jne,s done\n\t"
10190 "subq rsp, #8\n\t"
10191 "movsd [rsp], $src\n\t"
10192 "call d2i_fixup\n\t"
10193 "popq $dst\n"
10194 "done: "%}
10195 ins_encode %{
10196 Label done;
10197 __ cvttsd2sil($dst$$Register, $src$$XMMRegister);
10198 __ cmpl($dst$$Register, 0x80000000);
10199 __ jccb(Assembler::notEqual, done);
10200 __ subptr(rsp, 8);
10201 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
10202 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::d2i_fixup())));
10203 __ pop($dst$$Register);
10204 __ bind(done);
10205 %}
10206 ins_pipe(pipe_slow);
10207 %}
10208
10209 instruct convD2L_reg_reg(rRegL dst, regD src, rFlagsReg cr)
10210 %{
10211 match(Set dst (ConvD2L src));
10212 effect(KILL cr);
10213
10214 format %{ "cvttsd2siq $dst, $src\t# d2l\n\t"
10215 "cmpq $dst, [0x8000000000000000]\n\t"
10216 "jne,s done\n\t"
10217 "subq rsp, #8\n\t"
10218 "movsd [rsp], $src\n\t"
10219 "call d2l_fixup\n\t"
10220 "popq $dst\n"
10221 "done: "%}
10222 ins_encode %{
10223 Label done;
10224 __ cvttsd2siq($dst$$Register, $src$$XMMRegister);
10225 __ cmp64($dst$$Register,
10226 ExternalAddress((address) StubRoutines::x86::double_sign_flip()));
10227 __ jccb(Assembler::notEqual, done);
10228 __ subptr(rsp, 8);
10229 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
10230 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::d2l_fixup())));
10231 __ pop($dst$$Register);
10232 __ bind(done);
10233 %}
10234 ins_pipe(pipe_slow);
10235 %}
10236
10237 instruct convI2F_reg_reg(regF dst, rRegI src)
10238 %{
10239 predicate(!UseXmmI2F);
10240 match(Set dst (ConvI2F src));
10241
10242 format %{ "cvtsi2ssl $dst, $src\t# i2f" %}
10243 ins_encode %{
10244 __ cvtsi2ssl ($dst$$XMMRegister, $src$$Register);
10245 %}
10246 ins_pipe(pipe_slow); // XXX
10247 %}
10248
10249 instruct convI2F_reg_mem(regF dst, memory src)
10250 %{
10251 match(Set dst (ConvI2F (LoadI src)));
10252
10253 format %{ "cvtsi2ssl $dst, $src\t# i2f" %}
10254 ins_encode %{
10255 __ cvtsi2ssl ($dst$$XMMRegister, $src$$Address);
10256 %}
10257 ins_pipe(pipe_slow); // XXX
10258 %}
10259
10260 instruct convI2D_reg_reg(regD dst, rRegI src)
10261 %{
10262 predicate(!UseXmmI2D);
10263 match(Set dst (ConvI2D src));
10264
10265 format %{ "cvtsi2sdl $dst, $src\t# i2d" %}
10266 ins_encode %{
10267 __ cvtsi2sdl ($dst$$XMMRegister, $src$$Register);
10268 %}
10269 ins_pipe(pipe_slow); // XXX
10270 %}
10271
10272 instruct convI2D_reg_mem(regD dst, memory src)
10273 %{
10274 match(Set dst (ConvI2D (LoadI src)));
10275
10276 format %{ "cvtsi2sdl $dst, $src\t# i2d" %}
10277 ins_encode %{
10278 __ cvtsi2sdl ($dst$$XMMRegister, $src$$Address);
10279 %}
10280 ins_pipe(pipe_slow); // XXX
10281 %}
10282
10283 instruct convXI2F_reg(regF dst, rRegI src)
10284 %{
10285 predicate(UseXmmI2F);
10286 match(Set dst (ConvI2F src));
10287
10288 format %{ "movdl $dst, $src\n\t"
10289 "cvtdq2psl $dst, $dst\t# i2f" %}
10290 ins_encode %{
10291 __ movdl($dst$$XMMRegister, $src$$Register);
10292 __ cvtdq2ps($dst$$XMMRegister, $dst$$XMMRegister);
10293 %}
10294 ins_pipe(pipe_slow); // XXX
10295 %}
10296
10297 instruct convXI2D_reg(regD dst, rRegI src)
10298 %{
10299 predicate(UseXmmI2D);
10300 match(Set dst (ConvI2D src));
10301
10302 format %{ "movdl $dst, $src\n\t"
10303 "cvtdq2pdl $dst, $dst\t# i2d" %}
10304 ins_encode %{
10305 __ movdl($dst$$XMMRegister, $src$$Register);
10306 __ cvtdq2pd($dst$$XMMRegister, $dst$$XMMRegister);
10307 %}
10308 ins_pipe(pipe_slow); // XXX
10309 %}
10310
10311 instruct convL2F_reg_reg(regF dst, rRegL src)
10312 %{
10313 match(Set dst (ConvL2F src));
10314
10315 format %{ "cvtsi2ssq $dst, $src\t# l2f" %}
10316 ins_encode %{
10317 __ cvtsi2ssq ($dst$$XMMRegister, $src$$Register);
10318 %}
10319 ins_pipe(pipe_slow); // XXX
10320 %}
10321
10322 instruct convL2F_reg_mem(regF dst, memory src)
10323 %{
10324 match(Set dst (ConvL2F (LoadL src)));
10325
10326 format %{ "cvtsi2ssq $dst, $src\t# l2f" %}
10327 ins_encode %{
10328 __ cvtsi2ssq ($dst$$XMMRegister, $src$$Address);
10329 %}
10330 ins_pipe(pipe_slow); // XXX
10331 %}
10332
10333 instruct convL2D_reg_reg(regD dst, rRegL src)
10334 %{
10335 match(Set dst (ConvL2D src));
10336
10337 format %{ "cvtsi2sdq $dst, $src\t# l2d" %}
10338 ins_encode %{
10339 __ cvtsi2sdq ($dst$$XMMRegister, $src$$Register);
10340 %}
10341 ins_pipe(pipe_slow); // XXX
10342 %}
10343
10344 instruct convL2D_reg_mem(regD dst, memory src)
10345 %{
10346 match(Set dst (ConvL2D (LoadL src)));
10347
10348 format %{ "cvtsi2sdq $dst, $src\t# l2d" %}
10349 ins_encode %{
10350 __ cvtsi2sdq ($dst$$XMMRegister, $src$$Address);
10351 %}
10352 ins_pipe(pipe_slow); // XXX
10353 %}
10354
10355 instruct convI2L_reg_reg(rRegL dst, rRegI src)
10356 %{
10357 match(Set dst (ConvI2L src));
10358
10359 ins_cost(125);
10360 format %{ "movslq $dst, $src\t# i2l" %}
10361 ins_encode %{
10362 __ movslq($dst$$Register, $src$$Register);
10363 %}
10364 ins_pipe(ialu_reg_reg);
10365 %}
10366
10367 // instruct convI2L_reg_reg_foo(rRegL dst, rRegI src)
10368 // %{
10369 // match(Set dst (ConvI2L src));
10370 // // predicate(_kids[0]->_leaf->as_Type()->type()->is_int()->_lo >= 0 &&
10371 // // _kids[0]->_leaf->as_Type()->type()->is_int()->_hi >= 0);
10372 // predicate(((const TypeNode*) n)->type()->is_long()->_hi ==
10373 // (unsigned int) ((const TypeNode*) n)->type()->is_long()->_hi &&
10374 // ((const TypeNode*) n)->type()->is_long()->_lo ==
10375 // (unsigned int) ((const TypeNode*) n)->type()->is_long()->_lo);
10376
10377 // format %{ "movl $dst, $src\t# unsigned i2l" %}
10378 // ins_encode(enc_copy(dst, src));
10379 // // opcode(0x63); // needs REX.W
10380 // // ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst,src));
10381 // ins_pipe(ialu_reg_reg);
10382 // %}
10383
10384 // Zero-extend convert int to long
10385 instruct convI2L_reg_reg_zex(rRegL dst, rRegI src, immL_32bits mask)
10386 %{
10387 match(Set dst (AndL (ConvI2L src) mask));
10388
10389 format %{ "movl $dst, $src\t# i2l zero-extend\n\t" %}
10390 ins_encode %{
10391 if ($dst$$reg != $src$$reg) {
10392 __ movl($dst$$Register, $src$$Register);
10393 }
10394 %}
10395 ins_pipe(ialu_reg_reg);
10396 %}
10397
10398 // Zero-extend convert int to long
10399 instruct convI2L_reg_mem_zex(rRegL dst, memory src, immL_32bits mask)
10400 %{
10401 match(Set dst (AndL (ConvI2L (LoadI src)) mask));
10402
10403 format %{ "movl $dst, $src\t# i2l zero-extend\n\t" %}
10404 ins_encode %{
10405 __ movl($dst$$Register, $src$$Address);
10406 %}
10407 ins_pipe(ialu_reg_mem);
10408 %}
10409
10410 instruct zerox_long_reg_reg(rRegL dst, rRegL src, immL_32bits mask)
10411 %{
10412 match(Set dst (AndL src mask));
10413
10414 format %{ "movl $dst, $src\t# zero-extend long" %}
10415 ins_encode %{
10416 __ movl($dst$$Register, $src$$Register);
10417 %}
10418 ins_pipe(ialu_reg_reg);
10419 %}
10420
10421 instruct convL2I_reg_reg(rRegI dst, rRegL src)
10422 %{
10423 match(Set dst (ConvL2I src));
10424
10425 format %{ "movl $dst, $src\t# l2i" %}
10426 ins_encode %{
10427 __ movl($dst$$Register, $src$$Register);
10428 %}
10429 ins_pipe(ialu_reg_reg);
10430 %}
10431
10432
10433 instruct MoveF2I_stack_reg(rRegI dst, stackSlotF src) %{
10434 match(Set dst (MoveF2I src));
10435 effect(DEF dst, USE src);
10436
10437 ins_cost(125);
10438 format %{ "movl $dst, $src\t# MoveF2I_stack_reg" %}
10439 ins_encode %{
10440 __ movl($dst$$Register, Address(rsp, $src$$disp));
10441 %}
10442 ins_pipe(ialu_reg_mem);
10443 %}
10444
10445 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{
10446 match(Set dst (MoveI2F src));
10447 effect(DEF dst, USE src);
10448
10449 ins_cost(125);
10450 format %{ "movss $dst, $src\t# MoveI2F_stack_reg" %}
10451 ins_encode %{
10452 __ movflt($dst$$XMMRegister, Address(rsp, $src$$disp));
10453 %}
10454 ins_pipe(pipe_slow);
10455 %}
10456
10457 instruct MoveD2L_stack_reg(rRegL dst, stackSlotD src) %{
10458 match(Set dst (MoveD2L src));
10459 effect(DEF dst, USE src);
10460
10461 ins_cost(125);
10462 format %{ "movq $dst, $src\t# MoveD2L_stack_reg" %}
10463 ins_encode %{
10464 __ movq($dst$$Register, Address(rsp, $src$$disp));
10465 %}
10466 ins_pipe(ialu_reg_mem);
10467 %}
10468
10469 instruct MoveL2D_stack_reg_partial(regD dst, stackSlotL src) %{
10470 predicate(!UseXmmLoadAndClearUpper);
10471 match(Set dst (MoveL2D src));
10472 effect(DEF dst, USE src);
10473
10474 ins_cost(125);
10475 format %{ "movlpd $dst, $src\t# MoveL2D_stack_reg" %}
10476 ins_encode %{
10477 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
10478 %}
10479 ins_pipe(pipe_slow);
10480 %}
10481
10482 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{
10483 predicate(UseXmmLoadAndClearUpper);
10484 match(Set dst (MoveL2D src));
10485 effect(DEF dst, USE src);
10486
10487 ins_cost(125);
10488 format %{ "movsd $dst, $src\t# MoveL2D_stack_reg" %}
10489 ins_encode %{
10490 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
10491 %}
10492 ins_pipe(pipe_slow);
10493 %}
10494
10495
10496 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{
10497 match(Set dst (MoveF2I src));
10498 effect(DEF dst, USE src);
10499
10500 ins_cost(95); // XXX
10501 format %{ "movss $dst, $src\t# MoveF2I_reg_stack" %}
10502 ins_encode %{
10503 __ movflt(Address(rsp, $dst$$disp), $src$$XMMRegister);
10504 %}
10505 ins_pipe(pipe_slow);
10506 %}
10507
10508 instruct MoveI2F_reg_stack(stackSlotF dst, rRegI src) %{
10509 match(Set dst (MoveI2F src));
10510 effect(DEF dst, USE src);
10511
10512 ins_cost(100);
10513 format %{ "movl $dst, $src\t# MoveI2F_reg_stack" %}
10514 ins_encode %{
10515 __ movl(Address(rsp, $dst$$disp), $src$$Register);
10516 %}
10517 ins_pipe( ialu_mem_reg );
10518 %}
10519
10520 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{
10521 match(Set dst (MoveD2L src));
10522 effect(DEF dst, USE src);
10523
10524 ins_cost(95); // XXX
10525 format %{ "movsd $dst, $src\t# MoveL2D_reg_stack" %}
10526 ins_encode %{
10527 __ movdbl(Address(rsp, $dst$$disp), $src$$XMMRegister);
10528 %}
10529 ins_pipe(pipe_slow);
10530 %}
10531
10532 instruct MoveL2D_reg_stack(stackSlotD dst, rRegL src) %{
10533 match(Set dst (MoveL2D src));
10534 effect(DEF dst, USE src);
10535
10536 ins_cost(100);
10537 format %{ "movq $dst, $src\t# MoveL2D_reg_stack" %}
10538 ins_encode %{
10539 __ movq(Address(rsp, $dst$$disp), $src$$Register);
10540 %}
10541 ins_pipe(ialu_mem_reg);
10542 %}
10543
10544 instruct MoveF2I_reg_reg(rRegI dst, regF src) %{
10545 match(Set dst (MoveF2I src));
10546 effect(DEF dst, USE src);
10547 ins_cost(85);
10548 format %{ "movd $dst,$src\t# MoveF2I" %}
10549 ins_encode %{
10550 __ movdl($dst$$Register, $src$$XMMRegister);
10551 %}
10552 ins_pipe( pipe_slow );
10553 %}
10554
10555 instruct MoveD2L_reg_reg(rRegL dst, regD src) %{
10556 match(Set dst (MoveD2L src));
10557 effect(DEF dst, USE src);
10558 ins_cost(85);
10559 format %{ "movd $dst,$src\t# MoveD2L" %}
10560 ins_encode %{
10561 __ movdq($dst$$Register, $src$$XMMRegister);
10562 %}
10563 ins_pipe( pipe_slow );
10564 %}
10565
10566 instruct MoveI2F_reg_reg(regF dst, rRegI src) %{
10567 match(Set dst (MoveI2F src));
10568 effect(DEF dst, USE src);
10569 ins_cost(100);
10570 format %{ "movd $dst,$src\t# MoveI2F" %}
10571 ins_encode %{
10572 __ movdl($dst$$XMMRegister, $src$$Register);
10573 %}
10574 ins_pipe( pipe_slow );
10575 %}
10576
10577 instruct MoveL2D_reg_reg(regD dst, rRegL src) %{
10578 match(Set dst (MoveL2D src));
10579 effect(DEF dst, USE src);
10580 ins_cost(100);
10581 format %{ "movd $dst,$src\t# MoveL2D" %}
10582 ins_encode %{
10583 __ movdq($dst$$XMMRegister, $src$$Register);
10584 %}
10585 ins_pipe( pipe_slow );
10586 %}
10587
10588
10589 // =======================================================================
10590 // fast clearing of an array
10591 instruct rep_stos(rcx_RegL cnt, rdi_RegP base, rax_RegI zero, Universe dummy,
10592 rFlagsReg cr)
10593 %{
10594 predicate(!((ClearArrayNode*)n)->is_large());
10595 match(Set dummy (ClearArray cnt base));
10596 effect(USE_KILL cnt, USE_KILL base, KILL zero, KILL cr);
10597
10598 format %{ $$template
10599 $$emit$$"xorq rax, rax\t# ClearArray:\n\t"
10600 $$emit$$"cmp InitArrayShortSize,rcx\n\t"
10601 $$emit$$"jg LARGE\n\t"
10602 $$emit$$"dec rcx\n\t"
10603 $$emit$$"js DONE\t# Zero length\n\t"
10604 $$emit$$"mov rax,(rdi,rcx,8)\t# LOOP\n\t"
10605 $$emit$$"dec rcx\n\t"
10606 $$emit$$"jge LOOP\n\t"
10607 $$emit$$"jmp DONE\n\t"
10608 $$emit$$"# LARGE:\n\t"
10609 if (UseFastStosb) {
10610 $$emit$$"shlq rcx,3\t# Convert doublewords to bytes\n\t"
10611 $$emit$$"rep stosb\t# Store rax to *rdi++ while rcx--\n\t"
10612 } else {
10613 $$emit$$"rep stosq\t# Store rax to *rdi++ while rcx--\n\t"
10614 }
10615 $$emit$$"# DONE"
10616 %}
10617 ins_encode %{
10618 __ clear_mem($base$$Register, $cnt$$Register, $zero$$Register, false);
10619 %}
10620 ins_pipe(pipe_slow);
10621 %}
10622
10623 instruct rep_stos_large(rcx_RegL cnt, rdi_RegP base, rax_RegI zero, Universe dummy,
10624 rFlagsReg cr)
10625 %{
10626 predicate(((ClearArrayNode*)n)->is_large());
10627 match(Set dummy (ClearArray cnt base));
10628 effect(USE_KILL cnt, USE_KILL base, KILL zero, KILL cr);
10629
10630 format %{ $$template
10631 $$emit$$"xorq rax, rax\t# ClearArray:\n\t"
10632 if (UseFastStosb) {
10633 $$emit$$"shlq rcx,3\t# Convert doublewords to bytes\n\t"
10634 $$emit$$"rep stosb\t# Store rax to *rdi++ while rcx--"
10635 } else {
10636 $$emit$$"rep stosq\t# Store rax to *rdi++ while rcx--"
10637 }
10638 %}
10639 ins_encode %{
10640 __ clear_mem($base$$Register, $cnt$$Register, $zero$$Register, true);
10641 %}
10642 ins_pipe(pipe_slow);
10643 %}
10644
10645 instruct string_compareL(rdi_RegP str1, rcx_RegI cnt1, rsi_RegP str2, rdx_RegI cnt2,
10646 rax_RegI result, regD tmp1, rFlagsReg cr)
10647 %{
10648 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::LL);
10649 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10650 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
10651
10652 format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
10653 ins_encode %{
10654 __ string_compare($str1$$Register, $str2$$Register,
10655 $cnt1$$Register, $cnt2$$Register, $result$$Register,
10656 $tmp1$$XMMRegister, StrIntrinsicNode::LL);
10657 %}
10658 ins_pipe( pipe_slow );
10659 %}
10660
10661 instruct string_compareU(rdi_RegP str1, rcx_RegI cnt1, rsi_RegP str2, rdx_RegI cnt2,
10662 rax_RegI result, regD tmp1, rFlagsReg cr)
10663 %{
10664 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::UU);
10665 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10666 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
10667
10668 format %{ "String Compare char[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
10669 ins_encode %{
10670 __ string_compare($str1$$Register, $str2$$Register,
10671 $cnt1$$Register, $cnt2$$Register, $result$$Register,
10672 $tmp1$$XMMRegister, StrIntrinsicNode::UU);
10673 %}
10674 ins_pipe( pipe_slow );
10675 %}
10676
10677 instruct string_compareLU(rdi_RegP str1, rcx_RegI cnt1, rsi_RegP str2, rdx_RegI cnt2,
10678 rax_RegI result, regD tmp1, rFlagsReg cr)
10679 %{
10680 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::LU);
10681 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10682 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
10683
10684 format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
10685 ins_encode %{
10686 __ string_compare($str1$$Register, $str2$$Register,
10687 $cnt1$$Register, $cnt2$$Register, $result$$Register,
10688 $tmp1$$XMMRegister, StrIntrinsicNode::LU);
10689 %}
10690 ins_pipe( pipe_slow );
10691 %}
10692
10693 instruct string_compareUL(rsi_RegP str1, rdx_RegI cnt1, rdi_RegP str2, rcx_RegI cnt2,
10694 rax_RegI result, regD tmp1, rFlagsReg cr)
10695 %{
10696 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::UL);
10697 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10698 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
10699
10700 format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
10701 ins_encode %{
10702 __ string_compare($str2$$Register, $str1$$Register,
10703 $cnt2$$Register, $cnt1$$Register, $result$$Register,
10704 $tmp1$$XMMRegister, StrIntrinsicNode::UL);
10705 %}
10706 ins_pipe( pipe_slow );
10707 %}
10708
10709 // fast search of substring with known size.
10710 instruct string_indexof_conL(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, immI int_cnt2,
10711 rbx_RegI result, regD vec, rax_RegI cnt2, rcx_RegI tmp, rFlagsReg cr)
10712 %{
10713 predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL));
10714 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
10715 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, KILL cnt2, KILL tmp, KILL cr);
10716
10717 format %{ "String IndexOf byte[] $str1,$cnt1,$str2,$int_cnt2 -> $result // KILL $vec, $cnt1, $cnt2, $tmp" %}
10718 ins_encode %{
10719 int icnt2 = (int)$int_cnt2$$constant;
10720 if (icnt2 >= 16) {
10721 // IndexOf for constant substrings with size >= 16 elements
10722 // which don't need to be loaded through stack.
10723 __ string_indexofC8($str1$$Register, $str2$$Register,
10724 $cnt1$$Register, $cnt2$$Register,
10725 icnt2, $result$$Register,
10726 $vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::LL);
10727 } else {
10728 // Small strings are loaded through stack if they cross page boundary.
10729 __ string_indexof($str1$$Register, $str2$$Register,
10730 $cnt1$$Register, $cnt2$$Register,
10731 icnt2, $result$$Register,
10732 $vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::LL);
10733 }
10734 %}
10735 ins_pipe( pipe_slow );
10736 %}
10737
10738 // fast search of substring with known size.
10739 instruct string_indexof_conU(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, immI int_cnt2,
10740 rbx_RegI result, regD vec, rax_RegI cnt2, rcx_RegI tmp, rFlagsReg cr)
10741 %{
10742 predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU));
10743 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
10744 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, KILL cnt2, KILL tmp, KILL cr);
10745
10746 format %{ "String IndexOf char[] $str1,$cnt1,$str2,$int_cnt2 -> $result // KILL $vec, $cnt1, $cnt2, $tmp" %}
10747 ins_encode %{
10748 int icnt2 = (int)$int_cnt2$$constant;
10749 if (icnt2 >= 8) {
10750 // IndexOf for constant substrings with size >= 8 elements
10751 // which don't need to be loaded through stack.
10752 __ string_indexofC8($str1$$Register, $str2$$Register,
10753 $cnt1$$Register, $cnt2$$Register,
10754 icnt2, $result$$Register,
10755 $vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UU);
10756 } else {
10757 // Small strings are loaded through stack if they cross page boundary.
10758 __ string_indexof($str1$$Register, $str2$$Register,
10759 $cnt1$$Register, $cnt2$$Register,
10760 icnt2, $result$$Register,
10761 $vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UU);
10762 }
10763 %}
10764 ins_pipe( pipe_slow );
10765 %}
10766
10767 // fast search of substring with known size.
10768 instruct string_indexof_conUL(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, immI int_cnt2,
10769 rbx_RegI result, regD vec, rax_RegI cnt2, rcx_RegI tmp, rFlagsReg cr)
10770 %{
10771 predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL));
10772 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
10773 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, KILL cnt2, KILL tmp, KILL cr);
10774
10775 format %{ "String IndexOf char[] $str1,$cnt1,$str2,$int_cnt2 -> $result // KILL $vec, $cnt1, $cnt2, $tmp" %}
10776 ins_encode %{
10777 int icnt2 = (int)$int_cnt2$$constant;
10778 if (icnt2 >= 8) {
10779 // IndexOf for constant substrings with size >= 8 elements
10780 // which don't need to be loaded through stack.
10781 __ string_indexofC8($str1$$Register, $str2$$Register,
10782 $cnt1$$Register, $cnt2$$Register,
10783 icnt2, $result$$Register,
10784 $vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UL);
10785 } else {
10786 // Small strings are loaded through stack if they cross page boundary.
10787 __ string_indexof($str1$$Register, $str2$$Register,
10788 $cnt1$$Register, $cnt2$$Register,
10789 icnt2, $result$$Register,
10790 $vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UL);
10791 }
10792 %}
10793 ins_pipe( pipe_slow );
10794 %}
10795
10796 instruct string_indexofL(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, rax_RegI cnt2,
10797 rbx_RegI result, regD vec, rcx_RegI tmp, rFlagsReg cr)
10798 %{
10799 predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL));
10800 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
10801 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp, KILL cr);
10802
10803 format %{ "String IndexOf byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL all" %}
10804 ins_encode %{
10805 __ string_indexof($str1$$Register, $str2$$Register,
10806 $cnt1$$Register, $cnt2$$Register,
10807 (-1), $result$$Register,
10808 $vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::LL);
10809 %}
10810 ins_pipe( pipe_slow );
10811 %}
10812
10813 instruct string_indexofU(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, rax_RegI cnt2,
10814 rbx_RegI result, regD vec, rcx_RegI tmp, rFlagsReg cr)
10815 %{
10816 predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU));
10817 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
10818 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp, KILL cr);
10819
10820 format %{ "String IndexOf char[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL all" %}
10821 ins_encode %{
10822 __ string_indexof($str1$$Register, $str2$$Register,
10823 $cnt1$$Register, $cnt2$$Register,
10824 (-1), $result$$Register,
10825 $vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UU);
10826 %}
10827 ins_pipe( pipe_slow );
10828 %}
10829
10830 instruct string_indexofUL(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, rax_RegI cnt2,
10831 rbx_RegI result, regD vec, rcx_RegI tmp, rFlagsReg cr)
10832 %{
10833 predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL));
10834 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
10835 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp, KILL cr);
10836
10837 format %{ "String IndexOf char[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL all" %}
10838 ins_encode %{
10839 __ string_indexof($str1$$Register, $str2$$Register,
10840 $cnt1$$Register, $cnt2$$Register,
10841 (-1), $result$$Register,
10842 $vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UL);
10843 %}
10844 ins_pipe( pipe_slow );
10845 %}
10846
10847 instruct string_indexofU_char(rdi_RegP str1, rdx_RegI cnt1, rax_RegI ch,
10848 rbx_RegI result, regD vec1, regD vec2, regD vec3, rcx_RegI tmp, rFlagsReg cr)
10849 %{
10850 predicate(UseSSE42Intrinsics);
10851 match(Set result (StrIndexOfChar (Binary str1 cnt1) ch));
10852 effect(TEMP vec1, TEMP vec2, TEMP vec3, USE_KILL str1, USE_KILL cnt1, USE_KILL ch, TEMP tmp, KILL cr);
10853 format %{ "String IndexOf char[] $str1,$cnt1,$ch -> $result // KILL all" %}
10854 ins_encode %{
10855 __ string_indexof_char($str1$$Register, $cnt1$$Register, $ch$$Register, $result$$Register,
10856 $vec1$$XMMRegister, $vec2$$XMMRegister, $vec3$$XMMRegister, $tmp$$Register);
10857 %}
10858 ins_pipe( pipe_slow );
10859 %}
10860
10861 // fast string equals
10862 instruct string_equals(rdi_RegP str1, rsi_RegP str2, rcx_RegI cnt, rax_RegI result,
10863 regD tmp1, regD tmp2, rbx_RegI tmp3, rFlagsReg cr)
10864 %{
10865 match(Set result (StrEquals (Binary str1 str2) cnt));
10866 effect(TEMP tmp1, TEMP tmp2, USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp3, KILL cr);
10867
10868 format %{ "String Equals $str1,$str2,$cnt -> $result // KILL $tmp1, $tmp2, $tmp3" %}
10869 ins_encode %{
10870 __ arrays_equals(false, $str1$$Register, $str2$$Register,
10871 $cnt$$Register, $result$$Register, $tmp3$$Register,
10872 $tmp1$$XMMRegister, $tmp2$$XMMRegister, false /* char */);
10873 %}
10874 ins_pipe( pipe_slow );
10875 %}
10876
10877 // fast array equals
10878 instruct array_equalsB(rdi_RegP ary1, rsi_RegP ary2, rax_RegI result,
10879 regD tmp1, regD tmp2, rcx_RegI tmp3, rbx_RegI tmp4, rFlagsReg cr)
10880 %{
10881 predicate(((AryEqNode*)n)->encoding() == StrIntrinsicNode::LL);
10882 match(Set result (AryEq ary1 ary2));
10883 effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr);
10884
10885 format %{ "Array Equals byte[] $ary1,$ary2 -> $result // KILL $tmp1, $tmp2, $tmp3, $tmp4" %}
10886 ins_encode %{
10887 __ arrays_equals(true, $ary1$$Register, $ary2$$Register,
10888 $tmp3$$Register, $result$$Register, $tmp4$$Register,
10889 $tmp1$$XMMRegister, $tmp2$$XMMRegister, false /* char */);
10890 %}
10891 ins_pipe( pipe_slow );
10892 %}
10893
10894 instruct array_equalsC(rdi_RegP ary1, rsi_RegP ary2, rax_RegI result,
10895 regD tmp1, regD tmp2, rcx_RegI tmp3, rbx_RegI tmp4, rFlagsReg cr)
10896 %{
10897 predicate(((AryEqNode*)n)->encoding() == StrIntrinsicNode::UU);
10898 match(Set result (AryEq ary1 ary2));
10899 effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr);
10900
10901 format %{ "Array Equals char[] $ary1,$ary2 -> $result // KILL $tmp1, $tmp2, $tmp3, $tmp4" %}
10902 ins_encode %{
10903 __ arrays_equals(true, $ary1$$Register, $ary2$$Register,
10904 $tmp3$$Register, $result$$Register, $tmp4$$Register,
10905 $tmp1$$XMMRegister, $tmp2$$XMMRegister, true /* char */);
10906 %}
10907 ins_pipe( pipe_slow );
10908 %}
10909
10910 instruct has_negatives(rsi_RegP ary1, rcx_RegI len, rax_RegI result,
10911 regD tmp1, regD tmp2, rbx_RegI tmp3, rFlagsReg cr)
10912 %{
10913 match(Set result (HasNegatives ary1 len));
10914 effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL len, KILL tmp3, KILL cr);
10915
10916 format %{ "has negatives byte[] $ary1,$len -> $result // KILL $tmp1, $tmp2, $tmp3" %}
10917 ins_encode %{
10918 __ has_negatives($ary1$$Register, $len$$Register,
10919 $result$$Register, $tmp3$$Register,
10920 $tmp1$$XMMRegister, $tmp2$$XMMRegister);
10921 %}
10922 ins_pipe( pipe_slow );
10923 %}
10924
10925 // fast char[] to byte[] compression
10926 instruct string_compress(rsi_RegP src, rdi_RegP dst, rdx_RegI len, regD tmp1, regD tmp2, regD tmp3, regD tmp4,
10927 rcx_RegI tmp5, rax_RegI result, rFlagsReg cr) %{
10928 match(Set result (StrCompressedCopy src (Binary dst len)));
10929 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, USE_KILL src, USE_KILL dst, USE_KILL len, KILL tmp5, KILL cr);
10930
10931 format %{ "String Compress $src,$dst -> $result // KILL RAX, RCX, RDX" %}
10932 ins_encode %{
10933 __ char_array_compress($src$$Register, $dst$$Register, $len$$Register,
10934 $tmp1$$XMMRegister, $tmp2$$XMMRegister, $tmp3$$XMMRegister,
10935 $tmp4$$XMMRegister, $tmp5$$Register, $result$$Register);
10936 %}
10937 ins_pipe( pipe_slow );
10938 %}
10939
10940 // fast byte[] to char[] inflation
10941 instruct string_inflate(Universe dummy, rsi_RegP src, rdi_RegP dst, rdx_RegI len,
10942 regD tmp1, rcx_RegI tmp2, rFlagsReg cr) %{
10943 match(Set dummy (StrInflatedCopy src (Binary dst len)));
10944 effect(TEMP tmp1, TEMP tmp2, USE_KILL src, USE_KILL dst, USE_KILL len, KILL cr);
10945
10946 format %{ "String Inflate $src,$dst // KILL $tmp1, $tmp2" %}
10947 ins_encode %{
10948 __ byte_array_inflate($src$$Register, $dst$$Register, $len$$Register,
10949 $tmp1$$XMMRegister, $tmp2$$Register);
10950 %}
10951 ins_pipe( pipe_slow );
10952 %}
10953
10954 // encode char[] to byte[] in ISO_8859_1
10955 instruct encode_iso_array(rsi_RegP src, rdi_RegP dst, rdx_RegI len,
10956 regD tmp1, regD tmp2, regD tmp3, regD tmp4,
10957 rcx_RegI tmp5, rax_RegI result, rFlagsReg cr) %{
10958 match(Set result (EncodeISOArray src (Binary dst len)));
10959 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, USE_KILL src, USE_KILL dst, USE_KILL len, KILL tmp5, KILL cr);
10960
10961 format %{ "Encode array $src,$dst,$len -> $result // KILL RCX, RDX, $tmp1, $tmp2, $tmp3, $tmp4, RSI, RDI " %}
10962 ins_encode %{
10963 __ encode_iso_array($src$$Register, $dst$$Register, $len$$Register,
10964 $tmp1$$XMMRegister, $tmp2$$XMMRegister, $tmp3$$XMMRegister,
10965 $tmp4$$XMMRegister, $tmp5$$Register, $result$$Register);
10966 %}
10967 ins_pipe( pipe_slow );
10968 %}
10969
10970 //----------Overflow Math Instructions-----------------------------------------
10971
10972 instruct overflowAddI_rReg(rFlagsReg cr, rax_RegI op1, rRegI op2)
10973 %{
10974 match(Set cr (OverflowAddI op1 op2));
10975 effect(DEF cr, USE_KILL op1, USE op2);
10976
10977 format %{ "addl $op1, $op2\t# overflow check int" %}
10978
10979 ins_encode %{
10980 __ addl($op1$$Register, $op2$$Register);
10981 %}
10982 ins_pipe(ialu_reg_reg);
10983 %}
10984
10985 instruct overflowAddI_rReg_imm(rFlagsReg cr, rax_RegI op1, immI op2)
10986 %{
10987 match(Set cr (OverflowAddI op1 op2));
10988 effect(DEF cr, USE_KILL op1, USE op2);
10989
10990 format %{ "addl $op1, $op2\t# overflow check int" %}
10991
10992 ins_encode %{
10993 __ addl($op1$$Register, $op2$$constant);
10994 %}
10995 ins_pipe(ialu_reg_reg);
10996 %}
10997
10998 instruct overflowAddL_rReg(rFlagsReg cr, rax_RegL op1, rRegL op2)
10999 %{
11000 match(Set cr (OverflowAddL op1 op2));
11001 effect(DEF cr, USE_KILL op1, USE op2);
11002
11003 format %{ "addq $op1, $op2\t# overflow check long" %}
11004 ins_encode %{
11005 __ addq($op1$$Register, $op2$$Register);
11006 %}
11007 ins_pipe(ialu_reg_reg);
11008 %}
11009
11010 instruct overflowAddL_rReg_imm(rFlagsReg cr, rax_RegL op1, immL32 op2)
11011 %{
11012 match(Set cr (OverflowAddL op1 op2));
11013 effect(DEF cr, USE_KILL op1, USE op2);
11014
11015 format %{ "addq $op1, $op2\t# overflow check long" %}
11016 ins_encode %{
11017 __ addq($op1$$Register, $op2$$constant);
11018 %}
11019 ins_pipe(ialu_reg_reg);
11020 %}
11021
11022 instruct overflowSubI_rReg(rFlagsReg cr, rRegI op1, rRegI op2)
11023 %{
11024 match(Set cr (OverflowSubI op1 op2));
11025
11026 format %{ "cmpl $op1, $op2\t# overflow check int" %}
11027 ins_encode %{
11028 __ cmpl($op1$$Register, $op2$$Register);
11029 %}
11030 ins_pipe(ialu_reg_reg);
11031 %}
11032
11033 instruct overflowSubI_rReg_imm(rFlagsReg cr, rRegI op1, immI op2)
11034 %{
11035 match(Set cr (OverflowSubI op1 op2));
11036
11037 format %{ "cmpl $op1, $op2\t# overflow check int" %}
11038 ins_encode %{
11039 __ cmpl($op1$$Register, $op2$$constant);
11040 %}
11041 ins_pipe(ialu_reg_reg);
11042 %}
11043
11044 instruct overflowSubL_rReg(rFlagsReg cr, rRegL op1, rRegL op2)
11045 %{
11046 match(Set cr (OverflowSubL op1 op2));
11047
11048 format %{ "cmpq $op1, $op2\t# overflow check long" %}
11049 ins_encode %{
11050 __ cmpq($op1$$Register, $op2$$Register);
11051 %}
11052 ins_pipe(ialu_reg_reg);
11053 %}
11054
11055 instruct overflowSubL_rReg_imm(rFlagsReg cr, rRegL op1, immL32 op2)
11056 %{
11057 match(Set cr (OverflowSubL op1 op2));
11058
11059 format %{ "cmpq $op1, $op2\t# overflow check long" %}
11060 ins_encode %{
11061 __ cmpq($op1$$Register, $op2$$constant);
11062 %}
11063 ins_pipe(ialu_reg_reg);
11064 %}
11065
11066 instruct overflowNegI_rReg(rFlagsReg cr, immI0 zero, rax_RegI op2)
11067 %{
11068 match(Set cr (OverflowSubI zero op2));
11069 effect(DEF cr, USE_KILL op2);
11070
11071 format %{ "negl $op2\t# overflow check int" %}
11072 ins_encode %{
11073 __ negl($op2$$Register);
11074 %}
11075 ins_pipe(ialu_reg_reg);
11076 %}
11077
11078 instruct overflowNegL_rReg(rFlagsReg cr, immL0 zero, rax_RegL op2)
11079 %{
11080 match(Set cr (OverflowSubL zero op2));
11081 effect(DEF cr, USE_KILL op2);
11082
11083 format %{ "negq $op2\t# overflow check long" %}
11084 ins_encode %{
11085 __ negq($op2$$Register);
11086 %}
11087 ins_pipe(ialu_reg_reg);
11088 %}
11089
11090 instruct overflowMulI_rReg(rFlagsReg cr, rax_RegI op1, rRegI op2)
11091 %{
11092 match(Set cr (OverflowMulI op1 op2));
11093 effect(DEF cr, USE_KILL op1, USE op2);
11094
11095 format %{ "imull $op1, $op2\t# overflow check int" %}
11096 ins_encode %{
11097 __ imull($op1$$Register, $op2$$Register);
11098 %}
11099 ins_pipe(ialu_reg_reg_alu0);
11100 %}
11101
11102 instruct overflowMulI_rReg_imm(rFlagsReg cr, rRegI op1, immI op2, rRegI tmp)
11103 %{
11104 match(Set cr (OverflowMulI op1 op2));
11105 effect(DEF cr, TEMP tmp, USE op1, USE op2);
11106
11107 format %{ "imull $tmp, $op1, $op2\t# overflow check int" %}
11108 ins_encode %{
11109 __ imull($tmp$$Register, $op1$$Register, $op2$$constant);
11110 %}
11111 ins_pipe(ialu_reg_reg_alu0);
11112 %}
11113
11114 instruct overflowMulL_rReg(rFlagsReg cr, rax_RegL op1, rRegL op2)
11115 %{
11116 match(Set cr (OverflowMulL op1 op2));
11117 effect(DEF cr, USE_KILL op1, USE op2);
11118
11119 format %{ "imulq $op1, $op2\t# overflow check long" %}
11120 ins_encode %{
11121 __ imulq($op1$$Register, $op2$$Register);
11122 %}
11123 ins_pipe(ialu_reg_reg_alu0);
11124 %}
11125
11126 instruct overflowMulL_rReg_imm(rFlagsReg cr, rRegL op1, immL32 op2, rRegL tmp)
11127 %{
11128 match(Set cr (OverflowMulL op1 op2));
11129 effect(DEF cr, TEMP tmp, USE op1, USE op2);
11130
11131 format %{ "imulq $tmp, $op1, $op2\t# overflow check long" %}
11132 ins_encode %{
11133 __ imulq($tmp$$Register, $op1$$Register, $op2$$constant);
11134 %}
11135 ins_pipe(ialu_reg_reg_alu0);
11136 %}
11137
11138
11139 //----------Control Flow Instructions------------------------------------------
11140 // Signed compare Instructions
11141
11142 // XXX more variants!!
11143 instruct compI_rReg(rFlagsReg cr, rRegI op1, rRegI op2)
11144 %{
11145 match(Set cr (CmpI op1 op2));
11146 effect(DEF cr, USE op1, USE op2);
11147
11148 format %{ "cmpl $op1, $op2" %}
11149 opcode(0x3B); /* Opcode 3B /r */
11150 ins_encode(REX_reg_reg(op1, op2), OpcP, reg_reg(op1, op2));
11151 ins_pipe(ialu_cr_reg_reg);
11152 %}
11153
11154 instruct compI_rReg_imm(rFlagsReg cr, rRegI op1, immI op2)
11155 %{
11156 match(Set cr (CmpI op1 op2));
11157
11158 format %{ "cmpl $op1, $op2" %}
11159 opcode(0x81, 0x07); /* Opcode 81 /7 */
11160 ins_encode(OpcSErm(op1, op2), Con8or32(op2));
11161 ins_pipe(ialu_cr_reg_imm);
11162 %}
11163
11164 instruct compI_rReg_mem(rFlagsReg cr, rRegI op1, memory op2)
11165 %{
11166 match(Set cr (CmpI op1 (LoadI op2)));
11167
11168 ins_cost(500); // XXX
11169 format %{ "cmpl $op1, $op2" %}
11170 opcode(0x3B); /* Opcode 3B /r */
11171 ins_encode(REX_reg_mem(op1, op2), OpcP, reg_mem(op1, op2));
11172 ins_pipe(ialu_cr_reg_mem);
11173 %}
11174
11175 instruct testI_reg(rFlagsReg cr, rRegI src, immI0 zero)
11176 %{
11177 match(Set cr (CmpI src zero));
11178
11179 format %{ "testl $src, $src" %}
11180 opcode(0x85);
11181 ins_encode(REX_reg_reg(src, src), OpcP, reg_reg(src, src));
11182 ins_pipe(ialu_cr_reg_imm);
11183 %}
11184
11185 instruct testI_reg_imm(rFlagsReg cr, rRegI src, immI con, immI0 zero)
11186 %{
11187 match(Set cr (CmpI (AndI src con) zero));
11188
11189 format %{ "testl $src, $con" %}
11190 opcode(0xF7, 0x00);
11191 ins_encode(REX_reg(src), OpcP, reg_opc(src), Con32(con));
11192 ins_pipe(ialu_cr_reg_imm);
11193 %}
11194
11195 instruct testI_reg_mem(rFlagsReg cr, rRegI src, memory mem, immI0 zero)
11196 %{
11197 match(Set cr (CmpI (AndI src (LoadI mem)) zero));
11198
11199 format %{ "testl $src, $mem" %}
11200 opcode(0x85);
11201 ins_encode(REX_reg_mem(src, mem), OpcP, reg_mem(src, mem));
11202 ins_pipe(ialu_cr_reg_mem);
11203 %}
11204
11205 // Unsigned compare Instructions; really, same as signed except they
11206 // produce an rFlagsRegU instead of rFlagsReg.
11207 instruct compU_rReg(rFlagsRegU cr, rRegI op1, rRegI op2)
11208 %{
11209 match(Set cr (CmpU op1 op2));
11210
11211 format %{ "cmpl $op1, $op2\t# unsigned" %}
11212 opcode(0x3B); /* Opcode 3B /r */
11213 ins_encode(REX_reg_reg(op1, op2), OpcP, reg_reg(op1, op2));
11214 ins_pipe(ialu_cr_reg_reg);
11215 %}
11216
11217 instruct compU_rReg_imm(rFlagsRegU cr, rRegI op1, immI op2)
11218 %{
11219 match(Set cr (CmpU op1 op2));
11220
11221 format %{ "cmpl $op1, $op2\t# unsigned" %}
11222 opcode(0x81,0x07); /* Opcode 81 /7 */
11223 ins_encode(OpcSErm(op1, op2), Con8or32(op2));
11224 ins_pipe(ialu_cr_reg_imm);
11225 %}
11226
11227 instruct compU_rReg_mem(rFlagsRegU cr, rRegI op1, memory op2)
11228 %{
11229 match(Set cr (CmpU op1 (LoadI op2)));
11230
11231 ins_cost(500); // XXX
11232 format %{ "cmpl $op1, $op2\t# unsigned" %}
11233 opcode(0x3B); /* Opcode 3B /r */
11234 ins_encode(REX_reg_mem(op1, op2), OpcP, reg_mem(op1, op2));
11235 ins_pipe(ialu_cr_reg_mem);
11236 %}
11237
11238 // // // Cisc-spilled version of cmpU_rReg
11239 // //instruct compU_mem_rReg(rFlagsRegU cr, memory op1, rRegI op2)
11240 // //%{
11241 // // match(Set cr (CmpU (LoadI op1) op2));
11242 // //
11243 // // format %{ "CMPu $op1,$op2" %}
11244 // // ins_cost(500);
11245 // // opcode(0x39); /* Opcode 39 /r */
11246 // // ins_encode( OpcP, reg_mem( op1, op2) );
11247 // //%}
11248
11249 instruct testU_reg(rFlagsRegU cr, rRegI src, immI0 zero)
11250 %{
11251 match(Set cr (CmpU src zero));
11252
11253 format %{ "testl $src, $src\t# unsigned" %}
11254 opcode(0x85);
11255 ins_encode(REX_reg_reg(src, src), OpcP, reg_reg(src, src));
11256 ins_pipe(ialu_cr_reg_imm);
11257 %}
11258
11259 instruct compP_rReg(rFlagsRegU cr, rRegP op1, rRegP op2)
11260 %{
11261 match(Set cr (CmpP op1 op2));
11262
11263 format %{ "cmpq $op1, $op2\t# ptr" %}
11264 opcode(0x3B); /* Opcode 3B /r */
11265 ins_encode(REX_reg_reg_wide(op1, op2), OpcP, reg_reg(op1, op2));
11266 ins_pipe(ialu_cr_reg_reg);
11267 %}
11268
11269 instruct compP_rReg_mem(rFlagsRegU cr, rRegP op1, memory op2)
11270 %{
11271 match(Set cr (CmpP op1 (LoadP op2)));
11272
11273 ins_cost(500); // XXX
11274 format %{ "cmpq $op1, $op2\t# ptr" %}
11275 opcode(0x3B); /* Opcode 3B /r */
11276 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2));
11277 ins_pipe(ialu_cr_reg_mem);
11278 %}
11279
11280 // // // Cisc-spilled version of cmpP_rReg
11281 // //instruct compP_mem_rReg(rFlagsRegU cr, memory op1, rRegP op2)
11282 // //%{
11283 // // match(Set cr (CmpP (LoadP op1) op2));
11284 // //
11285 // // format %{ "CMPu $op1,$op2" %}
11286 // // ins_cost(500);
11287 // // opcode(0x39); /* Opcode 39 /r */
11288 // // ins_encode( OpcP, reg_mem( op1, op2) );
11289 // //%}
11290
11291 // XXX this is generalized by compP_rReg_mem???
11292 // Compare raw pointer (used in out-of-heap check).
11293 // Only works because non-oop pointers must be raw pointers
11294 // and raw pointers have no anti-dependencies.
11295 instruct compP_mem_rReg(rFlagsRegU cr, rRegP op1, memory op2)
11296 %{
11297 predicate(n->in(2)->in(2)->bottom_type()->reloc() == relocInfo::none);
11298 match(Set cr (CmpP op1 (LoadP op2)));
11299
11300 format %{ "cmpq $op1, $op2\t# raw ptr" %}
11301 opcode(0x3B); /* Opcode 3B /r */
11302 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2));
11303 ins_pipe(ialu_cr_reg_mem);
11304 %}
11305
11306 // This will generate a signed flags result. This should be OK since
11307 // any compare to a zero should be eq/neq.
11308 instruct testP_reg(rFlagsReg cr, rRegP src, immP0 zero)
11309 %{
11310 match(Set cr (CmpP src zero));
11311
11312 format %{ "testq $src, $src\t# ptr" %}
11313 opcode(0x85);
11314 ins_encode(REX_reg_reg_wide(src, src), OpcP, reg_reg(src, src));
11315 ins_pipe(ialu_cr_reg_imm);
11316 %}
11317
11318 // This will generate a signed flags result. This should be OK since
11319 // any compare to a zero should be eq/neq.
11320 instruct testP_mem(rFlagsReg cr, memory op, immP0 zero)
11321 %{
11322 predicate(!UseCompressedOops || (Universe::narrow_oop_base() != NULL));
11323 match(Set cr (CmpP (LoadP op) zero));
11324
11325 ins_cost(500); // XXX
11326 format %{ "testq $op, 0xffffffffffffffff\t# ptr" %}
11327 opcode(0xF7); /* Opcode F7 /0 */
11328 ins_encode(REX_mem_wide(op),
11329 OpcP, RM_opc_mem(0x00, op), Con_d32(0xFFFFFFFF));
11330 ins_pipe(ialu_cr_reg_imm);
11331 %}
11332
11333 instruct testP_mem_reg0(rFlagsReg cr, memory mem, immP0 zero)
11334 %{
11335 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
11336 match(Set cr (CmpP (LoadP mem) zero));
11337
11338 format %{ "cmpq R12, $mem\t# ptr (R12_heapbase==0)" %}
11339 ins_encode %{
11340 __ cmpq(r12, $mem$$Address);
11341 %}
11342 ins_pipe(ialu_cr_reg_mem);
11343 %}
11344
11345 instruct compN_rReg(rFlagsRegU cr, rRegN op1, rRegN op2)
11346 %{
11347 match(Set cr (CmpN op1 op2));
11348
11349 format %{ "cmpl $op1, $op2\t# compressed ptr" %}
11350 ins_encode %{ __ cmpl($op1$$Register, $op2$$Register); %}
11351 ins_pipe(ialu_cr_reg_reg);
11352 %}
11353
11354 instruct compN_rReg_mem(rFlagsRegU cr, rRegN src, memory mem)
11355 %{
11356 match(Set cr (CmpN src (LoadN mem)));
11357
11358 format %{ "cmpl $src, $mem\t# compressed ptr" %}
11359 ins_encode %{
11360 __ cmpl($src$$Register, $mem$$Address);
11361 %}
11362 ins_pipe(ialu_cr_reg_mem);
11363 %}
11364
11365 instruct compN_rReg_imm(rFlagsRegU cr, rRegN op1, immN op2) %{
11366 match(Set cr (CmpN op1 op2));
11367
11368 format %{ "cmpl $op1, $op2\t# compressed ptr" %}
11369 ins_encode %{
11370 __ cmp_narrow_oop($op1$$Register, (jobject)$op2$$constant);
11371 %}
11372 ins_pipe(ialu_cr_reg_imm);
11373 %}
11374
11375 instruct compN_mem_imm(rFlagsRegU cr, memory mem, immN src)
11376 %{
11377 match(Set cr (CmpN src (LoadN mem)));
11378
11379 format %{ "cmpl $mem, $src\t# compressed ptr" %}
11380 ins_encode %{
11381 __ cmp_narrow_oop($mem$$Address, (jobject)$src$$constant);
11382 %}
11383 ins_pipe(ialu_cr_reg_mem);
11384 %}
11385
11386 instruct compN_rReg_imm_klass(rFlagsRegU cr, rRegN op1, immNKlass op2) %{
11387 match(Set cr (CmpN op1 op2));
11388
11389 format %{ "cmpl $op1, $op2\t# compressed klass ptr" %}
11390 ins_encode %{
11391 __ cmp_narrow_klass($op1$$Register, (Klass*)$op2$$constant);
11392 %}
11393 ins_pipe(ialu_cr_reg_imm);
11394 %}
11395
11396 instruct compN_mem_imm_klass(rFlagsRegU cr, memory mem, immNKlass src)
11397 %{
11398 match(Set cr (CmpN src (LoadNKlass mem)));
11399
11400 format %{ "cmpl $mem, $src\t# compressed klass ptr" %}
11401 ins_encode %{
11402 __ cmp_narrow_klass($mem$$Address, (Klass*)$src$$constant);
11403 %}
11404 ins_pipe(ialu_cr_reg_mem);
11405 %}
11406
11407 instruct testN_reg(rFlagsReg cr, rRegN src, immN0 zero) %{
11408 match(Set cr (CmpN src zero));
11409
11410 format %{ "testl $src, $src\t# compressed ptr" %}
11411 ins_encode %{ __ testl($src$$Register, $src$$Register); %}
11412 ins_pipe(ialu_cr_reg_imm);
11413 %}
11414
11415 instruct testN_mem(rFlagsReg cr, memory mem, immN0 zero)
11416 %{
11417 predicate(Universe::narrow_oop_base() != NULL);
11418 match(Set cr (CmpN (LoadN mem) zero));
11419
11420 ins_cost(500); // XXX
11421 format %{ "testl $mem, 0xffffffff\t# compressed ptr" %}
11422 ins_encode %{
11423 __ cmpl($mem$$Address, (int)0xFFFFFFFF);
11424 %}
11425 ins_pipe(ialu_cr_reg_mem);
11426 %}
11427
11428 instruct testN_mem_reg0(rFlagsReg cr, memory mem, immN0 zero)
11429 %{
11430 predicate(Universe::narrow_oop_base() == NULL && (Universe::narrow_klass_base() == NULL));
11431 match(Set cr (CmpN (LoadN mem) zero));
11432
11433 format %{ "cmpl R12, $mem\t# compressed ptr (R12_heapbase==0)" %}
11434 ins_encode %{
11435 __ cmpl(r12, $mem$$Address);
11436 %}
11437 ins_pipe(ialu_cr_reg_mem);
11438 %}
11439
11440 // Yanked all unsigned pointer compare operations.
11441 // Pointer compares are done with CmpP which is already unsigned.
11442
11443 instruct compL_rReg(rFlagsReg cr, rRegL op1, rRegL op2)
11444 %{
11445 match(Set cr (CmpL op1 op2));
11446
11447 format %{ "cmpq $op1, $op2" %}
11448 opcode(0x3B); /* Opcode 3B /r */
11449 ins_encode(REX_reg_reg_wide(op1, op2), OpcP, reg_reg(op1, op2));
11450 ins_pipe(ialu_cr_reg_reg);
11451 %}
11452
11453 instruct compL_rReg_imm(rFlagsReg cr, rRegL op1, immL32 op2)
11454 %{
11455 match(Set cr (CmpL op1 op2));
11456
11457 format %{ "cmpq $op1, $op2" %}
11458 opcode(0x81, 0x07); /* Opcode 81 /7 */
11459 ins_encode(OpcSErm_wide(op1, op2), Con8or32(op2));
11460 ins_pipe(ialu_cr_reg_imm);
11461 %}
11462
11463 instruct compL_rReg_mem(rFlagsReg cr, rRegL op1, memory op2)
11464 %{
11465 match(Set cr (CmpL op1 (LoadL op2)));
11466
11467 format %{ "cmpq $op1, $op2" %}
11468 opcode(0x3B); /* Opcode 3B /r */
11469 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2));
11470 ins_pipe(ialu_cr_reg_mem);
11471 %}
11472
11473 instruct testL_reg(rFlagsReg cr, rRegL src, immL0 zero)
11474 %{
11475 match(Set cr (CmpL src zero));
11476
11477 format %{ "testq $src, $src" %}
11478 opcode(0x85);
11479 ins_encode(REX_reg_reg_wide(src, src), OpcP, reg_reg(src, src));
11480 ins_pipe(ialu_cr_reg_imm);
11481 %}
11482
11483 instruct testL_reg_imm(rFlagsReg cr, rRegL src, immL32 con, immL0 zero)
11484 %{
11485 match(Set cr (CmpL (AndL src con) zero));
11486
11487 format %{ "testq $src, $con\t# long" %}
11488 opcode(0xF7, 0x00);
11489 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src), Con32(con));
11490 ins_pipe(ialu_cr_reg_imm);
11491 %}
11492
11493 instruct testL_reg_mem(rFlagsReg cr, rRegL src, memory mem, immL0 zero)
11494 %{
11495 match(Set cr (CmpL (AndL src (LoadL mem)) zero));
11496
11497 format %{ "testq $src, $mem" %}
11498 opcode(0x85);
11499 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem));
11500 ins_pipe(ialu_cr_reg_mem);
11501 %}
11502
11503 // Manifest a CmpL result in an integer register. Very painful.
11504 // This is the test to avoid.
11505 instruct cmpL3_reg_reg(rRegI dst, rRegL src1, rRegL src2, rFlagsReg flags)
11506 %{
11507 match(Set dst (CmpL3 src1 src2));
11508 effect(KILL flags);
11509
11510 ins_cost(275); // XXX
11511 format %{ "cmpq $src1, $src2\t# CmpL3\n\t"
11512 "movl $dst, -1\n\t"
11513 "jl,s done\n\t"
11514 "setne $dst\n\t"
11515 "movzbl $dst, $dst\n\t"
11516 "done:" %}
11517 ins_encode(cmpl3_flag(src1, src2, dst));
11518 ins_pipe(pipe_slow);
11519 %}
11520
11521 //----------Max and Min--------------------------------------------------------
11522 // Min Instructions
11523
11524 instruct cmovI_reg_g(rRegI dst, rRegI src, rFlagsReg cr)
11525 %{
11526 effect(USE_DEF dst, USE src, USE cr);
11527
11528 format %{ "cmovlgt $dst, $src\t# min" %}
11529 opcode(0x0F, 0x4F);
11530 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
11531 ins_pipe(pipe_cmov_reg);
11532 %}
11533
11534
11535 instruct minI_rReg(rRegI dst, rRegI src)
11536 %{
11537 match(Set dst (MinI dst src));
11538
11539 ins_cost(200);
11540 expand %{
11541 rFlagsReg cr;
11542 compI_rReg(cr, dst, src);
11543 cmovI_reg_g(dst, src, cr);
11544 %}
11545 %}
11546
11547 instruct cmovI_reg_l(rRegI dst, rRegI src, rFlagsReg cr)
11548 %{
11549 effect(USE_DEF dst, USE src, USE cr);
11550
11551 format %{ "cmovllt $dst, $src\t# max" %}
11552 opcode(0x0F, 0x4C);
11553 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
11554 ins_pipe(pipe_cmov_reg);
11555 %}
11556
11557
11558 instruct maxI_rReg(rRegI dst, rRegI src)
11559 %{
11560 match(Set dst (MaxI dst src));
11561
11562 ins_cost(200);
11563 expand %{
11564 rFlagsReg cr;
11565 compI_rReg(cr, dst, src);
11566 cmovI_reg_l(dst, src, cr);
11567 %}
11568 %}
11569
11570 // ============================================================================
11571 // Branch Instructions
11572
11573 // Jump Direct - Label defines a relative address from JMP+1
11574 instruct jmpDir(label labl)
11575 %{
11576 match(Goto);
11577 effect(USE labl);
11578
11579 ins_cost(300);
11580 format %{ "jmp $labl" %}
11581 size(5);
11582 ins_encode %{
11583 Label* L = $labl$$label;
11584 __ jmp(*L, false); // Always long jump
11585 %}
11586 ins_pipe(pipe_jmp);
11587 %}
11588
11589 // Jump Direct Conditional - Label defines a relative address from Jcc+1
11590 instruct jmpCon(cmpOp cop, rFlagsReg cr, label labl)
11591 %{
11592 match(If cop cr);
11593 effect(USE labl);
11594
11595 ins_cost(300);
11596 format %{ "j$cop $labl" %}
11597 size(6);
11598 ins_encode %{
11599 Label* L = $labl$$label;
11600 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
11601 %}
11602 ins_pipe(pipe_jcc);
11603 %}
11604
11605 // Jump Direct Conditional - Label defines a relative address from Jcc+1
11606 instruct jmpLoopEnd(cmpOp cop, rFlagsReg cr, label labl)
11607 %{
11608 predicate(!n->has_vector_mask_set());
11609 match(CountedLoopEnd cop cr);
11610 effect(USE labl);
11611
11612 ins_cost(300);
11613 format %{ "j$cop $labl\t# loop end" %}
11614 size(6);
11615 ins_encode %{
11616 Label* L = $labl$$label;
11617 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
11618 %}
11619 ins_pipe(pipe_jcc);
11620 %}
11621
11622 // Jump Direct Conditional - Label defines a relative address from Jcc+1
11623 instruct jmpLoopEndU(cmpOpU cop, rFlagsRegU cmp, label labl) %{
11624 predicate(!n->has_vector_mask_set());
11625 match(CountedLoopEnd cop cmp);
11626 effect(USE labl);
11627
11628 ins_cost(300);
11629 format %{ "j$cop,u $labl\t# loop end" %}
11630 size(6);
11631 ins_encode %{
11632 Label* L = $labl$$label;
11633 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
11634 %}
11635 ins_pipe(pipe_jcc);
11636 %}
11637
11638 instruct jmpLoopEndUCF(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
11639 predicate(!n->has_vector_mask_set());
11640 match(CountedLoopEnd cop cmp);
11641 effect(USE labl);
11642
11643 ins_cost(200);
11644 format %{ "j$cop,u $labl\t# loop end" %}
11645 size(6);
11646 ins_encode %{
11647 Label* L = $labl$$label;
11648 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
11649 %}
11650 ins_pipe(pipe_jcc);
11651 %}
11652
11653 // mask version
11654 // Jump Direct Conditional - Label defines a relative address from Jcc+1
11655 instruct jmpLoopEnd_and_restoreMask(cmpOp cop, rFlagsReg cr, label labl)
11656 %{
11657 predicate(n->has_vector_mask_set());
11658 match(CountedLoopEnd cop cr);
11659 effect(USE labl);
11660
11661 ins_cost(400);
11662 format %{ "j$cop $labl\t# loop end\n\t"
11663 "restorevectmask \t# vector mask restore for loops" %}
11664 size(10);
11665 ins_encode %{
11666 Label* L = $labl$$label;
11667 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
11668 __ restorevectmask();
11669 %}
11670 ins_pipe(pipe_jcc);
11671 %}
11672
11673 // Jump Direct Conditional - Label defines a relative address from Jcc+1
11674 instruct jmpLoopEndU_and_restoreMask(cmpOpU cop, rFlagsRegU cmp, label labl) %{
11675 predicate(n->has_vector_mask_set());
11676 match(CountedLoopEnd cop cmp);
11677 effect(USE labl);
11678
11679 ins_cost(400);
11680 format %{ "j$cop,u $labl\t# loop end\n\t"
11681 "restorevectmask \t# vector mask restore for loops" %}
11682 size(10);
11683 ins_encode %{
11684 Label* L = $labl$$label;
11685 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
11686 __ restorevectmask();
11687 %}
11688 ins_pipe(pipe_jcc);
11689 %}
11690
11691 instruct jmpLoopEndUCF_and_restoreMask(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
11692 predicate(n->has_vector_mask_set());
11693 match(CountedLoopEnd cop cmp);
11694 effect(USE labl);
11695
11696 ins_cost(300);
11697 format %{ "j$cop,u $labl\t# loop end\n\t"
11698 "restorevectmask \t# vector mask restore for loops" %}
11699 size(10);
11700 ins_encode %{
11701 Label* L = $labl$$label;
11702 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
11703 __ restorevectmask();
11704 %}
11705 ins_pipe(pipe_jcc);
11706 %}
11707
11708 // Jump Direct Conditional - using unsigned comparison
11709 instruct jmpConU(cmpOpU cop, rFlagsRegU cmp, label labl) %{
11710 match(If cop cmp);
11711 effect(USE labl);
11712
11713 ins_cost(300);
11714 format %{ "j$cop,u $labl" %}
11715 size(6);
11716 ins_encode %{
11717 Label* L = $labl$$label;
11718 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
11719 %}
11720 ins_pipe(pipe_jcc);
11721 %}
11722
11723 instruct jmpConUCF(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
11724 match(If cop cmp);
11725 effect(USE labl);
11726
11727 ins_cost(200);
11728 format %{ "j$cop,u $labl" %}
11729 size(6);
11730 ins_encode %{
11731 Label* L = $labl$$label;
11732 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
11733 %}
11734 ins_pipe(pipe_jcc);
11735 %}
11736
11737 instruct jmpConUCF2(cmpOpUCF2 cop, rFlagsRegUCF cmp, label labl) %{
11738 match(If cop cmp);
11739 effect(USE labl);
11740
11741 ins_cost(200);
11742 format %{ $$template
11743 if ($cop$$cmpcode == Assembler::notEqual) {
11744 $$emit$$"jp,u $labl\n\t"
11745 $$emit$$"j$cop,u $labl"
11746 } else {
11747 $$emit$$"jp,u done\n\t"
11748 $$emit$$"j$cop,u $labl\n\t"
11749 $$emit$$"done:"
11750 }
11751 %}
11752 ins_encode %{
11753 Label* l = $labl$$label;
11754 if ($cop$$cmpcode == Assembler::notEqual) {
11755 __ jcc(Assembler::parity, *l, false);
11756 __ jcc(Assembler::notEqual, *l, false);
11757 } else if ($cop$$cmpcode == Assembler::equal) {
11758 Label done;
11759 __ jccb(Assembler::parity, done);
11760 __ jcc(Assembler::equal, *l, false);
11761 __ bind(done);
11762 } else {
11763 ShouldNotReachHere();
11764 }
11765 %}
11766 ins_pipe(pipe_jcc);
11767 %}
11768
11769 // ============================================================================
11770 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary
11771 // superklass array for an instance of the superklass. Set a hidden
11772 // internal cache on a hit (cache is checked with exposed code in
11773 // gen_subtype_check()). Return NZ for a miss or zero for a hit. The
11774 // encoding ALSO sets flags.
11775
11776 instruct partialSubtypeCheck(rdi_RegP result,
11777 rsi_RegP sub, rax_RegP super, rcx_RegI rcx,
11778 rFlagsReg cr)
11779 %{
11780 match(Set result (PartialSubtypeCheck sub super));
11781 effect(KILL rcx, KILL cr);
11782
11783 ins_cost(1100); // slightly larger than the next version
11784 format %{ "movq rdi, [$sub + in_bytes(Klass::secondary_supers_offset())]\n\t"
11785 "movl rcx, [rdi + Array<Klass*>::length_offset_in_bytes()]\t# length to scan\n\t"
11786 "addq rdi, Array<Klass*>::base_offset_in_bytes()\t# Skip to start of data; set NZ in case count is zero\n\t"
11787 "repne scasq\t# Scan *rdi++ for a match with rax while rcx--\n\t"
11788 "jne,s miss\t\t# Missed: rdi not-zero\n\t"
11789 "movq [$sub + in_bytes(Klass::secondary_super_cache_offset())], $super\t# Hit: update cache\n\t"
11790 "xorq $result, $result\t\t Hit: rdi zero\n\t"
11791 "miss:\t" %}
11792
11793 opcode(0x1); // Force a XOR of RDI
11794 ins_encode(enc_PartialSubtypeCheck());
11795 ins_pipe(pipe_slow);
11796 %}
11797
11798 instruct partialSubtypeCheck_vs_Zero(rFlagsReg cr,
11799 rsi_RegP sub, rax_RegP super, rcx_RegI rcx,
11800 immP0 zero,
11801 rdi_RegP result)
11802 %{
11803 match(Set cr (CmpP (PartialSubtypeCheck sub super) zero));
11804 effect(KILL rcx, KILL result);
11805
11806 ins_cost(1000);
11807 format %{ "movq rdi, [$sub + in_bytes(Klass::secondary_supers_offset())]\n\t"
11808 "movl rcx, [rdi + Array<Klass*>::length_offset_in_bytes()]\t# length to scan\n\t"
11809 "addq rdi, Array<Klass*>::base_offset_in_bytes()\t# Skip to start of data; set NZ in case count is zero\n\t"
11810 "repne scasq\t# Scan *rdi++ for a match with rax while cx-- != 0\n\t"
11811 "jne,s miss\t\t# Missed: flags nz\n\t"
11812 "movq [$sub + in_bytes(Klass::secondary_super_cache_offset())], $super\t# Hit: update cache\n\t"
11813 "miss:\t" %}
11814
11815 opcode(0x0); // No need to XOR RDI
11816 ins_encode(enc_PartialSubtypeCheck());
11817 ins_pipe(pipe_slow);
11818 %}
11819
11820 // ============================================================================
11821 // Branch Instructions -- short offset versions
11822 //
11823 // These instructions are used to replace jumps of a long offset (the default
11824 // match) with jumps of a shorter offset. These instructions are all tagged
11825 // with the ins_short_branch attribute, which causes the ADLC to suppress the
11826 // match rules in general matching. Instead, the ADLC generates a conversion
11827 // method in the MachNode which can be used to do in-place replacement of the
11828 // long variant with the shorter variant. The compiler will determine if a
11829 // branch can be taken by the is_short_branch_offset() predicate in the machine
11830 // specific code section of the file.
11831
11832 // Jump Direct - Label defines a relative address from JMP+1
11833 instruct jmpDir_short(label labl) %{
11834 match(Goto);
11835 effect(USE labl);
11836
11837 ins_cost(300);
11838 format %{ "jmp,s $labl" %}
11839 size(2);
11840 ins_encode %{
11841 Label* L = $labl$$label;
11842 __ jmpb(*L);
11843 %}
11844 ins_pipe(pipe_jmp);
11845 ins_short_branch(1);
11846 %}
11847
11848 // Jump Direct Conditional - Label defines a relative address from Jcc+1
11849 instruct jmpCon_short(cmpOp cop, rFlagsReg cr, label labl) %{
11850 match(If cop cr);
11851 effect(USE labl);
11852
11853 ins_cost(300);
11854 format %{ "j$cop,s $labl" %}
11855 size(2);
11856 ins_encode %{
11857 Label* L = $labl$$label;
11858 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
11859 %}
11860 ins_pipe(pipe_jcc);
11861 ins_short_branch(1);
11862 %}
11863
11864 // Jump Direct Conditional - Label defines a relative address from Jcc+1
11865 instruct jmpLoopEnd_short(cmpOp cop, rFlagsReg cr, label labl) %{
11866 match(CountedLoopEnd cop cr);
11867 effect(USE labl);
11868
11869 ins_cost(300);
11870 format %{ "j$cop,s $labl\t# loop end" %}
11871 size(2);
11872 ins_encode %{
11873 Label* L = $labl$$label;
11874 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
11875 %}
11876 ins_pipe(pipe_jcc);
11877 ins_short_branch(1);
11878 %}
11879
11880 // Jump Direct Conditional - Label defines a relative address from Jcc+1
11881 instruct jmpLoopEndU_short(cmpOpU cop, rFlagsRegU cmp, label labl) %{
11882 match(CountedLoopEnd cop cmp);
11883 effect(USE labl);
11884
11885 ins_cost(300);
11886 format %{ "j$cop,us $labl\t# loop end" %}
11887 size(2);
11888 ins_encode %{
11889 Label* L = $labl$$label;
11890 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
11891 %}
11892 ins_pipe(pipe_jcc);
11893 ins_short_branch(1);
11894 %}
11895
11896 instruct jmpLoopEndUCF_short(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
11897 match(CountedLoopEnd cop cmp);
11898 effect(USE labl);
11899
11900 ins_cost(300);
11901 format %{ "j$cop,us $labl\t# loop end" %}
11902 size(2);
11903 ins_encode %{
11904 Label* L = $labl$$label;
11905 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
11906 %}
11907 ins_pipe(pipe_jcc);
11908 ins_short_branch(1);
11909 %}
11910
11911 // Jump Direct Conditional - using unsigned comparison
11912 instruct jmpConU_short(cmpOpU cop, rFlagsRegU cmp, label labl) %{
11913 match(If cop cmp);
11914 effect(USE labl);
11915
11916 ins_cost(300);
11917 format %{ "j$cop,us $labl" %}
11918 size(2);
11919 ins_encode %{
11920 Label* L = $labl$$label;
11921 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
11922 %}
11923 ins_pipe(pipe_jcc);
11924 ins_short_branch(1);
11925 %}
11926
11927 instruct jmpConUCF_short(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
11928 match(If cop cmp);
11929 effect(USE labl);
11930
11931 ins_cost(300);
11932 format %{ "j$cop,us $labl" %}
11933 size(2);
11934 ins_encode %{
11935 Label* L = $labl$$label;
11936 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
11937 %}
11938 ins_pipe(pipe_jcc);
11939 ins_short_branch(1);
11940 %}
11941
11942 instruct jmpConUCF2_short(cmpOpUCF2 cop, rFlagsRegUCF cmp, label labl) %{
11943 match(If cop cmp);
11944 effect(USE labl);
11945
11946 ins_cost(300);
11947 format %{ $$template
11948 if ($cop$$cmpcode == Assembler::notEqual) {
11949 $$emit$$"jp,u,s $labl\n\t"
11950 $$emit$$"j$cop,u,s $labl"
11951 } else {
11952 $$emit$$"jp,u,s done\n\t"
11953 $$emit$$"j$cop,u,s $labl\n\t"
11954 $$emit$$"done:"
11955 }
11956 %}
11957 size(4);
11958 ins_encode %{
11959 Label* l = $labl$$label;
11960 if ($cop$$cmpcode == Assembler::notEqual) {
11961 __ jccb(Assembler::parity, *l);
11962 __ jccb(Assembler::notEqual, *l);
11963 } else if ($cop$$cmpcode == Assembler::equal) {
11964 Label done;
11965 __ jccb(Assembler::parity, done);
11966 __ jccb(Assembler::equal, *l);
11967 __ bind(done);
11968 } else {
11969 ShouldNotReachHere();
11970 }
11971 %}
11972 ins_pipe(pipe_jcc);
11973 ins_short_branch(1);
11974 %}
11975
11976 // ============================================================================
11977 // inlined locking and unlocking
11978
11979 instruct cmpFastLockRTM(rFlagsReg cr, rRegP object, rbx_RegP box, rax_RegI tmp, rdx_RegI scr, rRegI cx1, rRegI cx2) %{
11980 predicate(Compile::current()->use_rtm());
11981 match(Set cr (FastLock object box));
11982 effect(TEMP tmp, TEMP scr, TEMP cx1, TEMP cx2, USE_KILL box);
11983 ins_cost(300);
11984 format %{ "fastlock $object,$box\t! kills $box,$tmp,$scr,$cx1,$cx2" %}
11985 ins_encode %{
11986 __ fast_lock($object$$Register, $box$$Register, $tmp$$Register,
11987 $scr$$Register, $cx1$$Register, $cx2$$Register,
11988 _counters, _rtm_counters, _stack_rtm_counters,
11989 ((Method*)(ra_->C->method()->constant_encoding()))->method_data(),
11990 true, ra_->C->profile_rtm());
11991 %}
11992 ins_pipe(pipe_slow);
11993 %}
11994
11995 instruct cmpFastLock(rFlagsReg cr, rRegP object, rbx_RegP box, rax_RegI tmp, rRegP scr) %{
11996 predicate(!Compile::current()->use_rtm());
11997 match(Set cr (FastLock object box));
11998 effect(TEMP tmp, TEMP scr, USE_KILL box);
11999 ins_cost(300);
12000 format %{ "fastlock $object,$box\t! kills $box,$tmp,$scr" %}
12001 ins_encode %{
12002 __ fast_lock($object$$Register, $box$$Register, $tmp$$Register,
12003 $scr$$Register, noreg, noreg, _counters, NULL, NULL, NULL, false, false);
12004 %}
12005 ins_pipe(pipe_slow);
12006 %}
12007
12008 instruct cmpFastUnlock(rFlagsReg cr, rRegP object, rax_RegP box, rRegP tmp) %{
12009 match(Set cr (FastUnlock object box));
12010 effect(TEMP tmp, USE_KILL box);
12011 ins_cost(300);
12012 format %{ "fastunlock $object,$box\t! kills $box,$tmp" %}
12013 ins_encode %{
12014 __ fast_unlock($object$$Register, $box$$Register, $tmp$$Register, ra_->C->use_rtm());
12015 %}
12016 ins_pipe(pipe_slow);
12017 %}
12018
12019
12020 // ============================================================================
12021 // Safepoint Instructions
12022 instruct safePoint_poll(rFlagsReg cr)
12023 %{
12024 predicate(!Assembler::is_polling_page_far());
12025 match(SafePoint);
12026 effect(KILL cr);
12027
12028 format %{ "testl rax, [rip + #offset_to_poll_page]\t"
12029 "# Safepoint: poll for GC" %}
12030 ins_cost(125);
12031 ins_encode %{
12032 AddressLiteral addr(os::get_polling_page(), relocInfo::poll_type);
12033 __ testl(rax, addr);
12034 %}
12035 ins_pipe(ialu_reg_mem);
12036 %}
12037
12038 instruct safePoint_poll_far(rFlagsReg cr, rRegP poll)
12039 %{
12040 predicate(Assembler::is_polling_page_far());
12041 match(SafePoint poll);
12042 effect(KILL cr, USE poll);
12043
12044 format %{ "testl rax, [$poll]\t"
12045 "# Safepoint: poll for GC" %}
12046 ins_cost(125);
12047 ins_encode %{
12048 __ relocate(relocInfo::poll_type);
12049 __ testl(rax, Address($poll$$Register, 0));
12050 %}
12051 ins_pipe(ialu_reg_mem);
12052 %}
12053
12054 // ============================================================================
12055 // Procedure Call/Return Instructions
12056 // Call Java Static Instruction
12057 // Note: If this code changes, the corresponding ret_addr_offset() and
12058 // compute_padding() functions will have to be adjusted.
12059 instruct CallStaticJavaDirect(method meth) %{
12060 match(CallStaticJava);
12061 effect(USE meth);
12062
12063 ins_cost(300);
12064 format %{ "call,static " %}
12065 opcode(0xE8); /* E8 cd */
12066 ins_encode(clear_avx, Java_Static_Call(meth), call_epilog);
12067 ins_pipe(pipe_slow);
12068 ins_alignment(4);
12069 %}
12070
12071 // Call Java Dynamic Instruction
12072 // Note: If this code changes, the corresponding ret_addr_offset() and
12073 // compute_padding() functions will have to be adjusted.
12074 instruct CallDynamicJavaDirect(method meth)
12075 %{
12076 match(CallDynamicJava);
12077 effect(USE meth);
12078
12079 ins_cost(300);
12080 format %{ "movq rax, #Universe::non_oop_word()\n\t"
12081 "call,dynamic " %}
12082 ins_encode(clear_avx, Java_Dynamic_Call(meth), call_epilog);
12083 ins_pipe(pipe_slow);
12084 ins_alignment(4);
12085 %}
12086
12087 // Call Runtime Instruction
12088 instruct CallRuntimeDirect(method meth)
12089 %{
12090 match(CallRuntime);
12091 effect(USE meth);
12092
12093 ins_cost(300);
12094 format %{ "call,runtime " %}
12095 ins_encode(clear_avx, Java_To_Runtime(meth));
12096 ins_pipe(pipe_slow);
12097 %}
12098
12099 // Call runtime without safepoint
12100 instruct CallLeafDirect(method meth)
12101 %{
12102 match(CallLeaf);
12103 effect(USE meth);
12104
12105 ins_cost(300);
12106 format %{ "call_leaf,runtime " %}
12107 ins_encode(clear_avx, Java_To_Runtime(meth));
12108 ins_pipe(pipe_slow);
12109 %}
12110
12111 // Call runtime without safepoint
12112 instruct CallLeafNoFPDirect(method meth)
12113 %{
12114 match(CallLeafNoFP);
12115 effect(USE meth);
12116
12117 ins_cost(300);
12118 format %{ "call_leaf_nofp,runtime " %}
12119 ins_encode(Java_To_Runtime(meth));
12120 ins_pipe(pipe_slow);
12121 %}
12122
12123 // Return Instruction
12124 // Remove the return address & jump to it.
12125 // Notice: We always emit a nop after a ret to make sure there is room
12126 // for safepoint patching
12127 instruct Ret()
12128 %{
12129 match(Return);
12130
12131 format %{ "ret" %}
12132 opcode(0xC3);
12133 ins_encode(OpcP);
12134 ins_pipe(pipe_jmp);
12135 %}
12136
12137 // Tail Call; Jump from runtime stub to Java code.
12138 // Also known as an 'interprocedural jump'.
12139 // Target of jump will eventually return to caller.
12140 // TailJump below removes the return address.
12141 instruct TailCalljmpInd(no_rbp_RegP jump_target, rbx_RegP method_oop)
12142 %{
12143 match(TailCall jump_target method_oop);
12144
12145 ins_cost(300);
12146 format %{ "jmp $jump_target\t# rbx holds method oop" %}
12147 opcode(0xFF, 0x4); /* Opcode FF /4 */
12148 ins_encode(REX_reg(jump_target), OpcP, reg_opc(jump_target));
12149 ins_pipe(pipe_jmp);
12150 %}
12151
12152 // Tail Jump; remove the return address; jump to target.
12153 // TailCall above leaves the return address around.
12154 instruct tailjmpInd(no_rbp_RegP jump_target, rax_RegP ex_oop)
12155 %{
12156 match(TailJump jump_target ex_oop);
12157
12158 ins_cost(300);
12159 format %{ "popq rdx\t# pop return address\n\t"
12160 "jmp $jump_target" %}
12161 opcode(0xFF, 0x4); /* Opcode FF /4 */
12162 ins_encode(Opcode(0x5a), // popq rdx
12163 REX_reg(jump_target), OpcP, reg_opc(jump_target));
12164 ins_pipe(pipe_jmp);
12165 %}
12166
12167 // Create exception oop: created by stack-crawling runtime code.
12168 // Created exception is now available to this handler, and is setup
12169 // just prior to jumping to this handler. No code emitted.
12170 instruct CreateException(rax_RegP ex_oop)
12171 %{
12172 match(Set ex_oop (CreateEx));
12173
12174 size(0);
12175 // use the following format syntax
12176 format %{ "# exception oop is in rax; no code emitted" %}
12177 ins_encode();
12178 ins_pipe(empty);
12179 %}
12180
12181 // Rethrow exception:
12182 // The exception oop will come in the first argument position.
12183 // Then JUMP (not call) to the rethrow stub code.
12184 instruct RethrowException()
12185 %{
12186 match(Rethrow);
12187
12188 // use the following format syntax
12189 format %{ "jmp rethrow_stub" %}
12190 ins_encode(enc_rethrow);
12191 ins_pipe(pipe_jmp);
12192 %}
12193
12194
12195 // ============================================================================
12196 // This name is KNOWN by the ADLC and cannot be changed.
12197 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
12198 // for this guy.
12199 instruct tlsLoadP(r15_RegP dst) %{
12200 match(Set dst (ThreadLocal));
12201 effect(DEF dst);
12202
12203 size(0);
12204 format %{ "# TLS is in R15" %}
12205 ins_encode( /*empty encoding*/ );
12206 ins_pipe(ialu_reg_reg);
12207 %}
12208
12209
12210 //----------PEEPHOLE RULES-----------------------------------------------------
12211 // These must follow all instruction definitions as they use the names
12212 // defined in the instructions definitions.
12213 //
12214 // peepmatch ( root_instr_name [preceding_instruction]* );
12215 //
12216 // peepconstraint %{
12217 // (instruction_number.operand_name relational_op instruction_number.operand_name
12218 // [, ...] );
12219 // // instruction numbers are zero-based using left to right order in peepmatch
12220 //
12221 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
12222 // // provide an instruction_number.operand_name for each operand that appears
12223 // // in the replacement instruction's match rule
12224 //
12225 // ---------VM FLAGS---------------------------------------------------------
12226 //
12227 // All peephole optimizations can be turned off using -XX:-OptoPeephole
12228 //
12229 // Each peephole rule is given an identifying number starting with zero and
12230 // increasing by one in the order seen by the parser. An individual peephole
12231 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
12232 // on the command-line.
12233 //
12234 // ---------CURRENT LIMITATIONS----------------------------------------------
12235 //
12236 // Only match adjacent instructions in same basic block
12237 // Only equality constraints
12238 // Only constraints between operands, not (0.dest_reg == RAX_enc)
12239 // Only one replacement instruction
12240 //
12241 // ---------EXAMPLE----------------------------------------------------------
12242 //
12243 // // pertinent parts of existing instructions in architecture description
12244 // instruct movI(rRegI dst, rRegI src)
12245 // %{
12246 // match(Set dst (CopyI src));
12247 // %}
12248 //
12249 // instruct incI_rReg(rRegI dst, immI1 src, rFlagsReg cr)
12250 // %{
12251 // match(Set dst (AddI dst src));
12252 // effect(KILL cr);
12253 // %}
12254 //
12255 // // Change (inc mov) to lea
12256 // peephole %{
12257 // // increment preceeded by register-register move
12258 // peepmatch ( incI_rReg movI );
12259 // // require that the destination register of the increment
12260 // // match the destination register of the move
12261 // peepconstraint ( 0.dst == 1.dst );
12262 // // construct a replacement instruction that sets
12263 // // the destination to ( move's source register + one )
12264 // peepreplace ( leaI_rReg_immI( 0.dst 1.src 0.src ) );
12265 // %}
12266 //
12267
12268 // Implementation no longer uses movX instructions since
12269 // machine-independent system no longer uses CopyX nodes.
12270 //
12271 // peephole
12272 // %{
12273 // peepmatch (incI_rReg movI);
12274 // peepconstraint (0.dst == 1.dst);
12275 // peepreplace (leaI_rReg_immI(0.dst 1.src 0.src));
12276 // %}
12277
12278 // peephole
12279 // %{
12280 // peepmatch (decI_rReg movI);
12281 // peepconstraint (0.dst == 1.dst);
12282 // peepreplace (leaI_rReg_immI(0.dst 1.src 0.src));
12283 // %}
12284
12285 // peephole
12286 // %{
12287 // peepmatch (addI_rReg_imm movI);
12288 // peepconstraint (0.dst == 1.dst);
12289 // peepreplace (leaI_rReg_immI(0.dst 1.src 0.src));
12290 // %}
12291
12292 // peephole
12293 // %{
12294 // peepmatch (incL_rReg movL);
12295 // peepconstraint (0.dst == 1.dst);
12296 // peepreplace (leaL_rReg_immL(0.dst 1.src 0.src));
12297 // %}
12298
12299 // peephole
12300 // %{
12301 // peepmatch (decL_rReg movL);
12302 // peepconstraint (0.dst == 1.dst);
12303 // peepreplace (leaL_rReg_immL(0.dst 1.src 0.src));
12304 // %}
12305
12306 // peephole
12307 // %{
12308 // peepmatch (addL_rReg_imm movL);
12309 // peepconstraint (0.dst == 1.dst);
12310 // peepreplace (leaL_rReg_immL(0.dst 1.src 0.src));
12311 // %}
12312
12313 // peephole
12314 // %{
12315 // peepmatch (addP_rReg_imm movP);
12316 // peepconstraint (0.dst == 1.dst);
12317 // peepreplace (leaP_rReg_imm(0.dst 1.src 0.src));
12318 // %}
12319
12320 // // Change load of spilled value to only a spill
12321 // instruct storeI(memory mem, rRegI src)
12322 // %{
12323 // match(Set mem (StoreI mem src));
12324 // %}
12325 //
12326 // instruct loadI(rRegI dst, memory mem)
12327 // %{
12328 // match(Set dst (LoadI mem));
12329 // %}
12330 //
12331
12332 peephole
12333 %{
12334 peepmatch (loadI storeI);
12335 peepconstraint (1.src == 0.dst, 1.mem == 0.mem);
12336 peepreplace (storeI(1.mem 1.mem 1.src));
12337 %}
12338
12339 peephole
12340 %{
12341 peepmatch (loadL storeL);
12342 peepconstraint (1.src == 0.dst, 1.mem == 0.mem);
12343 peepreplace (storeL(1.mem 1.mem 1.src));
12344 %}
12345
12346 //----------SMARTSPILL RULES---------------------------------------------------
12347 // These must follow all instruction definitions as they use the names
12348 // defined in the instructions definitions.