2794   assert(tmp->is_illegal(), "wasting a register if tmp is allocated");
2795 
2796   if (left->is_single_cpu()) {
2797     assert(dest->is_single_cpu(), "expect single result reg");
2798     __ negw(dest->as_register(), left->as_register());
2799   } else if (left->is_double_cpu()) {
2800     assert(dest->is_double_cpu(), "expect double result reg");
2801     __ neg(dest->as_register_lo(), left->as_register_lo());
2802   } else if (left->is_single_fpu()) {
2803     assert(dest->is_single_fpu(), "expect single float result reg");
2804     __ fnegs(dest->as_float_reg(), left->as_float_reg());
2805   } else {
2806     assert(left->is_double_fpu(), "expect double float operand reg");
2807     assert(dest->is_double_fpu(), "expect double float result reg");
2808     __ fnegd(dest->as_double_reg(), left->as_double_reg());
2809   }
2810 }
2811 
2812 
2813 void LIR_Assembler::leal(LIR_Opr addr, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
2814   assert(patch_code == lir_patch_none, "Patch code not supported");




2815   __ lea(dest->as_register_lo(), as_Address(addr->as_address_ptr()));
2816 }
2817 
2818 
2819 void LIR_Assembler::rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
2820   assert(!tmp->is_valid(), "don't need temporary");
2821 
2822   CodeBlob *cb = CodeCache::find_blob(dest);
2823   if (cb) {
2824     __ far_call(RuntimeAddress(dest));
2825   } else {
2826     __ mov(rscratch1, RuntimeAddress(dest));
2827     __ blr(rscratch1);
2828   }
2829 
2830   if (info != NULL) {
2831     add_call_info_here(info);
2832   }
2833   __ maybe_isb();
2834 }

2794   assert(tmp->is_illegal(), "wasting a register if tmp is allocated");
2795 
2796   if (left->is_single_cpu()) {
2797     assert(dest->is_single_cpu(), "expect single result reg");
2798     __ negw(dest->as_register(), left->as_register());
2799   } else if (left->is_double_cpu()) {
2800     assert(dest->is_double_cpu(), "expect double result reg");
2801     __ neg(dest->as_register_lo(), left->as_register_lo());
2802   } else if (left->is_single_fpu()) {
2803     assert(dest->is_single_fpu(), "expect single float result reg");
2804     __ fnegs(dest->as_float_reg(), left->as_float_reg());
2805   } else {
2806     assert(left->is_double_fpu(), "expect double float operand reg");
2807     assert(dest->is_double_fpu(), "expect double float result reg");
2808     __ fnegd(dest->as_double_reg(), left->as_double_reg());
2809   }
2810 }
2811 
2812 
2813 void LIR_Assembler::leal(LIR_Opr addr, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
2814   if (patch_code != lir_patch_none) {
2815     deoptimize_trap(info);
2816     return;
2817   }
2818 
2819   __ lea(dest->as_register_lo(), as_Address(addr->as_address_ptr()));
2820 }
2821 
2822 
2823 void LIR_Assembler::rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
2824   assert(!tmp->is_valid(), "don't need temporary");
2825 
2826   CodeBlob *cb = CodeCache::find_blob(dest);
2827   if (cb) {
2828     __ far_call(RuntimeAddress(dest));
2829   } else {
2830     __ mov(rscratch1, RuntimeAddress(dest));
2831     __ blr(rscratch1);
2832   }
2833 
2834   if (info != NULL) {
2835     add_call_info_here(info);
2836   }
2837   __ maybe_isb();
2838 }