1 /*
2 * Copyright (c) 1997, 2017, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "memory/allocation.inline.hpp"
27 #include "memory/resourceArea.hpp"
28 #include "opto/ad.hpp"
29 #include "opto/addnode.hpp"
30 #include "opto/callnode.hpp"
31 #include "opto/idealGraphPrinter.hpp"
32 #include "opto/matcher.hpp"
33 #include "opto/memnode.hpp"
34 #include "opto/movenode.hpp"
35 #include "opto/opcodes.hpp"
36 #include "opto/regmask.hpp"
37 #include "opto/rootnode.hpp"
38 #include "opto/runtime.hpp"
39 #include "opto/type.hpp"
40 #include "opto/vectornode.hpp"
41 #include "runtime/os.hpp"
42 #include "runtime/sharedRuntime.hpp"
43 #include "utilities/align.hpp"
44 #if INCLUDE_ZGC
45 #include "gc/z/zBarrierSetRuntime.hpp"
46 #endif // INCLUDE_ZGC
47
48 OptoReg::Name OptoReg::c_frame_pointer;
49
50 const RegMask *Matcher::idealreg2regmask[_last_machine_leaf];
51 RegMask Matcher::mreg2regmask[_last_Mach_Reg];
52 RegMask Matcher::STACK_ONLY_mask;
53 RegMask Matcher::c_frame_ptr_mask;
54 const uint Matcher::_begin_rematerialize = _BEGIN_REMATERIALIZE;
55 const uint Matcher::_end_rematerialize = _END_REMATERIALIZE;
56
57 //---------------------------Matcher-------------------------------------------
58 Matcher::Matcher()
59 : PhaseTransform( Phase::Ins_Select ),
60 #ifdef ASSERT
61 _old2new_map(C->comp_arena()),
62 _new2old_map(C->comp_arena()),
63 #endif
64 _shared_nodes(C->comp_arena()),
65 _reduceOp(reduceOp), _leftOp(leftOp), _rightOp(rightOp),
66 _swallowed(swallowed),
67 _begin_inst_chain_rule(_BEGIN_INST_CHAIN_RULE),
68 _end_inst_chain_rule(_END_INST_CHAIN_RULE),
69 _must_clone(must_clone),
70 _register_save_policy(register_save_policy),
71 _c_reg_save_policy(c_reg_save_policy),
72 _register_save_type(register_save_type),
73 _ruleName(ruleName),
74 _allocation_started(false),
75 _states_arena(Chunk::medium_size, mtCompiler),
76 _visited(&_states_arena),
77 _shared(&_states_arena),
78 _dontcare(&_states_arena) {
79 C->set_matcher(this);
80
81 idealreg2spillmask [Op_RegI] = NULL;
82 idealreg2spillmask [Op_RegN] = NULL;
83 idealreg2spillmask [Op_RegL] = NULL;
84 idealreg2spillmask [Op_RegF] = NULL;
85 idealreg2spillmask [Op_RegD] = NULL;
86 idealreg2spillmask [Op_RegP] = NULL;
87 idealreg2spillmask [Op_VecS] = NULL;
88 idealreg2spillmask [Op_VecD] = NULL;
89 idealreg2spillmask [Op_VecX] = NULL;
90 idealreg2spillmask [Op_VecY] = NULL;
91 idealreg2spillmask [Op_VecZ] = NULL;
92 idealreg2spillmask [Op_RegFlags] = NULL;
93
94 idealreg2debugmask [Op_RegI] = NULL;
95 idealreg2debugmask [Op_RegN] = NULL;
96 idealreg2debugmask [Op_RegL] = NULL;
97 idealreg2debugmask [Op_RegF] = NULL;
98 idealreg2debugmask [Op_RegD] = NULL;
99 idealreg2debugmask [Op_RegP] = NULL;
100 idealreg2debugmask [Op_VecS] = NULL;
101 idealreg2debugmask [Op_VecD] = NULL;
102 idealreg2debugmask [Op_VecX] = NULL;
103 idealreg2debugmask [Op_VecY] = NULL;
104 idealreg2debugmask [Op_VecZ] = NULL;
105 idealreg2debugmask [Op_RegFlags] = NULL;
106
107 idealreg2mhdebugmask[Op_RegI] = NULL;
108 idealreg2mhdebugmask[Op_RegN] = NULL;
109 idealreg2mhdebugmask[Op_RegL] = NULL;
110 idealreg2mhdebugmask[Op_RegF] = NULL;
111 idealreg2mhdebugmask[Op_RegD] = NULL;
112 idealreg2mhdebugmask[Op_RegP] = NULL;
113 idealreg2mhdebugmask[Op_VecS] = NULL;
114 idealreg2mhdebugmask[Op_VecD] = NULL;
115 idealreg2mhdebugmask[Op_VecX] = NULL;
116 idealreg2mhdebugmask[Op_VecY] = NULL;
117 idealreg2mhdebugmask[Op_VecZ] = NULL;
118 idealreg2mhdebugmask[Op_RegFlags] = NULL;
119
120 debug_only(_mem_node = NULL;) // Ideal memory node consumed by mach node
121 }
122
123 //------------------------------warp_incoming_stk_arg------------------------
124 // This warps a VMReg into an OptoReg::Name
125 OptoReg::Name Matcher::warp_incoming_stk_arg( VMReg reg ) {
126 OptoReg::Name warped;
127 if( reg->is_stack() ) { // Stack slot argument?
128 warped = OptoReg::add(_old_SP, reg->reg2stack() );
129 warped = OptoReg::add(warped, C->out_preserve_stack_slots());
130 if( warped >= _in_arg_limit )
131 _in_arg_limit = OptoReg::add(warped, 1); // Bump max stack slot seen
132 if (!RegMask::can_represent_arg(warped)) {
133 // the compiler cannot represent this method's calling sequence
134 C->record_method_not_compilable("unsupported incoming calling sequence");
135 return OptoReg::Bad;
136 }
137 return warped;
138 }
139 return OptoReg::as_OptoReg(reg);
140 }
141
142 //---------------------------compute_old_SP------------------------------------
143 OptoReg::Name Compile::compute_old_SP() {
144 int fixed = fixed_slots();
145 int preserve = in_preserve_stack_slots();
146 return OptoReg::stack2reg(align_up(fixed + preserve, (int)Matcher::stack_alignment_in_slots()));
147 }
148
149
150
151 #ifdef ASSERT
152 void Matcher::verify_new_nodes_only(Node* xroot) {
153 // Make sure that the new graph only references new nodes
154 ResourceMark rm;
155 Unique_Node_List worklist;
156 VectorSet visited(Thread::current()->resource_area());
157 worklist.push(xroot);
158 while (worklist.size() > 0) {
159 Node* n = worklist.pop();
160 visited <<= n->_idx;
161 assert(C->node_arena()->contains(n), "dead node");
162 for (uint j = 0; j < n->req(); j++) {
163 Node* in = n->in(j);
164 if (in != NULL) {
165 assert(C->node_arena()->contains(in), "dead node");
166 if (!visited.test(in->_idx)) {
167 worklist.push(in);
168 }
169 }
170 }
171 }
172 }
173 #endif
174
175
176 //---------------------------match---------------------------------------------
177 void Matcher::match( ) {
178 if( MaxLabelRootDepth < 100 ) { // Too small?
179 assert(false, "invalid MaxLabelRootDepth, increase it to 100 minimum");
180 MaxLabelRootDepth = 100;
181 }
182 // One-time initialization of some register masks.
183 init_spill_mask( C->root()->in(1) );
184 _return_addr_mask = return_addr();
185 #ifdef _LP64
186 // Pointers take 2 slots in 64-bit land
187 _return_addr_mask.Insert(OptoReg::add(return_addr(),1));
188 #endif
189
190 // Map a Java-signature return type into return register-value
191 // machine registers for 0, 1 and 2 returned values.
192 const TypeTuple *range = C->tf()->range();
193 if( range->cnt() > TypeFunc::Parms ) { // If not a void function
194 // Get ideal-register return type
195 uint ireg = range->field_at(TypeFunc::Parms)->ideal_reg();
196 // Get machine return register
197 uint sop = C->start()->Opcode();
198 OptoRegPair regs = return_value(ireg, false);
199
200 // And mask for same
201 _return_value_mask = RegMask(regs.first());
202 if( OptoReg::is_valid(regs.second()) )
203 _return_value_mask.Insert(regs.second());
204 }
205
206 // ---------------
207 // Frame Layout
208
209 // Need the method signature to determine the incoming argument types,
210 // because the types determine which registers the incoming arguments are
211 // in, and this affects the matched code.
212 const TypeTuple *domain = C->tf()->domain();
213 uint argcnt = domain->cnt() - TypeFunc::Parms;
214 BasicType *sig_bt = NEW_RESOURCE_ARRAY( BasicType, argcnt );
215 VMRegPair *vm_parm_regs = NEW_RESOURCE_ARRAY( VMRegPair, argcnt );
216 _parm_regs = NEW_RESOURCE_ARRAY( OptoRegPair, argcnt );
217 _calling_convention_mask = NEW_RESOURCE_ARRAY( RegMask, argcnt );
218 uint i;
219 for( i = 0; i<argcnt; i++ ) {
220 sig_bt[i] = domain->field_at(i+TypeFunc::Parms)->basic_type();
221 }
222
223 // Pass array of ideal registers and length to USER code (from the AD file)
224 // that will convert this to an array of register numbers.
225 const StartNode *start = C->start();
226 start->calling_convention( sig_bt, vm_parm_regs, argcnt );
227 #ifdef ASSERT
228 // Sanity check users' calling convention. Real handy while trying to
229 // get the initial port correct.
230 { for (uint i = 0; i<argcnt; i++) {
231 if( !vm_parm_regs[i].first()->is_valid() && !vm_parm_regs[i].second()->is_valid() ) {
232 assert(domain->field_at(i+TypeFunc::Parms)==Type::HALF, "only allowed on halve" );
233 _parm_regs[i].set_bad();
234 continue;
235 }
236 VMReg parm_reg = vm_parm_regs[i].first();
237 assert(parm_reg->is_valid(), "invalid arg?");
238 if (parm_reg->is_reg()) {
239 OptoReg::Name opto_parm_reg = OptoReg::as_OptoReg(parm_reg);
240 assert(can_be_java_arg(opto_parm_reg) ||
241 C->stub_function() == CAST_FROM_FN_PTR(address, OptoRuntime::rethrow_C) ||
242 opto_parm_reg == inline_cache_reg(),
243 "parameters in register must be preserved by runtime stubs");
244 }
245 for (uint j = 0; j < i; j++) {
246 assert(parm_reg != vm_parm_regs[j].first(),
247 "calling conv. must produce distinct regs");
248 }
249 }
250 }
251 #endif
252
253 // Do some initial frame layout.
254
255 // Compute the old incoming SP (may be called FP) as
256 // OptoReg::stack0() + locks + in_preserve_stack_slots + pad2.
257 _old_SP = C->compute_old_SP();
258 assert( is_even(_old_SP), "must be even" );
259
260 // Compute highest incoming stack argument as
261 // _old_SP + out_preserve_stack_slots + incoming argument size.
262 _in_arg_limit = OptoReg::add(_old_SP, C->out_preserve_stack_slots());
263 assert( is_even(_in_arg_limit), "out_preserve must be even" );
264 for( i = 0; i < argcnt; i++ ) {
265 // Permit args to have no register
266 _calling_convention_mask[i].Clear();
267 if( !vm_parm_regs[i].first()->is_valid() && !vm_parm_regs[i].second()->is_valid() ) {
268 continue;
269 }
270 // calling_convention returns stack arguments as a count of
271 // slots beyond OptoReg::stack0()/VMRegImpl::stack0. We need to convert this to
272 // the allocators point of view, taking into account all the
273 // preserve area, locks & pad2.
274
275 OptoReg::Name reg1 = warp_incoming_stk_arg(vm_parm_regs[i].first());
276 if( OptoReg::is_valid(reg1))
277 _calling_convention_mask[i].Insert(reg1);
278
279 OptoReg::Name reg2 = warp_incoming_stk_arg(vm_parm_regs[i].second());
280 if( OptoReg::is_valid(reg2))
281 _calling_convention_mask[i].Insert(reg2);
282
283 // Saved biased stack-slot register number
284 _parm_regs[i].set_pair(reg2, reg1);
285 }
286
287 // Finally, make sure the incoming arguments take up an even number of
288 // words, in case the arguments or locals need to contain doubleword stack
289 // slots. The rest of the system assumes that stack slot pairs (in
290 // particular, in the spill area) which look aligned will in fact be
291 // aligned relative to the stack pointer in the target machine. Double
292 // stack slots will always be allocated aligned.
293 _new_SP = OptoReg::Name(align_up(_in_arg_limit, (int)RegMask::SlotsPerLong));
294
295 // Compute highest outgoing stack argument as
296 // _new_SP + out_preserve_stack_slots + max(outgoing argument size).
297 _out_arg_limit = OptoReg::add(_new_SP, C->out_preserve_stack_slots());
298 assert( is_even(_out_arg_limit), "out_preserve must be even" );
299
300 if (!RegMask::can_represent_arg(OptoReg::add(_out_arg_limit,-1))) {
301 // the compiler cannot represent this method's calling sequence
302 C->record_method_not_compilable("must be able to represent all call arguments in reg mask");
303 }
304
305 if (C->failing()) return; // bailed out on incoming arg failure
306
307 // ---------------
308 // Collect roots of matcher trees. Every node for which
309 // _shared[_idx] is cleared is guaranteed to not be shared, and thus
310 // can be a valid interior of some tree.
311 find_shared( C->root() );
312 find_shared( C->top() );
313
314 C->print_method(PHASE_BEFORE_MATCHING);
315
316 // Create new ideal node ConP #NULL even if it does exist in old space
317 // to avoid false sharing if the corresponding mach node is not used.
318 // The corresponding mach node is only used in rare cases for derived
319 // pointers.
320 Node* new_ideal_null = ConNode::make(TypePtr::NULL_PTR);
321
322 // Swap out to old-space; emptying new-space
323 Arena *old = C->node_arena()->move_contents(C->old_arena());
324
325 // Save debug and profile information for nodes in old space:
326 _old_node_note_array = C->node_note_array();
327 if (_old_node_note_array != NULL) {
328 C->set_node_note_array(new(C->comp_arena()) GrowableArray<Node_Notes*>
329 (C->comp_arena(), _old_node_note_array->length(),
330 0, NULL));
331 }
332
333 // Pre-size the new_node table to avoid the need for range checks.
334 grow_new_node_array(C->unique());
335
336 // Reset node counter so MachNodes start with _idx at 0
337 int live_nodes = C->live_nodes();
338 C->set_unique(0);
339 C->reset_dead_node_list();
340
341 // Recursively match trees from old space into new space.
342 // Correct leaves of new-space Nodes; they point to old-space.
343 _visited.Clear(); // Clear visit bits for xform call
344 C->set_cached_top_node(xform( C->top(), live_nodes ));
345 if (!C->failing()) {
346 Node* xroot = xform( C->root(), 1 );
347 if (xroot == NULL) {
348 Matcher::soft_match_failure(); // recursive matching process failed
349 C->record_method_not_compilable("instruction match failed");
350 } else {
351 // During matching shared constants were attached to C->root()
352 // because xroot wasn't available yet, so transfer the uses to
353 // the xroot.
354 for( DUIterator_Fast jmax, j = C->root()->fast_outs(jmax); j < jmax; j++ ) {
355 Node* n = C->root()->fast_out(j);
356 if (C->node_arena()->contains(n)) {
357 assert(n->in(0) == C->root(), "should be control user");
358 n->set_req(0, xroot);
359 --j;
360 --jmax;
361 }
362 }
363
364 // Generate new mach node for ConP #NULL
365 assert(new_ideal_null != NULL, "sanity");
366 _mach_null = match_tree(new_ideal_null);
367 // Don't set control, it will confuse GCM since there are no uses.
368 // The control will be set when this node is used first time
369 // in find_base_for_derived().
370 assert(_mach_null != NULL, "");
371
372 C->set_root(xroot->is_Root() ? xroot->as_Root() : NULL);
373
374 #ifdef ASSERT
375 verify_new_nodes_only(xroot);
376 #endif
377 }
378 }
379 if (C->top() == NULL || C->root() == NULL) {
380 C->record_method_not_compilable("graph lost"); // %%% cannot happen?
381 }
382 if (C->failing()) {
383 // delete old;
384 old->destruct_contents();
385 return;
386 }
387 assert( C->top(), "" );
388 assert( C->root(), "" );
389 validate_null_checks();
390
391 // Now smoke old-space
392 NOT_DEBUG( old->destruct_contents() );
393
394 // ------------------------
395 // Set up save-on-entry registers
396 Fixup_Save_On_Entry( );
397 }
398
399
400 //------------------------------Fixup_Save_On_Entry----------------------------
401 // The stated purpose of this routine is to take care of save-on-entry
402 // registers. However, the overall goal of the Match phase is to convert into
403 // machine-specific instructions which have RegMasks to guide allocation.
404 // So what this procedure really does is put a valid RegMask on each input
405 // to the machine-specific variations of all Return, TailCall and Halt
406 // instructions. It also adds edgs to define the save-on-entry values (and of
407 // course gives them a mask).
408
409 static RegMask *init_input_masks( uint size, RegMask &ret_adr, RegMask &fp ) {
410 RegMask *rms = NEW_RESOURCE_ARRAY( RegMask, size );
411 // Do all the pre-defined register masks
412 rms[TypeFunc::Control ] = RegMask::Empty;
413 rms[TypeFunc::I_O ] = RegMask::Empty;
414 rms[TypeFunc::Memory ] = RegMask::Empty;
415 rms[TypeFunc::ReturnAdr] = ret_adr;
416 rms[TypeFunc::FramePtr ] = fp;
417 return rms;
418 }
419
420 //---------------------------init_first_stack_mask-----------------------------
421 // Create the initial stack mask used by values spilling to the stack.
422 // Disallow any debug info in outgoing argument areas by setting the
423 // initial mask accordingly.
424 void Matcher::init_first_stack_mask() {
425
426 // Allocate storage for spill masks as masks for the appropriate load type.
427 RegMask *rms = (RegMask*)C->comp_arena()->Amalloc_D(sizeof(RegMask) * (3*6+5));
428
429 idealreg2spillmask [Op_RegN] = &rms[0];
430 idealreg2spillmask [Op_RegI] = &rms[1];
431 idealreg2spillmask [Op_RegL] = &rms[2];
432 idealreg2spillmask [Op_RegF] = &rms[3];
433 idealreg2spillmask [Op_RegD] = &rms[4];
434 idealreg2spillmask [Op_RegP] = &rms[5];
435
436 idealreg2debugmask [Op_RegN] = &rms[6];
437 idealreg2debugmask [Op_RegI] = &rms[7];
438 idealreg2debugmask [Op_RegL] = &rms[8];
439 idealreg2debugmask [Op_RegF] = &rms[9];
440 idealreg2debugmask [Op_RegD] = &rms[10];
441 idealreg2debugmask [Op_RegP] = &rms[11];
442
443 idealreg2mhdebugmask[Op_RegN] = &rms[12];
444 idealreg2mhdebugmask[Op_RegI] = &rms[13];
445 idealreg2mhdebugmask[Op_RegL] = &rms[14];
446 idealreg2mhdebugmask[Op_RegF] = &rms[15];
447 idealreg2mhdebugmask[Op_RegD] = &rms[16];
448 idealreg2mhdebugmask[Op_RegP] = &rms[17];
449
450 idealreg2spillmask [Op_VecS] = &rms[18];
451 idealreg2spillmask [Op_VecD] = &rms[19];
452 idealreg2spillmask [Op_VecX] = &rms[20];
453 idealreg2spillmask [Op_VecY] = &rms[21];
454 idealreg2spillmask [Op_VecZ] = &rms[22];
455
456 OptoReg::Name i;
457
458 // At first, start with the empty mask
459 C->FIRST_STACK_mask().Clear();
460
461 // Add in the incoming argument area
462 OptoReg::Name init_in = OptoReg::add(_old_SP, C->out_preserve_stack_slots());
463 for (i = init_in; i < _in_arg_limit; i = OptoReg::add(i,1)) {
464 C->FIRST_STACK_mask().Insert(i);
465 }
466 // Add in all bits past the outgoing argument area
467 guarantee(RegMask::can_represent_arg(OptoReg::add(_out_arg_limit,-1)),
468 "must be able to represent all call arguments in reg mask");
469 OptoReg::Name init = _out_arg_limit;
470 for (i = init; RegMask::can_represent(i); i = OptoReg::add(i,1)) {
471 C->FIRST_STACK_mask().Insert(i);
472 }
473 // Finally, set the "infinite stack" bit.
474 C->FIRST_STACK_mask().set_AllStack();
475
476 // Make spill masks. Registers for their class, plus FIRST_STACK_mask.
477 RegMask aligned_stack_mask = C->FIRST_STACK_mask();
478 // Keep spill masks aligned.
479 aligned_stack_mask.clear_to_pairs();
480 assert(aligned_stack_mask.is_AllStack(), "should be infinite stack");
481
482 *idealreg2spillmask[Op_RegP] = *idealreg2regmask[Op_RegP];
483 #ifdef _LP64
484 *idealreg2spillmask[Op_RegN] = *idealreg2regmask[Op_RegN];
485 idealreg2spillmask[Op_RegN]->OR(C->FIRST_STACK_mask());
486 idealreg2spillmask[Op_RegP]->OR(aligned_stack_mask);
487 #else
488 idealreg2spillmask[Op_RegP]->OR(C->FIRST_STACK_mask());
489 #endif
490 *idealreg2spillmask[Op_RegI] = *idealreg2regmask[Op_RegI];
491 idealreg2spillmask[Op_RegI]->OR(C->FIRST_STACK_mask());
492 *idealreg2spillmask[Op_RegL] = *idealreg2regmask[Op_RegL];
493 idealreg2spillmask[Op_RegL]->OR(aligned_stack_mask);
494 *idealreg2spillmask[Op_RegF] = *idealreg2regmask[Op_RegF];
495 idealreg2spillmask[Op_RegF]->OR(C->FIRST_STACK_mask());
496 *idealreg2spillmask[Op_RegD] = *idealreg2regmask[Op_RegD];
497 idealreg2spillmask[Op_RegD]->OR(aligned_stack_mask);
498
499 if (Matcher::vector_size_supported(T_BYTE,4)) {
500 *idealreg2spillmask[Op_VecS] = *idealreg2regmask[Op_VecS];
501 idealreg2spillmask[Op_VecS]->OR(C->FIRST_STACK_mask());
502 }
503 if (Matcher::vector_size_supported(T_FLOAT,2)) {
504 // For VecD we need dual alignment and 8 bytes (2 slots) for spills.
505 // RA guarantees such alignment since it is needed for Double and Long values.
506 *idealreg2spillmask[Op_VecD] = *idealreg2regmask[Op_VecD];
507 idealreg2spillmask[Op_VecD]->OR(aligned_stack_mask);
508 }
509 if (Matcher::vector_size_supported(T_FLOAT,4)) {
510 // For VecX we need quadro alignment and 16 bytes (4 slots) for spills.
511 //
512 // RA can use input arguments stack slots for spills but until RA
513 // we don't know frame size and offset of input arg stack slots.
514 //
515 // Exclude last input arg stack slots to avoid spilling vectors there
516 // otherwise vector spills could stomp over stack slots in caller frame.
517 OptoReg::Name in = OptoReg::add(_in_arg_limit, -1);
518 for (int k = 1; (in >= init_in) && (k < RegMask::SlotsPerVecX); k++) {
519 aligned_stack_mask.Remove(in);
520 in = OptoReg::add(in, -1);
521 }
522 aligned_stack_mask.clear_to_sets(RegMask::SlotsPerVecX);
523 assert(aligned_stack_mask.is_AllStack(), "should be infinite stack");
524 *idealreg2spillmask[Op_VecX] = *idealreg2regmask[Op_VecX];
525 idealreg2spillmask[Op_VecX]->OR(aligned_stack_mask);
526 }
527 if (Matcher::vector_size_supported(T_FLOAT,8)) {
528 // For VecY we need octo alignment and 32 bytes (8 slots) for spills.
529 OptoReg::Name in = OptoReg::add(_in_arg_limit, -1);
530 for (int k = 1; (in >= init_in) && (k < RegMask::SlotsPerVecY); k++) {
531 aligned_stack_mask.Remove(in);
532 in = OptoReg::add(in, -1);
533 }
534 aligned_stack_mask.clear_to_sets(RegMask::SlotsPerVecY);
535 assert(aligned_stack_mask.is_AllStack(), "should be infinite stack");
536 *idealreg2spillmask[Op_VecY] = *idealreg2regmask[Op_VecY];
537 idealreg2spillmask[Op_VecY]->OR(aligned_stack_mask);
538 }
539 if (Matcher::vector_size_supported(T_FLOAT,16)) {
540 // For VecZ we need enough alignment and 64 bytes (16 slots) for spills.
541 OptoReg::Name in = OptoReg::add(_in_arg_limit, -1);
542 for (int k = 1; (in >= init_in) && (k < RegMask::SlotsPerVecZ); k++) {
543 aligned_stack_mask.Remove(in);
544 in = OptoReg::add(in, -1);
545 }
546 aligned_stack_mask.clear_to_sets(RegMask::SlotsPerVecZ);
547 assert(aligned_stack_mask.is_AllStack(), "should be infinite stack");
548 *idealreg2spillmask[Op_VecZ] = *idealreg2regmask[Op_VecZ];
549 idealreg2spillmask[Op_VecZ]->OR(aligned_stack_mask);
550 }
551 if (UseFPUForSpilling) {
552 // This mask logic assumes that the spill operations are
553 // symmetric and that the registers involved are the same size.
554 // On sparc for instance we may have to use 64 bit moves will
555 // kill 2 registers when used with F0-F31.
556 idealreg2spillmask[Op_RegI]->OR(*idealreg2regmask[Op_RegF]);
557 idealreg2spillmask[Op_RegF]->OR(*idealreg2regmask[Op_RegI]);
558 #ifdef _LP64
559 idealreg2spillmask[Op_RegN]->OR(*idealreg2regmask[Op_RegF]);
560 idealreg2spillmask[Op_RegL]->OR(*idealreg2regmask[Op_RegD]);
561 idealreg2spillmask[Op_RegD]->OR(*idealreg2regmask[Op_RegL]);
562 idealreg2spillmask[Op_RegP]->OR(*idealreg2regmask[Op_RegD]);
563 #else
564 idealreg2spillmask[Op_RegP]->OR(*idealreg2regmask[Op_RegF]);
565 #ifdef ARM
566 // ARM has support for moving 64bit values between a pair of
567 // integer registers and a double register
568 idealreg2spillmask[Op_RegL]->OR(*idealreg2regmask[Op_RegD]);
569 idealreg2spillmask[Op_RegD]->OR(*idealreg2regmask[Op_RegL]);
570 #endif
571 #endif
572 }
573
574 // Make up debug masks. Any spill slot plus callee-save registers.
575 // Caller-save registers are assumed to be trashable by the various
576 // inline-cache fixup routines.
577 *idealreg2debugmask [Op_RegN]= *idealreg2spillmask[Op_RegN];
578 *idealreg2debugmask [Op_RegI]= *idealreg2spillmask[Op_RegI];
579 *idealreg2debugmask [Op_RegL]= *idealreg2spillmask[Op_RegL];
580 *idealreg2debugmask [Op_RegF]= *idealreg2spillmask[Op_RegF];
581 *idealreg2debugmask [Op_RegD]= *idealreg2spillmask[Op_RegD];
582 *idealreg2debugmask [Op_RegP]= *idealreg2spillmask[Op_RegP];
583
584 *idealreg2mhdebugmask[Op_RegN]= *idealreg2spillmask[Op_RegN];
585 *idealreg2mhdebugmask[Op_RegI]= *idealreg2spillmask[Op_RegI];
586 *idealreg2mhdebugmask[Op_RegL]= *idealreg2spillmask[Op_RegL];
587 *idealreg2mhdebugmask[Op_RegF]= *idealreg2spillmask[Op_RegF];
588 *idealreg2mhdebugmask[Op_RegD]= *idealreg2spillmask[Op_RegD];
589 *idealreg2mhdebugmask[Op_RegP]= *idealreg2spillmask[Op_RegP];
590
591 // Prevent stub compilations from attempting to reference
592 // callee-saved registers from debug info
593 bool exclude_soe = !Compile::current()->is_method_compilation();
594
595 for( i=OptoReg::Name(0); i<OptoReg::Name(_last_Mach_Reg); i = OptoReg::add(i,1) ) {
596 // registers the caller has to save do not work
597 if( _register_save_policy[i] == 'C' ||
598 _register_save_policy[i] == 'A' ||
599 (_register_save_policy[i] == 'E' && exclude_soe) ) {
600 idealreg2debugmask [Op_RegN]->Remove(i);
601 idealreg2debugmask [Op_RegI]->Remove(i); // Exclude save-on-call
602 idealreg2debugmask [Op_RegL]->Remove(i); // registers from debug
603 idealreg2debugmask [Op_RegF]->Remove(i); // masks
604 idealreg2debugmask [Op_RegD]->Remove(i);
605 idealreg2debugmask [Op_RegP]->Remove(i);
606
607 idealreg2mhdebugmask[Op_RegN]->Remove(i);
608 idealreg2mhdebugmask[Op_RegI]->Remove(i);
609 idealreg2mhdebugmask[Op_RegL]->Remove(i);
610 idealreg2mhdebugmask[Op_RegF]->Remove(i);
611 idealreg2mhdebugmask[Op_RegD]->Remove(i);
612 idealreg2mhdebugmask[Op_RegP]->Remove(i);
613 }
614 }
615
616 // Subtract the register we use to save the SP for MethodHandle
617 // invokes to from the debug mask.
618 const RegMask save_mask = method_handle_invoke_SP_save_mask();
619 idealreg2mhdebugmask[Op_RegN]->SUBTRACT(save_mask);
620 idealreg2mhdebugmask[Op_RegI]->SUBTRACT(save_mask);
621 idealreg2mhdebugmask[Op_RegL]->SUBTRACT(save_mask);
622 idealreg2mhdebugmask[Op_RegF]->SUBTRACT(save_mask);
623 idealreg2mhdebugmask[Op_RegD]->SUBTRACT(save_mask);
624 idealreg2mhdebugmask[Op_RegP]->SUBTRACT(save_mask);
625 }
626
627 //---------------------------is_save_on_entry----------------------------------
628 bool Matcher::is_save_on_entry( int reg ) {
629 return
630 _register_save_policy[reg] == 'E' ||
631 _register_save_policy[reg] == 'A' || // Save-on-entry register?
632 // Also save argument registers in the trampolining stubs
633 (C->save_argument_registers() && is_spillable_arg(reg));
634 }
635
636 //---------------------------Fixup_Save_On_Entry-------------------------------
637 void Matcher::Fixup_Save_On_Entry( ) {
638 init_first_stack_mask();
639
640 Node *root = C->root(); // Short name for root
641 // Count number of save-on-entry registers.
642 uint soe_cnt = number_of_saved_registers();
643 uint i;
644
645 // Find the procedure Start Node
646 StartNode *start = C->start();
647 assert( start, "Expect a start node" );
648
649 // Save argument registers in the trampolining stubs
650 if( C->save_argument_registers() )
651 for( i = 0; i < _last_Mach_Reg; i++ )
652 if( is_spillable_arg(i) )
653 soe_cnt++;
654
655 // Input RegMask array shared by all Returns.
656 // The type for doubles and longs has a count of 2, but
657 // there is only 1 returned value
658 uint ret_edge_cnt = TypeFunc::Parms + ((C->tf()->range()->cnt() == TypeFunc::Parms) ? 0 : 1);
659 RegMask *ret_rms = init_input_masks( ret_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
660 // Returns have 0 or 1 returned values depending on call signature.
661 // Return register is specified by return_value in the AD file.
662 if (ret_edge_cnt > TypeFunc::Parms)
663 ret_rms[TypeFunc::Parms+0] = _return_value_mask;
664
665 // Input RegMask array shared by all Rethrows.
666 uint reth_edge_cnt = TypeFunc::Parms+1;
667 RegMask *reth_rms = init_input_masks( reth_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
668 // Rethrow takes exception oop only, but in the argument 0 slot.
669 OptoReg::Name reg = find_receiver(false);
670 if (reg >= 0) {
671 reth_rms[TypeFunc::Parms] = mreg2regmask[reg];
672 #ifdef _LP64
673 // Need two slots for ptrs in 64-bit land
674 reth_rms[TypeFunc::Parms].Insert(OptoReg::add(OptoReg::Name(reg), 1));
675 #endif
676 }
677
678 // Input RegMask array shared by all TailCalls
679 uint tail_call_edge_cnt = TypeFunc::Parms+2;
680 RegMask *tail_call_rms = init_input_masks( tail_call_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
681
682 // Input RegMask array shared by all TailJumps
683 uint tail_jump_edge_cnt = TypeFunc::Parms+2;
684 RegMask *tail_jump_rms = init_input_masks( tail_jump_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
685
686 // TailCalls have 2 returned values (target & moop), whose masks come
687 // from the usual MachNode/MachOper mechanism. Find a sample
688 // TailCall to extract these masks and put the correct masks into
689 // the tail_call_rms array.
690 for( i=1; i < root->req(); i++ ) {
691 MachReturnNode *m = root->in(i)->as_MachReturn();
692 if( m->ideal_Opcode() == Op_TailCall ) {
693 tail_call_rms[TypeFunc::Parms+0] = m->MachNode::in_RegMask(TypeFunc::Parms+0);
694 tail_call_rms[TypeFunc::Parms+1] = m->MachNode::in_RegMask(TypeFunc::Parms+1);
695 break;
696 }
697 }
698
699 // TailJumps have 2 returned values (target & ex_oop), whose masks come
700 // from the usual MachNode/MachOper mechanism. Find a sample
701 // TailJump to extract these masks and put the correct masks into
702 // the tail_jump_rms array.
703 for( i=1; i < root->req(); i++ ) {
704 MachReturnNode *m = root->in(i)->as_MachReturn();
705 if( m->ideal_Opcode() == Op_TailJump ) {
706 tail_jump_rms[TypeFunc::Parms+0] = m->MachNode::in_RegMask(TypeFunc::Parms+0);
707 tail_jump_rms[TypeFunc::Parms+1] = m->MachNode::in_RegMask(TypeFunc::Parms+1);
708 break;
709 }
710 }
711
712 // Input RegMask array shared by all Halts
713 uint halt_edge_cnt = TypeFunc::Parms;
714 RegMask *halt_rms = init_input_masks( halt_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
715
716 // Capture the return input masks into each exit flavor
717 for( i=1; i < root->req(); i++ ) {
718 MachReturnNode *exit = root->in(i)->as_MachReturn();
719 switch( exit->ideal_Opcode() ) {
720 case Op_Return : exit->_in_rms = ret_rms; break;
721 case Op_Rethrow : exit->_in_rms = reth_rms; break;
722 case Op_TailCall : exit->_in_rms = tail_call_rms; break;
723 case Op_TailJump : exit->_in_rms = tail_jump_rms; break;
724 case Op_Halt : exit->_in_rms = halt_rms; break;
725 default : ShouldNotReachHere();
726 }
727 }
728
729 // Next unused projection number from Start.
730 int proj_cnt = C->tf()->domain()->cnt();
731
732 // Do all the save-on-entry registers. Make projections from Start for
733 // them, and give them a use at the exit points. To the allocator, they
734 // look like incoming register arguments.
735 for( i = 0; i < _last_Mach_Reg; i++ ) {
736 if( is_save_on_entry(i) ) {
737
738 // Add the save-on-entry to the mask array
739 ret_rms [ ret_edge_cnt] = mreg2regmask[i];
740 reth_rms [ reth_edge_cnt] = mreg2regmask[i];
741 tail_call_rms[tail_call_edge_cnt] = mreg2regmask[i];
742 tail_jump_rms[tail_jump_edge_cnt] = mreg2regmask[i];
743 // Halts need the SOE registers, but only in the stack as debug info.
744 // A just-prior uncommon-trap or deoptimization will use the SOE regs.
745 halt_rms [ halt_edge_cnt] = *idealreg2spillmask[_register_save_type[i]];
746
747 Node *mproj;
748
749 // Is this a RegF low half of a RegD? Double up 2 adjacent RegF's
750 // into a single RegD.
751 if( (i&1) == 0 &&
752 _register_save_type[i ] == Op_RegF &&
753 _register_save_type[i+1] == Op_RegF &&
754 is_save_on_entry(i+1) ) {
755 // Add other bit for double
756 ret_rms [ ret_edge_cnt].Insert(OptoReg::Name(i+1));
757 reth_rms [ reth_edge_cnt].Insert(OptoReg::Name(i+1));
758 tail_call_rms[tail_call_edge_cnt].Insert(OptoReg::Name(i+1));
759 tail_jump_rms[tail_jump_edge_cnt].Insert(OptoReg::Name(i+1));
760 halt_rms [ halt_edge_cnt].Insert(OptoReg::Name(i+1));
761 mproj = new MachProjNode( start, proj_cnt, ret_rms[ret_edge_cnt], Op_RegD );
762 proj_cnt += 2; // Skip 2 for doubles
763 }
764 else if( (i&1) == 1 && // Else check for high half of double
765 _register_save_type[i-1] == Op_RegF &&
766 _register_save_type[i ] == Op_RegF &&
767 is_save_on_entry(i-1) ) {
768 ret_rms [ ret_edge_cnt] = RegMask::Empty;
769 reth_rms [ reth_edge_cnt] = RegMask::Empty;
770 tail_call_rms[tail_call_edge_cnt] = RegMask::Empty;
771 tail_jump_rms[tail_jump_edge_cnt] = RegMask::Empty;
772 halt_rms [ halt_edge_cnt] = RegMask::Empty;
773 mproj = C->top();
774 }
775 // Is this a RegI low half of a RegL? Double up 2 adjacent RegI's
776 // into a single RegL.
777 else if( (i&1) == 0 &&
778 _register_save_type[i ] == Op_RegI &&
779 _register_save_type[i+1] == Op_RegI &&
780 is_save_on_entry(i+1) ) {
781 // Add other bit for long
782 ret_rms [ ret_edge_cnt].Insert(OptoReg::Name(i+1));
783 reth_rms [ reth_edge_cnt].Insert(OptoReg::Name(i+1));
784 tail_call_rms[tail_call_edge_cnt].Insert(OptoReg::Name(i+1));
785 tail_jump_rms[tail_jump_edge_cnt].Insert(OptoReg::Name(i+1));
786 halt_rms [ halt_edge_cnt].Insert(OptoReg::Name(i+1));
787 mproj = new MachProjNode( start, proj_cnt, ret_rms[ret_edge_cnt], Op_RegL );
788 proj_cnt += 2; // Skip 2 for longs
789 }
790 else if( (i&1) == 1 && // Else check for high half of long
791 _register_save_type[i-1] == Op_RegI &&
792 _register_save_type[i ] == Op_RegI &&
793 is_save_on_entry(i-1) ) {
794 ret_rms [ ret_edge_cnt] = RegMask::Empty;
795 reth_rms [ reth_edge_cnt] = RegMask::Empty;
796 tail_call_rms[tail_call_edge_cnt] = RegMask::Empty;
797 tail_jump_rms[tail_jump_edge_cnt] = RegMask::Empty;
798 halt_rms [ halt_edge_cnt] = RegMask::Empty;
799 mproj = C->top();
800 } else {
801 // Make a projection for it off the Start
802 mproj = new MachProjNode( start, proj_cnt++, ret_rms[ret_edge_cnt], _register_save_type[i] );
803 }
804
805 ret_edge_cnt ++;
806 reth_edge_cnt ++;
807 tail_call_edge_cnt ++;
808 tail_jump_edge_cnt ++;
809 halt_edge_cnt ++;
810
811 // Add a use of the SOE register to all exit paths
812 for( uint j=1; j < root->req(); j++ )
813 root->in(j)->add_req(mproj);
814 } // End of if a save-on-entry register
815 } // End of for all machine registers
816 }
817
818 //------------------------------init_spill_mask--------------------------------
819 void Matcher::init_spill_mask( Node *ret ) {
820 if( idealreg2regmask[Op_RegI] ) return; // One time only init
821
822 OptoReg::c_frame_pointer = c_frame_pointer();
823 c_frame_ptr_mask = c_frame_pointer();
824 #ifdef _LP64
825 // pointers are twice as big
826 c_frame_ptr_mask.Insert(OptoReg::add(c_frame_pointer(),1));
827 #endif
828
829 // Start at OptoReg::stack0()
830 STACK_ONLY_mask.Clear();
831 OptoReg::Name init = OptoReg::stack2reg(0);
832 // STACK_ONLY_mask is all stack bits
833 OptoReg::Name i;
834 for (i = init; RegMask::can_represent(i); i = OptoReg::add(i,1))
835 STACK_ONLY_mask.Insert(i);
836 // Also set the "infinite stack" bit.
837 STACK_ONLY_mask.set_AllStack();
838
839 // Copy the register names over into the shared world
840 for( i=OptoReg::Name(0); i<OptoReg::Name(_last_Mach_Reg); i = OptoReg::add(i,1) ) {
841 // SharedInfo::regName[i] = regName[i];
842 // Handy RegMasks per machine register
843 mreg2regmask[i].Insert(i);
844 }
845
846 // Grab the Frame Pointer
847 Node *fp = ret->in(TypeFunc::FramePtr);
848 Node *mem = ret->in(TypeFunc::Memory);
849 const TypePtr* atp = TypePtr::BOTTOM;
850 // Share frame pointer while making spill ops
851 set_shared(fp);
852
853 // Compute generic short-offset Loads
854 #ifdef _LP64
855 MachNode *spillCP = match_tree(new LoadNNode(NULL,mem,fp,atp,TypeInstPtr::BOTTOM,MemNode::unordered));
856 #endif
857 MachNode *spillI = match_tree(new LoadINode(NULL,mem,fp,atp,TypeInt::INT,MemNode::unordered));
858 MachNode *spillL = match_tree(new LoadLNode(NULL,mem,fp,atp,TypeLong::LONG,MemNode::unordered, LoadNode::DependsOnlyOnTest, false));
859 MachNode *spillF = match_tree(new LoadFNode(NULL,mem,fp,atp,Type::FLOAT,MemNode::unordered));
860 MachNode *spillD = match_tree(new LoadDNode(NULL,mem,fp,atp,Type::DOUBLE,MemNode::unordered));
861 MachNode *spillP = match_tree(new LoadPNode(NULL,mem,fp,atp,TypeInstPtr::BOTTOM,MemNode::unordered));
862 assert(spillI != NULL && spillL != NULL && spillF != NULL &&
863 spillD != NULL && spillP != NULL, "");
864 // Get the ADLC notion of the right regmask, for each basic type.
865 #ifdef _LP64
866 idealreg2regmask[Op_RegN] = &spillCP->out_RegMask();
867 #endif
868 idealreg2regmask[Op_RegI] = &spillI->out_RegMask();
869 idealreg2regmask[Op_RegL] = &spillL->out_RegMask();
870 idealreg2regmask[Op_RegF] = &spillF->out_RegMask();
871 idealreg2regmask[Op_RegD] = &spillD->out_RegMask();
872 idealreg2regmask[Op_RegP] = &spillP->out_RegMask();
873
874 // Vector regmasks.
875 if (Matcher::vector_size_supported(T_BYTE,4)) {
876 TypeVect::VECTS = TypeVect::make(T_BYTE, 4);
877 MachNode *spillVectS = match_tree(new LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTS));
878 idealreg2regmask[Op_VecS] = &spillVectS->out_RegMask();
879 }
880 if (Matcher::vector_size_supported(T_FLOAT,2)) {
881 MachNode *spillVectD = match_tree(new LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTD));
882 idealreg2regmask[Op_VecD] = &spillVectD->out_RegMask();
883 }
884 if (Matcher::vector_size_supported(T_FLOAT,4)) {
885 MachNode *spillVectX = match_tree(new LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTX));
886 idealreg2regmask[Op_VecX] = &spillVectX->out_RegMask();
887 }
888 if (Matcher::vector_size_supported(T_FLOAT,8)) {
889 MachNode *spillVectY = match_tree(new LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTY));
890 idealreg2regmask[Op_VecY] = &spillVectY->out_RegMask();
891 }
892 if (Matcher::vector_size_supported(T_FLOAT,16)) {
893 MachNode *spillVectZ = match_tree(new LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTZ));
894 idealreg2regmask[Op_VecZ] = &spillVectZ->out_RegMask();
895 }
896 }
897
898 #ifdef ASSERT
899 static void match_alias_type(Compile* C, Node* n, Node* m) {
900 if (!VerifyAliases) return; // do not go looking for trouble by default
901 const TypePtr* nat = n->adr_type();
902 const TypePtr* mat = m->adr_type();
903 int nidx = C->get_alias_index(nat);
904 int midx = C->get_alias_index(mat);
905 // Detune the assert for cases like (AndI 0xFF (LoadB p)).
906 if (nidx == Compile::AliasIdxTop && midx >= Compile::AliasIdxRaw) {
907 for (uint i = 1; i < n->req(); i++) {
908 Node* n1 = n->in(i);
909 const TypePtr* n1at = n1->adr_type();
910 if (n1at != NULL) {
911 nat = n1at;
912 nidx = C->get_alias_index(n1at);
913 }
914 }
915 }
916 // %%% Kludgery. Instead, fix ideal adr_type methods for all these cases:
917 if (nidx == Compile::AliasIdxTop && midx == Compile::AliasIdxRaw) {
918 switch (n->Opcode()) {
919 case Op_PrefetchAllocation:
920 nidx = Compile::AliasIdxRaw;
921 nat = TypeRawPtr::BOTTOM;
922 break;
923 }
924 }
925 if (nidx == Compile::AliasIdxRaw && midx == Compile::AliasIdxTop) {
926 switch (n->Opcode()) {
927 case Op_ClearArray:
928 midx = Compile::AliasIdxRaw;
929 mat = TypeRawPtr::BOTTOM;
930 break;
931 }
932 }
933 if (nidx == Compile::AliasIdxTop && midx == Compile::AliasIdxBot) {
934 switch (n->Opcode()) {
935 case Op_Return:
936 case Op_Rethrow:
937 case Op_Halt:
938 case Op_TailCall:
939 case Op_TailJump:
940 nidx = Compile::AliasIdxBot;
941 nat = TypePtr::BOTTOM;
942 break;
943 }
944 }
945 if (nidx == Compile::AliasIdxBot && midx == Compile::AliasIdxTop) {
946 switch (n->Opcode()) {
947 case Op_StrComp:
948 case Op_StrEquals:
949 case Op_StrIndexOf:
950 case Op_StrIndexOfChar:
951 case Op_AryEq:
952 case Op_HasNegatives:
953 case Op_MemBarVolatile:
954 case Op_MemBarCPUOrder: // %%% these ideals should have narrower adr_type?
955 case Op_StrInflatedCopy:
956 case Op_StrCompressedCopy:
957 case Op_OnSpinWait:
958 case Op_EncodeISOArray:
959 nidx = Compile::AliasIdxTop;
960 nat = NULL;
961 break;
962 }
963 }
964 if (nidx != midx) {
965 if (PrintOpto || (PrintMiscellaneous && (WizardMode || Verbose))) {
966 tty->print_cr("==== Matcher alias shift %d => %d", nidx, midx);
967 n->dump();
968 m->dump();
969 }
970 assert(C->subsume_loads() && C->must_alias(nat, midx),
971 "must not lose alias info when matching");
972 }
973 }
974 #endif
975
976 //------------------------------xform------------------------------------------
977 // Given a Node in old-space, Match him (Label/Reduce) to produce a machine
978 // Node in new-space. Given a new-space Node, recursively walk his children.
979 Node *Matcher::transform( Node *n ) { ShouldNotCallThis(); return n; }
980 Node *Matcher::xform( Node *n, int max_stack ) {
981 // Use one stack to keep both: child's node/state and parent's node/index
982 MStack mstack(max_stack * 2 * 2); // usually: C->live_nodes() * 2 * 2
983 mstack.push(n, Visit, NULL, -1); // set NULL as parent to indicate root
984 while (mstack.is_nonempty()) {
985 C->check_node_count(NodeLimitFudgeFactor, "too many nodes matching instructions");
986 if (C->failing()) return NULL;
987 n = mstack.node(); // Leave node on stack
988 Node_State nstate = mstack.state();
989 if (nstate == Visit) {
990 mstack.set_state(Post_Visit);
991 Node *oldn = n;
992 // Old-space or new-space check
993 if (!C->node_arena()->contains(n)) {
994 // Old space!
995 Node* m;
996 if (has_new_node(n)) { // Not yet Label/Reduced
997 m = new_node(n);
998 } else {
999 if (!is_dontcare(n)) { // Matcher can match this guy
1000 // Calls match special. They match alone with no children.
1001 // Their children, the incoming arguments, match normally.
1002 m = n->is_SafePoint() ? match_sfpt(n->as_SafePoint()):match_tree(n);
1003 if (C->failing()) return NULL;
1004 if (m == NULL) { Matcher::soft_match_failure(); return NULL; }
1005 if (n->is_MemBar()) {
1006 m->as_MachMemBar()->set_adr_type(n->adr_type());
1007 }
1008 } else { // Nothing the matcher cares about
1009 if (n->is_Proj() && n->in(0) != NULL && n->in(0)->is_Multi()) { // Projections?
1010 // Convert to machine-dependent projection
1011 m = n->in(0)->as_Multi()->match( n->as_Proj(), this );
1012 #ifdef ASSERT
1013 _new2old_map.map(m->_idx, n);
1014 #endif
1015 if (m->in(0) != NULL) // m might be top
1016 collect_null_checks(m, n);
1017 } else { // Else just a regular 'ol guy
1018 m = n->clone(); // So just clone into new-space
1019 #ifdef ASSERT
1020 _new2old_map.map(m->_idx, n);
1021 #endif
1022 // Def-Use edges will be added incrementally as Uses
1023 // of this node are matched.
1024 assert(m->outcnt() == 0, "no Uses of this clone yet");
1025 }
1026 }
1027
1028 set_new_node(n, m); // Map old to new
1029 if (_old_node_note_array != NULL) {
1030 Node_Notes* nn = C->locate_node_notes(_old_node_note_array,
1031 n->_idx);
1032 C->set_node_notes_at(m->_idx, nn);
1033 }
1034 debug_only(match_alias_type(C, n, m));
1035 }
1036 n = m; // n is now a new-space node
1037 mstack.set_node(n);
1038 }
1039
1040 // New space!
1041 if (_visited.test_set(n->_idx)) continue; // while(mstack.is_nonempty())
1042
1043 int i;
1044 // Put precedence edges on stack first (match them last).
1045 for (i = oldn->req(); (uint)i < oldn->len(); i++) {
1046 Node *m = oldn->in(i);
1047 if (m == NULL) break;
1048 // set -1 to call add_prec() instead of set_req() during Step1
1049 mstack.push(m, Visit, n, -1);
1050 }
1051
1052 // Handle precedence edges for interior nodes
1053 for (i = n->len()-1; (uint)i >= n->req(); i--) {
1054 Node *m = n->in(i);
1055 if (m == NULL || C->node_arena()->contains(m)) continue;
1056 n->rm_prec(i);
1057 // set -1 to call add_prec() instead of set_req() during Step1
1058 mstack.push(m, Visit, n, -1);
1059 }
1060
1061 // For constant debug info, I'd rather have unmatched constants.
1062 int cnt = n->req();
1063 JVMState* jvms = n->jvms();
1064 int debug_cnt = jvms ? jvms->debug_start() : cnt;
1065
1066 // Now do only debug info. Clone constants rather than matching.
1067 // Constants are represented directly in the debug info without
1068 // the need for executable machine instructions.
1069 // Monitor boxes are also represented directly.
1070 for (i = cnt - 1; i >= debug_cnt; --i) { // For all debug inputs do
1071 Node *m = n->in(i); // Get input
1072 int op = m->Opcode();
1073 assert((op == Op_BoxLock) == jvms->is_monitor_use(i), "boxes only at monitor sites");
1074 if( op == Op_ConI || op == Op_ConP || op == Op_ConN || op == Op_ConNKlass ||
1075 op == Op_ConF || op == Op_ConD || op == Op_ConL
1076 // || op == Op_BoxLock // %%%% enable this and remove (+++) in chaitin.cpp
1077 ) {
1078 m = m->clone();
1079 #ifdef ASSERT
1080 _new2old_map.map(m->_idx, n);
1081 #endif
1082 mstack.push(m, Post_Visit, n, i); // Don't need to visit
1083 mstack.push(m->in(0), Visit, m, 0);
1084 } else {
1085 mstack.push(m, Visit, n, i);
1086 }
1087 }
1088
1089 // And now walk his children, and convert his inputs to new-space.
1090 for( ; i >= 0; --i ) { // For all normal inputs do
1091 Node *m = n->in(i); // Get input
1092 if(m != NULL)
1093 mstack.push(m, Visit, n, i);
1094 }
1095
1096 }
1097 else if (nstate == Post_Visit) {
1098 // Set xformed input
1099 Node *p = mstack.parent();
1100 if (p != NULL) { // root doesn't have parent
1101 int i = (int)mstack.index();
1102 if (i >= 0)
1103 p->set_req(i, n); // required input
1104 else if (i == -1)
1105 p->add_prec(n); // precedence input
1106 else
1107 ShouldNotReachHere();
1108 }
1109 mstack.pop(); // remove processed node from stack
1110 }
1111 else {
1112 ShouldNotReachHere();
1113 }
1114 } // while (mstack.is_nonempty())
1115 return n; // Return new-space Node
1116 }
1117
1118 //------------------------------warp_outgoing_stk_arg------------------------
1119 OptoReg::Name Matcher::warp_outgoing_stk_arg( VMReg reg, OptoReg::Name begin_out_arg_area, OptoReg::Name &out_arg_limit_per_call ) {
1120 // Convert outgoing argument location to a pre-biased stack offset
1121 if (reg->is_stack()) {
1122 OptoReg::Name warped = reg->reg2stack();
1123 // Adjust the stack slot offset to be the register number used
1124 // by the allocator.
1125 warped = OptoReg::add(begin_out_arg_area, warped);
1126 // Keep track of the largest numbered stack slot used for an arg.
1127 // Largest used slot per call-site indicates the amount of stack
1128 // that is killed by the call.
1129 if( warped >= out_arg_limit_per_call )
1130 out_arg_limit_per_call = OptoReg::add(warped,1);
1131 if (!RegMask::can_represent_arg(warped)) {
1132 C->record_method_not_compilable("unsupported calling sequence");
1133 return OptoReg::Bad;
1134 }
1135 return warped;
1136 }
1137 return OptoReg::as_OptoReg(reg);
1138 }
1139
1140
1141 //------------------------------match_sfpt-------------------------------------
1142 // Helper function to match call instructions. Calls match special.
1143 // They match alone with no children. Their children, the incoming
1144 // arguments, match normally.
1145 MachNode *Matcher::match_sfpt( SafePointNode *sfpt ) {
1146 MachSafePointNode *msfpt = NULL;
1147 MachCallNode *mcall = NULL;
1148 uint cnt;
1149 // Split out case for SafePoint vs Call
1150 CallNode *call;
1151 const TypeTuple *domain;
1152 ciMethod* method = NULL;
1153 bool is_method_handle_invoke = false; // for special kill effects
1154 if( sfpt->is_Call() ) {
1155 call = sfpt->as_Call();
1156 domain = call->tf()->domain();
1157 cnt = domain->cnt();
1158
1159 // Match just the call, nothing else
1160 MachNode *m = match_tree(call);
1161 if (C->failing()) return NULL;
1162 if( m == NULL ) { Matcher::soft_match_failure(); return NULL; }
1163
1164 // Copy data from the Ideal SafePoint to the machine version
1165 mcall = m->as_MachCall();
1166
1167 mcall->set_tf( call->tf());
1168 mcall->set_entry_point(call->entry_point());
1169 mcall->set_cnt( call->cnt());
1170
1171 if( mcall->is_MachCallJava() ) {
1172 MachCallJavaNode *mcall_java = mcall->as_MachCallJava();
1173 const CallJavaNode *call_java = call->as_CallJava();
1174 assert(call_java->validate_symbolic_info(), "inconsistent info");
1175 method = call_java->method();
1176 mcall_java->_method = method;
1177 mcall_java->_bci = call_java->_bci;
1178 mcall_java->_optimized_virtual = call_java->is_optimized_virtual();
1179 is_method_handle_invoke = call_java->is_method_handle_invoke();
1180 mcall_java->_method_handle_invoke = is_method_handle_invoke;
1181 mcall_java->_override_symbolic_info = call_java->override_symbolic_info();
1182 if (is_method_handle_invoke) {
1183 C->set_has_method_handle_invokes(true);
1184 }
1185 if( mcall_java->is_MachCallStaticJava() )
1186 mcall_java->as_MachCallStaticJava()->_name =
1187 call_java->as_CallStaticJava()->_name;
1188 if( mcall_java->is_MachCallDynamicJava() )
1189 mcall_java->as_MachCallDynamicJava()->_vtable_index =
1190 call_java->as_CallDynamicJava()->_vtable_index;
1191 }
1192 else if( mcall->is_MachCallRuntime() ) {
1193 mcall->as_MachCallRuntime()->_name = call->as_CallRuntime()->_name;
1194 }
1195 msfpt = mcall;
1196 }
1197 // This is a non-call safepoint
1198 else {
1199 call = NULL;
1200 domain = NULL;
1201 MachNode *mn = match_tree(sfpt);
1202 if (C->failing()) return NULL;
1203 msfpt = mn->as_MachSafePoint();
1204 cnt = TypeFunc::Parms;
1205 }
1206
1207 // Advertise the correct memory effects (for anti-dependence computation).
1208 msfpt->set_adr_type(sfpt->adr_type());
1209
1210 // Allocate a private array of RegMasks. These RegMasks are not shared.
1211 msfpt->_in_rms = NEW_RESOURCE_ARRAY( RegMask, cnt );
1212 // Empty them all.
1213 memset( msfpt->_in_rms, 0, sizeof(RegMask)*cnt );
1214
1215 // Do all the pre-defined non-Empty register masks
1216 msfpt->_in_rms[TypeFunc::ReturnAdr] = _return_addr_mask;
1217 msfpt->_in_rms[TypeFunc::FramePtr ] = c_frame_ptr_mask;
1218
1219 // Place first outgoing argument can possibly be put.
1220 OptoReg::Name begin_out_arg_area = OptoReg::add(_new_SP, C->out_preserve_stack_slots());
1221 assert( is_even(begin_out_arg_area), "" );
1222 // Compute max outgoing register number per call site.
1223 OptoReg::Name out_arg_limit_per_call = begin_out_arg_area;
1224 // Calls to C may hammer extra stack slots above and beyond any arguments.
1225 // These are usually backing store for register arguments for varargs.
1226 if( call != NULL && call->is_CallRuntime() )
1227 out_arg_limit_per_call = OptoReg::add(out_arg_limit_per_call,C->varargs_C_out_slots_killed());
1228
1229
1230 // Do the normal argument list (parameters) register masks
1231 int argcnt = cnt - TypeFunc::Parms;
1232 if( argcnt > 0 ) { // Skip it all if we have no args
1233 BasicType *sig_bt = NEW_RESOURCE_ARRAY( BasicType, argcnt );
1234 VMRegPair *parm_regs = NEW_RESOURCE_ARRAY( VMRegPair, argcnt );
1235 int i;
1236 for( i = 0; i < argcnt; i++ ) {
1237 sig_bt[i] = domain->field_at(i+TypeFunc::Parms)->basic_type();
1238 }
1239 // V-call to pick proper calling convention
1240 call->calling_convention( sig_bt, parm_regs, argcnt );
1241
1242 #ifdef ASSERT
1243 // Sanity check users' calling convention. Really handy during
1244 // the initial porting effort. Fairly expensive otherwise.
1245 { for (int i = 0; i<argcnt; i++) {
1246 if( !parm_regs[i].first()->is_valid() &&
1247 !parm_regs[i].second()->is_valid() ) continue;
1248 VMReg reg1 = parm_regs[i].first();
1249 VMReg reg2 = parm_regs[i].second();
1250 for (int j = 0; j < i; j++) {
1251 if( !parm_regs[j].first()->is_valid() &&
1252 !parm_regs[j].second()->is_valid() ) continue;
1253 VMReg reg3 = parm_regs[j].first();
1254 VMReg reg4 = parm_regs[j].second();
1255 if( !reg1->is_valid() ) {
1256 assert( !reg2->is_valid(), "valid halvsies" );
1257 } else if( !reg3->is_valid() ) {
1258 assert( !reg4->is_valid(), "valid halvsies" );
1259 } else {
1260 assert( reg1 != reg2, "calling conv. must produce distinct regs");
1261 assert( reg1 != reg3, "calling conv. must produce distinct regs");
1262 assert( reg1 != reg4, "calling conv. must produce distinct regs");
1263 assert( reg2 != reg3, "calling conv. must produce distinct regs");
1264 assert( reg2 != reg4 || !reg2->is_valid(), "calling conv. must produce distinct regs");
1265 assert( reg3 != reg4, "calling conv. must produce distinct regs");
1266 }
1267 }
1268 }
1269 }
1270 #endif
1271
1272 // Visit each argument. Compute its outgoing register mask.
1273 // Return results now can have 2 bits returned.
1274 // Compute max over all outgoing arguments both per call-site
1275 // and over the entire method.
1276 for( i = 0; i < argcnt; i++ ) {
1277 // Address of incoming argument mask to fill in
1278 RegMask *rm = &mcall->_in_rms[i+TypeFunc::Parms];
1279 if( !parm_regs[i].first()->is_valid() &&
1280 !parm_regs[i].second()->is_valid() ) {
1281 continue; // Avoid Halves
1282 }
1283 // Grab first register, adjust stack slots and insert in mask.
1284 OptoReg::Name reg1 = warp_outgoing_stk_arg(parm_regs[i].first(), begin_out_arg_area, out_arg_limit_per_call );
1285 if (OptoReg::is_valid(reg1))
1286 rm->Insert( reg1 );
1287 // Grab second register (if any), adjust stack slots and insert in mask.
1288 OptoReg::Name reg2 = warp_outgoing_stk_arg(parm_regs[i].second(), begin_out_arg_area, out_arg_limit_per_call );
1289 if (OptoReg::is_valid(reg2))
1290 rm->Insert( reg2 );
1291 } // End of for all arguments
1292
1293 // Compute number of stack slots needed to restore stack in case of
1294 // Pascal-style argument popping.
1295 mcall->_argsize = out_arg_limit_per_call - begin_out_arg_area;
1296 }
1297
1298 // Compute the max stack slot killed by any call. These will not be
1299 // available for debug info, and will be used to adjust FIRST_STACK_mask
1300 // after all call sites have been visited.
1301 if( _out_arg_limit < out_arg_limit_per_call)
1302 _out_arg_limit = out_arg_limit_per_call;
1303
1304 if (mcall) {
1305 // Kill the outgoing argument area, including any non-argument holes and
1306 // any legacy C-killed slots. Use Fat-Projections to do the killing.
1307 // Since the max-per-method covers the max-per-call-site and debug info
1308 // is excluded on the max-per-method basis, debug info cannot land in
1309 // this killed area.
1310 uint r_cnt = mcall->tf()->range()->cnt();
1311 MachProjNode *proj = new MachProjNode( mcall, r_cnt+10000, RegMask::Empty, MachProjNode::fat_proj );
1312 if (!RegMask::can_represent_arg(OptoReg::Name(out_arg_limit_per_call-1))) {
1313 C->record_method_not_compilable("unsupported outgoing calling sequence");
1314 } else {
1315 for (int i = begin_out_arg_area; i < out_arg_limit_per_call; i++)
1316 proj->_rout.Insert(OptoReg::Name(i));
1317 }
1318 if (proj->_rout.is_NotEmpty()) {
1319 push_projection(proj);
1320 }
1321 }
1322 // Transfer the safepoint information from the call to the mcall
1323 // Move the JVMState list
1324 msfpt->set_jvms(sfpt->jvms());
1325 for (JVMState* jvms = msfpt->jvms(); jvms; jvms = jvms->caller()) {
1326 jvms->set_map(sfpt);
1327 }
1328
1329 // Debug inputs begin just after the last incoming parameter
1330 assert((mcall == NULL) || (mcall->jvms() == NULL) ||
1331 (mcall->jvms()->debug_start() + mcall->_jvmadj == mcall->tf()->domain()->cnt()), "");
1332
1333 // Move the OopMap
1334 msfpt->_oop_map = sfpt->_oop_map;
1335
1336 // Add additional edges.
1337 if (msfpt->mach_constant_base_node_input() != (uint)-1 && !msfpt->is_MachCallLeaf()) {
1338 // For these calls we can not add MachConstantBase in expand(), as the
1339 // ins are not complete then.
1340 msfpt->ins_req(msfpt->mach_constant_base_node_input(), C->mach_constant_base_node());
1341 if (msfpt->jvms() &&
1342 msfpt->mach_constant_base_node_input() <= msfpt->jvms()->debug_start() + msfpt->_jvmadj) {
1343 // We added an edge before jvms, so we must adapt the position of the ins.
1344 msfpt->jvms()->adapt_position(+1);
1345 }
1346 }
1347
1348 // Registers killed by the call are set in the local scheduling pass
1349 // of Global Code Motion.
1350 return msfpt;
1351 }
1352
1353 //---------------------------match_tree----------------------------------------
1354 // Match a Ideal Node DAG - turn it into a tree; Label & Reduce. Used as part
1355 // of the whole-sale conversion from Ideal to Mach Nodes. Also used for
1356 // making GotoNodes while building the CFG and in init_spill_mask() to identify
1357 // a Load's result RegMask for memoization in idealreg2regmask[]
1358 MachNode *Matcher::match_tree( const Node *n ) {
1359 assert( n->Opcode() != Op_Phi, "cannot match" );
1360 assert( !n->is_block_start(), "cannot match" );
1361 // Set the mark for all locally allocated State objects.
1362 // When this call returns, the _states_arena arena will be reset
1363 // freeing all State objects.
1364 ResourceMark rm( &_states_arena );
1365
1366 LabelRootDepth = 0;
1367
1368 // StoreNodes require their Memory input to match any LoadNodes
1369 Node *mem = n->is_Store() ? n->in(MemNode::Memory) : (Node*)1 ;
1370 #ifdef ASSERT
1371 Node* save_mem_node = _mem_node;
1372 _mem_node = n->is_Store() ? (Node*)n : NULL;
1373 #endif
1374 // State object for root node of match tree
1375 // Allocate it on _states_arena - stack allocation can cause stack overflow.
1376 State *s = new (&_states_arena) State;
1377 s->_kids[0] = NULL;
1378 s->_kids[1] = NULL;
1379 s->_leaf = (Node*)n;
1380 // Label the input tree, allocating labels from top-level arena
1381 Label_Root( n, s, n->in(0), mem );
1382 if (C->failing()) return NULL;
1383
1384 // The minimum cost match for the whole tree is found at the root State
1385 uint mincost = max_juint;
1386 uint cost = max_juint;
1387 uint i;
1388 for( i = 0; i < NUM_OPERANDS; i++ ) {
1389 if( s->valid(i) && // valid entry and
1390 s->_cost[i] < cost && // low cost and
1391 s->_rule[i] >= NUM_OPERANDS ) // not an operand
1392 cost = s->_cost[mincost=i];
1393 }
1394 if (mincost == max_juint) {
1395 #ifndef PRODUCT
1396 tty->print("No matching rule for:");
1397 s->dump();
1398 #endif
1399 Matcher::soft_match_failure();
1400 return NULL;
1401 }
1402 // Reduce input tree based upon the state labels to machine Nodes
1403 MachNode *m = ReduceInst( s, s->_rule[mincost], mem );
1404 #ifdef ASSERT
1405 _old2new_map.map(n->_idx, m);
1406 _new2old_map.map(m->_idx, (Node*)n);
1407 #endif
1408
1409 // Add any Matcher-ignored edges
1410 uint cnt = n->req();
1411 uint start = 1;
1412 if( mem != (Node*)1 ) start = MemNode::Memory+1;
1413 if( n->is_AddP() ) {
1414 assert( mem == (Node*)1, "" );
1415 start = AddPNode::Base+1;
1416 }
1417 for( i = start; i < cnt; i++ ) {
1418 if( !n->match_edge(i) ) {
1419 if( i < m->req() )
1420 m->ins_req( i, n->in(i) );
1421 else
1422 m->add_req( n->in(i) );
1423 }
1424 }
1425
1426 debug_only( _mem_node = save_mem_node; )
1427 return m;
1428 }
1429
1430
1431 //------------------------------match_into_reg---------------------------------
1432 // Choose to either match this Node in a register or part of the current
1433 // match tree. Return true for requiring a register and false for matching
1434 // as part of the current match tree.
1435 static bool match_into_reg( const Node *n, Node *m, Node *control, int i, bool shared ) {
1436
1437 const Type *t = m->bottom_type();
1438
1439 if (t->singleton()) {
1440 // Never force constants into registers. Allow them to match as
1441 // constants or registers. Copies of the same value will share
1442 // the same register. See find_shared_node.
1443 return false;
1444 } else { // Not a constant
1445 // Stop recursion if they have different Controls.
1446 Node* m_control = m->in(0);
1447 // Control of load's memory can post-dominates load's control.
1448 // So use it since load can't float above its memory.
1449 Node* mem_control = (m->is_Load()) ? m->in(MemNode::Memory)->in(0) : NULL;
1450 if (control && m_control && control != m_control && control != mem_control) {
1451
1452 // Actually, we can live with the most conservative control we
1453 // find, if it post-dominates the others. This allows us to
1454 // pick up load/op/store trees where the load can float a little
1455 // above the store.
1456 Node *x = control;
1457 const uint max_scan = 6; // Arbitrary scan cutoff
1458 uint j;
1459 for (j=0; j<max_scan; j++) {
1460 if (x->is_Region()) // Bail out at merge points
1461 return true;
1462 x = x->in(0);
1463 if (x == m_control) // Does 'control' post-dominate
1464 break; // m->in(0)? If so, we can use it
1465 if (x == mem_control) // Does 'control' post-dominate
1466 break; // mem_control? If so, we can use it
1467 }
1468 if (j == max_scan) // No post-domination before scan end?
1469 return true; // Then break the match tree up
1470 }
1471 if ((m->is_DecodeN() && Matcher::narrow_oop_use_complex_address()) ||
1472 (m->is_DecodeNKlass() && Matcher::narrow_klass_use_complex_address())) {
1473 // These are commonly used in address expressions and can
1474 // efficiently fold into them on X64 in some cases.
1475 return false;
1476 }
1477 }
1478
1479 // Not forceable cloning. If shared, put it into a register.
1480 return shared;
1481 }
1482
1483
1484 //------------------------------Instruction Selection--------------------------
1485 // Label method walks a "tree" of nodes, using the ADLC generated DFA to match
1486 // ideal nodes to machine instructions. Trees are delimited by shared Nodes,
1487 // things the Matcher does not match (e.g., Memory), and things with different
1488 // Controls (hence forced into different blocks). We pass in the Control
1489 // selected for this entire State tree.
1490
1491 // The Matcher works on Trees, but an Intel add-to-memory requires a DAG: the
1492 // Store and the Load must have identical Memories (as well as identical
1493 // pointers). Since the Matcher does not have anything for Memory (and
1494 // does not handle DAGs), I have to match the Memory input myself. If the
1495 // Tree root is a Store, I require all Loads to have the identical memory.
1496 Node *Matcher::Label_Root( const Node *n, State *svec, Node *control, const Node *mem){
1497 // Since Label_Root is a recursive function, its possible that we might run
1498 // out of stack space. See bugs 6272980 & 6227033 for more info.
1499 LabelRootDepth++;
1500 if (LabelRootDepth > MaxLabelRootDepth) {
1501 C->record_method_not_compilable("Out of stack space, increase MaxLabelRootDepth");
1502 return NULL;
1503 }
1504 uint care = 0; // Edges matcher cares about
1505 uint cnt = n->req();
1506 uint i = 0;
1507
1508 // Examine children for memory state
1509 // Can only subsume a child into your match-tree if that child's memory state
1510 // is not modified along the path to another input.
1511 // It is unsafe even if the other inputs are separate roots.
1512 Node *input_mem = NULL;
1513 for( i = 1; i < cnt; i++ ) {
1514 if( !n->match_edge(i) ) continue;
1515 Node *m = n->in(i); // Get ith input
1516 assert( m, "expect non-null children" );
1517 if( m->is_Load() ) {
1518 if( input_mem == NULL ) {
1519 input_mem = m->in(MemNode::Memory);
1520 } else if( input_mem != m->in(MemNode::Memory) ) {
1521 input_mem = NodeSentinel;
1522 }
1523 }
1524 }
1525
1526 for( i = 1; i < cnt; i++ ){// For my children
1527 if( !n->match_edge(i) ) continue;
1528 Node *m = n->in(i); // Get ith input
1529 // Allocate states out of a private arena
1530 State *s = new (&_states_arena) State;
1531 svec->_kids[care++] = s;
1532 assert( care <= 2, "binary only for now" );
1533
1534 // Recursively label the State tree.
1535 s->_kids[0] = NULL;
1536 s->_kids[1] = NULL;
1537 s->_leaf = m;
1538
1539 // Check for leaves of the State Tree; things that cannot be a part of
1540 // the current tree. If it finds any, that value is matched as a
1541 // register operand. If not, then the normal matching is used.
1542 if( match_into_reg(n, m, control, i, is_shared(m)) ||
1543 //
1544 // Stop recursion if this is LoadNode and the root of this tree is a
1545 // StoreNode and the load & store have different memories.
1546 ((mem!=(Node*)1) && m->is_Load() && m->in(MemNode::Memory) != mem) ||
1547 // Can NOT include the match of a subtree when its memory state
1548 // is used by any of the other subtrees
1549 (input_mem == NodeSentinel) ) {
1550 // Print when we exclude matching due to different memory states at input-loads
1551 if (PrintOpto && (Verbose && WizardMode) && (input_mem == NodeSentinel)
1552 && !((mem!=(Node*)1) && m->is_Load() && m->in(MemNode::Memory) != mem)) {
1553 tty->print_cr("invalid input_mem");
1554 }
1555 // Switch to a register-only opcode; this value must be in a register
1556 // and cannot be subsumed as part of a larger instruction.
1557 s->DFA( m->ideal_reg(), m );
1558
1559 } else {
1560 // If match tree has no control and we do, adopt it for entire tree
1561 if( control == NULL && m->in(0) != NULL && m->req() > 1 )
1562 control = m->in(0); // Pick up control
1563 // Else match as a normal part of the match tree.
1564 control = Label_Root(m,s,control,mem);
1565 if (C->failing()) return NULL;
1566 }
1567 }
1568
1569
1570 // Call DFA to match this node, and return
1571 svec->DFA( n->Opcode(), n );
1572
1573 #ifdef ASSERT
1574 uint x;
1575 for( x = 0; x < _LAST_MACH_OPER; x++ )
1576 if( svec->valid(x) )
1577 break;
1578
1579 if (x >= _LAST_MACH_OPER) {
1580 n->dump();
1581 svec->dump();
1582 assert( false, "bad AD file" );
1583 }
1584 #endif
1585 return control;
1586 }
1587
1588
1589 // Con nodes reduced using the same rule can share their MachNode
1590 // which reduces the number of copies of a constant in the final
1591 // program. The register allocator is free to split uses later to
1592 // split live ranges.
1593 MachNode* Matcher::find_shared_node(Node* leaf, uint rule) {
1594 if (!leaf->is_Con() && !leaf->is_DecodeNarrowPtr()) return NULL;
1595
1596 // See if this Con has already been reduced using this rule.
1597 if (_shared_nodes.Size() <= leaf->_idx) return NULL;
1598 MachNode* last = (MachNode*)_shared_nodes.at(leaf->_idx);
1599 if (last != NULL && rule == last->rule()) {
1600 // Don't expect control change for DecodeN
1601 if (leaf->is_DecodeNarrowPtr())
1602 return last;
1603 // Get the new space root.
1604 Node* xroot = new_node(C->root());
1605 if (xroot == NULL) {
1606 // This shouldn't happen give the order of matching.
1607 return NULL;
1608 }
1609
1610 // Shared constants need to have their control be root so they
1611 // can be scheduled properly.
1612 Node* control = last->in(0);
1613 if (control != xroot) {
1614 if (control == NULL || control == C->root()) {
1615 last->set_req(0, xroot);
1616 } else {
1617 assert(false, "unexpected control");
1618 return NULL;
1619 }
1620 }
1621 return last;
1622 }
1623 return NULL;
1624 }
1625
1626
1627 //------------------------------ReduceInst-------------------------------------
1628 // Reduce a State tree (with given Control) into a tree of MachNodes.
1629 // This routine (and it's cohort ReduceOper) convert Ideal Nodes into
1630 // complicated machine Nodes. Each MachNode covers some tree of Ideal Nodes.
1631 // Each MachNode has a number of complicated MachOper operands; each
1632 // MachOper also covers a further tree of Ideal Nodes.
1633
1634 // The root of the Ideal match tree is always an instruction, so we enter
1635 // the recursion here. After building the MachNode, we need to recurse
1636 // the tree checking for these cases:
1637 // (1) Child is an instruction -
1638 // Build the instruction (recursively), add it as an edge.
1639 // Build a simple operand (register) to hold the result of the instruction.
1640 // (2) Child is an interior part of an instruction -
1641 // Skip over it (do nothing)
1642 // (3) Child is the start of a operand -
1643 // Build the operand, place it inside the instruction
1644 // Call ReduceOper.
1645 MachNode *Matcher::ReduceInst( State *s, int rule, Node *&mem ) {
1646 assert( rule >= NUM_OPERANDS, "called with operand rule" );
1647
1648 MachNode* shared_node = find_shared_node(s->_leaf, rule);
1649 if (shared_node != NULL) {
1650 return shared_node;
1651 }
1652
1653 // Build the object to represent this state & prepare for recursive calls
1654 MachNode *mach = s->MachNodeGenerator(rule);
1655 guarantee(mach != NULL, "Missing MachNode");
1656 mach->_opnds[0] = s->MachOperGenerator(_reduceOp[rule]);
1657 assert( mach->_opnds[0] != NULL, "Missing result operand" );
1658 Node *leaf = s->_leaf;
1659 // Check for instruction or instruction chain rule
1660 if( rule >= _END_INST_CHAIN_RULE || rule < _BEGIN_INST_CHAIN_RULE ) {
1661 assert(C->node_arena()->contains(s->_leaf) || !has_new_node(s->_leaf),
1662 "duplicating node that's already been matched");
1663 // Instruction
1664 mach->add_req( leaf->in(0) ); // Set initial control
1665 // Reduce interior of complex instruction
1666 ReduceInst_Interior( s, rule, mem, mach, 1 );
1667 } else {
1668 // Instruction chain rules are data-dependent on their inputs
1669 mach->add_req(0); // Set initial control to none
1670 ReduceInst_Chain_Rule( s, rule, mem, mach );
1671 }
1672
1673 // If a Memory was used, insert a Memory edge
1674 if( mem != (Node*)1 ) {
1675 mach->ins_req(MemNode::Memory,mem);
1676 #ifdef ASSERT
1677 // Verify adr type after matching memory operation
1678 const MachOper* oper = mach->memory_operand();
1679 if (oper != NULL && oper != (MachOper*)-1) {
1680 // It has a unique memory operand. Find corresponding ideal mem node.
1681 Node* m = NULL;
1682 if (leaf->is_Mem()) {
1683 m = leaf;
1684 } else {
1685 m = _mem_node;
1686 assert(m != NULL && m->is_Mem(), "expecting memory node");
1687 }
1688 const Type* mach_at = mach->adr_type();
1689 // DecodeN node consumed by an address may have different type
1690 // than its input. Don't compare types for such case.
1691 if (m->adr_type() != mach_at &&
1692 (m->in(MemNode::Address)->is_DecodeNarrowPtr() ||
1693 (m->in(MemNode::Address)->is_AddP() &&
1694 m->in(MemNode::Address)->in(AddPNode::Address)->is_DecodeNarrowPtr()) ||
1695 (m->in(MemNode::Address)->is_AddP() &&
1696 m->in(MemNode::Address)->in(AddPNode::Address)->is_AddP() &&
1697 m->in(MemNode::Address)->in(AddPNode::Address)->in(AddPNode::Address)->is_DecodeNarrowPtr()))) {
1698 mach_at = m->adr_type();
1699 }
1700 if (m->adr_type() != mach_at) {
1701 m->dump();
1702 tty->print_cr("mach:");
1703 mach->dump(1);
1704 }
1705 assert(m->adr_type() == mach_at, "matcher should not change adr type");
1706 }
1707 #endif
1708 }
1709
1710 // If the _leaf is an AddP, insert the base edge
1711 if (leaf->is_AddP()) {
1712 mach->ins_req(AddPNode::Base,leaf->in(AddPNode::Base));
1713 }
1714
1715 uint number_of_projections_prior = number_of_projections();
1716
1717 // Perform any 1-to-many expansions required
1718 MachNode *ex = mach->Expand(s, _projection_list, mem);
1719 if (ex != mach) {
1720 assert(ex->ideal_reg() == mach->ideal_reg(), "ideal types should match");
1721 if( ex->in(1)->is_Con() )
1722 ex->in(1)->set_req(0, C->root());
1723 // Remove old node from the graph
1724 for( uint i=0; i<mach->req(); i++ ) {
1725 mach->set_req(i,NULL);
1726 }
1727 #ifdef ASSERT
1728 _new2old_map.map(ex->_idx, s->_leaf);
1729 #endif
1730 }
1731
1732 // PhaseChaitin::fixup_spills will sometimes generate spill code
1733 // via the matcher. By the time, nodes have been wired into the CFG,
1734 // and any further nodes generated by expand rules will be left hanging
1735 // in space, and will not get emitted as output code. Catch this.
1736 // Also, catch any new register allocation constraints ("projections")
1737 // generated belatedly during spill code generation.
1738 if (_allocation_started) {
1739 guarantee(ex == mach, "no expand rules during spill generation");
1740 guarantee(number_of_projections_prior == number_of_projections(), "no allocation during spill generation");
1741 }
1742
1743 if (leaf->is_Con() || leaf->is_DecodeNarrowPtr()) {
1744 // Record the con for sharing
1745 _shared_nodes.map(leaf->_idx, ex);
1746 }
1747
1748 return ex;
1749 }
1750
1751 void Matcher::handle_precedence_edges(Node* n, MachNode *mach) {
1752 for (uint i = n->req(); i < n->len(); i++) {
1753 if (n->in(i) != NULL) {
1754 mach->add_prec(n->in(i));
1755 }
1756 }
1757 }
1758
1759 void Matcher::ReduceInst_Chain_Rule( State *s, int rule, Node *&mem, MachNode *mach ) {
1760 // 'op' is what I am expecting to receive
1761 int op = _leftOp[rule];
1762 // Operand type to catch childs result
1763 // This is what my child will give me.
1764 int opnd_class_instance = s->_rule[op];
1765 // Choose between operand class or not.
1766 // This is what I will receive.
1767 int catch_op = (FIRST_OPERAND_CLASS <= op && op < NUM_OPERANDS) ? opnd_class_instance : op;
1768 // New rule for child. Chase operand classes to get the actual rule.
1769 int newrule = s->_rule[catch_op];
1770
1771 if( newrule < NUM_OPERANDS ) {
1772 // Chain from operand or operand class, may be output of shared node
1773 assert( 0 <= opnd_class_instance && opnd_class_instance < NUM_OPERANDS,
1774 "Bad AD file: Instruction chain rule must chain from operand");
1775 // Insert operand into array of operands for this instruction
1776 mach->_opnds[1] = s->MachOperGenerator(opnd_class_instance);
1777
1778 ReduceOper( s, newrule, mem, mach );
1779 } else {
1780 // Chain from the result of an instruction
1781 assert( newrule >= _LAST_MACH_OPER, "Do NOT chain from internal operand");
1782 mach->_opnds[1] = s->MachOperGenerator(_reduceOp[catch_op]);
1783 Node *mem1 = (Node*)1;
1784 debug_only(Node *save_mem_node = _mem_node;)
1785 mach->add_req( ReduceInst(s, newrule, mem1) );
1786 debug_only(_mem_node = save_mem_node;)
1787 }
1788 return;
1789 }
1790
1791
1792 uint Matcher::ReduceInst_Interior( State *s, int rule, Node *&mem, MachNode *mach, uint num_opnds ) {
1793 handle_precedence_edges(s->_leaf, mach);
1794
1795 if( s->_leaf->is_Load() ) {
1796 Node *mem2 = s->_leaf->in(MemNode::Memory);
1797 assert( mem == (Node*)1 || mem == mem2, "multiple Memories being matched at once?" );
1798 debug_only( if( mem == (Node*)1 ) _mem_node = s->_leaf;)
1799 mem = mem2;
1800 }
1801 if( s->_leaf->in(0) != NULL && s->_leaf->req() > 1) {
1802 if( mach->in(0) == NULL )
1803 mach->set_req(0, s->_leaf->in(0));
1804 }
1805
1806 // Now recursively walk the state tree & add operand list.
1807 for( uint i=0; i<2; i++ ) { // binary tree
1808 State *newstate = s->_kids[i];
1809 if( newstate == NULL ) break; // Might only have 1 child
1810 // 'op' is what I am expecting to receive
1811 int op;
1812 if( i == 0 ) {
1813 op = _leftOp[rule];
1814 } else {
1815 op = _rightOp[rule];
1816 }
1817 // Operand type to catch childs result
1818 // This is what my child will give me.
1819 int opnd_class_instance = newstate->_rule[op];
1820 // Choose between operand class or not.
1821 // This is what I will receive.
1822 int catch_op = (op >= FIRST_OPERAND_CLASS && op < NUM_OPERANDS) ? opnd_class_instance : op;
1823 // New rule for child. Chase operand classes to get the actual rule.
1824 int newrule = newstate->_rule[catch_op];
1825
1826 if( newrule < NUM_OPERANDS ) { // Operand/operandClass or internalOp/instruction?
1827 // Operand/operandClass
1828 // Insert operand into array of operands for this instruction
1829 mach->_opnds[num_opnds++] = newstate->MachOperGenerator(opnd_class_instance);
1830 ReduceOper( newstate, newrule, mem, mach );
1831
1832 } else { // Child is internal operand or new instruction
1833 if( newrule < _LAST_MACH_OPER ) { // internal operand or instruction?
1834 // internal operand --> call ReduceInst_Interior
1835 // Interior of complex instruction. Do nothing but recurse.
1836 num_opnds = ReduceInst_Interior( newstate, newrule, mem, mach, num_opnds );
1837 } else {
1838 // instruction --> call build operand( ) to catch result
1839 // --> ReduceInst( newrule )
1840 mach->_opnds[num_opnds++] = s->MachOperGenerator(_reduceOp[catch_op]);
1841 Node *mem1 = (Node*)1;
1842 debug_only(Node *save_mem_node = _mem_node;)
1843 mach->add_req( ReduceInst( newstate, newrule, mem1 ) );
1844 debug_only(_mem_node = save_mem_node;)
1845 }
1846 }
1847 assert( mach->_opnds[num_opnds-1], "" );
1848 }
1849 return num_opnds;
1850 }
1851
1852 // This routine walks the interior of possible complex operands.
1853 // At each point we check our children in the match tree:
1854 // (1) No children -
1855 // We are a leaf; add _leaf field as an input to the MachNode
1856 // (2) Child is an internal operand -
1857 // Skip over it ( do nothing )
1858 // (3) Child is an instruction -
1859 // Call ReduceInst recursively and
1860 // and instruction as an input to the MachNode
1861 void Matcher::ReduceOper( State *s, int rule, Node *&mem, MachNode *mach ) {
1862 assert( rule < _LAST_MACH_OPER, "called with operand rule" );
1863 State *kid = s->_kids[0];
1864 assert( kid == NULL || s->_leaf->in(0) == NULL, "internal operands have no control" );
1865
1866 // Leaf? And not subsumed?
1867 if( kid == NULL && !_swallowed[rule] ) {
1868 mach->add_req( s->_leaf ); // Add leaf pointer
1869 return; // Bail out
1870 }
1871
1872 if( s->_leaf->is_Load() ) {
1873 assert( mem == (Node*)1, "multiple Memories being matched at once?" );
1874 mem = s->_leaf->in(MemNode::Memory);
1875 debug_only(_mem_node = s->_leaf;)
1876 }
1877
1878 handle_precedence_edges(s->_leaf, mach);
1879
1880 if( s->_leaf->in(0) && s->_leaf->req() > 1) {
1881 if( !mach->in(0) )
1882 mach->set_req(0,s->_leaf->in(0));
1883 else {
1884 assert( s->_leaf->in(0) == mach->in(0), "same instruction, differing controls?" );
1885 }
1886 }
1887
1888 for( uint i=0; kid != NULL && i<2; kid = s->_kids[1], i++ ) { // binary tree
1889 int newrule;
1890 if( i == 0)
1891 newrule = kid->_rule[_leftOp[rule]];
1892 else
1893 newrule = kid->_rule[_rightOp[rule]];
1894
1895 if( newrule < _LAST_MACH_OPER ) { // Operand or instruction?
1896 // Internal operand; recurse but do nothing else
1897 ReduceOper( kid, newrule, mem, mach );
1898
1899 } else { // Child is a new instruction
1900 // Reduce the instruction, and add a direct pointer from this
1901 // machine instruction to the newly reduced one.
1902 Node *mem1 = (Node*)1;
1903 debug_only(Node *save_mem_node = _mem_node;)
1904 mach->add_req( ReduceInst( kid, newrule, mem1 ) );
1905 debug_only(_mem_node = save_mem_node;)
1906 }
1907 }
1908 }
1909
1910
1911 // -------------------------------------------------------------------------
1912 // Java-Java calling convention
1913 // (what you use when Java calls Java)
1914
1915 //------------------------------find_receiver----------------------------------
1916 // For a given signature, return the OptoReg for parameter 0.
1917 OptoReg::Name Matcher::find_receiver( bool is_outgoing ) {
1918 VMRegPair regs;
1919 BasicType sig_bt = T_OBJECT;
1920 calling_convention(&sig_bt, ®s, 1, is_outgoing);
1921 // Return argument 0 register. In the LP64 build pointers
1922 // take 2 registers, but the VM wants only the 'main' name.
1923 return OptoReg::as_OptoReg(regs.first());
1924 }
1925
1926 // This function identifies sub-graphs in which a 'load' node is
1927 // input to two different nodes, and such that it can be matched
1928 // with BMI instructions like blsi, blsr, etc.
1929 // Example : for b = -a[i] & a[i] can be matched to blsi r32, m32.
1930 // The graph is (AndL (SubL Con0 LoadL*) LoadL*), where LoadL*
1931 // refers to the same node.
1932 #ifdef X86
1933 // Match the generic fused operations pattern (op1 (op2 Con{ConType} mop) mop)
1934 // This is a temporary solution until we make DAGs expressible in ADL.
1935 template<typename ConType>
1936 class FusedPatternMatcher {
1937 Node* _op1_node;
1938 Node* _mop_node;
1939 int _con_op;
1940
1941 static int match_next(Node* n, int next_op, int next_op_idx) {
1942 if (n->in(1) == NULL || n->in(2) == NULL) {
1943 return -1;
1944 }
1945
1946 if (next_op_idx == -1) { // n is commutative, try rotations
1947 if (n->in(1)->Opcode() == next_op) {
1948 return 1;
1949 } else if (n->in(2)->Opcode() == next_op) {
1950 return 2;
1951 }
1952 } else {
1953 assert(next_op_idx > 0 && next_op_idx <= 2, "Bad argument index");
1954 if (n->in(next_op_idx)->Opcode() == next_op) {
1955 return next_op_idx;
1956 }
1957 }
1958 return -1;
1959 }
1960 public:
1961 FusedPatternMatcher(Node* op1_node, Node *mop_node, int con_op) :
1962 _op1_node(op1_node), _mop_node(mop_node), _con_op(con_op) { }
1963
1964 bool match(int op1, int op1_op2_idx, // op1 and the index of the op1->op2 edge, -1 if op1 is commutative
1965 int op2, int op2_con_idx, // op2 and the index of the op2->con edge, -1 if op2 is commutative
1966 typename ConType::NativeType con_value) {
1967 if (_op1_node->Opcode() != op1) {
1968 return false;
1969 }
1970 if (_mop_node->outcnt() > 2) {
1971 return false;
1972 }
1973 op1_op2_idx = match_next(_op1_node, op2, op1_op2_idx);
1974 if (op1_op2_idx == -1) {
1975 return false;
1976 }
1977 // Memory operation must be the other edge
1978 int op1_mop_idx = (op1_op2_idx & 1) + 1;
1979
1980 // Check that the mop node is really what we want
1981 if (_op1_node->in(op1_mop_idx) == _mop_node) {
1982 Node *op2_node = _op1_node->in(op1_op2_idx);
1983 if (op2_node->outcnt() > 1) {
1984 return false;
1985 }
1986 assert(op2_node->Opcode() == op2, "Should be");
1987 op2_con_idx = match_next(op2_node, _con_op, op2_con_idx);
1988 if (op2_con_idx == -1) {
1989 return false;
1990 }
1991 // Memory operation must be the other edge
1992 int op2_mop_idx = (op2_con_idx & 1) + 1;
1993 // Check that the memory operation is the same node
1994 if (op2_node->in(op2_mop_idx) == _mop_node) {
1995 // Now check the constant
1996 const Type* con_type = op2_node->in(op2_con_idx)->bottom_type();
1997 if (con_type != Type::TOP && ConType::as_self(con_type)->get_con() == con_value) {
1998 return true;
1999 }
2000 }
2001 }
2002 return false;
2003 }
2004 };
2005
2006
2007 bool Matcher::is_bmi_pattern(Node *n, Node *m) {
2008 if (n != NULL && m != NULL) {
2009 if (m->Opcode() == Op_LoadI) {
2010 FusedPatternMatcher<TypeInt> bmii(n, m, Op_ConI);
2011 return bmii.match(Op_AndI, -1, Op_SubI, 1, 0) ||
2012 bmii.match(Op_AndI, -1, Op_AddI, -1, -1) ||
2013 bmii.match(Op_XorI, -1, Op_AddI, -1, -1);
2014 } else if (m->Opcode() == Op_LoadL) {
2015 FusedPatternMatcher<TypeLong> bmil(n, m, Op_ConL);
2016 return bmil.match(Op_AndL, -1, Op_SubL, 1, 0) ||
2017 bmil.match(Op_AndL, -1, Op_AddL, -1, -1) ||
2018 bmil.match(Op_XorL, -1, Op_AddL, -1, -1);
2019 }
2020 }
2021 return false;
2022 }
2023 #endif // X86
2024
2025 bool Matcher::clone_base_plus_offset_address(AddPNode* m, Matcher::MStack& mstack, VectorSet& address_visited) {
2026 Node *off = m->in(AddPNode::Offset);
2027 if (off->is_Con()) {
2028 address_visited.test_set(m->_idx); // Flag as address_visited
2029 mstack.push(m->in(AddPNode::Address), Pre_Visit);
2030 // Clone X+offset as it also folds into most addressing expressions
2031 mstack.push(off, Visit);
2032 mstack.push(m->in(AddPNode::Base), Pre_Visit);
2033 return true;
2034 }
2035 return false;
2036 }
2037
2038 // A method-klass-holder may be passed in the inline_cache_reg
2039 // and then expanded into the inline_cache_reg and a method_oop register
2040 // defined in ad_<arch>.cpp
2041
2042 //------------------------------find_shared------------------------------------
2043 // Set bits if Node is shared or otherwise a root
2044 void Matcher::find_shared( Node *n ) {
2045 // Allocate stack of size C->live_nodes() * 2 to avoid frequent realloc
2046 MStack mstack(C->live_nodes() * 2);
2047 // Mark nodes as address_visited if they are inputs to an address expression
2048 VectorSet address_visited(Thread::current()->resource_area());
2049 mstack.push(n, Visit); // Don't need to pre-visit root node
2050 while (mstack.is_nonempty()) {
2051 n = mstack.node(); // Leave node on stack
2052 Node_State nstate = mstack.state();
2053 uint nop = n->Opcode();
2054 if (nstate == Pre_Visit) {
2055 if (address_visited.test(n->_idx)) { // Visited in address already?
2056 // Flag as visited and shared now.
2057 set_visited(n);
2058 }
2059 if (is_visited(n)) { // Visited already?
2060 // Node is shared and has no reason to clone. Flag it as shared.
2061 // This causes it to match into a register for the sharing.
2062 set_shared(n); // Flag as shared and
2063 if (n->is_DecodeNarrowPtr()) {
2064 // Oop field/array element loads must be shared but since
2065 // they are shared through a DecodeN they may appear to have
2066 // a single use so force sharing here.
2067 set_shared(n->in(1));
2068 }
2069 mstack.pop(); // remove node from stack
2070 continue;
2071 }
2072 nstate = Visit; // Not already visited; so visit now
2073 }
2074 if (nstate == Visit) {
2075 mstack.set_state(Post_Visit);
2076 set_visited(n); // Flag as visited now
2077 bool mem_op = false;
2078 int mem_addr_idx = MemNode::Address;
2079
2080 switch( nop ) { // Handle some opcodes special
2081 case Op_Phi: // Treat Phis as shared roots
2082 case Op_Parm:
2083 case Op_Proj: // All handled specially during matching
2084 case Op_SafePointScalarObject:
2085 set_shared(n);
2086 set_dontcare(n);
2087 break;
2088 case Op_If:
2089 case Op_CountedLoopEnd:
2090 mstack.set_state(Alt_Post_Visit); // Alternative way
2091 // Convert (If (Bool (CmpX A B))) into (If (Bool) (CmpX A B)). Helps
2092 // with matching cmp/branch in 1 instruction. The Matcher needs the
2093 // Bool and CmpX side-by-side, because it can only get at constants
2094 // that are at the leaves of Match trees, and the Bool's condition acts
2095 // as a constant here.
2096 mstack.push(n->in(1), Visit); // Clone the Bool
2097 mstack.push(n->in(0), Pre_Visit); // Visit control input
2098 continue; // while (mstack.is_nonempty())
2099 case Op_ConvI2D: // These forms efficiently match with a prior
2100 case Op_ConvI2F: // Load but not a following Store
2101 if( n->in(1)->is_Load() && // Prior load
2102 n->outcnt() == 1 && // Not already shared
2103 n->unique_out()->is_Store() ) // Following store
2104 set_shared(n); // Force it to be a root
2105 break;
2106 case Op_ReverseBytesI:
2107 case Op_ReverseBytesL:
2108 if( n->in(1)->is_Load() && // Prior load
2109 n->outcnt() == 1 ) // Not already shared
2110 set_shared(n); // Force it to be a root
2111 break;
2112 case Op_BoxLock: // Cant match until we get stack-regs in ADLC
2113 case Op_IfFalse:
2114 case Op_IfTrue:
2115 case Op_MachProj:
2116 case Op_MergeMem:
2117 case Op_Catch:
2118 case Op_CatchProj:
2119 case Op_CProj:
2120 case Op_JumpProj:
2121 case Op_JProj:
2122 case Op_NeverBranch:
2123 set_dontcare(n);
2124 break;
2125 case Op_Jump:
2126 mstack.push(n->in(1), Pre_Visit); // Switch Value (could be shared)
2127 mstack.push(n->in(0), Pre_Visit); // Visit Control input
2128 continue; // while (mstack.is_nonempty())
2129 case Op_StrComp:
2130 case Op_StrEquals:
2131 case Op_StrIndexOf:
2132 case Op_StrIndexOfChar:
2133 case Op_AryEq:
2134 case Op_HasNegatives:
2135 case Op_StrInflatedCopy:
2136 case Op_StrCompressedCopy:
2137 case Op_EncodeISOArray:
2138 case Op_FmaD:
2139 case Op_FmaF:
2140 case Op_FmaVD:
2141 case Op_FmaVF:
2142 set_shared(n); // Force result into register (it will be anyways)
2143 break;
2144 case Op_ConP: { // Convert pointers above the centerline to NUL
2145 TypeNode *tn = n->as_Type(); // Constants derive from type nodes
2146 const TypePtr* tp = tn->type()->is_ptr();
2147 if (tp->_ptr == TypePtr::AnyNull) {
2148 tn->set_type(TypePtr::NULL_PTR);
2149 }
2150 break;
2151 }
2152 case Op_ConN: { // Convert narrow pointers above the centerline to NUL
2153 TypeNode *tn = n->as_Type(); // Constants derive from type nodes
2154 const TypePtr* tp = tn->type()->make_ptr();
2155 if (tp && tp->_ptr == TypePtr::AnyNull) {
2156 tn->set_type(TypeNarrowOop::NULL_PTR);
2157 }
2158 break;
2159 }
2160 case Op_Binary: // These are introduced in the Post_Visit state.
2161 ShouldNotReachHere();
2162 break;
2163 case Op_ClearArray:
2164 case Op_SafePoint:
2165 mem_op = true;
2166 break;
2167 #if INCLUDE_ZGC
2168 case Op_CallLeaf:
2169 if (UseZGC) {
2170 if (n->as_Call()->entry_point() == ZBarrierSetRuntime::load_barrier_on_oop_field_preloaded_addr() ||
2171 n->as_Call()->entry_point() == ZBarrierSetRuntime::load_barrier_on_weak_oop_field_preloaded_addr()) {
2172 mem_op = true;
2173 mem_addr_idx = TypeFunc::Parms+1;
2174 }
2175 break;
2176 }
2177 #endif
2178 default:
2179 if( n->is_Store() ) {
2180 // Do match stores, despite no ideal reg
2181 mem_op = true;
2182 break;
2183 }
2184 if( n->is_Mem() ) { // Loads and LoadStores
2185 mem_op = true;
2186 // Loads must be root of match tree due to prior load conflict
2187 if( C->subsume_loads() == false )
2188 set_shared(n);
2189 }
2190 // Fall into default case
2191 if( !n->ideal_reg() )
2192 set_dontcare(n); // Unmatchable Nodes
2193 } // end_switch
2194
2195 for(int i = n->req() - 1; i >= 0; --i) { // For my children
2196 Node *m = n->in(i); // Get ith input
2197 if (m == NULL) continue; // Ignore NULLs
2198 uint mop = m->Opcode();
2199
2200 // Must clone all producers of flags, or we will not match correctly.
2201 // Suppose a compare setting int-flags is shared (e.g., a switch-tree)
2202 // then it will match into an ideal Op_RegFlags. Alas, the fp-flags
2203 // are also there, so we may match a float-branch to int-flags and
2204 // expect the allocator to haul the flags from the int-side to the
2205 // fp-side. No can do.
2206 if( _must_clone[mop] ) {
2207 mstack.push(m, Visit);
2208 continue; // for(int i = ...)
2209 }
2210
2211 // if 'n' and 'm' are part of a graph for BMI instruction, clone this node.
2212 #ifdef X86
2213 if (UseBMI1Instructions && is_bmi_pattern(n, m)) {
2214 mstack.push(m, Visit);
2215 continue;
2216 }
2217 #endif
2218
2219 // Clone addressing expressions as they are "free" in memory access instructions
2220 if (mem_op && i == mem_addr_idx && mop == Op_AddP &&
2221 // When there are other uses besides address expressions
2222 // put it on stack and mark as shared.
2223 !is_visited(m)) {
2224 // Some inputs for address expression are not put on stack
2225 // to avoid marking them as shared and forcing them into register
2226 // if they are used only in address expressions.
2227 // But they should be marked as shared if there are other uses
2228 // besides address expressions.
2229
2230 if (clone_address_expressions(m->as_AddP(), mstack, address_visited)) {
2231 continue;
2232 }
2233 } // if( mem_op &&
2234 mstack.push(m, Pre_Visit);
2235 } // for(int i = ...)
2236 }
2237 else if (nstate == Alt_Post_Visit) {
2238 mstack.pop(); // Remove node from stack
2239 // We cannot remove the Cmp input from the Bool here, as the Bool may be
2240 // shared and all users of the Bool need to move the Cmp in parallel.
2241 // This leaves both the Bool and the If pointing at the Cmp. To
2242 // prevent the Matcher from trying to Match the Cmp along both paths
2243 // BoolNode::match_edge always returns a zero.
2244
2245 // We reorder the Op_If in a pre-order manner, so we can visit without
2246 // accidentally sharing the Cmp (the Bool and the If make 2 users).
2247 n->add_req( n->in(1)->in(1) ); // Add the Cmp next to the Bool
2248 }
2249 else if (nstate == Post_Visit) {
2250 mstack.pop(); // Remove node from stack
2251
2252 // Now hack a few special opcodes
2253 switch( n->Opcode() ) { // Handle some opcodes special
2254 case Op_StorePConditional:
2255 case Op_StoreIConditional:
2256 case Op_StoreLConditional:
2257 case Op_CompareAndExchangeB:
2258 case Op_CompareAndExchangeS:
2259 case Op_CompareAndExchangeI:
2260 case Op_CompareAndExchangeL:
2261 case Op_CompareAndExchangeP:
2262 case Op_CompareAndExchangeN:
2263 case Op_WeakCompareAndSwapB:
2264 case Op_WeakCompareAndSwapS:
2265 case Op_WeakCompareAndSwapI:
2266 case Op_WeakCompareAndSwapL:
2267 case Op_WeakCompareAndSwapP:
2268 case Op_WeakCompareAndSwapN:
2269 case Op_CompareAndSwapB:
2270 case Op_CompareAndSwapS:
2271 case Op_CompareAndSwapI:
2272 case Op_CompareAndSwapL:
2273 case Op_CompareAndSwapP:
2274 case Op_CompareAndSwapN: { // Convert trinary to binary-tree
2275 Node *newval = n->in(MemNode::ValueIn );
2276 Node *oldval = n->in(LoadStoreConditionalNode::ExpectedIn);
2277 Node *pair = new BinaryNode( oldval, newval );
2278 n->set_req(MemNode::ValueIn,pair);
2279 n->del_req(LoadStoreConditionalNode::ExpectedIn);
2280 break;
2281 }
2282 case Op_CMoveD: // Convert trinary to binary-tree
2283 case Op_CMoveF:
2284 case Op_CMoveI:
2285 case Op_CMoveL:
2286 case Op_CMoveN:
2287 case Op_CMoveP:
2288 case Op_CMoveVF:
2289 case Op_CMoveVD: {
2290 // Restructure into a binary tree for Matching. It's possible that
2291 // we could move this code up next to the graph reshaping for IfNodes
2292 // or vice-versa, but I do not want to debug this for Ladybird.
2293 // 10/2/2000 CNC.
2294 Node *pair1 = new BinaryNode(n->in(1),n->in(1)->in(1));
2295 n->set_req(1,pair1);
2296 Node *pair2 = new BinaryNode(n->in(2),n->in(3));
2297 n->set_req(2,pair2);
2298 n->del_req(3);
2299 break;
2300 }
2301 case Op_LoopLimit: {
2302 Node *pair1 = new BinaryNode(n->in(1),n->in(2));
2303 n->set_req(1,pair1);
2304 n->set_req(2,n->in(3));
2305 n->del_req(3);
2306 break;
2307 }
2308 case Op_StrEquals:
2309 case Op_StrIndexOfChar: {
2310 Node *pair1 = new BinaryNode(n->in(2),n->in(3));
2311 n->set_req(2,pair1);
2312 n->set_req(3,n->in(4));
2313 n->del_req(4);
2314 break;
2315 }
2316 case Op_StrComp:
2317 case Op_StrIndexOf: {
2318 Node *pair1 = new BinaryNode(n->in(2),n->in(3));
2319 n->set_req(2,pair1);
2320 Node *pair2 = new BinaryNode(n->in(4),n->in(5));
2321 n->set_req(3,pair2);
2322 n->del_req(5);
2323 n->del_req(4);
2324 break;
2325 }
2326 case Op_StrCompressedCopy:
2327 case Op_StrInflatedCopy:
2328 case Op_EncodeISOArray: {
2329 // Restructure into a binary tree for Matching.
2330 Node* pair = new BinaryNode(n->in(3), n->in(4));
2331 n->set_req(3, pair);
2332 n->del_req(4);
2333 break;
2334 }
2335 case Op_FmaD:
2336 case Op_FmaF:
2337 case Op_FmaVD:
2338 case Op_FmaVF: {
2339 // Restructure into a binary tree for Matching.
2340 Node* pair = new BinaryNode(n->in(1), n->in(2));
2341 n->set_req(2, pair);
2342 n->set_req(1, n->in(3));
2343 n->del_req(3);
2344 break;
2345 }
2346 default:
2347 break;
2348 }
2349 }
2350 else {
2351 ShouldNotReachHere();
2352 }
2353 } // end of while (mstack.is_nonempty())
2354 }
2355
2356 #ifdef ASSERT
2357 // machine-independent root to machine-dependent root
2358 void Matcher::dump_old2new_map() {
2359 _old2new_map.dump();
2360 }
2361 #endif
2362
2363 //---------------------------collect_null_checks-------------------------------
2364 // Find null checks in the ideal graph; write a machine-specific node for
2365 // it. Used by later implicit-null-check handling. Actually collects
2366 // either an IfTrue or IfFalse for the common NOT-null path, AND the ideal
2367 // value being tested.
2368 void Matcher::collect_null_checks( Node *proj, Node *orig_proj ) {
2369 Node *iff = proj->in(0);
2370 if( iff->Opcode() == Op_If ) {
2371 // During matching If's have Bool & Cmp side-by-side
2372 BoolNode *b = iff->in(1)->as_Bool();
2373 Node *cmp = iff->in(2);
2374 int opc = cmp->Opcode();
2375 if (opc != Op_CmpP && opc != Op_CmpN) return;
2376
2377 const Type* ct = cmp->in(2)->bottom_type();
2378 if (ct == TypePtr::NULL_PTR ||
2379 (opc == Op_CmpN && ct == TypeNarrowOop::NULL_PTR)) {
2380
2381 bool push_it = false;
2382 if( proj->Opcode() == Op_IfTrue ) {
2383 #ifndef PRODUCT
2384 extern int all_null_checks_found;
2385 all_null_checks_found++;
2386 #endif
2387 if( b->_test._test == BoolTest::ne ) {
2388 push_it = true;
2389 }
2390 } else {
2391 assert( proj->Opcode() == Op_IfFalse, "" );
2392 if( b->_test._test == BoolTest::eq ) {
2393 push_it = true;
2394 }
2395 }
2396 if( push_it ) {
2397 _null_check_tests.push(proj);
2398 Node* val = cmp->in(1);
2399 #ifdef _LP64
2400 if (val->bottom_type()->isa_narrowoop() &&
2401 !Matcher::narrow_oop_use_complex_address()) {
2402 //
2403 // Look for DecodeN node which should be pinned to orig_proj.
2404 // On platforms (Sparc) which can not handle 2 adds
2405 // in addressing mode we have to keep a DecodeN node and
2406 // use it to do implicit NULL check in address.
2407 //
2408 // DecodeN node was pinned to non-null path (orig_proj) during
2409 // CastPP transformation in final_graph_reshaping_impl().
2410 //
2411 uint cnt = orig_proj->outcnt();
2412 for (uint i = 0; i < orig_proj->outcnt(); i++) {
2413 Node* d = orig_proj->raw_out(i);
2414 if (d->is_DecodeN() && d->in(1) == val) {
2415 val = d;
2416 val->set_req(0, NULL); // Unpin now.
2417 // Mark this as special case to distinguish from
2418 // a regular case: CmpP(DecodeN, NULL).
2419 val = (Node*)(((intptr_t)val) | 1);
2420 break;
2421 }
2422 }
2423 }
2424 #endif
2425 _null_check_tests.push(val);
2426 }
2427 }
2428 }
2429 }
2430
2431 //---------------------------validate_null_checks------------------------------
2432 // Its possible that the value being NULL checked is not the root of a match
2433 // tree. If so, I cannot use the value in an implicit null check.
2434 void Matcher::validate_null_checks( ) {
2435 uint cnt = _null_check_tests.size();
2436 for( uint i=0; i < cnt; i+=2 ) {
2437 Node *test = _null_check_tests[i];
2438 Node *val = _null_check_tests[i+1];
2439 bool is_decoden = ((intptr_t)val) & 1;
2440 val = (Node*)(((intptr_t)val) & ~1);
2441 if (has_new_node(val)) {
2442 Node* new_val = new_node(val);
2443 if (is_decoden) {
2444 assert(val->is_DecodeNarrowPtr() && val->in(0) == NULL, "sanity");
2445 // Note: new_val may have a control edge if
2446 // the original ideal node DecodeN was matched before
2447 // it was unpinned in Matcher::collect_null_checks().
2448 // Unpin the mach node and mark it.
2449 new_val->set_req(0, NULL);
2450 new_val = (Node*)(((intptr_t)new_val) | 1);
2451 }
2452 // Is a match-tree root, so replace with the matched value
2453 _null_check_tests.map(i+1, new_val);
2454 } else {
2455 // Yank from candidate list
2456 _null_check_tests.map(i+1,_null_check_tests[--cnt]);
2457 _null_check_tests.map(i,_null_check_tests[--cnt]);
2458 _null_check_tests.pop();
2459 _null_check_tests.pop();
2460 i-=2;
2461 }
2462 }
2463 }
2464
2465 // Used by the DFA in dfa_xxx.cpp. Check for a following barrier or
2466 // atomic instruction acting as a store_load barrier without any
2467 // intervening volatile load, and thus we don't need a barrier here.
2468 // We retain the Node to act as a compiler ordering barrier.
2469 bool Matcher::post_store_load_barrier(const Node* vmb) {
2470 Compile* C = Compile::current();
2471 assert(vmb->is_MemBar(), "");
2472 assert(vmb->Opcode() != Op_MemBarAcquire && vmb->Opcode() != Op_LoadFence, "");
2473 const MemBarNode* membar = vmb->as_MemBar();
2474
2475 // Get the Ideal Proj node, ctrl, that can be used to iterate forward
2476 Node* ctrl = NULL;
2477 for (DUIterator_Fast imax, i = membar->fast_outs(imax); i < imax; i++) {
2478 Node* p = membar->fast_out(i);
2479 assert(p->is_Proj(), "only projections here");
2480 if ((p->as_Proj()->_con == TypeFunc::Control) &&
2481 !C->node_arena()->contains(p)) { // Unmatched old-space only
2482 ctrl = p;
2483 break;
2484 }
2485 }
2486 assert((ctrl != NULL), "missing control projection");
2487
2488 for (DUIterator_Fast jmax, j = ctrl->fast_outs(jmax); j < jmax; j++) {
2489 Node *x = ctrl->fast_out(j);
2490 int xop = x->Opcode();
2491
2492 // We don't need current barrier if we see another or a lock
2493 // before seeing volatile load.
2494 //
2495 // Op_Fastunlock previously appeared in the Op_* list below.
2496 // With the advent of 1-0 lock operations we're no longer guaranteed
2497 // that a monitor exit operation contains a serializing instruction.
2498
2499 if (xop == Op_MemBarVolatile ||
2500 xop == Op_CompareAndExchangeB ||
2501 xop == Op_CompareAndExchangeS ||
2502 xop == Op_CompareAndExchangeI ||
2503 xop == Op_CompareAndExchangeL ||
2504 xop == Op_CompareAndExchangeP ||
2505 xop == Op_CompareAndExchangeN ||
2506 xop == Op_WeakCompareAndSwapB ||
2507 xop == Op_WeakCompareAndSwapS ||
2508 xop == Op_WeakCompareAndSwapL ||
2509 xop == Op_WeakCompareAndSwapP ||
2510 xop == Op_WeakCompareAndSwapN ||
2511 xop == Op_WeakCompareAndSwapI ||
2512 xop == Op_CompareAndSwapB ||
2513 xop == Op_CompareAndSwapS ||
2514 xop == Op_CompareAndSwapL ||
2515 xop == Op_CompareAndSwapP ||
2516 xop == Op_CompareAndSwapN ||
2517 xop == Op_CompareAndSwapI) {
2518 return true;
2519 }
2520
2521 // Op_FastLock previously appeared in the Op_* list above.
2522 // With biased locking we're no longer guaranteed that a monitor
2523 // enter operation contains a serializing instruction.
2524 if ((xop == Op_FastLock) && !UseBiasedLocking) {
2525 return true;
2526 }
2527
2528 if (x->is_MemBar()) {
2529 // We must retain this membar if there is an upcoming volatile
2530 // load, which will be followed by acquire membar.
2531 if (xop == Op_MemBarAcquire || xop == Op_LoadFence) {
2532 return false;
2533 } else {
2534 // For other kinds of barriers, check by pretending we
2535 // are them, and seeing if we can be removed.
2536 return post_store_load_barrier(x->as_MemBar());
2537 }
2538 }
2539
2540 // probably not necessary to check for these
2541 if (x->is_Call() || x->is_SafePoint() || x->is_block_proj()) {
2542 return false;
2543 }
2544 }
2545 return false;
2546 }
2547
2548 // Check whether node n is a branch to an uncommon trap that we could
2549 // optimize as test with very high branch costs in case of going to
2550 // the uncommon trap. The code must be able to be recompiled to use
2551 // a cheaper test.
2552 bool Matcher::branches_to_uncommon_trap(const Node *n) {
2553 // Don't do it for natives, adapters, or runtime stubs
2554 Compile *C = Compile::current();
2555 if (!C->is_method_compilation()) return false;
2556
2557 assert(n->is_If(), "You should only call this on if nodes.");
2558 IfNode *ifn = n->as_If();
2559
2560 Node *ifFalse = NULL;
2561 for (DUIterator_Fast imax, i = ifn->fast_outs(imax); i < imax; i++) {
2562 if (ifn->fast_out(i)->is_IfFalse()) {
2563 ifFalse = ifn->fast_out(i);
2564 break;
2565 }
2566 }
2567 assert(ifFalse, "An If should have an ifFalse. Graph is broken.");
2568
2569 Node *reg = ifFalse;
2570 int cnt = 4; // We must protect against cycles. Limit to 4 iterations.
2571 // Alternatively use visited set? Seems too expensive.
2572 while (reg != NULL && cnt > 0) {
2573 CallNode *call = NULL;
2574 RegionNode *nxt_reg = NULL;
2575 for (DUIterator_Fast imax, i = reg->fast_outs(imax); i < imax; i++) {
2576 Node *o = reg->fast_out(i);
2577 if (o->is_Call()) {
2578 call = o->as_Call();
2579 }
2580 if (o->is_Region()) {
2581 nxt_reg = o->as_Region();
2582 }
2583 }
2584
2585 if (call &&
2586 call->entry_point() == SharedRuntime::uncommon_trap_blob()->entry_point()) {
2587 const Type* trtype = call->in(TypeFunc::Parms)->bottom_type();
2588 if (trtype->isa_int() && trtype->is_int()->is_con()) {
2589 jint tr_con = trtype->is_int()->get_con();
2590 Deoptimization::DeoptReason reason = Deoptimization::trap_request_reason(tr_con);
2591 Deoptimization::DeoptAction action = Deoptimization::trap_request_action(tr_con);
2592 assert((int)reason < (int)BitsPerInt, "recode bit map");
2593
2594 if (is_set_nth_bit(C->allowed_deopt_reasons(), (int)reason)
2595 && action != Deoptimization::Action_none) {
2596 // This uncommon trap is sure to recompile, eventually.
2597 // When that happens, C->too_many_traps will prevent
2598 // this transformation from happening again.
2599 return true;
2600 }
2601 }
2602 }
2603
2604 reg = nxt_reg;
2605 cnt--;
2606 }
2607
2608 return false;
2609 }
2610
2611 //=============================================================================
2612 //---------------------------State---------------------------------------------
2613 State::State(void) {
2614 #ifdef ASSERT
2615 _id = 0;
2616 _kids[0] = _kids[1] = (State*)(intptr_t) CONST64(0xcafebabecafebabe);
2617 _leaf = (Node*)(intptr_t) CONST64(0xbaadf00dbaadf00d);
2618 //memset(_cost, -1, sizeof(_cost));
2619 //memset(_rule, -1, sizeof(_rule));
2620 #endif
2621 memset(_valid, 0, sizeof(_valid));
2622 }
2623
2624 #ifdef ASSERT
2625 State::~State() {
2626 _id = 99;
2627 _kids[0] = _kids[1] = (State*)(intptr_t) CONST64(0xcafebabecafebabe);
2628 _leaf = (Node*)(intptr_t) CONST64(0xbaadf00dbaadf00d);
2629 memset(_cost, -3, sizeof(_cost));
2630 memset(_rule, -3, sizeof(_rule));
2631 }
2632 #endif
2633
2634 #ifndef PRODUCT
2635 //---------------------------dump----------------------------------------------
2636 void State::dump() {
2637 tty->print("\n");
2638 dump(0);
2639 }
2640
2641 void State::dump(int depth) {
2642 for( int j = 0; j < depth; j++ )
2643 tty->print(" ");
2644 tty->print("--N: ");
2645 _leaf->dump();
2646 uint i;
2647 for( i = 0; i < _LAST_MACH_OPER; i++ )
2648 // Check for valid entry
2649 if( valid(i) ) {
2650 for( int j = 0; j < depth; j++ )
2651 tty->print(" ");
2652 assert(_cost[i] != max_juint, "cost must be a valid value");
2653 assert(_rule[i] < _last_Mach_Node, "rule[i] must be valid rule");
2654 tty->print_cr("%s %d %s",
2655 ruleName[i], _cost[i], ruleName[_rule[i]] );
2656 }
2657 tty->cr();
2658
2659 for( i=0; i<2; i++ )
2660 if( _kids[i] )
2661 _kids[i]->dump(depth+1);
2662 }
2663 #endif