src/hotspot/cpu/x86/c1_LIRGenerator_x86.cpp

rev 52710 : Upstream/backport Shenandoah to JDK11u

@@ -34,10 +34,11 @@
 #include "ci/ciObjArrayKlass.hpp"
 #include "ci/ciTypeArrayKlass.hpp"
 #include "gc/shared/c1/barrierSetC1.hpp"
 #include "runtime/sharedRuntime.hpp"
 #include "runtime/stubRoutines.hpp"
+#include "utilities/macros.hpp"
 #include "vmreg_x86.inline.hpp"
 
 #ifdef ASSERT
 #define __ gen()->lir(__FILE__, __LINE__)->
 #else

@@ -672,10 +673,15 @@
 LIR_Opr LIRGenerator::atomic_cmpxchg(BasicType type, LIR_Opr addr, LIRItem& cmp_value, LIRItem& new_value) {
   LIR_Opr ill = LIR_OprFact::illegalOpr;  // for convenience
   if (type == T_OBJECT || type == T_ARRAY) {
     cmp_value.load_item_force(FrameMap::rax_oop_opr);
     new_value.load_item();
+#if INCLUDE_SHENANDOAHGC
+    if (UseShenandoahGC) {
+      __ cas_obj(addr->as_address_ptr()->base(), cmp_value.result(), new_value.result(), new_register(T_OBJECT), new_register(T_OBJECT));
+    } else
+#endif
     __ cas_obj(addr->as_address_ptr()->base(), cmp_value.result(), new_value.result(), ill, ill);
   } else if (type == T_INT) {
     cmp_value.load_item_force(FrameMap::rax_opr);
     new_value.load_item();
     __ cas_int(addr->as_address_ptr()->base(), cmp_value.result(), new_value.result(), ill, ill);

@@ -697,10 +703,16 @@
   LIR_Opr result = new_register(type);
   value.load_item();
   // Because we want a 2-arg form of xchg and xadd
   __ move(value.result(), result);
   assert(type == T_INT || is_oop LP64_ONLY( || type == T_LONG ), "unexpected type");
+#if INCLUDE_SHENANDOAHGC
+  if (UseShenandoahGC) {
+    LIR_Opr tmp = is_oop ? new_register(type) : LIR_OprFact::illegalOpr;
+    __ xchg(addr, result, result, tmp);
+  } else
+#endif
   __ xchg(addr, result, result, LIR_OprFact::illegalOpr);
   return result;
 }
 
 LIR_Opr LIRGenerator::atomic_add(BasicType type, LIR_Opr addr, LIRItem& value) {