1 /*
2 * Copyright (c) 2000, 2011, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "c1/c1_Compilation.hpp"
27 #include "c1/c1_LIRAssembler.hpp"
28 #include "c1/c1_MacroAssembler.hpp"
29 #include "c1/c1_Runtime1.hpp"
30 #include "c1/c1_ValueStack.hpp"
31 #include "ci/ciArrayKlass.hpp"
32 #include "ci/ciInstance.hpp"
33 #include "gc_interface/collectedHeap.hpp"
34 #include "memory/barrierSet.hpp"
35 #include "memory/cardTableModRefBS.hpp"
36 #include "nativeInst_sparc.hpp"
37 #include "oops/objArrayKlass.hpp"
38 #include "runtime/sharedRuntime.hpp"
39
40 #define __ _masm->
41
42
43 //------------------------------------------------------------
44
45
46 bool LIR_Assembler::is_small_constant(LIR_Opr opr) {
47 if (opr->is_constant()) {
48 LIR_Const* constant = opr->as_constant_ptr();
49 switch (constant->type()) {
50 case T_INT: {
51 jint value = constant->as_jint();
52 return Assembler::is_simm13(value);
53 }
54
55 default:
56 return false;
57 }
58 }
59 return false;
60 }
61
62
63 bool LIR_Assembler::is_single_instruction(LIR_Op* op) {
64 switch (op->code()) {
65 case lir_null_check:
66 return true;
67
68
69 case lir_add:
70 case lir_ushr:
71 case lir_shr:
72 case lir_shl:
73 // integer shifts and adds are always one instruction
74 return op->result_opr()->is_single_cpu();
75
76
77 case lir_move: {
78 LIR_Op1* op1 = op->as_Op1();
79 LIR_Opr src = op1->in_opr();
80 LIR_Opr dst = op1->result_opr();
81
82 if (src == dst) {
83 NEEDS_CLEANUP;
84 // this works around a problem where moves with the same src and dst
85 // end up in the delay slot and then the assembler swallows the mov
86 // since it has no effect and then it complains because the delay slot
87 // is empty. returning false stops the optimizer from putting this in
88 // the delay slot
89 return false;
90 }
91
92 // don't put moves involving oops into the delay slot since the VerifyOops code
93 // will make it much larger than a single instruction.
94 if (VerifyOops) {
95 return false;
96 }
97
98 if (src->is_double_cpu() || dst->is_double_cpu() || op1->patch_code() != lir_patch_none ||
99 ((src->is_double_fpu() || dst->is_double_fpu()) && op1->move_kind() != lir_move_normal)) {
100 return false;
101 }
102
103 if (UseCompressedOops) {
104 if (dst->is_address() && !dst->is_stack() && (dst->type() == T_OBJECT || dst->type() == T_ARRAY)) return false;
105 if (src->is_address() && !src->is_stack() && (src->type() == T_OBJECT || src->type() == T_ARRAY)) return false;
106 }
107
108 if (dst->is_register()) {
109 if (src->is_address() && Assembler::is_simm13(src->as_address_ptr()->disp())) {
110 return !PatchALot;
111 } else if (src->is_single_stack()) {
112 return true;
113 }
114 }
115
116 if (src->is_register()) {
117 if (dst->is_address() && Assembler::is_simm13(dst->as_address_ptr()->disp())) {
118 return !PatchALot;
119 } else if (dst->is_single_stack()) {
120 return true;
121 }
122 }
123
124 if (dst->is_register() &&
125 ((src->is_register() && src->is_single_word() && src->is_same_type(dst)) ||
126 (src->is_constant() && LIR_Assembler::is_small_constant(op->as_Op1()->in_opr())))) {
127 return true;
128 }
129
130 return false;
131 }
132
133 default:
134 return false;
135 }
136 ShouldNotReachHere();
137 }
138
139
140 LIR_Opr LIR_Assembler::receiverOpr() {
141 return FrameMap::O0_oop_opr;
142 }
143
144
145 LIR_Opr LIR_Assembler::osrBufferPointer() {
146 return FrameMap::I0_opr;
147 }
148
149
150 int LIR_Assembler::initial_frame_size_in_bytes() {
151 return in_bytes(frame_map()->framesize_in_bytes());
152 }
153
154
155 // inline cache check: the inline cached class is in G5_inline_cache_reg(G5);
156 // we fetch the class of the receiver (O0) and compare it with the cached class.
157 // If they do not match we jump to slow case.
158 int LIR_Assembler::check_icache() {
159 int offset = __ offset();
160 __ inline_cache_check(O0, G5_inline_cache_reg);
161 return offset;
162 }
163
164
165 void LIR_Assembler::osr_entry() {
166 // On-stack-replacement entry sequence (interpreter frame layout described in interpreter_sparc.cpp):
167 //
168 // 1. Create a new compiled activation.
169 // 2. Initialize local variables in the compiled activation. The expression stack must be empty
170 // at the osr_bci; it is not initialized.
171 // 3. Jump to the continuation address in compiled code to resume execution.
172
173 // OSR entry point
174 offsets()->set_value(CodeOffsets::OSR_Entry, code_offset());
175 BlockBegin* osr_entry = compilation()->hir()->osr_entry();
176 ValueStack* entry_state = osr_entry->end()->state();
177 int number_of_locks = entry_state->locks_size();
178
179 // Create a frame for the compiled activation.
180 __ build_frame(initial_frame_size_in_bytes());
181
182 // OSR buffer is
183 //
184 // locals[nlocals-1..0]
185 // monitors[number_of_locks-1..0]
186 //
187 // locals is a direct copy of the interpreter frame so in the osr buffer
188 // so first slot in the local array is the last local from the interpreter
189 // and last slot is local[0] (receiver) from the interpreter
190 //
191 // Similarly with locks. The first lock slot in the osr buffer is the nth lock
192 // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock
193 // in the interpreter frame (the method lock if a sync method)
194
195 // Initialize monitors in the compiled activation.
196 // I0: pointer to osr buffer
197 //
198 // All other registers are dead at this point and the locals will be
199 // copied into place by code emitted in the IR.
200
201 Register OSR_buf = osrBufferPointer()->as_register();
202 { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");
203 int monitor_offset = BytesPerWord * method()->max_locals() +
204 (2 * BytesPerWord) * (number_of_locks - 1);
205 // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in
206 // the OSR buffer using 2 word entries: first the lock and then
207 // the oop.
208 for (int i = 0; i < number_of_locks; i++) {
209 int slot_offset = monitor_offset - ((i * 2) * BytesPerWord);
210 #ifdef ASSERT
211 // verify the interpreter's monitor has a non-null object
212 {
213 Label L;
214 __ ld_ptr(OSR_buf, slot_offset + 1*BytesPerWord, O7);
215 __ cmp_and_br_short(O7, G0, Assembler::notEqual, Assembler::pt, L);
216 __ stop("locked object is NULL");
217 __ bind(L);
218 }
219 #endif // ASSERT
220 // Copy the lock field into the compiled activation.
221 __ ld_ptr(OSR_buf, slot_offset + 0, O7);
222 __ st_ptr(O7, frame_map()->address_for_monitor_lock(i));
223 __ ld_ptr(OSR_buf, slot_offset + 1*BytesPerWord, O7);
224 __ st_ptr(O7, frame_map()->address_for_monitor_object(i));
225 }
226 }
227 }
228
229
230 // Optimized Library calls
231 // This is the fast version of java.lang.String.compare; it has not
232 // OSR-entry and therefore, we generate a slow version for OSR's
233 void LIR_Assembler::emit_string_compare(LIR_Opr left, LIR_Opr right, LIR_Opr dst, CodeEmitInfo* info) {
234 Register str0 = left->as_register();
235 Register str1 = right->as_register();
236
237 Label Ldone;
238
239 Register result = dst->as_register();
240 {
241 // Get a pointer to the first character of string0 in tmp0 and get string0.count in str0
242 // Get a pointer to the first character of string1 in tmp1 and get string1.count in str1
243 // Also, get string0.count-string1.count in o7 and get the condition code set
244 // Note: some instructions have been hoisted for better instruction scheduling
245
246 Register tmp0 = L0;
247 Register tmp1 = L1;
248 Register tmp2 = L2;
249
250 int value_offset = java_lang_String:: value_offset_in_bytes(); // char array
251 int offset_offset = java_lang_String::offset_offset_in_bytes(); // first character position
252 int count_offset = java_lang_String:: count_offset_in_bytes();
253
254 __ load_heap_oop(str0, value_offset, tmp0);
255 __ ld(str0, offset_offset, tmp2);
256 __ add(tmp0, arrayOopDesc::base_offset_in_bytes(T_CHAR), tmp0);
257 __ ld(str0, count_offset, str0);
258 __ sll(tmp2, exact_log2(sizeof(jchar)), tmp2);
259
260 // str1 may be null
261 add_debug_info_for_null_check_here(info);
262
263 __ load_heap_oop(str1, value_offset, tmp1);
264 __ add(tmp0, tmp2, tmp0);
265
266 __ ld(str1, offset_offset, tmp2);
267 __ add(tmp1, arrayOopDesc::base_offset_in_bytes(T_CHAR), tmp1);
268 __ ld(str1, count_offset, str1);
269 __ sll(tmp2, exact_log2(sizeof(jchar)), tmp2);
270 __ subcc(str0, str1, O7);
271 __ add(tmp1, tmp2, tmp1);
272 }
273
274 {
275 // Compute the minimum of the string lengths, scale it and store it in limit
276 Register count0 = I0;
277 Register count1 = I1;
278 Register limit = L3;
279
280 Label Lskip;
281 __ sll(count0, exact_log2(sizeof(jchar)), limit); // string0 is shorter
282 __ br(Assembler::greater, true, Assembler::pt, Lskip);
283 __ delayed()->sll(count1, exact_log2(sizeof(jchar)), limit); // string1 is shorter
284 __ bind(Lskip);
285
286 // If either string is empty (or both of them) the result is the difference in lengths
287 __ cmp(limit, 0);
288 __ br(Assembler::equal, true, Assembler::pn, Ldone);
289 __ delayed()->mov(O7, result); // result is difference in lengths
290 }
291
292 {
293 // Neither string is empty
294 Label Lloop;
295
296 Register base0 = L0;
297 Register base1 = L1;
298 Register chr0 = I0;
299 Register chr1 = I1;
300 Register limit = L3;
301
302 // Shift base0 and base1 to the end of the arrays, negate limit
303 __ add(base0, limit, base0);
304 __ add(base1, limit, base1);
305 __ neg(limit); // limit = -min{string0.count, strin1.count}
306
307 __ lduh(base0, limit, chr0);
308 __ bind(Lloop);
309 __ lduh(base1, limit, chr1);
310 __ subcc(chr0, chr1, chr0);
311 __ br(Assembler::notZero, false, Assembler::pn, Ldone);
312 assert(chr0 == result, "result must be pre-placed");
313 __ delayed()->inccc(limit, sizeof(jchar));
314 __ br(Assembler::notZero, true, Assembler::pt, Lloop);
315 __ delayed()->lduh(base0, limit, chr0);
316 }
317
318 // If strings are equal up to min length, return the length difference.
319 __ mov(O7, result);
320
321 // Otherwise, return the difference between the first mismatched chars.
322 __ bind(Ldone);
323 }
324
325
326 // --------------------------------------------------------------------------------------------
327
328 void LIR_Assembler::monitorexit(LIR_Opr obj_opr, LIR_Opr lock_opr, Register hdr, int monitor_no) {
329 if (!GenerateSynchronizationCode) return;
330
331 Register obj_reg = obj_opr->as_register();
332 Register lock_reg = lock_opr->as_register();
333
334 Address mon_addr = frame_map()->address_for_monitor_lock(monitor_no);
335 Register reg = mon_addr.base();
336 int offset = mon_addr.disp();
337 // compute pointer to BasicLock
338 if (mon_addr.is_simm13()) {
339 __ add(reg, offset, lock_reg);
340 }
341 else {
342 __ set(offset, lock_reg);
343 __ add(reg, lock_reg, lock_reg);
344 }
345 // unlock object
346 MonitorAccessStub* slow_case = new MonitorExitStub(lock_opr, UseFastLocking, monitor_no);
347 // _slow_case_stubs->append(slow_case);
348 // temporary fix: must be created after exceptionhandler, therefore as call stub
349 _slow_case_stubs->append(slow_case);
350 if (UseFastLocking) {
351 // try inlined fast unlocking first, revert to slow locking if it fails
352 // note: lock_reg points to the displaced header since the displaced header offset is 0!
353 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
354 __ unlock_object(hdr, obj_reg, lock_reg, *slow_case->entry());
355 } else {
356 // always do slow unlocking
357 // note: the slow unlocking code could be inlined here, however if we use
358 // slow unlocking, speed doesn't matter anyway and this solution is
359 // simpler and requires less duplicated code - additionally, the
360 // slow unlocking code is the same in either case which simplifies
361 // debugging
362 __ br(Assembler::always, false, Assembler::pt, *slow_case->entry());
363 __ delayed()->nop();
364 }
365 // done
366 __ bind(*slow_case->continuation());
367 }
368
369
370 int LIR_Assembler::emit_exception_handler() {
371 // if the last instruction is a call (typically to do a throw which
372 // is coming at the end after block reordering) the return address
373 // must still point into the code area in order to avoid assertion
374 // failures when searching for the corresponding bci => add a nop
375 // (was bug 5/14/1999 - gri)
376 __ nop();
377
378 // generate code for exception handler
379 ciMethod* method = compilation()->method();
380
381 address handler_base = __ start_a_stub(exception_handler_size);
382
383 if (handler_base == NULL) {
384 // not enough space left for the handler
385 bailout("exception handler overflow");
386 return -1;
387 }
388
389 int offset = code_offset();
390
391 __ call(Runtime1::entry_for(Runtime1::handle_exception_from_callee_id), relocInfo::runtime_call_type);
392 __ delayed()->nop();
393 __ should_not_reach_here();
394 assert(code_offset() - offset <= exception_handler_size, "overflow");
395 __ end_a_stub();
396
397 return offset;
398 }
399
400
401 // Emit the code to remove the frame from the stack in the exception
402 // unwind path.
403 int LIR_Assembler::emit_unwind_handler() {
404 #ifndef PRODUCT
405 if (CommentedAssembly) {
406 _masm->block_comment("Unwind handler");
407 }
408 #endif
409
410 int offset = code_offset();
411
412 // Fetch the exception from TLS and clear out exception related thread state
413 __ ld_ptr(G2_thread, in_bytes(JavaThread::exception_oop_offset()), O0);
414 __ st_ptr(G0, G2_thread, in_bytes(JavaThread::exception_oop_offset()));
415 __ st_ptr(G0, G2_thread, in_bytes(JavaThread::exception_pc_offset()));
416
417 __ bind(_unwind_handler_entry);
418 __ verify_not_null_oop(O0);
419 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
420 __ mov(O0, I0); // Preserve the exception
421 }
422
423 // Preform needed unlocking
424 MonitorExitStub* stub = NULL;
425 if (method()->is_synchronized()) {
426 monitor_address(0, FrameMap::I1_opr);
427 stub = new MonitorExitStub(FrameMap::I1_opr, true, 0);
428 __ unlock_object(I3, I2, I1, *stub->entry());
429 __ bind(*stub->continuation());
430 }
431
432 if (compilation()->env()->dtrace_method_probes()) {
433 __ mov(G2_thread, O0);
434 jobject2reg(method()->constant_encoding(), O1);
435 __ call(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit), relocInfo::runtime_call_type);
436 __ delayed()->nop();
437 }
438
439 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
440 __ mov(I0, O0); // Restore the exception
441 }
442
443 // dispatch to the unwind logic
444 __ call(Runtime1::entry_for(Runtime1::unwind_exception_id), relocInfo::runtime_call_type);
445 __ delayed()->nop();
446
447 // Emit the slow path assembly
448 if (stub != NULL) {
449 stub->emit_code(this);
450 }
451
452 return offset;
453 }
454
455
456 int LIR_Assembler::emit_deopt_handler() {
457 // if the last instruction is a call (typically to do a throw which
458 // is coming at the end after block reordering) the return address
459 // must still point into the code area in order to avoid assertion
460 // failures when searching for the corresponding bci => add a nop
461 // (was bug 5/14/1999 - gri)
462 __ nop();
463
464 // generate code for deopt handler
465 ciMethod* method = compilation()->method();
466 address handler_base = __ start_a_stub(deopt_handler_size);
467 if (handler_base == NULL) {
468 // not enough space left for the handler
469 bailout("deopt handler overflow");
470 return -1;
471 }
472
473 int offset = code_offset();
474 AddressLiteral deopt_blob(SharedRuntime::deopt_blob()->unpack());
475 __ JUMP(deopt_blob, G3_scratch, 0); // sethi;jmp
476 __ delayed()->nop();
477 assert(code_offset() - offset <= deopt_handler_size, "overflow");
478 debug_only(__ stop("should have gone to the caller");)
479 __ end_a_stub();
480
481 return offset;
482 }
483
484
485 void LIR_Assembler::jobject2reg(jobject o, Register reg) {
486 if (o == NULL) {
487 __ set(NULL_WORD, reg);
488 } else {
489 int oop_index = __ oop_recorder()->find_index(o);
490 RelocationHolder rspec = oop_Relocation::spec(oop_index);
491 __ set(NULL_WORD, reg, rspec); // Will be set when the nmethod is created
492 }
493 }
494
495
496 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo *info) {
497 // Allocate a new index in oop table to hold the oop once it's been patched
498 int oop_index = __ oop_recorder()->allocate_index((jobject)NULL);
499 PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id, oop_index);
500
501 AddressLiteral addrlit(NULL, oop_Relocation::spec(oop_index));
502 assert(addrlit.rspec().type() == relocInfo::oop_type, "must be an oop reloc");
503 // It may not seem necessary to use a sethi/add pair to load a NULL into dest, but the
504 // NULL will be dynamically patched later and the patched value may be large. We must
505 // therefore generate the sethi/add as a placeholders
506 __ patchable_set(addrlit, reg);
507
508 patching_epilog(patch, lir_patch_normal, reg, info);
509 }
510
511
512 void LIR_Assembler::emit_op3(LIR_Op3* op) {
513 Register Rdividend = op->in_opr1()->as_register();
514 Register Rdivisor = noreg;
515 Register Rscratch = op->in_opr3()->as_register();
516 Register Rresult = op->result_opr()->as_register();
517 int divisor = -1;
518
519 if (op->in_opr2()->is_register()) {
520 Rdivisor = op->in_opr2()->as_register();
521 } else {
522 divisor = op->in_opr2()->as_constant_ptr()->as_jint();
523 assert(Assembler::is_simm13(divisor), "can only handle simm13");
524 }
525
526 assert(Rdividend != Rscratch, "");
527 assert(Rdivisor != Rscratch, "");
528 assert(op->code() == lir_idiv || op->code() == lir_irem, "Must be irem or idiv");
529
530 if (Rdivisor == noreg && is_power_of_2(divisor)) {
531 // convert division by a power of two into some shifts and logical operations
532 if (op->code() == lir_idiv) {
533 if (divisor == 2) {
534 __ srl(Rdividend, 31, Rscratch);
535 } else {
536 __ sra(Rdividend, 31, Rscratch);
537 __ and3(Rscratch, divisor - 1, Rscratch);
538 }
539 __ add(Rdividend, Rscratch, Rscratch);
540 __ sra(Rscratch, log2_intptr(divisor), Rresult);
541 return;
542 } else {
543 if (divisor == 2) {
544 __ srl(Rdividend, 31, Rscratch);
545 } else {
546 __ sra(Rdividend, 31, Rscratch);
547 __ and3(Rscratch, divisor - 1,Rscratch);
548 }
549 __ add(Rdividend, Rscratch, Rscratch);
550 __ andn(Rscratch, divisor - 1,Rscratch);
551 __ sub(Rdividend, Rscratch, Rresult);
552 return;
553 }
554 }
555
556 __ sra(Rdividend, 31, Rscratch);
557 __ wry(Rscratch);
558 if (!VM_Version::v9_instructions_work()) {
559 // v9 doesn't require these nops
560 __ nop();
561 __ nop();
562 __ nop();
563 __ nop();
564 }
565
566 add_debug_info_for_div0_here(op->info());
567
568 if (Rdivisor != noreg) {
569 __ sdivcc(Rdividend, Rdivisor, (op->code() == lir_idiv ? Rresult : Rscratch));
570 } else {
571 assert(Assembler::is_simm13(divisor), "can only handle simm13");
572 __ sdivcc(Rdividend, divisor, (op->code() == lir_idiv ? Rresult : Rscratch));
573 }
574
575 Label skip;
576 __ br(Assembler::overflowSet, true, Assembler::pn, skip);
577 __ delayed()->Assembler::sethi(0x80000000, (op->code() == lir_idiv ? Rresult : Rscratch));
578 __ bind(skip);
579
580 if (op->code() == lir_irem) {
581 if (Rdivisor != noreg) {
582 __ smul(Rscratch, Rdivisor, Rscratch);
583 } else {
584 __ smul(Rscratch, divisor, Rscratch);
585 }
586 __ sub(Rdividend, Rscratch, Rresult);
587 }
588 }
589
590
591 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {
592 #ifdef ASSERT
593 assert(op->block() == NULL || op->block()->label() == op->label(), "wrong label");
594 if (op->block() != NULL) _branch_target_blocks.append(op->block());
595 if (op->ublock() != NULL) _branch_target_blocks.append(op->ublock());
596 #endif
597 assert(op->info() == NULL, "shouldn't have CodeEmitInfo");
598
599 if (op->cond() == lir_cond_always) {
600 __ br(Assembler::always, false, Assembler::pt, *(op->label()));
601 } else if (op->code() == lir_cond_float_branch) {
602 assert(op->ublock() != NULL, "must have unordered successor");
603 bool is_unordered = (op->ublock() == op->block());
604 Assembler::Condition acond;
605 switch (op->cond()) {
606 case lir_cond_equal: acond = Assembler::f_equal; break;
607 case lir_cond_notEqual: acond = Assembler::f_notEqual; break;
608 case lir_cond_less: acond = (is_unordered ? Assembler::f_unorderedOrLess : Assembler::f_less); break;
609 case lir_cond_greater: acond = (is_unordered ? Assembler::f_unorderedOrGreater : Assembler::f_greater); break;
610 case lir_cond_lessEqual: acond = (is_unordered ? Assembler::f_unorderedOrLessOrEqual : Assembler::f_lessOrEqual); break;
611 case lir_cond_greaterEqual: acond = (is_unordered ? Assembler::f_unorderedOrGreaterOrEqual: Assembler::f_greaterOrEqual); break;
612 default : ShouldNotReachHere();
613 };
614
615 if (!VM_Version::v9_instructions_work()) {
616 __ nop();
617 }
618 __ fb( acond, false, Assembler::pn, *(op->label()));
619 } else {
620 assert (op->code() == lir_branch, "just checking");
621
622 Assembler::Condition acond;
623 switch (op->cond()) {
624 case lir_cond_equal: acond = Assembler::equal; break;
625 case lir_cond_notEqual: acond = Assembler::notEqual; break;
626 case lir_cond_less: acond = Assembler::less; break;
627 case lir_cond_lessEqual: acond = Assembler::lessEqual; break;
628 case lir_cond_greaterEqual: acond = Assembler::greaterEqual; break;
629 case lir_cond_greater: acond = Assembler::greater; break;
630 case lir_cond_aboveEqual: acond = Assembler::greaterEqualUnsigned; break;
631 case lir_cond_belowEqual: acond = Assembler::lessEqualUnsigned; break;
632 default: ShouldNotReachHere();
633 };
634
635 // sparc has different condition codes for testing 32-bit
636 // vs. 64-bit values. We could always test xcc is we could
637 // guarantee that 32-bit loads always sign extended but that isn't
638 // true and since sign extension isn't free, it would impose a
639 // slight cost.
640 #ifdef _LP64
641 if (op->type() == T_INT) {
642 __ br(acond, false, Assembler::pn, *(op->label()));
643 } else
644 #endif
645 __ brx(acond, false, Assembler::pn, *(op->label()));
646 }
647 // The peephole pass fills the delay slot
648 }
649
650
651 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
652 Bytecodes::Code code = op->bytecode();
653 LIR_Opr dst = op->result_opr();
654
655 switch(code) {
656 case Bytecodes::_i2l: {
657 Register rlo = dst->as_register_lo();
658 Register rhi = dst->as_register_hi();
659 Register rval = op->in_opr()->as_register();
660 #ifdef _LP64
661 __ sra(rval, 0, rlo);
662 #else
663 __ mov(rval, rlo);
664 __ sra(rval, BitsPerInt-1, rhi);
665 #endif
666 break;
667 }
668 case Bytecodes::_i2d:
669 case Bytecodes::_i2f: {
670 bool is_double = (code == Bytecodes::_i2d);
671 FloatRegister rdst = is_double ? dst->as_double_reg() : dst->as_float_reg();
672 FloatRegisterImpl::Width w = is_double ? FloatRegisterImpl::D : FloatRegisterImpl::S;
673 FloatRegister rsrc = op->in_opr()->as_float_reg();
674 if (rsrc != rdst) {
675 __ fmov(FloatRegisterImpl::S, rsrc, rdst);
676 }
677 __ fitof(w, rdst, rdst);
678 break;
679 }
680 case Bytecodes::_f2i:{
681 FloatRegister rsrc = op->in_opr()->as_float_reg();
682 Address addr = frame_map()->address_for_slot(dst->single_stack_ix());
683 Label L;
684 // result must be 0 if value is NaN; test by comparing value to itself
685 __ fcmp(FloatRegisterImpl::S, Assembler::fcc0, rsrc, rsrc);
686 if (!VM_Version::v9_instructions_work()) {
687 __ nop();
688 }
689 __ fb(Assembler::f_unordered, true, Assembler::pn, L);
690 __ delayed()->st(G0, addr); // annuled if contents of rsrc is not NaN
691 __ ftoi(FloatRegisterImpl::S, rsrc, rsrc);
692 // move integer result from float register to int register
693 __ stf(FloatRegisterImpl::S, rsrc, addr.base(), addr.disp());
694 __ bind (L);
695 break;
696 }
697 case Bytecodes::_l2i: {
698 Register rlo = op->in_opr()->as_register_lo();
699 Register rhi = op->in_opr()->as_register_hi();
700 Register rdst = dst->as_register();
701 #ifdef _LP64
702 __ sra(rlo, 0, rdst);
703 #else
704 __ mov(rlo, rdst);
705 #endif
706 break;
707 }
708 case Bytecodes::_d2f:
709 case Bytecodes::_f2d: {
710 bool is_double = (code == Bytecodes::_f2d);
711 assert((!is_double && dst->is_single_fpu()) || (is_double && dst->is_double_fpu()), "check");
712 LIR_Opr val = op->in_opr();
713 FloatRegister rval = (code == Bytecodes::_d2f) ? val->as_double_reg() : val->as_float_reg();
714 FloatRegister rdst = is_double ? dst->as_double_reg() : dst->as_float_reg();
715 FloatRegisterImpl::Width vw = is_double ? FloatRegisterImpl::S : FloatRegisterImpl::D;
716 FloatRegisterImpl::Width dw = is_double ? FloatRegisterImpl::D : FloatRegisterImpl::S;
717 __ ftof(vw, dw, rval, rdst);
718 break;
719 }
720 case Bytecodes::_i2s:
721 case Bytecodes::_i2b: {
722 Register rval = op->in_opr()->as_register();
723 Register rdst = dst->as_register();
724 int shift = (code == Bytecodes::_i2b) ? (BitsPerInt - T_BYTE_aelem_bytes * BitsPerByte) : (BitsPerInt - BitsPerShort);
725 __ sll (rval, shift, rdst);
726 __ sra (rdst, shift, rdst);
727 break;
728 }
729 case Bytecodes::_i2c: {
730 Register rval = op->in_opr()->as_register();
731 Register rdst = dst->as_register();
732 int shift = BitsPerInt - T_CHAR_aelem_bytes * BitsPerByte;
733 __ sll (rval, shift, rdst);
734 __ srl (rdst, shift, rdst);
735 break;
736 }
737
738 default: ShouldNotReachHere();
739 }
740 }
741
742
743 void LIR_Assembler::align_call(LIR_Code) {
744 // do nothing since all instructions are word aligned on sparc
745 }
746
747
748 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) {
749 __ call(op->addr(), rtype);
750 // The peephole pass fills the delay slot, add_call_info is done in
751 // LIR_Assembler::emit_delay.
752 }
753
754
755 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) {
756 RelocationHolder rspec = virtual_call_Relocation::spec(pc());
757 __ set_oop((jobject)Universe::non_oop_word(), G5_inline_cache_reg);
758 __ relocate(rspec);
759 __ call(op->addr(), relocInfo::none);
760 // The peephole pass fills the delay slot, add_call_info is done in
761 // LIR_Assembler::emit_delay.
762 }
763
764
765 void LIR_Assembler::vtable_call(LIR_OpJavaCall* op) {
766 add_debug_info_for_null_check_here(op->info());
767 __ load_klass(O0, G3_scratch);
768 if (Assembler::is_simm13(op->vtable_offset())) {
769 __ ld_ptr(G3_scratch, op->vtable_offset(), G5_method);
770 } else {
771 // This will generate 2 instructions
772 __ set(op->vtable_offset(), G5_method);
773 // ld_ptr, set_hi, set
774 __ ld_ptr(G3_scratch, G5_method, G5_method);
775 }
776 __ ld_ptr(G5_method, methodOopDesc::from_compiled_offset(), G3_scratch);
777 __ callr(G3_scratch, G0);
778 // the peephole pass fills the delay slot
779 }
780
781 int LIR_Assembler::store(LIR_Opr from_reg, Register base, int offset, BasicType type, bool wide, bool unaligned) {
782 int store_offset;
783 if (!Assembler::is_simm13(offset + (type == T_LONG) ? wordSize : 0)) {
784 assert(!unaligned, "can't handle this");
785 // for offsets larger than a simm13 we setup the offset in O7
786 __ set(offset, O7);
787 store_offset = store(from_reg, base, O7, type, wide);
788 } else {
789 if (type == T_ARRAY || type == T_OBJECT) {
790 __ verify_oop(from_reg->as_register());
791 }
792 store_offset = code_offset();
793 switch (type) {
794 case T_BOOLEAN: // fall through
795 case T_BYTE : __ stb(from_reg->as_register(), base, offset); break;
796 case T_CHAR : __ sth(from_reg->as_register(), base, offset); break;
797 case T_SHORT : __ sth(from_reg->as_register(), base, offset); break;
798 case T_INT : __ stw(from_reg->as_register(), base, offset); break;
799 case T_LONG :
800 #ifdef _LP64
801 if (unaligned || PatchALot) {
802 __ srax(from_reg->as_register_lo(), 32, O7);
803 __ stw(from_reg->as_register_lo(), base, offset + lo_word_offset_in_bytes);
804 __ stw(O7, base, offset + hi_word_offset_in_bytes);
805 } else {
806 __ stx(from_reg->as_register_lo(), base, offset);
807 }
808 #else
809 assert(Assembler::is_simm13(offset + 4), "must be");
810 __ stw(from_reg->as_register_lo(), base, offset + lo_word_offset_in_bytes);
811 __ stw(from_reg->as_register_hi(), base, offset + hi_word_offset_in_bytes);
812 #endif
813 break;
814 case T_ADDRESS:
815 __ st_ptr(from_reg->as_register(), base, offset);
816 break;
817 case T_ARRAY : // fall through
818 case T_OBJECT:
819 {
820 if (UseCompressedOops && !wide) {
821 __ encode_heap_oop(from_reg->as_register(), G3_scratch);
822 store_offset = code_offset();
823 __ stw(G3_scratch, base, offset);
824 } else {
825 __ st_ptr(from_reg->as_register(), base, offset);
826 }
827 break;
828 }
829
830 case T_FLOAT : __ stf(FloatRegisterImpl::S, from_reg->as_float_reg(), base, offset); break;
831 case T_DOUBLE:
832 {
833 FloatRegister reg = from_reg->as_double_reg();
834 // split unaligned stores
835 if (unaligned || PatchALot) {
836 assert(Assembler::is_simm13(offset + 4), "must be");
837 __ stf(FloatRegisterImpl::S, reg->successor(), base, offset + 4);
838 __ stf(FloatRegisterImpl::S, reg, base, offset);
839 } else {
840 __ stf(FloatRegisterImpl::D, reg, base, offset);
841 }
842 break;
843 }
844 default : ShouldNotReachHere();
845 }
846 }
847 return store_offset;
848 }
849
850
851 int LIR_Assembler::store(LIR_Opr from_reg, Register base, Register disp, BasicType type, bool wide) {
852 if (type == T_ARRAY || type == T_OBJECT) {
853 __ verify_oop(from_reg->as_register());
854 }
855 int store_offset = code_offset();
856 switch (type) {
857 case T_BOOLEAN: // fall through
858 case T_BYTE : __ stb(from_reg->as_register(), base, disp); break;
859 case T_CHAR : __ sth(from_reg->as_register(), base, disp); break;
860 case T_SHORT : __ sth(from_reg->as_register(), base, disp); break;
861 case T_INT : __ stw(from_reg->as_register(), base, disp); break;
862 case T_LONG :
863 #ifdef _LP64
864 __ stx(from_reg->as_register_lo(), base, disp);
865 #else
866 assert(from_reg->as_register_hi()->successor() == from_reg->as_register_lo(), "must match");
867 __ std(from_reg->as_register_hi(), base, disp);
868 #endif
869 break;
870 case T_ADDRESS:
871 __ st_ptr(from_reg->as_register(), base, disp);
872 break;
873 case T_ARRAY : // fall through
874 case T_OBJECT:
875 {
876 if (UseCompressedOops && !wide) {
877 __ encode_heap_oop(from_reg->as_register(), G3_scratch);
878 store_offset = code_offset();
879 __ stw(G3_scratch, base, disp);
880 } else {
881 __ st_ptr(from_reg->as_register(), base, disp);
882 }
883 break;
884 }
885 case T_FLOAT : __ stf(FloatRegisterImpl::S, from_reg->as_float_reg(), base, disp); break;
886 case T_DOUBLE: __ stf(FloatRegisterImpl::D, from_reg->as_double_reg(), base, disp); break;
887 default : ShouldNotReachHere();
888 }
889 return store_offset;
890 }
891
892
893 int LIR_Assembler::load(Register base, int offset, LIR_Opr to_reg, BasicType type, bool wide, bool unaligned) {
894 int load_offset;
895 if (!Assembler::is_simm13(offset + (type == T_LONG) ? wordSize : 0)) {
896 assert(base != O7, "destroying register");
897 assert(!unaligned, "can't handle this");
898 // for offsets larger than a simm13 we setup the offset in O7
899 __ set(offset, O7);
900 load_offset = load(base, O7, to_reg, type, wide);
901 } else {
902 load_offset = code_offset();
903 switch(type) {
904 case T_BOOLEAN: // fall through
905 case T_BYTE : __ ldsb(base, offset, to_reg->as_register()); break;
906 case T_CHAR : __ lduh(base, offset, to_reg->as_register()); break;
907 case T_SHORT : __ ldsh(base, offset, to_reg->as_register()); break;
908 case T_INT : __ ld(base, offset, to_reg->as_register()); break;
909 case T_LONG :
910 if (!unaligned) {
911 #ifdef _LP64
912 __ ldx(base, offset, to_reg->as_register_lo());
913 #else
914 assert(to_reg->as_register_hi()->successor() == to_reg->as_register_lo(),
915 "must be sequential");
916 __ ldd(base, offset, to_reg->as_register_hi());
917 #endif
918 } else {
919 #ifdef _LP64
920 assert(base != to_reg->as_register_lo(), "can't handle this");
921 assert(O7 != to_reg->as_register_lo(), "can't handle this");
922 __ ld(base, offset + hi_word_offset_in_bytes, to_reg->as_register_lo());
923 __ lduw(base, offset + lo_word_offset_in_bytes, O7); // in case O7 is base or offset, use it last
924 __ sllx(to_reg->as_register_lo(), 32, to_reg->as_register_lo());
925 __ or3(to_reg->as_register_lo(), O7, to_reg->as_register_lo());
926 #else
927 if (base == to_reg->as_register_lo()) {
928 __ ld(base, offset + hi_word_offset_in_bytes, to_reg->as_register_hi());
929 __ ld(base, offset + lo_word_offset_in_bytes, to_reg->as_register_lo());
930 } else {
931 __ ld(base, offset + lo_word_offset_in_bytes, to_reg->as_register_lo());
932 __ ld(base, offset + hi_word_offset_in_bytes, to_reg->as_register_hi());
933 }
934 #endif
935 }
936 break;
937 case T_ADDRESS: __ ld_ptr(base, offset, to_reg->as_register()); break;
938 case T_ARRAY : // fall through
939 case T_OBJECT:
940 {
941 if (UseCompressedOops && !wide) {
942 __ lduw(base, offset, to_reg->as_register());
943 __ decode_heap_oop(to_reg->as_register());
944 } else {
945 __ ld_ptr(base, offset, to_reg->as_register());
946 }
947 break;
948 }
949 case T_FLOAT: __ ldf(FloatRegisterImpl::S, base, offset, to_reg->as_float_reg()); break;
950 case T_DOUBLE:
951 {
952 FloatRegister reg = to_reg->as_double_reg();
953 // split unaligned loads
954 if (unaligned || PatchALot) {
955 __ ldf(FloatRegisterImpl::S, base, offset + 4, reg->successor());
956 __ ldf(FloatRegisterImpl::S, base, offset, reg);
957 } else {
958 __ ldf(FloatRegisterImpl::D, base, offset, to_reg->as_double_reg());
959 }
960 break;
961 }
962 default : ShouldNotReachHere();
963 }
964 if (type == T_ARRAY || type == T_OBJECT) {
965 __ verify_oop(to_reg->as_register());
966 }
967 }
968 return load_offset;
969 }
970
971
972 int LIR_Assembler::load(Register base, Register disp, LIR_Opr to_reg, BasicType type, bool wide) {
973 int load_offset = code_offset();
974 switch(type) {
975 case T_BOOLEAN: // fall through
976 case T_BYTE : __ ldsb(base, disp, to_reg->as_register()); break;
977 case T_CHAR : __ lduh(base, disp, to_reg->as_register()); break;
978 case T_SHORT : __ ldsh(base, disp, to_reg->as_register()); break;
979 case T_INT : __ ld(base, disp, to_reg->as_register()); break;
980 case T_ADDRESS: __ ld_ptr(base, disp, to_reg->as_register()); break;
981 case T_ARRAY : // fall through
982 case T_OBJECT:
983 {
984 if (UseCompressedOops && !wide) {
985 __ lduw(base, disp, to_reg->as_register());
986 __ decode_heap_oop(to_reg->as_register());
987 } else {
988 __ ld_ptr(base, disp, to_reg->as_register());
989 }
990 break;
991 }
992 case T_FLOAT: __ ldf(FloatRegisterImpl::S, base, disp, to_reg->as_float_reg()); break;
993 case T_DOUBLE: __ ldf(FloatRegisterImpl::D, base, disp, to_reg->as_double_reg()); break;
994 case T_LONG :
995 #ifdef _LP64
996 __ ldx(base, disp, to_reg->as_register_lo());
997 #else
998 assert(to_reg->as_register_hi()->successor() == to_reg->as_register_lo(),
999 "must be sequential");
1000 __ ldd(base, disp, to_reg->as_register_hi());
1001 #endif
1002 break;
1003 default : ShouldNotReachHere();
1004 }
1005 if (type == T_ARRAY || type == T_OBJECT) {
1006 __ verify_oop(to_reg->as_register());
1007 }
1008 return load_offset;
1009 }
1010
1011 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
1012 LIR_Const* c = src->as_constant_ptr();
1013 switch (c->type()) {
1014 case T_INT:
1015 case T_FLOAT: {
1016 Register src_reg = O7;
1017 int value = c->as_jint_bits();
1018 if (value == 0) {
1019 src_reg = G0;
1020 } else {
1021 __ set(value, O7);
1022 }
1023 Address addr = frame_map()->address_for_slot(dest->single_stack_ix());
1024 __ stw(src_reg, addr.base(), addr.disp());
1025 break;
1026 }
1027 case T_ADDRESS: {
1028 Register src_reg = O7;
1029 int value = c->as_jint_bits();
1030 if (value == 0) {
1031 src_reg = G0;
1032 } else {
1033 __ set(value, O7);
1034 }
1035 Address addr = frame_map()->address_for_slot(dest->single_stack_ix());
1036 __ st_ptr(src_reg, addr.base(), addr.disp());
1037 break;
1038 }
1039 case T_OBJECT: {
1040 Register src_reg = O7;
1041 jobject2reg(c->as_jobject(), src_reg);
1042 Address addr = frame_map()->address_for_slot(dest->single_stack_ix());
1043 __ st_ptr(src_reg, addr.base(), addr.disp());
1044 break;
1045 }
1046 case T_LONG:
1047 case T_DOUBLE: {
1048 Address addr = frame_map()->address_for_double_slot(dest->double_stack_ix());
1049
1050 Register tmp = O7;
1051 int value_lo = c->as_jint_lo_bits();
1052 if (value_lo == 0) {
1053 tmp = G0;
1054 } else {
1055 __ set(value_lo, O7);
1056 }
1057 __ stw(tmp, addr.base(), addr.disp() + lo_word_offset_in_bytes);
1058 int value_hi = c->as_jint_hi_bits();
1059 if (value_hi == 0) {
1060 tmp = G0;
1061 } else {
1062 __ set(value_hi, O7);
1063 }
1064 __ stw(tmp, addr.base(), addr.disp() + hi_word_offset_in_bytes);
1065 break;
1066 }
1067 default:
1068 Unimplemented();
1069 }
1070 }
1071
1072
1073 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) {
1074 LIR_Const* c = src->as_constant_ptr();
1075 LIR_Address* addr = dest->as_address_ptr();
1076 Register base = addr->base()->as_pointer_register();
1077 int offset = -1;
1078
1079 switch (c->type()) {
1080 case T_INT:
1081 case T_FLOAT:
1082 case T_ADDRESS: {
1083 LIR_Opr tmp = FrameMap::O7_opr;
1084 int value = c->as_jint_bits();
1085 if (value == 0) {
1086 tmp = FrameMap::G0_opr;
1087 } else if (Assembler::is_simm13(value)) {
1088 __ set(value, O7);
1089 }
1090 if (addr->index()->is_valid()) {
1091 assert(addr->disp() == 0, "must be zero");
1092 offset = store(tmp, base, addr->index()->as_pointer_register(), type, wide);
1093 } else {
1094 assert(Assembler::is_simm13(addr->disp()), "can't handle larger addresses");
1095 offset = store(tmp, base, addr->disp(), type, wide, false);
1096 }
1097 break;
1098 }
1099 case T_LONG:
1100 case T_DOUBLE: {
1101 assert(!addr->index()->is_valid(), "can't handle reg reg address here");
1102 assert(Assembler::is_simm13(addr->disp()) &&
1103 Assembler::is_simm13(addr->disp() + 4), "can't handle larger addresses");
1104
1105 LIR_Opr tmp = FrameMap::O7_opr;
1106 int value_lo = c->as_jint_lo_bits();
1107 if (value_lo == 0) {
1108 tmp = FrameMap::G0_opr;
1109 } else {
1110 __ set(value_lo, O7);
1111 }
1112 offset = store(tmp, base, addr->disp() + lo_word_offset_in_bytes, T_INT, wide, false);
1113 int value_hi = c->as_jint_hi_bits();
1114 if (value_hi == 0) {
1115 tmp = FrameMap::G0_opr;
1116 } else {
1117 __ set(value_hi, O7);
1118 }
1119 store(tmp, base, addr->disp() + hi_word_offset_in_bytes, T_INT, wide, false);
1120 break;
1121 }
1122 case T_OBJECT: {
1123 jobject obj = c->as_jobject();
1124 LIR_Opr tmp;
1125 if (obj == NULL) {
1126 tmp = FrameMap::G0_opr;
1127 } else {
1128 tmp = FrameMap::O7_opr;
1129 jobject2reg(c->as_jobject(), O7);
1130 }
1131 // handle either reg+reg or reg+disp address
1132 if (addr->index()->is_valid()) {
1133 assert(addr->disp() == 0, "must be zero");
1134 offset = store(tmp, base, addr->index()->as_pointer_register(), type, wide);
1135 } else {
1136 assert(Assembler::is_simm13(addr->disp()), "can't handle larger addresses");
1137 offset = store(tmp, base, addr->disp(), type, wide, false);
1138 }
1139
1140 break;
1141 }
1142 default:
1143 Unimplemented();
1144 }
1145 if (info != NULL) {
1146 assert(offset != -1, "offset should've been set");
1147 add_debug_info_for_null_check(offset, info);
1148 }
1149 }
1150
1151
1152 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
1153 LIR_Const* c = src->as_constant_ptr();
1154 LIR_Opr to_reg = dest;
1155
1156 switch (c->type()) {
1157 case T_INT:
1158 case T_ADDRESS:
1159 {
1160 jint con = c->as_jint();
1161 if (to_reg->is_single_cpu()) {
1162 assert(patch_code == lir_patch_none, "no patching handled here");
1163 __ set(con, to_reg->as_register());
1164 } else {
1165 ShouldNotReachHere();
1166 assert(to_reg->is_single_fpu(), "wrong register kind");
1167
1168 __ set(con, O7);
1169 Address temp_slot(SP, (frame::register_save_words * wordSize) + STACK_BIAS);
1170 __ st(O7, temp_slot);
1171 __ ldf(FloatRegisterImpl::S, temp_slot, to_reg->as_float_reg());
1172 }
1173 }
1174 break;
1175
1176 case T_LONG:
1177 {
1178 jlong con = c->as_jlong();
1179
1180 if (to_reg->is_double_cpu()) {
1181 #ifdef _LP64
1182 __ set(con, to_reg->as_register_lo());
1183 #else
1184 __ set(low(con), to_reg->as_register_lo());
1185 __ set(high(con), to_reg->as_register_hi());
1186 #endif
1187 #ifdef _LP64
1188 } else if (to_reg->is_single_cpu()) {
1189 __ set(con, to_reg->as_register());
1190 #endif
1191 } else {
1192 ShouldNotReachHere();
1193 assert(to_reg->is_double_fpu(), "wrong register kind");
1194 Address temp_slot_lo(SP, ((frame::register_save_words ) * wordSize) + STACK_BIAS);
1195 Address temp_slot_hi(SP, ((frame::register_save_words) * wordSize) + (longSize/2) + STACK_BIAS);
1196 __ set(low(con), O7);
1197 __ st(O7, temp_slot_lo);
1198 __ set(high(con), O7);
1199 __ st(O7, temp_slot_hi);
1200 __ ldf(FloatRegisterImpl::D, temp_slot_lo, to_reg->as_double_reg());
1201 }
1202 }
1203 break;
1204
1205 case T_OBJECT:
1206 {
1207 if (patch_code == lir_patch_none) {
1208 jobject2reg(c->as_jobject(), to_reg->as_register());
1209 } else {
1210 jobject2reg_with_patching(to_reg->as_register(), info);
1211 }
1212 }
1213 break;
1214
1215 case T_FLOAT:
1216 {
1217 address const_addr = __ float_constant(c->as_jfloat());
1218 if (const_addr == NULL) {
1219 bailout("const section overflow");
1220 break;
1221 }
1222 RelocationHolder rspec = internal_word_Relocation::spec(const_addr);
1223 AddressLiteral const_addrlit(const_addr, rspec);
1224 if (to_reg->is_single_fpu()) {
1225 __ patchable_sethi(const_addrlit, O7);
1226 __ relocate(rspec);
1227 __ ldf(FloatRegisterImpl::S, O7, const_addrlit.low10(), to_reg->as_float_reg());
1228
1229 } else {
1230 assert(to_reg->is_single_cpu(), "Must be a cpu register.");
1231
1232 __ set(const_addrlit, O7);
1233 __ ld(O7, 0, to_reg->as_register());
1234 }
1235 }
1236 break;
1237
1238 case T_DOUBLE:
1239 {
1240 address const_addr = __ double_constant(c->as_jdouble());
1241 if (const_addr == NULL) {
1242 bailout("const section overflow");
1243 break;
1244 }
1245 RelocationHolder rspec = internal_word_Relocation::spec(const_addr);
1246
1247 if (to_reg->is_double_fpu()) {
1248 AddressLiteral const_addrlit(const_addr, rspec);
1249 __ patchable_sethi(const_addrlit, O7);
1250 __ relocate(rspec);
1251 __ ldf (FloatRegisterImpl::D, O7, const_addrlit.low10(), to_reg->as_double_reg());
1252 } else {
1253 assert(to_reg->is_double_cpu(), "Must be a long register.");
1254 #ifdef _LP64
1255 __ set(jlong_cast(c->as_jdouble()), to_reg->as_register_lo());
1256 #else
1257 __ set(low(jlong_cast(c->as_jdouble())), to_reg->as_register_lo());
1258 __ set(high(jlong_cast(c->as_jdouble())), to_reg->as_register_hi());
1259 #endif
1260 }
1261
1262 }
1263 break;
1264
1265 default:
1266 ShouldNotReachHere();
1267 }
1268 }
1269
1270 Address LIR_Assembler::as_Address(LIR_Address* addr) {
1271 Register reg = addr->base()->as_register();
1272 return Address(reg, addr->disp());
1273 }
1274
1275
1276 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
1277 switch (type) {
1278 case T_INT:
1279 case T_FLOAT: {
1280 Register tmp = O7;
1281 Address from = frame_map()->address_for_slot(src->single_stack_ix());
1282 Address to = frame_map()->address_for_slot(dest->single_stack_ix());
1283 __ lduw(from.base(), from.disp(), tmp);
1284 __ stw(tmp, to.base(), to.disp());
1285 break;
1286 }
1287 case T_OBJECT: {
1288 Register tmp = O7;
1289 Address from = frame_map()->address_for_slot(src->single_stack_ix());
1290 Address to = frame_map()->address_for_slot(dest->single_stack_ix());
1291 __ ld_ptr(from.base(), from.disp(), tmp);
1292 __ st_ptr(tmp, to.base(), to.disp());
1293 break;
1294 }
1295 case T_LONG:
1296 case T_DOUBLE: {
1297 Register tmp = O7;
1298 Address from = frame_map()->address_for_double_slot(src->double_stack_ix());
1299 Address to = frame_map()->address_for_double_slot(dest->double_stack_ix());
1300 __ lduw(from.base(), from.disp(), tmp);
1301 __ stw(tmp, to.base(), to.disp());
1302 __ lduw(from.base(), from.disp() + 4, tmp);
1303 __ stw(tmp, to.base(), to.disp() + 4);
1304 break;
1305 }
1306
1307 default:
1308 ShouldNotReachHere();
1309 }
1310 }
1311
1312
1313 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) {
1314 Address base = as_Address(addr);
1315 return Address(base.base(), base.disp() + hi_word_offset_in_bytes);
1316 }
1317
1318
1319 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) {
1320 Address base = as_Address(addr);
1321 return Address(base.base(), base.disp() + lo_word_offset_in_bytes);
1322 }
1323
1324
1325 void LIR_Assembler::mem2reg(LIR_Opr src_opr, LIR_Opr dest, BasicType type,
1326 LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide, bool unaligned) {
1327
1328 LIR_Address* addr = src_opr->as_address_ptr();
1329 LIR_Opr to_reg = dest;
1330
1331 Register src = addr->base()->as_pointer_register();
1332 Register disp_reg = noreg;
1333 int disp_value = addr->disp();
1334 bool needs_patching = (patch_code != lir_patch_none);
1335
1336 if (addr->base()->type() == T_OBJECT) {
1337 __ verify_oop(src);
1338 }
1339
1340 PatchingStub* patch = NULL;
1341 if (needs_patching) {
1342 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1343 assert(!to_reg->is_double_cpu() ||
1344 patch_code == lir_patch_none ||
1345 patch_code == lir_patch_normal, "patching doesn't match register");
1346 }
1347
1348 if (addr->index()->is_illegal()) {
1349 if (!Assembler::is_simm13(disp_value) && (!unaligned || Assembler::is_simm13(disp_value + 4))) {
1350 if (needs_patching) {
1351 __ patchable_set(0, O7);
1352 } else {
1353 __ set(disp_value, O7);
1354 }
1355 disp_reg = O7;
1356 }
1357 } else if (unaligned || PatchALot) {
1358 __ add(src, addr->index()->as_register(), O7);
1359 src = O7;
1360 } else {
1361 disp_reg = addr->index()->as_pointer_register();
1362 assert(disp_value == 0, "can't handle 3 operand addresses");
1363 }
1364
1365 // remember the offset of the load. The patching_epilog must be done
1366 // before the call to add_debug_info, otherwise the PcDescs don't get
1367 // entered in increasing order.
1368 int offset = code_offset();
1369
1370 assert(disp_reg != noreg || Assembler::is_simm13(disp_value), "should have set this up");
1371 if (disp_reg == noreg) {
1372 offset = load(src, disp_value, to_reg, type, wide, unaligned);
1373 } else {
1374 assert(!unaligned, "can't handle this");
1375 offset = load(src, disp_reg, to_reg, type, wide);
1376 }
1377
1378 if (patch != NULL) {
1379 patching_epilog(patch, patch_code, src, info);
1380 }
1381 if (info != NULL) add_debug_info_for_null_check(offset, info);
1382 }
1383
1384
1385 void LIR_Assembler::prefetchr(LIR_Opr src) {
1386 LIR_Address* addr = src->as_address_ptr();
1387 Address from_addr = as_Address(addr);
1388
1389 if (VM_Version::has_v9()) {
1390 __ prefetch(from_addr, Assembler::severalReads);
1391 }
1392 }
1393
1394
1395 void LIR_Assembler::prefetchw(LIR_Opr src) {
1396 LIR_Address* addr = src->as_address_ptr();
1397 Address from_addr = as_Address(addr);
1398
1399 if (VM_Version::has_v9()) {
1400 __ prefetch(from_addr, Assembler::severalWritesAndPossiblyReads);
1401 }
1402 }
1403
1404
1405 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
1406 Address addr;
1407 if (src->is_single_word()) {
1408 addr = frame_map()->address_for_slot(src->single_stack_ix());
1409 } else if (src->is_double_word()) {
1410 addr = frame_map()->address_for_double_slot(src->double_stack_ix());
1411 }
1412
1413 bool unaligned = (addr.disp() - STACK_BIAS) % 8 != 0;
1414 load(addr.base(), addr.disp(), dest, dest->type(), true /*wide*/, unaligned);
1415 }
1416
1417
1418 void LIR_Assembler::reg2stack(LIR_Opr from_reg, LIR_Opr dest, BasicType type, bool pop_fpu_stack) {
1419 Address addr;
1420 if (dest->is_single_word()) {
1421 addr = frame_map()->address_for_slot(dest->single_stack_ix());
1422 } else if (dest->is_double_word()) {
1423 addr = frame_map()->address_for_slot(dest->double_stack_ix());
1424 }
1425 bool unaligned = (addr.disp() - STACK_BIAS) % 8 != 0;
1426 store(from_reg, addr.base(), addr.disp(), from_reg->type(), true /*wide*/, unaligned);
1427 }
1428
1429
1430 void LIR_Assembler::reg2reg(LIR_Opr from_reg, LIR_Opr to_reg) {
1431 if (from_reg->is_float_kind() && to_reg->is_float_kind()) {
1432 if (from_reg->is_double_fpu()) {
1433 // double to double moves
1434 assert(to_reg->is_double_fpu(), "should match");
1435 __ fmov(FloatRegisterImpl::D, from_reg->as_double_reg(), to_reg->as_double_reg());
1436 } else {
1437 // float to float moves
1438 assert(to_reg->is_single_fpu(), "should match");
1439 __ fmov(FloatRegisterImpl::S, from_reg->as_float_reg(), to_reg->as_float_reg());
1440 }
1441 } else if (!from_reg->is_float_kind() && !to_reg->is_float_kind()) {
1442 if (from_reg->is_double_cpu()) {
1443 #ifdef _LP64
1444 __ mov(from_reg->as_pointer_register(), to_reg->as_pointer_register());
1445 #else
1446 assert(to_reg->is_double_cpu() &&
1447 from_reg->as_register_hi() != to_reg->as_register_lo() &&
1448 from_reg->as_register_lo() != to_reg->as_register_hi(),
1449 "should both be long and not overlap");
1450 // long to long moves
1451 __ mov(from_reg->as_register_hi(), to_reg->as_register_hi());
1452 __ mov(from_reg->as_register_lo(), to_reg->as_register_lo());
1453 #endif
1454 #ifdef _LP64
1455 } else if (to_reg->is_double_cpu()) {
1456 // int to int moves
1457 __ mov(from_reg->as_register(), to_reg->as_register_lo());
1458 #endif
1459 } else {
1460 // int to int moves
1461 __ mov(from_reg->as_register(), to_reg->as_register());
1462 }
1463 } else {
1464 ShouldNotReachHere();
1465 }
1466 if (to_reg->type() == T_OBJECT || to_reg->type() == T_ARRAY) {
1467 __ verify_oop(to_reg->as_register());
1468 }
1469 }
1470
1471
1472 void LIR_Assembler::reg2mem(LIR_Opr from_reg, LIR_Opr dest, BasicType type,
1473 LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack,
1474 bool wide, bool unaligned) {
1475 LIR_Address* addr = dest->as_address_ptr();
1476
1477 Register src = addr->base()->as_pointer_register();
1478 Register disp_reg = noreg;
1479 int disp_value = addr->disp();
1480 bool needs_patching = (patch_code != lir_patch_none);
1481
1482 if (addr->base()->is_oop_register()) {
1483 __ verify_oop(src);
1484 }
1485
1486 PatchingStub* patch = NULL;
1487 if (needs_patching) {
1488 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1489 assert(!from_reg->is_double_cpu() ||
1490 patch_code == lir_patch_none ||
1491 patch_code == lir_patch_normal, "patching doesn't match register");
1492 }
1493
1494 if (addr->index()->is_illegal()) {
1495 if (!Assembler::is_simm13(disp_value) && (!unaligned || Assembler::is_simm13(disp_value + 4))) {
1496 if (needs_patching) {
1497 __ patchable_set(0, O7);
1498 } else {
1499 __ set(disp_value, O7);
1500 }
1501 disp_reg = O7;
1502 }
1503 } else if (unaligned || PatchALot) {
1504 __ add(src, addr->index()->as_register(), O7);
1505 src = O7;
1506 } else {
1507 disp_reg = addr->index()->as_pointer_register();
1508 assert(disp_value == 0, "can't handle 3 operand addresses");
1509 }
1510
1511 // remember the offset of the store. The patching_epilog must be done
1512 // before the call to add_debug_info_for_null_check, otherwise the PcDescs don't get
1513 // entered in increasing order.
1514 int offset;
1515
1516 assert(disp_reg != noreg || Assembler::is_simm13(disp_value), "should have set this up");
1517 if (disp_reg == noreg) {
1518 offset = store(from_reg, src, disp_value, type, wide, unaligned);
1519 } else {
1520 assert(!unaligned, "can't handle this");
1521 offset = store(from_reg, src, disp_reg, type, wide);
1522 }
1523
1524 if (patch != NULL) {
1525 patching_epilog(patch, patch_code, src, info);
1526 }
1527
1528 if (info != NULL) add_debug_info_for_null_check(offset, info);
1529 }
1530
1531
1532 void LIR_Assembler::return_op(LIR_Opr result) {
1533 // the poll may need a register so just pick one that isn't the return register
1534 #if defined(TIERED) && !defined(_LP64)
1535 if (result->type_field() == LIR_OprDesc::long_type) {
1536 // Must move the result to G1
1537 // Must leave proper result in O0,O1 and G1 (TIERED only)
1538 __ sllx(I0, 32, G1); // Shift bits into high G1
1539 __ srl (I1, 0, I1); // Zero extend O1 (harmless?)
1540 __ or3 (I1, G1, G1); // OR 64 bits into G1
1541 #ifdef ASSERT
1542 // mangle it so any problems will show up
1543 __ set(0xdeadbeef, I0);
1544 __ set(0xdeadbeef, I1);
1545 #endif
1546 }
1547 #endif // TIERED
1548 __ set((intptr_t)os::get_polling_page(), L0);
1549 __ relocate(relocInfo::poll_return_type);
1550 __ ld_ptr(L0, 0, G0);
1551 __ ret();
1552 __ delayed()->restore();
1553 }
1554
1555
1556 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) {
1557 __ set((intptr_t)os::get_polling_page(), tmp->as_register());
1558 if (info != NULL) {
1559 add_debug_info_for_branch(info);
1560 } else {
1561 __ relocate(relocInfo::poll_type);
1562 }
1563
1564 int offset = __ offset();
1565 __ ld_ptr(tmp->as_register(), 0, G0);
1566
1567 return offset;
1568 }
1569
1570
1571 void LIR_Assembler::emit_static_call_stub() {
1572 address call_pc = __ pc();
1573 address stub = __ start_a_stub(call_stub_size);
1574 if (stub == NULL) {
1575 bailout("static call stub overflow");
1576 return;
1577 }
1578
1579 int start = __ offset();
1580 __ relocate(static_stub_Relocation::spec(call_pc));
1581
1582 __ set_oop(NULL, G5);
1583 // must be set to -1 at code generation time
1584 AddressLiteral addrlit(-1);
1585 __ jump_to(addrlit, G3);
1586 __ delayed()->nop();
1587
1588 assert(__ offset() - start <= call_stub_size, "stub too big");
1589 __ end_a_stub();
1590 }
1591
1592
1593 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) {
1594 if (opr1->is_single_fpu()) {
1595 __ fcmp(FloatRegisterImpl::S, Assembler::fcc0, opr1->as_float_reg(), opr2->as_float_reg());
1596 } else if (opr1->is_double_fpu()) {
1597 __ fcmp(FloatRegisterImpl::D, Assembler::fcc0, opr1->as_double_reg(), opr2->as_double_reg());
1598 } else if (opr1->is_single_cpu()) {
1599 if (opr2->is_constant()) {
1600 switch (opr2->as_constant_ptr()->type()) {
1601 case T_INT:
1602 { jint con = opr2->as_constant_ptr()->as_jint();
1603 if (Assembler::is_simm13(con)) {
1604 __ cmp(opr1->as_register(), con);
1605 } else {
1606 __ set(con, O7);
1607 __ cmp(opr1->as_register(), O7);
1608 }
1609 }
1610 break;
1611
1612 case T_OBJECT:
1613 // there are only equal/notequal comparisions on objects
1614 { jobject con = opr2->as_constant_ptr()->as_jobject();
1615 if (con == NULL) {
1616 __ cmp(opr1->as_register(), 0);
1617 } else {
1618 jobject2reg(con, O7);
1619 __ cmp(opr1->as_register(), O7);
1620 }
1621 }
1622 break;
1623
1624 default:
1625 ShouldNotReachHere();
1626 break;
1627 }
1628 } else {
1629 if (opr2->is_address()) {
1630 LIR_Address * addr = opr2->as_address_ptr();
1631 BasicType type = addr->type();
1632 if ( type == T_OBJECT ) __ ld_ptr(as_Address(addr), O7);
1633 else __ ld(as_Address(addr), O7);
1634 __ cmp(opr1->as_register(), O7);
1635 } else {
1636 __ cmp(opr1->as_register(), opr2->as_register());
1637 }
1638 }
1639 } else if (opr1->is_double_cpu()) {
1640 Register xlo = opr1->as_register_lo();
1641 Register xhi = opr1->as_register_hi();
1642 if (opr2->is_constant() && opr2->as_jlong() == 0) {
1643 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "only handles these cases");
1644 #ifdef _LP64
1645 __ orcc(xhi, G0, G0);
1646 #else
1647 __ orcc(xhi, xlo, G0);
1648 #endif
1649 } else if (opr2->is_register()) {
1650 Register ylo = opr2->as_register_lo();
1651 Register yhi = opr2->as_register_hi();
1652 #ifdef _LP64
1653 __ cmp(xlo, ylo);
1654 #else
1655 __ subcc(xlo, ylo, xlo);
1656 __ subccc(xhi, yhi, xhi);
1657 if (condition == lir_cond_equal || condition == lir_cond_notEqual) {
1658 __ orcc(xhi, xlo, G0);
1659 }
1660 #endif
1661 } else {
1662 ShouldNotReachHere();
1663 }
1664 } else if (opr1->is_address()) {
1665 LIR_Address * addr = opr1->as_address_ptr();
1666 BasicType type = addr->type();
1667 assert (opr2->is_constant(), "Checking");
1668 if ( type == T_OBJECT ) __ ld_ptr(as_Address(addr), O7);
1669 else __ ld(as_Address(addr), O7);
1670 __ cmp(O7, opr2->as_constant_ptr()->as_jint());
1671 } else {
1672 ShouldNotReachHere();
1673 }
1674 }
1675
1676
1677 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op){
1678 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) {
1679 bool is_unordered_less = (code == lir_ucmp_fd2i);
1680 if (left->is_single_fpu()) {
1681 __ float_cmp(true, is_unordered_less ? -1 : 1, left->as_float_reg(), right->as_float_reg(), dst->as_register());
1682 } else if (left->is_double_fpu()) {
1683 __ float_cmp(false, is_unordered_less ? -1 : 1, left->as_double_reg(), right->as_double_reg(), dst->as_register());
1684 } else {
1685 ShouldNotReachHere();
1686 }
1687 } else if (code == lir_cmp_l2i) {
1688 #ifdef _LP64
1689 __ lcmp(left->as_register_lo(), right->as_register_lo(), dst->as_register());
1690 #else
1691 __ lcmp(left->as_register_hi(), left->as_register_lo(),
1692 right->as_register_hi(), right->as_register_lo(),
1693 dst->as_register());
1694 #endif
1695 } else {
1696 ShouldNotReachHere();
1697 }
1698 }
1699
1700
1701 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type) {
1702 Assembler::Condition acond;
1703 switch (condition) {
1704 case lir_cond_equal: acond = Assembler::equal; break;
1705 case lir_cond_notEqual: acond = Assembler::notEqual; break;
1706 case lir_cond_less: acond = Assembler::less; break;
1707 case lir_cond_lessEqual: acond = Assembler::lessEqual; break;
1708 case lir_cond_greaterEqual: acond = Assembler::greaterEqual; break;
1709 case lir_cond_greater: acond = Assembler::greater; break;
1710 case lir_cond_aboveEqual: acond = Assembler::greaterEqualUnsigned; break;
1711 case lir_cond_belowEqual: acond = Assembler::lessEqualUnsigned; break;
1712 default: ShouldNotReachHere();
1713 };
1714
1715 if (opr1->is_constant() && opr1->type() == T_INT) {
1716 Register dest = result->as_register();
1717 // load up first part of constant before branch
1718 // and do the rest in the delay slot.
1719 if (!Assembler::is_simm13(opr1->as_jint())) {
1720 __ sethi(opr1->as_jint(), dest);
1721 }
1722 } else if (opr1->is_constant()) {
1723 const2reg(opr1, result, lir_patch_none, NULL);
1724 } else if (opr1->is_register()) {
1725 reg2reg(opr1, result);
1726 } else if (opr1->is_stack()) {
1727 stack2reg(opr1, result, result->type());
1728 } else {
1729 ShouldNotReachHere();
1730 }
1731 Label skip;
1732 #ifdef _LP64
1733 if (type == T_INT) {
1734 __ br(acond, false, Assembler::pt, skip);
1735 } else
1736 #endif
1737 __ brx(acond, false, Assembler::pt, skip); // checks icc on 32bit and xcc on 64bit
1738 if (opr1->is_constant() && opr1->type() == T_INT) {
1739 Register dest = result->as_register();
1740 if (Assembler::is_simm13(opr1->as_jint())) {
1741 __ delayed()->or3(G0, opr1->as_jint(), dest);
1742 } else {
1743 // the sethi has been done above, so just put in the low 10 bits
1744 __ delayed()->or3(dest, opr1->as_jint() & 0x3ff, dest);
1745 }
1746 } else {
1747 // can't do anything useful in the delay slot
1748 __ delayed()->nop();
1749 }
1750 if (opr2->is_constant()) {
1751 const2reg(opr2, result, lir_patch_none, NULL);
1752 } else if (opr2->is_register()) {
1753 reg2reg(opr2, result);
1754 } else if (opr2->is_stack()) {
1755 stack2reg(opr2, result, result->type());
1756 } else {
1757 ShouldNotReachHere();
1758 }
1759 __ bind(skip);
1760 }
1761
1762
1763 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack) {
1764 assert(info == NULL, "unused on this code path");
1765 assert(left->is_register(), "wrong items state");
1766 assert(dest->is_register(), "wrong items state");
1767
1768 if (right->is_register()) {
1769 if (dest->is_float_kind()) {
1770
1771 FloatRegister lreg, rreg, res;
1772 FloatRegisterImpl::Width w;
1773 if (right->is_single_fpu()) {
1774 w = FloatRegisterImpl::S;
1775 lreg = left->as_float_reg();
1776 rreg = right->as_float_reg();
1777 res = dest->as_float_reg();
1778 } else {
1779 w = FloatRegisterImpl::D;
1780 lreg = left->as_double_reg();
1781 rreg = right->as_double_reg();
1782 res = dest->as_double_reg();
1783 }
1784
1785 switch (code) {
1786 case lir_add: __ fadd(w, lreg, rreg, res); break;
1787 case lir_sub: __ fsub(w, lreg, rreg, res); break;
1788 case lir_mul: // fall through
1789 case lir_mul_strictfp: __ fmul(w, lreg, rreg, res); break;
1790 case lir_div: // fall through
1791 case lir_div_strictfp: __ fdiv(w, lreg, rreg, res); break;
1792 default: ShouldNotReachHere();
1793 }
1794
1795 } else if (dest->is_double_cpu()) {
1796 #ifdef _LP64
1797 Register dst_lo = dest->as_register_lo();
1798 Register op1_lo = left->as_pointer_register();
1799 Register op2_lo = right->as_pointer_register();
1800
1801 switch (code) {
1802 case lir_add:
1803 __ add(op1_lo, op2_lo, dst_lo);
1804 break;
1805
1806 case lir_sub:
1807 __ sub(op1_lo, op2_lo, dst_lo);
1808 break;
1809
1810 default: ShouldNotReachHere();
1811 }
1812 #else
1813 Register op1_lo = left->as_register_lo();
1814 Register op1_hi = left->as_register_hi();
1815 Register op2_lo = right->as_register_lo();
1816 Register op2_hi = right->as_register_hi();
1817 Register dst_lo = dest->as_register_lo();
1818 Register dst_hi = dest->as_register_hi();
1819
1820 switch (code) {
1821 case lir_add:
1822 __ addcc(op1_lo, op2_lo, dst_lo);
1823 __ addc (op1_hi, op2_hi, dst_hi);
1824 break;
1825
1826 case lir_sub:
1827 __ subcc(op1_lo, op2_lo, dst_lo);
1828 __ subc (op1_hi, op2_hi, dst_hi);
1829 break;
1830
1831 default: ShouldNotReachHere();
1832 }
1833 #endif
1834 } else {
1835 assert (right->is_single_cpu(), "Just Checking");
1836
1837 Register lreg = left->as_register();
1838 Register res = dest->as_register();
1839 Register rreg = right->as_register();
1840 switch (code) {
1841 case lir_add: __ add (lreg, rreg, res); break;
1842 case lir_sub: __ sub (lreg, rreg, res); break;
1843 case lir_mul: __ mult (lreg, rreg, res); break;
1844 default: ShouldNotReachHere();
1845 }
1846 }
1847 } else {
1848 assert (right->is_constant(), "must be constant");
1849
1850 if (dest->is_single_cpu()) {
1851 Register lreg = left->as_register();
1852 Register res = dest->as_register();
1853 int simm13 = right->as_constant_ptr()->as_jint();
1854
1855 switch (code) {
1856 case lir_add: __ add (lreg, simm13, res); break;
1857 case lir_sub: __ sub (lreg, simm13, res); break;
1858 case lir_mul: __ mult (lreg, simm13, res); break;
1859 default: ShouldNotReachHere();
1860 }
1861 } else {
1862 Register lreg = left->as_pointer_register();
1863 Register res = dest->as_register_lo();
1864 long con = right->as_constant_ptr()->as_jlong();
1865 assert(Assembler::is_simm13(con), "must be simm13");
1866
1867 switch (code) {
1868 case lir_add: __ add (lreg, (int)con, res); break;
1869 case lir_sub: __ sub (lreg, (int)con, res); break;
1870 case lir_mul: __ mult (lreg, (int)con, res); break;
1871 default: ShouldNotReachHere();
1872 }
1873 }
1874 }
1875 }
1876
1877
1878 void LIR_Assembler::fpop() {
1879 // do nothing
1880 }
1881
1882
1883 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr thread, LIR_Opr dest, LIR_Op* op) {
1884 switch (code) {
1885 case lir_sin:
1886 case lir_tan:
1887 case lir_cos: {
1888 assert(thread->is_valid(), "preserve the thread object for performance reasons");
1889 assert(dest->as_double_reg() == F0, "the result will be in f0/f1");
1890 break;
1891 }
1892 case lir_sqrt: {
1893 assert(!thread->is_valid(), "there is no need for a thread_reg for dsqrt");
1894 FloatRegister src_reg = value->as_double_reg();
1895 FloatRegister dst_reg = dest->as_double_reg();
1896 __ fsqrt(FloatRegisterImpl::D, src_reg, dst_reg);
1897 break;
1898 }
1899 case lir_abs: {
1900 assert(!thread->is_valid(), "there is no need for a thread_reg for fabs");
1901 FloatRegister src_reg = value->as_double_reg();
1902 FloatRegister dst_reg = dest->as_double_reg();
1903 __ fabs(FloatRegisterImpl::D, src_reg, dst_reg);
1904 break;
1905 }
1906 default: {
1907 ShouldNotReachHere();
1908 break;
1909 }
1910 }
1911 }
1912
1913
1914 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest) {
1915 if (right->is_constant()) {
1916 if (dest->is_single_cpu()) {
1917 int simm13 = right->as_constant_ptr()->as_jint();
1918 switch (code) {
1919 case lir_logic_and: __ and3 (left->as_register(), simm13, dest->as_register()); break;
1920 case lir_logic_or: __ or3 (left->as_register(), simm13, dest->as_register()); break;
1921 case lir_logic_xor: __ xor3 (left->as_register(), simm13, dest->as_register()); break;
1922 default: ShouldNotReachHere();
1923 }
1924 } else {
1925 long c = right->as_constant_ptr()->as_jlong();
1926 assert(c == (int)c && Assembler::is_simm13(c), "out of range");
1927 int simm13 = (int)c;
1928 switch (code) {
1929 case lir_logic_and:
1930 #ifndef _LP64
1931 __ and3 (left->as_register_hi(), 0, dest->as_register_hi());
1932 #endif
1933 __ and3 (left->as_register_lo(), simm13, dest->as_register_lo());
1934 break;
1935
1936 case lir_logic_or:
1937 #ifndef _LP64
1938 __ or3 (left->as_register_hi(), 0, dest->as_register_hi());
1939 #endif
1940 __ or3 (left->as_register_lo(), simm13, dest->as_register_lo());
1941 break;
1942
1943 case lir_logic_xor:
1944 #ifndef _LP64
1945 __ xor3 (left->as_register_hi(), 0, dest->as_register_hi());
1946 #endif
1947 __ xor3 (left->as_register_lo(), simm13, dest->as_register_lo());
1948 break;
1949
1950 default: ShouldNotReachHere();
1951 }
1952 }
1953 } else {
1954 assert(right->is_register(), "right should be in register");
1955
1956 if (dest->is_single_cpu()) {
1957 switch (code) {
1958 case lir_logic_and: __ and3 (left->as_register(), right->as_register(), dest->as_register()); break;
1959 case lir_logic_or: __ or3 (left->as_register(), right->as_register(), dest->as_register()); break;
1960 case lir_logic_xor: __ xor3 (left->as_register(), right->as_register(), dest->as_register()); break;
1961 default: ShouldNotReachHere();
1962 }
1963 } else {
1964 #ifdef _LP64
1965 Register l = (left->is_single_cpu() && left->is_oop_register()) ? left->as_register() :
1966 left->as_register_lo();
1967 Register r = (right->is_single_cpu() && right->is_oop_register()) ? right->as_register() :
1968 right->as_register_lo();
1969
1970 switch (code) {
1971 case lir_logic_and: __ and3 (l, r, dest->as_register_lo()); break;
1972 case lir_logic_or: __ or3 (l, r, dest->as_register_lo()); break;
1973 case lir_logic_xor: __ xor3 (l, r, dest->as_register_lo()); break;
1974 default: ShouldNotReachHere();
1975 }
1976 #else
1977 switch (code) {
1978 case lir_logic_and:
1979 __ and3 (left->as_register_hi(), right->as_register_hi(), dest->as_register_hi());
1980 __ and3 (left->as_register_lo(), right->as_register_lo(), dest->as_register_lo());
1981 break;
1982
1983 case lir_logic_or:
1984 __ or3 (left->as_register_hi(), right->as_register_hi(), dest->as_register_hi());
1985 __ or3 (left->as_register_lo(), right->as_register_lo(), dest->as_register_lo());
1986 break;
1987
1988 case lir_logic_xor:
1989 __ xor3 (left->as_register_hi(), right->as_register_hi(), dest->as_register_hi());
1990 __ xor3 (left->as_register_lo(), right->as_register_lo(), dest->as_register_lo());
1991 break;
1992
1993 default: ShouldNotReachHere();
1994 }
1995 #endif
1996 }
1997 }
1998 }
1999
2000
2001 int LIR_Assembler::shift_amount(BasicType t) {
2002 int elem_size = type2aelembytes(t);
2003 switch (elem_size) {
2004 case 1 : return 0;
2005 case 2 : return 1;
2006 case 4 : return 2;
2007 case 8 : return 3;
2008 }
2009 ShouldNotReachHere();
2010 return -1;
2011 }
2012
2013
2014 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) {
2015 assert(exceptionOop->as_register() == Oexception, "should match");
2016 assert(exceptionPC->as_register() == Oissuing_pc, "should match");
2017
2018 info->add_register_oop(exceptionOop);
2019
2020 // reuse the debug info from the safepoint poll for the throw op itself
2021 address pc_for_athrow = __ pc();
2022 int pc_for_athrow_offset = __ offset();
2023 RelocationHolder rspec = internal_word_Relocation::spec(pc_for_athrow);
2024 __ set(pc_for_athrow, Oissuing_pc, rspec);
2025 add_call_info(pc_for_athrow_offset, info); // for exception handler
2026
2027 __ call(Runtime1::entry_for(Runtime1::handle_exception_id), relocInfo::runtime_call_type);
2028 __ delayed()->nop();
2029 }
2030
2031
2032 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) {
2033 assert(exceptionOop->as_register() == Oexception, "should match");
2034
2035 __ br(Assembler::always, false, Assembler::pt, _unwind_handler_entry);
2036 __ delayed()->nop();
2037 }
2038
2039
2040 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
2041 Register src = op->src()->as_register();
2042 Register dst = op->dst()->as_register();
2043 Register src_pos = op->src_pos()->as_register();
2044 Register dst_pos = op->dst_pos()->as_register();
2045 Register length = op->length()->as_register();
2046 Register tmp = op->tmp()->as_register();
2047 Register tmp2 = O7;
2048
2049 int flags = op->flags();
2050 ciArrayKlass* default_type = op->expected_type();
2051 BasicType basic_type = default_type != NULL ? default_type->element_type()->basic_type() : T_ILLEGAL;
2052 if (basic_type == T_ARRAY) basic_type = T_OBJECT;
2053
2054 #ifdef _LP64
2055 // higher 32bits must be null
2056 __ sra(dst_pos, 0, dst_pos);
2057 __ sra(src_pos, 0, src_pos);
2058 __ sra(length, 0, length);
2059 #endif
2060
2061 // set up the arraycopy stub information
2062 ArrayCopyStub* stub = op->stub();
2063
2064 // always do stub if no type information is available. it's ok if
2065 // the known type isn't loaded since the code sanity checks
2066 // in debug mode and the type isn't required when we know the exact type
2067 // also check that the type is an array type.
2068 if (op->expected_type() == NULL) {
2069 __ mov(src, O0);
2070 __ mov(src_pos, O1);
2071 __ mov(dst, O2);
2072 __ mov(dst_pos, O3);
2073 __ mov(length, O4);
2074 address copyfunc_addr = StubRoutines::generic_arraycopy();
2075
2076 if (copyfunc_addr == NULL) { // Use C version if stub was not generated
2077 __ call_VM_leaf(tmp, CAST_FROM_FN_PTR(address, Runtime1::arraycopy));
2078 } else {
2079 #ifndef PRODUCT
2080 if (PrintC1Statistics) {
2081 address counter = (address)&Runtime1::_generic_arraycopystub_cnt;
2082 __ inc_counter(counter, G1, G3);
2083 }
2084 #endif
2085 __ call_VM_leaf(tmp, copyfunc_addr);
2086 }
2087
2088 if (copyfunc_addr != NULL) {
2089 __ xor3(O0, -1, tmp);
2090 __ sub(length, tmp, length);
2091 __ add(src_pos, tmp, src_pos);
2092 __ cmp_zero_and_br(Assembler::less, O0, *stub->entry());
2093 __ delayed()->add(dst_pos, tmp, dst_pos);
2094 } else {
2095 __ cmp_zero_and_br(Assembler::less, O0, *stub->entry());
2096 __ delayed()->nop();
2097 }
2098 __ bind(*stub->continuation());
2099 return;
2100 }
2101
2102 assert(default_type != NULL && default_type->is_array_klass(), "must be true at this point");
2103
2104 // make sure src and dst are non-null and load array length
2105 if (flags & LIR_OpArrayCopy::src_null_check) {
2106 __ tst(src);
2107 __ brx(Assembler::equal, false, Assembler::pn, *stub->entry());
2108 __ delayed()->nop();
2109 }
2110
2111 if (flags & LIR_OpArrayCopy::dst_null_check) {
2112 __ tst(dst);
2113 __ brx(Assembler::equal, false, Assembler::pn, *stub->entry());
2114 __ delayed()->nop();
2115 }
2116
2117 if (flags & LIR_OpArrayCopy::src_pos_positive_check) {
2118 // test src_pos register
2119 __ cmp_zero_and_br(Assembler::less, src_pos, *stub->entry());
2120 __ delayed()->nop();
2121 }
2122
2123 if (flags & LIR_OpArrayCopy::dst_pos_positive_check) {
2124 // test dst_pos register
2125 __ cmp_zero_and_br(Assembler::less, dst_pos, *stub->entry());
2126 __ delayed()->nop();
2127 }
2128
2129 if (flags & LIR_OpArrayCopy::length_positive_check) {
2130 // make sure length isn't negative
2131 __ cmp_zero_and_br(Assembler::less, length, *stub->entry());
2132 __ delayed()->nop();
2133 }
2134
2135 if (flags & LIR_OpArrayCopy::src_range_check) {
2136 __ ld(src, arrayOopDesc::length_offset_in_bytes(), tmp2);
2137 __ add(length, src_pos, tmp);
2138 __ cmp(tmp2, tmp);
2139 __ br(Assembler::carrySet, false, Assembler::pn, *stub->entry());
2140 __ delayed()->nop();
2141 }
2142
2143 if (flags & LIR_OpArrayCopy::dst_range_check) {
2144 __ ld(dst, arrayOopDesc::length_offset_in_bytes(), tmp2);
2145 __ add(length, dst_pos, tmp);
2146 __ cmp(tmp2, tmp);
2147 __ br(Assembler::carrySet, false, Assembler::pn, *stub->entry());
2148 __ delayed()->nop();
2149 }
2150
2151 int shift = shift_amount(basic_type);
2152
2153 if (flags & LIR_OpArrayCopy::type_check) {
2154 // We don't know the array types are compatible
2155 if (basic_type != T_OBJECT) {
2156 // Simple test for basic type arrays
2157 if (UseCompressedOops) {
2158 // We don't need decode because we just need to compare
2159 __ lduw(src, oopDesc::klass_offset_in_bytes(), tmp);
2160 __ lduw(dst, oopDesc::klass_offset_in_bytes(), tmp2);
2161 __ cmp(tmp, tmp2);
2162 __ br(Assembler::notEqual, false, Assembler::pt, *stub->entry());
2163 } else {
2164 __ ld_ptr(src, oopDesc::klass_offset_in_bytes(), tmp);
2165 __ ld_ptr(dst, oopDesc::klass_offset_in_bytes(), tmp2);
2166 __ cmp(tmp, tmp2);
2167 __ brx(Assembler::notEqual, false, Assembler::pt, *stub->entry());
2168 }
2169 __ delayed()->nop();
2170 } else {
2171 // For object arrays, if src is a sub class of dst then we can
2172 // safely do the copy.
2173 address copyfunc_addr = StubRoutines::checkcast_arraycopy();
2174
2175 Label cont, slow;
2176 assert_different_registers(tmp, tmp2, G3, G1);
2177
2178 __ load_klass(src, G3);
2179 __ load_klass(dst, G1);
2180
2181 __ check_klass_subtype_fast_path(G3, G1, tmp, tmp2, &cont, copyfunc_addr == NULL ? stub->entry() : &slow, NULL);
2182
2183 __ call(Runtime1::entry_for(Runtime1::slow_subtype_check_id), relocInfo::runtime_call_type);
2184 __ delayed()->nop();
2185
2186 __ cmp(G3, 0);
2187 if (copyfunc_addr != NULL) { // use stub if available
2188 // src is not a sub class of dst so we have to do a
2189 // per-element check.
2190 __ br(Assembler::notEqual, false, Assembler::pt, cont);
2191 __ delayed()->nop();
2192
2193 __ bind(slow);
2194
2195 int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray;
2196 if ((flags & mask) != mask) {
2197 // Check that at least both of them object arrays.
2198 assert(flags & mask, "one of the two should be known to be an object array");
2199
2200 if (!(flags & LIR_OpArrayCopy::src_objarray)) {
2201 __ load_klass(src, tmp);
2202 } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
2203 __ load_klass(dst, tmp);
2204 }
2205 int lh_offset = klassOopDesc::header_size() * HeapWordSize +
2206 Klass::layout_helper_offset_in_bytes();
2207
2208 __ lduw(tmp, lh_offset, tmp2);
2209
2210 jint objArray_lh = Klass::array_layout_helper(T_OBJECT);
2211 __ set(objArray_lh, tmp);
2212 __ cmp(tmp, tmp2);
2213 __ br(Assembler::notEqual, false, Assembler::pt, *stub->entry());
2214 __ delayed()->nop();
2215 }
2216
2217 Register src_ptr = O0;
2218 Register dst_ptr = O1;
2219 Register len = O2;
2220 Register chk_off = O3;
2221 Register super_k = O4;
2222
2223 __ add(src, arrayOopDesc::base_offset_in_bytes(basic_type), src_ptr);
2224 if (shift == 0) {
2225 __ add(src_ptr, src_pos, src_ptr);
2226 } else {
2227 __ sll(src_pos, shift, tmp);
2228 __ add(src_ptr, tmp, src_ptr);
2229 }
2230
2231 __ add(dst, arrayOopDesc::base_offset_in_bytes(basic_type), dst_ptr);
2232 if (shift == 0) {
2233 __ add(dst_ptr, dst_pos, dst_ptr);
2234 } else {
2235 __ sll(dst_pos, shift, tmp);
2236 __ add(dst_ptr, tmp, dst_ptr);
2237 }
2238 __ mov(length, len);
2239 __ load_klass(dst, tmp);
2240
2241 int ek_offset = (klassOopDesc::header_size() * HeapWordSize +
2242 objArrayKlass::element_klass_offset_in_bytes());
2243 __ ld_ptr(tmp, ek_offset, super_k);
2244
2245 int sco_offset = (klassOopDesc::header_size() * HeapWordSize +
2246 Klass::super_check_offset_offset_in_bytes());
2247 __ lduw(super_k, sco_offset, chk_off);
2248
2249 __ call_VM_leaf(tmp, copyfunc_addr);
2250
2251 #ifndef PRODUCT
2252 if (PrintC1Statistics) {
2253 Label failed;
2254 __ br_notnull_short(O0, Assembler::pn, failed);
2255 __ inc_counter((address)&Runtime1::_arraycopy_checkcast_cnt, G1, G3);
2256 __ bind(failed);
2257 }
2258 #endif
2259
2260 __ br_null(O0, false, Assembler::pt, *stub->continuation());
2261 __ delayed()->xor3(O0, -1, tmp);
2262
2263 #ifndef PRODUCT
2264 if (PrintC1Statistics) {
2265 __ inc_counter((address)&Runtime1::_arraycopy_checkcast_attempt_cnt, G1, G3);
2266 }
2267 #endif
2268
2269 __ sub(length, tmp, length);
2270 __ add(src_pos, tmp, src_pos);
2271 __ br(Assembler::always, false, Assembler::pt, *stub->entry());
2272 __ delayed()->add(dst_pos, tmp, dst_pos);
2273
2274 __ bind(cont);
2275 } else {
2276 __ br(Assembler::equal, false, Assembler::pn, *stub->entry());
2277 __ delayed()->nop();
2278 __ bind(cont);
2279 }
2280 }
2281 }
2282
2283 #ifdef ASSERT
2284 if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) {
2285 // Sanity check the known type with the incoming class. For the
2286 // primitive case the types must match exactly with src.klass and
2287 // dst.klass each exactly matching the default type. For the
2288 // object array case, if no type check is needed then either the
2289 // dst type is exactly the expected type and the src type is a
2290 // subtype which we can't check or src is the same array as dst
2291 // but not necessarily exactly of type default_type.
2292 Label known_ok, halt;
2293 jobject2reg(op->expected_type()->constant_encoding(), tmp);
2294 if (UseCompressedOops) {
2295 // tmp holds the default type. It currently comes uncompressed after the
2296 // load of a constant, so encode it.
2297 __ encode_heap_oop(tmp);
2298 // load the raw value of the dst klass, since we will be comparing
2299 // uncompressed values directly.
2300 __ lduw(dst, oopDesc::klass_offset_in_bytes(), tmp2);
2301 if (basic_type != T_OBJECT) {
2302 __ cmp(tmp, tmp2);
2303 __ br(Assembler::notEqual, false, Assembler::pn, halt);
2304 // load the raw value of the src klass.
2305 __ delayed()->lduw(src, oopDesc::klass_offset_in_bytes(), tmp2);
2306 __ cmp_and_br_short(tmp, tmp2, Assembler::equal, Assembler::pn, known_ok);
2307 } else {
2308 __ cmp(tmp, tmp2);
2309 __ br(Assembler::equal, false, Assembler::pn, known_ok);
2310 __ delayed()->cmp(src, dst);
2311 __ brx(Assembler::equal, false, Assembler::pn, known_ok);
2312 __ delayed()->nop();
2313 }
2314 } else {
2315 __ ld_ptr(dst, oopDesc::klass_offset_in_bytes(), tmp2);
2316 if (basic_type != T_OBJECT) {
2317 __ cmp(tmp, tmp2);
2318 __ brx(Assembler::notEqual, false, Assembler::pn, halt);
2319 __ delayed()->ld_ptr(src, oopDesc::klass_offset_in_bytes(), tmp2);
2320 __ cmp_and_brx_short(tmp, tmp2, Assembler::equal, Assembler::pn, known_ok);
2321 } else {
2322 __ cmp(tmp, tmp2);
2323 __ brx(Assembler::equal, false, Assembler::pn, known_ok);
2324 __ delayed()->cmp(src, dst);
2325 __ brx(Assembler::equal, false, Assembler::pn, known_ok);
2326 __ delayed()->nop();
2327 }
2328 }
2329 __ bind(halt);
2330 __ stop("incorrect type information in arraycopy");
2331 __ bind(known_ok);
2332 }
2333 #endif
2334
2335 #ifndef PRODUCT
2336 if (PrintC1Statistics) {
2337 address counter = Runtime1::arraycopy_count_address(basic_type);
2338 __ inc_counter(counter, G1, G3);
2339 }
2340 #endif
2341
2342 Register src_ptr = O0;
2343 Register dst_ptr = O1;
2344 Register len = O2;
2345
2346 __ add(src, arrayOopDesc::base_offset_in_bytes(basic_type), src_ptr);
2347 if (shift == 0) {
2348 __ add(src_ptr, src_pos, src_ptr);
2349 } else {
2350 __ sll(src_pos, shift, tmp);
2351 __ add(src_ptr, tmp, src_ptr);
2352 }
2353
2354 __ add(dst, arrayOopDesc::base_offset_in_bytes(basic_type), dst_ptr);
2355 if (shift == 0) {
2356 __ add(dst_ptr, dst_pos, dst_ptr);
2357 } else {
2358 __ sll(dst_pos, shift, tmp);
2359 __ add(dst_ptr, tmp, dst_ptr);
2360 }
2361
2362 bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0;
2363 bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0;
2364 const char *name;
2365 address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false);
2366
2367 // arraycopy stubs takes a length in number of elements, so don't scale it.
2368 __ mov(length, len);
2369 __ call_VM_leaf(tmp, entry);
2370
2371 __ bind(*stub->continuation());
2372 }
2373
2374
2375 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) {
2376 if (dest->is_single_cpu()) {
2377 #ifdef _LP64
2378 if (left->type() == T_OBJECT) {
2379 switch (code) {
2380 case lir_shl: __ sllx (left->as_register(), count->as_register(), dest->as_register()); break;
2381 case lir_shr: __ srax (left->as_register(), count->as_register(), dest->as_register()); break;
2382 case lir_ushr: __ srl (left->as_register(), count->as_register(), dest->as_register()); break;
2383 default: ShouldNotReachHere();
2384 }
2385 } else
2386 #endif
2387 switch (code) {
2388 case lir_shl: __ sll (left->as_register(), count->as_register(), dest->as_register()); break;
2389 case lir_shr: __ sra (left->as_register(), count->as_register(), dest->as_register()); break;
2390 case lir_ushr: __ srl (left->as_register(), count->as_register(), dest->as_register()); break;
2391 default: ShouldNotReachHere();
2392 }
2393 } else {
2394 #ifdef _LP64
2395 switch (code) {
2396 case lir_shl: __ sllx (left->as_register_lo(), count->as_register(), dest->as_register_lo()); break;
2397 case lir_shr: __ srax (left->as_register_lo(), count->as_register(), dest->as_register_lo()); break;
2398 case lir_ushr: __ srlx (left->as_register_lo(), count->as_register(), dest->as_register_lo()); break;
2399 default: ShouldNotReachHere();
2400 }
2401 #else
2402 switch (code) {
2403 case lir_shl: __ lshl (left->as_register_hi(), left->as_register_lo(), count->as_register(), dest->as_register_hi(), dest->as_register_lo(), G3_scratch); break;
2404 case lir_shr: __ lshr (left->as_register_hi(), left->as_register_lo(), count->as_register(), dest->as_register_hi(), dest->as_register_lo(), G3_scratch); break;
2405 case lir_ushr: __ lushr (left->as_register_hi(), left->as_register_lo(), count->as_register(), dest->as_register_hi(), dest->as_register_lo(), G3_scratch); break;
2406 default: ShouldNotReachHere();
2407 }
2408 #endif
2409 }
2410 }
2411
2412
2413 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) {
2414 #ifdef _LP64
2415 if (left->type() == T_OBJECT) {
2416 count = count & 63; // shouldn't shift by more than sizeof(intptr_t)
2417 Register l = left->as_register();
2418 Register d = dest->as_register_lo();
2419 switch (code) {
2420 case lir_shl: __ sllx (l, count, d); break;
2421 case lir_shr: __ srax (l, count, d); break;
2422 case lir_ushr: __ srlx (l, count, d); break;
2423 default: ShouldNotReachHere();
2424 }
2425 return;
2426 }
2427 #endif
2428
2429 if (dest->is_single_cpu()) {
2430 count = count & 0x1F; // Java spec
2431 switch (code) {
2432 case lir_shl: __ sll (left->as_register(), count, dest->as_register()); break;
2433 case lir_shr: __ sra (left->as_register(), count, dest->as_register()); break;
2434 case lir_ushr: __ srl (left->as_register(), count, dest->as_register()); break;
2435 default: ShouldNotReachHere();
2436 }
2437 } else if (dest->is_double_cpu()) {
2438 count = count & 63; // Java spec
2439 switch (code) {
2440 case lir_shl: __ sllx (left->as_pointer_register(), count, dest->as_pointer_register()); break;
2441 case lir_shr: __ srax (left->as_pointer_register(), count, dest->as_pointer_register()); break;
2442 case lir_ushr: __ srlx (left->as_pointer_register(), count, dest->as_pointer_register()); break;
2443 default: ShouldNotReachHere();
2444 }
2445 } else {
2446 ShouldNotReachHere();
2447 }
2448 }
2449
2450
2451 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) {
2452 assert(op->tmp1()->as_register() == G1 &&
2453 op->tmp2()->as_register() == G3 &&
2454 op->tmp3()->as_register() == G4 &&
2455 op->obj()->as_register() == O0 &&
2456 op->klass()->as_register() == G5, "must be");
2457 if (op->init_check()) {
2458 __ ld(op->klass()->as_register(),
2459 instanceKlass::init_state_offset_in_bytes() + sizeof(oopDesc),
2460 op->tmp1()->as_register());
2461 add_debug_info_for_null_check_here(op->stub()->info());
2462 __ cmp(op->tmp1()->as_register(), instanceKlass::fully_initialized);
2463 __ br(Assembler::notEqual, false, Assembler::pn, *op->stub()->entry());
2464 __ delayed()->nop();
2465 }
2466 __ allocate_object(op->obj()->as_register(),
2467 op->tmp1()->as_register(),
2468 op->tmp2()->as_register(),
2469 op->tmp3()->as_register(),
2470 op->header_size(),
2471 op->object_size(),
2472 op->klass()->as_register(),
2473 *op->stub()->entry());
2474 __ bind(*op->stub()->continuation());
2475 __ verify_oop(op->obj()->as_register());
2476 }
2477
2478
2479 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) {
2480 assert(op->tmp1()->as_register() == G1 &&
2481 op->tmp2()->as_register() == G3 &&
2482 op->tmp3()->as_register() == G4 &&
2483 op->tmp4()->as_register() == O1 &&
2484 op->klass()->as_register() == G5, "must be");
2485
2486 LP64_ONLY( __ signx(op->len()->as_register()); )
2487 if (UseSlowPath ||
2488 (!UseFastNewObjectArray && (op->type() == T_OBJECT || op->type() == T_ARRAY)) ||
2489 (!UseFastNewTypeArray && (op->type() != T_OBJECT && op->type() != T_ARRAY))) {
2490 __ br(Assembler::always, false, Assembler::pt, *op->stub()->entry());
2491 __ delayed()->nop();
2492 } else {
2493 __ allocate_array(op->obj()->as_register(),
2494 op->len()->as_register(),
2495 op->tmp1()->as_register(),
2496 op->tmp2()->as_register(),
2497 op->tmp3()->as_register(),
2498 arrayOopDesc::header_size(op->type()),
2499 type2aelembytes(op->type()),
2500 op->klass()->as_register(),
2501 *op->stub()->entry());
2502 }
2503 __ bind(*op->stub()->continuation());
2504 }
2505
2506
2507 void LIR_Assembler::type_profile_helper(Register mdo, int mdo_offset_bias,
2508 ciMethodData *md, ciProfileData *data,
2509 Register recv, Register tmp1, Label* update_done) {
2510 uint i;
2511 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2512 Label next_test;
2513 // See if the receiver is receiver[n].
2514 Address receiver_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)) -
2515 mdo_offset_bias);
2516 __ ld_ptr(receiver_addr, tmp1);
2517 __ verify_oop(tmp1);
2518 __ cmp_and_brx_short(recv, tmp1, Assembler::notEqual, Assembler::pt, next_test);
2519 Address data_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)) -
2520 mdo_offset_bias);
2521 __ ld_ptr(data_addr, tmp1);
2522 __ add(tmp1, DataLayout::counter_increment, tmp1);
2523 __ st_ptr(tmp1, data_addr);
2524 __ ba(*update_done);
2525 __ delayed()->nop();
2526 __ bind(next_test);
2527 }
2528
2529 // Didn't find receiver; find next empty slot and fill it in
2530 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2531 Label next_test;
2532 Address recv_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)) -
2533 mdo_offset_bias);
2534 __ ld_ptr(recv_addr, tmp1);
2535 __ br_notnull_short(tmp1, Assembler::pt, next_test);
2536 __ st_ptr(recv, recv_addr);
2537 __ set(DataLayout::counter_increment, tmp1);
2538 __ st_ptr(tmp1, mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)) -
2539 mdo_offset_bias);
2540 __ ba(*update_done);
2541 __ delayed()->nop();
2542 __ bind(next_test);
2543 }
2544 }
2545
2546
2547 void LIR_Assembler::setup_md_access(ciMethod* method, int bci,
2548 ciMethodData*& md, ciProfileData*& data, int& mdo_offset_bias) {
2549 md = method->method_data_or_null();
2550 assert(md != NULL, "Sanity");
2551 data = md->bci_to_data(bci);
2552 assert(data != NULL, "need data for checkcast");
2553 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
2554 if (!Assembler::is_simm13(md->byte_offset_of_slot(data, DataLayout::header_offset()) + data->size_in_bytes())) {
2555 // The offset is large so bias the mdo by the base of the slot so
2556 // that the ld can use simm13s to reference the slots of the data
2557 mdo_offset_bias = md->byte_offset_of_slot(data, DataLayout::header_offset());
2558 }
2559 }
2560
2561 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) {
2562 // we always need a stub for the failure case.
2563 CodeStub* stub = op->stub();
2564 Register obj = op->object()->as_register();
2565 Register k_RInfo = op->tmp1()->as_register();
2566 Register klass_RInfo = op->tmp2()->as_register();
2567 Register dst = op->result_opr()->as_register();
2568 Register Rtmp1 = op->tmp3()->as_register();
2569 ciKlass* k = op->klass();
2570
2571
2572 if (obj == k_RInfo) {
2573 k_RInfo = klass_RInfo;
2574 klass_RInfo = obj;
2575 }
2576
2577 ciMethodData* md;
2578 ciProfileData* data;
2579 int mdo_offset_bias = 0;
2580 if (op->should_profile()) {
2581 ciMethod* method = op->profiled_method();
2582 assert(method != NULL, "Should have method");
2583 setup_md_access(method, op->profiled_bci(), md, data, mdo_offset_bias);
2584
2585 Label not_null;
2586 __ br_notnull_short(obj, Assembler::pn, not_null);
2587 Register mdo = k_RInfo;
2588 Register data_val = Rtmp1;
2589 jobject2reg(md->constant_encoding(), mdo);
2590 if (mdo_offset_bias > 0) {
2591 __ set(mdo_offset_bias, data_val);
2592 __ add(mdo, data_val, mdo);
2593 }
2594 Address flags_addr(mdo, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias);
2595 __ ldub(flags_addr, data_val);
2596 __ or3(data_val, BitData::null_seen_byte_constant(), data_val);
2597 __ stb(data_val, flags_addr);
2598 __ ba(*obj_is_null);
2599 __ delayed()->nop();
2600 __ bind(not_null);
2601 } else {
2602 __ br_null(obj, false, Assembler::pn, *obj_is_null);
2603 __ delayed()->nop();
2604 }
2605
2606 Label profile_cast_failure, profile_cast_success;
2607 Label *failure_target = op->should_profile() ? &profile_cast_failure : failure;
2608 Label *success_target = op->should_profile() ? &profile_cast_success : success;
2609
2610 // patching may screw with our temporaries on sparc,
2611 // so let's do it before loading the class
2612 if (k->is_loaded()) {
2613 jobject2reg(k->constant_encoding(), k_RInfo);
2614 } else {
2615 jobject2reg_with_patching(k_RInfo, op->info_for_patch());
2616 }
2617 assert(obj != k_RInfo, "must be different");
2618
2619 // get object class
2620 // not a safepoint as obj null check happens earlier
2621 __ load_klass(obj, klass_RInfo);
2622 if (op->fast_check()) {
2623 assert_different_registers(klass_RInfo, k_RInfo);
2624 __ cmp(k_RInfo, klass_RInfo);
2625 __ brx(Assembler::notEqual, false, Assembler::pt, *failure_target);
2626 __ delayed()->nop();
2627 } else {
2628 bool need_slow_path = true;
2629 if (k->is_loaded()) {
2630 if (k->super_check_offset() != sizeof(oopDesc) + Klass::secondary_super_cache_offset_in_bytes())
2631 need_slow_path = false;
2632 // perform the fast part of the checking logic
2633 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, noreg,
2634 (need_slow_path ? success_target : NULL),
2635 failure_target, NULL,
2636 RegisterOrConstant(k->super_check_offset()));
2637 } else {
2638 // perform the fast part of the checking logic
2639 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, O7, success_target,
2640 failure_target, NULL);
2641 }
2642 if (need_slow_path) {
2643 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
2644 assert(klass_RInfo == G3 && k_RInfo == G1, "incorrect call setup");
2645 __ call(Runtime1::entry_for(Runtime1::slow_subtype_check_id), relocInfo::runtime_call_type);
2646 __ delayed()->nop();
2647 __ cmp(G3, 0);
2648 __ br(Assembler::equal, false, Assembler::pn, *failure_target);
2649 __ delayed()->nop();
2650 // Fall through to success case
2651 }
2652 }
2653
2654 if (op->should_profile()) {
2655 Register mdo = klass_RInfo, recv = k_RInfo, tmp1 = Rtmp1;
2656 assert_different_registers(obj, mdo, recv, tmp1);
2657 __ bind(profile_cast_success);
2658 jobject2reg(md->constant_encoding(), mdo);
2659 if (mdo_offset_bias > 0) {
2660 __ set(mdo_offset_bias, tmp1);
2661 __ add(mdo, tmp1, mdo);
2662 }
2663 __ load_klass(obj, recv);
2664 type_profile_helper(mdo, mdo_offset_bias, md, data, recv, tmp1, success);
2665 // Jump over the failure case
2666 __ ba(*success);
2667 __ delayed()->nop();
2668 // Cast failure case
2669 __ bind(profile_cast_failure);
2670 jobject2reg(md->constant_encoding(), mdo);
2671 if (mdo_offset_bias > 0) {
2672 __ set(mdo_offset_bias, tmp1);
2673 __ add(mdo, tmp1, mdo);
2674 }
2675 Address data_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias);
2676 __ ld_ptr(data_addr, tmp1);
2677 __ sub(tmp1, DataLayout::counter_increment, tmp1);
2678 __ st_ptr(tmp1, data_addr);
2679 __ ba(*failure);
2680 __ delayed()->nop();
2681 }
2682 __ ba(*success);
2683 __ delayed()->nop();
2684 }
2685
2686 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
2687 LIR_Code code = op->code();
2688 if (code == lir_store_check) {
2689 Register value = op->object()->as_register();
2690 Register array = op->array()->as_register();
2691 Register k_RInfo = op->tmp1()->as_register();
2692 Register klass_RInfo = op->tmp2()->as_register();
2693 Register Rtmp1 = op->tmp3()->as_register();
2694
2695 __ verify_oop(value);
2696 CodeStub* stub = op->stub();
2697 // check if it needs to be profiled
2698 ciMethodData* md;
2699 ciProfileData* data;
2700 int mdo_offset_bias = 0;
2701 if (op->should_profile()) {
2702 ciMethod* method = op->profiled_method();
2703 assert(method != NULL, "Should have method");
2704 setup_md_access(method, op->profiled_bci(), md, data, mdo_offset_bias);
2705 }
2706 Label profile_cast_success, profile_cast_failure, done;
2707 Label *success_target = op->should_profile() ? &profile_cast_success : &done;
2708 Label *failure_target = op->should_profile() ? &profile_cast_failure : stub->entry();
2709
2710 if (op->should_profile()) {
2711 Label not_null;
2712 __ br_notnull_short(value, Assembler::pn, not_null);
2713 Register mdo = k_RInfo;
2714 Register data_val = Rtmp1;
2715 jobject2reg(md->constant_encoding(), mdo);
2716 if (mdo_offset_bias > 0) {
2717 __ set(mdo_offset_bias, data_val);
2718 __ add(mdo, data_val, mdo);
2719 }
2720 Address flags_addr(mdo, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias);
2721 __ ldub(flags_addr, data_val);
2722 __ or3(data_val, BitData::null_seen_byte_constant(), data_val);
2723 __ stb(data_val, flags_addr);
2724 __ ba_short(done);
2725 __ bind(not_null);
2726 } else {
2727 __ br_null_short(value, Assembler::pn, done);
2728 }
2729 add_debug_info_for_null_check_here(op->info_for_exception());
2730 __ load_klass(array, k_RInfo);
2731 __ load_klass(value, klass_RInfo);
2732
2733 // get instance klass
2734 __ ld_ptr(Address(k_RInfo, objArrayKlass::element_klass_offset_in_bytes() + sizeof(oopDesc)), k_RInfo);
2735 // perform the fast part of the checking logic
2736 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, O7, success_target, failure_target, NULL);
2737
2738 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
2739 assert(klass_RInfo == G3 && k_RInfo == G1, "incorrect call setup");
2740 __ call(Runtime1::entry_for(Runtime1::slow_subtype_check_id), relocInfo::runtime_call_type);
2741 __ delayed()->nop();
2742 __ cmp(G3, 0);
2743 __ br(Assembler::equal, false, Assembler::pn, *failure_target);
2744 __ delayed()->nop();
2745 // fall through to the success case
2746
2747 if (op->should_profile()) {
2748 Register mdo = klass_RInfo, recv = k_RInfo, tmp1 = Rtmp1;
2749 assert_different_registers(value, mdo, recv, tmp1);
2750 __ bind(profile_cast_success);
2751 jobject2reg(md->constant_encoding(), mdo);
2752 if (mdo_offset_bias > 0) {
2753 __ set(mdo_offset_bias, tmp1);
2754 __ add(mdo, tmp1, mdo);
2755 }
2756 __ load_klass(value, recv);
2757 type_profile_helper(mdo, mdo_offset_bias, md, data, recv, tmp1, &done);
2758 __ ba_short(done);
2759 // Cast failure case
2760 __ bind(profile_cast_failure);
2761 jobject2reg(md->constant_encoding(), mdo);
2762 if (mdo_offset_bias > 0) {
2763 __ set(mdo_offset_bias, tmp1);
2764 __ add(mdo, tmp1, mdo);
2765 }
2766 Address data_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias);
2767 __ ld_ptr(data_addr, tmp1);
2768 __ sub(tmp1, DataLayout::counter_increment, tmp1);
2769 __ st_ptr(tmp1, data_addr);
2770 __ ba(*stub->entry());
2771 __ delayed()->nop();
2772 }
2773 __ bind(done);
2774 } else if (code == lir_checkcast) {
2775 Register obj = op->object()->as_register();
2776 Register dst = op->result_opr()->as_register();
2777 Label success;
2778 emit_typecheck_helper(op, &success, op->stub()->entry(), &success);
2779 __ bind(success);
2780 __ mov(obj, dst);
2781 } else if (code == lir_instanceof) {
2782 Register obj = op->object()->as_register();
2783 Register dst = op->result_opr()->as_register();
2784 Label success, failure, done;
2785 emit_typecheck_helper(op, &success, &failure, &failure);
2786 __ bind(failure);
2787 __ set(0, dst);
2788 __ ba_short(done);
2789 __ bind(success);
2790 __ set(1, dst);
2791 __ bind(done);
2792 } else {
2793 ShouldNotReachHere();
2794 }
2795
2796 }
2797
2798
2799 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
2800 if (op->code() == lir_cas_long) {
2801 assert(VM_Version::supports_cx8(), "wrong machine");
2802 Register addr = op->addr()->as_pointer_register();
2803 Register cmp_value_lo = op->cmp_value()->as_register_lo();
2804 Register cmp_value_hi = op->cmp_value()->as_register_hi();
2805 Register new_value_lo = op->new_value()->as_register_lo();
2806 Register new_value_hi = op->new_value()->as_register_hi();
2807 Register t1 = op->tmp1()->as_register();
2808 Register t2 = op->tmp2()->as_register();
2809 #ifdef _LP64
2810 __ mov(cmp_value_lo, t1);
2811 __ mov(new_value_lo, t2);
2812 // perform the compare and swap operation
2813 __ casx(addr, t1, t2);
2814 // generate condition code - if the swap succeeded, t2 ("new value" reg) was
2815 // overwritten with the original value in "addr" and will be equal to t1.
2816 __ cmp(t1, t2);
2817 #else
2818 // move high and low halves of long values into single registers
2819 __ sllx(cmp_value_hi, 32, t1); // shift high half into temp reg
2820 __ srl(cmp_value_lo, 0, cmp_value_lo); // clear upper 32 bits of low half
2821 __ or3(t1, cmp_value_lo, t1); // t1 holds 64-bit compare value
2822 __ sllx(new_value_hi, 32, t2);
2823 __ srl(new_value_lo, 0, new_value_lo);
2824 __ or3(t2, new_value_lo, t2); // t2 holds 64-bit value to swap
2825 // perform the compare and swap operation
2826 __ casx(addr, t1, t2);
2827 // generate condition code - if the swap succeeded, t2 ("new value" reg) was
2828 // overwritten with the original value in "addr" and will be equal to t1.
2829 // Produce icc flag for 32bit.
2830 __ sub(t1, t2, t2);
2831 __ srlx(t2, 32, t1);
2832 __ orcc(t2, t1, G0);
2833 #endif
2834 } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj) {
2835 Register addr = op->addr()->as_pointer_register();
2836 Register cmp_value = op->cmp_value()->as_register();
2837 Register new_value = op->new_value()->as_register();
2838 Register t1 = op->tmp1()->as_register();
2839 Register t2 = op->tmp2()->as_register();
2840 __ mov(cmp_value, t1);
2841 __ mov(new_value, t2);
2842 if (op->code() == lir_cas_obj) {
2843 if (UseCompressedOops) {
2844 __ encode_heap_oop(t1);
2845 __ encode_heap_oop(t2);
2846 __ cas(addr, t1, t2);
2847 } else {
2848 __ cas_ptr(addr, t1, t2);
2849 }
2850 } else {
2851 __ cas(addr, t1, t2);
2852 }
2853 __ cmp(t1, t2);
2854 } else {
2855 Unimplemented();
2856 }
2857 }
2858
2859 void LIR_Assembler::set_24bit_FPU() {
2860 Unimplemented();
2861 }
2862
2863
2864 void LIR_Assembler::reset_FPU() {
2865 Unimplemented();
2866 }
2867
2868
2869 void LIR_Assembler::breakpoint() {
2870 __ breakpoint_trap();
2871 }
2872
2873
2874 void LIR_Assembler::push(LIR_Opr opr) {
2875 Unimplemented();
2876 }
2877
2878
2879 void LIR_Assembler::pop(LIR_Opr opr) {
2880 Unimplemented();
2881 }
2882
2883
2884 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst_opr) {
2885 Address mon_addr = frame_map()->address_for_monitor_lock(monitor_no);
2886 Register dst = dst_opr->as_register();
2887 Register reg = mon_addr.base();
2888 int offset = mon_addr.disp();
2889 // compute pointer to BasicLock
2890 if (mon_addr.is_simm13()) {
2891 __ add(reg, offset, dst);
2892 } else {
2893 __ set(offset, dst);
2894 __ add(dst, reg, dst);
2895 }
2896 }
2897
2898
2899 void LIR_Assembler::emit_lock(LIR_OpLock* op) {
2900 Register obj = op->obj_opr()->as_register();
2901 Register hdr = op->hdr_opr()->as_register();
2902 Register lock = op->lock_opr()->as_register();
2903
2904 // obj may not be an oop
2905 if (op->code() == lir_lock) {
2906 MonitorEnterStub* stub = (MonitorEnterStub*)op->stub();
2907 if (UseFastLocking) {
2908 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
2909 // add debug info for NullPointerException only if one is possible
2910 if (op->info() != NULL) {
2911 add_debug_info_for_null_check_here(op->info());
2912 }
2913 __ lock_object(hdr, obj, lock, op->scratch_opr()->as_register(), *op->stub()->entry());
2914 } else {
2915 // always do slow locking
2916 // note: the slow locking code could be inlined here, however if we use
2917 // slow locking, speed doesn't matter anyway and this solution is
2918 // simpler and requires less duplicated code - additionally, the
2919 // slow locking code is the same in either case which simplifies
2920 // debugging
2921 __ br(Assembler::always, false, Assembler::pt, *op->stub()->entry());
2922 __ delayed()->nop();
2923 }
2924 } else {
2925 assert (op->code() == lir_unlock, "Invalid code, expected lir_unlock");
2926 if (UseFastLocking) {
2927 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
2928 __ unlock_object(hdr, obj, lock, *op->stub()->entry());
2929 } else {
2930 // always do slow unlocking
2931 // note: the slow unlocking code could be inlined here, however if we use
2932 // slow unlocking, speed doesn't matter anyway and this solution is
2933 // simpler and requires less duplicated code - additionally, the
2934 // slow unlocking code is the same in either case which simplifies
2935 // debugging
2936 __ br(Assembler::always, false, Assembler::pt, *op->stub()->entry());
2937 __ delayed()->nop();
2938 }
2939 }
2940 __ bind(*op->stub()->continuation());
2941 }
2942
2943
2944 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
2945 ciMethod* method = op->profiled_method();
2946 int bci = op->profiled_bci();
2947
2948 // Update counter for all call types
2949 ciMethodData* md = method->method_data_or_null();
2950 assert(md != NULL, "Sanity");
2951 ciProfileData* data = md->bci_to_data(bci);
2952 assert(data->is_CounterData(), "need CounterData for calls");
2953 assert(op->mdo()->is_single_cpu(), "mdo must be allocated");
2954 Register mdo = op->mdo()->as_register();
2955 #ifdef _LP64
2956 assert(op->tmp1()->is_double_cpu(), "tmp1 must be allocated");
2957 Register tmp1 = op->tmp1()->as_register_lo();
2958 #else
2959 assert(op->tmp1()->is_single_cpu(), "tmp1 must be allocated");
2960 Register tmp1 = op->tmp1()->as_register();
2961 #endif
2962 jobject2reg(md->constant_encoding(), mdo);
2963 int mdo_offset_bias = 0;
2964 if (!Assembler::is_simm13(md->byte_offset_of_slot(data, CounterData::count_offset()) +
2965 data->size_in_bytes())) {
2966 // The offset is large so bias the mdo by the base of the slot so
2967 // that the ld can use simm13s to reference the slots of the data
2968 mdo_offset_bias = md->byte_offset_of_slot(data, CounterData::count_offset());
2969 __ set(mdo_offset_bias, O7);
2970 __ add(mdo, O7, mdo);
2971 }
2972
2973 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias);
2974 Bytecodes::Code bc = method->java_code_at_bci(bci);
2975 // Perform additional virtual call profiling for invokevirtual and
2976 // invokeinterface bytecodes
2977 if ((bc == Bytecodes::_invokevirtual || bc == Bytecodes::_invokeinterface) &&
2978 C1ProfileVirtualCalls) {
2979 assert(op->recv()->is_single_cpu(), "recv must be allocated");
2980 Register recv = op->recv()->as_register();
2981 assert_different_registers(mdo, tmp1, recv);
2982 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls");
2983 ciKlass* known_klass = op->known_holder();
2984 if (C1OptimizeVirtualCallProfiling && known_klass != NULL) {
2985 // We know the type that will be seen at this call site; we can
2986 // statically update the methodDataOop rather than needing to do
2987 // dynamic tests on the receiver type
2988
2989 // NOTE: we should probably put a lock around this search to
2990 // avoid collisions by concurrent compilations
2991 ciVirtualCallData* vc_data = (ciVirtualCallData*) data;
2992 uint i;
2993 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2994 ciKlass* receiver = vc_data->receiver(i);
2995 if (known_klass->equals(receiver)) {
2996 Address data_addr(mdo, md->byte_offset_of_slot(data,
2997 VirtualCallData::receiver_count_offset(i)) -
2998 mdo_offset_bias);
2999 __ ld_ptr(data_addr, tmp1);
3000 __ add(tmp1, DataLayout::counter_increment, tmp1);
3001 __ st_ptr(tmp1, data_addr);
3002 return;
3003 }
3004 }
3005
3006 // Receiver type not found in profile data; select an empty slot
3007
3008 // Note that this is less efficient than it should be because it
3009 // always does a write to the receiver part of the
3010 // VirtualCallData rather than just the first time
3011 for (i = 0; i < VirtualCallData::row_limit(); i++) {
3012 ciKlass* receiver = vc_data->receiver(i);
3013 if (receiver == NULL) {
3014 Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)) -
3015 mdo_offset_bias);
3016 jobject2reg(known_klass->constant_encoding(), tmp1);
3017 __ st_ptr(tmp1, recv_addr);
3018 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) -
3019 mdo_offset_bias);
3020 __ ld_ptr(data_addr, tmp1);
3021 __ add(tmp1, DataLayout::counter_increment, tmp1);
3022 __ st_ptr(tmp1, data_addr);
3023 return;
3024 }
3025 }
3026 } else {
3027 __ load_klass(recv, recv);
3028 Label update_done;
3029 type_profile_helper(mdo, mdo_offset_bias, md, data, recv, tmp1, &update_done);
3030 // Receiver did not match any saved receiver and there is no empty row for it.
3031 // Increment total counter to indicate polymorphic case.
3032 __ ld_ptr(counter_addr, tmp1);
3033 __ add(tmp1, DataLayout::counter_increment, tmp1);
3034 __ st_ptr(tmp1, counter_addr);
3035
3036 __ bind(update_done);
3037 }
3038 } else {
3039 // Static call
3040 __ ld_ptr(counter_addr, tmp1);
3041 __ add(tmp1, DataLayout::counter_increment, tmp1);
3042 __ st_ptr(tmp1, counter_addr);
3043 }
3044 }
3045
3046 void LIR_Assembler::align_backward_branch_target() {
3047 __ align(OptoLoopAlignment);
3048 }
3049
3050
3051 void LIR_Assembler::emit_delay(LIR_OpDelay* op) {
3052 // make sure we are expecting a delay
3053 // this has the side effect of clearing the delay state
3054 // so we can use _masm instead of _masm->delayed() to do the
3055 // code generation.
3056 __ delayed();
3057
3058 // make sure we only emit one instruction
3059 int offset = code_offset();
3060 op->delay_op()->emit_code(this);
3061 #ifdef ASSERT
3062 if (code_offset() - offset != NativeInstruction::nop_instruction_size) {
3063 op->delay_op()->print();
3064 }
3065 assert(code_offset() - offset == NativeInstruction::nop_instruction_size,
3066 "only one instruction can go in a delay slot");
3067 #endif
3068
3069 // we may also be emitting the call info for the instruction
3070 // which we are the delay slot of.
3071 CodeEmitInfo* call_info = op->call_info();
3072 if (call_info) {
3073 add_call_info(code_offset(), call_info);
3074 }
3075
3076 if (VerifyStackAtCalls) {
3077 _masm->sub(FP, SP, O7);
3078 _masm->cmp(O7, initial_frame_size_in_bytes());
3079 _masm->trap(Assembler::notEqual, Assembler::ptr_cc, G0, ST_RESERVED_FOR_USER_0+2 );
3080 }
3081 }
3082
3083
3084 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest) {
3085 assert(left->is_register(), "can only handle registers");
3086
3087 if (left->is_single_cpu()) {
3088 __ neg(left->as_register(), dest->as_register());
3089 } else if (left->is_single_fpu()) {
3090 __ fneg(FloatRegisterImpl::S, left->as_float_reg(), dest->as_float_reg());
3091 } else if (left->is_double_fpu()) {
3092 __ fneg(FloatRegisterImpl::D, left->as_double_reg(), dest->as_double_reg());
3093 } else {
3094 assert (left->is_double_cpu(), "Must be a long");
3095 Register Rlow = left->as_register_lo();
3096 Register Rhi = left->as_register_hi();
3097 #ifdef _LP64
3098 __ sub(G0, Rlow, dest->as_register_lo());
3099 #else
3100 __ subcc(G0, Rlow, dest->as_register_lo());
3101 __ subc (G0, Rhi, dest->as_register_hi());
3102 #endif
3103 }
3104 }
3105
3106
3107 void LIR_Assembler::fxch(int i) {
3108 Unimplemented();
3109 }
3110
3111 void LIR_Assembler::fld(int i) {
3112 Unimplemented();
3113 }
3114
3115 void LIR_Assembler::ffree(int i) {
3116 Unimplemented();
3117 }
3118
3119 void LIR_Assembler::rt_call(LIR_Opr result, address dest,
3120 const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
3121
3122 // if tmp is invalid, then the function being called doesn't destroy the thread
3123 if (tmp->is_valid()) {
3124 __ save_thread(tmp->as_register());
3125 }
3126 __ call(dest, relocInfo::runtime_call_type);
3127 __ delayed()->nop();
3128 if (info != NULL) {
3129 add_call_info_here(info);
3130 }
3131 if (tmp->is_valid()) {
3132 __ restore_thread(tmp->as_register());
3133 }
3134
3135 #ifdef ASSERT
3136 __ verify_thread();
3137 #endif // ASSERT
3138 }
3139
3140
3141 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) {
3142 #ifdef _LP64
3143 ShouldNotReachHere();
3144 #endif
3145
3146 NEEDS_CLEANUP;
3147 if (type == T_LONG) {
3148 LIR_Address* mem_addr = dest->is_address() ? dest->as_address_ptr() : src->as_address_ptr();
3149
3150 // (extended to allow indexed as well as constant displaced for JSR-166)
3151 Register idx = noreg; // contains either constant offset or index
3152
3153 int disp = mem_addr->disp();
3154 if (mem_addr->index() == LIR_OprFact::illegalOpr) {
3155 if (!Assembler::is_simm13(disp)) {
3156 idx = O7;
3157 __ set(disp, idx);
3158 }
3159 } else {
3160 assert(disp == 0, "not both indexed and disp");
3161 idx = mem_addr->index()->as_register();
3162 }
3163
3164 int null_check_offset = -1;
3165
3166 Register base = mem_addr->base()->as_register();
3167 if (src->is_register() && dest->is_address()) {
3168 // G4 is high half, G5 is low half
3169 if (VM_Version::v9_instructions_work()) {
3170 // clear the top bits of G5, and scale up G4
3171 __ srl (src->as_register_lo(), 0, G5);
3172 __ sllx(src->as_register_hi(), 32, G4);
3173 // combine the two halves into the 64 bits of G4
3174 __ or3(G4, G5, G4);
3175 null_check_offset = __ offset();
3176 if (idx == noreg) {
3177 __ stx(G4, base, disp);
3178 } else {
3179 __ stx(G4, base, idx);
3180 }
3181 } else {
3182 __ mov (src->as_register_hi(), G4);
3183 __ mov (src->as_register_lo(), G5);
3184 null_check_offset = __ offset();
3185 if (idx == noreg) {
3186 __ std(G4, base, disp);
3187 } else {
3188 __ std(G4, base, idx);
3189 }
3190 }
3191 } else if (src->is_address() && dest->is_register()) {
3192 null_check_offset = __ offset();
3193 if (VM_Version::v9_instructions_work()) {
3194 if (idx == noreg) {
3195 __ ldx(base, disp, G5);
3196 } else {
3197 __ ldx(base, idx, G5);
3198 }
3199 __ srax(G5, 32, dest->as_register_hi()); // fetch the high half into hi
3200 __ mov (G5, dest->as_register_lo()); // copy low half into lo
3201 } else {
3202 if (idx == noreg) {
3203 __ ldd(base, disp, G4);
3204 } else {
3205 __ ldd(base, idx, G4);
3206 }
3207 // G4 is high half, G5 is low half
3208 __ mov (G4, dest->as_register_hi());
3209 __ mov (G5, dest->as_register_lo());
3210 }
3211 } else {
3212 Unimplemented();
3213 }
3214 if (info != NULL) {
3215 add_debug_info_for_null_check(null_check_offset, info);
3216 }
3217
3218 } else {
3219 // use normal move for all other volatiles since they don't need
3220 // special handling to remain atomic.
3221 move_op(src, dest, type, lir_patch_none, info, false, false, false);
3222 }
3223 }
3224
3225 void LIR_Assembler::membar() {
3226 // only StoreLoad membars are ever explicitly needed on sparcs in TSO mode
3227 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad) );
3228 }
3229
3230 void LIR_Assembler::membar_acquire() {
3231 // no-op on TSO
3232 }
3233
3234 void LIR_Assembler::membar_release() {
3235 // no-op on TSO
3236 }
3237
3238 // Pack two sequential registers containing 32 bit values
3239 // into a single 64 bit register.
3240 // src and src->successor() are packed into dst
3241 // src and dst may be the same register.
3242 // Note: src is destroyed
3243 void LIR_Assembler::pack64(LIR_Opr src, LIR_Opr dst) {
3244 Register rs = src->as_register();
3245 Register rd = dst->as_register_lo();
3246 __ sllx(rs, 32, rs);
3247 __ srl(rs->successor(), 0, rs->successor());
3248 __ or3(rs, rs->successor(), rd);
3249 }
3250
3251 // Unpack a 64 bit value in a register into
3252 // two sequential registers.
3253 // src is unpacked into dst and dst->successor()
3254 void LIR_Assembler::unpack64(LIR_Opr src, LIR_Opr dst) {
3255 Register rs = src->as_register_lo();
3256 Register rd = dst->as_register_hi();
3257 assert_different_registers(rs, rd, rd->successor());
3258 __ srlx(rs, 32, rd);
3259 __ srl (rs, 0, rd->successor());
3260 }
3261
3262
3263 void LIR_Assembler::leal(LIR_Opr addr_opr, LIR_Opr dest) {
3264 LIR_Address* addr = addr_opr->as_address_ptr();
3265 assert(addr->index()->is_illegal() && addr->scale() == LIR_Address::times_1 && Assembler::is_simm13(addr->disp()), "can't handle complex addresses yet");
3266
3267 __ add(addr->base()->as_pointer_register(), addr->disp(), dest->as_pointer_register());
3268 }
3269
3270
3271 void LIR_Assembler::get_thread(LIR_Opr result_reg) {
3272 assert(result_reg->is_register(), "check");
3273 __ mov(G2_thread, result_reg->as_register());
3274 }
3275
3276
3277 void LIR_Assembler::peephole(LIR_List* lir) {
3278 LIR_OpList* inst = lir->instructions_list();
3279 for (int i = 0; i < inst->length(); i++) {
3280 LIR_Op* op = inst->at(i);
3281 switch (op->code()) {
3282 case lir_cond_float_branch:
3283 case lir_branch: {
3284 LIR_OpBranch* branch = op->as_OpBranch();
3285 assert(branch->info() == NULL, "shouldn't be state on branches anymore");
3286 LIR_Op* delay_op = NULL;
3287 // we'd like to be able to pull following instructions into
3288 // this slot but we don't know enough to do it safely yet so
3289 // only optimize block to block control flow.
3290 if (LIRFillDelaySlots && branch->block()) {
3291 LIR_Op* prev = inst->at(i - 1);
3292 if (prev && LIR_Assembler::is_single_instruction(prev) && prev->info() == NULL) {
3293 // swap previous instruction into delay slot
3294 inst->at_put(i - 1, op);
3295 inst->at_put(i, new LIR_OpDelay(prev, op->info()));
3296 #ifndef PRODUCT
3297 if (LIRTracePeephole) {
3298 tty->print_cr("delayed");
3299 inst->at(i - 1)->print();
3300 inst->at(i)->print();
3301 tty->cr();
3302 }
3303 #endif
3304 continue;
3305 }
3306 }
3307
3308 if (!delay_op) {
3309 delay_op = new LIR_OpDelay(new LIR_Op0(lir_nop), NULL);
3310 }
3311 inst->insert_before(i + 1, delay_op);
3312 break;
3313 }
3314 case lir_static_call:
3315 case lir_virtual_call:
3316 case lir_icvirtual_call:
3317 case lir_optvirtual_call:
3318 case lir_dynamic_call: {
3319 LIR_Op* prev = inst->at(i - 1);
3320 if (LIRFillDelaySlots && prev && prev->code() == lir_move && prev->info() == NULL &&
3321 (op->code() != lir_virtual_call ||
3322 !prev->result_opr()->is_single_cpu() ||
3323 prev->result_opr()->as_register() != O0) &&
3324 LIR_Assembler::is_single_instruction(prev)) {
3325 // Only moves without info can be put into the delay slot.
3326 // Also don't allow the setup of the receiver in the delay
3327 // slot for vtable calls.
3328 inst->at_put(i - 1, op);
3329 inst->at_put(i, new LIR_OpDelay(prev, op->info()));
3330 #ifndef PRODUCT
3331 if (LIRTracePeephole) {
3332 tty->print_cr("delayed");
3333 inst->at(i - 1)->print();
3334 inst->at(i)->print();
3335 tty->cr();
3336 }
3337 #endif
3338 } else {
3339 LIR_Op* delay_op = new LIR_OpDelay(new LIR_Op0(lir_nop), op->as_OpJavaCall()->info());
3340 inst->insert_before(i + 1, delay_op);
3341 i++;
3342 }
3343
3344 #if defined(TIERED) && !defined(_LP64)
3345 // fixup the return value from G1 to O0/O1 for long returns.
3346 // It's done here instead of in LIRGenerator because there's
3347 // such a mismatch between the single reg and double reg
3348 // calling convention.
3349 LIR_OpJavaCall* callop = op->as_OpJavaCall();
3350 if (callop->result_opr() == FrameMap::out_long_opr) {
3351 LIR_OpJavaCall* call;
3352 LIR_OprList* arguments = new LIR_OprList(callop->arguments()->length());
3353 for (int a = 0; a < arguments->length(); a++) {
3354 arguments[a] = callop->arguments()[a];
3355 }
3356 if (op->code() == lir_virtual_call) {
3357 call = new LIR_OpJavaCall(op->code(), callop->method(), callop->receiver(), FrameMap::g1_long_single_opr,
3358 callop->vtable_offset(), arguments, callop->info());
3359 } else {
3360 call = new LIR_OpJavaCall(op->code(), callop->method(), callop->receiver(), FrameMap::g1_long_single_opr,
3361 callop->addr(), arguments, callop->info());
3362 }
3363 inst->at_put(i - 1, call);
3364 inst->insert_before(i + 1, new LIR_Op1(lir_unpack64, FrameMap::g1_long_single_opr, callop->result_opr(),
3365 T_LONG, lir_patch_none, NULL));
3366 }
3367 #endif
3368 break;
3369 }
3370 }
3371 }
3372 }
3373
3374
3375
3376
3377 #undef __