1 /*
2 * Copyright (c) 1997, 2016, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
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23 */
24
25 #ifndef CPU_X86_VM_MACROASSEMBLER_X86_HPP
26 #define CPU_X86_VM_MACROASSEMBLER_X86_HPP
27
28 #include "asm/assembler.hpp"
29 #include "utilities/macros.hpp"
30 #include "runtime/rtmLocking.hpp"
31
32 // MacroAssembler extends Assembler by frequently used macros.
33 //
34 // Instructions for which a 'better' code sequence exists depending
35 // on arguments should also go in here.
36
37 class MacroAssembler: public Assembler {
38 friend class LIR_Assembler;
39 friend class Runtime1; // as_Address()
40
41 protected:
42
43 Address as_Address(AddressLiteral adr);
44 Address as_Address(ArrayAddress adr);
45
46 // Support for VM calls
47 //
48 // This is the base routine called by the different versions of call_VM_leaf. The interpreter
49 // may customize this version by overriding it for its purposes (e.g., to save/restore
50 // additional registers when doing a VM call).
51
52 virtual void call_VM_leaf_base(
53 address entry_point, // the entry point
54 int number_of_arguments // the number of arguments to pop after the call
55 );
56
57 // This is the base routine called by the different versions of call_VM. The interpreter
58 // may customize this version by overriding it for its purposes (e.g., to save/restore
59 // additional registers when doing a VM call).
60 //
61 // If no java_thread register is specified (noreg) than rdi will be used instead. call_VM_base
62 // returns the register which contains the thread upon return. If a thread register has been
63 // specified, the return value will correspond to that register. If no last_java_sp is specified
64 // (noreg) than rsp will be used instead.
65 virtual void call_VM_base( // returns the register containing the thread upon return
66 Register oop_result, // where an oop-result ends up if any; use noreg otherwise
67 Register java_thread, // the thread if computed before ; use noreg otherwise
68 Register last_java_sp, // to set up last_Java_frame in stubs; use noreg otherwise
69 address entry_point, // the entry point
70 int number_of_arguments, // the number of arguments (w/o thread) to pop after the call
71 bool check_exceptions // whether to check for pending exceptions after return
72 );
73
74 // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code.
75 // The implementation is only non-empty for the InterpreterMacroAssembler,
76 // as only the interpreter handles PopFrame and ForceEarlyReturn requests.
77 virtual void check_and_handle_popframe(Register java_thread);
78 virtual void check_and_handle_earlyret(Register java_thread);
79
80 void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions = true);
81
82 // helpers for FPU flag access
83 // tmp is a temporary register, if none is available use noreg
84 void save_rax (Register tmp);
85 void restore_rax(Register tmp);
86
87 public:
88 MacroAssembler(CodeBuffer* code) : Assembler(code) {}
89
90 // Support for NULL-checks
91 //
92 // Generates code that causes a NULL OS exception if the content of reg is NULL.
93 // If the accessed location is M[reg + offset] and the offset is known, provide the
94 // offset. No explicit code generation is needed if the offset is within a certain
95 // range (0 <= offset <= page_size).
96
97 void null_check(Register reg, int offset = -1);
98 static bool needs_explicit_null_check(intptr_t offset);
99
100 // Required platform-specific helpers for Label::patch_instructions.
101 // They _shadow_ the declarations in AbstractAssembler, which are undefined.
102 void pd_patch_instruction(address branch, address target) {
103 unsigned char op = branch[0];
104 assert(op == 0xE8 /* call */ ||
105 op == 0xE9 /* jmp */ ||
106 op == 0xEB /* short jmp */ ||
107 (op & 0xF0) == 0x70 /* short jcc */ ||
108 op == 0x0F && (branch[1] & 0xF0) == 0x80 /* jcc */ ||
109 op == 0xC7 && branch[1] == 0xF8 /* xbegin */,
110 "Invalid opcode at patch point");
111
112 if (op == 0xEB || (op & 0xF0) == 0x70) {
113 // short offset operators (jmp and jcc)
114 char* disp = (char*) &branch[1];
115 int imm8 = target - (address) &disp[1];
116 guarantee(this->is8bit(imm8), "Short forward jump exceeds 8-bit offset");
117 *disp = imm8;
118 } else {
119 int* disp = (int*) &branch[(op == 0x0F || op == 0xC7)? 2: 1];
120 int imm32 = target - (address) &disp[1];
121 *disp = imm32;
122 }
123 }
124
125 // The following 4 methods return the offset of the appropriate move instruction
126
127 // Support for fast byte/short loading with zero extension (depending on particular CPU)
128 int load_unsigned_byte(Register dst, Address src);
129 int load_unsigned_short(Register dst, Address src);
130
131 // Support for fast byte/short loading with sign extension (depending on particular CPU)
132 int load_signed_byte(Register dst, Address src);
133 int load_signed_short(Register dst, Address src);
134
135 // Support for sign-extension (hi:lo = extend_sign(lo))
136 void extend_sign(Register hi, Register lo);
137
138 // Load and store values by size and signed-ness
139 void load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2 = noreg);
140 void store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2 = noreg);
141
142 // Support for inc/dec with optimal instruction selection depending on value
143
144 void increment(Register reg, int value = 1) { LP64_ONLY(incrementq(reg, value)) NOT_LP64(incrementl(reg, value)) ; }
145 void decrement(Register reg, int value = 1) { LP64_ONLY(decrementq(reg, value)) NOT_LP64(decrementl(reg, value)) ; }
146
147 void decrementl(Address dst, int value = 1);
148 void decrementl(Register reg, int value = 1);
149
150 void decrementq(Register reg, int value = 1);
151 void decrementq(Address dst, int value = 1);
152
153 void incrementl(Address dst, int value = 1);
154 void incrementl(Register reg, int value = 1);
155
156 void incrementq(Register reg, int value = 1);
157 void incrementq(Address dst, int value = 1);
158
159 // special instructions for EVEX
160 void setvectmask(Register dst, Register src);
161 void restorevectmask();
162
163 // Support optimal SSE move instructions.
164 void movflt(XMMRegister dst, XMMRegister src) {
165 if (UseXmmRegToRegMoveAll) { movaps(dst, src); return; }
166 else { movss (dst, src); return; }
167 }
168 void movflt(XMMRegister dst, Address src) { movss(dst, src); }
169 void movflt(XMMRegister dst, AddressLiteral src);
170 void movflt(Address dst, XMMRegister src) { movss(dst, src); }
171
172 void movdbl(XMMRegister dst, XMMRegister src) {
173 if (UseXmmRegToRegMoveAll) { movapd(dst, src); return; }
174 else { movsd (dst, src); return; }
175 }
176
177 void movdbl(XMMRegister dst, AddressLiteral src);
178
179 void movdbl(XMMRegister dst, Address src) {
180 if (UseXmmLoadAndClearUpper) { movsd (dst, src); return; }
181 else { movlpd(dst, src); return; }
182 }
183 void movdbl(Address dst, XMMRegister src) { movsd(dst, src); }
184
185 void incrementl(AddressLiteral dst);
186 void incrementl(ArrayAddress dst);
187
188 void incrementq(AddressLiteral dst);
189
190 // Alignment
191 void align(int modulus);
192 void align(int modulus, int target);
193
194 // A 5 byte nop that is safe for patching (see patch_verified_entry)
195 void fat_nop();
196
197 // Stack frame creation/removal
198 void enter();
199 void leave();
200
201 // Support for getting the JavaThread pointer (i.e.; a reference to thread-local information)
202 // The pointer will be loaded into the thread register.
203 void get_thread(Register thread);
204
205
206 // Support for VM calls
207 //
208 // It is imperative that all calls into the VM are handled via the call_VM macros.
209 // They make sure that the stack linkage is setup correctly. call_VM's correspond
210 // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points.
211
212
213 void call_VM(Register oop_result,
214 address entry_point,
215 bool check_exceptions = true);
216 void call_VM(Register oop_result,
217 address entry_point,
218 Register arg_1,
219 bool check_exceptions = true);
220 void call_VM(Register oop_result,
221 address entry_point,
222 Register arg_1, Register arg_2,
223 bool check_exceptions = true);
224 void call_VM(Register oop_result,
225 address entry_point,
226 Register arg_1, Register arg_2, Register arg_3,
227 bool check_exceptions = true);
228
229 // Overloadings with last_Java_sp
230 void call_VM(Register oop_result,
231 Register last_java_sp,
232 address entry_point,
233 int number_of_arguments = 0,
234 bool check_exceptions = true);
235 void call_VM(Register oop_result,
236 Register last_java_sp,
237 address entry_point,
238 Register arg_1, bool
239 check_exceptions = true);
240 void call_VM(Register oop_result,
241 Register last_java_sp,
242 address entry_point,
243 Register arg_1, Register arg_2,
244 bool check_exceptions = true);
245 void call_VM(Register oop_result,
246 Register last_java_sp,
247 address entry_point,
248 Register arg_1, Register arg_2, Register arg_3,
249 bool check_exceptions = true);
250
251 void get_vm_result (Register oop_result, Register thread);
252 void get_vm_result_2(Register metadata_result, Register thread);
253
254 // These always tightly bind to MacroAssembler::call_VM_base
255 // bypassing the virtual implementation
256 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true);
257 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true);
258 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
259 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);
260 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4, bool check_exceptions = true);
261
262 void call_VM_leaf0(address entry_point);
263 void call_VM_leaf(address entry_point,
264 int number_of_arguments = 0);
265 void call_VM_leaf(address entry_point,
266 Register arg_1);
267 void call_VM_leaf(address entry_point,
268 Register arg_1, Register arg_2);
269 void call_VM_leaf(address entry_point,
270 Register arg_1, Register arg_2, Register arg_3);
271
272 // These always tightly bind to MacroAssembler::call_VM_leaf_base
273 // bypassing the virtual implementation
274 void super_call_VM_leaf(address entry_point);
275 void super_call_VM_leaf(address entry_point, Register arg_1);
276 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2);
277 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3);
278 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4);
279
280 // last Java Frame (fills frame anchor)
281 void set_last_Java_frame(Register thread,
282 Register last_java_sp,
283 Register last_java_fp,
284 address last_java_pc);
285
286 // thread in the default location (r15_thread on 64bit)
287 void set_last_Java_frame(Register last_java_sp,
288 Register last_java_fp,
289 address last_java_pc);
290
291 void reset_last_Java_frame(Register thread, bool clear_fp);
292
293 // thread in the default location (r15_thread on 64bit)
294 void reset_last_Java_frame(bool clear_fp);
295
296 // Stores
297 void store_check(Register obj); // store check for obj - register is destroyed afterwards
298 void store_check(Register obj, Address dst); // same as above, dst is exact store location (reg. is destroyed)
299
300 #if INCLUDE_ALL_GCS
301
302 void g1_write_barrier_pre(Register obj,
303 Register pre_val,
304 Register thread,
305 Register tmp,
306 bool tosca_live,
307 bool expand_call);
308
309 void g1_write_barrier_post(Register store_addr,
310 Register new_val,
311 Register thread,
312 Register tmp,
313 Register tmp2);
314
315 #endif // INCLUDE_ALL_GCS
316
317 // C 'boolean' to Java boolean: x == 0 ? 0 : 1
318 void c2bool(Register x);
319
320 // C++ bool manipulation
321
322 void movbool(Register dst, Address src);
323 void movbool(Address dst, bool boolconst);
324 void movbool(Address dst, Register src);
325 void testbool(Register dst);
326
327 void load_mirror(Register mirror, Register method);
328
329 // oop manipulations
330 void load_klass(Register dst, Register src);
331 void store_klass(Register dst, Register src);
332
333 void load_heap_oop(Register dst, Address src);
334 void load_heap_oop_not_null(Register dst, Address src);
335 void store_heap_oop(Address dst, Register src);
336 void cmp_heap_oop(Register src1, Address src2, Register tmp = noreg);
337
338 // Used for storing NULL. All other oop constants should be
339 // stored using routines that take a jobject.
340 void store_heap_oop_null(Address dst);
341
342 void load_prototype_header(Register dst, Register src);
343
344 #ifdef _LP64
345 void store_klass_gap(Register dst, Register src);
346
347 // This dummy is to prevent a call to store_heap_oop from
348 // converting a zero (like NULL) into a Register by giving
349 // the compiler two choices it can't resolve
350
351 void store_heap_oop(Address dst, void* dummy);
352
353 void encode_heap_oop(Register r);
354 void decode_heap_oop(Register r);
355 void encode_heap_oop_not_null(Register r);
356 void decode_heap_oop_not_null(Register r);
357 void encode_heap_oop_not_null(Register dst, Register src);
358 void decode_heap_oop_not_null(Register dst, Register src);
359
360 void set_narrow_oop(Register dst, jobject obj);
361 void set_narrow_oop(Address dst, jobject obj);
362 void cmp_narrow_oop(Register dst, jobject obj);
363 void cmp_narrow_oop(Address dst, jobject obj);
364
365 void encode_klass_not_null(Register r);
366 void decode_klass_not_null(Register r);
367 void encode_klass_not_null(Register dst, Register src);
368 void decode_klass_not_null(Register dst, Register src);
369 void set_narrow_klass(Register dst, Klass* k);
370 void set_narrow_klass(Address dst, Klass* k);
371 void cmp_narrow_klass(Register dst, Klass* k);
372 void cmp_narrow_klass(Address dst, Klass* k);
373
374 // Returns the byte size of the instructions generated by decode_klass_not_null()
375 // when compressed klass pointers are being used.
376 static int instr_size_for_decode_klass_not_null();
377
378 // if heap base register is used - reinit it with the correct value
379 void reinit_heapbase();
380
381 DEBUG_ONLY(void verify_heapbase(const char* msg);)
382
383 #endif // _LP64
384
385 // Int division/remainder for Java
386 // (as idivl, but checks for special case as described in JVM spec.)
387 // returns idivl instruction offset for implicit exception handling
388 int corrected_idivl(Register reg);
389
390 // Long division/remainder for Java
391 // (as idivq, but checks for special case as described in JVM spec.)
392 // returns idivq instruction offset for implicit exception handling
393 int corrected_idivq(Register reg);
394
395 void int3();
396
397 // Long operation macros for a 32bit cpu
398 // Long negation for Java
399 void lneg(Register hi, Register lo);
400
401 // Long multiplication for Java
402 // (destroys contents of eax, ebx, ecx and edx)
403 void lmul(int x_rsp_offset, int y_rsp_offset); // rdx:rax = x * y
404
405 // Long shifts for Java
406 // (semantics as described in JVM spec.)
407 void lshl(Register hi, Register lo); // hi:lo << (rcx & 0x3f)
408 void lshr(Register hi, Register lo, bool sign_extension = false); // hi:lo >> (rcx & 0x3f)
409
410 // Long compare for Java
411 // (semantics as described in JVM spec.)
412 void lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo); // x_hi = lcmp(x, y)
413
414
415 // misc
416
417 // Sign extension
418 void sign_extend_short(Register reg);
419 void sign_extend_byte(Register reg);
420
421 // Division by power of 2, rounding towards 0
422 void division_with_shift(Register reg, int shift_value);
423
424 // Compares the top-most stack entries on the FPU stack and sets the eflags as follows:
425 //
426 // CF (corresponds to C0) if x < y
427 // PF (corresponds to C2) if unordered
428 // ZF (corresponds to C3) if x = y
429 //
430 // The arguments are in reversed order on the stack (i.e., top of stack is first argument).
431 // tmp is a temporary register, if none is available use noreg (only matters for non-P6 code)
432 void fcmp(Register tmp);
433 // Variant of the above which allows y to be further down the stack
434 // and which only pops x and y if specified. If pop_right is
435 // specified then pop_left must also be specified.
436 void fcmp(Register tmp, int index, bool pop_left, bool pop_right);
437
438 // Floating-point comparison for Java
439 // Compares the top-most stack entries on the FPU stack and stores the result in dst.
440 // The arguments are in reversed order on the stack (i.e., top of stack is first argument).
441 // (semantics as described in JVM spec.)
442 void fcmp2int(Register dst, bool unordered_is_less);
443 // Variant of the above which allows y to be further down the stack
444 // and which only pops x and y if specified. If pop_right is
445 // specified then pop_left must also be specified.
446 void fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right);
447
448 // Floating-point remainder for Java (ST0 = ST0 fremr ST1, ST1 is empty afterwards)
449 // tmp is a temporary register, if none is available use noreg
450 void fremr(Register tmp);
451
452 // dst = c = a * b + c
453 void fmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c);
454 void fmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c);
455
456
457 // same as fcmp2int, but using SSE2
458 void cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less);
459 void cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less);
460
461 // branch to L if FPU flag C2 is set/not set
462 // tmp is a temporary register, if none is available use noreg
463 void jC2 (Register tmp, Label& L);
464 void jnC2(Register tmp, Label& L);
465
466 // Pop ST (ffree & fincstp combined)
467 void fpop();
468
469 // Load float value from 'address'. If UseSSE >= 1, the value is loaded into
470 // register xmm0. Otherwise, the value is loaded onto the FPU stack.
471 void load_float(Address src);
472
473 // Store float value to 'address'. If UseSSE >= 1, the value is stored
474 // from register xmm0. Otherwise, the value is stored from the FPU stack.
475 void store_float(Address dst);
476
477 // Load double value from 'address'. If UseSSE >= 2, the value is loaded into
478 // register xmm0. Otherwise, the value is loaded onto the FPU stack.
479 void load_double(Address src);
480
481 // Store double value to 'address'. If UseSSE >= 2, the value is stored
482 // from register xmm0. Otherwise, the value is stored from the FPU stack.
483 void store_double(Address dst);
484
485 // pushes double TOS element of FPU stack on CPU stack; pops from FPU stack
486 void push_fTOS();
487
488 // pops double TOS element from CPU stack and pushes on FPU stack
489 void pop_fTOS();
490
491 void empty_FPU_stack();
492
493 void push_IU_state();
494 void pop_IU_state();
495
496 void push_FPU_state();
497 void pop_FPU_state();
498
499 void push_CPU_state();
500 void pop_CPU_state();
501
502 // Round up to a power of two
503 void round_to(Register reg, int modulus);
504
505 // Callee saved registers handling
506 void push_callee_saved_registers();
507 void pop_callee_saved_registers();
508
509 // allocation
510 void eden_allocate(
511 Register obj, // result: pointer to object after successful allocation
512 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
513 int con_size_in_bytes, // object size in bytes if known at compile time
514 Register t1, // temp register
515 Label& slow_case // continuation point if fast allocation fails
516 );
517 void tlab_allocate(
518 Register obj, // result: pointer to object after successful allocation
519 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
520 int con_size_in_bytes, // object size in bytes if known at compile time
521 Register t1, // temp register
522 Register t2, // temp register
523 Label& slow_case // continuation point if fast allocation fails
524 );
525 Register tlab_refill(Label& retry_tlab, Label& try_eden, Label& slow_case); // returns TLS address
526 void zero_memory(Register address, Register length_in_bytes, int offset_in_bytes, Register temp);
527
528 void incr_allocated_bytes(Register thread,
529 Register var_size_in_bytes, int con_size_in_bytes,
530 Register t1 = noreg);
531
532 // interface method calling
533 void lookup_interface_method(Register recv_klass,
534 Register intf_klass,
535 RegisterOrConstant itable_index,
536 Register method_result,
537 Register scan_temp,
538 Label& no_such_interface);
539
540 // virtual method calling
541 void lookup_virtual_method(Register recv_klass,
542 RegisterOrConstant vtable_index,
543 Register method_result);
544
545 // Test sub_klass against super_klass, with fast and slow paths.
546
547 // The fast path produces a tri-state answer: yes / no / maybe-slow.
548 // One of the three labels can be NULL, meaning take the fall-through.
549 // If super_check_offset is -1, the value is loaded up from super_klass.
550 // No registers are killed, except temp_reg.
551 void check_klass_subtype_fast_path(Register sub_klass,
552 Register super_klass,
553 Register temp_reg,
554 Label* L_success,
555 Label* L_failure,
556 Label* L_slow_path,
557 RegisterOrConstant super_check_offset = RegisterOrConstant(-1));
558
559 // The rest of the type check; must be wired to a corresponding fast path.
560 // It does not repeat the fast path logic, so don't use it standalone.
561 // The temp_reg and temp2_reg can be noreg, if no temps are available.
562 // Updates the sub's secondary super cache as necessary.
563 // If set_cond_codes, condition codes will be Z on success, NZ on failure.
564 void check_klass_subtype_slow_path(Register sub_klass,
565 Register super_klass,
566 Register temp_reg,
567 Register temp2_reg,
568 Label* L_success,
569 Label* L_failure,
570 bool set_cond_codes = false);
571
572 // Simplified, combined version, good for typical uses.
573 // Falls through on failure.
574 void check_klass_subtype(Register sub_klass,
575 Register super_klass,
576 Register temp_reg,
577 Label& L_success);
578
579 // method handles (JSR 292)
580 Address argument_address(RegisterOrConstant arg_slot, int extra_slot_offset = 0);
581
582 //----
583 void set_word_if_not_zero(Register reg); // sets reg to 1 if not zero, otherwise 0
584
585 // Debugging
586
587 // only if +VerifyOops
588 // TODO: Make these macros with file and line like sparc version!
589 void verify_oop(Register reg, const char* s = "broken oop");
590 void verify_oop_addr(Address addr, const char * s = "broken oop addr");
591
592 // TODO: verify method and klass metadata (compare against vptr?)
593 void _verify_method_ptr(Register reg, const char * msg, const char * file, int line) {}
594 void _verify_klass_ptr(Register reg, const char * msg, const char * file, int line){}
595
596 #define verify_method_ptr(reg) _verify_method_ptr(reg, "broken method " #reg, __FILE__, __LINE__)
597 #define verify_klass_ptr(reg) _verify_klass_ptr(reg, "broken klass " #reg, __FILE__, __LINE__)
598
599 // only if +VerifyFPU
600 void verify_FPU(int stack_depth, const char* s = "illegal FPU state");
601
602 // Verify or restore cpu control state after JNI call
603 void restore_cpu_control_state_after_jni();
604
605 // prints msg, dumps registers and stops execution
606 void stop(const char* msg);
607
608 // prints msg and continues
609 void warn(const char* msg);
610
611 // dumps registers and other state
612 void print_state();
613
614 static void debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg);
615 static void debug64(char* msg, int64_t pc, int64_t regs[]);
616 static void print_state32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip);
617 static void print_state64(int64_t pc, int64_t regs[]);
618
619 void os_breakpoint();
620
621 void untested() { stop("untested"); }
622
623 void unimplemented(const char* what = "") { char* b = new char[1024]; jio_snprintf(b, 1024, "unimplemented: %s", what); stop(b); }
624
625 void should_not_reach_here() { stop("should not reach here"); }
626
627 void print_CPU_state();
628
629 // Stack overflow checking
630 void bang_stack_with_offset(int offset) {
631 // stack grows down, caller passes positive offset
632 assert(offset > 0, "must bang with negative offset");
633 movl(Address(rsp, (-offset)), rax);
634 }
635
636 // Writes to stack successive pages until offset reached to check for
637 // stack overflow + shadow pages. Also, clobbers tmp
638 void bang_stack_size(Register size, Register tmp);
639
640 // Check for reserved stack access in method being exited (for JIT)
641 void reserved_stack_check();
642
643 virtual RegisterOrConstant delayed_value_impl(intptr_t* delayed_value_addr,
644 Register tmp,
645 int offset);
646
647 // Support for serializing memory accesses between threads
648 void serialize_memory(Register thread, Register tmp);
649
650 void verify_tlab();
651
652 // Biased locking support
653 // lock_reg and obj_reg must be loaded up with the appropriate values.
654 // swap_reg must be rax, and is killed.
655 // tmp_reg is optional. If it is supplied (i.e., != noreg) it will
656 // be killed; if not supplied, push/pop will be used internally to
657 // allocate a temporary (inefficient, avoid if possible).
658 // Optional slow case is for implementations (interpreter and C1) which branch to
659 // slow case directly. Leaves condition codes set for C2's Fast_Lock node.
660 // Returns offset of first potentially-faulting instruction for null
661 // check info (currently consumed only by C1). If
662 // swap_reg_contains_mark is true then returns -1 as it is assumed
663 // the calling code has already passed any potential faults.
664 int biased_locking_enter(Register lock_reg, Register obj_reg,
665 Register swap_reg, Register tmp_reg,
666 bool swap_reg_contains_mark,
667 Label& done, Label* slow_case = NULL,
668 BiasedLockingCounters* counters = NULL);
669 void biased_locking_exit (Register obj_reg, Register temp_reg, Label& done);
670 #ifdef COMPILER2
671 // Code used by cmpFastLock and cmpFastUnlock mach instructions in .ad file.
672 // See full desription in macroAssembler_x86.cpp.
673 void fast_lock(Register obj, Register box, Register tmp,
674 Register scr, Register cx1, Register cx2,
675 BiasedLockingCounters* counters,
676 RTMLockingCounters* rtm_counters,
677 RTMLockingCounters* stack_rtm_counters,
678 Metadata* method_data,
679 bool use_rtm, bool profile_rtm);
680 void fast_unlock(Register obj, Register box, Register tmp, bool use_rtm);
681 #if INCLUDE_RTM_OPT
682 void rtm_counters_update(Register abort_status, Register rtm_counters);
683 void branch_on_random_using_rdtsc(Register tmp, Register scr, int count, Label& brLabel);
684 void rtm_abort_ratio_calculation(Register tmp, Register rtm_counters_reg,
685 RTMLockingCounters* rtm_counters,
686 Metadata* method_data);
687 void rtm_profiling(Register abort_status_Reg, Register rtm_counters_Reg,
688 RTMLockingCounters* rtm_counters, Metadata* method_data, bool profile_rtm);
689 void rtm_retry_lock_on_abort(Register retry_count, Register abort_status, Label& retryLabel);
690 void rtm_retry_lock_on_busy(Register retry_count, Register box, Register tmp, Register scr, Label& retryLabel);
691 void rtm_stack_locking(Register obj, Register tmp, Register scr,
692 Register retry_on_abort_count,
693 RTMLockingCounters* stack_rtm_counters,
694 Metadata* method_data, bool profile_rtm,
695 Label& DONE_LABEL, Label& IsInflated);
696 void rtm_inflated_locking(Register obj, Register box, Register tmp,
697 Register scr, Register retry_on_busy_count,
698 Register retry_on_abort_count,
699 RTMLockingCounters* rtm_counters,
700 Metadata* method_data, bool profile_rtm,
701 Label& DONE_LABEL);
702 #endif
703 #endif
704
705 Condition negate_condition(Condition cond);
706
707 // Instructions that use AddressLiteral operands. These instruction can handle 32bit/64bit
708 // operands. In general the names are modified to avoid hiding the instruction in Assembler
709 // so that we don't need to implement all the varieties in the Assembler with trivial wrappers
710 // here in MacroAssembler. The major exception to this rule is call
711
712 // Arithmetics
713
714
715 void addptr(Address dst, int32_t src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)) ; }
716 void addptr(Address dst, Register src);
717
718 void addptr(Register dst, Address src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)); }
719 void addptr(Register dst, int32_t src);
720 void addptr(Register dst, Register src);
721 void addptr(Register dst, RegisterOrConstant src) {
722 if (src.is_constant()) addptr(dst, (int) src.as_constant());
723 else addptr(dst, src.as_register());
724 }
725
726 void andptr(Register dst, int32_t src);
727 void andptr(Register src1, Register src2) { LP64_ONLY(andq(src1, src2)) NOT_LP64(andl(src1, src2)) ; }
728
729 void cmp8(AddressLiteral src1, int imm);
730
731 // renamed to drag out the casting of address to int32_t/intptr_t
732 void cmp32(Register src1, int32_t imm);
733
734 void cmp32(AddressLiteral src1, int32_t imm);
735 // compare reg - mem, or reg - &mem
736 void cmp32(Register src1, AddressLiteral src2);
737
738 void cmp32(Register src1, Address src2);
739
740 #ifndef _LP64
741 void cmpklass(Address dst, Metadata* obj);
742 void cmpklass(Register dst, Metadata* obj);
743 void cmpoop(Address dst, jobject obj);
744 void cmpoop(Register dst, jobject obj);
745 #endif // _LP64
746
747 // NOTE src2 must be the lval. This is NOT an mem-mem compare
748 void cmpptr(Address src1, AddressLiteral src2);
749
750 void cmpptr(Register src1, AddressLiteral src2);
751
752 void cmpptr(Register src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
753 void cmpptr(Register src1, Address src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
754 // void cmpptr(Address src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
755
756 void cmpptr(Register src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
757 void cmpptr(Address src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
758
759 // cmp64 to avoild hiding cmpq
760 void cmp64(Register src1, AddressLiteral src);
761
762 void cmpxchgptr(Register reg, Address adr);
763
764 void locked_cmpxchgptr(Register reg, AddressLiteral adr);
765
766
767 void imulptr(Register dst, Register src) { LP64_ONLY(imulq(dst, src)) NOT_LP64(imull(dst, src)); }
768 void imulptr(Register dst, Register src, int imm32) { LP64_ONLY(imulq(dst, src, imm32)) NOT_LP64(imull(dst, src, imm32)); }
769
770
771 void negptr(Register dst) { LP64_ONLY(negq(dst)) NOT_LP64(negl(dst)); }
772
773 void notptr(Register dst) { LP64_ONLY(notq(dst)) NOT_LP64(notl(dst)); }
774
775 void shlptr(Register dst, int32_t shift);
776 void shlptr(Register dst) { LP64_ONLY(shlq(dst)) NOT_LP64(shll(dst)); }
777
778 void shrptr(Register dst, int32_t shift);
779 void shrptr(Register dst) { LP64_ONLY(shrq(dst)) NOT_LP64(shrl(dst)); }
780
781 void sarptr(Register dst) { LP64_ONLY(sarq(dst)) NOT_LP64(sarl(dst)); }
782 void sarptr(Register dst, int32_t src) { LP64_ONLY(sarq(dst, src)) NOT_LP64(sarl(dst, src)); }
783
784 void subptr(Address dst, int32_t src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); }
785
786 void subptr(Register dst, Address src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); }
787 void subptr(Register dst, int32_t src);
788 // Force generation of a 4 byte immediate value even if it fits into 8bit
789 void subptr_imm32(Register dst, int32_t src);
790 void subptr(Register dst, Register src);
791 void subptr(Register dst, RegisterOrConstant src) {
792 if (src.is_constant()) subptr(dst, (int) src.as_constant());
793 else subptr(dst, src.as_register());
794 }
795
796 void sbbptr(Address dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); }
797 void sbbptr(Register dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); }
798
799 void xchgptr(Register src1, Register src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; }
800 void xchgptr(Register src1, Address src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; }
801
802 void xaddptr(Address src1, Register src2) { LP64_ONLY(xaddq(src1, src2)) NOT_LP64(xaddl(src1, src2)) ; }
803
804
805
806 // Helper functions for statistics gathering.
807 // Conditionally (atomically, on MPs) increments passed counter address, preserving condition codes.
808 void cond_inc32(Condition cond, AddressLiteral counter_addr);
809 // Unconditional atomic increment.
810 void atomic_incl(Address counter_addr);
811 void atomic_incl(AddressLiteral counter_addr, Register scr = rscratch1);
812 #ifdef _LP64
813 void atomic_incq(Address counter_addr);
814 void atomic_incq(AddressLiteral counter_addr, Register scr = rscratch1);
815 #endif
816 void atomic_incptr(AddressLiteral counter_addr, Register scr = rscratch1) { LP64_ONLY(atomic_incq(counter_addr, scr)) NOT_LP64(atomic_incl(counter_addr, scr)) ; }
817 void atomic_incptr(Address counter_addr) { LP64_ONLY(atomic_incq(counter_addr)) NOT_LP64(atomic_incl(counter_addr)) ; }
818
819 void lea(Register dst, AddressLiteral adr);
820 void lea(Address dst, AddressLiteral adr);
821 void lea(Register dst, Address adr) { Assembler::lea(dst, adr); }
822
823 void leal32(Register dst, Address src) { leal(dst, src); }
824
825 // Import other testl() methods from the parent class or else
826 // they will be hidden by the following overriding declaration.
827 using Assembler::testl;
828 void testl(Register dst, AddressLiteral src);
829
830 void orptr(Register dst, Address src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
831 void orptr(Register dst, Register src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
832 void orptr(Register dst, int32_t src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
833 void orptr(Address dst, int32_t imm32) { LP64_ONLY(orq(dst, imm32)) NOT_LP64(orl(dst, imm32)); }
834
835 void testptr(Register src, int32_t imm32) { LP64_ONLY(testq(src, imm32)) NOT_LP64(testl(src, imm32)); }
836 void testptr(Register src1, Register src2);
837
838 void xorptr(Register dst, Register src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); }
839 void xorptr(Register dst, Address src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); }
840
841 // Calls
842
843 void call(Label& L, relocInfo::relocType rtype);
844 void call(Register entry);
845
846 // NOTE: this call transfers to the effective address of entry NOT
847 // the address contained by entry. This is because this is more natural
848 // for jumps/calls.
849 void call(AddressLiteral entry);
850
851 // Emit the CompiledIC call idiom
852 void ic_call(address entry, jint method_index = 0);
853
854 // Jumps
855
856 // NOTE: these jumps tranfer to the effective address of dst NOT
857 // the address contained by dst. This is because this is more natural
858 // for jumps/calls.
859 void jump(AddressLiteral dst);
860 void jump_cc(Condition cc, AddressLiteral dst);
861
862 // 32bit can do a case table jump in one instruction but we no longer allow the base
863 // to be installed in the Address class. This jump will tranfers to the address
864 // contained in the location described by entry (not the address of entry)
865 void jump(ArrayAddress entry);
866
867 // Floating
868
869 void andpd(XMMRegister dst, Address src) { Assembler::andpd(dst, src); }
870 void andpd(XMMRegister dst, AddressLiteral src);
871 void andpd(XMMRegister dst, XMMRegister src) { Assembler::andpd(dst, src); }
872
873 void andps(XMMRegister dst, XMMRegister src) { Assembler::andps(dst, src); }
874 void andps(XMMRegister dst, Address src) { Assembler::andps(dst, src); }
875 void andps(XMMRegister dst, AddressLiteral src);
876
877 void comiss(XMMRegister dst, XMMRegister src) { Assembler::comiss(dst, src); }
878 void comiss(XMMRegister dst, Address src) { Assembler::comiss(dst, src); }
879 void comiss(XMMRegister dst, AddressLiteral src);
880
881 void comisd(XMMRegister dst, XMMRegister src) { Assembler::comisd(dst, src); }
882 void comisd(XMMRegister dst, Address src) { Assembler::comisd(dst, src); }
883 void comisd(XMMRegister dst, AddressLiteral src);
884
885 void fadd_s(Address src) { Assembler::fadd_s(src); }
886 void fadd_s(AddressLiteral src) { Assembler::fadd_s(as_Address(src)); }
887
888 void fldcw(Address src) { Assembler::fldcw(src); }
889 void fldcw(AddressLiteral src);
890
891 void fld_s(int index) { Assembler::fld_s(index); }
892 void fld_s(Address src) { Assembler::fld_s(src); }
893 void fld_s(AddressLiteral src);
894
895 void fld_d(Address src) { Assembler::fld_d(src); }
896 void fld_d(AddressLiteral src);
897
898 void fld_x(Address src) { Assembler::fld_x(src); }
899 void fld_x(AddressLiteral src);
900
901 void fmul_s(Address src) { Assembler::fmul_s(src); }
902 void fmul_s(AddressLiteral src) { Assembler::fmul_s(as_Address(src)); }
903
904 void ldmxcsr(Address src) { Assembler::ldmxcsr(src); }
905 void ldmxcsr(AddressLiteral src);
906
907 #ifdef _LP64
908 private:
909 void sha256_AVX2_one_round_compute(
910 Register reg_old_h,
911 Register reg_a,
912 Register reg_b,
913 Register reg_c,
914 Register reg_d,
915 Register reg_e,
916 Register reg_f,
917 Register reg_g,
918 Register reg_h,
919 int iter);
920 void sha256_AVX2_four_rounds_compute_first(int start);
921 void sha256_AVX2_four_rounds_compute_last(int start);
922 void sha256_AVX2_one_round_and_sched(
923 XMMRegister xmm_0, /* == ymm4 on 0, 1, 2, 3 iterations, then rotate 4 registers left on 4, 8, 12 iterations */
924 XMMRegister xmm_1, /* ymm5 */ /* full cycle is 16 iterations */
925 XMMRegister xmm_2, /* ymm6 */
926 XMMRegister xmm_3, /* ymm7 */
927 Register reg_a, /* == eax on 0 iteration, then rotate 8 register right on each next iteration */
928 Register reg_b, /* ebx */ /* full cycle is 8 iterations */
929 Register reg_c, /* edi */
930 Register reg_d, /* esi */
931 Register reg_e, /* r8d */
932 Register reg_f, /* r9d */
933 Register reg_g, /* r10d */
934 Register reg_h, /* r11d */
935 int iter);
936
937 void addm(int disp, Register r1, Register r2);
938
939 public:
940 void sha256_AVX2(XMMRegister msg, XMMRegister state0, XMMRegister state1, XMMRegister msgtmp0,
941 XMMRegister msgtmp1, XMMRegister msgtmp2, XMMRegister msgtmp3, XMMRegister msgtmp4,
942 Register buf, Register state, Register ofs, Register limit, Register rsp,
943 bool multi_block, XMMRegister shuf_mask);
944 #endif
945
946 #ifdef _LP64
947 private:
948 void sha512_AVX2_one_round_compute(Register old_h, Register a, Register b, Register c, Register d,
949 Register e, Register f, Register g, Register h, int iteration);
950
951 void sha512_AVX2_one_round_and_schedule(XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
952 Register a, Register b, Register c, Register d, Register e, Register f,
953 Register g, Register h, int iteration);
954
955 void addmq(int disp, Register r1, Register r2);
956 public:
957 void sha512_AVX2(XMMRegister msg, XMMRegister state0, XMMRegister state1, XMMRegister msgtmp0,
958 XMMRegister msgtmp1, XMMRegister msgtmp2, XMMRegister msgtmp3, XMMRegister msgtmp4,
959 Register buf, Register state, Register ofs, Register limit, Register rsp, bool multi_block,
960 XMMRegister shuf_mask);
961 #endif
962
963 void fast_sha1(XMMRegister abcd, XMMRegister e0, XMMRegister e1, XMMRegister msg0,
964 XMMRegister msg1, XMMRegister msg2, XMMRegister msg3, XMMRegister shuf_mask,
965 Register buf, Register state, Register ofs, Register limit, Register rsp,
966 bool multi_block);
967
968 #ifdef _LP64
969 void fast_sha256(XMMRegister msg, XMMRegister state0, XMMRegister state1, XMMRegister msgtmp0,
970 XMMRegister msgtmp1, XMMRegister msgtmp2, XMMRegister msgtmp3, XMMRegister msgtmp4,
971 Register buf, Register state, Register ofs, Register limit, Register rsp,
972 bool multi_block, XMMRegister shuf_mask);
973 #else
974 void fast_sha256(XMMRegister msg, XMMRegister state0, XMMRegister state1, XMMRegister msgtmp0,
975 XMMRegister msgtmp1, XMMRegister msgtmp2, XMMRegister msgtmp3, XMMRegister msgtmp4,
976 Register buf, Register state, Register ofs, Register limit, Register rsp,
977 bool multi_block);
978 #endif
979
980 void fast_exp(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
981 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
982 Register rax, Register rcx, Register rdx, Register tmp);
983
984 #ifdef _LP64
985 void fast_log(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
986 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
987 Register rax, Register rcx, Register rdx, Register tmp1, Register tmp2);
988
989 void fast_log10(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
990 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
991 Register rax, Register rcx, Register rdx, Register r11);
992
993 void fast_pow(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3, XMMRegister xmm4,
994 XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7, Register rax, Register rcx,
995 Register rdx, Register tmp1, Register tmp2, Register tmp3, Register tmp4);
996
997 void fast_sin(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
998 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
999 Register rax, Register rbx, Register rcx, Register rdx, Register tmp1, Register tmp2,
1000 Register tmp3, Register tmp4);
1001
1002 void fast_cos(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1003 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1004 Register rax, Register rcx, Register rdx, Register tmp1,
1005 Register tmp2, Register tmp3, Register tmp4);
1006 void fast_tan(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1007 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1008 Register rax, Register rcx, Register rdx, Register tmp1,
1009 Register tmp2, Register tmp3, Register tmp4);
1010 #else
1011 void fast_log(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1012 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1013 Register rax, Register rcx, Register rdx, Register tmp1);
1014
1015 void fast_log10(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1016 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1017 Register rax, Register rcx, Register rdx, Register tmp);
1018
1019 void fast_pow(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3, XMMRegister xmm4,
1020 XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7, Register rax, Register rcx,
1021 Register rdx, Register tmp);
1022
1023 void fast_sin(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1024 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1025 Register rax, Register rbx, Register rdx);
1026
1027 void fast_cos(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1028 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1029 Register rax, Register rcx, Register rdx, Register tmp);
1030
1031 void libm_sincos_huge(XMMRegister xmm0, XMMRegister xmm1, Register eax, Register ecx,
1032 Register edx, Register ebx, Register esi, Register edi,
1033 Register ebp, Register esp);
1034
1035 void libm_reduce_pi04l(Register eax, Register ecx, Register edx, Register ebx,
1036 Register esi, Register edi, Register ebp, Register esp);
1037
1038 void libm_tancot_huge(XMMRegister xmm0, XMMRegister xmm1, Register eax, Register ecx,
1039 Register edx, Register ebx, Register esi, Register edi,
1040 Register ebp, Register esp);
1041
1042 void fast_tan(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1043 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1044 Register rax, Register rcx, Register rdx, Register tmp);
1045 #endif
1046
1047 void increase_precision();
1048 void restore_precision();
1049
1050 private:
1051
1052 // these are private because users should be doing movflt/movdbl
1053
1054 void movss(Address dst, XMMRegister src) { Assembler::movss(dst, src); }
1055 void movss(XMMRegister dst, XMMRegister src) { Assembler::movss(dst, src); }
1056 void movss(XMMRegister dst, Address src) { Assembler::movss(dst, src); }
1057 void movss(XMMRegister dst, AddressLiteral src);
1058
1059 void movlpd(XMMRegister dst, Address src) {Assembler::movlpd(dst, src); }
1060 void movlpd(XMMRegister dst, AddressLiteral src);
1061
1062 public:
1063
1064 void addsd(XMMRegister dst, XMMRegister src) { Assembler::addsd(dst, src); }
1065 void addsd(XMMRegister dst, Address src) { Assembler::addsd(dst, src); }
1066 void addsd(XMMRegister dst, AddressLiteral src);
1067
1068 void addss(XMMRegister dst, XMMRegister src) { Assembler::addss(dst, src); }
1069 void addss(XMMRegister dst, Address src) { Assembler::addss(dst, src); }
1070 void addss(XMMRegister dst, AddressLiteral src);
1071
1072 void addpd(XMMRegister dst, XMMRegister src) { Assembler::addpd(dst, src); }
1073 void addpd(XMMRegister dst, Address src) { Assembler::addpd(dst, src); }
1074 void addpd(XMMRegister dst, AddressLiteral src);
1075
1076 void divsd(XMMRegister dst, XMMRegister src) { Assembler::divsd(dst, src); }
1077 void divsd(XMMRegister dst, Address src) { Assembler::divsd(dst, src); }
1078 void divsd(XMMRegister dst, AddressLiteral src);
1079
1080 void divss(XMMRegister dst, XMMRegister src) { Assembler::divss(dst, src); }
1081 void divss(XMMRegister dst, Address src) { Assembler::divss(dst, src); }
1082 void divss(XMMRegister dst, AddressLiteral src);
1083
1084 // Move Unaligned Double Quadword
1085 void movdqu(Address dst, XMMRegister src);
1086 void movdqu(XMMRegister dst, Address src);
1087 void movdqu(XMMRegister dst, XMMRegister src);
1088 void movdqu(XMMRegister dst, AddressLiteral src, Register scratchReg = rscratch1);
1089 // AVX Unaligned forms
1090 void vmovdqu(Address dst, XMMRegister src);
1091 void vmovdqu(XMMRegister dst, Address src);
1092 void vmovdqu(XMMRegister dst, XMMRegister src);
1093 void vmovdqu(XMMRegister dst, AddressLiteral src);
1094
1095 // Move Aligned Double Quadword
1096 void movdqa(XMMRegister dst, Address src) { Assembler::movdqa(dst, src); }
1097 void movdqa(XMMRegister dst, XMMRegister src) { Assembler::movdqa(dst, src); }
1098 void movdqa(XMMRegister dst, AddressLiteral src);
1099
1100 void movsd(XMMRegister dst, XMMRegister src) { Assembler::movsd(dst, src); }
1101 void movsd(Address dst, XMMRegister src) { Assembler::movsd(dst, src); }
1102 void movsd(XMMRegister dst, Address src) { Assembler::movsd(dst, src); }
1103 void movsd(XMMRegister dst, AddressLiteral src);
1104
1105 void mulpd(XMMRegister dst, XMMRegister src) { Assembler::mulpd(dst, src); }
1106 void mulpd(XMMRegister dst, Address src) { Assembler::mulpd(dst, src); }
1107 void mulpd(XMMRegister dst, AddressLiteral src);
1108
1109 void mulsd(XMMRegister dst, XMMRegister src) { Assembler::mulsd(dst, src); }
1110 void mulsd(XMMRegister dst, Address src) { Assembler::mulsd(dst, src); }
1111 void mulsd(XMMRegister dst, AddressLiteral src);
1112
1113 void mulss(XMMRegister dst, XMMRegister src) { Assembler::mulss(dst, src); }
1114 void mulss(XMMRegister dst, Address src) { Assembler::mulss(dst, src); }
1115 void mulss(XMMRegister dst, AddressLiteral src);
1116
1117 // Carry-Less Multiplication Quadword
1118 void pclmulldq(XMMRegister dst, XMMRegister src) {
1119 // 0x00 - multiply lower 64 bits [0:63]
1120 Assembler::pclmulqdq(dst, src, 0x00);
1121 }
1122 void pclmulhdq(XMMRegister dst, XMMRegister src) {
1123 // 0x11 - multiply upper 64 bits [64:127]
1124 Assembler::pclmulqdq(dst, src, 0x11);
1125 }
1126
1127 void pcmpeqb(XMMRegister dst, XMMRegister src);
1128 void pcmpeqw(XMMRegister dst, XMMRegister src);
1129
1130 void pcmpestri(XMMRegister dst, Address src, int imm8);
1131 void pcmpestri(XMMRegister dst, XMMRegister src, int imm8);
1132
1133 void pmovzxbw(XMMRegister dst, XMMRegister src);
1134 void pmovzxbw(XMMRegister dst, Address src);
1135
1136 void pmovmskb(Register dst, XMMRegister src);
1137
1138 void ptest(XMMRegister dst, XMMRegister src);
1139
1140 void sqrtsd(XMMRegister dst, XMMRegister src) { Assembler::sqrtsd(dst, src); }
1141 void sqrtsd(XMMRegister dst, Address src) { Assembler::sqrtsd(dst, src); }
1142 void sqrtsd(XMMRegister dst, AddressLiteral src);
1143
1144 void sqrtss(XMMRegister dst, XMMRegister src) { Assembler::sqrtss(dst, src); }
1145 void sqrtss(XMMRegister dst, Address src) { Assembler::sqrtss(dst, src); }
1146 void sqrtss(XMMRegister dst, AddressLiteral src);
1147
1148 void subsd(XMMRegister dst, XMMRegister src) { Assembler::subsd(dst, src); }
1149 void subsd(XMMRegister dst, Address src) { Assembler::subsd(dst, src); }
1150 void subsd(XMMRegister dst, AddressLiteral src);
1151
1152 void subss(XMMRegister dst, XMMRegister src) { Assembler::subss(dst, src); }
1153 void subss(XMMRegister dst, Address src) { Assembler::subss(dst, src); }
1154 void subss(XMMRegister dst, AddressLiteral src);
1155
1156 void ucomiss(XMMRegister dst, XMMRegister src) { Assembler::ucomiss(dst, src); }
1157 void ucomiss(XMMRegister dst, Address src) { Assembler::ucomiss(dst, src); }
1158 void ucomiss(XMMRegister dst, AddressLiteral src);
1159
1160 void ucomisd(XMMRegister dst, XMMRegister src) { Assembler::ucomisd(dst, src); }
1161 void ucomisd(XMMRegister dst, Address src) { Assembler::ucomisd(dst, src); }
1162 void ucomisd(XMMRegister dst, AddressLiteral src);
1163
1164 // Bitwise Logical XOR of Packed Double-Precision Floating-Point Values
1165 void xorpd(XMMRegister dst, XMMRegister src);
1166 void xorpd(XMMRegister dst, Address src) { Assembler::xorpd(dst, src); }
1167 void xorpd(XMMRegister dst, AddressLiteral src);
1168
1169 // Bitwise Logical XOR of Packed Single-Precision Floating-Point Values
1170 void xorps(XMMRegister dst, XMMRegister src);
1171 void xorps(XMMRegister dst, Address src) { Assembler::xorps(dst, src); }
1172 void xorps(XMMRegister dst, AddressLiteral src);
1173
1174 // Shuffle Bytes
1175 void pshufb(XMMRegister dst, XMMRegister src) { Assembler::pshufb(dst, src); }
1176 void pshufb(XMMRegister dst, Address src) { Assembler::pshufb(dst, src); }
1177 void pshufb(XMMRegister dst, AddressLiteral src);
1178 // AVX 3-operands instructions
1179
1180 void vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vaddsd(dst, nds, src); }
1181 void vaddsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vaddsd(dst, nds, src); }
1182 void vaddsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1183
1184 void vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vaddss(dst, nds, src); }
1185 void vaddss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vaddss(dst, nds, src); }
1186 void vaddss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1187
1188 void vabsss(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len);
1189 void vabssd(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len);
1190
1191 void vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1192 void vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1193
1194 void vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1195 void vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1196
1197 void vpand(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vpand(dst, nds, src, vector_len); }
1198 void vpand(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vpand(dst, nds, src, vector_len); }
1199 void vpand(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len);
1200
1201 void vpbroadcastw(XMMRegister dst, XMMRegister src);
1202
1203 void vpcmpeqb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1204 void vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1205
1206 void vpmovzxbw(XMMRegister dst, Address src, int vector_len);
1207 void vpmovmskb(Register dst, XMMRegister src);
1208
1209 void vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1210 void vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1211
1212 void vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1213 void vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1214
1215 void vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1216 void vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1217
1218 void vpsraw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len);
1219 void vpsraw(XMMRegister dst, XMMRegister nds, int shift, int vector_len);
1220
1221 void vpsrlw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len);
1222 void vpsrlw(XMMRegister dst, XMMRegister nds, int shift, int vector_len);
1223
1224 void vpsllw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len);
1225 void vpsllw(XMMRegister dst, XMMRegister nds, int shift, int vector_len);
1226
1227 void vptest(XMMRegister dst, XMMRegister src);
1228
1229 void punpcklbw(XMMRegister dst, XMMRegister src);
1230 void punpcklbw(XMMRegister dst, Address src) { Assembler::punpcklbw(dst, src); }
1231
1232 void pshuflw(XMMRegister dst, XMMRegister src, int mode);
1233 void pshuflw(XMMRegister dst, Address src, int mode) { Assembler::pshuflw(dst, src, mode); }
1234
1235 void vandpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vandpd(dst, nds, src, vector_len); }
1236 void vandpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vandpd(dst, nds, src, vector_len); }
1237 void vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len);
1238
1239 void vandps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vandps(dst, nds, src, vector_len); }
1240 void vandps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vandps(dst, nds, src, vector_len); }
1241 void vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len);
1242
1243 void vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vdivsd(dst, nds, src); }
1244 void vdivsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vdivsd(dst, nds, src); }
1245 void vdivsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1246
1247 void vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vdivss(dst, nds, src); }
1248 void vdivss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vdivss(dst, nds, src); }
1249 void vdivss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1250
1251 void vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vmulsd(dst, nds, src); }
1252 void vmulsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vmulsd(dst, nds, src); }
1253 void vmulsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1254
1255 void vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vmulss(dst, nds, src); }
1256 void vmulss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vmulss(dst, nds, src); }
1257 void vmulss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1258
1259 void vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vsubsd(dst, nds, src); }
1260 void vsubsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vsubsd(dst, nds, src); }
1261 void vsubsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1262
1263 void vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vsubss(dst, nds, src); }
1264 void vsubss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vsubss(dst, nds, src); }
1265 void vsubss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1266
1267 void vnegatess(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1268 void vnegatesd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1269
1270 // AVX Vector instructions
1271
1272 void vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vxorpd(dst, nds, src, vector_len); }
1273 void vxorpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vxorpd(dst, nds, src, vector_len); }
1274 void vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len);
1275
1276 void vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vxorps(dst, nds, src, vector_len); }
1277 void vxorps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vxorps(dst, nds, src, vector_len); }
1278 void vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len);
1279
1280 void vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
1281 if (UseAVX > 1 || (vector_len < 1)) // vpxor 256 bit is available only in AVX2
1282 Assembler::vpxor(dst, nds, src, vector_len);
1283 else
1284 Assembler::vxorpd(dst, nds, src, vector_len);
1285 }
1286 void vpxor(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
1287 if (UseAVX > 1 || (vector_len < 1)) // vpxor 256 bit is available only in AVX2
1288 Assembler::vpxor(dst, nds, src, vector_len);
1289 else
1290 Assembler::vxorpd(dst, nds, src, vector_len);
1291 }
1292
1293 // Simple version for AVX2 256bit vectors
1294 void vpxor(XMMRegister dst, XMMRegister src) { Assembler::vpxor(dst, dst, src, true); }
1295 void vpxor(XMMRegister dst, Address src) { Assembler::vpxor(dst, dst, src, true); }
1296
1297 void vinserti128(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
1298 if (UseAVX > 2) {
1299 Assembler::vinserti32x4(dst, dst, src, imm8);
1300 } else if (UseAVX > 1) {
1301 // vinserti128 is available only in AVX2
1302 Assembler::vinserti128(dst, nds, src, imm8);
1303 } else {
1304 Assembler::vinsertf128(dst, nds, src, imm8);
1305 }
1306 }
1307
1308 void vinserti128(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
1309 if (UseAVX > 2) {
1310 Assembler::vinserti32x4(dst, dst, src, imm8);
1311 } else if (UseAVX > 1) {
1312 // vinserti128 is available only in AVX2
1313 Assembler::vinserti128(dst, nds, src, imm8);
1314 } else {
1315 Assembler::vinsertf128(dst, nds, src, imm8);
1316 }
1317 }
1318
1319 void vextracti128(XMMRegister dst, XMMRegister src, uint8_t imm8) {
1320 if (UseAVX > 2) {
1321 Assembler::vextracti32x4(dst, src, imm8);
1322 } else if (UseAVX > 1) {
1323 // vextracti128 is available only in AVX2
1324 Assembler::vextracti128(dst, src, imm8);
1325 } else {
1326 Assembler::vextractf128(dst, src, imm8);
1327 }
1328 }
1329
1330 void vextracti128(Address dst, XMMRegister src, uint8_t imm8) {
1331 if (UseAVX > 2) {
1332 Assembler::vextracti32x4(dst, src, imm8);
1333 } else if (UseAVX > 1) {
1334 // vextracti128 is available only in AVX2
1335 Assembler::vextracti128(dst, src, imm8);
1336 } else {
1337 Assembler::vextractf128(dst, src, imm8);
1338 }
1339 }
1340
1341 // 128bit copy to/from high 128 bits of 256bit (YMM) vector registers
1342 void vinserti128_high(XMMRegister dst, XMMRegister src) {
1343 vinserti128(dst, dst, src, 1);
1344 }
1345 void vinserti128_high(XMMRegister dst, Address src) {
1346 vinserti128(dst, dst, src, 1);
1347 }
1348 void vextracti128_high(XMMRegister dst, XMMRegister src) {
1349 vextracti128(dst, src, 1);
1350 }
1351 void vextracti128_high(Address dst, XMMRegister src) {
1352 vextracti128(dst, src, 1);
1353 }
1354
1355 void vinsertf128_high(XMMRegister dst, XMMRegister src) {
1356 if (UseAVX > 2) {
1357 Assembler::vinsertf32x4(dst, dst, src, 1);
1358 } else {
1359 Assembler::vinsertf128(dst, dst, src, 1);
1360 }
1361 }
1362
1363 void vinsertf128_high(XMMRegister dst, Address src) {
1364 if (UseAVX > 2) {
1365 Assembler::vinsertf32x4(dst, dst, src, 1);
1366 } else {
1367 Assembler::vinsertf128(dst, dst, src, 1);
1368 }
1369 }
1370
1371 void vextractf128_high(XMMRegister dst, XMMRegister src) {
1372 if (UseAVX > 2) {
1373 Assembler::vextractf32x4(dst, src, 1);
1374 } else {
1375 Assembler::vextractf128(dst, src, 1);
1376 }
1377 }
1378
1379 void vextractf128_high(Address dst, XMMRegister src) {
1380 if (UseAVX > 2) {
1381 Assembler::vextractf32x4(dst, src, 1);
1382 } else {
1383 Assembler::vextractf128(dst, src, 1);
1384 }
1385 }
1386
1387 // 256bit copy to/from high 256 bits of 512bit (ZMM) vector registers
1388 void vinserti64x4_high(XMMRegister dst, XMMRegister src) {
1389 Assembler::vinserti64x4(dst, dst, src, 1);
1390 }
1391 void vinsertf64x4_high(XMMRegister dst, XMMRegister src) {
1392 Assembler::vinsertf64x4(dst, dst, src, 1);
1393 }
1394 void vextracti64x4_high(XMMRegister dst, XMMRegister src) {
1395 Assembler::vextracti64x4(dst, src, 1);
1396 }
1397 void vextractf64x4_high(XMMRegister dst, XMMRegister src) {
1398 Assembler::vextractf64x4(dst, src, 1);
1399 }
1400 void vextractf64x4_high(Address dst, XMMRegister src) {
1401 Assembler::vextractf64x4(dst, src, 1);
1402 }
1403 void vinsertf64x4_high(XMMRegister dst, Address src) {
1404 Assembler::vinsertf64x4(dst, dst, src, 1);
1405 }
1406
1407 // 128bit copy to/from low 128 bits of 256bit (YMM) vector registers
1408 void vinserti128_low(XMMRegister dst, XMMRegister src) {
1409 vinserti128(dst, dst, src, 0);
1410 }
1411 void vinserti128_low(XMMRegister dst, Address src) {
1412 vinserti128(dst, dst, src, 0);
1413 }
1414 void vextracti128_low(XMMRegister dst, XMMRegister src) {
1415 vextracti128(dst, src, 0);
1416 }
1417 void vextracti128_low(Address dst, XMMRegister src) {
1418 vextracti128(dst, src, 0);
1419 }
1420
1421 void vinsertf128_low(XMMRegister dst, XMMRegister src) {
1422 if (UseAVX > 2) {
1423 Assembler::vinsertf32x4(dst, dst, src, 0);
1424 } else {
1425 Assembler::vinsertf128(dst, dst, src, 0);
1426 }
1427 }
1428
1429 void vinsertf128_low(XMMRegister dst, Address src) {
1430 if (UseAVX > 2) {
1431 Assembler::vinsertf32x4(dst, dst, src, 0);
1432 } else {
1433 Assembler::vinsertf128(dst, dst, src, 0);
1434 }
1435 }
1436
1437 void vextractf128_low(XMMRegister dst, XMMRegister src) {
1438 if (UseAVX > 2) {
1439 Assembler::vextractf32x4(dst, src, 0);
1440 } else {
1441 Assembler::vextractf128(dst, src, 0);
1442 }
1443 }
1444
1445 void vextractf128_low(Address dst, XMMRegister src) {
1446 if (UseAVX > 2) {
1447 Assembler::vextractf32x4(dst, src, 0);
1448 } else {
1449 Assembler::vextractf128(dst, src, 0);
1450 }
1451 }
1452
1453 // 256bit copy to/from low 256 bits of 512bit (ZMM) vector registers
1454 void vinserti64x4_low(XMMRegister dst, XMMRegister src) {
1455 Assembler::vinserti64x4(dst, dst, src, 0);
1456 }
1457 void vinsertf64x4_low(XMMRegister dst, XMMRegister src) {
1458 Assembler::vinsertf64x4(dst, dst, src, 0);
1459 }
1460 void vextracti64x4_low(XMMRegister dst, XMMRegister src) {
1461 Assembler::vextracti64x4(dst, src, 0);
1462 }
1463 void vextractf64x4_low(XMMRegister dst, XMMRegister src) {
1464 Assembler::vextractf64x4(dst, src, 0);
1465 }
1466 void vextractf64x4_low(Address dst, XMMRegister src) {
1467 Assembler::vextractf64x4(dst, src, 0);
1468 }
1469 void vinsertf64x4_low(XMMRegister dst, Address src) {
1470 Assembler::vinsertf64x4(dst, dst, src, 0);
1471 }
1472
1473 // Carry-Less Multiplication Quadword
1474 void vpclmulldq(XMMRegister dst, XMMRegister nds, XMMRegister src) {
1475 // 0x00 - multiply lower 64 bits [0:63]
1476 Assembler::vpclmulqdq(dst, nds, src, 0x00);
1477 }
1478 void vpclmulhdq(XMMRegister dst, XMMRegister nds, XMMRegister src) {
1479 // 0x11 - multiply upper 64 bits [64:127]
1480 Assembler::vpclmulqdq(dst, nds, src, 0x11);
1481 }
1482
1483 // Data
1484
1485 void cmov32( Condition cc, Register dst, Address src);
1486 void cmov32( Condition cc, Register dst, Register src);
1487
1488 void cmov( Condition cc, Register dst, Register src) { cmovptr(cc, dst, src); }
1489
1490 void cmovptr(Condition cc, Register dst, Address src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmov32(cc, dst, src)); }
1491 void cmovptr(Condition cc, Register dst, Register src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmov32(cc, dst, src)); }
1492
1493 void movoop(Register dst, jobject obj);
1494 void movoop(Address dst, jobject obj);
1495
1496 void mov_metadata(Register dst, Metadata* obj);
1497 void mov_metadata(Address dst, Metadata* obj);
1498
1499 void movptr(ArrayAddress dst, Register src);
1500 // can this do an lea?
1501 void movptr(Register dst, ArrayAddress src);
1502
1503 void movptr(Register dst, Address src);
1504
1505 #ifdef _LP64
1506 void movptr(Register dst, AddressLiteral src, Register scratch=rscratch1);
1507 #else
1508 void movptr(Register dst, AddressLiteral src, Register scratch=noreg); // Scratch reg is ignored in 32-bit
1509 #endif
1510
1511 void movptr(Register dst, intptr_t src);
1512 void movptr(Register dst, Register src);
1513 void movptr(Address dst, intptr_t src);
1514
1515 void movptr(Address dst, Register src);
1516
1517 void movptr(Register dst, RegisterOrConstant src) {
1518 if (src.is_constant()) movptr(dst, src.as_constant());
1519 else movptr(dst, src.as_register());
1520 }
1521
1522 #ifdef _LP64
1523 // Generally the next two are only used for moving NULL
1524 // Although there are situations in initializing the mark word where
1525 // they could be used. They are dangerous.
1526
1527 // They only exist on LP64 so that int32_t and intptr_t are not the same
1528 // and we have ambiguous declarations.
1529
1530 void movptr(Address dst, int32_t imm32);
1531 void movptr(Register dst, int32_t imm32);
1532 #endif // _LP64
1533
1534 // to avoid hiding movl
1535 void mov32(AddressLiteral dst, Register src);
1536 void mov32(Register dst, AddressLiteral src);
1537
1538 // to avoid hiding movb
1539 void movbyte(ArrayAddress dst, int src);
1540
1541 // Import other mov() methods from the parent class or else
1542 // they will be hidden by the following overriding declaration.
1543 using Assembler::movdl;
1544 using Assembler::movq;
1545 void movdl(XMMRegister dst, AddressLiteral src);
1546 void movq(XMMRegister dst, AddressLiteral src);
1547
1548 // Can push value or effective address
1549 void pushptr(AddressLiteral src);
1550
1551 void pushptr(Address src) { LP64_ONLY(pushq(src)) NOT_LP64(pushl(src)); }
1552 void popptr(Address src) { LP64_ONLY(popq(src)) NOT_LP64(popl(src)); }
1553
1554 void pushoop(jobject obj);
1555 void pushklass(Metadata* obj);
1556
1557 // sign extend as need a l to ptr sized element
1558 void movl2ptr(Register dst, Address src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(movl(dst, src)); }
1559 void movl2ptr(Register dst, Register src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(if (dst != src) movl(dst, src)); }
1560
1561 // C2 compiled method's prolog code.
1562 void verified_entry(int framesize, int stack_bang_size, bool fp_mode_24b);
1563
1564 // clear memory of size 'cnt' qwords, starting at 'base';
1565 // if 'is_large' is set, do not try to produce short loop
1566 void clear_mem(Register base, Register cnt, Register rtmp, bool is_large);
1567
1568 #ifdef COMPILER2
1569 void string_indexof_char(Register str1, Register cnt1, Register ch, Register result,
1570 XMMRegister vec1, XMMRegister vec2, XMMRegister vec3, Register tmp);
1571
1572 // IndexOf strings.
1573 // Small strings are loaded through stack if they cross page boundary.
1574 void string_indexof(Register str1, Register str2,
1575 Register cnt1, Register cnt2,
1576 int int_cnt2, Register result,
1577 XMMRegister vec, Register tmp,
1578 int ae);
1579
1580 // IndexOf for constant substrings with size >= 8 elements
1581 // which don't need to be loaded through stack.
1582 void string_indexofC8(Register str1, Register str2,
1583 Register cnt1, Register cnt2,
1584 int int_cnt2, Register result,
1585 XMMRegister vec, Register tmp,
1586 int ae);
1587
1588 // Smallest code: we don't need to load through stack,
1589 // check string tail.
1590
1591 // helper function for string_compare
1592 void load_next_elements(Register elem1, Register elem2, Register str1, Register str2,
1593 Address::ScaleFactor scale, Address::ScaleFactor scale1,
1594 Address::ScaleFactor scale2, Register index, int ae);
1595 // Compare strings.
1596 void string_compare(Register str1, Register str2,
1597 Register cnt1, Register cnt2, Register result,
1598 XMMRegister vec1, int ae);
1599
1600 // Search for Non-ASCII character (Negative byte value) in a byte array,
1601 // return true if it has any and false otherwise.
1602 void has_negatives(Register ary1, Register len,
1603 Register result, Register tmp1,
1604 XMMRegister vec1, XMMRegister vec2);
1605
1606 // Compare char[] or byte[] arrays.
1607 void arrays_equals(bool is_array_equ, Register ary1, Register ary2,
1608 Register limit, Register result, Register chr,
1609 XMMRegister vec1, XMMRegister vec2, bool is_char);
1610
1611 #endif
1612
1613 // Fill primitive arrays
1614 void generate_fill(BasicType t, bool aligned,
1615 Register to, Register value, Register count,
1616 Register rtmp, XMMRegister xtmp);
1617
1618 void encode_iso_array(Register src, Register dst, Register len,
1619 XMMRegister tmp1, XMMRegister tmp2, XMMRegister tmp3,
1620 XMMRegister tmp4, Register tmp5, Register result);
1621
1622 #ifdef _LP64
1623 void add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2);
1624 void multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
1625 Register y, Register y_idx, Register z,
1626 Register carry, Register product,
1627 Register idx, Register kdx);
1628 void multiply_add_128_x_128(Register x_xstart, Register y, Register z,
1629 Register yz_idx, Register idx,
1630 Register carry, Register product, int offset);
1631 void multiply_128_x_128_bmi2_loop(Register y, Register z,
1632 Register carry, Register carry2,
1633 Register idx, Register jdx,
1634 Register yz_idx1, Register yz_idx2,
1635 Register tmp, Register tmp3, Register tmp4);
1636 void multiply_128_x_128_loop(Register x_xstart, Register y, Register z,
1637 Register yz_idx, Register idx, Register jdx,
1638 Register carry, Register product,
1639 Register carry2);
1640 void multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z, Register zlen,
1641 Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5);
1642 void square_rshift(Register x, Register len, Register z, Register tmp1, Register tmp3,
1643 Register tmp4, Register tmp5, Register rdxReg, Register raxReg);
1644 void multiply_add_64_bmi2(Register sum, Register op1, Register op2, Register carry,
1645 Register tmp2);
1646 void multiply_add_64(Register sum, Register op1, Register op2, Register carry,
1647 Register rdxReg, Register raxReg);
1648 void add_one_64(Register z, Register zlen, Register carry, Register tmp1);
1649 void lshift_by_1(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2,
1650 Register tmp3, Register tmp4);
1651 void square_to_len(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2,
1652 Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg);
1653
1654 void mul_add_128_x_32_loop(Register out, Register in, Register offset, Register len, Register tmp1,
1655 Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg,
1656 Register raxReg);
1657 void mul_add(Register out, Register in, Register offset, Register len, Register k, Register tmp1,
1658 Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg,
1659 Register raxReg);
1660 void vectorized_mismatch(Register obja, Register objb, Register length, Register log2_array_indxscale,
1661 Register result, Register tmp1, Register tmp2,
1662 XMMRegister vec1, XMMRegister vec2, XMMRegister vec3);
1663 #endif
1664
1665 // CRC32 code for java.util.zip.CRC32::updateBytes() intrinsic.
1666 void update_byte_crc32(Register crc, Register val, Register table);
1667 void kernel_crc32(Register crc, Register buf, Register len, Register table, Register tmp);
1668 // CRC32C code for java.util.zip.CRC32C::updateBytes() intrinsic
1669 // Note on a naming convention:
1670 // Prefix w = register only used on a Westmere+ architecture
1671 // Prefix n = register only used on a Nehalem architecture
1672 #ifdef _LP64
1673 void crc32c_ipl_alg4(Register in_out, uint32_t n,
1674 Register tmp1, Register tmp2, Register tmp3);
1675 #else
1676 void crc32c_ipl_alg4(Register in_out, uint32_t n,
1677 Register tmp1, Register tmp2, Register tmp3,
1678 XMMRegister xtmp1, XMMRegister xtmp2);
1679 #endif
1680 void crc32c_pclmulqdq(XMMRegister w_xtmp1,
1681 Register in_out,
1682 uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported,
1683 XMMRegister w_xtmp2,
1684 Register tmp1,
1685 Register n_tmp2, Register n_tmp3);
1686 void crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2,
1687 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
1688 Register tmp1, Register tmp2,
1689 Register n_tmp3);
1690 void crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported,
1691 Register in_out1, Register in_out2, Register in_out3,
1692 Register tmp1, Register tmp2, Register tmp3,
1693 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
1694 Register tmp4, Register tmp5,
1695 Register n_tmp6);
1696 void crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2,
1697 Register tmp1, Register tmp2, Register tmp3,
1698 Register tmp4, Register tmp5, Register tmp6,
1699 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
1700 bool is_pclmulqdq_supported);
1701 // Fold 128-bit data chunk
1702 void fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset);
1703 void fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, XMMRegister xbuf);
1704 // Fold 8-bit data
1705 void fold_8bit_crc32(Register crc, Register table, Register tmp);
1706 void fold_8bit_crc32(XMMRegister crc, Register table, XMMRegister xtmp, Register tmp);
1707
1708 // Compress char[] array to byte[].
1709 void char_array_compress(Register src, Register dst, Register len,
1710 XMMRegister tmp1, XMMRegister tmp2, XMMRegister tmp3,
1711 XMMRegister tmp4, Register tmp5, Register result);
1712
1713 // Inflate byte[] array to char[].
1714 void byte_array_inflate(Register src, Register dst, Register len,
1715 XMMRegister tmp1, Register tmp2);
1716
1717 };
1718
1719 /**
1720 * class SkipIfEqual:
1721 *
1722 * Instantiating this class will result in assembly code being output that will
1723 * jump around any code emitted between the creation of the instance and it's
1724 * automatic destruction at the end of a scope block, depending on the value of
1725 * the flag passed to the constructor, which will be checked at run-time.
1726 */
1727 class SkipIfEqual {
1728 private:
1729 MacroAssembler* _masm;
1730 Label _label;
1731
1732 public:
1733 SkipIfEqual(MacroAssembler*, const bool* flag_addr, bool value);
1734 ~SkipIfEqual();
1735 };
1736
1737 #endif // CPU_X86_VM_MACROASSEMBLER_X86_HPP