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src/cpu/x86/vm/x86.ad

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rev 12700 : 8176506: C2: loop unswitching and unsafe accesses cause crash
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1789     not_equal    (0xC, "ne");
1790     greater_equal(0xD, "ge");
1791     greater      (0xE, "gt");
1792     //TODO cannot compile (adlc breaks) without two next lines with error:
1793     // x86_64.ad(13987) Syntax Error: :In operand cmpOp_vcmppd: Do not support this encode constant: ' %{
1794     // equal' for overflow.
1795     overflow     (0x20, "o");  // not really supported by the instruction
1796     no_overflow  (0x21, "no"); // not really supported by the instruction
1797   %}
1798 %}
1799 
1800 
1801 // INSTRUCTIONS -- Platform independent definitions (same for 32- and 64-bit)
1802 
1803 // ============================================================================
1804 
1805 instruct ShouldNotReachHere() %{
1806   match(Halt);
1807   format %{ "int3\t# ShouldNotReachHere" %}
1808   ins_encode %{
1809     __ int3();
1810   %}
1811   ins_pipe(pipe_slow);
1812 %}
1813 
1814 // =================================EVEX special===============================
1815 
1816 instruct setMask(rRegI dst, rRegI src) %{
1817   predicate(Matcher::has_predicated_vectors());
1818   match(Set dst (SetVectMaskI  src));
1819   effect(TEMP dst);
1820   format %{ "setvectmask   $dst, $src" %}
1821   ins_encode %{
1822     __ setvectmask($dst$$Register, $src$$Register);
1823   %}
1824   ins_pipe(pipe_slow);
1825 %}
1826 
1827 // ============================================================================
1828 
1829 instruct addF_reg(regF dst, regF src) %{




1789     not_equal    (0xC, "ne");
1790     greater_equal(0xD, "ge");
1791     greater      (0xE, "gt");
1792     //TODO cannot compile (adlc breaks) without two next lines with error:
1793     // x86_64.ad(13987) Syntax Error: :In operand cmpOp_vcmppd: Do not support this encode constant: ' %{
1794     // equal' for overflow.
1795     overflow     (0x20, "o");  // not really supported by the instruction
1796     no_overflow  (0x21, "no"); // not really supported by the instruction
1797   %}
1798 %}
1799 
1800 
1801 // INSTRUCTIONS -- Platform independent definitions (same for 32- and 64-bit)
1802 
1803 // ============================================================================
1804 
1805 instruct ShouldNotReachHere() %{
1806   match(Halt);
1807   format %{ "int3\t# ShouldNotReachHere" %}
1808   ins_encode %{
1809     __ halt();
1810   %}
1811   ins_pipe(pipe_slow);
1812 %}
1813 
1814 // =================================EVEX special===============================
1815 
1816 instruct setMask(rRegI dst, rRegI src) %{
1817   predicate(Matcher::has_predicated_vectors());
1818   match(Set dst (SetVectMaskI  src));
1819   effect(TEMP dst);
1820   format %{ "setvectmask   $dst, $src" %}
1821   ins_encode %{
1822     __ setvectmask($dst$$Register, $src$$Register);
1823   %}
1824   ins_pipe(pipe_slow);
1825 %}
1826 
1827 // ============================================================================
1828 
1829 instruct addF_reg(regF dst, regF src) %{


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