1 //
2 // Copyright (c) 1998, 2011, Oracle and/or its affiliates. All rights reserved.
3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 //
5 // This code is free software; you can redistribute it and/or modify it
6 // under the terms of the GNU General Public License version 2 only, as
7 // published by the Free Software Foundation.
8 //
9 // This code is distributed in the hope that it will be useful, but WITHOUT
10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 // version 2 for more details (a copy is included in the LICENSE file that
13 // accompanied this code).
14 //
15 // You should have received a copy of the GNU General Public License version
16 // 2 along with this work; if not, write to the Free Software Foundation,
17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 //
19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 // or visit www.oracle.com if you need additional information or have any
21 // questions.
22 //
23 //
24
25 // SPARC Architecture Description File
26
27 //----------REGISTER DEFINITION BLOCK------------------------------------------
28 // This information is used by the matcher and the register allocator to
29 // describe individual registers and classes of registers within the target
30 // archtecture.
31 register %{
32 //----------Architecture Description Register Definitions----------------------
33 // General Registers
34 // "reg_def" name ( register save type, C convention save type,
35 // ideal register type, encoding, vm name );
36 // Register Save Types:
37 //
38 // NS = No-Save: The register allocator assumes that these registers
39 // can be used without saving upon entry to the method, &
40 // that they do not need to be saved at call sites.
41 //
42 // SOC = Save-On-Call: The register allocator assumes that these registers
43 // can be used without saving upon entry to the method,
44 // but that they must be saved at call sites.
45 //
46 // SOE = Save-On-Entry: The register allocator assumes that these registers
47 // must be saved before using them upon entry to the
48 // method, but they do not need to be saved at call
49 // sites.
50 //
51 // AS = Always-Save: The register allocator assumes that these registers
52 // must be saved before using them upon entry to the
53 // method, & that they must be saved at call sites.
54 //
55 // Ideal Register Type is used to determine how to save & restore a
56 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
57 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
58 //
59 // The encoding number is the actual bit-pattern placed into the opcodes.
60
61
62 // ----------------------------
63 // Integer/Long Registers
64 // ----------------------------
65
66 // Need to expose the hi/lo aspect of 64-bit registers
67 // This register set is used for both the 64-bit build and
68 // the 32-bit build with 1-register longs.
69
70 // Global Registers 0-7
71 reg_def R_G0H( NS, NS, Op_RegI,128, G0->as_VMReg()->next());
72 reg_def R_G0 ( NS, NS, Op_RegI, 0, G0->as_VMReg());
73 reg_def R_G1H(SOC, SOC, Op_RegI,129, G1->as_VMReg()->next());
74 reg_def R_G1 (SOC, SOC, Op_RegI, 1, G1->as_VMReg());
75 reg_def R_G2H( NS, NS, Op_RegI,130, G2->as_VMReg()->next());
76 reg_def R_G2 ( NS, NS, Op_RegI, 2, G2->as_VMReg());
77 reg_def R_G3H(SOC, SOC, Op_RegI,131, G3->as_VMReg()->next());
78 reg_def R_G3 (SOC, SOC, Op_RegI, 3, G3->as_VMReg());
79 reg_def R_G4H(SOC, SOC, Op_RegI,132, G4->as_VMReg()->next());
80 reg_def R_G4 (SOC, SOC, Op_RegI, 4, G4->as_VMReg());
81 reg_def R_G5H(SOC, SOC, Op_RegI,133, G5->as_VMReg()->next());
82 reg_def R_G5 (SOC, SOC, Op_RegI, 5, G5->as_VMReg());
83 reg_def R_G6H( NS, NS, Op_RegI,134, G6->as_VMReg()->next());
84 reg_def R_G6 ( NS, NS, Op_RegI, 6, G6->as_VMReg());
85 reg_def R_G7H( NS, NS, Op_RegI,135, G7->as_VMReg()->next());
86 reg_def R_G7 ( NS, NS, Op_RegI, 7, G7->as_VMReg());
87
88 // Output Registers 0-7
89 reg_def R_O0H(SOC, SOC, Op_RegI,136, O0->as_VMReg()->next());
90 reg_def R_O0 (SOC, SOC, Op_RegI, 8, O0->as_VMReg());
91 reg_def R_O1H(SOC, SOC, Op_RegI,137, O1->as_VMReg()->next());
92 reg_def R_O1 (SOC, SOC, Op_RegI, 9, O1->as_VMReg());
93 reg_def R_O2H(SOC, SOC, Op_RegI,138, O2->as_VMReg()->next());
94 reg_def R_O2 (SOC, SOC, Op_RegI, 10, O2->as_VMReg());
95 reg_def R_O3H(SOC, SOC, Op_RegI,139, O3->as_VMReg()->next());
96 reg_def R_O3 (SOC, SOC, Op_RegI, 11, O3->as_VMReg());
97 reg_def R_O4H(SOC, SOC, Op_RegI,140, O4->as_VMReg()->next());
98 reg_def R_O4 (SOC, SOC, Op_RegI, 12, O4->as_VMReg());
99 reg_def R_O5H(SOC, SOC, Op_RegI,141, O5->as_VMReg()->next());
100 reg_def R_O5 (SOC, SOC, Op_RegI, 13, O5->as_VMReg());
101 reg_def R_SPH( NS, NS, Op_RegI,142, SP->as_VMReg()->next());
102 reg_def R_SP ( NS, NS, Op_RegI, 14, SP->as_VMReg());
103 reg_def R_O7H(SOC, SOC, Op_RegI,143, O7->as_VMReg()->next());
104 reg_def R_O7 (SOC, SOC, Op_RegI, 15, O7->as_VMReg());
105
106 // Local Registers 0-7
107 reg_def R_L0H( NS, NS, Op_RegI,144, L0->as_VMReg()->next());
108 reg_def R_L0 ( NS, NS, Op_RegI, 16, L0->as_VMReg());
109 reg_def R_L1H( NS, NS, Op_RegI,145, L1->as_VMReg()->next());
110 reg_def R_L1 ( NS, NS, Op_RegI, 17, L1->as_VMReg());
111 reg_def R_L2H( NS, NS, Op_RegI,146, L2->as_VMReg()->next());
112 reg_def R_L2 ( NS, NS, Op_RegI, 18, L2->as_VMReg());
113 reg_def R_L3H( NS, NS, Op_RegI,147, L3->as_VMReg()->next());
114 reg_def R_L3 ( NS, NS, Op_RegI, 19, L3->as_VMReg());
115 reg_def R_L4H( NS, NS, Op_RegI,148, L4->as_VMReg()->next());
116 reg_def R_L4 ( NS, NS, Op_RegI, 20, L4->as_VMReg());
117 reg_def R_L5H( NS, NS, Op_RegI,149, L5->as_VMReg()->next());
118 reg_def R_L5 ( NS, NS, Op_RegI, 21, L5->as_VMReg());
119 reg_def R_L6H( NS, NS, Op_RegI,150, L6->as_VMReg()->next());
120 reg_def R_L6 ( NS, NS, Op_RegI, 22, L6->as_VMReg());
121 reg_def R_L7H( NS, NS, Op_RegI,151, L7->as_VMReg()->next());
122 reg_def R_L7 ( NS, NS, Op_RegI, 23, L7->as_VMReg());
123
124 // Input Registers 0-7
125 reg_def R_I0H( NS, NS, Op_RegI,152, I0->as_VMReg()->next());
126 reg_def R_I0 ( NS, NS, Op_RegI, 24, I0->as_VMReg());
127 reg_def R_I1H( NS, NS, Op_RegI,153, I1->as_VMReg()->next());
128 reg_def R_I1 ( NS, NS, Op_RegI, 25, I1->as_VMReg());
129 reg_def R_I2H( NS, NS, Op_RegI,154, I2->as_VMReg()->next());
130 reg_def R_I2 ( NS, NS, Op_RegI, 26, I2->as_VMReg());
131 reg_def R_I3H( NS, NS, Op_RegI,155, I3->as_VMReg()->next());
132 reg_def R_I3 ( NS, NS, Op_RegI, 27, I3->as_VMReg());
133 reg_def R_I4H( NS, NS, Op_RegI,156, I4->as_VMReg()->next());
134 reg_def R_I4 ( NS, NS, Op_RegI, 28, I4->as_VMReg());
135 reg_def R_I5H( NS, NS, Op_RegI,157, I5->as_VMReg()->next());
136 reg_def R_I5 ( NS, NS, Op_RegI, 29, I5->as_VMReg());
137 reg_def R_FPH( NS, NS, Op_RegI,158, FP->as_VMReg()->next());
138 reg_def R_FP ( NS, NS, Op_RegI, 30, FP->as_VMReg());
139 reg_def R_I7H( NS, NS, Op_RegI,159, I7->as_VMReg()->next());
140 reg_def R_I7 ( NS, NS, Op_RegI, 31, I7->as_VMReg());
141
142 // ----------------------------
143 // Float/Double Registers
144 // ----------------------------
145
146 // Float Registers
147 reg_def R_F0 ( SOC, SOC, Op_RegF, 0, F0->as_VMReg());
148 reg_def R_F1 ( SOC, SOC, Op_RegF, 1, F1->as_VMReg());
149 reg_def R_F2 ( SOC, SOC, Op_RegF, 2, F2->as_VMReg());
150 reg_def R_F3 ( SOC, SOC, Op_RegF, 3, F3->as_VMReg());
151 reg_def R_F4 ( SOC, SOC, Op_RegF, 4, F4->as_VMReg());
152 reg_def R_F5 ( SOC, SOC, Op_RegF, 5, F5->as_VMReg());
153 reg_def R_F6 ( SOC, SOC, Op_RegF, 6, F6->as_VMReg());
154 reg_def R_F7 ( SOC, SOC, Op_RegF, 7, F7->as_VMReg());
155 reg_def R_F8 ( SOC, SOC, Op_RegF, 8, F8->as_VMReg());
156 reg_def R_F9 ( SOC, SOC, Op_RegF, 9, F9->as_VMReg());
157 reg_def R_F10( SOC, SOC, Op_RegF, 10, F10->as_VMReg());
158 reg_def R_F11( SOC, SOC, Op_RegF, 11, F11->as_VMReg());
159 reg_def R_F12( SOC, SOC, Op_RegF, 12, F12->as_VMReg());
160 reg_def R_F13( SOC, SOC, Op_RegF, 13, F13->as_VMReg());
161 reg_def R_F14( SOC, SOC, Op_RegF, 14, F14->as_VMReg());
162 reg_def R_F15( SOC, SOC, Op_RegF, 15, F15->as_VMReg());
163 reg_def R_F16( SOC, SOC, Op_RegF, 16, F16->as_VMReg());
164 reg_def R_F17( SOC, SOC, Op_RegF, 17, F17->as_VMReg());
165 reg_def R_F18( SOC, SOC, Op_RegF, 18, F18->as_VMReg());
166 reg_def R_F19( SOC, SOC, Op_RegF, 19, F19->as_VMReg());
167 reg_def R_F20( SOC, SOC, Op_RegF, 20, F20->as_VMReg());
168 reg_def R_F21( SOC, SOC, Op_RegF, 21, F21->as_VMReg());
169 reg_def R_F22( SOC, SOC, Op_RegF, 22, F22->as_VMReg());
170 reg_def R_F23( SOC, SOC, Op_RegF, 23, F23->as_VMReg());
171 reg_def R_F24( SOC, SOC, Op_RegF, 24, F24->as_VMReg());
172 reg_def R_F25( SOC, SOC, Op_RegF, 25, F25->as_VMReg());
173 reg_def R_F26( SOC, SOC, Op_RegF, 26, F26->as_VMReg());
174 reg_def R_F27( SOC, SOC, Op_RegF, 27, F27->as_VMReg());
175 reg_def R_F28( SOC, SOC, Op_RegF, 28, F28->as_VMReg());
176 reg_def R_F29( SOC, SOC, Op_RegF, 29, F29->as_VMReg());
177 reg_def R_F30( SOC, SOC, Op_RegF, 30, F30->as_VMReg());
178 reg_def R_F31( SOC, SOC, Op_RegF, 31, F31->as_VMReg());
179
180 // Double Registers
181 // The rules of ADL require that double registers be defined in pairs.
182 // Each pair must be two 32-bit values, but not necessarily a pair of
183 // single float registers. In each pair, ADLC-assigned register numbers
184 // must be adjacent, with the lower number even. Finally, when the
185 // CPU stores such a register pair to memory, the word associated with
186 // the lower ADLC-assigned number must be stored to the lower address.
187
188 // These definitions specify the actual bit encodings of the sparc
189 // double fp register numbers. FloatRegisterImpl in register_sparc.hpp
190 // wants 0-63, so we have to convert every time we want to use fp regs
191 // with the macroassembler, using reg_to_DoubleFloatRegister_object().
192 // 255 is a flag meaning "don't go here".
193 // I believe we can't handle callee-save doubles D32 and up until
194 // the place in the sparc stack crawler that asserts on the 255 is
195 // fixed up.
196 reg_def R_D32 (SOC, SOC, Op_RegD, 1, F32->as_VMReg());
197 reg_def R_D32x(SOC, SOC, Op_RegD,255, F32->as_VMReg()->next());
198 reg_def R_D34 (SOC, SOC, Op_RegD, 3, F34->as_VMReg());
199 reg_def R_D34x(SOC, SOC, Op_RegD,255, F34->as_VMReg()->next());
200 reg_def R_D36 (SOC, SOC, Op_RegD, 5, F36->as_VMReg());
201 reg_def R_D36x(SOC, SOC, Op_RegD,255, F36->as_VMReg()->next());
202 reg_def R_D38 (SOC, SOC, Op_RegD, 7, F38->as_VMReg());
203 reg_def R_D38x(SOC, SOC, Op_RegD,255, F38->as_VMReg()->next());
204 reg_def R_D40 (SOC, SOC, Op_RegD, 9, F40->as_VMReg());
205 reg_def R_D40x(SOC, SOC, Op_RegD,255, F40->as_VMReg()->next());
206 reg_def R_D42 (SOC, SOC, Op_RegD, 11, F42->as_VMReg());
207 reg_def R_D42x(SOC, SOC, Op_RegD,255, F42->as_VMReg()->next());
208 reg_def R_D44 (SOC, SOC, Op_RegD, 13, F44->as_VMReg());
209 reg_def R_D44x(SOC, SOC, Op_RegD,255, F44->as_VMReg()->next());
210 reg_def R_D46 (SOC, SOC, Op_RegD, 15, F46->as_VMReg());
211 reg_def R_D46x(SOC, SOC, Op_RegD,255, F46->as_VMReg()->next());
212 reg_def R_D48 (SOC, SOC, Op_RegD, 17, F48->as_VMReg());
213 reg_def R_D48x(SOC, SOC, Op_RegD,255, F48->as_VMReg()->next());
214 reg_def R_D50 (SOC, SOC, Op_RegD, 19, F50->as_VMReg());
215 reg_def R_D50x(SOC, SOC, Op_RegD,255, F50->as_VMReg()->next());
216 reg_def R_D52 (SOC, SOC, Op_RegD, 21, F52->as_VMReg());
217 reg_def R_D52x(SOC, SOC, Op_RegD,255, F52->as_VMReg()->next());
218 reg_def R_D54 (SOC, SOC, Op_RegD, 23, F54->as_VMReg());
219 reg_def R_D54x(SOC, SOC, Op_RegD,255, F54->as_VMReg()->next());
220 reg_def R_D56 (SOC, SOC, Op_RegD, 25, F56->as_VMReg());
221 reg_def R_D56x(SOC, SOC, Op_RegD,255, F56->as_VMReg()->next());
222 reg_def R_D58 (SOC, SOC, Op_RegD, 27, F58->as_VMReg());
223 reg_def R_D58x(SOC, SOC, Op_RegD,255, F58->as_VMReg()->next());
224 reg_def R_D60 (SOC, SOC, Op_RegD, 29, F60->as_VMReg());
225 reg_def R_D60x(SOC, SOC, Op_RegD,255, F60->as_VMReg()->next());
226 reg_def R_D62 (SOC, SOC, Op_RegD, 31, F62->as_VMReg());
227 reg_def R_D62x(SOC, SOC, Op_RegD,255, F62->as_VMReg()->next());
228
229
230 // ----------------------------
231 // Special Registers
232 // Condition Codes Flag Registers
233 // I tried to break out ICC and XCC but it's not very pretty.
234 // Every Sparc instruction which defs/kills one also kills the other.
235 // Hence every compare instruction which defs one kind of flags ends
236 // up needing a kill of the other.
237 reg_def CCR (SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad());
238
239 reg_def FCC0(SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad());
240 reg_def FCC1(SOC, SOC, Op_RegFlags, 1, VMRegImpl::Bad());
241 reg_def FCC2(SOC, SOC, Op_RegFlags, 2, VMRegImpl::Bad());
242 reg_def FCC3(SOC, SOC, Op_RegFlags, 3, VMRegImpl::Bad());
243
244 // ----------------------------
245 // Specify the enum values for the registers. These enums are only used by the
246 // OptoReg "class". We can convert these enum values at will to VMReg when needed
247 // for visibility to the rest of the vm. The order of this enum influences the
248 // register allocator so having the freedom to set this order and not be stuck
249 // with the order that is natural for the rest of the vm is worth it.
250 alloc_class chunk0(
251 R_L0,R_L0H, R_L1,R_L1H, R_L2,R_L2H, R_L3,R_L3H, R_L4,R_L4H, R_L5,R_L5H, R_L6,R_L6H, R_L7,R_L7H,
252 R_G0,R_G0H, R_G1,R_G1H, R_G2,R_G2H, R_G3,R_G3H, R_G4,R_G4H, R_G5,R_G5H, R_G6,R_G6H, R_G7,R_G7H,
253 R_O7,R_O7H, R_SP,R_SPH, R_O0,R_O0H, R_O1,R_O1H, R_O2,R_O2H, R_O3,R_O3H, R_O4,R_O4H, R_O5,R_O5H,
254 R_I0,R_I0H, R_I1,R_I1H, R_I2,R_I2H, R_I3,R_I3H, R_I4,R_I4H, R_I5,R_I5H, R_FP,R_FPH, R_I7,R_I7H);
255
256 // Note that a register is not allocatable unless it is also mentioned
257 // in a widely-used reg_class below. Thus, R_G7 and R_G0 are outside i_reg.
258
259 alloc_class chunk1(
260 // The first registers listed here are those most likely to be used
261 // as temporaries. We move F0..F7 away from the front of the list,
262 // to reduce the likelihood of interferences with parameters and
263 // return values. Likewise, we avoid using F0/F1 for parameters,
264 // since they are used for return values.
265 // This FPU fine-tuning is worth about 1% on the SPEC geomean.
266 R_F8 ,R_F9 ,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
267 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,
268 R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,R_F30,R_F31,
269 R_F0 ,R_F1 ,R_F2 ,R_F3 ,R_F4 ,R_F5 ,R_F6 ,R_F7 , // used for arguments and return values
270 R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x,
271 R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x,
272 R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x,
273 R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x);
274
275 alloc_class chunk2(CCR, FCC0, FCC1, FCC2, FCC3);
276
277 //----------Architecture Description Register Classes--------------------------
278 // Several register classes are automatically defined based upon information in
279 // this architecture description.
280 // 1) reg_class inline_cache_reg ( as defined in frame section )
281 // 2) reg_class interpreter_method_oop_reg ( as defined in frame section )
282 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
283 //
284
285 // G0 is not included in integer class since it has special meaning.
286 reg_class g0_reg(R_G0);
287
288 // ----------------------------
289 // Integer Register Classes
290 // ----------------------------
291 // Exclusions from i_reg:
292 // R_G0: hardwired zero
293 // R_G2: reserved by HotSpot to the TLS register (invariant within Java)
294 // R_G6: reserved by Solaris ABI to tools
295 // R_G7: reserved by Solaris ABI to libthread
296 // R_O7: Used as a temp in many encodings
297 reg_class int_reg(R_G1,R_G3,R_G4,R_G5,R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
298
299 // Class for all integer registers, except the G registers. This is used for
300 // encodings which use G registers as temps. The regular inputs to such
301 // instructions use a "notemp_" prefix, as a hack to ensure that the allocator
302 // will not put an input into a temp register.
303 reg_class notemp_int_reg(R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
304
305 reg_class g1_regI(R_G1);
306 reg_class g3_regI(R_G3);
307 reg_class g4_regI(R_G4);
308 reg_class o0_regI(R_O0);
309 reg_class o7_regI(R_O7);
310
311 // ----------------------------
312 // Pointer Register Classes
313 // ----------------------------
314 #ifdef _LP64
315 // 64-bit build means 64-bit pointers means hi/lo pairs
316 reg_class ptr_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5,
317 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5,
318 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
319 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 );
320 // Lock encodings use G3 and G4 internally
321 reg_class lock_ptr_reg( R_G1H,R_G1, R_G5H,R_G5,
322 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5,
323 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
324 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 );
325 // Special class for storeP instructions, which can store SP or RPC to TLS.
326 // It is also used for memory addressing, allowing direct TLS addressing.
327 reg_class sp_ptr_reg( R_G1H,R_G1, R_G2H,R_G2, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5,
328 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, R_SPH,R_SP,
329 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
330 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5, R_FPH,R_FP );
331 // R_L7 is the lowest-priority callee-save (i.e., NS) register
332 // We use it to save R_G2 across calls out of Java.
333 reg_class l7_regP(R_L7H,R_L7);
334
335 // Other special pointer regs
336 reg_class g1_regP(R_G1H,R_G1);
337 reg_class g2_regP(R_G2H,R_G2);
338 reg_class g3_regP(R_G3H,R_G3);
339 reg_class g4_regP(R_G4H,R_G4);
340 reg_class g5_regP(R_G5H,R_G5);
341 reg_class i0_regP(R_I0H,R_I0);
342 reg_class o0_regP(R_O0H,R_O0);
343 reg_class o1_regP(R_O1H,R_O1);
344 reg_class o2_regP(R_O2H,R_O2);
345 reg_class o7_regP(R_O7H,R_O7);
346
347 #else // _LP64
348 // 32-bit build means 32-bit pointers means 1 register.
349 reg_class ptr_reg( R_G1, R_G3,R_G4,R_G5,
350 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,
351 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,
352 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
353 // Lock encodings use G3 and G4 internally
354 reg_class lock_ptr_reg(R_G1, R_G5,
355 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,
356 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,
357 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
358 // Special class for storeP instructions, which can store SP or RPC to TLS.
359 // It is also used for memory addressing, allowing direct TLS addressing.
360 reg_class sp_ptr_reg( R_G1,R_G2,R_G3,R_G4,R_G5,
361 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_SP,
362 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,
363 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5,R_FP);
364 // R_L7 is the lowest-priority callee-save (i.e., NS) register
365 // We use it to save R_G2 across calls out of Java.
366 reg_class l7_regP(R_L7);
367
368 // Other special pointer regs
369 reg_class g1_regP(R_G1);
370 reg_class g2_regP(R_G2);
371 reg_class g3_regP(R_G3);
372 reg_class g4_regP(R_G4);
373 reg_class g5_regP(R_G5);
374 reg_class i0_regP(R_I0);
375 reg_class o0_regP(R_O0);
376 reg_class o1_regP(R_O1);
377 reg_class o2_regP(R_O2);
378 reg_class o7_regP(R_O7);
379 #endif // _LP64
380
381
382 // ----------------------------
383 // Long Register Classes
384 // ----------------------------
385 // Longs in 1 register. Aligned adjacent hi/lo pairs.
386 // Note: O7 is never in this class; it is sometimes used as an encoding temp.
387 reg_class long_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5
388 ,R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5
389 #ifdef _LP64
390 // 64-bit, longs in 1 register: use all 64-bit integer registers
391 // 32-bit, longs in 1 register: cannot use I's and L's. Restrict to O's and G's.
392 ,R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7
393 ,R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5
394 #endif // _LP64
395 );
396
397 reg_class g1_regL(R_G1H,R_G1);
398 reg_class g3_regL(R_G3H,R_G3);
399 reg_class o2_regL(R_O2H,R_O2);
400 reg_class o7_regL(R_O7H,R_O7);
401
402 // ----------------------------
403 // Special Class for Condition Code Flags Register
404 reg_class int_flags(CCR);
405 reg_class float_flags(FCC0,FCC1,FCC2,FCC3);
406 reg_class float_flag0(FCC0);
407
408
409 // ----------------------------
410 // Float Point Register Classes
411 // ----------------------------
412 // Skip F30/F31, they are reserved for mem-mem copies
413 reg_class sflt_reg(R_F0,R_F1,R_F2,R_F3,R_F4,R_F5,R_F6,R_F7,R_F8,R_F9,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29);
414
415 // Paired floating point registers--they show up in the same order as the floats,
416 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs.
417 reg_class dflt_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
418 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,
419 /* Use extra V9 double registers; this AD file does not support V8 */
420 R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x,R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x,
421 R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x,R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x
422 );
423
424 // Paired floating point registers--they show up in the same order as the floats,
425 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs.
426 // This class is usable for mis-aligned loads as happen in I2C adapters.
427 reg_class dflt_low_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
428 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,R_F30,R_F31 );
429 %}
430
431 //----------DEFINITION BLOCK---------------------------------------------------
432 // Define name --> value mappings to inform the ADLC of an integer valued name
433 // Current support includes integer values in the range [0, 0x7FFFFFFF]
434 // Format:
435 // int_def <name> ( <int_value>, <expression>);
436 // Generated Code in ad_<arch>.hpp
437 // #define <name> (<expression>)
438 // // value == <int_value>
439 // Generated code in ad_<arch>.cpp adlc_verification()
440 // assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>");
441 //
442 definitions %{
443 // The default cost (of an ALU instruction).
444 int_def DEFAULT_COST ( 100, 100);
445 int_def HUGE_COST (1000000, 1000000);
446
447 // Memory refs are twice as expensive as run-of-the-mill.
448 int_def MEMORY_REF_COST ( 200, DEFAULT_COST * 2);
449
450 // Branches are even more expensive.
451 int_def BRANCH_COST ( 300, DEFAULT_COST * 3);
452 int_def CALL_COST ( 300, DEFAULT_COST * 3);
453 %}
454
455
456 //----------SOURCE BLOCK-------------------------------------------------------
457 // This is a block of C++ code which provides values, functions, and
458 // definitions necessary in the rest of the architecture description
459 source_hpp %{
460 // Must be visible to the DFA in dfa_sparc.cpp
461 extern bool can_branch_register( Node *bol, Node *cmp );
462
463 // Macros to extract hi & lo halves from a long pair.
464 // G0 is not part of any long pair, so assert on that.
465 // Prevents accidentally using G1 instead of G0.
466 #define LONG_HI_REG(x) (x)
467 #define LONG_LO_REG(x) (x)
468
469 %}
470
471 source %{
472 #define __ _masm.
473
474 // Block initializing store
475 #define ASI_BLK_INIT_QUAD_LDD_P 0xE2
476
477 // tertiary op of a LoadP or StoreP encoding
478 #define REGP_OP true
479
480 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding);
481 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding);
482 static Register reg_to_register_object(int register_encoding);
483
484 // Used by the DFA in dfa_sparc.cpp.
485 // Check for being able to use a V9 branch-on-register. Requires a
486 // compare-vs-zero, equal/not-equal, of a value which was zero- or sign-
487 // extended. Doesn't work following an integer ADD, for example, because of
488 // overflow (-1 incremented yields 0 plus a carry in the high-order word). On
489 // 32-bit V9 systems, interrupts currently blow away the high-order 32 bits and
490 // replace them with zero, which could become sign-extension in a different OS
491 // release. There's no obvious reason why an interrupt will ever fill these
492 // bits with non-zero junk (the registers are reloaded with standard LD
493 // instructions which either zero-fill or sign-fill).
494 bool can_branch_register( Node *bol, Node *cmp ) {
495 if( !BranchOnRegister ) return false;
496 #ifdef _LP64
497 if( cmp->Opcode() == Op_CmpP )
498 return true; // No problems with pointer compares
499 #endif
500 if( cmp->Opcode() == Op_CmpL )
501 return true; // No problems with long compares
502
503 if( !SparcV9RegsHiBitsZero ) return false;
504 if( bol->as_Bool()->_test._test != BoolTest::ne &&
505 bol->as_Bool()->_test._test != BoolTest::eq )
506 return false;
507
508 // Check for comparing against a 'safe' value. Any operation which
509 // clears out the high word is safe. Thus, loads and certain shifts
510 // are safe, as are non-negative constants. Any operation which
511 // preserves zero bits in the high word is safe as long as each of its
512 // inputs are safe. Thus, phis and bitwise booleans are safe if their
513 // inputs are safe. At present, the only important case to recognize
514 // seems to be loads. Constants should fold away, and shifts &
515 // logicals can use the 'cc' forms.
516 Node *x = cmp->in(1);
517 if( x->is_Load() ) return true;
518 if( x->is_Phi() ) {
519 for( uint i = 1; i < x->req(); i++ )
520 if( !x->in(i)->is_Load() )
521 return false;
522 return true;
523 }
524 return false;
525 }
526
527 // ****************************************************************************
528
529 // REQUIRED FUNCTIONALITY
530
531 // !!!!! Special hack to get all type of calls to specify the byte offset
532 // from the start of the call to the point where the return address
533 // will point.
534 // The "return address" is the address of the call instruction, plus 8.
535
536 int MachCallStaticJavaNode::ret_addr_offset() {
537 int offset = NativeCall::instruction_size; // call; delay slot
538 if (_method_handle_invoke)
539 offset += 4; // restore SP
540 return offset;
541 }
542
543 int MachCallDynamicJavaNode::ret_addr_offset() {
544 int vtable_index = this->_vtable_index;
545 if (vtable_index < 0) {
546 // must be invalid_vtable_index, not nonvirtual_vtable_index
547 assert(vtable_index == methodOopDesc::invalid_vtable_index, "correct sentinel value");
548 return (NativeMovConstReg::instruction_size +
549 NativeCall::instruction_size); // sethi; setlo; call; delay slot
550 } else {
551 assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
552 int entry_offset = instanceKlass::vtable_start_offset() + vtable_index*vtableEntry::size();
553 int v_off = entry_offset*wordSize + vtableEntry::method_offset_in_bytes();
554 int klass_load_size;
555 if (UseCompressedOops) {
556 assert(Universe::heap() != NULL, "java heap should be initialized");
557 if (Universe::narrow_oop_base() == NULL)
558 klass_load_size = 2*BytesPerInstWord; // see MacroAssembler::load_klass()
559 else
560 klass_load_size = 3*BytesPerInstWord;
561 } else {
562 klass_load_size = 1*BytesPerInstWord;
563 }
564 if( Assembler::is_simm13(v_off) ) {
565 return klass_load_size +
566 (2*BytesPerInstWord + // ld_ptr, ld_ptr
567 NativeCall::instruction_size); // call; delay slot
568 } else {
569 return klass_load_size +
570 (4*BytesPerInstWord + // set_hi, set, ld_ptr, ld_ptr
571 NativeCall::instruction_size); // call; delay slot
572 }
573 }
574 }
575
576 int MachCallRuntimeNode::ret_addr_offset() {
577 #ifdef _LP64
578 if (MacroAssembler::is_far_target(entry_point())) {
579 return NativeFarCall::instruction_size;
580 } else {
581 return NativeCall::instruction_size;
582 }
583 #else
584 return NativeCall::instruction_size; // call; delay slot
585 #endif
586 }
587
588 // Indicate if the safepoint node needs the polling page as an input.
589 // Since Sparc does not have absolute addressing, it does.
590 bool SafePointNode::needs_polling_address_input() {
591 return true;
592 }
593
594 // emit an interrupt that is caught by the debugger (for debugging compiler)
595 void emit_break(CodeBuffer &cbuf) {
596 MacroAssembler _masm(&cbuf);
597 __ breakpoint_trap();
598 }
599
600 #ifndef PRODUCT
601 void MachBreakpointNode::format( PhaseRegAlloc *, outputStream *st ) const {
602 st->print("TA");
603 }
604 #endif
605
606 void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
607 emit_break(cbuf);
608 }
609
610 uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const {
611 return MachNode::size(ra_);
612 }
613
614 // Traceable jump
615 void emit_jmpl(CodeBuffer &cbuf, int jump_target) {
616 MacroAssembler _masm(&cbuf);
617 Register rdest = reg_to_register_object(jump_target);
618 __ JMP(rdest, 0);
619 __ delayed()->nop();
620 }
621
622 // Traceable jump and set exception pc
623 void emit_jmpl_set_exception_pc(CodeBuffer &cbuf, int jump_target) {
624 MacroAssembler _masm(&cbuf);
625 Register rdest = reg_to_register_object(jump_target);
626 __ JMP(rdest, 0);
627 __ delayed()->add(O7, frame::pc_return_offset, Oissuing_pc );
628 }
629
630 void emit_nop(CodeBuffer &cbuf) {
631 MacroAssembler _masm(&cbuf);
632 __ nop();
633 }
634
635 void emit_illtrap(CodeBuffer &cbuf) {
636 MacroAssembler _masm(&cbuf);
637 __ illtrap(0);
638 }
639
640
641 intptr_t get_offset_from_base(const MachNode* n, const TypePtr* atype, int disp32) {
642 assert(n->rule() != loadUB_rule, "");
643
644 intptr_t offset = 0;
645 const TypePtr *adr_type = TYPE_PTR_SENTINAL; // Check for base==RegI, disp==immP
646 const Node* addr = n->get_base_and_disp(offset, adr_type);
647 assert(adr_type == (const TypePtr*)-1, "VerifyOops: no support for sparc operands with base==RegI, disp==immP");
648 assert(addr != NULL && addr != (Node*)-1, "invalid addr");
649 assert(addr->bottom_type()->isa_oopptr() == atype, "");
650 atype = atype->add_offset(offset);
651 assert(disp32 == offset, "wrong disp32");
652 return atype->_offset;
653 }
654
655
656 intptr_t get_offset_from_base_2(const MachNode* n, const TypePtr* atype, int disp32) {
657 assert(n->rule() != loadUB_rule, "");
658
659 intptr_t offset = 0;
660 Node* addr = n->in(2);
661 assert(addr->bottom_type()->isa_oopptr() == atype, "");
662 if (addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP) {
663 Node* a = addr->in(2/*AddPNode::Address*/);
664 Node* o = addr->in(3/*AddPNode::Offset*/);
665 offset = o->is_Con() ? o->bottom_type()->is_intptr_t()->get_con() : Type::OffsetBot;
666 atype = a->bottom_type()->is_ptr()->add_offset(offset);
667 assert(atype->isa_oop_ptr(), "still an oop");
668 }
669 offset = atype->is_ptr()->_offset;
670 if (offset != Type::OffsetBot) offset += disp32;
671 return offset;
672 }
673
674 static inline jdouble replicate_immI(int con, int count, int width) {
675 // Load a constant replicated "count" times with width "width"
676 int bit_width = width * 8;
677 jlong elt_val = con;
678 elt_val &= (((jlong) 1) << bit_width) - 1; // mask off sign bits
679 jlong val = elt_val;
680 for (int i = 0; i < count - 1; i++) {
681 val <<= bit_width;
682 val |= elt_val;
683 }
684 jdouble dval = *((jdouble*) &val); // coerce to double type
685 return dval;
686 }
687
688 // Standard Sparc opcode form2 field breakdown
689 static inline void emit2_19(CodeBuffer &cbuf, int f30, int f29, int f25, int f22, int f20, int f19, int f0 ) {
690 f0 &= (1<<19)-1; // Mask displacement to 19 bits
691 int op = (f30 << 30) |
692 (f29 << 29) |
693 (f25 << 25) |
694 (f22 << 22) |
695 (f20 << 20) |
696 (f19 << 19) |
697 (f0 << 0);
698 cbuf.insts()->emit_int32(op);
699 }
700
701 // Standard Sparc opcode form2 field breakdown
702 static inline void emit2_22(CodeBuffer &cbuf, int f30, int f25, int f22, int f0 ) {
703 f0 >>= 10; // Drop 10 bits
704 f0 &= (1<<22)-1; // Mask displacement to 22 bits
705 int op = (f30 << 30) |
706 (f25 << 25) |
707 (f22 << 22) |
708 (f0 << 0);
709 cbuf.insts()->emit_int32(op);
710 }
711
712 // Standard Sparc opcode form3 field breakdown
713 static inline void emit3(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int f5, int f0 ) {
714 int op = (f30 << 30) |
715 (f25 << 25) |
716 (f19 << 19) |
717 (f14 << 14) |
718 (f5 << 5) |
719 (f0 << 0);
720 cbuf.insts()->emit_int32(op);
721 }
722
723 // Standard Sparc opcode form3 field breakdown
724 static inline void emit3_simm13(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm13 ) {
725 simm13 &= (1<<13)-1; // Mask to 13 bits
726 int op = (f30 << 30) |
727 (f25 << 25) |
728 (f19 << 19) |
729 (f14 << 14) |
730 (1 << 13) | // bit to indicate immediate-mode
731 (simm13<<0);
732 cbuf.insts()->emit_int32(op);
733 }
734
735 static inline void emit3_simm10(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm10 ) {
736 simm10 &= (1<<10)-1; // Mask to 10 bits
737 emit3_simm13(cbuf,f30,f25,f19,f14,simm10);
738 }
739
740 #ifdef ASSERT
741 // Helper function for VerifyOops in emit_form3_mem_reg
742 void verify_oops_warning(const MachNode *n, int ideal_op, int mem_op) {
743 warning("VerifyOops encountered unexpected instruction:");
744 n->dump(2);
745 warning("Instruction has ideal_Opcode==Op_%s and op_ld==Op_%s \n", NodeClassNames[ideal_op], NodeClassNames[mem_op]);
746 }
747 #endif
748
749
750 void emit_form3_mem_reg(CodeBuffer &cbuf, const MachNode* n, int primary, int tertiary,
751 int src1_enc, int disp32, int src2_enc, int dst_enc) {
752
753 #ifdef ASSERT
754 // The following code implements the +VerifyOops feature.
755 // It verifies oop values which are loaded into or stored out of
756 // the current method activation. +VerifyOops complements techniques
757 // like ScavengeALot, because it eagerly inspects oops in transit,
758 // as they enter or leave the stack, as opposed to ScavengeALot,
759 // which inspects oops "at rest", in the stack or heap, at safepoints.
760 // For this reason, +VerifyOops can sometimes detect bugs very close
761 // to their point of creation. It can also serve as a cross-check
762 // on the validity of oop maps, when used toegether with ScavengeALot.
763
764 // It would be good to verify oops at other points, especially
765 // when an oop is used as a base pointer for a load or store.
766 // This is presently difficult, because it is hard to know when
767 // a base address is biased or not. (If we had such information,
768 // it would be easy and useful to make a two-argument version of
769 // verify_oop which unbiases the base, and performs verification.)
770
771 assert((uint)tertiary == 0xFFFFFFFF || tertiary == REGP_OP, "valid tertiary");
772 bool is_verified_oop_base = false;
773 bool is_verified_oop_load = false;
774 bool is_verified_oop_store = false;
775 int tmp_enc = -1;
776 if (VerifyOops && src1_enc != R_SP_enc) {
777 // classify the op, mainly for an assert check
778 int st_op = 0, ld_op = 0;
779 switch (primary) {
780 case Assembler::stb_op3: st_op = Op_StoreB; break;
781 case Assembler::sth_op3: st_op = Op_StoreC; break;
782 case Assembler::stx_op3: // may become StoreP or stay StoreI or StoreD0
783 case Assembler::stw_op3: st_op = Op_StoreI; break;
784 case Assembler::std_op3: st_op = Op_StoreL; break;
785 case Assembler::stf_op3: st_op = Op_StoreF; break;
786 case Assembler::stdf_op3: st_op = Op_StoreD; break;
787
788 case Assembler::ldsb_op3: ld_op = Op_LoadB; break;
789 case Assembler::lduh_op3: ld_op = Op_LoadUS; break;
790 case Assembler::ldsh_op3: ld_op = Op_LoadS; break;
791 case Assembler::ldx_op3: // may become LoadP or stay LoadI
792 case Assembler::ldsw_op3: // may become LoadP or stay LoadI
793 case Assembler::lduw_op3: ld_op = Op_LoadI; break;
794 case Assembler::ldd_op3: ld_op = Op_LoadL; break;
795 case Assembler::ldf_op3: ld_op = Op_LoadF; break;
796 case Assembler::lddf_op3: ld_op = Op_LoadD; break;
797 case Assembler::ldub_op3: ld_op = Op_LoadB; break;
798 case Assembler::prefetch_op3: ld_op = Op_LoadI; break;
799
800 default: ShouldNotReachHere();
801 }
802 if (tertiary == REGP_OP) {
803 if (st_op == Op_StoreI) st_op = Op_StoreP;
804 else if (ld_op == Op_LoadI) ld_op = Op_LoadP;
805 else ShouldNotReachHere();
806 if (st_op) {
807 // a store
808 // inputs are (0:control, 1:memory, 2:address, 3:value)
809 Node* n2 = n->in(3);
810 if (n2 != NULL) {
811 const Type* t = n2->bottom_type();
812 is_verified_oop_store = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false;
813 }
814 } else {
815 // a load
816 const Type* t = n->bottom_type();
817 is_verified_oop_load = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false;
818 }
819 }
820
821 if (ld_op) {
822 // a Load
823 // inputs are (0:control, 1:memory, 2:address)
824 if (!(n->ideal_Opcode()==ld_op) && // Following are special cases
825 !(n->ideal_Opcode()==Op_LoadLLocked && ld_op==Op_LoadI) &&
826 !(n->ideal_Opcode()==Op_LoadPLocked && ld_op==Op_LoadP) &&
827 !(n->ideal_Opcode()==Op_LoadI && ld_op==Op_LoadF) &&
828 !(n->ideal_Opcode()==Op_LoadF && ld_op==Op_LoadI) &&
829 !(n->ideal_Opcode()==Op_LoadRange && ld_op==Op_LoadI) &&
830 !(n->ideal_Opcode()==Op_LoadKlass && ld_op==Op_LoadP) &&
831 !(n->ideal_Opcode()==Op_LoadL && ld_op==Op_LoadI) &&
832 !(n->ideal_Opcode()==Op_LoadL_unaligned && ld_op==Op_LoadI) &&
833 !(n->ideal_Opcode()==Op_LoadD_unaligned && ld_op==Op_LoadF) &&
834 !(n->ideal_Opcode()==Op_ConvI2F && ld_op==Op_LoadF) &&
835 !(n->ideal_Opcode()==Op_ConvI2D && ld_op==Op_LoadF) &&
836 !(n->ideal_Opcode()==Op_PrefetchRead && ld_op==Op_LoadI) &&
837 !(n->ideal_Opcode()==Op_PrefetchWrite && ld_op==Op_LoadI) &&
838 !(n->ideal_Opcode()==Op_Load2I && ld_op==Op_LoadD) &&
839 !(n->ideal_Opcode()==Op_Load4C && ld_op==Op_LoadD) &&
840 !(n->ideal_Opcode()==Op_Load4S && ld_op==Op_LoadD) &&
841 !(n->ideal_Opcode()==Op_Load8B && ld_op==Op_LoadD) &&
842 !(n->rule() == loadUB_rule)) {
843 verify_oops_warning(n, n->ideal_Opcode(), ld_op);
844 }
845 } else if (st_op) {
846 // a Store
847 // inputs are (0:control, 1:memory, 2:address, 3:value)
848 if (!(n->ideal_Opcode()==st_op) && // Following are special cases
849 !(n->ideal_Opcode()==Op_StoreCM && st_op==Op_StoreB) &&
850 !(n->ideal_Opcode()==Op_StoreI && st_op==Op_StoreF) &&
851 !(n->ideal_Opcode()==Op_StoreF && st_op==Op_StoreI) &&
852 !(n->ideal_Opcode()==Op_StoreL && st_op==Op_StoreI) &&
853 !(n->ideal_Opcode()==Op_Store2I && st_op==Op_StoreD) &&
854 !(n->ideal_Opcode()==Op_Store4C && st_op==Op_StoreD) &&
855 !(n->ideal_Opcode()==Op_Store8B && st_op==Op_StoreD) &&
856 !(n->ideal_Opcode()==Op_StoreD && st_op==Op_StoreI && n->rule() == storeD0_rule)) {
857 verify_oops_warning(n, n->ideal_Opcode(), st_op);
858 }
859 }
860
861 if (src2_enc == R_G0_enc && n->rule() != loadUB_rule && n->ideal_Opcode() != Op_StoreCM ) {
862 Node* addr = n->in(2);
863 if (!(addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP)) {
864 const TypeOopPtr* atype = addr->bottom_type()->isa_instptr(); // %%% oopptr?
865 if (atype != NULL) {
866 intptr_t offset = get_offset_from_base(n, atype, disp32);
867 intptr_t offset_2 = get_offset_from_base_2(n, atype, disp32);
868 if (offset != offset_2) {
869 get_offset_from_base(n, atype, disp32);
870 get_offset_from_base_2(n, atype, disp32);
871 }
872 assert(offset == offset_2, "different offsets");
873 if (offset == disp32) {
874 // we now know that src1 is a true oop pointer
875 is_verified_oop_base = true;
876 if (ld_op && src1_enc == dst_enc && ld_op != Op_LoadF && ld_op != Op_LoadD) {
877 if( primary == Assembler::ldd_op3 ) {
878 is_verified_oop_base = false; // Cannot 'ldd' into O7
879 } else {
880 tmp_enc = dst_enc;
881 dst_enc = R_O7_enc; // Load into O7; preserve source oop
882 assert(src1_enc != dst_enc, "");
883 }
884 }
885 }
886 if (st_op && (( offset == oopDesc::klass_offset_in_bytes())
887 || offset == oopDesc::mark_offset_in_bytes())) {
888 // loading the mark should not be allowed either, but
889 // we don't check this since it conflicts with InlineObjectHash
890 // usage of LoadINode to get the mark. We could keep the
891 // check if we create a new LoadMarkNode
892 // but do not verify the object before its header is initialized
893 ShouldNotReachHere();
894 }
895 }
896 }
897 }
898 }
899 #endif
900
901 uint instr;
902 instr = (Assembler::ldst_op << 30)
903 | (dst_enc << 25)
904 | (primary << 19)
905 | (src1_enc << 14);
906
907 uint index = src2_enc;
908 int disp = disp32;
909
910 if (src1_enc == R_SP_enc || src1_enc == R_FP_enc)
911 disp += STACK_BIAS;
912
913 // We should have a compiler bailout here rather than a guarantee.
914 // Better yet would be some mechanism to handle variable-size matches correctly.
915 guarantee(Assembler::is_simm13(disp), "Do not match large constant offsets" );
916
917 if( disp == 0 ) {
918 // use reg-reg form
919 // bit 13 is already zero
920 instr |= index;
921 } else {
922 // use reg-imm form
923 instr |= 0x00002000; // set bit 13 to one
924 instr |= disp & 0x1FFF;
925 }
926
927 cbuf.insts()->emit_int32(instr);
928
929 #ifdef ASSERT
930 {
931 MacroAssembler _masm(&cbuf);
932 if (is_verified_oop_base) {
933 __ verify_oop(reg_to_register_object(src1_enc));
934 }
935 if (is_verified_oop_store) {
936 __ verify_oop(reg_to_register_object(dst_enc));
937 }
938 if (tmp_enc != -1) {
939 __ mov(O7, reg_to_register_object(tmp_enc));
940 }
941 if (is_verified_oop_load) {
942 __ verify_oop(reg_to_register_object(dst_enc));
943 }
944 }
945 #endif
946 }
947
948 void emit_call_reloc(CodeBuffer &cbuf, intptr_t entry_point, relocInfo::relocType rtype, bool preserve_g2 = false) {
949 // The method which records debug information at every safepoint
950 // expects the call to be the first instruction in the snippet as
951 // it creates a PcDesc structure which tracks the offset of a call
952 // from the start of the codeBlob. This offset is computed as
953 // code_end() - code_begin() of the code which has been emitted
954 // so far.
955 // In this particular case we have skirted around the problem by
956 // putting the "mov" instruction in the delay slot but the problem
957 // may bite us again at some other point and a cleaner/generic
958 // solution using relocations would be needed.
959 MacroAssembler _masm(&cbuf);
960 __ set_inst_mark();
961
962 // We flush the current window just so that there is a valid stack copy
963 // the fact that the current window becomes active again instantly is
964 // not a problem there is nothing live in it.
965
966 #ifdef ASSERT
967 int startpos = __ offset();
968 #endif /* ASSERT */
969
970 __ call((address)entry_point, rtype);
971
972 if (preserve_g2) __ delayed()->mov(G2, L7);
973 else __ delayed()->nop();
974
975 if (preserve_g2) __ mov(L7, G2);
976
977 #ifdef ASSERT
978 if (preserve_g2 && (VerifyCompiledCode || VerifyOops)) {
979 #ifdef _LP64
980 // Trash argument dump slots.
981 __ set(0xb0b8ac0db0b8ac0d, G1);
982 __ mov(G1, G5);
983 __ stx(G1, SP, STACK_BIAS + 0x80);
984 __ stx(G1, SP, STACK_BIAS + 0x88);
985 __ stx(G1, SP, STACK_BIAS + 0x90);
986 __ stx(G1, SP, STACK_BIAS + 0x98);
987 __ stx(G1, SP, STACK_BIAS + 0xA0);
988 __ stx(G1, SP, STACK_BIAS + 0xA8);
989 #else // _LP64
990 // this is also a native call, so smash the first 7 stack locations,
991 // and the various registers
992
993 // Note: [SP+0x40] is sp[callee_aggregate_return_pointer_sp_offset],
994 // while [SP+0x44..0x58] are the argument dump slots.
995 __ set((intptr_t)0xbaadf00d, G1);
996 __ mov(G1, G5);
997 __ sllx(G1, 32, G1);
998 __ or3(G1, G5, G1);
999 __ mov(G1, G5);
1000 __ stx(G1, SP, 0x40);
1001 __ stx(G1, SP, 0x48);
1002 __ stx(G1, SP, 0x50);
1003 __ stw(G1, SP, 0x58); // Do not trash [SP+0x5C] which is a usable spill slot
1004 #endif // _LP64
1005 }
1006 #endif /*ASSERT*/
1007 }
1008
1009 //=============================================================================
1010 // REQUIRED FUNCTIONALITY for encoding
1011 void emit_lo(CodeBuffer &cbuf, int val) { }
1012 void emit_hi(CodeBuffer &cbuf, int val) { }
1013
1014
1015 //=============================================================================
1016 const bool Matcher::constant_table_absolute_addressing = false;
1017 const RegMask& MachConstantBaseNode::_out_RegMask = PTR_REG_mask;
1018
1019 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
1020 Compile* C = ra_->C;
1021 Compile::ConstantTable& constant_table = C->constant_table();
1022 MacroAssembler _masm(&cbuf);
1023
1024 Register r = as_Register(ra_->get_encode(this));
1025 CodeSection* cs = __ code()->consts();
1026 int consts_size = cs->align_at_start(cs->size());
1027
1028 if (UseRDPCForConstantTableBase) {
1029 // For the following RDPC logic to work correctly the consts
1030 // section must be allocated right before the insts section. This
1031 // assert checks for that. The layout and the SECT_* constants
1032 // are defined in src/share/vm/asm/codeBuffer.hpp.
1033 assert(CodeBuffer::SECT_CONSTS + 1 == CodeBuffer::SECT_INSTS, "must be");
1034 int offset = __ offset();
1035 int disp;
1036
1037 // If the displacement from the current PC to the constant table
1038 // base fits into simm13 we set the constant table base to the
1039 // current PC.
1040 if (__ is_simm13(-(consts_size + offset))) {
1041 constant_table.set_table_base_offset(-(consts_size + offset));
1042 disp = 0;
1043 } else {
1044 // If the offset of the top constant (last entry in the table)
1045 // fits into simm13 we set the constant table base to the actual
1046 // table base.
1047 if (__ is_simm13(constant_table.top_offset())) {
1048 constant_table.set_table_base_offset(0);
1049 disp = consts_size + offset;
1050 } else {
1051 // Otherwise we set the constant table base in the middle of the
1052 // constant table.
1053 int half_consts_size = consts_size / 2;
1054 assert(half_consts_size * 2 == consts_size, "sanity");
1055 constant_table.set_table_base_offset(-half_consts_size); // table base offset gets added to the load displacement.
1056 disp = half_consts_size + offset;
1057 }
1058 }
1059
1060 __ rdpc(r);
1061
1062 if (disp != 0) {
1063 assert(r != O7, "need temporary");
1064 __ sub(r, __ ensure_simm13_or_reg(disp, O7), r);
1065 }
1066 }
1067 else {
1068 // Materialize the constant table base.
1069 assert(constant_table.size() == consts_size, err_msg("must be: %d == %d", constant_table.size(), consts_size));
1070 address baseaddr = cs->start() + -(constant_table.table_base_offset());
1071 RelocationHolder rspec = internal_word_Relocation::spec(baseaddr);
1072 AddressLiteral base(baseaddr, rspec);
1073 __ set(base, r);
1074 }
1075 }
1076
1077 uint MachConstantBaseNode::size(PhaseRegAlloc*) const {
1078 if (UseRDPCForConstantTableBase) {
1079 // This is really the worst case but generally it's only 1 instruction.
1080 return (1 /*rdpc*/ + 1 /*sub*/ + MacroAssembler::worst_case_insts_for_set()) * BytesPerInstWord;
1081 } else {
1082 return MacroAssembler::worst_case_insts_for_set() * BytesPerInstWord;
1083 }
1084 }
1085
1086 #ifndef PRODUCT
1087 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
1088 char reg[128];
1089 ra_->dump_register(this, reg);
1090 if (UseRDPCForConstantTableBase) {
1091 st->print("RDPC %s\t! constant table base", reg);
1092 } else {
1093 st->print("SET &constanttable,%s\t! constant table base", reg);
1094 }
1095 }
1096 #endif
1097
1098
1099 //=============================================================================
1100
1101 #ifndef PRODUCT
1102 void MachPrologNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1103 Compile* C = ra_->C;
1104
1105 for (int i = 0; i < OptoPrologueNops; i++) {
1106 st->print_cr("NOP"); st->print("\t");
1107 }
1108
1109 if( VerifyThread ) {
1110 st->print_cr("Verify_Thread"); st->print("\t");
1111 }
1112
1113 size_t framesize = C->frame_slots() << LogBytesPerInt;
1114
1115 // Calls to C2R adapters often do not accept exceptional returns.
1116 // We require that their callers must bang for them. But be careful, because
1117 // some VM calls (such as call site linkage) can use several kilobytes of
1118 // stack. But the stack safety zone should account for that.
1119 // See bugs 4446381, 4468289, 4497237.
1120 if (C->need_stack_bang(framesize)) {
1121 st->print_cr("! stack bang"); st->print("\t");
1122 }
1123
1124 if (Assembler::is_simm13(-framesize)) {
1125 st->print ("SAVE R_SP,-%d,R_SP",framesize);
1126 } else {
1127 st->print_cr("SETHI R_SP,hi%%(-%d),R_G3",framesize); st->print("\t");
1128 st->print_cr("ADD R_G3,lo%%(-%d),R_G3",framesize); st->print("\t");
1129 st->print ("SAVE R_SP,R_G3,R_SP");
1130 }
1131
1132 }
1133 #endif
1134
1135 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1136 Compile* C = ra_->C;
1137 MacroAssembler _masm(&cbuf);
1138
1139 for (int i = 0; i < OptoPrologueNops; i++) {
1140 __ nop();
1141 }
1142
1143 __ verify_thread();
1144
1145 size_t framesize = C->frame_slots() << LogBytesPerInt;
1146 assert(framesize >= 16*wordSize, "must have room for reg. save area");
1147 assert(framesize%(2*wordSize) == 0, "must preserve 2*wordSize alignment");
1148
1149 // Calls to C2R adapters often do not accept exceptional returns.
1150 // We require that their callers must bang for them. But be careful, because
1151 // some VM calls (such as call site linkage) can use several kilobytes of
1152 // stack. But the stack safety zone should account for that.
1153 // See bugs 4446381, 4468289, 4497237.
1154 if (C->need_stack_bang(framesize)) {
1155 __ generate_stack_overflow_check(framesize);
1156 }
1157
1158 if (Assembler::is_simm13(-framesize)) {
1159 __ save(SP, -framesize, SP);
1160 } else {
1161 __ sethi(-framesize & ~0x3ff, G3);
1162 __ add(G3, -framesize & 0x3ff, G3);
1163 __ save(SP, G3, SP);
1164 }
1165 C->set_frame_complete( __ offset() );
1166 }
1167
1168 uint MachPrologNode::size(PhaseRegAlloc *ra_) const {
1169 return MachNode::size(ra_);
1170 }
1171
1172 int MachPrologNode::reloc() const {
1173 return 10; // a large enough number
1174 }
1175
1176 //=============================================================================
1177 #ifndef PRODUCT
1178 void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1179 Compile* C = ra_->C;
1180
1181 if( do_polling() && ra_->C->is_method_compilation() ) {
1182 st->print("SETHI #PollAddr,L0\t! Load Polling address\n\t");
1183 #ifdef _LP64
1184 st->print("LDX [L0],G0\t!Poll for Safepointing\n\t");
1185 #else
1186 st->print("LDUW [L0],G0\t!Poll for Safepointing\n\t");
1187 #endif
1188 }
1189
1190 if( do_polling() )
1191 st->print("RET\n\t");
1192
1193 st->print("RESTORE");
1194 }
1195 #endif
1196
1197 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1198 MacroAssembler _masm(&cbuf);
1199 Compile* C = ra_->C;
1200
1201 __ verify_thread();
1202
1203 // If this does safepoint polling, then do it here
1204 if( do_polling() && ra_->C->is_method_compilation() ) {
1205 AddressLiteral polling_page(os::get_polling_page());
1206 __ sethi(polling_page, L0);
1207 __ relocate(relocInfo::poll_return_type);
1208 __ ld_ptr( L0, 0, G0 );
1209 }
1210
1211 // If this is a return, then stuff the restore in the delay slot
1212 if( do_polling() ) {
1213 __ ret();
1214 __ delayed()->restore();
1215 } else {
1216 __ restore();
1217 }
1218 }
1219
1220 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
1221 return MachNode::size(ra_);
1222 }
1223
1224 int MachEpilogNode::reloc() const {
1225 return 16; // a large enough number
1226 }
1227
1228 const Pipeline * MachEpilogNode::pipeline() const {
1229 return MachNode::pipeline_class();
1230 }
1231
1232 int MachEpilogNode::safepoint_offset() const {
1233 assert( do_polling(), "no return for this epilog node");
1234 return MacroAssembler::insts_for_sethi(os::get_polling_page()) * BytesPerInstWord;
1235 }
1236
1237 //=============================================================================
1238
1239 // Figure out which register class each belongs in: rc_int, rc_float, rc_stack
1240 enum RC { rc_bad, rc_int, rc_float, rc_stack };
1241 static enum RC rc_class( OptoReg::Name reg ) {
1242 if( !OptoReg::is_valid(reg) ) return rc_bad;
1243 if (OptoReg::is_stack(reg)) return rc_stack;
1244 VMReg r = OptoReg::as_VMReg(reg);
1245 if (r->is_Register()) return rc_int;
1246 assert(r->is_FloatRegister(), "must be");
1247 return rc_float;
1248 }
1249
1250 static int impl_helper( const MachNode *mach, CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, bool is_load, int offset, int reg, int opcode, const char *op_str, int size, outputStream* st ) {
1251 if( cbuf ) {
1252 // Better yet would be some mechanism to handle variable-size matches correctly
1253 if (!Assembler::is_simm13(offset + STACK_BIAS)) {
1254 ra_->C->record_method_not_compilable("unable to handle large constant offsets");
1255 } else {
1256 emit_form3_mem_reg(*cbuf, mach, opcode, -1, R_SP_enc, offset, 0, Matcher::_regEncode[reg]);
1257 }
1258 }
1259 #ifndef PRODUCT
1260 else if( !do_size ) {
1261 if( size != 0 ) st->print("\n\t");
1262 if( is_load ) st->print("%s [R_SP + #%d],R_%s\t! spill",op_str,offset,OptoReg::regname(reg));
1263 else st->print("%s R_%s,[R_SP + #%d]\t! spill",op_str,OptoReg::regname(reg),offset);
1264 }
1265 #endif
1266 return size+4;
1267 }
1268
1269 static int impl_mov_helper( CodeBuffer *cbuf, bool do_size, int src, int dst, int op1, int op2, const char *op_str, int size, outputStream* st ) {
1270 if( cbuf ) emit3( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst], op1, 0, op2, Matcher::_regEncode[src] );
1271 #ifndef PRODUCT
1272 else if( !do_size ) {
1273 if( size != 0 ) st->print("\n\t");
1274 st->print("%s R_%s,R_%s\t! spill",op_str,OptoReg::regname(src),OptoReg::regname(dst));
1275 }
1276 #endif
1277 return size+4;
1278 }
1279
1280 uint MachSpillCopyNode::implementation( CodeBuffer *cbuf,
1281 PhaseRegAlloc *ra_,
1282 bool do_size,
1283 outputStream* st ) const {
1284 // Get registers to move
1285 OptoReg::Name src_second = ra_->get_reg_second(in(1));
1286 OptoReg::Name src_first = ra_->get_reg_first(in(1));
1287 OptoReg::Name dst_second = ra_->get_reg_second(this );
1288 OptoReg::Name dst_first = ra_->get_reg_first(this );
1289
1290 enum RC src_second_rc = rc_class(src_second);
1291 enum RC src_first_rc = rc_class(src_first);
1292 enum RC dst_second_rc = rc_class(dst_second);
1293 enum RC dst_first_rc = rc_class(dst_first);
1294
1295 assert( OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register" );
1296
1297 // Generate spill code!
1298 int size = 0;
1299
1300 if( src_first == dst_first && src_second == dst_second )
1301 return size; // Self copy, no move
1302
1303 // --------------------------------------
1304 // Check for mem-mem move. Load into unused float registers and fall into
1305 // the float-store case.
1306 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
1307 int offset = ra_->reg2offset(src_first);
1308 // Further check for aligned-adjacent pair, so we can use a double load
1309 if( (src_first&1)==0 && src_first+1 == src_second ) {
1310 src_second = OptoReg::Name(R_F31_num);
1311 src_second_rc = rc_float;
1312 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F30_num,Assembler::lddf_op3,"LDDF",size, st);
1313 } else {
1314 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F30_num,Assembler::ldf_op3 ,"LDF ",size, st);
1315 }
1316 src_first = OptoReg::Name(R_F30_num);
1317 src_first_rc = rc_float;
1318 }
1319
1320 if( src_second_rc == rc_stack && dst_second_rc == rc_stack ) {
1321 int offset = ra_->reg2offset(src_second);
1322 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F31_num,Assembler::ldf_op3,"LDF ",size, st);
1323 src_second = OptoReg::Name(R_F31_num);
1324 src_second_rc = rc_float;
1325 }
1326
1327 // --------------------------------------
1328 // Check for float->int copy; requires a trip through memory
1329 if( src_first_rc == rc_float && dst_first_rc == rc_int ) {
1330 int offset = frame::register_save_words*wordSize;
1331 if( cbuf ) {
1332 emit3_simm13( *cbuf, Assembler::arith_op, R_SP_enc, Assembler::sub_op3, R_SP_enc, 16 );
1333 impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st);
1334 impl_helper(this,cbuf,ra_,do_size,true ,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st);
1335 emit3_simm13( *cbuf, Assembler::arith_op, R_SP_enc, Assembler::add_op3, R_SP_enc, 16 );
1336 }
1337 #ifndef PRODUCT
1338 else if( !do_size ) {
1339 if( size != 0 ) st->print("\n\t");
1340 st->print( "SUB R_SP,16,R_SP\n");
1341 impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st);
1342 impl_helper(this,cbuf,ra_,do_size,true ,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st);
1343 st->print("\tADD R_SP,16,R_SP\n");
1344 }
1345 #endif
1346 size += 16;
1347 }
1348
1349 // --------------------------------------
1350 // In the 32-bit 1-reg-longs build ONLY, I see mis-aligned long destinations.
1351 // In such cases, I have to do the big-endian swap. For aligned targets, the
1352 // hardware does the flop for me. Doubles are always aligned, so no problem
1353 // there. Misaligned sources only come from native-long-returns (handled
1354 // special below).
1355 #ifndef _LP64
1356 if( src_first_rc == rc_int && // source is already big-endian
1357 src_second_rc != rc_bad && // 64-bit move
1358 ((dst_first&1)!=0 || dst_second != dst_first+1) ) { // misaligned dst
1359 assert( (src_first&1)==0 && src_second == src_first+1, "source must be aligned" );
1360 // Do the big-endian flop.
1361 OptoReg::Name tmp = dst_first ; dst_first = dst_second ; dst_second = tmp ;
1362 enum RC tmp_rc = dst_first_rc; dst_first_rc = dst_second_rc; dst_second_rc = tmp_rc;
1363 }
1364 #endif
1365
1366 // --------------------------------------
1367 // Check for integer reg-reg copy
1368 if( src_first_rc == rc_int && dst_first_rc == rc_int ) {
1369 #ifndef _LP64
1370 if( src_first == R_O0_num && src_second == R_O1_num ) { // Check for the evil O0/O1 native long-return case
1371 // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value
1372 // as stored in memory. On a big-endian machine like SPARC, this means that the _second
1373 // operand contains the least significant word of the 64-bit value and vice versa.
1374 OptoReg::Name tmp = OptoReg::Name(R_O7_num);
1375 assert( (dst_first&1)==0 && dst_second == dst_first+1, "return a native O0/O1 long to an aligned-adjacent 64-bit reg" );
1376 // Shift O0 left in-place, zero-extend O1, then OR them into the dst
1377 if( cbuf ) {
1378 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[tmp], Assembler::sllx_op3, Matcher::_regEncode[src_first], 0x1020 );
1379 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[src_second], Assembler::srl_op3, Matcher::_regEncode[src_second], 0x0000 );
1380 emit3 ( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler:: or_op3, Matcher::_regEncode[tmp], 0, Matcher::_regEncode[src_second] );
1381 #ifndef PRODUCT
1382 } else if( !do_size ) {
1383 if( size != 0 ) st->print("\n\t");
1384 st->print("SLLX R_%s,32,R_%s\t! Move O0-first to O7-high\n\t", OptoReg::regname(src_first), OptoReg::regname(tmp));
1385 st->print("SRL R_%s, 0,R_%s\t! Zero-extend O1\n\t", OptoReg::regname(src_second), OptoReg::regname(src_second));
1386 st->print("OR R_%s,R_%s,R_%s\t! spill",OptoReg::regname(tmp), OptoReg::regname(src_second), OptoReg::regname(dst_first));
1387 #endif
1388 }
1389 return size+12;
1390 }
1391 else if( dst_first == R_I0_num && dst_second == R_I1_num ) {
1392 // returning a long value in I0/I1
1393 // a SpillCopy must be able to target a return instruction's reg_class
1394 // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value
1395 // as stored in memory. On a big-endian machine like SPARC, this means that the _second
1396 // operand contains the least significant word of the 64-bit value and vice versa.
1397 OptoReg::Name tdest = dst_first;
1398
1399 if (src_first == dst_first) {
1400 tdest = OptoReg::Name(R_O7_num);
1401 size += 4;
1402 }
1403
1404 if( cbuf ) {
1405 assert( (src_first&1) == 0 && (src_first+1) == src_second, "return value was in an aligned-adjacent 64-bit reg");
1406 // Shift value in upper 32-bits of src to lower 32-bits of I0; move lower 32-bits to I1
1407 // ShrL_reg_imm6
1408 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[tdest], Assembler::srlx_op3, Matcher::_regEncode[src_second], 32 | 0x1000 );
1409 // ShrR_reg_imm6 src, 0, dst
1410 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srl_op3, Matcher::_regEncode[src_first], 0x0000 );
1411 if (tdest != dst_first) {
1412 emit3 ( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler::or_op3, 0/*G0*/, 0/*op2*/, Matcher::_regEncode[tdest] );
1413 }
1414 }
1415 #ifndef PRODUCT
1416 else if( !do_size ) {
1417 if( size != 0 ) st->print("\n\t"); // %%%%% !!!!!
1418 st->print("SRLX R_%s,32,R_%s\t! Extract MSW\n\t",OptoReg::regname(src_second),OptoReg::regname(tdest));
1419 st->print("SRL R_%s, 0,R_%s\t! Extract LSW\n\t",OptoReg::regname(src_first),OptoReg::regname(dst_second));
1420 if (tdest != dst_first) {
1421 st->print("MOV R_%s,R_%s\t! spill\n\t", OptoReg::regname(tdest), OptoReg::regname(dst_first));
1422 }
1423 }
1424 #endif // PRODUCT
1425 return size+8;
1426 }
1427 #endif // !_LP64
1428 // Else normal reg-reg copy
1429 assert( src_second != dst_first, "smashed second before evacuating it" );
1430 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::or_op3,0,"MOV ",size, st);
1431 assert( (src_first&1) == 0 && (dst_first&1) == 0, "never move second-halves of int registers" );
1432 // This moves an aligned adjacent pair.
1433 // See if we are done.
1434 if( src_first+1 == src_second && dst_first+1 == dst_second )
1435 return size;
1436 }
1437
1438 // Check for integer store
1439 if( src_first_rc == rc_int && dst_first_rc == rc_stack ) {
1440 int offset = ra_->reg2offset(dst_first);
1441 // Further check for aligned-adjacent pair, so we can use a double store
1442 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1443 return impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stx_op3,"STX ",size, st);
1444 size = impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stw_op3,"STW ",size, st);
1445 }
1446
1447 // Check for integer load
1448 if( dst_first_rc == rc_int && src_first_rc == rc_stack ) {
1449 int offset = ra_->reg2offset(src_first);
1450 // Further check for aligned-adjacent pair, so we can use a double load
1451 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1452 return impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::ldx_op3 ,"LDX ",size, st);
1453 size = impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st);
1454 }
1455
1456 // Check for float reg-reg copy
1457 if( src_first_rc == rc_float && dst_first_rc == rc_float ) {
1458 // Further check for aligned-adjacent pair, so we can use a double move
1459 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1460 return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::fpop1_op3,Assembler::fmovd_opf,"FMOVD",size, st);
1461 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::fpop1_op3,Assembler::fmovs_opf,"FMOVS",size, st);
1462 }
1463
1464 // Check for float store
1465 if( src_first_rc == rc_float && dst_first_rc == rc_stack ) {
1466 int offset = ra_->reg2offset(dst_first);
1467 // Further check for aligned-adjacent pair, so we can use a double store
1468 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1469 return impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stdf_op3,"STDF",size, st);
1470 size = impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st);
1471 }
1472
1473 // Check for float load
1474 if( dst_first_rc == rc_float && src_first_rc == rc_stack ) {
1475 int offset = ra_->reg2offset(src_first);
1476 // Further check for aligned-adjacent pair, so we can use a double load
1477 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1478 return impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::lddf_op3,"LDDF",size, st);
1479 size = impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::ldf_op3 ,"LDF ",size, st);
1480 }
1481
1482 // --------------------------------------------------------------------
1483 // Check for hi bits still needing moving. Only happens for misaligned
1484 // arguments to native calls.
1485 if( src_second == dst_second )
1486 return size; // Self copy; no move
1487 assert( src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad" );
1488
1489 #ifndef _LP64
1490 // In the LP64 build, all registers can be moved as aligned/adjacent
1491 // pairs, so there's never any need to move the high bits separately.
1492 // The 32-bit builds have to deal with the 32-bit ABI which can force
1493 // all sorts of silly alignment problems.
1494
1495 // Check for integer reg-reg copy. Hi bits are stuck up in the top
1496 // 32-bits of a 64-bit register, but are needed in low bits of another
1497 // register (else it's a hi-bits-to-hi-bits copy which should have
1498 // happened already as part of a 64-bit move)
1499 if( src_second_rc == rc_int && dst_second_rc == rc_int ) {
1500 assert( (src_second&1)==1, "its the evil O0/O1 native return case" );
1501 assert( (dst_second&1)==0, "should have moved with 1 64-bit move" );
1502 // Shift src_second down to dst_second's low bits.
1503 if( cbuf ) {
1504 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020 );
1505 #ifndef PRODUCT
1506 } else if( !do_size ) {
1507 if( size != 0 ) st->print("\n\t");
1508 st->print("SRLX R_%s,32,R_%s\t! spill: Move high bits down low",OptoReg::regname(src_second-1),OptoReg::regname(dst_second));
1509 #endif
1510 }
1511 return size+4;
1512 }
1513
1514 // Check for high word integer store. Must down-shift the hi bits
1515 // into a temp register, then fall into the case of storing int bits.
1516 if( src_second_rc == rc_int && dst_second_rc == rc_stack && (src_second&1)==1 ) {
1517 // Shift src_second down to dst_second's low bits.
1518 if( cbuf ) {
1519 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[R_O7_num], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020 );
1520 #ifndef PRODUCT
1521 } else if( !do_size ) {
1522 if( size != 0 ) st->print("\n\t");
1523 st->print("SRLX R_%s,32,R_%s\t! spill: Move high bits down low",OptoReg::regname(src_second-1),OptoReg::regname(R_O7_num));
1524 #endif
1525 }
1526 size+=4;
1527 src_second = OptoReg::Name(R_O7_num); // Not R_O7H_num!
1528 }
1529
1530 // Check for high word integer load
1531 if( dst_second_rc == rc_int && src_second_rc == rc_stack )
1532 return impl_helper(this,cbuf,ra_,do_size,true ,ra_->reg2offset(src_second),dst_second,Assembler::lduw_op3,"LDUW",size, st);
1533
1534 // Check for high word integer store
1535 if( src_second_rc == rc_int && dst_second_rc == rc_stack )
1536 return impl_helper(this,cbuf,ra_,do_size,false,ra_->reg2offset(dst_second),src_second,Assembler::stw_op3 ,"STW ",size, st);
1537
1538 // Check for high word float store
1539 if( src_second_rc == rc_float && dst_second_rc == rc_stack )
1540 return impl_helper(this,cbuf,ra_,do_size,false,ra_->reg2offset(dst_second),src_second,Assembler::stf_op3 ,"STF ",size, st);
1541
1542 #endif // !_LP64
1543
1544 Unimplemented();
1545 }
1546
1547 #ifndef PRODUCT
1548 void MachSpillCopyNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1549 implementation( NULL, ra_, false, st );
1550 }
1551 #endif
1552
1553 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1554 implementation( &cbuf, ra_, false, NULL );
1555 }
1556
1557 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1558 return implementation( NULL, ra_, true, NULL );
1559 }
1560
1561 //=============================================================================
1562 #ifndef PRODUCT
1563 void MachNopNode::format( PhaseRegAlloc *, outputStream *st ) const {
1564 st->print("NOP \t# %d bytes pad for loops and calls", 4 * _count);
1565 }
1566 #endif
1567
1568 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc * ) const {
1569 MacroAssembler _masm(&cbuf);
1570 for(int i = 0; i < _count; i += 1) {
1571 __ nop();
1572 }
1573 }
1574
1575 uint MachNopNode::size(PhaseRegAlloc *ra_) const {
1576 return 4 * _count;
1577 }
1578
1579
1580 //=============================================================================
1581 #ifndef PRODUCT
1582 void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1583 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1584 int reg = ra_->get_reg_first(this);
1585 st->print("LEA [R_SP+#%d+BIAS],%s",offset,Matcher::regName[reg]);
1586 }
1587 #endif
1588
1589 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1590 MacroAssembler _masm(&cbuf);
1591 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()) + STACK_BIAS;
1592 int reg = ra_->get_encode(this);
1593
1594 if (Assembler::is_simm13(offset)) {
1595 __ add(SP, offset, reg_to_register_object(reg));
1596 } else {
1597 __ set(offset, O7);
1598 __ add(SP, O7, reg_to_register_object(reg));
1599 }
1600 }
1601
1602 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
1603 // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_)
1604 assert(ra_ == ra_->C->regalloc(), "sanity");
1605 return ra_->C->scratch_emit_size(this);
1606 }
1607
1608 //=============================================================================
1609
1610 // emit call stub, compiled java to interpretor
1611 void emit_java_to_interp(CodeBuffer &cbuf ) {
1612
1613 // Stub is fixed up when the corresponding call is converted from calling
1614 // compiled code to calling interpreted code.
1615 // set (empty), G5
1616 // jmp -1
1617
1618 address mark = cbuf.insts_mark(); // get mark within main instrs section
1619
1620 MacroAssembler _masm(&cbuf);
1621
1622 address base =
1623 __ start_a_stub(Compile::MAX_stubs_size);
1624 if (base == NULL) return; // CodeBuffer::expand failed
1625
1626 // static stub relocation stores the instruction address of the call
1627 __ relocate(static_stub_Relocation::spec(mark));
1628
1629 __ set_oop(NULL, reg_to_register_object(Matcher::inline_cache_reg_encode()));
1630
1631 __ set_inst_mark();
1632 AddressLiteral addrlit(-1);
1633 __ JUMP(addrlit, G3, 0);
1634
1635 __ delayed()->nop();
1636
1637 // Update current stubs pointer and restore code_end.
1638 __ end_a_stub();
1639 }
1640
1641 // size of call stub, compiled java to interpretor
1642 uint size_java_to_interp() {
1643 // This doesn't need to be accurate but it must be larger or equal to
1644 // the real size of the stub.
1645 return (NativeMovConstReg::instruction_size + // sethi/setlo;
1646 NativeJump::instruction_size + // sethi; jmp; nop
1647 (TraceJumps ? 20 * BytesPerInstWord : 0) );
1648 }
1649 // relocation entries for call stub, compiled java to interpretor
1650 uint reloc_java_to_interp() {
1651 return 10; // 4 in emit_java_to_interp + 1 in Java_Static_Call
1652 }
1653
1654
1655 //=============================================================================
1656 #ifndef PRODUCT
1657 void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1658 st->print_cr("\nUEP:");
1659 #ifdef _LP64
1660 if (UseCompressedOops) {
1661 assert(Universe::heap() != NULL, "java heap should be initialized");
1662 st->print_cr("\tLDUW [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check - compressed klass");
1663 st->print_cr("\tSLL R_G5,3,R_G5");
1664 if (Universe::narrow_oop_base() != NULL)
1665 st->print_cr("\tADD R_G5,R_G6_heap_base,R_G5");
1666 } else {
1667 st->print_cr("\tLDX [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check");
1668 }
1669 st->print_cr("\tCMP R_G5,R_G3" );
1670 st->print ("\tTne xcc,R_G0+ST_RESERVED_FOR_USER_0+2");
1671 #else // _LP64
1672 st->print_cr("\tLDUW [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check");
1673 st->print_cr("\tCMP R_G5,R_G3" );
1674 st->print ("\tTne icc,R_G0+ST_RESERVED_FOR_USER_0+2");
1675 #endif // _LP64
1676 }
1677 #endif
1678
1679 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1680 MacroAssembler _masm(&cbuf);
1681 Label L;
1682 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
1683 Register temp_reg = G3;
1684 assert( G5_ic_reg != temp_reg, "conflicting registers" );
1685
1686 // Load klass from receiver
1687 __ load_klass(O0, temp_reg);
1688 // Compare against expected klass
1689 __ cmp(temp_reg, G5_ic_reg);
1690 // Branch to miss code, checks xcc or icc depending
1691 __ trap(Assembler::notEqual, Assembler::ptr_cc, G0, ST_RESERVED_FOR_USER_0+2);
1692 }
1693
1694 uint MachUEPNode::size(PhaseRegAlloc *ra_) const {
1695 return MachNode::size(ra_);
1696 }
1697
1698
1699 //=============================================================================
1700
1701 uint size_exception_handler() {
1702 if (TraceJumps) {
1703 return (400); // just a guess
1704 }
1705 return ( NativeJump::instruction_size ); // sethi;jmp;nop
1706 }
1707
1708 uint size_deopt_handler() {
1709 if (TraceJumps) {
1710 return (400); // just a guess
1711 }
1712 return ( 4+ NativeJump::instruction_size ); // save;sethi;jmp;restore
1713 }
1714
1715 // Emit exception handler code.
1716 int emit_exception_handler(CodeBuffer& cbuf) {
1717 Register temp_reg = G3;
1718 AddressLiteral exception_blob(OptoRuntime::exception_blob()->entry_point());
1719 MacroAssembler _masm(&cbuf);
1720
1721 address base =
1722 __ start_a_stub(size_exception_handler());
1723 if (base == NULL) return 0; // CodeBuffer::expand failed
1724
1725 int offset = __ offset();
1726
1727 __ JUMP(exception_blob, temp_reg, 0); // sethi;jmp
1728 __ delayed()->nop();
1729
1730 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow");
1731
1732 __ end_a_stub();
1733
1734 return offset;
1735 }
1736
1737 int emit_deopt_handler(CodeBuffer& cbuf) {
1738 // Can't use any of the current frame's registers as we may have deopted
1739 // at a poll and everything (including G3) can be live.
1740 Register temp_reg = L0;
1741 AddressLiteral deopt_blob(SharedRuntime::deopt_blob()->unpack());
1742 MacroAssembler _masm(&cbuf);
1743
1744 address base =
1745 __ start_a_stub(size_deopt_handler());
1746 if (base == NULL) return 0; // CodeBuffer::expand failed
1747
1748 int offset = __ offset();
1749 __ save_frame(0);
1750 __ JUMP(deopt_blob, temp_reg, 0); // sethi;jmp
1751 __ delayed()->restore();
1752
1753 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
1754
1755 __ end_a_stub();
1756 return offset;
1757
1758 }
1759
1760 // Given a register encoding, produce a Integer Register object
1761 static Register reg_to_register_object(int register_encoding) {
1762 assert(L5->encoding() == R_L5_enc && G1->encoding() == R_G1_enc, "right coding");
1763 return as_Register(register_encoding);
1764 }
1765
1766 // Given a register encoding, produce a single-precision Float Register object
1767 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding) {
1768 assert(F5->encoding(FloatRegisterImpl::S) == R_F5_enc && F12->encoding(FloatRegisterImpl::S) == R_F12_enc, "right coding");
1769 return as_SingleFloatRegister(register_encoding);
1770 }
1771
1772 // Given a register encoding, produce a double-precision Float Register object
1773 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding) {
1774 assert(F4->encoding(FloatRegisterImpl::D) == R_F4_enc, "right coding");
1775 assert(F32->encoding(FloatRegisterImpl::D) == R_D32_enc, "right coding");
1776 return as_DoubleFloatRegister(register_encoding);
1777 }
1778
1779 const bool Matcher::match_rule_supported(int opcode) {
1780 if (!has_match_rule(opcode))
1781 return false;
1782
1783 switch (opcode) {
1784 case Op_CountLeadingZerosI:
1785 case Op_CountLeadingZerosL:
1786 case Op_CountTrailingZerosI:
1787 case Op_CountTrailingZerosL:
1788 if (!UsePopCountInstruction)
1789 return false;
1790 break;
1791 }
1792
1793 return true; // Per default match rules are supported.
1794 }
1795
1796 int Matcher::regnum_to_fpu_offset(int regnum) {
1797 return regnum - 32; // The FP registers are in the second chunk
1798 }
1799
1800 #ifdef ASSERT
1801 address last_rethrow = NULL; // debugging aid for Rethrow encoding
1802 #endif
1803
1804 // Vector width in bytes
1805 const uint Matcher::vector_width_in_bytes(void) {
1806 return 8;
1807 }
1808
1809 // Vector ideal reg
1810 const uint Matcher::vector_ideal_reg(void) {
1811 return Op_RegD;
1812 }
1813
1814 // USII supports fxtof through the whole range of number, USIII doesn't
1815 const bool Matcher::convL2FSupported(void) {
1816 return VM_Version::has_fast_fxtof();
1817 }
1818
1819 // Is this branch offset short enough that a short branch can be used?
1820 //
1821 // NOTE: If the platform does not provide any short branch variants, then
1822 // this method should return false for offset 0.
1823 bool Matcher::is_short_branch_offset(int rule, int offset) {
1824 return false;
1825 }
1826
1827 const bool Matcher::isSimpleConstant64(jlong value) {
1828 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
1829 // Depends on optimizations in MacroAssembler::setx.
1830 int hi = (int)(value >> 32);
1831 int lo = (int)(value & ~0);
1832 return (hi == 0) || (hi == -1) || (lo == 0);
1833 }
1834
1835 // No scaling for the parameter the ClearArray node.
1836 const bool Matcher::init_array_count_is_in_bytes = true;
1837
1838 // Threshold size for cleararray.
1839 const int Matcher::init_array_short_size = 8 * BytesPerLong;
1840
1841 // Should the Matcher clone shifts on addressing modes, expecting them to
1842 // be subsumed into complex addressing expressions or compute them into
1843 // registers? True for Intel but false for most RISCs
1844 const bool Matcher::clone_shift_expressions = false;
1845
1846 // Do we need to mask the count passed to shift instructions or does
1847 // the cpu only look at the lower 5/6 bits anyway?
1848 const bool Matcher::need_masked_shift_count = false;
1849
1850 bool Matcher::narrow_oop_use_complex_address() {
1851 NOT_LP64(ShouldNotCallThis());
1852 assert(UseCompressedOops, "only for compressed oops code");
1853 return false;
1854 }
1855
1856 // Is it better to copy float constants, or load them directly from memory?
1857 // Intel can load a float constant from a direct address, requiring no
1858 // extra registers. Most RISCs will have to materialize an address into a
1859 // register first, so they would do better to copy the constant from stack.
1860 const bool Matcher::rematerialize_float_constants = false;
1861
1862 // If CPU can load and store mis-aligned doubles directly then no fixup is
1863 // needed. Else we split the double into 2 integer pieces and move it
1864 // piece-by-piece. Only happens when passing doubles into C code as the
1865 // Java calling convention forces doubles to be aligned.
1866 #ifdef _LP64
1867 const bool Matcher::misaligned_doubles_ok = true;
1868 #else
1869 const bool Matcher::misaligned_doubles_ok = false;
1870 #endif
1871
1872 // No-op on SPARC.
1873 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {
1874 }
1875
1876 // Advertise here if the CPU requires explicit rounding operations
1877 // to implement the UseStrictFP mode.
1878 const bool Matcher::strict_fp_requires_explicit_rounding = false;
1879
1880 // Are floats conerted to double when stored to stack during deoptimization?
1881 // Sparc does not handle callee-save floats.
1882 bool Matcher::float_in_double() { return false; }
1883
1884 // Do ints take an entire long register or just half?
1885 // Note that we if-def off of _LP64.
1886 // The relevant question is how the int is callee-saved. In _LP64
1887 // the whole long is written but de-opt'ing will have to extract
1888 // the relevant 32 bits, in not-_LP64 only the low 32 bits is written.
1889 #ifdef _LP64
1890 const bool Matcher::int_in_long = true;
1891 #else
1892 const bool Matcher::int_in_long = false;
1893 #endif
1894
1895 // Return whether or not this register is ever used as an argument. This
1896 // function is used on startup to build the trampoline stubs in generateOptoStub.
1897 // Registers not mentioned will be killed by the VM call in the trampoline, and
1898 // arguments in those registers not be available to the callee.
1899 bool Matcher::can_be_java_arg( int reg ) {
1900 // Standard sparc 6 args in registers
1901 if( reg == R_I0_num ||
1902 reg == R_I1_num ||
1903 reg == R_I2_num ||
1904 reg == R_I3_num ||
1905 reg == R_I4_num ||
1906 reg == R_I5_num ) return true;
1907 #ifdef _LP64
1908 // 64-bit builds can pass 64-bit pointers and longs in
1909 // the high I registers
1910 if( reg == R_I0H_num ||
1911 reg == R_I1H_num ||
1912 reg == R_I2H_num ||
1913 reg == R_I3H_num ||
1914 reg == R_I4H_num ||
1915 reg == R_I5H_num ) return true;
1916
1917 if ((UseCompressedOops) && (reg == R_G6_num || reg == R_G6H_num)) {
1918 return true;
1919 }
1920
1921 #else
1922 // 32-bit builds with longs-in-one-entry pass longs in G1 & G4.
1923 // Longs cannot be passed in O regs, because O regs become I regs
1924 // after a 'save' and I regs get their high bits chopped off on
1925 // interrupt.
1926 if( reg == R_G1H_num || reg == R_G1_num ) return true;
1927 if( reg == R_G4H_num || reg == R_G4_num ) return true;
1928 #endif
1929 // A few float args in registers
1930 if( reg >= R_F0_num && reg <= R_F7_num ) return true;
1931
1932 return false;
1933 }
1934
1935 bool Matcher::is_spillable_arg( int reg ) {
1936 return can_be_java_arg(reg);
1937 }
1938
1939 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) {
1940 // Use hardware SDIVX instruction when it is
1941 // faster than a code which use multiply.
1942 return VM_Version::has_fast_idiv();
1943 }
1944
1945 // Register for DIVI projection of divmodI
1946 RegMask Matcher::divI_proj_mask() {
1947 ShouldNotReachHere();
1948 return RegMask();
1949 }
1950
1951 // Register for MODI projection of divmodI
1952 RegMask Matcher::modI_proj_mask() {
1953 ShouldNotReachHere();
1954 return RegMask();
1955 }
1956
1957 // Register for DIVL projection of divmodL
1958 RegMask Matcher::divL_proj_mask() {
1959 ShouldNotReachHere();
1960 return RegMask();
1961 }
1962
1963 // Register for MODL projection of divmodL
1964 RegMask Matcher::modL_proj_mask() {
1965 ShouldNotReachHere();
1966 return RegMask();
1967 }
1968
1969 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
1970 return L7_REGP_mask;
1971 }
1972
1973 %}
1974
1975
1976 // The intptr_t operand types, defined by textual substitution.
1977 // (Cf. opto/type.hpp. This lets us avoid many, many other ifdefs.)
1978 #ifdef _LP64
1979 #define immX immL
1980 #define immX13 immL13
1981 #define immX13m7 immL13m7
1982 #define iRegX iRegL
1983 #define g1RegX g1RegL
1984 #else
1985 #define immX immI
1986 #define immX13 immI13
1987 #define immX13m7 immI13m7
1988 #define iRegX iRegI
1989 #define g1RegX g1RegI
1990 #endif
1991
1992 //----------ENCODING BLOCK-----------------------------------------------------
1993 // This block specifies the encoding classes used by the compiler to output
1994 // byte streams. Encoding classes are parameterized macros used by
1995 // Machine Instruction Nodes in order to generate the bit encoding of the
1996 // instruction. Operands specify their base encoding interface with the
1997 // interface keyword. There are currently supported four interfaces,
1998 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an
1999 // operand to generate a function which returns its register number when
2000 // queried. CONST_INTER causes an operand to generate a function which
2001 // returns the value of the constant when queried. MEMORY_INTER causes an
2002 // operand to generate four functions which return the Base Register, the
2003 // Index Register, the Scale Value, and the Offset Value of the operand when
2004 // queried. COND_INTER causes an operand to generate six functions which
2005 // return the encoding code (ie - encoding bits for the instruction)
2006 // associated with each basic boolean condition for a conditional instruction.
2007 //
2008 // Instructions specify two basic values for encoding. Again, a function
2009 // is available to check if the constant displacement is an oop. They use the
2010 // ins_encode keyword to specify their encoding classes (which must be
2011 // a sequence of enc_class names, and their parameters, specified in
2012 // the encoding block), and they use the
2013 // opcode keyword to specify, in order, their primary, secondary, and
2014 // tertiary opcode. Only the opcode sections which a particular instruction
2015 // needs for encoding need to be specified.
2016 encode %{
2017 enc_class enc_untested %{
2018 #ifdef ASSERT
2019 MacroAssembler _masm(&cbuf);
2020 __ untested("encoding");
2021 #endif
2022 %}
2023
2024 enc_class form3_mem_reg( memory mem, iRegI dst ) %{
2025 emit_form3_mem_reg(cbuf, this, $primary, $tertiary,
2026 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg);
2027 %}
2028
2029 enc_class simple_form3_mem_reg( memory mem, iRegI dst ) %{
2030 emit_form3_mem_reg(cbuf, this, $primary, -1,
2031 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg);
2032 %}
2033
2034 enc_class form3_mem_prefetch_read( memory mem ) %{
2035 emit_form3_mem_reg(cbuf, this, $primary, -1,
2036 $mem$$base, $mem$$disp, $mem$$index, 0/*prefetch function many-reads*/);
2037 %}
2038
2039 enc_class form3_mem_prefetch_write( memory mem ) %{
2040 emit_form3_mem_reg(cbuf, this, $primary, -1,
2041 $mem$$base, $mem$$disp, $mem$$index, 2/*prefetch function many-writes*/);
2042 %}
2043
2044 enc_class form3_mem_reg_long_unaligned_marshal( memory mem, iRegL reg ) %{
2045 assert( Assembler::is_simm13($mem$$disp ), "need disp and disp+4" );
2046 assert( Assembler::is_simm13($mem$$disp+4), "need disp and disp+4" );
2047 guarantee($mem$$index == R_G0_enc, "double index?");
2048 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, R_O7_enc );
2049 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg );
2050 emit3_simm13( cbuf, Assembler::arith_op, $reg$$reg, Assembler::sllx_op3, $reg$$reg, 0x1020 );
2051 emit3( cbuf, Assembler::arith_op, $reg$$reg, Assembler::or_op3, $reg$$reg, 0, R_O7_enc );
2052 %}
2053
2054 enc_class form3_mem_reg_double_unaligned( memory mem, RegD_low reg ) %{
2055 assert( Assembler::is_simm13($mem$$disp ), "need disp and disp+4" );
2056 assert( Assembler::is_simm13($mem$$disp+4), "need disp and disp+4" );
2057 guarantee($mem$$index == R_G0_enc, "double index?");
2058 // Load long with 2 instructions
2059 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg+0 );
2060 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, $reg$$reg+1 );
2061 %}
2062
2063 //%%% form3_mem_plus_4_reg is a hack--get rid of it
2064 enc_class form3_mem_plus_4_reg( memory mem, iRegI dst ) %{
2065 guarantee($mem$$disp, "cannot offset a reg-reg operand by 4");
2066 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp + 4, $mem$$index, $dst$$reg);
2067 %}
2068
2069 enc_class form3_g0_rs2_rd_move( iRegI rs2, iRegI rd ) %{
2070 // Encode a reg-reg copy. If it is useless, then empty encoding.
2071 if( $rs2$$reg != $rd$$reg )
2072 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, $rs2$$reg );
2073 %}
2074
2075 // Target lo half of long
2076 enc_class form3_g0_rs2_rd_move_lo( iRegI rs2, iRegL rd ) %{
2077 // Encode a reg-reg copy. If it is useless, then empty encoding.
2078 if( $rs2$$reg != LONG_LO_REG($rd$$reg) )
2079 emit3( cbuf, Assembler::arith_op, LONG_LO_REG($rd$$reg), Assembler::or_op3, 0, 0, $rs2$$reg );
2080 %}
2081
2082 // Source lo half of long
2083 enc_class form3_g0_rs2_rd_move_lo2( iRegL rs2, iRegI rd ) %{
2084 // Encode a reg-reg copy. If it is useless, then empty encoding.
2085 if( LONG_LO_REG($rs2$$reg) != $rd$$reg )
2086 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_LO_REG($rs2$$reg) );
2087 %}
2088
2089 // Target hi half of long
2090 enc_class form3_rs1_rd_copysign_hi( iRegI rs1, iRegL rd ) %{
2091 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 31 );
2092 %}
2093
2094 // Source lo half of long, and leave it sign extended.
2095 enc_class form3_rs1_rd_signextend_lo1( iRegL rs1, iRegI rd ) %{
2096 // Sign extend low half
2097 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 0, 0 );
2098 %}
2099
2100 // Source hi half of long, and leave it sign extended.
2101 enc_class form3_rs1_rd_copy_hi1( iRegL rs1, iRegI rd ) %{
2102 // Shift high half to low half
2103 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::srlx_op3, $rs1$$reg, 32 );
2104 %}
2105
2106 // Source hi half of long
2107 enc_class form3_g0_rs2_rd_move_hi2( iRegL rs2, iRegI rd ) %{
2108 // Encode a reg-reg copy. If it is useless, then empty encoding.
2109 if( LONG_HI_REG($rs2$$reg) != $rd$$reg )
2110 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_HI_REG($rs2$$reg) );
2111 %}
2112
2113 enc_class form3_rs1_rs2_rd( iRegI rs1, iRegI rs2, iRegI rd ) %{
2114 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0, $rs2$$reg );
2115 %}
2116
2117 enc_class enc_to_bool( iRegI src, iRegI dst ) %{
2118 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, 0, 0, $src$$reg );
2119 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::addc_op3 , 0, 0 );
2120 %}
2121
2122 enc_class enc_ltmask( iRegI p, iRegI q, iRegI dst ) %{
2123 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $p$$reg, 0, $q$$reg );
2124 // clear if nothing else is happening
2125 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 0 );
2126 // blt,a,pn done
2127 emit2_19 ( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less, Assembler::bp_op2, Assembler::icc, 0/*predict not taken*/, 2 );
2128 // mov dst,-1 in delay slot
2129 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 );
2130 %}
2131
2132 enc_class form3_rs1_imm5_rd( iRegI rs1, immU5 imm5, iRegI rd ) %{
2133 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $imm5$$constant & 0x1F );
2134 %}
2135
2136 enc_class form3_sd_rs1_imm6_rd( iRegL rs1, immU6 imm6, iRegL rd ) %{
2137 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, ($imm6$$constant & 0x3F) | 0x1000 );
2138 %}
2139
2140 enc_class form3_sd_rs1_rs2_rd( iRegL rs1, iRegI rs2, iRegL rd ) %{
2141 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0x80, $rs2$$reg );
2142 %}
2143
2144 enc_class form3_rs1_simm13_rd( iRegI rs1, immI13 simm13, iRegI rd ) %{
2145 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $simm13$$constant );
2146 %}
2147
2148 enc_class move_return_pc_to_o1() %{
2149 emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::add_op3, R_O7_enc, frame::pc_return_offset );
2150 %}
2151
2152 #ifdef _LP64
2153 /* %%% merge with enc_to_bool */
2154 enc_class enc_convP2B( iRegI dst, iRegP src ) %{
2155 MacroAssembler _masm(&cbuf);
2156
2157 Register src_reg = reg_to_register_object($src$$reg);
2158 Register dst_reg = reg_to_register_object($dst$$reg);
2159 __ movr(Assembler::rc_nz, src_reg, 1, dst_reg);
2160 %}
2161 #endif
2162
2163 enc_class enc_cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp ) %{
2164 // (Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)))
2165 MacroAssembler _masm(&cbuf);
2166
2167 Register p_reg = reg_to_register_object($p$$reg);
2168 Register q_reg = reg_to_register_object($q$$reg);
2169 Register y_reg = reg_to_register_object($y$$reg);
2170 Register tmp_reg = reg_to_register_object($tmp$$reg);
2171
2172 __ subcc( p_reg, q_reg, p_reg );
2173 __ add ( p_reg, y_reg, tmp_reg );
2174 __ movcc( Assembler::less, false, Assembler::icc, tmp_reg, p_reg );
2175 %}
2176
2177 enc_class form_d2i_helper(regD src, regF dst) %{
2178 // fcmp %fcc0,$src,$src
2179 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg );
2180 // branch %fcc0 not-nan, predict taken
2181 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2182 // fdtoi $src,$dst
2183 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtoi_opf, $src$$reg );
2184 // fitos $dst,$dst (if nan)
2185 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg );
2186 // clear $dst (if nan)
2187 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg );
2188 // carry on here...
2189 %}
2190
2191 enc_class form_d2l_helper(regD src, regD dst) %{
2192 // fcmp %fcc0,$src,$src check for NAN
2193 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg );
2194 // branch %fcc0 not-nan, predict taken
2195 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2196 // fdtox $src,$dst convert in delay slot
2197 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtox_opf, $src$$reg );
2198 // fxtod $dst,$dst (if nan)
2199 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg );
2200 // clear $dst (if nan)
2201 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg );
2202 // carry on here...
2203 %}
2204
2205 enc_class form_f2i_helper(regF src, regF dst) %{
2206 // fcmps %fcc0,$src,$src
2207 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg );
2208 // branch %fcc0 not-nan, predict taken
2209 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2210 // fstoi $src,$dst
2211 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstoi_opf, $src$$reg );
2212 // fitos $dst,$dst (if nan)
2213 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg );
2214 // clear $dst (if nan)
2215 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg );
2216 // carry on here...
2217 %}
2218
2219 enc_class form_f2l_helper(regF src, regD dst) %{
2220 // fcmps %fcc0,$src,$src
2221 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg );
2222 // branch %fcc0 not-nan, predict taken
2223 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2224 // fstox $src,$dst
2225 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstox_opf, $src$$reg );
2226 // fxtod $dst,$dst (if nan)
2227 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg );
2228 // clear $dst (if nan)
2229 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg );
2230 // carry on here...
2231 %}
2232
2233 enc_class form3_opf_rs2F_rdF(regF rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2234 enc_class form3_opf_rs2F_rdD(regF rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2235 enc_class form3_opf_rs2D_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2236 enc_class form3_opf_rs2D_rdD(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2237
2238 enc_class form3_opf_rs2D_lo_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg+1); %}
2239
2240 enc_class form3_opf_rs2D_hi_rdD_hi(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2241 enc_class form3_opf_rs2D_lo_rdD_lo(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg+1,$primary,0,$tertiary,$rs2$$reg+1); %}
2242
2243 enc_class form3_opf_rs1F_rs2F_rdF( regF rs1, regF rs2, regF rd ) %{
2244 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2245 %}
2246
2247 enc_class form3_opf_rs1D_rs2D_rdD( regD rs1, regD rs2, regD rd ) %{
2248 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2249 %}
2250
2251 enc_class form3_opf_rs1F_rs2F_fcc( regF rs1, regF rs2, flagsRegF fcc ) %{
2252 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2253 %}
2254
2255 enc_class form3_opf_rs1D_rs2D_fcc( regD rs1, regD rs2, flagsRegF fcc ) %{
2256 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2257 %}
2258
2259 enc_class form3_convI2F(regF rs2, regF rd) %{
2260 emit3(cbuf,Assembler::arith_op,$rd$$reg,Assembler::fpop1_op3,0,$secondary,$rs2$$reg);
2261 %}
2262
2263 // Encloding class for traceable jumps
2264 enc_class form_jmpl(g3RegP dest) %{
2265 emit_jmpl(cbuf, $dest$$reg);
2266 %}
2267
2268 enc_class form_jmpl_set_exception_pc(g1RegP dest) %{
2269 emit_jmpl_set_exception_pc(cbuf, $dest$$reg);
2270 %}
2271
2272 enc_class form2_nop() %{
2273 emit_nop(cbuf);
2274 %}
2275
2276 enc_class form2_illtrap() %{
2277 emit_illtrap(cbuf);
2278 %}
2279
2280
2281 // Compare longs and convert into -1, 0, 1.
2282 enc_class cmpl_flag( iRegL src1, iRegL src2, iRegI dst ) %{
2283 // CMP $src1,$src2
2284 emit3( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $src1$$reg, 0, $src2$$reg );
2285 // blt,a,pn done
2286 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less , Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 5 );
2287 // mov dst,-1 in delay slot
2288 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 );
2289 // bgt,a,pn done
2290 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::greater, Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 3 );
2291 // mov dst,1 in delay slot
2292 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 1 );
2293 // CLR $dst
2294 emit3( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3 , 0, 0, 0 );
2295 %}
2296
2297 enc_class enc_PartialSubtypeCheck() %{
2298 MacroAssembler _masm(&cbuf);
2299 __ call(StubRoutines::Sparc::partial_subtype_check(), relocInfo::runtime_call_type);
2300 __ delayed()->nop();
2301 %}
2302
2303 enc_class enc_bp( Label labl, cmpOp cmp, flagsReg cc ) %{
2304 MacroAssembler _masm(&cbuf);
2305 Label &L = *($labl$$label);
2306 Assembler::Predict predict_taken =
2307 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn;
2308
2309 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, L);
2310 __ delayed()->nop();
2311 %}
2312
2313 enc_class enc_bpl( Label labl, cmpOp cmp, flagsRegL cc ) %{
2314 MacroAssembler _masm(&cbuf);
2315 Label &L = *($labl$$label);
2316 Assembler::Predict predict_taken =
2317 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn;
2318
2319 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, L);
2320 __ delayed()->nop();
2321 %}
2322
2323 enc_class enc_bpx( Label labl, cmpOp cmp, flagsRegP cc ) %{
2324 MacroAssembler _masm(&cbuf);
2325 Label &L = *($labl$$label);
2326 Assembler::Predict predict_taken =
2327 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn;
2328
2329 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, L);
2330 __ delayed()->nop();
2331 %}
2332
2333 enc_class enc_fbp( Label labl, cmpOpF cmp, flagsRegF cc ) %{
2334 MacroAssembler _masm(&cbuf);
2335 Label &L = *($labl$$label);
2336 Assembler::Predict predict_taken =
2337 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn;
2338
2339 __ fbp( (Assembler::Condition)($cmp$$cmpcode), false, (Assembler::CC)($cc$$reg), predict_taken, L);
2340 __ delayed()->nop();
2341 %}
2342
2343 enc_class enc_ba( Label labl ) %{
2344 MacroAssembler _masm(&cbuf);
2345 Label &L = *($labl$$label);
2346 __ ba(false, L);
2347 __ delayed()->nop();
2348 %}
2349
2350 enc_class enc_bpr( Label labl, cmpOp_reg cmp, iRegI op1 ) %{
2351 MacroAssembler _masm(&cbuf);
2352 Label &L = *$labl$$label;
2353 Assembler::Predict predict_taken =
2354 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn;
2355
2356 __ bpr( (Assembler::RCondition)($cmp$$cmpcode), false, predict_taken, as_Register($op1$$reg), L);
2357 __ delayed()->nop();
2358 %}
2359
2360 enc_class enc_cmov_reg( cmpOp cmp, iRegI dst, iRegI src, immI pcc) %{
2361 int op = (Assembler::arith_op << 30) |
2362 ($dst$$reg << 25) |
2363 (Assembler::movcc_op3 << 19) |
2364 (1 << 18) | // cc2 bit for 'icc'
2365 ($cmp$$cmpcode << 14) |
2366 (0 << 13) | // select register move
2367 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc' or 'xcc'
2368 ($src$$reg << 0);
2369 cbuf.insts()->emit_int32(op);
2370 %}
2371
2372 enc_class enc_cmov_imm( cmpOp cmp, iRegI dst, immI11 src, immI pcc ) %{
2373 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits
2374 int op = (Assembler::arith_op << 30) |
2375 ($dst$$reg << 25) |
2376 (Assembler::movcc_op3 << 19) |
2377 (1 << 18) | // cc2 bit for 'icc'
2378 ($cmp$$cmpcode << 14) |
2379 (1 << 13) | // select immediate move
2380 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc'
2381 (simm11 << 0);
2382 cbuf.insts()->emit_int32(op);
2383 %}
2384
2385 enc_class enc_cmov_reg_f( cmpOpF cmp, iRegI dst, iRegI src, flagsRegF fcc ) %{
2386 int op = (Assembler::arith_op << 30) |
2387 ($dst$$reg << 25) |
2388 (Assembler::movcc_op3 << 19) |
2389 (0 << 18) | // cc2 bit for 'fccX'
2390 ($cmp$$cmpcode << 14) |
2391 (0 << 13) | // select register move
2392 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3
2393 ($src$$reg << 0);
2394 cbuf.insts()->emit_int32(op);
2395 %}
2396
2397 enc_class enc_cmov_imm_f( cmpOp cmp, iRegI dst, immI11 src, flagsRegF fcc ) %{
2398 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits
2399 int op = (Assembler::arith_op << 30) |
2400 ($dst$$reg << 25) |
2401 (Assembler::movcc_op3 << 19) |
2402 (0 << 18) | // cc2 bit for 'fccX'
2403 ($cmp$$cmpcode << 14) |
2404 (1 << 13) | // select immediate move
2405 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3
2406 (simm11 << 0);
2407 cbuf.insts()->emit_int32(op);
2408 %}
2409
2410 enc_class enc_cmovf_reg( cmpOp cmp, regD dst, regD src, immI pcc ) %{
2411 int op = (Assembler::arith_op << 30) |
2412 ($dst$$reg << 25) |
2413 (Assembler::fpop2_op3 << 19) |
2414 (0 << 18) |
2415 ($cmp$$cmpcode << 14) |
2416 (1 << 13) | // select register move
2417 ($pcc$$constant << 11) | // cc1-cc0 bits for 'icc' or 'xcc'
2418 ($primary << 5) | // select single, double or quad
2419 ($src$$reg << 0);
2420 cbuf.insts()->emit_int32(op);
2421 %}
2422
2423 enc_class enc_cmovff_reg( cmpOpF cmp, flagsRegF fcc, regD dst, regD src ) %{
2424 int op = (Assembler::arith_op << 30) |
2425 ($dst$$reg << 25) |
2426 (Assembler::fpop2_op3 << 19) |
2427 (0 << 18) |
2428 ($cmp$$cmpcode << 14) |
2429 ($fcc$$reg << 11) | // cc2-cc0 bits for 'fccX'
2430 ($primary << 5) | // select single, double or quad
2431 ($src$$reg << 0);
2432 cbuf.insts()->emit_int32(op);
2433 %}
2434
2435 // Used by the MIN/MAX encodings. Same as a CMOV, but
2436 // the condition comes from opcode-field instead of an argument.
2437 enc_class enc_cmov_reg_minmax( iRegI dst, iRegI src ) %{
2438 int op = (Assembler::arith_op << 30) |
2439 ($dst$$reg << 25) |
2440 (Assembler::movcc_op3 << 19) |
2441 (1 << 18) | // cc2 bit for 'icc'
2442 ($primary << 14) |
2443 (0 << 13) | // select register move
2444 (0 << 11) | // cc1, cc0 bits for 'icc'
2445 ($src$$reg << 0);
2446 cbuf.insts()->emit_int32(op);
2447 %}
2448
2449 enc_class enc_cmov_reg_minmax_long( iRegL dst, iRegL src ) %{
2450 int op = (Assembler::arith_op << 30) |
2451 ($dst$$reg << 25) |
2452 (Assembler::movcc_op3 << 19) |
2453 (6 << 16) | // cc2 bit for 'xcc'
2454 ($primary << 14) |
2455 (0 << 13) | // select register move
2456 (0 << 11) | // cc1, cc0 bits for 'icc'
2457 ($src$$reg << 0);
2458 cbuf.insts()->emit_int32(op);
2459 %}
2460
2461 enc_class Set13( immI13 src, iRegI rd ) %{
2462 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, $src$$constant );
2463 %}
2464
2465 enc_class SetHi22( immI src, iRegI rd ) %{
2466 emit2_22( cbuf, Assembler::branch_op, $rd$$reg, Assembler::sethi_op2, $src$$constant );
2467 %}
2468
2469 enc_class Set32( immI src, iRegI rd ) %{
2470 MacroAssembler _masm(&cbuf);
2471 __ set($src$$constant, reg_to_register_object($rd$$reg));
2472 %}
2473
2474 enc_class call_epilog %{
2475 if( VerifyStackAtCalls ) {
2476 MacroAssembler _masm(&cbuf);
2477 int framesize = ra_->C->frame_slots() << LogBytesPerInt;
2478 Register temp_reg = G3;
2479 __ add(SP, framesize, temp_reg);
2480 __ cmp(temp_reg, FP);
2481 __ breakpoint_trap(Assembler::notEqual, Assembler::ptr_cc);
2482 }
2483 %}
2484
2485 // Long values come back from native calls in O0:O1 in the 32-bit VM, copy the value
2486 // to G1 so the register allocator will not have to deal with the misaligned register
2487 // pair.
2488 enc_class adjust_long_from_native_call %{
2489 #ifndef _LP64
2490 if (returns_long()) {
2491 // sllx O0,32,O0
2492 emit3_simm13( cbuf, Assembler::arith_op, R_O0_enc, Assembler::sllx_op3, R_O0_enc, 0x1020 );
2493 // srl O1,0,O1
2494 emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::srl_op3, R_O1_enc, 0x0000 );
2495 // or O0,O1,G1
2496 emit3 ( cbuf, Assembler::arith_op, R_G1_enc, Assembler:: or_op3, R_O0_enc, 0, R_O1_enc );
2497 }
2498 #endif
2499 %}
2500
2501 enc_class Java_To_Runtime (method meth) %{ // CALL Java_To_Runtime
2502 // CALL directly to the runtime
2503 // The user of this is responsible for ensuring that R_L7 is empty (killed).
2504 emit_call_reloc(cbuf, $meth$$method, relocInfo::runtime_call_type,
2505 /*preserve_g2=*/true);
2506 %}
2507
2508 enc_class preserve_SP %{
2509 MacroAssembler _masm(&cbuf);
2510 __ mov(SP, L7_mh_SP_save);
2511 %}
2512
2513 enc_class restore_SP %{
2514 MacroAssembler _masm(&cbuf);
2515 __ mov(L7_mh_SP_save, SP);
2516 %}
2517
2518 enc_class Java_Static_Call (method meth) %{ // JAVA STATIC CALL
2519 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
2520 // who we intended to call.
2521 if ( !_method ) {
2522 emit_call_reloc(cbuf, $meth$$method, relocInfo::runtime_call_type);
2523 } else if (_optimized_virtual) {
2524 emit_call_reloc(cbuf, $meth$$method, relocInfo::opt_virtual_call_type);
2525 } else {
2526 emit_call_reloc(cbuf, $meth$$method, relocInfo::static_call_type);
2527 }
2528 if( _method ) { // Emit stub for static call
2529 emit_java_to_interp(cbuf);
2530 }
2531 %}
2532
2533 enc_class Java_Dynamic_Call (method meth) %{ // JAVA DYNAMIC CALL
2534 MacroAssembler _masm(&cbuf);
2535 __ set_inst_mark();
2536 int vtable_index = this->_vtable_index;
2537 // MachCallDynamicJavaNode::ret_addr_offset uses this same test
2538 if (vtable_index < 0) {
2539 // must be invalid_vtable_index, not nonvirtual_vtable_index
2540 assert(vtable_index == methodOopDesc::invalid_vtable_index, "correct sentinel value");
2541 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
2542 assert(G5_ic_reg == G5_inline_cache_reg, "G5_inline_cache_reg used in assemble_ic_buffer_code()");
2543 assert(G5_ic_reg == G5_megamorphic_method, "G5_megamorphic_method used in megamorphic call stub");
2544 // !!!!!
2545 // Generate "set 0x01, R_G5", placeholder instruction to load oop-info
2546 // emit_call_dynamic_prologue( cbuf );
2547 __ set_oop((jobject)Universe::non_oop_word(), G5_ic_reg);
2548
2549 address virtual_call_oop_addr = __ inst_mark();
2550 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
2551 // who we intended to call.
2552 __ relocate(virtual_call_Relocation::spec(virtual_call_oop_addr));
2553 emit_call_reloc(cbuf, $meth$$method, relocInfo::none);
2554 } else {
2555 assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
2556 // Just go thru the vtable
2557 // get receiver klass (receiver already checked for non-null)
2558 // If we end up going thru a c2i adapter interpreter expects method in G5
2559 int off = __ offset();
2560 __ load_klass(O0, G3_scratch);
2561 int klass_load_size;
2562 if (UseCompressedOops) {
2563 assert(Universe::heap() != NULL, "java heap should be initialized");
2564 if (Universe::narrow_oop_base() == NULL)
2565 klass_load_size = 2*BytesPerInstWord;
2566 else
2567 klass_load_size = 3*BytesPerInstWord;
2568 } else {
2569 klass_load_size = 1*BytesPerInstWord;
2570 }
2571 int entry_offset = instanceKlass::vtable_start_offset() + vtable_index*vtableEntry::size();
2572 int v_off = entry_offset*wordSize + vtableEntry::method_offset_in_bytes();
2573 if( __ is_simm13(v_off) ) {
2574 __ ld_ptr(G3, v_off, G5_method);
2575 } else {
2576 // Generate 2 instructions
2577 __ Assembler::sethi(v_off & ~0x3ff, G5_method);
2578 __ or3(G5_method, v_off & 0x3ff, G5_method);
2579 // ld_ptr, set_hi, set
2580 assert(__ offset() - off == klass_load_size + 2*BytesPerInstWord,
2581 "Unexpected instruction size(s)");
2582 __ ld_ptr(G3, G5_method, G5_method);
2583 }
2584 // NOTE: for vtable dispatches, the vtable entry will never be null.
2585 // However it may very well end up in handle_wrong_method if the
2586 // method is abstract for the particular class.
2587 __ ld_ptr(G5_method, in_bytes(methodOopDesc::from_compiled_offset()), G3_scratch);
2588 // jump to target (either compiled code or c2iadapter)
2589 __ jmpl(G3_scratch, G0, O7);
2590 __ delayed()->nop();
2591 }
2592 %}
2593
2594 enc_class Java_Compiled_Call (method meth) %{ // JAVA COMPILED CALL
2595 MacroAssembler _masm(&cbuf);
2596
2597 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
2598 Register temp_reg = G3; // caller must kill G3! We cannot reuse G5_ic_reg here because
2599 // we might be calling a C2I adapter which needs it.
2600
2601 assert(temp_reg != G5_ic_reg, "conflicting registers");
2602 // Load nmethod
2603 __ ld_ptr(G5_ic_reg, in_bytes(methodOopDesc::from_compiled_offset()), temp_reg);
2604
2605 // CALL to compiled java, indirect the contents of G3
2606 __ set_inst_mark();
2607 __ callr(temp_reg, G0);
2608 __ delayed()->nop();
2609 %}
2610
2611 enc_class idiv_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst) %{
2612 MacroAssembler _masm(&cbuf);
2613 Register Rdividend = reg_to_register_object($src1$$reg);
2614 Register Rdivisor = reg_to_register_object($src2$$reg);
2615 Register Rresult = reg_to_register_object($dst$$reg);
2616
2617 __ sra(Rdivisor, 0, Rdivisor);
2618 __ sra(Rdividend, 0, Rdividend);
2619 __ sdivx(Rdividend, Rdivisor, Rresult);
2620 %}
2621
2622 enc_class idiv_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst) %{
2623 MacroAssembler _masm(&cbuf);
2624
2625 Register Rdividend = reg_to_register_object($src1$$reg);
2626 int divisor = $imm$$constant;
2627 Register Rresult = reg_to_register_object($dst$$reg);
2628
2629 __ sra(Rdividend, 0, Rdividend);
2630 __ sdivx(Rdividend, divisor, Rresult);
2631 %}
2632
2633 enc_class enc_mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2) %{
2634 MacroAssembler _masm(&cbuf);
2635 Register Rsrc1 = reg_to_register_object($src1$$reg);
2636 Register Rsrc2 = reg_to_register_object($src2$$reg);
2637 Register Rdst = reg_to_register_object($dst$$reg);
2638
2639 __ sra( Rsrc1, 0, Rsrc1 );
2640 __ sra( Rsrc2, 0, Rsrc2 );
2641 __ mulx( Rsrc1, Rsrc2, Rdst );
2642 __ srlx( Rdst, 32, Rdst );
2643 %}
2644
2645 enc_class irem_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst, o7RegL scratch) %{
2646 MacroAssembler _masm(&cbuf);
2647 Register Rdividend = reg_to_register_object($src1$$reg);
2648 Register Rdivisor = reg_to_register_object($src2$$reg);
2649 Register Rresult = reg_to_register_object($dst$$reg);
2650 Register Rscratch = reg_to_register_object($scratch$$reg);
2651
2652 assert(Rdividend != Rscratch, "");
2653 assert(Rdivisor != Rscratch, "");
2654
2655 __ sra(Rdividend, 0, Rdividend);
2656 __ sra(Rdivisor, 0, Rdivisor);
2657 __ sdivx(Rdividend, Rdivisor, Rscratch);
2658 __ mulx(Rscratch, Rdivisor, Rscratch);
2659 __ sub(Rdividend, Rscratch, Rresult);
2660 %}
2661
2662 enc_class irem_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst, o7RegL scratch) %{
2663 MacroAssembler _masm(&cbuf);
2664
2665 Register Rdividend = reg_to_register_object($src1$$reg);
2666 int divisor = $imm$$constant;
2667 Register Rresult = reg_to_register_object($dst$$reg);
2668 Register Rscratch = reg_to_register_object($scratch$$reg);
2669
2670 assert(Rdividend != Rscratch, "");
2671
2672 __ sra(Rdividend, 0, Rdividend);
2673 __ sdivx(Rdividend, divisor, Rscratch);
2674 __ mulx(Rscratch, divisor, Rscratch);
2675 __ sub(Rdividend, Rscratch, Rresult);
2676 %}
2677
2678 enc_class fabss (sflt_reg dst, sflt_reg src) %{
2679 MacroAssembler _masm(&cbuf);
2680
2681 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
2682 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
2683
2684 __ fabs(FloatRegisterImpl::S, Fsrc, Fdst);
2685 %}
2686
2687 enc_class fabsd (dflt_reg dst, dflt_reg src) %{
2688 MacroAssembler _masm(&cbuf);
2689
2690 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2691 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2692
2693 __ fabs(FloatRegisterImpl::D, Fsrc, Fdst);
2694 %}
2695
2696 enc_class fnegd (dflt_reg dst, dflt_reg src) %{
2697 MacroAssembler _masm(&cbuf);
2698
2699 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2700 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2701
2702 __ fneg(FloatRegisterImpl::D, Fsrc, Fdst);
2703 %}
2704
2705 enc_class fsqrts (sflt_reg dst, sflt_reg src) %{
2706 MacroAssembler _masm(&cbuf);
2707
2708 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
2709 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
2710
2711 __ fsqrt(FloatRegisterImpl::S, Fsrc, Fdst);
2712 %}
2713
2714 enc_class fsqrtd (dflt_reg dst, dflt_reg src) %{
2715 MacroAssembler _masm(&cbuf);
2716
2717 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2718 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2719
2720 __ fsqrt(FloatRegisterImpl::D, Fsrc, Fdst);
2721 %}
2722
2723 enc_class fmovs (dflt_reg dst, dflt_reg src) %{
2724 MacroAssembler _masm(&cbuf);
2725
2726 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
2727 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
2728
2729 __ fmov(FloatRegisterImpl::S, Fsrc, Fdst);
2730 %}
2731
2732 enc_class fmovd (dflt_reg dst, dflt_reg src) %{
2733 MacroAssembler _masm(&cbuf);
2734
2735 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2736 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2737
2738 __ fmov(FloatRegisterImpl::D, Fsrc, Fdst);
2739 %}
2740
2741 enc_class Fast_Lock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{
2742 MacroAssembler _masm(&cbuf);
2743
2744 Register Roop = reg_to_register_object($oop$$reg);
2745 Register Rbox = reg_to_register_object($box$$reg);
2746 Register Rscratch = reg_to_register_object($scratch$$reg);
2747 Register Rmark = reg_to_register_object($scratch2$$reg);
2748
2749 assert(Roop != Rscratch, "");
2750 assert(Roop != Rmark, "");
2751 assert(Rbox != Rscratch, "");
2752 assert(Rbox != Rmark, "");
2753
2754 __ compiler_lock_object(Roop, Rmark, Rbox, Rscratch, _counters, UseBiasedLocking && !UseOptoBiasInlining);
2755 %}
2756
2757 enc_class Fast_Unlock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{
2758 MacroAssembler _masm(&cbuf);
2759
2760 Register Roop = reg_to_register_object($oop$$reg);
2761 Register Rbox = reg_to_register_object($box$$reg);
2762 Register Rscratch = reg_to_register_object($scratch$$reg);
2763 Register Rmark = reg_to_register_object($scratch2$$reg);
2764
2765 assert(Roop != Rscratch, "");
2766 assert(Roop != Rmark, "");
2767 assert(Rbox != Rscratch, "");
2768 assert(Rbox != Rmark, "");
2769
2770 __ compiler_unlock_object(Roop, Rmark, Rbox, Rscratch, UseBiasedLocking && !UseOptoBiasInlining);
2771 %}
2772
2773 enc_class enc_cas( iRegP mem, iRegP old, iRegP new ) %{
2774 MacroAssembler _masm(&cbuf);
2775 Register Rmem = reg_to_register_object($mem$$reg);
2776 Register Rold = reg_to_register_object($old$$reg);
2777 Register Rnew = reg_to_register_object($new$$reg);
2778
2779 // casx_under_lock picks 1 of 3 encodings:
2780 // For 32-bit pointers you get a 32-bit CAS
2781 // For 64-bit pointers you get a 64-bit CASX
2782 __ casn(Rmem, Rold, Rnew); // Swap(*Rmem,Rnew) if *Rmem == Rold
2783 __ cmp( Rold, Rnew );
2784 %}
2785
2786 enc_class enc_casx( iRegP mem, iRegL old, iRegL new) %{
2787 Register Rmem = reg_to_register_object($mem$$reg);
2788 Register Rold = reg_to_register_object($old$$reg);
2789 Register Rnew = reg_to_register_object($new$$reg);
2790
2791 MacroAssembler _masm(&cbuf);
2792 __ mov(Rnew, O7);
2793 __ casx(Rmem, Rold, O7);
2794 __ cmp( Rold, O7 );
2795 %}
2796
2797 // raw int cas, used for compareAndSwap
2798 enc_class enc_casi( iRegP mem, iRegL old, iRegL new) %{
2799 Register Rmem = reg_to_register_object($mem$$reg);
2800 Register Rold = reg_to_register_object($old$$reg);
2801 Register Rnew = reg_to_register_object($new$$reg);
2802
2803 MacroAssembler _masm(&cbuf);
2804 __ mov(Rnew, O7);
2805 __ cas(Rmem, Rold, O7);
2806 __ cmp( Rold, O7 );
2807 %}
2808
2809 enc_class enc_lflags_ne_to_boolean( iRegI res ) %{
2810 Register Rres = reg_to_register_object($res$$reg);
2811
2812 MacroAssembler _masm(&cbuf);
2813 __ mov(1, Rres);
2814 __ movcc( Assembler::notEqual, false, Assembler::xcc, G0, Rres );
2815 %}
2816
2817 enc_class enc_iflags_ne_to_boolean( iRegI res ) %{
2818 Register Rres = reg_to_register_object($res$$reg);
2819
2820 MacroAssembler _masm(&cbuf);
2821 __ mov(1, Rres);
2822 __ movcc( Assembler::notEqual, false, Assembler::icc, G0, Rres );
2823 %}
2824
2825 enc_class floating_cmp ( iRegP dst, regF src1, regF src2 ) %{
2826 MacroAssembler _masm(&cbuf);
2827 Register Rdst = reg_to_register_object($dst$$reg);
2828 FloatRegister Fsrc1 = $primary ? reg_to_SingleFloatRegister_object($src1$$reg)
2829 : reg_to_DoubleFloatRegister_object($src1$$reg);
2830 FloatRegister Fsrc2 = $primary ? reg_to_SingleFloatRegister_object($src2$$reg)
2831 : reg_to_DoubleFloatRegister_object($src2$$reg);
2832
2833 // Convert condition code fcc0 into -1,0,1; unordered reports less-than (-1)
2834 __ float_cmp( $primary, -1, Fsrc1, Fsrc2, Rdst);
2835 %}
2836
2837 // Compiler ensures base is doubleword aligned and cnt is count of doublewords
2838 enc_class enc_Clear_Array(iRegX cnt, iRegP base, iRegX temp) %{
2839 MacroAssembler _masm(&cbuf);
2840 Register nof_bytes_arg = reg_to_register_object($cnt$$reg);
2841 Register nof_bytes_tmp = reg_to_register_object($temp$$reg);
2842 Register base_pointer_arg = reg_to_register_object($base$$reg);
2843
2844 Label loop;
2845 __ mov(nof_bytes_arg, nof_bytes_tmp);
2846
2847 // Loop and clear, walking backwards through the array.
2848 // nof_bytes_tmp (if >0) is always the number of bytes to zero
2849 __ bind(loop);
2850 __ deccc(nof_bytes_tmp, 8);
2851 __ br(Assembler::greaterEqual, true, Assembler::pt, loop);
2852 __ delayed()-> stx(G0, base_pointer_arg, nof_bytes_tmp);
2853 // %%%% this mini-loop must not cross a cache boundary!
2854 %}
2855
2856
2857 enc_class enc_String_Compare(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result) %{
2858 Label Ldone, Lloop;
2859 MacroAssembler _masm(&cbuf);
2860
2861 Register str1_reg = reg_to_register_object($str1$$reg);
2862 Register str2_reg = reg_to_register_object($str2$$reg);
2863 Register cnt1_reg = reg_to_register_object($cnt1$$reg);
2864 Register cnt2_reg = reg_to_register_object($cnt2$$reg);
2865 Register result_reg = reg_to_register_object($result$$reg);
2866
2867 assert(result_reg != str1_reg &&
2868 result_reg != str2_reg &&
2869 result_reg != cnt1_reg &&
2870 result_reg != cnt2_reg ,
2871 "need different registers");
2872
2873 // Compute the minimum of the string lengths(str1_reg) and the
2874 // difference of the string lengths (stack)
2875
2876 // See if the lengths are different, and calculate min in str1_reg.
2877 // Stash diff in O7 in case we need it for a tie-breaker.
2878 Label Lskip;
2879 __ subcc(cnt1_reg, cnt2_reg, O7);
2880 __ sll(cnt1_reg, exact_log2(sizeof(jchar)), cnt1_reg); // scale the limit
2881 __ br(Assembler::greater, true, Assembler::pt, Lskip);
2882 // cnt2 is shorter, so use its count:
2883 __ delayed()->sll(cnt2_reg, exact_log2(sizeof(jchar)), cnt1_reg); // scale the limit
2884 __ bind(Lskip);
2885
2886 // reallocate cnt1_reg, cnt2_reg, result_reg
2887 // Note: limit_reg holds the string length pre-scaled by 2
2888 Register limit_reg = cnt1_reg;
2889 Register chr2_reg = cnt2_reg;
2890 Register chr1_reg = result_reg;
2891 // str{12} are the base pointers
2892
2893 // Is the minimum length zero?
2894 __ cmp(limit_reg, (int)(0 * sizeof(jchar))); // use cast to resolve overloading ambiguity
2895 __ br(Assembler::equal, true, Assembler::pn, Ldone);
2896 __ delayed()->mov(O7, result_reg); // result is difference in lengths
2897
2898 // Load first characters
2899 __ lduh(str1_reg, 0, chr1_reg);
2900 __ lduh(str2_reg, 0, chr2_reg);
2901
2902 // Compare first characters
2903 __ subcc(chr1_reg, chr2_reg, chr1_reg);
2904 __ br(Assembler::notZero, false, Assembler::pt, Ldone);
2905 assert(chr1_reg == result_reg, "result must be pre-placed");
2906 __ delayed()->nop();
2907
2908 {
2909 // Check after comparing first character to see if strings are equivalent
2910 Label LSkip2;
2911 // Check if the strings start at same location
2912 __ cmp(str1_reg, str2_reg);
2913 __ brx(Assembler::notEqual, true, Assembler::pt, LSkip2);
2914 __ delayed()->nop();
2915
2916 // Check if the length difference is zero (in O7)
2917 __ cmp(G0, O7);
2918 __ br(Assembler::equal, true, Assembler::pn, Ldone);
2919 __ delayed()->mov(G0, result_reg); // result is zero
2920
2921 // Strings might not be equal
2922 __ bind(LSkip2);
2923 }
2924
2925 __ subcc(limit_reg, 1 * sizeof(jchar), chr1_reg);
2926 __ br(Assembler::equal, true, Assembler::pn, Ldone);
2927 __ delayed()->mov(O7, result_reg); // result is difference in lengths
2928
2929 // Shift str1_reg and str2_reg to the end of the arrays, negate limit
2930 __ add(str1_reg, limit_reg, str1_reg);
2931 __ add(str2_reg, limit_reg, str2_reg);
2932 __ neg(chr1_reg, limit_reg); // limit = -(limit-2)
2933
2934 // Compare the rest of the characters
2935 __ lduh(str1_reg, limit_reg, chr1_reg);
2936 __ bind(Lloop);
2937 // __ lduh(str1_reg, limit_reg, chr1_reg); // hoisted
2938 __ lduh(str2_reg, limit_reg, chr2_reg);
2939 __ subcc(chr1_reg, chr2_reg, chr1_reg);
2940 __ br(Assembler::notZero, false, Assembler::pt, Ldone);
2941 assert(chr1_reg == result_reg, "result must be pre-placed");
2942 __ delayed()->inccc(limit_reg, sizeof(jchar));
2943 // annul LDUH if branch is not taken to prevent access past end of string
2944 __ br(Assembler::notZero, true, Assembler::pt, Lloop);
2945 __ delayed()->lduh(str1_reg, limit_reg, chr1_reg); // hoisted
2946
2947 // If strings are equal up to min length, return the length difference.
2948 __ mov(O7, result_reg);
2949
2950 // Otherwise, return the difference between the first mismatched chars.
2951 __ bind(Ldone);
2952 %}
2953
2954 enc_class enc_String_Equals(o0RegP str1, o1RegP str2, g3RegI cnt, notemp_iRegI result) %{
2955 Label Lword_loop, Lpost_word, Lchar, Lchar_loop, Ldone;
2956 MacroAssembler _masm(&cbuf);
2957
2958 Register str1_reg = reg_to_register_object($str1$$reg);
2959 Register str2_reg = reg_to_register_object($str2$$reg);
2960 Register cnt_reg = reg_to_register_object($cnt$$reg);
2961 Register tmp1_reg = O7;
2962 Register result_reg = reg_to_register_object($result$$reg);
2963
2964 assert(result_reg != str1_reg &&
2965 result_reg != str2_reg &&
2966 result_reg != cnt_reg &&
2967 result_reg != tmp1_reg ,
2968 "need different registers");
2969
2970 __ cmp(str1_reg, str2_reg); //same char[] ?
2971 __ brx(Assembler::equal, true, Assembler::pn, Ldone);
2972 __ delayed()->add(G0, 1, result_reg);
2973
2974 __ br_on_reg_cond(Assembler::rc_z, true, Assembler::pn, cnt_reg, Ldone);
2975 __ delayed()->add(G0, 1, result_reg); // count == 0
2976
2977 //rename registers
2978 Register limit_reg = cnt_reg;
2979 Register chr1_reg = result_reg;
2980 Register chr2_reg = tmp1_reg;
2981
2982 //check for alignment and position the pointers to the ends
2983 __ or3(str1_reg, str2_reg, chr1_reg);
2984 __ andcc(chr1_reg, 0x3, chr1_reg);
2985 // notZero means at least one not 4-byte aligned.
2986 // We could optimize the case when both arrays are not aligned
2987 // but it is not frequent case and it requires additional checks.
2988 __ br(Assembler::notZero, false, Assembler::pn, Lchar); // char by char compare
2989 __ delayed()->sll(limit_reg, exact_log2(sizeof(jchar)), limit_reg); // set byte count
2990
2991 // Compare char[] arrays aligned to 4 bytes.
2992 __ char_arrays_equals(str1_reg, str2_reg, limit_reg, result_reg,
2993 chr1_reg, chr2_reg, Ldone);
2994 __ ba(false,Ldone);
2995 __ delayed()->add(G0, 1, result_reg);
2996
2997 // char by char compare
2998 __ bind(Lchar);
2999 __ add(str1_reg, limit_reg, str1_reg);
3000 __ add(str2_reg, limit_reg, str2_reg);
3001 __ neg(limit_reg); //negate count
3002
3003 __ lduh(str1_reg, limit_reg, chr1_reg);
3004 // Lchar_loop
3005 __ bind(Lchar_loop);
3006 __ lduh(str2_reg, limit_reg, chr2_reg);
3007 __ cmp(chr1_reg, chr2_reg);
3008 __ br(Assembler::notEqual, true, Assembler::pt, Ldone);
3009 __ delayed()->mov(G0, result_reg); //not equal
3010 __ inccc(limit_reg, sizeof(jchar));
3011 // annul LDUH if branch is not taken to prevent access past end of string
3012 __ br(Assembler::notZero, true, Assembler::pt, Lchar_loop);
3013 __ delayed()->lduh(str1_reg, limit_reg, chr1_reg); // hoisted
3014
3015 __ add(G0, 1, result_reg); //equal
3016
3017 __ bind(Ldone);
3018 %}
3019
3020 enc_class enc_Array_Equals(o0RegP ary1, o1RegP ary2, g3RegP tmp1, notemp_iRegI result) %{
3021 Label Lvector, Ldone, Lloop;
3022 MacroAssembler _masm(&cbuf);
3023
3024 Register ary1_reg = reg_to_register_object($ary1$$reg);
3025 Register ary2_reg = reg_to_register_object($ary2$$reg);
3026 Register tmp1_reg = reg_to_register_object($tmp1$$reg);
3027 Register tmp2_reg = O7;
3028 Register result_reg = reg_to_register_object($result$$reg);
3029
3030 int length_offset = arrayOopDesc::length_offset_in_bytes();
3031 int base_offset = arrayOopDesc::base_offset_in_bytes(T_CHAR);
3032
3033 // return true if the same array
3034 __ cmp(ary1_reg, ary2_reg);
3035 __ brx(Assembler::equal, true, Assembler::pn, Ldone);
3036 __ delayed()->add(G0, 1, result_reg); // equal
3037
3038 __ br_null(ary1_reg, true, Assembler::pn, Ldone);
3039 __ delayed()->mov(G0, result_reg); // not equal
3040
3041 __ br_null(ary2_reg, true, Assembler::pn, Ldone);
3042 __ delayed()->mov(G0, result_reg); // not equal
3043
3044 //load the lengths of arrays
3045 __ ld(Address(ary1_reg, length_offset), tmp1_reg);
3046 __ ld(Address(ary2_reg, length_offset), tmp2_reg);
3047
3048 // return false if the two arrays are not equal length
3049 __ cmp(tmp1_reg, tmp2_reg);
3050 __ br(Assembler::notEqual, true, Assembler::pn, Ldone);
3051 __ delayed()->mov(G0, result_reg); // not equal
3052
3053 __ br_on_reg_cond(Assembler::rc_z, true, Assembler::pn, tmp1_reg, Ldone);
3054 __ delayed()->add(G0, 1, result_reg); // zero-length arrays are equal
3055
3056 // load array addresses
3057 __ add(ary1_reg, base_offset, ary1_reg);
3058 __ add(ary2_reg, base_offset, ary2_reg);
3059
3060 // renaming registers
3061 Register chr1_reg = result_reg; // for characters in ary1
3062 Register chr2_reg = tmp2_reg; // for characters in ary2
3063 Register limit_reg = tmp1_reg; // length
3064
3065 // set byte count
3066 __ sll(limit_reg, exact_log2(sizeof(jchar)), limit_reg);
3067
3068 // Compare char[] arrays aligned to 4 bytes.
3069 __ char_arrays_equals(ary1_reg, ary2_reg, limit_reg, result_reg,
3070 chr1_reg, chr2_reg, Ldone);
3071 __ add(G0, 1, result_reg); // equals
3072
3073 __ bind(Ldone);
3074 %}
3075
3076 enc_class enc_rethrow() %{
3077 cbuf.set_insts_mark();
3078 Register temp_reg = G3;
3079 AddressLiteral rethrow_stub(OptoRuntime::rethrow_stub());
3080 assert(temp_reg != reg_to_register_object(R_I0_num), "temp must not break oop_reg");
3081 MacroAssembler _masm(&cbuf);
3082 #ifdef ASSERT
3083 __ save_frame(0);
3084 AddressLiteral last_rethrow_addrlit(&last_rethrow);
3085 __ sethi(last_rethrow_addrlit, L1);
3086 Address addr(L1, last_rethrow_addrlit.low10());
3087 __ get_pc(L2);
3088 __ inc(L2, 3 * BytesPerInstWord); // skip this & 2 more insns to point at jump_to
3089 __ st_ptr(L2, addr);
3090 __ restore();
3091 #endif
3092 __ JUMP(rethrow_stub, temp_reg, 0); // sethi;jmp
3093 __ delayed()->nop();
3094 %}
3095
3096 enc_class emit_mem_nop() %{
3097 // Generates the instruction LDUXA [o6,g0],#0x82,g0
3098 cbuf.insts()->emit_int32((unsigned int) 0xc0839040);
3099 %}
3100
3101 enc_class emit_fadd_nop() %{
3102 // Generates the instruction FMOVS f31,f31
3103 cbuf.insts()->emit_int32((unsigned int) 0xbfa0003f);
3104 %}
3105
3106 enc_class emit_br_nop() %{
3107 // Generates the instruction BPN,PN .
3108 cbuf.insts()->emit_int32((unsigned int) 0x00400000);
3109 %}
3110
3111 enc_class enc_membar_acquire %{
3112 MacroAssembler _masm(&cbuf);
3113 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::LoadLoad) );
3114 %}
3115
3116 enc_class enc_membar_release %{
3117 MacroAssembler _masm(&cbuf);
3118 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::StoreStore) );
3119 %}
3120
3121 enc_class enc_membar_volatile %{
3122 MacroAssembler _masm(&cbuf);
3123 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad) );
3124 %}
3125
3126 enc_class enc_repl8b( iRegI src, iRegL dst ) %{
3127 MacroAssembler _masm(&cbuf);
3128 Register src_reg = reg_to_register_object($src$$reg);
3129 Register dst_reg = reg_to_register_object($dst$$reg);
3130 __ sllx(src_reg, 56, dst_reg);
3131 __ srlx(dst_reg, 8, O7);
3132 __ or3 (dst_reg, O7, dst_reg);
3133 __ srlx(dst_reg, 16, O7);
3134 __ or3 (dst_reg, O7, dst_reg);
3135 __ srlx(dst_reg, 32, O7);
3136 __ or3 (dst_reg, O7, dst_reg);
3137 %}
3138
3139 enc_class enc_repl4b( iRegI src, iRegL dst ) %{
3140 MacroAssembler _masm(&cbuf);
3141 Register src_reg = reg_to_register_object($src$$reg);
3142 Register dst_reg = reg_to_register_object($dst$$reg);
3143 __ sll(src_reg, 24, dst_reg);
3144 __ srl(dst_reg, 8, O7);
3145 __ or3(dst_reg, O7, dst_reg);
3146 __ srl(dst_reg, 16, O7);
3147 __ or3(dst_reg, O7, dst_reg);
3148 %}
3149
3150 enc_class enc_repl4s( iRegI src, iRegL dst ) %{
3151 MacroAssembler _masm(&cbuf);
3152 Register src_reg = reg_to_register_object($src$$reg);
3153 Register dst_reg = reg_to_register_object($dst$$reg);
3154 __ sllx(src_reg, 48, dst_reg);
3155 __ srlx(dst_reg, 16, O7);
3156 __ or3 (dst_reg, O7, dst_reg);
3157 __ srlx(dst_reg, 32, O7);
3158 __ or3 (dst_reg, O7, dst_reg);
3159 %}
3160
3161 enc_class enc_repl2i( iRegI src, iRegL dst ) %{
3162 MacroAssembler _masm(&cbuf);
3163 Register src_reg = reg_to_register_object($src$$reg);
3164 Register dst_reg = reg_to_register_object($dst$$reg);
3165 __ sllx(src_reg, 32, dst_reg);
3166 __ srlx(dst_reg, 32, O7);
3167 __ or3 (dst_reg, O7, dst_reg);
3168 %}
3169
3170 %}
3171
3172 //----------FRAME--------------------------------------------------------------
3173 // Definition of frame structure and management information.
3174 //
3175 // S T A C K L A Y O U T Allocators stack-slot number
3176 // | (to get allocators register number
3177 // G Owned by | | v add VMRegImpl::stack0)
3178 // r CALLER | |
3179 // o | +--------+ pad to even-align allocators stack-slot
3180 // w V | pad0 | numbers; owned by CALLER
3181 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
3182 // h ^ | in | 5
3183 // | | args | 4 Holes in incoming args owned by SELF
3184 // | | | | 3
3185 // | | +--------+
3186 // V | | old out| Empty on Intel, window on Sparc
3187 // | old |preserve| Must be even aligned.
3188 // | SP-+--------+----> Matcher::_old_SP, 8 (or 16 in LP64)-byte aligned
3189 // | | in | 3 area for Intel ret address
3190 // Owned by |preserve| Empty on Sparc.
3191 // SELF +--------+
3192 // | | pad2 | 2 pad to align old SP
3193 // | +--------+ 1
3194 // | | locks | 0
3195 // | +--------+----> VMRegImpl::stack0, 8 (or 16 in LP64)-byte aligned
3196 // | | pad1 | 11 pad to align new SP
3197 // | +--------+
3198 // | | | 10
3199 // | | spills | 9 spills
3200 // V | | 8 (pad0 slot for callee)
3201 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
3202 // ^ | out | 7
3203 // | | args | 6 Holes in outgoing args owned by CALLEE
3204 // Owned by +--------+
3205 // CALLEE | new out| 6 Empty on Intel, window on Sparc
3206 // | new |preserve| Must be even-aligned.
3207 // | SP-+--------+----> Matcher::_new_SP, even aligned
3208 // | | |
3209 //
3210 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
3211 // known from SELF's arguments and the Java calling convention.
3212 // Region 6-7 is determined per call site.
3213 // Note 2: If the calling convention leaves holes in the incoming argument
3214 // area, those holes are owned by SELF. Holes in the outgoing area
3215 // are owned by the CALLEE. Holes should not be nessecary in the
3216 // incoming area, as the Java calling convention is completely under
3217 // the control of the AD file. Doubles can be sorted and packed to
3218 // avoid holes. Holes in the outgoing arguments may be nessecary for
3219 // varargs C calling conventions.
3220 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
3221 // even aligned with pad0 as needed.
3222 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
3223 // region 6-11 is even aligned; it may be padded out more so that
3224 // the region from SP to FP meets the minimum stack alignment.
3225
3226 frame %{
3227 // What direction does stack grow in (assumed to be same for native & Java)
3228 stack_direction(TOWARDS_LOW);
3229
3230 // These two registers define part of the calling convention
3231 // between compiled code and the interpreter.
3232 inline_cache_reg(R_G5); // Inline Cache Register or methodOop for I2C
3233 interpreter_method_oop_reg(R_G5); // Method Oop Register when calling interpreter
3234
3235 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset]
3236 cisc_spilling_operand_name(indOffset);
3237
3238 // Number of stack slots consumed by a Monitor enter
3239 #ifdef _LP64
3240 sync_stack_slots(2);
3241 #else
3242 sync_stack_slots(1);
3243 #endif
3244
3245 // Compiled code's Frame Pointer
3246 frame_pointer(R_SP);
3247
3248 // Stack alignment requirement
3249 stack_alignment(StackAlignmentInBytes);
3250 // LP64: Alignment size in bytes (128-bit -> 16 bytes)
3251 // !LP64: Alignment size in bytes (64-bit -> 8 bytes)
3252
3253 // Number of stack slots between incoming argument block and the start of
3254 // a new frame. The PROLOG must add this many slots to the stack. The
3255 // EPILOG must remove this many slots.
3256 in_preserve_stack_slots(0);
3257
3258 // Number of outgoing stack slots killed above the out_preserve_stack_slots
3259 // for calls to C. Supports the var-args backing area for register parms.
3260 // ADLC doesn't support parsing expressions, so I folded the math by hand.
3261 #ifdef _LP64
3262 // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (0)) * 2-stack-slots-per-word
3263 varargs_C_out_slots_killed(12);
3264 #else
3265 // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (1)) * 1-stack-slots-per-word
3266 varargs_C_out_slots_killed( 7);
3267 #endif
3268
3269 // The after-PROLOG location of the return address. Location of
3270 // return address specifies a type (REG or STACK) and a number
3271 // representing the register number (i.e. - use a register name) or
3272 // stack slot.
3273 return_addr(REG R_I7); // Ret Addr is in register I7
3274
3275 // Body of function which returns an OptoRegs array locating
3276 // arguments either in registers or in stack slots for calling
3277 // java
3278 calling_convention %{
3279 (void) SharedRuntime::java_calling_convention(sig_bt, regs, length, is_outgoing);
3280
3281 %}
3282
3283 // Body of function which returns an OptoRegs array locating
3284 // arguments either in registers or in stack slots for callin
3285 // C.
3286 c_calling_convention %{
3287 // This is obviously always outgoing
3288 (void) SharedRuntime::c_calling_convention(sig_bt, regs, length);
3289 %}
3290
3291 // Location of native (C/C++) and interpreter return values. This is specified to
3292 // be the same as Java. In the 32-bit VM, long values are actually returned from
3293 // native calls in O0:O1 and returned to the interpreter in I0:I1. The copying
3294 // to and from the register pairs is done by the appropriate call and epilog
3295 // opcodes. This simplifies the register allocator.
3296 c_return_value %{
3297 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3298 #ifdef _LP64
3299 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num };
3300 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num};
3301 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num };
3302 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num};
3303 #else // !_LP64
3304 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_G1_num };
3305 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num };
3306 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_G1_num };
3307 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num };
3308 #endif
3309 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg],
3310 (is_outgoing?lo_out:lo_in)[ideal_reg] );
3311 %}
3312
3313 // Location of compiled Java return values. Same as C
3314 return_value %{
3315 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3316 #ifdef _LP64
3317 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num };
3318 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num};
3319 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num };
3320 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num};
3321 #else // !_LP64
3322 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_G1_num };
3323 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num};
3324 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_G1_num };
3325 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num};
3326 #endif
3327 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg],
3328 (is_outgoing?lo_out:lo_in)[ideal_reg] );
3329 %}
3330
3331 %}
3332
3333
3334 //----------ATTRIBUTES---------------------------------------------------------
3335 //----------Operand Attributes-------------------------------------------------
3336 op_attrib op_cost(1); // Required cost attribute
3337
3338 //----------Instruction Attributes---------------------------------------------
3339 ins_attrib ins_cost(DEFAULT_COST); // Required cost attribute
3340 ins_attrib ins_size(32); // Required size attribute (in bits)
3341 ins_attrib ins_pc_relative(0); // Required PC Relative flag
3342 ins_attrib ins_short_branch(0); // Required flag: is this instruction a
3343 // non-matching short branch variant of some
3344 // long branch?
3345
3346 //----------OPERANDS-----------------------------------------------------------
3347 // Operand definitions must precede instruction definitions for correct parsing
3348 // in the ADLC because operands constitute user defined types which are used in
3349 // instruction definitions.
3350
3351 //----------Simple Operands----------------------------------------------------
3352 // Immediate Operands
3353 // Integer Immediate: 32-bit
3354 operand immI() %{
3355 match(ConI);
3356
3357 op_cost(0);
3358 // formats are generated automatically for constants and base registers
3359 format %{ %}
3360 interface(CONST_INTER);
3361 %}
3362
3363 // Integer Immediate: 8-bit
3364 operand immI8() %{
3365 predicate(Assembler::is_simm(n->get_int(), 8));
3366 match(ConI);
3367 op_cost(0);
3368 format %{ %}
3369 interface(CONST_INTER);
3370 %}
3371
3372 // Integer Immediate: 13-bit
3373 operand immI13() %{
3374 predicate(Assembler::is_simm13(n->get_int()));
3375 match(ConI);
3376 op_cost(0);
3377
3378 format %{ %}
3379 interface(CONST_INTER);
3380 %}
3381
3382 // Integer Immediate: 13-bit minus 7
3383 operand immI13m7() %{
3384 predicate((-4096 < n->get_int()) && ((n->get_int() + 7) <= 4095));
3385 match(ConI);
3386 op_cost(0);
3387
3388 format %{ %}
3389 interface(CONST_INTER);
3390 %}
3391
3392 // Integer Immediate: 16-bit
3393 operand immI16() %{
3394 predicate(Assembler::is_simm(n->get_int(), 16));
3395 match(ConI);
3396 op_cost(0);
3397 format %{ %}
3398 interface(CONST_INTER);
3399 %}
3400
3401 // Unsigned (positive) Integer Immediate: 13-bit
3402 operand immU13() %{
3403 predicate((0 <= n->get_int()) && Assembler::is_simm13(n->get_int()));
3404 match(ConI);
3405 op_cost(0);
3406
3407 format %{ %}
3408 interface(CONST_INTER);
3409 %}
3410
3411 // Integer Immediate: 6-bit
3412 operand immU6() %{
3413 predicate(n->get_int() >= 0 && n->get_int() <= 63);
3414 match(ConI);
3415 op_cost(0);
3416 format %{ %}
3417 interface(CONST_INTER);
3418 %}
3419
3420 // Integer Immediate: 11-bit
3421 operand immI11() %{
3422 predicate(Assembler::is_simm(n->get_int(),11));
3423 match(ConI);
3424 op_cost(0);
3425 format %{ %}
3426 interface(CONST_INTER);
3427 %}
3428
3429 // Integer Immediate: 0-bit
3430 operand immI0() %{
3431 predicate(n->get_int() == 0);
3432 match(ConI);
3433 op_cost(0);
3434
3435 format %{ %}
3436 interface(CONST_INTER);
3437 %}
3438
3439 // Integer Immediate: the value 10
3440 operand immI10() %{
3441 predicate(n->get_int() == 10);
3442 match(ConI);
3443 op_cost(0);
3444
3445 format %{ %}
3446 interface(CONST_INTER);
3447 %}
3448
3449 // Integer Immediate: the values 0-31
3450 operand immU5() %{
3451 predicate(n->get_int() >= 0 && n->get_int() <= 31);
3452 match(ConI);
3453 op_cost(0);
3454
3455 format %{ %}
3456 interface(CONST_INTER);
3457 %}
3458
3459 // Integer Immediate: the values 1-31
3460 operand immI_1_31() %{
3461 predicate(n->get_int() >= 1 && n->get_int() <= 31);
3462 match(ConI);
3463 op_cost(0);
3464
3465 format %{ %}
3466 interface(CONST_INTER);
3467 %}
3468
3469 // Integer Immediate: the values 32-63
3470 operand immI_32_63() %{
3471 predicate(n->get_int() >= 32 && n->get_int() <= 63);
3472 match(ConI);
3473 op_cost(0);
3474
3475 format %{ %}
3476 interface(CONST_INTER);
3477 %}
3478
3479 // Immediates for special shifts (sign extend)
3480
3481 // Integer Immediate: the value 16
3482 operand immI_16() %{
3483 predicate(n->get_int() == 16);
3484 match(ConI);
3485 op_cost(0);
3486
3487 format %{ %}
3488 interface(CONST_INTER);
3489 %}
3490
3491 // Integer Immediate: the value 24
3492 operand immI_24() %{
3493 predicate(n->get_int() == 24);
3494 match(ConI);
3495 op_cost(0);
3496
3497 format %{ %}
3498 interface(CONST_INTER);
3499 %}
3500
3501 // Integer Immediate: the value 255
3502 operand immI_255() %{
3503 predicate( n->get_int() == 255 );
3504 match(ConI);
3505 op_cost(0);
3506
3507 format %{ %}
3508 interface(CONST_INTER);
3509 %}
3510
3511 // Integer Immediate: the value 65535
3512 operand immI_65535() %{
3513 predicate(n->get_int() == 65535);
3514 match(ConI);
3515 op_cost(0);
3516
3517 format %{ %}
3518 interface(CONST_INTER);
3519 %}
3520
3521 // Long Immediate: the value FF
3522 operand immL_FF() %{
3523 predicate( n->get_long() == 0xFFL );
3524 match(ConL);
3525 op_cost(0);
3526
3527 format %{ %}
3528 interface(CONST_INTER);
3529 %}
3530
3531 // Long Immediate: the value FFFF
3532 operand immL_FFFF() %{
3533 predicate( n->get_long() == 0xFFFFL );
3534 match(ConL);
3535 op_cost(0);
3536
3537 format %{ %}
3538 interface(CONST_INTER);
3539 %}
3540
3541 // Pointer Immediate: 32 or 64-bit
3542 operand immP() %{
3543 match(ConP);
3544
3545 op_cost(5);
3546 // formats are generated automatically for constants and base registers
3547 format %{ %}
3548 interface(CONST_INTER);
3549 %}
3550
3551 #ifdef _LP64
3552 // Pointer Immediate: 64-bit
3553 operand immP_set() %{
3554 predicate(!VM_Version::is_niagara_plus());
3555 match(ConP);
3556
3557 op_cost(5);
3558 // formats are generated automatically for constants and base registers
3559 format %{ %}
3560 interface(CONST_INTER);
3561 %}
3562
3563 // Pointer Immediate: 64-bit
3564 // From Niagara2 processors on a load should be better than materializing.
3565 operand immP_load() %{
3566 predicate(VM_Version::is_niagara_plus() && (n->bottom_type()->isa_oop_ptr() || (MacroAssembler::insts_for_set(n->get_ptr()) > 3)));
3567 match(ConP);
3568
3569 op_cost(5);
3570 // formats are generated automatically for constants and base registers
3571 format %{ %}
3572 interface(CONST_INTER);
3573 %}
3574
3575 // Pointer Immediate: 64-bit
3576 operand immP_no_oop_cheap() %{
3577 predicate(VM_Version::is_niagara_plus() && !n->bottom_type()->isa_oop_ptr() && (MacroAssembler::insts_for_set(n->get_ptr()) <= 3));
3578 match(ConP);
3579
3580 op_cost(5);
3581 // formats are generated automatically for constants and base registers
3582 format %{ %}
3583 interface(CONST_INTER);
3584 %}
3585 #endif
3586
3587 operand immP13() %{
3588 predicate((-4096 < n->get_ptr()) && (n->get_ptr() <= 4095));
3589 match(ConP);
3590 op_cost(0);
3591
3592 format %{ %}
3593 interface(CONST_INTER);
3594 %}
3595
3596 operand immP0() %{
3597 predicate(n->get_ptr() == 0);
3598 match(ConP);
3599 op_cost(0);
3600
3601 format %{ %}
3602 interface(CONST_INTER);
3603 %}
3604
3605 operand immP_poll() %{
3606 predicate(n->get_ptr() != 0 && n->get_ptr() == (intptr_t)os::get_polling_page());
3607 match(ConP);
3608
3609 // formats are generated automatically for constants and base registers
3610 format %{ %}
3611 interface(CONST_INTER);
3612 %}
3613
3614 // Pointer Immediate
3615 operand immN()
3616 %{
3617 match(ConN);
3618
3619 op_cost(10);
3620 format %{ %}
3621 interface(CONST_INTER);
3622 %}
3623
3624 // NULL Pointer Immediate
3625 operand immN0()
3626 %{
3627 predicate(n->get_narrowcon() == 0);
3628 match(ConN);
3629
3630 op_cost(0);
3631 format %{ %}
3632 interface(CONST_INTER);
3633 %}
3634
3635 operand immL() %{
3636 match(ConL);
3637 op_cost(40);
3638 // formats are generated automatically for constants and base registers
3639 format %{ %}
3640 interface(CONST_INTER);
3641 %}
3642
3643 operand immL0() %{
3644 predicate(n->get_long() == 0L);
3645 match(ConL);
3646 op_cost(0);
3647 // formats are generated automatically for constants and base registers
3648 format %{ %}
3649 interface(CONST_INTER);
3650 %}
3651
3652 // Long Immediate: 13-bit
3653 operand immL13() %{
3654 predicate((-4096L < n->get_long()) && (n->get_long() <= 4095L));
3655 match(ConL);
3656 op_cost(0);
3657
3658 format %{ %}
3659 interface(CONST_INTER);
3660 %}
3661
3662 // Long Immediate: 13-bit minus 7
3663 operand immL13m7() %{
3664 predicate((-4096L < n->get_long()) && ((n->get_long() + 7L) <= 4095L));
3665 match(ConL);
3666 op_cost(0);
3667
3668 format %{ %}
3669 interface(CONST_INTER);
3670 %}
3671
3672 // Long Immediate: low 32-bit mask
3673 operand immL_32bits() %{
3674 predicate(n->get_long() == 0xFFFFFFFFL);
3675 match(ConL);
3676 op_cost(0);
3677
3678 format %{ %}
3679 interface(CONST_INTER);
3680 %}
3681
3682 // Long Immediate: cheap (materialize in <= 3 instructions)
3683 operand immL_cheap() %{
3684 predicate(!VM_Version::is_niagara_plus() || MacroAssembler::insts_for_set64(n->get_long()) <= 3);
3685 match(ConL);
3686 op_cost(0);
3687
3688 format %{ %}
3689 interface(CONST_INTER);
3690 %}
3691
3692 // Long Immediate: expensive (materialize in > 3 instructions)
3693 operand immL_expensive() %{
3694 predicate(VM_Version::is_niagara_plus() && MacroAssembler::insts_for_set64(n->get_long()) > 3);
3695 match(ConL);
3696 op_cost(0);
3697
3698 format %{ %}
3699 interface(CONST_INTER);
3700 %}
3701
3702 // Double Immediate
3703 operand immD() %{
3704 match(ConD);
3705
3706 op_cost(40);
3707 format %{ %}
3708 interface(CONST_INTER);
3709 %}
3710
3711 operand immD0() %{
3712 #ifdef _LP64
3713 // on 64-bit architectures this comparision is faster
3714 predicate(jlong_cast(n->getd()) == 0);
3715 #else
3716 predicate((n->getd() == 0) && (fpclass(n->getd()) == FP_PZERO));
3717 #endif
3718 match(ConD);
3719
3720 op_cost(0);
3721 format %{ %}
3722 interface(CONST_INTER);
3723 %}
3724
3725 // Float Immediate
3726 operand immF() %{
3727 match(ConF);
3728
3729 op_cost(20);
3730 format %{ %}
3731 interface(CONST_INTER);
3732 %}
3733
3734 // Float Immediate: 0
3735 operand immF0() %{
3736 predicate((n->getf() == 0) && (fpclass(n->getf()) == FP_PZERO));
3737 match(ConF);
3738
3739 op_cost(0);
3740 format %{ %}
3741 interface(CONST_INTER);
3742 %}
3743
3744 // Integer Register Operands
3745 // Integer Register
3746 operand iRegI() %{
3747 constraint(ALLOC_IN_RC(int_reg));
3748 match(RegI);
3749
3750 match(notemp_iRegI);
3751 match(g1RegI);
3752 match(o0RegI);
3753 match(iRegIsafe);
3754
3755 format %{ %}
3756 interface(REG_INTER);
3757 %}
3758
3759 operand notemp_iRegI() %{
3760 constraint(ALLOC_IN_RC(notemp_int_reg));
3761 match(RegI);
3762
3763 match(o0RegI);
3764
3765 format %{ %}
3766 interface(REG_INTER);
3767 %}
3768
3769 operand o0RegI() %{
3770 constraint(ALLOC_IN_RC(o0_regI));
3771 match(iRegI);
3772
3773 format %{ %}
3774 interface(REG_INTER);
3775 %}
3776
3777 // Pointer Register
3778 operand iRegP() %{
3779 constraint(ALLOC_IN_RC(ptr_reg));
3780 match(RegP);
3781
3782 match(lock_ptr_RegP);
3783 match(g1RegP);
3784 match(g2RegP);
3785 match(g3RegP);
3786 match(g4RegP);
3787 match(i0RegP);
3788 match(o0RegP);
3789 match(o1RegP);
3790 match(l7RegP);
3791
3792 format %{ %}
3793 interface(REG_INTER);
3794 %}
3795
3796 operand sp_ptr_RegP() %{
3797 constraint(ALLOC_IN_RC(sp_ptr_reg));
3798 match(RegP);
3799 match(iRegP);
3800
3801 format %{ %}
3802 interface(REG_INTER);
3803 %}
3804
3805 operand lock_ptr_RegP() %{
3806 constraint(ALLOC_IN_RC(lock_ptr_reg));
3807 match(RegP);
3808 match(i0RegP);
3809 match(o0RegP);
3810 match(o1RegP);
3811 match(l7RegP);
3812
3813 format %{ %}
3814 interface(REG_INTER);
3815 %}
3816
3817 operand g1RegP() %{
3818 constraint(ALLOC_IN_RC(g1_regP));
3819 match(iRegP);
3820
3821 format %{ %}
3822 interface(REG_INTER);
3823 %}
3824
3825 operand g2RegP() %{
3826 constraint(ALLOC_IN_RC(g2_regP));
3827 match(iRegP);
3828
3829 format %{ %}
3830 interface(REG_INTER);
3831 %}
3832
3833 operand g3RegP() %{
3834 constraint(ALLOC_IN_RC(g3_regP));
3835 match(iRegP);
3836
3837 format %{ %}
3838 interface(REG_INTER);
3839 %}
3840
3841 operand g1RegI() %{
3842 constraint(ALLOC_IN_RC(g1_regI));
3843 match(iRegI);
3844
3845 format %{ %}
3846 interface(REG_INTER);
3847 %}
3848
3849 operand g3RegI() %{
3850 constraint(ALLOC_IN_RC(g3_regI));
3851 match(iRegI);
3852
3853 format %{ %}
3854 interface(REG_INTER);
3855 %}
3856
3857 operand g4RegI() %{
3858 constraint(ALLOC_IN_RC(g4_regI));
3859 match(iRegI);
3860
3861 format %{ %}
3862 interface(REG_INTER);
3863 %}
3864
3865 operand g4RegP() %{
3866 constraint(ALLOC_IN_RC(g4_regP));
3867 match(iRegP);
3868
3869 format %{ %}
3870 interface(REG_INTER);
3871 %}
3872
3873 operand i0RegP() %{
3874 constraint(ALLOC_IN_RC(i0_regP));
3875 match(iRegP);
3876
3877 format %{ %}
3878 interface(REG_INTER);
3879 %}
3880
3881 operand o0RegP() %{
3882 constraint(ALLOC_IN_RC(o0_regP));
3883 match(iRegP);
3884
3885 format %{ %}
3886 interface(REG_INTER);
3887 %}
3888
3889 operand o1RegP() %{
3890 constraint(ALLOC_IN_RC(o1_regP));
3891 match(iRegP);
3892
3893 format %{ %}
3894 interface(REG_INTER);
3895 %}
3896
3897 operand o2RegP() %{
3898 constraint(ALLOC_IN_RC(o2_regP));
3899 match(iRegP);
3900
3901 format %{ %}
3902 interface(REG_INTER);
3903 %}
3904
3905 operand o7RegP() %{
3906 constraint(ALLOC_IN_RC(o7_regP));
3907 match(iRegP);
3908
3909 format %{ %}
3910 interface(REG_INTER);
3911 %}
3912
3913 operand l7RegP() %{
3914 constraint(ALLOC_IN_RC(l7_regP));
3915 match(iRegP);
3916
3917 format %{ %}
3918 interface(REG_INTER);
3919 %}
3920
3921 operand o7RegI() %{
3922 constraint(ALLOC_IN_RC(o7_regI));
3923 match(iRegI);
3924
3925 format %{ %}
3926 interface(REG_INTER);
3927 %}
3928
3929 operand iRegN() %{
3930 constraint(ALLOC_IN_RC(int_reg));
3931 match(RegN);
3932
3933 format %{ %}
3934 interface(REG_INTER);
3935 %}
3936
3937 // Long Register
3938 operand iRegL() %{
3939 constraint(ALLOC_IN_RC(long_reg));
3940 match(RegL);
3941
3942 format %{ %}
3943 interface(REG_INTER);
3944 %}
3945
3946 operand o2RegL() %{
3947 constraint(ALLOC_IN_RC(o2_regL));
3948 match(iRegL);
3949
3950 format %{ %}
3951 interface(REG_INTER);
3952 %}
3953
3954 operand o7RegL() %{
3955 constraint(ALLOC_IN_RC(o7_regL));
3956 match(iRegL);
3957
3958 format %{ %}
3959 interface(REG_INTER);
3960 %}
3961
3962 operand g1RegL() %{
3963 constraint(ALLOC_IN_RC(g1_regL));
3964 match(iRegL);
3965
3966 format %{ %}
3967 interface(REG_INTER);
3968 %}
3969
3970 operand g3RegL() %{
3971 constraint(ALLOC_IN_RC(g3_regL));
3972 match(iRegL);
3973
3974 format %{ %}
3975 interface(REG_INTER);
3976 %}
3977
3978 // Int Register safe
3979 // This is 64bit safe
3980 operand iRegIsafe() %{
3981 constraint(ALLOC_IN_RC(long_reg));
3982
3983 match(iRegI);
3984
3985 format %{ %}
3986 interface(REG_INTER);
3987 %}
3988
3989 // Condition Code Flag Register
3990 operand flagsReg() %{
3991 constraint(ALLOC_IN_RC(int_flags));
3992 match(RegFlags);
3993
3994 format %{ "ccr" %} // both ICC and XCC
3995 interface(REG_INTER);
3996 %}
3997
3998 // Condition Code Register, unsigned comparisons.
3999 operand flagsRegU() %{
4000 constraint(ALLOC_IN_RC(int_flags));
4001 match(RegFlags);
4002
4003 format %{ "icc_U" %}
4004 interface(REG_INTER);
4005 %}
4006
4007 // Condition Code Register, pointer comparisons.
4008 operand flagsRegP() %{
4009 constraint(ALLOC_IN_RC(int_flags));
4010 match(RegFlags);
4011
4012 #ifdef _LP64
4013 format %{ "xcc_P" %}
4014 #else
4015 format %{ "icc_P" %}
4016 #endif
4017 interface(REG_INTER);
4018 %}
4019
4020 // Condition Code Register, long comparisons.
4021 operand flagsRegL() %{
4022 constraint(ALLOC_IN_RC(int_flags));
4023 match(RegFlags);
4024
4025 format %{ "xcc_L" %}
4026 interface(REG_INTER);
4027 %}
4028
4029 // Condition Code Register, floating comparisons, unordered same as "less".
4030 operand flagsRegF() %{
4031 constraint(ALLOC_IN_RC(float_flags));
4032 match(RegFlags);
4033 match(flagsRegF0);
4034
4035 format %{ %}
4036 interface(REG_INTER);
4037 %}
4038
4039 operand flagsRegF0() %{
4040 constraint(ALLOC_IN_RC(float_flag0));
4041 match(RegFlags);
4042
4043 format %{ %}
4044 interface(REG_INTER);
4045 %}
4046
4047
4048 // Condition Code Flag Register used by long compare
4049 operand flagsReg_long_LTGE() %{
4050 constraint(ALLOC_IN_RC(int_flags));
4051 match(RegFlags);
4052 format %{ "icc_LTGE" %}
4053 interface(REG_INTER);
4054 %}
4055 operand flagsReg_long_EQNE() %{
4056 constraint(ALLOC_IN_RC(int_flags));
4057 match(RegFlags);
4058 format %{ "icc_EQNE" %}
4059 interface(REG_INTER);
4060 %}
4061 operand flagsReg_long_LEGT() %{
4062 constraint(ALLOC_IN_RC(int_flags));
4063 match(RegFlags);
4064 format %{ "icc_LEGT" %}
4065 interface(REG_INTER);
4066 %}
4067
4068
4069 operand regD() %{
4070 constraint(ALLOC_IN_RC(dflt_reg));
4071 match(RegD);
4072
4073 match(regD_low);
4074
4075 format %{ %}
4076 interface(REG_INTER);
4077 %}
4078
4079 operand regF() %{
4080 constraint(ALLOC_IN_RC(sflt_reg));
4081 match(RegF);
4082
4083 format %{ %}
4084 interface(REG_INTER);
4085 %}
4086
4087 operand regD_low() %{
4088 constraint(ALLOC_IN_RC(dflt_low_reg));
4089 match(regD);
4090
4091 format %{ %}
4092 interface(REG_INTER);
4093 %}
4094
4095 // Special Registers
4096
4097 // Method Register
4098 operand inline_cache_regP(iRegP reg) %{
4099 constraint(ALLOC_IN_RC(g5_regP)); // G5=inline_cache_reg but uses 2 bits instead of 1
4100 match(reg);
4101 format %{ %}
4102 interface(REG_INTER);
4103 %}
4104
4105 operand interpreter_method_oop_regP(iRegP reg) %{
4106 constraint(ALLOC_IN_RC(g5_regP)); // G5=interpreter_method_oop_reg but uses 2 bits instead of 1
4107 match(reg);
4108 format %{ %}
4109 interface(REG_INTER);
4110 %}
4111
4112
4113 //----------Complex Operands---------------------------------------------------
4114 // Indirect Memory Reference
4115 operand indirect(sp_ptr_RegP reg) %{
4116 constraint(ALLOC_IN_RC(sp_ptr_reg));
4117 match(reg);
4118
4119 op_cost(100);
4120 format %{ "[$reg]" %}
4121 interface(MEMORY_INTER) %{
4122 base($reg);
4123 index(0x0);
4124 scale(0x0);
4125 disp(0x0);
4126 %}
4127 %}
4128
4129 // Indirect with simm13 Offset
4130 operand indOffset13(sp_ptr_RegP reg, immX13 offset) %{
4131 constraint(ALLOC_IN_RC(sp_ptr_reg));
4132 match(AddP reg offset);
4133
4134 op_cost(100);
4135 format %{ "[$reg + $offset]" %}
4136 interface(MEMORY_INTER) %{
4137 base($reg);
4138 index(0x0);
4139 scale(0x0);
4140 disp($offset);
4141 %}
4142 %}
4143
4144 // Indirect with simm13 Offset minus 7
4145 operand indOffset13m7(sp_ptr_RegP reg, immX13m7 offset) %{
4146 constraint(ALLOC_IN_RC(sp_ptr_reg));
4147 match(AddP reg offset);
4148
4149 op_cost(100);
4150 format %{ "[$reg + $offset]" %}
4151 interface(MEMORY_INTER) %{
4152 base($reg);
4153 index(0x0);
4154 scale(0x0);
4155 disp($offset);
4156 %}
4157 %}
4158
4159 // Note: Intel has a swapped version also, like this:
4160 //operand indOffsetX(iRegI reg, immP offset) %{
4161 // constraint(ALLOC_IN_RC(int_reg));
4162 // match(AddP offset reg);
4163 //
4164 // op_cost(100);
4165 // format %{ "[$reg + $offset]" %}
4166 // interface(MEMORY_INTER) %{
4167 // base($reg);
4168 // index(0x0);
4169 // scale(0x0);
4170 // disp($offset);
4171 // %}
4172 //%}
4173 //// However, it doesn't make sense for SPARC, since
4174 // we have no particularly good way to embed oops in
4175 // single instructions.
4176
4177 // Indirect with Register Index
4178 operand indIndex(iRegP addr, iRegX index) %{
4179 constraint(ALLOC_IN_RC(ptr_reg));
4180 match(AddP addr index);
4181
4182 op_cost(100);
4183 format %{ "[$addr + $index]" %}
4184 interface(MEMORY_INTER) %{
4185 base($addr);
4186 index($index);
4187 scale(0x0);
4188 disp(0x0);
4189 %}
4190 %}
4191
4192 //----------Special Memory Operands--------------------------------------------
4193 // Stack Slot Operand - This operand is used for loading and storing temporary
4194 // values on the stack where a match requires a value to
4195 // flow through memory.
4196 operand stackSlotI(sRegI reg) %{
4197 constraint(ALLOC_IN_RC(stack_slots));
4198 op_cost(100);
4199 //match(RegI);
4200 format %{ "[$reg]" %}
4201 interface(MEMORY_INTER) %{
4202 base(0xE); // R_SP
4203 index(0x0);
4204 scale(0x0);
4205 disp($reg); // Stack Offset
4206 %}
4207 %}
4208
4209 operand stackSlotP(sRegP reg) %{
4210 constraint(ALLOC_IN_RC(stack_slots));
4211 op_cost(100);
4212 //match(RegP);
4213 format %{ "[$reg]" %}
4214 interface(MEMORY_INTER) %{
4215 base(0xE); // R_SP
4216 index(0x0);
4217 scale(0x0);
4218 disp($reg); // Stack Offset
4219 %}
4220 %}
4221
4222 operand stackSlotF(sRegF reg) %{
4223 constraint(ALLOC_IN_RC(stack_slots));
4224 op_cost(100);
4225 //match(RegF);
4226 format %{ "[$reg]" %}
4227 interface(MEMORY_INTER) %{
4228 base(0xE); // R_SP
4229 index(0x0);
4230 scale(0x0);
4231 disp($reg); // Stack Offset
4232 %}
4233 %}
4234 operand stackSlotD(sRegD reg) %{
4235 constraint(ALLOC_IN_RC(stack_slots));
4236 op_cost(100);
4237 //match(RegD);
4238 format %{ "[$reg]" %}
4239 interface(MEMORY_INTER) %{
4240 base(0xE); // R_SP
4241 index(0x0);
4242 scale(0x0);
4243 disp($reg); // Stack Offset
4244 %}
4245 %}
4246 operand stackSlotL(sRegL reg) %{
4247 constraint(ALLOC_IN_RC(stack_slots));
4248 op_cost(100);
4249 //match(RegL);
4250 format %{ "[$reg]" %}
4251 interface(MEMORY_INTER) %{
4252 base(0xE); // R_SP
4253 index(0x0);
4254 scale(0x0);
4255 disp($reg); // Stack Offset
4256 %}
4257 %}
4258
4259 // Operands for expressing Control Flow
4260 // NOTE: Label is a predefined operand which should not be redefined in
4261 // the AD file. It is generically handled within the ADLC.
4262
4263 //----------Conditional Branch Operands----------------------------------------
4264 // Comparison Op - This is the operation of the comparison, and is limited to
4265 // the following set of codes:
4266 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
4267 //
4268 // Other attributes of the comparison, such as unsignedness, are specified
4269 // by the comparison instruction that sets a condition code flags register.
4270 // That result is represented by a flags operand whose subtype is appropriate
4271 // to the unsignedness (etc.) of the comparison.
4272 //
4273 // Later, the instruction which matches both the Comparison Op (a Bool) and
4274 // the flags (produced by the Cmp) specifies the coding of the comparison op
4275 // by matching a specific subtype of Bool operand below, such as cmpOpU.
4276
4277 operand cmpOp() %{
4278 match(Bool);
4279
4280 format %{ "" %}
4281 interface(COND_INTER) %{
4282 equal(0x1);
4283 not_equal(0x9);
4284 less(0x3);
4285 greater_equal(0xB);
4286 less_equal(0x2);
4287 greater(0xA);
4288 %}
4289 %}
4290
4291 // Comparison Op, unsigned
4292 operand cmpOpU() %{
4293 match(Bool);
4294
4295 format %{ "u" %}
4296 interface(COND_INTER) %{
4297 equal(0x1);
4298 not_equal(0x9);
4299 less(0x5);
4300 greater_equal(0xD);
4301 less_equal(0x4);
4302 greater(0xC);
4303 %}
4304 %}
4305
4306 // Comparison Op, pointer (same as unsigned)
4307 operand cmpOpP() %{
4308 match(Bool);
4309
4310 format %{ "p" %}
4311 interface(COND_INTER) %{
4312 equal(0x1);
4313 not_equal(0x9);
4314 less(0x5);
4315 greater_equal(0xD);
4316 less_equal(0x4);
4317 greater(0xC);
4318 %}
4319 %}
4320
4321 // Comparison Op, branch-register encoding
4322 operand cmpOp_reg() %{
4323 match(Bool);
4324
4325 format %{ "" %}
4326 interface(COND_INTER) %{
4327 equal (0x1);
4328 not_equal (0x5);
4329 less (0x3);
4330 greater_equal(0x7);
4331 less_equal (0x2);
4332 greater (0x6);
4333 %}
4334 %}
4335
4336 // Comparison Code, floating, unordered same as less
4337 operand cmpOpF() %{
4338 match(Bool);
4339
4340 format %{ "fl" %}
4341 interface(COND_INTER) %{
4342 equal(0x9);
4343 not_equal(0x1);
4344 less(0x3);
4345 greater_equal(0xB);
4346 less_equal(0xE);
4347 greater(0x6);
4348 %}
4349 %}
4350
4351 // Used by long compare
4352 operand cmpOp_commute() %{
4353 match(Bool);
4354
4355 format %{ "" %}
4356 interface(COND_INTER) %{
4357 equal(0x1);
4358 not_equal(0x9);
4359 less(0xA);
4360 greater_equal(0x2);
4361 less_equal(0xB);
4362 greater(0x3);
4363 %}
4364 %}
4365
4366 //----------OPERAND CLASSES----------------------------------------------------
4367 // Operand Classes are groups of operands that are used to simplify
4368 // instruction definitions by not requiring the AD writer to specify separate
4369 // instructions for every form of operand when the instruction accepts
4370 // multiple operand types with the same basic encoding and format. The classic
4371 // case of this is memory operands.
4372 opclass memory( indirect, indOffset13, indIndex );
4373 opclass indIndexMemory( indIndex );
4374
4375 //----------PIPELINE-----------------------------------------------------------
4376 pipeline %{
4377
4378 //----------ATTRIBUTES---------------------------------------------------------
4379 attributes %{
4380 fixed_size_instructions; // Fixed size instructions
4381 branch_has_delay_slot; // Branch has delay slot following
4382 max_instructions_per_bundle = 4; // Up to 4 instructions per bundle
4383 instruction_unit_size = 4; // An instruction is 4 bytes long
4384 instruction_fetch_unit_size = 16; // The processor fetches one line
4385 instruction_fetch_units = 1; // of 16 bytes
4386
4387 // List of nop instructions
4388 nops( Nop_A0, Nop_A1, Nop_MS, Nop_FA, Nop_BR );
4389 %}
4390
4391 //----------RESOURCES----------------------------------------------------------
4392 // Resources are the functional units available to the machine
4393 resources(A0, A1, MS, BR, FA, FM, IDIV, FDIV, IALU = A0 | A1);
4394
4395 //----------PIPELINE DESCRIPTION-----------------------------------------------
4396 // Pipeline Description specifies the stages in the machine's pipeline
4397
4398 pipe_desc(A, P, F, B, I, J, S, R, E, C, M, W, X, T, D);
4399
4400 //----------PIPELINE CLASSES---------------------------------------------------
4401 // Pipeline Classes describe the stages in which input and output are
4402 // referenced by the hardware pipeline.
4403
4404 // Integer ALU reg-reg operation
4405 pipe_class ialu_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
4406 single_instruction;
4407 dst : E(write);
4408 src1 : R(read);
4409 src2 : R(read);
4410 IALU : R;
4411 %}
4412
4413 // Integer ALU reg-reg long operation
4414 pipe_class ialu_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{
4415 instruction_count(2);
4416 dst : E(write);
4417 src1 : R(read);
4418 src2 : R(read);
4419 IALU : R;
4420 IALU : R;
4421 %}
4422
4423 // Integer ALU reg-reg long dependent operation
4424 pipe_class ialu_reg_reg_2_dep(iRegL dst, iRegL src1, iRegL src2, flagsReg cr) %{
4425 instruction_count(1); multiple_bundles;
4426 dst : E(write);
4427 src1 : R(read);
4428 src2 : R(read);
4429 cr : E(write);
4430 IALU : R(2);
4431 %}
4432
4433 // Integer ALU reg-imm operaion
4434 pipe_class ialu_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{
4435 single_instruction;
4436 dst : E(write);
4437 src1 : R(read);
4438 IALU : R;
4439 %}
4440
4441 // Integer ALU reg-reg operation with condition code
4442 pipe_class ialu_cc_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{
4443 single_instruction;
4444 dst : E(write);
4445 cr : E(write);
4446 src1 : R(read);
4447 src2 : R(read);
4448 IALU : R;
4449 %}
4450
4451 // Integer ALU reg-imm operation with condition code
4452 pipe_class ialu_cc_reg_imm(iRegI dst, iRegI src1, immI13 src2, flagsReg cr) %{
4453 single_instruction;
4454 dst : E(write);
4455 cr : E(write);
4456 src1 : R(read);
4457 IALU : R;
4458 %}
4459
4460 // Integer ALU zero-reg operation
4461 pipe_class ialu_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{
4462 single_instruction;
4463 dst : E(write);
4464 src2 : R(read);
4465 IALU : R;
4466 %}
4467
4468 // Integer ALU zero-reg operation with condition code only
4469 pipe_class ialu_cconly_zero_reg(flagsReg cr, iRegI src) %{
4470 single_instruction;
4471 cr : E(write);
4472 src : R(read);
4473 IALU : R;
4474 %}
4475
4476 // Integer ALU reg-reg operation with condition code only
4477 pipe_class ialu_cconly_reg_reg(flagsReg cr, iRegI src1, iRegI src2) %{
4478 single_instruction;
4479 cr : E(write);
4480 src1 : R(read);
4481 src2 : R(read);
4482 IALU : R;
4483 %}
4484
4485 // Integer ALU reg-imm operation with condition code only
4486 pipe_class ialu_cconly_reg_imm(flagsReg cr, iRegI src1, immI13 src2) %{
4487 single_instruction;
4488 cr : E(write);
4489 src1 : R(read);
4490 IALU : R;
4491 %}
4492
4493 // Integer ALU reg-reg-zero operation with condition code only
4494 pipe_class ialu_cconly_reg_reg_zero(flagsReg cr, iRegI src1, iRegI src2, immI0 zero) %{
4495 single_instruction;
4496 cr : E(write);
4497 src1 : R(read);
4498 src2 : R(read);
4499 IALU : R;
4500 %}
4501
4502 // Integer ALU reg-imm-zero operation with condition code only
4503 pipe_class ialu_cconly_reg_imm_zero(flagsReg cr, iRegI src1, immI13 src2, immI0 zero) %{
4504 single_instruction;
4505 cr : E(write);
4506 src1 : R(read);
4507 IALU : R;
4508 %}
4509
4510 // Integer ALU reg-reg operation with condition code, src1 modified
4511 pipe_class ialu_cc_rwreg_reg(flagsReg cr, iRegI src1, iRegI src2) %{
4512 single_instruction;
4513 cr : E(write);
4514 src1 : E(write);
4515 src1 : R(read);
4516 src2 : R(read);
4517 IALU : R;
4518 %}
4519
4520 // Integer ALU reg-imm operation with condition code, src1 modified
4521 pipe_class ialu_cc_rwreg_imm(flagsReg cr, iRegI src1, immI13 src2) %{
4522 single_instruction;
4523 cr : E(write);
4524 src1 : E(write);
4525 src1 : R(read);
4526 IALU : R;
4527 %}
4528
4529 pipe_class cmpL_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg cr ) %{
4530 multiple_bundles;
4531 dst : E(write)+4;
4532 cr : E(write);
4533 src1 : R(read);
4534 src2 : R(read);
4535 IALU : R(3);
4536 BR : R(2);
4537 %}
4538
4539 // Integer ALU operation
4540 pipe_class ialu_none(iRegI dst) %{
4541 single_instruction;
4542 dst : E(write);
4543 IALU : R;
4544 %}
4545
4546 // Integer ALU reg operation
4547 pipe_class ialu_reg(iRegI dst, iRegI src) %{
4548 single_instruction; may_have_no_code;
4549 dst : E(write);
4550 src : R(read);
4551 IALU : R;
4552 %}
4553
4554 // Integer ALU reg conditional operation
4555 // This instruction has a 1 cycle stall, and cannot execute
4556 // in the same cycle as the instruction setting the condition
4557 // code. We kludge this by pretending to read the condition code
4558 // 1 cycle earlier, and by marking the functional units as busy
4559 // for 2 cycles with the result available 1 cycle later than
4560 // is really the case.
4561 pipe_class ialu_reg_flags( iRegI op2_out, iRegI op2_in, iRegI op1, flagsReg cr ) %{
4562 single_instruction;
4563 op2_out : C(write);
4564 op1 : R(read);
4565 cr : R(read); // This is really E, with a 1 cycle stall
4566 BR : R(2);
4567 MS : R(2);
4568 %}
4569
4570 #ifdef _LP64
4571 pipe_class ialu_clr_and_mover( iRegI dst, iRegP src ) %{
4572 instruction_count(1); multiple_bundles;
4573 dst : C(write)+1;
4574 src : R(read)+1;
4575 IALU : R(1);
4576 BR : E(2);
4577 MS : E(2);
4578 %}
4579 #endif
4580
4581 // Integer ALU reg operation
4582 pipe_class ialu_move_reg_L_to_I(iRegI dst, iRegL src) %{
4583 single_instruction; may_have_no_code;
4584 dst : E(write);
4585 src : R(read);
4586 IALU : R;
4587 %}
4588 pipe_class ialu_move_reg_I_to_L(iRegL dst, iRegI src) %{
4589 single_instruction; may_have_no_code;
4590 dst : E(write);
4591 src : R(read);
4592 IALU : R;
4593 %}
4594
4595 // Two integer ALU reg operations
4596 pipe_class ialu_reg_2(iRegL dst, iRegL src) %{
4597 instruction_count(2);
4598 dst : E(write);
4599 src : R(read);
4600 A0 : R;
4601 A1 : R;
4602 %}
4603
4604 // Two integer ALU reg operations
4605 pipe_class ialu_move_reg_L_to_L(iRegL dst, iRegL src) %{
4606 instruction_count(2); may_have_no_code;
4607 dst : E(write);
4608 src : R(read);
4609 A0 : R;
4610 A1 : R;
4611 %}
4612
4613 // Integer ALU imm operation
4614 pipe_class ialu_imm(iRegI dst, immI13 src) %{
4615 single_instruction;
4616 dst : E(write);
4617 IALU : R;
4618 %}
4619
4620 // Integer ALU reg-reg with carry operation
4621 pipe_class ialu_reg_reg_cy(iRegI dst, iRegI src1, iRegI src2, iRegI cy) %{
4622 single_instruction;
4623 dst : E(write);
4624 src1 : R(read);
4625 src2 : R(read);
4626 IALU : R;
4627 %}
4628
4629 // Integer ALU cc operation
4630 pipe_class ialu_cc(iRegI dst, flagsReg cc) %{
4631 single_instruction;
4632 dst : E(write);
4633 cc : R(read);
4634 IALU : R;
4635 %}
4636
4637 // Integer ALU cc / second IALU operation
4638 pipe_class ialu_reg_ialu( iRegI dst, iRegI src ) %{
4639 instruction_count(1); multiple_bundles;
4640 dst : E(write)+1;
4641 src : R(read);
4642 IALU : R;
4643 %}
4644
4645 // Integer ALU cc / second IALU operation
4646 pipe_class ialu_reg_reg_ialu( iRegI dst, iRegI p, iRegI q ) %{
4647 instruction_count(1); multiple_bundles;
4648 dst : E(write)+1;
4649 p : R(read);
4650 q : R(read);
4651 IALU : R;
4652 %}
4653
4654 // Integer ALU hi-lo-reg operation
4655 pipe_class ialu_hi_lo_reg(iRegI dst, immI src) %{
4656 instruction_count(1); multiple_bundles;
4657 dst : E(write)+1;
4658 IALU : R(2);
4659 %}
4660
4661 // Float ALU hi-lo-reg operation (with temp)
4662 pipe_class ialu_hi_lo_reg_temp(regF dst, immF src, g3RegP tmp) %{
4663 instruction_count(1); multiple_bundles;
4664 dst : E(write)+1;
4665 IALU : R(2);
4666 %}
4667
4668 // Long Constant
4669 pipe_class loadConL( iRegL dst, immL src ) %{
4670 instruction_count(2); multiple_bundles;
4671 dst : E(write)+1;
4672 IALU : R(2);
4673 IALU : R(2);
4674 %}
4675
4676 // Pointer Constant
4677 pipe_class loadConP( iRegP dst, immP src ) %{
4678 instruction_count(0); multiple_bundles;
4679 fixed_latency(6);
4680 %}
4681
4682 // Polling Address
4683 pipe_class loadConP_poll( iRegP dst, immP_poll src ) %{
4684 #ifdef _LP64
4685 instruction_count(0); multiple_bundles;
4686 fixed_latency(6);
4687 #else
4688 dst : E(write);
4689 IALU : R;
4690 #endif
4691 %}
4692
4693 // Long Constant small
4694 pipe_class loadConLlo( iRegL dst, immL src ) %{
4695 instruction_count(2);
4696 dst : E(write);
4697 IALU : R;
4698 IALU : R;
4699 %}
4700
4701 // [PHH] This is wrong for 64-bit. See LdImmF/D.
4702 pipe_class loadConFD(regF dst, immF src, g3RegP tmp) %{
4703 instruction_count(1); multiple_bundles;
4704 src : R(read);
4705 dst : M(write)+1;
4706 IALU : R;
4707 MS : E;
4708 %}
4709
4710 // Integer ALU nop operation
4711 pipe_class ialu_nop() %{
4712 single_instruction;
4713 IALU : R;
4714 %}
4715
4716 // Integer ALU nop operation
4717 pipe_class ialu_nop_A0() %{
4718 single_instruction;
4719 A0 : R;
4720 %}
4721
4722 // Integer ALU nop operation
4723 pipe_class ialu_nop_A1() %{
4724 single_instruction;
4725 A1 : R;
4726 %}
4727
4728 // Integer Multiply reg-reg operation
4729 pipe_class imul_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
4730 single_instruction;
4731 dst : E(write);
4732 src1 : R(read);
4733 src2 : R(read);
4734 MS : R(5);
4735 %}
4736
4737 // Integer Multiply reg-imm operation
4738 pipe_class imul_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{
4739 single_instruction;
4740 dst : E(write);
4741 src1 : R(read);
4742 MS : R(5);
4743 %}
4744
4745 pipe_class mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
4746 single_instruction;
4747 dst : E(write)+4;
4748 src1 : R(read);
4749 src2 : R(read);
4750 MS : R(6);
4751 %}
4752
4753 pipe_class mulL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{
4754 single_instruction;
4755 dst : E(write)+4;
4756 src1 : R(read);
4757 MS : R(6);
4758 %}
4759
4760 // Integer Divide reg-reg
4761 pipe_class sdiv_reg_reg(iRegI dst, iRegI src1, iRegI src2, iRegI temp, flagsReg cr) %{
4762 instruction_count(1); multiple_bundles;
4763 dst : E(write);
4764 temp : E(write);
4765 src1 : R(read);
4766 src2 : R(read);
4767 temp : R(read);
4768 MS : R(38);
4769 %}
4770
4771 // Integer Divide reg-imm
4772 pipe_class sdiv_reg_imm(iRegI dst, iRegI src1, immI13 src2, iRegI temp, flagsReg cr) %{
4773 instruction_count(1); multiple_bundles;
4774 dst : E(write);
4775 temp : E(write);
4776 src1 : R(read);
4777 temp : R(read);
4778 MS : R(38);
4779 %}
4780
4781 // Long Divide
4782 pipe_class divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
4783 dst : E(write)+71;
4784 src1 : R(read);
4785 src2 : R(read)+1;
4786 MS : R(70);
4787 %}
4788
4789 pipe_class divL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{
4790 dst : E(write)+71;
4791 src1 : R(read);
4792 MS : R(70);
4793 %}
4794
4795 // Floating Point Add Float
4796 pipe_class faddF_reg_reg(regF dst, regF src1, regF src2) %{
4797 single_instruction;
4798 dst : X(write);
4799 src1 : E(read);
4800 src2 : E(read);
4801 FA : R;
4802 %}
4803
4804 // Floating Point Add Double
4805 pipe_class faddD_reg_reg(regD dst, regD src1, regD src2) %{
4806 single_instruction;
4807 dst : X(write);
4808 src1 : E(read);
4809 src2 : E(read);
4810 FA : R;
4811 %}
4812
4813 // Floating Point Conditional Move based on integer flags
4814 pipe_class int_conditional_float_move (cmpOp cmp, flagsReg cr, regF dst, regF src) %{
4815 single_instruction;
4816 dst : X(write);
4817 src : E(read);
4818 cr : R(read);
4819 FA : R(2);
4820 BR : R(2);
4821 %}
4822
4823 // Floating Point Conditional Move based on integer flags
4824 pipe_class int_conditional_double_move (cmpOp cmp, flagsReg cr, regD dst, regD src) %{
4825 single_instruction;
4826 dst : X(write);
4827 src : E(read);
4828 cr : R(read);
4829 FA : R(2);
4830 BR : R(2);
4831 %}
4832
4833 // Floating Point Multiply Float
4834 pipe_class fmulF_reg_reg(regF dst, regF src1, regF src2) %{
4835 single_instruction;
4836 dst : X(write);
4837 src1 : E(read);
4838 src2 : E(read);
4839 FM : R;
4840 %}
4841
4842 // Floating Point Multiply Double
4843 pipe_class fmulD_reg_reg(regD dst, regD src1, regD src2) %{
4844 single_instruction;
4845 dst : X(write);
4846 src1 : E(read);
4847 src2 : E(read);
4848 FM : R;
4849 %}
4850
4851 // Floating Point Divide Float
4852 pipe_class fdivF_reg_reg(regF dst, regF src1, regF src2) %{
4853 single_instruction;
4854 dst : X(write);
4855 src1 : E(read);
4856 src2 : E(read);
4857 FM : R;
4858 FDIV : C(14);
4859 %}
4860
4861 // Floating Point Divide Double
4862 pipe_class fdivD_reg_reg(regD dst, regD src1, regD src2) %{
4863 single_instruction;
4864 dst : X(write);
4865 src1 : E(read);
4866 src2 : E(read);
4867 FM : R;
4868 FDIV : C(17);
4869 %}
4870
4871 // Floating Point Move/Negate/Abs Float
4872 pipe_class faddF_reg(regF dst, regF src) %{
4873 single_instruction;
4874 dst : W(write);
4875 src : E(read);
4876 FA : R(1);
4877 %}
4878
4879 // Floating Point Move/Negate/Abs Double
4880 pipe_class faddD_reg(regD dst, regD src) %{
4881 single_instruction;
4882 dst : W(write);
4883 src : E(read);
4884 FA : R;
4885 %}
4886
4887 // Floating Point Convert F->D
4888 pipe_class fcvtF2D(regD dst, regF src) %{
4889 single_instruction;
4890 dst : X(write);
4891 src : E(read);
4892 FA : R;
4893 %}
4894
4895 // Floating Point Convert I->D
4896 pipe_class fcvtI2D(regD dst, regF src) %{
4897 single_instruction;
4898 dst : X(write);
4899 src : E(read);
4900 FA : R;
4901 %}
4902
4903 // Floating Point Convert LHi->D
4904 pipe_class fcvtLHi2D(regD dst, regD src) %{
4905 single_instruction;
4906 dst : X(write);
4907 src : E(read);
4908 FA : R;
4909 %}
4910
4911 // Floating Point Convert L->D
4912 pipe_class fcvtL2D(regD dst, regF src) %{
4913 single_instruction;
4914 dst : X(write);
4915 src : E(read);
4916 FA : R;
4917 %}
4918
4919 // Floating Point Convert L->F
4920 pipe_class fcvtL2F(regD dst, regF src) %{
4921 single_instruction;
4922 dst : X(write);
4923 src : E(read);
4924 FA : R;
4925 %}
4926
4927 // Floating Point Convert D->F
4928 pipe_class fcvtD2F(regD dst, regF src) %{
4929 single_instruction;
4930 dst : X(write);
4931 src : E(read);
4932 FA : R;
4933 %}
4934
4935 // Floating Point Convert I->L
4936 pipe_class fcvtI2L(regD dst, regF src) %{
4937 single_instruction;
4938 dst : X(write);
4939 src : E(read);
4940 FA : R;
4941 %}
4942
4943 // Floating Point Convert D->F
4944 pipe_class fcvtD2I(regF dst, regD src, flagsReg cr) %{
4945 instruction_count(1); multiple_bundles;
4946 dst : X(write)+6;
4947 src : E(read);
4948 FA : R;
4949 %}
4950
4951 // Floating Point Convert D->L
4952 pipe_class fcvtD2L(regD dst, regD src, flagsReg cr) %{
4953 instruction_count(1); multiple_bundles;
4954 dst : X(write)+6;
4955 src : E(read);
4956 FA : R;
4957 %}
4958
4959 // Floating Point Convert F->I
4960 pipe_class fcvtF2I(regF dst, regF src, flagsReg cr) %{
4961 instruction_count(1); multiple_bundles;
4962 dst : X(write)+6;
4963 src : E(read);
4964 FA : R;
4965 %}
4966
4967 // Floating Point Convert F->L
4968 pipe_class fcvtF2L(regD dst, regF src, flagsReg cr) %{
4969 instruction_count(1); multiple_bundles;
4970 dst : X(write)+6;
4971 src : E(read);
4972 FA : R;
4973 %}
4974
4975 // Floating Point Convert I->F
4976 pipe_class fcvtI2F(regF dst, regF src) %{
4977 single_instruction;
4978 dst : X(write);
4979 src : E(read);
4980 FA : R;
4981 %}
4982
4983 // Floating Point Compare
4984 pipe_class faddF_fcc_reg_reg_zero(flagsRegF cr, regF src1, regF src2, immI0 zero) %{
4985 single_instruction;
4986 cr : X(write);
4987 src1 : E(read);
4988 src2 : E(read);
4989 FA : R;
4990 %}
4991
4992 // Floating Point Compare
4993 pipe_class faddD_fcc_reg_reg_zero(flagsRegF cr, regD src1, regD src2, immI0 zero) %{
4994 single_instruction;
4995 cr : X(write);
4996 src1 : E(read);
4997 src2 : E(read);
4998 FA : R;
4999 %}
5000
5001 // Floating Add Nop
5002 pipe_class fadd_nop() %{
5003 single_instruction;
5004 FA : R;
5005 %}
5006
5007 // Integer Store to Memory
5008 pipe_class istore_mem_reg(memory mem, iRegI src) %{
5009 single_instruction;
5010 mem : R(read);
5011 src : C(read);
5012 MS : R;
5013 %}
5014
5015 // Integer Store to Memory
5016 pipe_class istore_mem_spORreg(memory mem, sp_ptr_RegP src) %{
5017 single_instruction;
5018 mem : R(read);
5019 src : C(read);
5020 MS : R;
5021 %}
5022
5023 // Integer Store Zero to Memory
5024 pipe_class istore_mem_zero(memory mem, immI0 src) %{
5025 single_instruction;
5026 mem : R(read);
5027 MS : R;
5028 %}
5029
5030 // Special Stack Slot Store
5031 pipe_class istore_stk_reg(stackSlotI stkSlot, iRegI src) %{
5032 single_instruction;
5033 stkSlot : R(read);
5034 src : C(read);
5035 MS : R;
5036 %}
5037
5038 // Special Stack Slot Store
5039 pipe_class lstoreI_stk_reg(stackSlotL stkSlot, iRegI src) %{
5040 instruction_count(2); multiple_bundles;
5041 stkSlot : R(read);
5042 src : C(read);
5043 MS : R(2);
5044 %}
5045
5046 // Float Store
5047 pipe_class fstoreF_mem_reg(memory mem, RegF src) %{
5048 single_instruction;
5049 mem : R(read);
5050 src : C(read);
5051 MS : R;
5052 %}
5053
5054 // Float Store
5055 pipe_class fstoreF_mem_zero(memory mem, immF0 src) %{
5056 single_instruction;
5057 mem : R(read);
5058 MS : R;
5059 %}
5060
5061 // Double Store
5062 pipe_class fstoreD_mem_reg(memory mem, RegD src) %{
5063 instruction_count(1);
5064 mem : R(read);
5065 src : C(read);
5066 MS : R;
5067 %}
5068
5069 // Double Store
5070 pipe_class fstoreD_mem_zero(memory mem, immD0 src) %{
5071 single_instruction;
5072 mem : R(read);
5073 MS : R;
5074 %}
5075
5076 // Special Stack Slot Float Store
5077 pipe_class fstoreF_stk_reg(stackSlotI stkSlot, RegF src) %{
5078 single_instruction;
5079 stkSlot : R(read);
5080 src : C(read);
5081 MS : R;
5082 %}
5083
5084 // Special Stack Slot Double Store
5085 pipe_class fstoreD_stk_reg(stackSlotI stkSlot, RegD src) %{
5086 single_instruction;
5087 stkSlot : R(read);
5088 src : C(read);
5089 MS : R;
5090 %}
5091
5092 // Integer Load (when sign bit propagation not needed)
5093 pipe_class iload_mem(iRegI dst, memory mem) %{
5094 single_instruction;
5095 mem : R(read);
5096 dst : C(write);
5097 MS : R;
5098 %}
5099
5100 // Integer Load from stack operand
5101 pipe_class iload_stkD(iRegI dst, stackSlotD mem ) %{
5102 single_instruction;
5103 mem : R(read);
5104 dst : C(write);
5105 MS : R;
5106 %}
5107
5108 // Integer Load (when sign bit propagation or masking is needed)
5109 pipe_class iload_mask_mem(iRegI dst, memory mem) %{
5110 single_instruction;
5111 mem : R(read);
5112 dst : M(write);
5113 MS : R;
5114 %}
5115
5116 // Float Load
5117 pipe_class floadF_mem(regF dst, memory mem) %{
5118 single_instruction;
5119 mem : R(read);
5120 dst : M(write);
5121 MS : R;
5122 %}
5123
5124 // Float Load
5125 pipe_class floadD_mem(regD dst, memory mem) %{
5126 instruction_count(1); multiple_bundles; // Again, unaligned argument is only multiple case
5127 mem : R(read);
5128 dst : M(write);
5129 MS : R;
5130 %}
5131
5132 // Float Load
5133 pipe_class floadF_stk(regF dst, stackSlotI stkSlot) %{
5134 single_instruction;
5135 stkSlot : R(read);
5136 dst : M(write);
5137 MS : R;
5138 %}
5139
5140 // Float Load
5141 pipe_class floadD_stk(regD dst, stackSlotI stkSlot) %{
5142 single_instruction;
5143 stkSlot : R(read);
5144 dst : M(write);
5145 MS : R;
5146 %}
5147
5148 // Memory Nop
5149 pipe_class mem_nop() %{
5150 single_instruction;
5151 MS : R;
5152 %}
5153
5154 pipe_class sethi(iRegP dst, immI src) %{
5155 single_instruction;
5156 dst : E(write);
5157 IALU : R;
5158 %}
5159
5160 pipe_class loadPollP(iRegP poll) %{
5161 single_instruction;
5162 poll : R(read);
5163 MS : R;
5164 %}
5165
5166 pipe_class br(Universe br, label labl) %{
5167 single_instruction_with_delay_slot;
5168 BR : R;
5169 %}
5170
5171 pipe_class br_cc(Universe br, cmpOp cmp, flagsReg cr, label labl) %{
5172 single_instruction_with_delay_slot;
5173 cr : E(read);
5174 BR : R;
5175 %}
5176
5177 pipe_class br_reg(Universe br, cmpOp cmp, iRegI op1, label labl) %{
5178 single_instruction_with_delay_slot;
5179 op1 : E(read);
5180 BR : R;
5181 MS : R;
5182 %}
5183
5184 pipe_class br_fcc(Universe br, cmpOpF cc, flagsReg cr, label labl) %{
5185 single_instruction_with_delay_slot;
5186 cr : E(read);
5187 BR : R;
5188 %}
5189
5190 pipe_class br_nop() %{
5191 single_instruction;
5192 BR : R;
5193 %}
5194
5195 pipe_class simple_call(method meth) %{
5196 instruction_count(2); multiple_bundles; force_serialization;
5197 fixed_latency(100);
5198 BR : R(1);
5199 MS : R(1);
5200 A0 : R(1);
5201 %}
5202
5203 pipe_class compiled_call(method meth) %{
5204 instruction_count(1); multiple_bundles; force_serialization;
5205 fixed_latency(100);
5206 MS : R(1);
5207 %}
5208
5209 pipe_class call(method meth) %{
5210 instruction_count(0); multiple_bundles; force_serialization;
5211 fixed_latency(100);
5212 %}
5213
5214 pipe_class tail_call(Universe ignore, label labl) %{
5215 single_instruction; has_delay_slot;
5216 fixed_latency(100);
5217 BR : R(1);
5218 MS : R(1);
5219 %}
5220
5221 pipe_class ret(Universe ignore) %{
5222 single_instruction; has_delay_slot;
5223 BR : R(1);
5224 MS : R(1);
5225 %}
5226
5227 pipe_class ret_poll(g3RegP poll) %{
5228 instruction_count(3); has_delay_slot;
5229 poll : E(read);
5230 MS : R;
5231 %}
5232
5233 // The real do-nothing guy
5234 pipe_class empty( ) %{
5235 instruction_count(0);
5236 %}
5237
5238 pipe_class long_memory_op() %{
5239 instruction_count(0); multiple_bundles; force_serialization;
5240 fixed_latency(25);
5241 MS : R(1);
5242 %}
5243
5244 // Check-cast
5245 pipe_class partial_subtype_check_pipe(Universe ignore, iRegP array, iRegP match ) %{
5246 array : R(read);
5247 match : R(read);
5248 IALU : R(2);
5249 BR : R(2);
5250 MS : R;
5251 %}
5252
5253 // Convert FPU flags into +1,0,-1
5254 pipe_class floating_cmp( iRegI dst, regF src1, regF src2 ) %{
5255 src1 : E(read);
5256 src2 : E(read);
5257 dst : E(write);
5258 FA : R;
5259 MS : R(2);
5260 BR : R(2);
5261 %}
5262
5263 // Compare for p < q, and conditionally add y
5264 pipe_class cadd_cmpltmask( iRegI p, iRegI q, iRegI y ) %{
5265 p : E(read);
5266 q : E(read);
5267 y : E(read);
5268 IALU : R(3)
5269 %}
5270
5271 // Perform a compare, then move conditionally in a branch delay slot.
5272 pipe_class min_max( iRegI src2, iRegI srcdst ) %{
5273 src2 : E(read);
5274 srcdst : E(read);
5275 IALU : R;
5276 BR : R;
5277 %}
5278
5279 // Define the class for the Nop node
5280 define %{
5281 MachNop = ialu_nop;
5282 %}
5283
5284 %}
5285
5286 //----------INSTRUCTIONS-------------------------------------------------------
5287
5288 //------------Special Stack Slot instructions - no match rules-----------------
5289 instruct stkI_to_regF(regF dst, stackSlotI src) %{
5290 // No match rule to avoid chain rule match.
5291 effect(DEF dst, USE src);
5292 ins_cost(MEMORY_REF_COST);
5293 size(4);
5294 format %{ "LDF $src,$dst\t! stkI to regF" %}
5295 opcode(Assembler::ldf_op3);
5296 ins_encode(simple_form3_mem_reg(src, dst));
5297 ins_pipe(floadF_stk);
5298 %}
5299
5300 instruct stkL_to_regD(regD dst, stackSlotL src) %{
5301 // No match rule to avoid chain rule match.
5302 effect(DEF dst, USE src);
5303 ins_cost(MEMORY_REF_COST);
5304 size(4);
5305 format %{ "LDDF $src,$dst\t! stkL to regD" %}
5306 opcode(Assembler::lddf_op3);
5307 ins_encode(simple_form3_mem_reg(src, dst));
5308 ins_pipe(floadD_stk);
5309 %}
5310
5311 instruct regF_to_stkI(stackSlotI dst, regF src) %{
5312 // No match rule to avoid chain rule match.
5313 effect(DEF dst, USE src);
5314 ins_cost(MEMORY_REF_COST);
5315 size(4);
5316 format %{ "STF $src,$dst\t! regF to stkI" %}
5317 opcode(Assembler::stf_op3);
5318 ins_encode(simple_form3_mem_reg(dst, src));
5319 ins_pipe(fstoreF_stk_reg);
5320 %}
5321
5322 instruct regD_to_stkL(stackSlotL dst, regD src) %{
5323 // No match rule to avoid chain rule match.
5324 effect(DEF dst, USE src);
5325 ins_cost(MEMORY_REF_COST);
5326 size(4);
5327 format %{ "STDF $src,$dst\t! regD to stkL" %}
5328 opcode(Assembler::stdf_op3);
5329 ins_encode(simple_form3_mem_reg(dst, src));
5330 ins_pipe(fstoreD_stk_reg);
5331 %}
5332
5333 instruct regI_to_stkLHi(stackSlotL dst, iRegI src) %{
5334 effect(DEF dst, USE src);
5335 ins_cost(MEMORY_REF_COST*2);
5336 size(8);
5337 format %{ "STW $src,$dst.hi\t! long\n\t"
5338 "STW R_G0,$dst.lo" %}
5339 opcode(Assembler::stw_op3);
5340 ins_encode(simple_form3_mem_reg(dst, src), form3_mem_plus_4_reg(dst, R_G0));
5341 ins_pipe(lstoreI_stk_reg);
5342 %}
5343
5344 instruct regL_to_stkD(stackSlotD dst, iRegL src) %{
5345 // No match rule to avoid chain rule match.
5346 effect(DEF dst, USE src);
5347 ins_cost(MEMORY_REF_COST);
5348 size(4);
5349 format %{ "STX $src,$dst\t! regL to stkD" %}
5350 opcode(Assembler::stx_op3);
5351 ins_encode(simple_form3_mem_reg( dst, src ) );
5352 ins_pipe(istore_stk_reg);
5353 %}
5354
5355 //---------- Chain stack slots between similar types --------
5356
5357 // Load integer from stack slot
5358 instruct stkI_to_regI( iRegI dst, stackSlotI src ) %{
5359 match(Set dst src);
5360 ins_cost(MEMORY_REF_COST);
5361
5362 size(4);
5363 format %{ "LDUW $src,$dst\t!stk" %}
5364 opcode(Assembler::lduw_op3);
5365 ins_encode(simple_form3_mem_reg( src, dst ) );
5366 ins_pipe(iload_mem);
5367 %}
5368
5369 // Store integer to stack slot
5370 instruct regI_to_stkI( stackSlotI dst, iRegI src ) %{
5371 match(Set dst src);
5372 ins_cost(MEMORY_REF_COST);
5373
5374 size(4);
5375 format %{ "STW $src,$dst\t!stk" %}
5376 opcode(Assembler::stw_op3);
5377 ins_encode(simple_form3_mem_reg( dst, src ) );
5378 ins_pipe(istore_mem_reg);
5379 %}
5380
5381 // Load long from stack slot
5382 instruct stkL_to_regL( iRegL dst, stackSlotL src ) %{
5383 match(Set dst src);
5384
5385 ins_cost(MEMORY_REF_COST);
5386 size(4);
5387 format %{ "LDX $src,$dst\t! long" %}
5388 opcode(Assembler::ldx_op3);
5389 ins_encode(simple_form3_mem_reg( src, dst ) );
5390 ins_pipe(iload_mem);
5391 %}
5392
5393 // Store long to stack slot
5394 instruct regL_to_stkL(stackSlotL dst, iRegL src) %{
5395 match(Set dst src);
5396
5397 ins_cost(MEMORY_REF_COST);
5398 size(4);
5399 format %{ "STX $src,$dst\t! long" %}
5400 opcode(Assembler::stx_op3);
5401 ins_encode(simple_form3_mem_reg( dst, src ) );
5402 ins_pipe(istore_mem_reg);
5403 %}
5404
5405 #ifdef _LP64
5406 // Load pointer from stack slot, 64-bit encoding
5407 instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{
5408 match(Set dst src);
5409 ins_cost(MEMORY_REF_COST);
5410 size(4);
5411 format %{ "LDX $src,$dst\t!ptr" %}
5412 opcode(Assembler::ldx_op3);
5413 ins_encode(simple_form3_mem_reg( src, dst ) );
5414 ins_pipe(iload_mem);
5415 %}
5416
5417 // Store pointer to stack slot
5418 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{
5419 match(Set dst src);
5420 ins_cost(MEMORY_REF_COST);
5421 size(4);
5422 format %{ "STX $src,$dst\t!ptr" %}
5423 opcode(Assembler::stx_op3);
5424 ins_encode(simple_form3_mem_reg( dst, src ) );
5425 ins_pipe(istore_mem_reg);
5426 %}
5427 #else // _LP64
5428 // Load pointer from stack slot, 32-bit encoding
5429 instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{
5430 match(Set dst src);
5431 ins_cost(MEMORY_REF_COST);
5432 format %{ "LDUW $src,$dst\t!ptr" %}
5433 opcode(Assembler::lduw_op3, Assembler::ldst_op);
5434 ins_encode(simple_form3_mem_reg( src, dst ) );
5435 ins_pipe(iload_mem);
5436 %}
5437
5438 // Store pointer to stack slot
5439 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{
5440 match(Set dst src);
5441 ins_cost(MEMORY_REF_COST);
5442 format %{ "STW $src,$dst\t!ptr" %}
5443 opcode(Assembler::stw_op3, Assembler::ldst_op);
5444 ins_encode(simple_form3_mem_reg( dst, src ) );
5445 ins_pipe(istore_mem_reg);
5446 %}
5447 #endif // _LP64
5448
5449 //------------Special Nop instructions for bundling - no match rules-----------
5450 // Nop using the A0 functional unit
5451 instruct Nop_A0() %{
5452 ins_cost(0);
5453
5454 format %{ "NOP ! Alu Pipeline" %}
5455 opcode(Assembler::or_op3, Assembler::arith_op);
5456 ins_encode( form2_nop() );
5457 ins_pipe(ialu_nop_A0);
5458 %}
5459
5460 // Nop using the A1 functional unit
5461 instruct Nop_A1( ) %{
5462 ins_cost(0);
5463
5464 format %{ "NOP ! Alu Pipeline" %}
5465 opcode(Assembler::or_op3, Assembler::arith_op);
5466 ins_encode( form2_nop() );
5467 ins_pipe(ialu_nop_A1);
5468 %}
5469
5470 // Nop using the memory functional unit
5471 instruct Nop_MS( ) %{
5472 ins_cost(0);
5473
5474 format %{ "NOP ! Memory Pipeline" %}
5475 ins_encode( emit_mem_nop );
5476 ins_pipe(mem_nop);
5477 %}
5478
5479 // Nop using the floating add functional unit
5480 instruct Nop_FA( ) %{
5481 ins_cost(0);
5482
5483 format %{ "NOP ! Floating Add Pipeline" %}
5484 ins_encode( emit_fadd_nop );
5485 ins_pipe(fadd_nop);
5486 %}
5487
5488 // Nop using the branch functional unit
5489 instruct Nop_BR( ) %{
5490 ins_cost(0);
5491
5492 format %{ "NOP ! Branch Pipeline" %}
5493 ins_encode( emit_br_nop );
5494 ins_pipe(br_nop);
5495 %}
5496
5497 //----------Load/Store/Move Instructions---------------------------------------
5498 //----------Load Instructions--------------------------------------------------
5499 // Load Byte (8bit signed)
5500 instruct loadB(iRegI dst, memory mem) %{
5501 match(Set dst (LoadB mem));
5502 ins_cost(MEMORY_REF_COST);
5503
5504 size(4);
5505 format %{ "LDSB $mem,$dst\t! byte" %}
5506 ins_encode %{
5507 __ ldsb($mem$$Address, $dst$$Register);
5508 %}
5509 ins_pipe(iload_mask_mem);
5510 %}
5511
5512 // Load Byte (8bit signed) into a Long Register
5513 instruct loadB2L(iRegL dst, memory mem) %{
5514 match(Set dst (ConvI2L (LoadB mem)));
5515 ins_cost(MEMORY_REF_COST);
5516
5517 size(4);
5518 format %{ "LDSB $mem,$dst\t! byte -> long" %}
5519 ins_encode %{
5520 __ ldsb($mem$$Address, $dst$$Register);
5521 %}
5522 ins_pipe(iload_mask_mem);
5523 %}
5524
5525 // Load Unsigned Byte (8bit UNsigned) into an int reg
5526 instruct loadUB(iRegI dst, memory mem) %{
5527 match(Set dst (LoadUB mem));
5528 ins_cost(MEMORY_REF_COST);
5529
5530 size(4);
5531 format %{ "LDUB $mem,$dst\t! ubyte" %}
5532 ins_encode %{
5533 __ ldub($mem$$Address, $dst$$Register);
5534 %}
5535 ins_pipe(iload_mem);
5536 %}
5537
5538 // Load Unsigned Byte (8bit UNsigned) into a Long Register
5539 instruct loadUB2L(iRegL dst, memory mem) %{
5540 match(Set dst (ConvI2L (LoadUB mem)));
5541 ins_cost(MEMORY_REF_COST);
5542
5543 size(4);
5544 format %{ "LDUB $mem,$dst\t! ubyte -> long" %}
5545 ins_encode %{
5546 __ ldub($mem$$Address, $dst$$Register);
5547 %}
5548 ins_pipe(iload_mem);
5549 %}
5550
5551 // Load Unsigned Byte (8 bit UNsigned) with 8-bit mask into Long Register
5552 instruct loadUB2L_immI8(iRegL dst, memory mem, immI8 mask) %{
5553 match(Set dst (ConvI2L (AndI (LoadUB mem) mask)));
5554 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5555
5556 size(2*4);
5557 format %{ "LDUB $mem,$dst\t# ubyte & 8-bit mask -> long\n\t"
5558 "AND $dst,$mask,$dst" %}
5559 ins_encode %{
5560 __ ldub($mem$$Address, $dst$$Register);
5561 __ and3($dst$$Register, $mask$$constant, $dst$$Register);
5562 %}
5563 ins_pipe(iload_mem);
5564 %}
5565
5566 // Load Short (16bit signed)
5567 instruct loadS(iRegI dst, memory mem) %{
5568 match(Set dst (LoadS mem));
5569 ins_cost(MEMORY_REF_COST);
5570
5571 size(4);
5572 format %{ "LDSH $mem,$dst\t! short" %}
5573 ins_encode %{
5574 __ ldsh($mem$$Address, $dst$$Register);
5575 %}
5576 ins_pipe(iload_mask_mem);
5577 %}
5578
5579 // Load Short (16 bit signed) to Byte (8 bit signed)
5580 instruct loadS2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{
5581 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour));
5582 ins_cost(MEMORY_REF_COST);
5583
5584 size(4);
5585
5586 format %{ "LDSB $mem+1,$dst\t! short -> byte" %}
5587 ins_encode %{
5588 __ ldsb($mem$$Address, $dst$$Register, 1);
5589 %}
5590 ins_pipe(iload_mask_mem);
5591 %}
5592
5593 // Load Short (16bit signed) into a Long Register
5594 instruct loadS2L(iRegL dst, memory mem) %{
5595 match(Set dst (ConvI2L (LoadS mem)));
5596 ins_cost(MEMORY_REF_COST);
5597
5598 size(4);
5599 format %{ "LDSH $mem,$dst\t! short -> long" %}
5600 ins_encode %{
5601 __ ldsh($mem$$Address, $dst$$Register);
5602 %}
5603 ins_pipe(iload_mask_mem);
5604 %}
5605
5606 // Load Unsigned Short/Char (16bit UNsigned)
5607 instruct loadUS(iRegI dst, memory mem) %{
5608 match(Set dst (LoadUS mem));
5609 ins_cost(MEMORY_REF_COST);
5610
5611 size(4);
5612 format %{ "LDUH $mem,$dst\t! ushort/char" %}
5613 ins_encode %{
5614 __ lduh($mem$$Address, $dst$$Register);
5615 %}
5616 ins_pipe(iload_mem);
5617 %}
5618
5619 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed)
5620 instruct loadUS2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{
5621 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour));
5622 ins_cost(MEMORY_REF_COST);
5623
5624 size(4);
5625 format %{ "LDSB $mem+1,$dst\t! ushort -> byte" %}
5626 ins_encode %{
5627 __ ldsb($mem$$Address, $dst$$Register, 1);
5628 %}
5629 ins_pipe(iload_mask_mem);
5630 %}
5631
5632 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register
5633 instruct loadUS2L(iRegL dst, memory mem) %{
5634 match(Set dst (ConvI2L (LoadUS mem)));
5635 ins_cost(MEMORY_REF_COST);
5636
5637 size(4);
5638 format %{ "LDUH $mem,$dst\t! ushort/char -> long" %}
5639 ins_encode %{
5640 __ lduh($mem$$Address, $dst$$Register);
5641 %}
5642 ins_pipe(iload_mem);
5643 %}
5644
5645 // Load Unsigned Short/Char (16bit UNsigned) with mask 0xFF into a Long Register
5646 instruct loadUS2L_immI_255(iRegL dst, indOffset13m7 mem, immI_255 mask) %{
5647 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5648 ins_cost(MEMORY_REF_COST);
5649
5650 size(4);
5651 format %{ "LDUB $mem+1,$dst\t! ushort/char & 0xFF -> long" %}
5652 ins_encode %{
5653 __ ldub($mem$$Address, $dst$$Register, 1); // LSB is index+1 on BE
5654 %}
5655 ins_pipe(iload_mem);
5656 %}
5657
5658 // Load Unsigned Short/Char (16bit UNsigned) with a 13-bit mask into a Long Register
5659 instruct loadUS2L_immI13(iRegL dst, memory mem, immI13 mask) %{
5660 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5661 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5662
5663 size(2*4);
5664 format %{ "LDUH $mem,$dst\t! ushort/char & 13-bit mask -> long\n\t"
5665 "AND $dst,$mask,$dst" %}
5666 ins_encode %{
5667 Register Rdst = $dst$$Register;
5668 __ lduh($mem$$Address, Rdst);
5669 __ and3(Rdst, $mask$$constant, Rdst);
5670 %}
5671 ins_pipe(iload_mem);
5672 %}
5673
5674 // Load Unsigned Short/Char (16bit UNsigned) with a 16-bit mask into a Long Register
5675 instruct loadUS2L_immI16(iRegL dst, memory mem, immI16 mask, iRegL tmp) %{
5676 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5677 effect(TEMP dst, TEMP tmp);
5678 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST);
5679
5680 size((3+1)*4); // set may use two instructions.
5681 format %{ "LDUH $mem,$dst\t! ushort/char & 16-bit mask -> long\n\t"
5682 "SET $mask,$tmp\n\t"
5683 "AND $dst,$tmp,$dst" %}
5684 ins_encode %{
5685 Register Rdst = $dst$$Register;
5686 Register Rtmp = $tmp$$Register;
5687 __ lduh($mem$$Address, Rdst);
5688 __ set($mask$$constant, Rtmp);
5689 __ and3(Rdst, Rtmp, Rdst);
5690 %}
5691 ins_pipe(iload_mem);
5692 %}
5693
5694 // Load Integer
5695 instruct loadI(iRegI dst, memory mem) %{
5696 match(Set dst (LoadI mem));
5697 ins_cost(MEMORY_REF_COST);
5698
5699 size(4);
5700 format %{ "LDUW $mem,$dst\t! int" %}
5701 ins_encode %{
5702 __ lduw($mem$$Address, $dst$$Register);
5703 %}
5704 ins_pipe(iload_mem);
5705 %}
5706
5707 // Load Integer to Byte (8 bit signed)
5708 instruct loadI2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{
5709 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour));
5710 ins_cost(MEMORY_REF_COST);
5711
5712 size(4);
5713
5714 format %{ "LDSB $mem+3,$dst\t! int -> byte" %}
5715 ins_encode %{
5716 __ ldsb($mem$$Address, $dst$$Register, 3);
5717 %}
5718 ins_pipe(iload_mask_mem);
5719 %}
5720
5721 // Load Integer to Unsigned Byte (8 bit UNsigned)
5722 instruct loadI2UB(iRegI dst, indOffset13m7 mem, immI_255 mask) %{
5723 match(Set dst (AndI (LoadI mem) mask));
5724 ins_cost(MEMORY_REF_COST);
5725
5726 size(4);
5727
5728 format %{ "LDUB $mem+3,$dst\t! int -> ubyte" %}
5729 ins_encode %{
5730 __ ldub($mem$$Address, $dst$$Register, 3);
5731 %}
5732 ins_pipe(iload_mask_mem);
5733 %}
5734
5735 // Load Integer to Short (16 bit signed)
5736 instruct loadI2S(iRegI dst, indOffset13m7 mem, immI_16 sixteen) %{
5737 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen));
5738 ins_cost(MEMORY_REF_COST);
5739
5740 size(4);
5741
5742 format %{ "LDSH $mem+2,$dst\t! int -> short" %}
5743 ins_encode %{
5744 __ ldsh($mem$$Address, $dst$$Register, 2);
5745 %}
5746 ins_pipe(iload_mask_mem);
5747 %}
5748
5749 // Load Integer to Unsigned Short (16 bit UNsigned)
5750 instruct loadI2US(iRegI dst, indOffset13m7 mem, immI_65535 mask) %{
5751 match(Set dst (AndI (LoadI mem) mask));
5752 ins_cost(MEMORY_REF_COST);
5753
5754 size(4);
5755
5756 format %{ "LDUH $mem+2,$dst\t! int -> ushort/char" %}
5757 ins_encode %{
5758 __ lduh($mem$$Address, $dst$$Register, 2);
5759 %}
5760 ins_pipe(iload_mask_mem);
5761 %}
5762
5763 // Load Integer into a Long Register
5764 instruct loadI2L(iRegL dst, memory mem) %{
5765 match(Set dst (ConvI2L (LoadI mem)));
5766 ins_cost(MEMORY_REF_COST);
5767
5768 size(4);
5769 format %{ "LDSW $mem,$dst\t! int -> long" %}
5770 ins_encode %{
5771 __ ldsw($mem$$Address, $dst$$Register);
5772 %}
5773 ins_pipe(iload_mask_mem);
5774 %}
5775
5776 // Load Integer with mask 0xFF into a Long Register
5777 instruct loadI2L_immI_255(iRegL dst, indOffset13m7 mem, immI_255 mask) %{
5778 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5779 ins_cost(MEMORY_REF_COST);
5780
5781 size(4);
5782 format %{ "LDUB $mem+3,$dst\t! int & 0xFF -> long" %}
5783 ins_encode %{
5784 __ ldub($mem$$Address, $dst$$Register, 3); // LSB is index+3 on BE
5785 %}
5786 ins_pipe(iload_mem);
5787 %}
5788
5789 // Load Integer with mask 0xFFFF into a Long Register
5790 instruct loadI2L_immI_65535(iRegL dst, indOffset13m7 mem, immI_65535 mask) %{
5791 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5792 ins_cost(MEMORY_REF_COST);
5793
5794 size(4);
5795 format %{ "LDUH $mem+2,$dst\t! int & 0xFFFF -> long" %}
5796 ins_encode %{
5797 __ lduh($mem$$Address, $dst$$Register, 2); // LSW is index+2 on BE
5798 %}
5799 ins_pipe(iload_mem);
5800 %}
5801
5802 // Load Integer with a 13-bit mask into a Long Register
5803 instruct loadI2L_immI13(iRegL dst, memory mem, immI13 mask) %{
5804 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5805 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5806
5807 size(2*4);
5808 format %{ "LDUW $mem,$dst\t! int & 13-bit mask -> long\n\t"
5809 "AND $dst,$mask,$dst" %}
5810 ins_encode %{
5811 Register Rdst = $dst$$Register;
5812 __ lduw($mem$$Address, Rdst);
5813 __ and3(Rdst, $mask$$constant, Rdst);
5814 %}
5815 ins_pipe(iload_mem);
5816 %}
5817
5818 // Load Integer with a 32-bit mask into a Long Register
5819 instruct loadI2L_immI(iRegL dst, memory mem, immI mask, iRegL tmp) %{
5820 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5821 effect(TEMP dst, TEMP tmp);
5822 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST);
5823
5824 size((3+1)*4); // set may use two instructions.
5825 format %{ "LDUW $mem,$dst\t! int & 32-bit mask -> long\n\t"
5826 "SET $mask,$tmp\n\t"
5827 "AND $dst,$tmp,$dst" %}
5828 ins_encode %{
5829 Register Rdst = $dst$$Register;
5830 Register Rtmp = $tmp$$Register;
5831 __ lduw($mem$$Address, Rdst);
5832 __ set($mask$$constant, Rtmp);
5833 __ and3(Rdst, Rtmp, Rdst);
5834 %}
5835 ins_pipe(iload_mem);
5836 %}
5837
5838 // Load Unsigned Integer into a Long Register
5839 instruct loadUI2L(iRegL dst, memory mem) %{
5840 match(Set dst (LoadUI2L mem));
5841 ins_cost(MEMORY_REF_COST);
5842
5843 size(4);
5844 format %{ "LDUW $mem,$dst\t! uint -> long" %}
5845 ins_encode %{
5846 __ lduw($mem$$Address, $dst$$Register);
5847 %}
5848 ins_pipe(iload_mem);
5849 %}
5850
5851 // Load Long - aligned
5852 instruct loadL(iRegL dst, memory mem ) %{
5853 match(Set dst (LoadL mem));
5854 ins_cost(MEMORY_REF_COST);
5855
5856 size(4);
5857 format %{ "LDX $mem,$dst\t! long" %}
5858 ins_encode %{
5859 __ ldx($mem$$Address, $dst$$Register);
5860 %}
5861 ins_pipe(iload_mem);
5862 %}
5863
5864 // Load Long - UNaligned
5865 instruct loadL_unaligned(iRegL dst, memory mem, o7RegI tmp) %{
5866 match(Set dst (LoadL_unaligned mem));
5867 effect(KILL tmp);
5868 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST);
5869 size(16);
5870 format %{ "LDUW $mem+4,R_O7\t! misaligned long\n"
5871 "\tLDUW $mem ,$dst\n"
5872 "\tSLLX #32, $dst, $dst\n"
5873 "\tOR $dst, R_O7, $dst" %}
5874 opcode(Assembler::lduw_op3);
5875 ins_encode(form3_mem_reg_long_unaligned_marshal( mem, dst ));
5876 ins_pipe(iload_mem);
5877 %}
5878
5879 // Load Aligned Packed Byte into a Double Register
5880 instruct loadA8B(regD dst, memory mem) %{
5881 match(Set dst (Load8B mem));
5882 ins_cost(MEMORY_REF_COST);
5883 size(4);
5884 format %{ "LDDF $mem,$dst\t! packed8B" %}
5885 opcode(Assembler::lddf_op3);
5886 ins_encode(simple_form3_mem_reg( mem, dst ) );
5887 ins_pipe(floadD_mem);
5888 %}
5889
5890 // Load Aligned Packed Char into a Double Register
5891 instruct loadA4C(regD dst, memory mem) %{
5892 match(Set dst (Load4C mem));
5893 ins_cost(MEMORY_REF_COST);
5894 size(4);
5895 format %{ "LDDF $mem,$dst\t! packed4C" %}
5896 opcode(Assembler::lddf_op3);
5897 ins_encode(simple_form3_mem_reg( mem, dst ) );
5898 ins_pipe(floadD_mem);
5899 %}
5900
5901 // Load Aligned Packed Short into a Double Register
5902 instruct loadA4S(regD dst, memory mem) %{
5903 match(Set dst (Load4S mem));
5904 ins_cost(MEMORY_REF_COST);
5905 size(4);
5906 format %{ "LDDF $mem,$dst\t! packed4S" %}
5907 opcode(Assembler::lddf_op3);
5908 ins_encode(simple_form3_mem_reg( mem, dst ) );
5909 ins_pipe(floadD_mem);
5910 %}
5911
5912 // Load Aligned Packed Int into a Double Register
5913 instruct loadA2I(regD dst, memory mem) %{
5914 match(Set dst (Load2I mem));
5915 ins_cost(MEMORY_REF_COST);
5916 size(4);
5917 format %{ "LDDF $mem,$dst\t! packed2I" %}
5918 opcode(Assembler::lddf_op3);
5919 ins_encode(simple_form3_mem_reg( mem, dst ) );
5920 ins_pipe(floadD_mem);
5921 %}
5922
5923 // Load Range
5924 instruct loadRange(iRegI dst, memory mem) %{
5925 match(Set dst (LoadRange mem));
5926 ins_cost(MEMORY_REF_COST);
5927
5928 size(4);
5929 format %{ "LDUW $mem,$dst\t! range" %}
5930 opcode(Assembler::lduw_op3);
5931 ins_encode(simple_form3_mem_reg( mem, dst ) );
5932 ins_pipe(iload_mem);
5933 %}
5934
5935 // Load Integer into %f register (for fitos/fitod)
5936 instruct loadI_freg(regF dst, memory mem) %{
5937 match(Set dst (LoadI mem));
5938 ins_cost(MEMORY_REF_COST);
5939 size(4);
5940
5941 format %{ "LDF $mem,$dst\t! for fitos/fitod" %}
5942 opcode(Assembler::ldf_op3);
5943 ins_encode(simple_form3_mem_reg( mem, dst ) );
5944 ins_pipe(floadF_mem);
5945 %}
5946
5947 // Load Pointer
5948 instruct loadP(iRegP dst, memory mem) %{
5949 match(Set dst (LoadP mem));
5950 ins_cost(MEMORY_REF_COST);
5951 size(4);
5952
5953 #ifndef _LP64
5954 format %{ "LDUW $mem,$dst\t! ptr" %}
5955 ins_encode %{
5956 __ lduw($mem$$Address, $dst$$Register);
5957 %}
5958 #else
5959 format %{ "LDX $mem,$dst\t! ptr" %}
5960 ins_encode %{
5961 __ ldx($mem$$Address, $dst$$Register);
5962 %}
5963 #endif
5964 ins_pipe(iload_mem);
5965 %}
5966
5967 // Load Compressed Pointer
5968 instruct loadN(iRegN dst, memory mem) %{
5969 match(Set dst (LoadN mem));
5970 ins_cost(MEMORY_REF_COST);
5971 size(4);
5972
5973 format %{ "LDUW $mem,$dst\t! compressed ptr" %}
5974 ins_encode %{
5975 __ lduw($mem$$Address, $dst$$Register);
5976 %}
5977 ins_pipe(iload_mem);
5978 %}
5979
5980 // Load Klass Pointer
5981 instruct loadKlass(iRegP dst, memory mem) %{
5982 match(Set dst (LoadKlass mem));
5983 ins_cost(MEMORY_REF_COST);
5984 size(4);
5985
5986 #ifndef _LP64
5987 format %{ "LDUW $mem,$dst\t! klass ptr" %}
5988 ins_encode %{
5989 __ lduw($mem$$Address, $dst$$Register);
5990 %}
5991 #else
5992 format %{ "LDX $mem,$dst\t! klass ptr" %}
5993 ins_encode %{
5994 __ ldx($mem$$Address, $dst$$Register);
5995 %}
5996 #endif
5997 ins_pipe(iload_mem);
5998 %}
5999
6000 // Load narrow Klass Pointer
6001 instruct loadNKlass(iRegN dst, memory mem) %{
6002 match(Set dst (LoadNKlass mem));
6003 ins_cost(MEMORY_REF_COST);
6004 size(4);
6005
6006 format %{ "LDUW $mem,$dst\t! compressed klass ptr" %}
6007 ins_encode %{
6008 __ lduw($mem$$Address, $dst$$Register);
6009 %}
6010 ins_pipe(iload_mem);
6011 %}
6012
6013 // Load Double
6014 instruct loadD(regD dst, memory mem) %{
6015 match(Set dst (LoadD mem));
6016 ins_cost(MEMORY_REF_COST);
6017
6018 size(4);
6019 format %{ "LDDF $mem,$dst" %}
6020 opcode(Assembler::lddf_op3);
6021 ins_encode(simple_form3_mem_reg( mem, dst ) );
6022 ins_pipe(floadD_mem);
6023 %}
6024
6025 // Load Double - UNaligned
6026 instruct loadD_unaligned(regD_low dst, memory mem ) %{
6027 match(Set dst (LoadD_unaligned mem));
6028 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST);
6029 size(8);
6030 format %{ "LDF $mem ,$dst.hi\t! misaligned double\n"
6031 "\tLDF $mem+4,$dst.lo\t!" %}
6032 opcode(Assembler::ldf_op3);
6033 ins_encode( form3_mem_reg_double_unaligned( mem, dst ));
6034 ins_pipe(iload_mem);
6035 %}
6036
6037 // Load Float
6038 instruct loadF(regF dst, memory mem) %{
6039 match(Set dst (LoadF mem));
6040 ins_cost(MEMORY_REF_COST);
6041
6042 size(4);
6043 format %{ "LDF $mem,$dst" %}
6044 opcode(Assembler::ldf_op3);
6045 ins_encode(simple_form3_mem_reg( mem, dst ) );
6046 ins_pipe(floadF_mem);
6047 %}
6048
6049 // Load Constant
6050 instruct loadConI( iRegI dst, immI src ) %{
6051 match(Set dst src);
6052 ins_cost(DEFAULT_COST * 3/2);
6053 format %{ "SET $src,$dst" %}
6054 ins_encode( Set32(src, dst) );
6055 ins_pipe(ialu_hi_lo_reg);
6056 %}
6057
6058 instruct loadConI13( iRegI dst, immI13 src ) %{
6059 match(Set dst src);
6060
6061 size(4);
6062 format %{ "MOV $src,$dst" %}
6063 ins_encode( Set13( src, dst ) );
6064 ins_pipe(ialu_imm);
6065 %}
6066
6067 #ifndef _LP64
6068 instruct loadConP(iRegP dst, immP con) %{
6069 match(Set dst con);
6070 ins_cost(DEFAULT_COST * 3/2);
6071 format %{ "SET $con,$dst\t!ptr" %}
6072 ins_encode %{
6073 // [RGV] This next line should be generated from ADLC
6074 if (_opnds[1]->constant_is_oop()) {
6075 intptr_t val = $con$$constant;
6076 __ set_oop_constant((jobject) val, $dst$$Register);
6077 } else { // non-oop pointers, e.g. card mark base, heap top
6078 __ set($con$$constant, $dst$$Register);
6079 }
6080 %}
6081 ins_pipe(loadConP);
6082 %}
6083 #else
6084 instruct loadConP_set(iRegP dst, immP_set con) %{
6085 match(Set dst con);
6086 ins_cost(DEFAULT_COST * 3/2);
6087 format %{ "SET $con,$dst\t! ptr" %}
6088 ins_encode %{
6089 // [RGV] This next line should be generated from ADLC
6090 if (_opnds[1]->constant_is_oop()) {
6091 intptr_t val = $con$$constant;
6092 __ set_oop_constant((jobject) val, $dst$$Register);
6093 } else { // non-oop pointers, e.g. card mark base, heap top
6094 __ set($con$$constant, $dst$$Register);
6095 }
6096 %}
6097 ins_pipe(loadConP);
6098 %}
6099
6100 instruct loadConP_load(iRegP dst, immP_load con) %{
6101 match(Set dst con);
6102 ins_cost(MEMORY_REF_COST);
6103 format %{ "LD [$constanttablebase + $constantoffset],$dst\t! load from constant table: ptr=$con" %}
6104 ins_encode %{
6105 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $dst$$Register);
6106 __ ld_ptr($constanttablebase, con_offset, $dst$$Register);
6107 %}
6108 ins_pipe(loadConP);
6109 %}
6110
6111 instruct loadConP_no_oop_cheap(iRegP dst, immP_no_oop_cheap con) %{
6112 match(Set dst con);
6113 ins_cost(DEFAULT_COST * 3/2);
6114 format %{ "SET $con,$dst\t! non-oop ptr" %}
6115 ins_encode %{
6116 __ set($con$$constant, $dst$$Register);
6117 %}
6118 ins_pipe(loadConP);
6119 %}
6120 #endif // _LP64
6121
6122 instruct loadConP0(iRegP dst, immP0 src) %{
6123 match(Set dst src);
6124
6125 size(4);
6126 format %{ "CLR $dst\t!ptr" %}
6127 ins_encode %{
6128 __ clr($dst$$Register);
6129 %}
6130 ins_pipe(ialu_imm);
6131 %}
6132
6133 instruct loadConP_poll(iRegP dst, immP_poll src) %{
6134 match(Set dst src);
6135 ins_cost(DEFAULT_COST);
6136 format %{ "SET $src,$dst\t!ptr" %}
6137 ins_encode %{
6138 AddressLiteral polling_page(os::get_polling_page());
6139 __ sethi(polling_page, reg_to_register_object($dst$$reg));
6140 %}
6141 ins_pipe(loadConP_poll);
6142 %}
6143
6144 instruct loadConN0(iRegN dst, immN0 src) %{
6145 match(Set dst src);
6146
6147 size(4);
6148 format %{ "CLR $dst\t! compressed NULL ptr" %}
6149 ins_encode %{
6150 __ clr($dst$$Register);
6151 %}
6152 ins_pipe(ialu_imm);
6153 %}
6154
6155 instruct loadConN(iRegN dst, immN src) %{
6156 match(Set dst src);
6157 ins_cost(DEFAULT_COST * 3/2);
6158 format %{ "SET $src,$dst\t! compressed ptr" %}
6159 ins_encode %{
6160 Register dst = $dst$$Register;
6161 __ set_narrow_oop((jobject)$src$$constant, dst);
6162 %}
6163 ins_pipe(ialu_hi_lo_reg);
6164 %}
6165
6166 // Materialize long value (predicated by immL_cheap).
6167 instruct loadConL_set64(iRegL dst, immL_cheap con, o7RegL tmp) %{
6168 match(Set dst con);
6169 effect(KILL tmp);
6170 ins_cost(DEFAULT_COST * 3);
6171 format %{ "SET64 $con,$dst KILL $tmp\t! cheap long" %}
6172 ins_encode %{
6173 __ set64($con$$constant, $dst$$Register, $tmp$$Register);
6174 %}
6175 ins_pipe(loadConL);
6176 %}
6177
6178 // Load long value from constant table (predicated by immL_expensive).
6179 instruct loadConL_ldx(iRegL dst, immL_expensive con) %{
6180 match(Set dst con);
6181 ins_cost(MEMORY_REF_COST);
6182 format %{ "LDX [$constanttablebase + $constantoffset],$dst\t! load from constant table: long=$con" %}
6183 ins_encode %{
6184 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $dst$$Register);
6185 __ ldx($constanttablebase, con_offset, $dst$$Register);
6186 %}
6187 ins_pipe(loadConL);
6188 %}
6189
6190 instruct loadConL0( iRegL dst, immL0 src ) %{
6191 match(Set dst src);
6192 ins_cost(DEFAULT_COST);
6193 size(4);
6194 format %{ "CLR $dst\t! long" %}
6195 ins_encode( Set13( src, dst ) );
6196 ins_pipe(ialu_imm);
6197 %}
6198
6199 instruct loadConL13( iRegL dst, immL13 src ) %{
6200 match(Set dst src);
6201 ins_cost(DEFAULT_COST * 2);
6202
6203 size(4);
6204 format %{ "MOV $src,$dst\t! long" %}
6205 ins_encode( Set13( src, dst ) );
6206 ins_pipe(ialu_imm);
6207 %}
6208
6209 instruct loadConF(regF dst, immF con, o7RegI tmp) %{
6210 match(Set dst con);
6211 effect(KILL tmp);
6212 format %{ "LDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: float=$con" %}
6213 ins_encode %{
6214 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $tmp$$Register);
6215 __ ldf(FloatRegisterImpl::S, $constanttablebase, con_offset, $dst$$FloatRegister);
6216 %}
6217 ins_pipe(loadConFD);
6218 %}
6219
6220 instruct loadConD(regD dst, immD con, o7RegI tmp) %{
6221 match(Set dst con);
6222 effect(KILL tmp);
6223 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: double=$con" %}
6224 ins_encode %{
6225 // XXX This is a quick fix for 6833573.
6226 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset($con), $dst$$FloatRegister);
6227 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $tmp$$Register);
6228 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
6229 %}
6230 ins_pipe(loadConFD);
6231 %}
6232
6233 // Prefetch instructions.
6234 // Must be safe to execute with invalid address (cannot fault).
6235
6236 instruct prefetchr( memory mem ) %{
6237 match( PrefetchRead mem );
6238 ins_cost(MEMORY_REF_COST);
6239
6240 format %{ "PREFETCH $mem,0\t! Prefetch read-many" %}
6241 opcode(Assembler::prefetch_op3);
6242 ins_encode( form3_mem_prefetch_read( mem ) );
6243 ins_pipe(iload_mem);
6244 %}
6245
6246 instruct prefetchw( memory mem ) %{
6247 predicate(AllocatePrefetchStyle != 3 );
6248 match( PrefetchWrite mem );
6249 ins_cost(MEMORY_REF_COST);
6250
6251 format %{ "PREFETCH $mem,2\t! Prefetch write-many (and read)" %}
6252 opcode(Assembler::prefetch_op3);
6253 ins_encode( form3_mem_prefetch_write( mem ) );
6254 ins_pipe(iload_mem);
6255 %}
6256
6257 // Use BIS instruction to prefetch.
6258 instruct prefetchw_bis( memory mem ) %{
6259 predicate(AllocatePrefetchStyle == 3);
6260 match( PrefetchWrite mem );
6261 ins_cost(MEMORY_REF_COST);
6262
6263 format %{ "STXA G0,$mem\t! // Block initializing store" %}
6264 ins_encode %{
6265 Register base = as_Register($mem$$base);
6266 int disp = $mem$$disp;
6267 if (disp != 0) {
6268 __ add(base, AllocatePrefetchStepSize, base);
6269 }
6270 __ stxa(G0, base, G0, ASI_BLK_INIT_QUAD_LDD_P);
6271 %}
6272 ins_pipe(istore_mem_reg);
6273 %}
6274
6275 //----------Store Instructions-------------------------------------------------
6276 // Store Byte
6277 instruct storeB(memory mem, iRegI src) %{
6278 match(Set mem (StoreB mem src));
6279 ins_cost(MEMORY_REF_COST);
6280
6281 size(4);
6282 format %{ "STB $src,$mem\t! byte" %}
6283 opcode(Assembler::stb_op3);
6284 ins_encode(simple_form3_mem_reg( mem, src ) );
6285 ins_pipe(istore_mem_reg);
6286 %}
6287
6288 instruct storeB0(memory mem, immI0 src) %{
6289 match(Set mem (StoreB mem src));
6290 ins_cost(MEMORY_REF_COST);
6291
6292 size(4);
6293 format %{ "STB $src,$mem\t! byte" %}
6294 opcode(Assembler::stb_op3);
6295 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6296 ins_pipe(istore_mem_zero);
6297 %}
6298
6299 instruct storeCM0(memory mem, immI0 src) %{
6300 match(Set mem (StoreCM mem src));
6301 ins_cost(MEMORY_REF_COST);
6302
6303 size(4);
6304 format %{ "STB $src,$mem\t! CMS card-mark byte 0" %}
6305 opcode(Assembler::stb_op3);
6306 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6307 ins_pipe(istore_mem_zero);
6308 %}
6309
6310 // Store Char/Short
6311 instruct storeC(memory mem, iRegI src) %{
6312 match(Set mem (StoreC mem src));
6313 ins_cost(MEMORY_REF_COST);
6314
6315 size(4);
6316 format %{ "STH $src,$mem\t! short" %}
6317 opcode(Assembler::sth_op3);
6318 ins_encode(simple_form3_mem_reg( mem, src ) );
6319 ins_pipe(istore_mem_reg);
6320 %}
6321
6322 instruct storeC0(memory mem, immI0 src) %{
6323 match(Set mem (StoreC mem src));
6324 ins_cost(MEMORY_REF_COST);
6325
6326 size(4);
6327 format %{ "STH $src,$mem\t! short" %}
6328 opcode(Assembler::sth_op3);
6329 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6330 ins_pipe(istore_mem_zero);
6331 %}
6332
6333 // Store Integer
6334 instruct storeI(memory mem, iRegI src) %{
6335 match(Set mem (StoreI mem src));
6336 ins_cost(MEMORY_REF_COST);
6337
6338 size(4);
6339 format %{ "STW $src,$mem" %}
6340 opcode(Assembler::stw_op3);
6341 ins_encode(simple_form3_mem_reg( mem, src ) );
6342 ins_pipe(istore_mem_reg);
6343 %}
6344
6345 // Store Long
6346 instruct storeL(memory mem, iRegL src) %{
6347 match(Set mem (StoreL mem src));
6348 ins_cost(MEMORY_REF_COST);
6349 size(4);
6350 format %{ "STX $src,$mem\t! long" %}
6351 opcode(Assembler::stx_op3);
6352 ins_encode(simple_form3_mem_reg( mem, src ) );
6353 ins_pipe(istore_mem_reg);
6354 %}
6355
6356 instruct storeI0(memory mem, immI0 src) %{
6357 match(Set mem (StoreI mem src));
6358 ins_cost(MEMORY_REF_COST);
6359
6360 size(4);
6361 format %{ "STW $src,$mem" %}
6362 opcode(Assembler::stw_op3);
6363 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6364 ins_pipe(istore_mem_zero);
6365 %}
6366
6367 instruct storeL0(memory mem, immL0 src) %{
6368 match(Set mem (StoreL mem src));
6369 ins_cost(MEMORY_REF_COST);
6370
6371 size(4);
6372 format %{ "STX $src,$mem" %}
6373 opcode(Assembler::stx_op3);
6374 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6375 ins_pipe(istore_mem_zero);
6376 %}
6377
6378 // Store Integer from float register (used after fstoi)
6379 instruct storeI_Freg(memory mem, regF src) %{
6380 match(Set mem (StoreI mem src));
6381 ins_cost(MEMORY_REF_COST);
6382
6383 size(4);
6384 format %{ "STF $src,$mem\t! after fstoi/fdtoi" %}
6385 opcode(Assembler::stf_op3);
6386 ins_encode(simple_form3_mem_reg( mem, src ) );
6387 ins_pipe(fstoreF_mem_reg);
6388 %}
6389
6390 // Store Pointer
6391 instruct storeP(memory dst, sp_ptr_RegP src) %{
6392 match(Set dst (StoreP dst src));
6393 ins_cost(MEMORY_REF_COST);
6394 size(4);
6395
6396 #ifndef _LP64
6397 format %{ "STW $src,$dst\t! ptr" %}
6398 opcode(Assembler::stw_op3, 0, REGP_OP);
6399 #else
6400 format %{ "STX $src,$dst\t! ptr" %}
6401 opcode(Assembler::stx_op3, 0, REGP_OP);
6402 #endif
6403 ins_encode( form3_mem_reg( dst, src ) );
6404 ins_pipe(istore_mem_spORreg);
6405 %}
6406
6407 instruct storeP0(memory dst, immP0 src) %{
6408 match(Set dst (StoreP dst src));
6409 ins_cost(MEMORY_REF_COST);
6410 size(4);
6411
6412 #ifndef _LP64
6413 format %{ "STW $src,$dst\t! ptr" %}
6414 opcode(Assembler::stw_op3, 0, REGP_OP);
6415 #else
6416 format %{ "STX $src,$dst\t! ptr" %}
6417 opcode(Assembler::stx_op3, 0, REGP_OP);
6418 #endif
6419 ins_encode( form3_mem_reg( dst, R_G0 ) );
6420 ins_pipe(istore_mem_zero);
6421 %}
6422
6423 // Store Compressed Pointer
6424 instruct storeN(memory dst, iRegN src) %{
6425 match(Set dst (StoreN dst src));
6426 ins_cost(MEMORY_REF_COST);
6427 size(4);
6428
6429 format %{ "STW $src,$dst\t! compressed ptr" %}
6430 ins_encode %{
6431 Register base = as_Register($dst$$base);
6432 Register index = as_Register($dst$$index);
6433 Register src = $src$$Register;
6434 if (index != G0) {
6435 __ stw(src, base, index);
6436 } else {
6437 __ stw(src, base, $dst$$disp);
6438 }
6439 %}
6440 ins_pipe(istore_mem_spORreg);
6441 %}
6442
6443 instruct storeN0(memory dst, immN0 src) %{
6444 match(Set dst (StoreN dst src));
6445 ins_cost(MEMORY_REF_COST);
6446 size(4);
6447
6448 format %{ "STW $src,$dst\t! compressed ptr" %}
6449 ins_encode %{
6450 Register base = as_Register($dst$$base);
6451 Register index = as_Register($dst$$index);
6452 if (index != G0) {
6453 __ stw(0, base, index);
6454 } else {
6455 __ stw(0, base, $dst$$disp);
6456 }
6457 %}
6458 ins_pipe(istore_mem_zero);
6459 %}
6460
6461 // Store Double
6462 instruct storeD( memory mem, regD src) %{
6463 match(Set mem (StoreD mem src));
6464 ins_cost(MEMORY_REF_COST);
6465
6466 size(4);
6467 format %{ "STDF $src,$mem" %}
6468 opcode(Assembler::stdf_op3);
6469 ins_encode(simple_form3_mem_reg( mem, src ) );
6470 ins_pipe(fstoreD_mem_reg);
6471 %}
6472
6473 instruct storeD0( memory mem, immD0 src) %{
6474 match(Set mem (StoreD mem src));
6475 ins_cost(MEMORY_REF_COST);
6476
6477 size(4);
6478 format %{ "STX $src,$mem" %}
6479 opcode(Assembler::stx_op3);
6480 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6481 ins_pipe(fstoreD_mem_zero);
6482 %}
6483
6484 // Store Float
6485 instruct storeF( memory mem, regF src) %{
6486 match(Set mem (StoreF mem src));
6487 ins_cost(MEMORY_REF_COST);
6488
6489 size(4);
6490 format %{ "STF $src,$mem" %}
6491 opcode(Assembler::stf_op3);
6492 ins_encode(simple_form3_mem_reg( mem, src ) );
6493 ins_pipe(fstoreF_mem_reg);
6494 %}
6495
6496 instruct storeF0( memory mem, immF0 src) %{
6497 match(Set mem (StoreF mem src));
6498 ins_cost(MEMORY_REF_COST);
6499
6500 size(4);
6501 format %{ "STW $src,$mem\t! storeF0" %}
6502 opcode(Assembler::stw_op3);
6503 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6504 ins_pipe(fstoreF_mem_zero);
6505 %}
6506
6507 // Store Aligned Packed Bytes in Double register to memory
6508 instruct storeA8B(memory mem, regD src) %{
6509 match(Set mem (Store8B mem src));
6510 ins_cost(MEMORY_REF_COST);
6511 size(4);
6512 format %{ "STDF $src,$mem\t! packed8B" %}
6513 opcode(Assembler::stdf_op3);
6514 ins_encode(simple_form3_mem_reg( mem, src ) );
6515 ins_pipe(fstoreD_mem_reg);
6516 %}
6517
6518 // Convert oop pointer into compressed form
6519 instruct encodeHeapOop(iRegN dst, iRegP src) %{
6520 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull);
6521 match(Set dst (EncodeP src));
6522 format %{ "encode_heap_oop $src, $dst" %}
6523 ins_encode %{
6524 __ encode_heap_oop($src$$Register, $dst$$Register);
6525 %}
6526 ins_pipe(ialu_reg);
6527 %}
6528
6529 instruct encodeHeapOop_not_null(iRegN dst, iRegP src) %{
6530 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull);
6531 match(Set dst (EncodeP src));
6532 format %{ "encode_heap_oop_not_null $src, $dst" %}
6533 ins_encode %{
6534 __ encode_heap_oop_not_null($src$$Register, $dst$$Register);
6535 %}
6536 ins_pipe(ialu_reg);
6537 %}
6538
6539 instruct decodeHeapOop(iRegP dst, iRegN src) %{
6540 predicate(n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull &&
6541 n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant);
6542 match(Set dst (DecodeN src));
6543 format %{ "decode_heap_oop $src, $dst" %}
6544 ins_encode %{
6545 __ decode_heap_oop($src$$Register, $dst$$Register);
6546 %}
6547 ins_pipe(ialu_reg);
6548 %}
6549
6550 instruct decodeHeapOop_not_null(iRegP dst, iRegN src) %{
6551 predicate(n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull ||
6552 n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant);
6553 match(Set dst (DecodeN src));
6554 format %{ "decode_heap_oop_not_null $src, $dst" %}
6555 ins_encode %{
6556 __ decode_heap_oop_not_null($src$$Register, $dst$$Register);
6557 %}
6558 ins_pipe(ialu_reg);
6559 %}
6560
6561
6562 // Store Zero into Aligned Packed Bytes
6563 instruct storeA8B0(memory mem, immI0 zero) %{
6564 match(Set mem (Store8B mem zero));
6565 ins_cost(MEMORY_REF_COST);
6566 size(4);
6567 format %{ "STX $zero,$mem\t! packed8B" %}
6568 opcode(Assembler::stx_op3);
6569 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6570 ins_pipe(fstoreD_mem_zero);
6571 %}
6572
6573 // Store Aligned Packed Chars/Shorts in Double register to memory
6574 instruct storeA4C(memory mem, regD src) %{
6575 match(Set mem (Store4C mem src));
6576 ins_cost(MEMORY_REF_COST);
6577 size(4);
6578 format %{ "STDF $src,$mem\t! packed4C" %}
6579 opcode(Assembler::stdf_op3);
6580 ins_encode(simple_form3_mem_reg( mem, src ) );
6581 ins_pipe(fstoreD_mem_reg);
6582 %}
6583
6584 // Store Zero into Aligned Packed Chars/Shorts
6585 instruct storeA4C0(memory mem, immI0 zero) %{
6586 match(Set mem (Store4C mem (Replicate4C zero)));
6587 ins_cost(MEMORY_REF_COST);
6588 size(4);
6589 format %{ "STX $zero,$mem\t! packed4C" %}
6590 opcode(Assembler::stx_op3);
6591 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6592 ins_pipe(fstoreD_mem_zero);
6593 %}
6594
6595 // Store Aligned Packed Ints in Double register to memory
6596 instruct storeA2I(memory mem, regD src) %{
6597 match(Set mem (Store2I mem src));
6598 ins_cost(MEMORY_REF_COST);
6599 size(4);
6600 format %{ "STDF $src,$mem\t! packed2I" %}
6601 opcode(Assembler::stdf_op3);
6602 ins_encode(simple_form3_mem_reg( mem, src ) );
6603 ins_pipe(fstoreD_mem_reg);
6604 %}
6605
6606 // Store Zero into Aligned Packed Ints
6607 instruct storeA2I0(memory mem, immI0 zero) %{
6608 match(Set mem (Store2I mem zero));
6609 ins_cost(MEMORY_REF_COST);
6610 size(4);
6611 format %{ "STX $zero,$mem\t! packed2I" %}
6612 opcode(Assembler::stx_op3);
6613 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6614 ins_pipe(fstoreD_mem_zero);
6615 %}
6616
6617
6618 //----------MemBar Instructions-----------------------------------------------
6619 // Memory barrier flavors
6620
6621 instruct membar_acquire() %{
6622 match(MemBarAcquire);
6623 ins_cost(4*MEMORY_REF_COST);
6624
6625 size(0);
6626 format %{ "MEMBAR-acquire" %}
6627 ins_encode( enc_membar_acquire );
6628 ins_pipe(long_memory_op);
6629 %}
6630
6631 instruct membar_release() %{
6632 match(MemBarRelease);
6633 ins_cost(4*MEMORY_REF_COST);
6634
6635 size(0);
6636 format %{ "MEMBAR-release" %}
6637 ins_encode( enc_membar_release );
6638 ins_pipe(long_memory_op);
6639 %}
6640
6641 instruct membar_volatile() %{
6642 match(MemBarVolatile);
6643 ins_cost(4*MEMORY_REF_COST);
6644
6645 size(4);
6646 format %{ "MEMBAR-volatile" %}
6647 ins_encode( enc_membar_volatile );
6648 ins_pipe(long_memory_op);
6649 %}
6650
6651 instruct unnecessary_membar_volatile() %{
6652 match(MemBarVolatile);
6653 predicate(Matcher::post_store_load_barrier(n));
6654 ins_cost(0);
6655
6656 size(0);
6657 format %{ "!MEMBAR-volatile (unnecessary so empty encoding)" %}
6658 ins_encode( );
6659 ins_pipe(empty);
6660 %}
6661
6662 //----------Register Move Instructions-----------------------------------------
6663 instruct roundDouble_nop(regD dst) %{
6664 match(Set dst (RoundDouble dst));
6665 ins_cost(0);
6666 // SPARC results are already "rounded" (i.e., normal-format IEEE)
6667 ins_encode( );
6668 ins_pipe(empty);
6669 %}
6670
6671
6672 instruct roundFloat_nop(regF dst) %{
6673 match(Set dst (RoundFloat dst));
6674 ins_cost(0);
6675 // SPARC results are already "rounded" (i.e., normal-format IEEE)
6676 ins_encode( );
6677 ins_pipe(empty);
6678 %}
6679
6680
6681 // Cast Index to Pointer for unsafe natives
6682 instruct castX2P(iRegX src, iRegP dst) %{
6683 match(Set dst (CastX2P src));
6684
6685 format %{ "MOV $src,$dst\t! IntX->Ptr" %}
6686 ins_encode( form3_g0_rs2_rd_move( src, dst ) );
6687 ins_pipe(ialu_reg);
6688 %}
6689
6690 // Cast Pointer to Index for unsafe natives
6691 instruct castP2X(iRegP src, iRegX dst) %{
6692 match(Set dst (CastP2X src));
6693
6694 format %{ "MOV $src,$dst\t! Ptr->IntX" %}
6695 ins_encode( form3_g0_rs2_rd_move( src, dst ) );
6696 ins_pipe(ialu_reg);
6697 %}
6698
6699 instruct stfSSD(stackSlotD stkSlot, regD src) %{
6700 // %%%% TO DO: Tell the coalescer that this kind of node is a copy!
6701 match(Set stkSlot src); // chain rule
6702 ins_cost(MEMORY_REF_COST);
6703 format %{ "STDF $src,$stkSlot\t!stk" %}
6704 opcode(Assembler::stdf_op3);
6705 ins_encode(simple_form3_mem_reg(stkSlot, src));
6706 ins_pipe(fstoreD_stk_reg);
6707 %}
6708
6709 instruct ldfSSD(regD dst, stackSlotD stkSlot) %{
6710 // %%%% TO DO: Tell the coalescer that this kind of node is a copy!
6711 match(Set dst stkSlot); // chain rule
6712 ins_cost(MEMORY_REF_COST);
6713 format %{ "LDDF $stkSlot,$dst\t!stk" %}
6714 opcode(Assembler::lddf_op3);
6715 ins_encode(simple_form3_mem_reg(stkSlot, dst));
6716 ins_pipe(floadD_stk);
6717 %}
6718
6719 instruct stfSSF(stackSlotF stkSlot, regF src) %{
6720 // %%%% TO DO: Tell the coalescer that this kind of node is a copy!
6721 match(Set stkSlot src); // chain rule
6722 ins_cost(MEMORY_REF_COST);
6723 format %{ "STF $src,$stkSlot\t!stk" %}
6724 opcode(Assembler::stf_op3);
6725 ins_encode(simple_form3_mem_reg(stkSlot, src));
6726 ins_pipe(fstoreF_stk_reg);
6727 %}
6728
6729 //----------Conditional Move---------------------------------------------------
6730 // Conditional move
6731 instruct cmovIP_reg(cmpOpP cmp, flagsRegP pcc, iRegI dst, iRegI src) %{
6732 match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src)));
6733 ins_cost(150);
6734 format %{ "MOV$cmp $pcc,$src,$dst" %}
6735 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6736 ins_pipe(ialu_reg);
6737 %}
6738
6739 instruct cmovIP_imm(cmpOpP cmp, flagsRegP pcc, iRegI dst, immI11 src) %{
6740 match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src)));
6741 ins_cost(140);
6742 format %{ "MOV$cmp $pcc,$src,$dst" %}
6743 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
6744 ins_pipe(ialu_imm);
6745 %}
6746
6747 instruct cmovII_reg(cmpOp cmp, flagsReg icc, iRegI dst, iRegI src) %{
6748 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6749 ins_cost(150);
6750 size(4);
6751 format %{ "MOV$cmp $icc,$src,$dst" %}
6752 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6753 ins_pipe(ialu_reg);
6754 %}
6755
6756 instruct cmovII_imm(cmpOp cmp, flagsReg icc, iRegI dst, immI11 src) %{
6757 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6758 ins_cost(140);
6759 size(4);
6760 format %{ "MOV$cmp $icc,$src,$dst" %}
6761 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6762 ins_pipe(ialu_imm);
6763 %}
6764
6765 instruct cmovIIu_reg(cmpOpU cmp, flagsRegU icc, iRegI dst, iRegI src) %{
6766 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6767 ins_cost(150);
6768 size(4);
6769 format %{ "MOV$cmp $icc,$src,$dst" %}
6770 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6771 ins_pipe(ialu_reg);
6772 %}
6773
6774 instruct cmovIIu_imm(cmpOpU cmp, flagsRegU icc, iRegI dst, immI11 src) %{
6775 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6776 ins_cost(140);
6777 size(4);
6778 format %{ "MOV$cmp $icc,$src,$dst" %}
6779 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6780 ins_pipe(ialu_imm);
6781 %}
6782
6783 instruct cmovIF_reg(cmpOpF cmp, flagsRegF fcc, iRegI dst, iRegI src) %{
6784 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src)));
6785 ins_cost(150);
6786 size(4);
6787 format %{ "MOV$cmp $fcc,$src,$dst" %}
6788 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6789 ins_pipe(ialu_reg);
6790 %}
6791
6792 instruct cmovIF_imm(cmpOpF cmp, flagsRegF fcc, iRegI dst, immI11 src) %{
6793 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src)));
6794 ins_cost(140);
6795 size(4);
6796 format %{ "MOV$cmp $fcc,$src,$dst" %}
6797 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) );
6798 ins_pipe(ialu_imm);
6799 %}
6800
6801 // Conditional move for RegN. Only cmov(reg,reg).
6802 instruct cmovNP_reg(cmpOpP cmp, flagsRegP pcc, iRegN dst, iRegN src) %{
6803 match(Set dst (CMoveN (Binary cmp pcc) (Binary dst src)));
6804 ins_cost(150);
6805 format %{ "MOV$cmp $pcc,$src,$dst" %}
6806 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6807 ins_pipe(ialu_reg);
6808 %}
6809
6810 // This instruction also works with CmpN so we don't need cmovNN_reg.
6811 instruct cmovNI_reg(cmpOp cmp, flagsReg icc, iRegN dst, iRegN src) %{
6812 match(Set dst (CMoveN (Binary cmp icc) (Binary dst src)));
6813 ins_cost(150);
6814 size(4);
6815 format %{ "MOV$cmp $icc,$src,$dst" %}
6816 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6817 ins_pipe(ialu_reg);
6818 %}
6819
6820 // This instruction also works with CmpN so we don't need cmovNN_reg.
6821 instruct cmovNIu_reg(cmpOpU cmp, flagsRegU icc, iRegN dst, iRegN src) %{
6822 match(Set dst (CMoveN (Binary cmp icc) (Binary dst src)));
6823 ins_cost(150);
6824 size(4);
6825 format %{ "MOV$cmp $icc,$src,$dst" %}
6826 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6827 ins_pipe(ialu_reg);
6828 %}
6829
6830 instruct cmovNF_reg(cmpOpF cmp, flagsRegF fcc, iRegN dst, iRegN src) %{
6831 match(Set dst (CMoveN (Binary cmp fcc) (Binary dst src)));
6832 ins_cost(150);
6833 size(4);
6834 format %{ "MOV$cmp $fcc,$src,$dst" %}
6835 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6836 ins_pipe(ialu_reg);
6837 %}
6838
6839 // Conditional move
6840 instruct cmovPP_reg(cmpOpP cmp, flagsRegP pcc, iRegP dst, iRegP src) %{
6841 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src)));
6842 ins_cost(150);
6843 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %}
6844 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6845 ins_pipe(ialu_reg);
6846 %}
6847
6848 instruct cmovPP_imm(cmpOpP cmp, flagsRegP pcc, iRegP dst, immP0 src) %{
6849 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src)));
6850 ins_cost(140);
6851 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %}
6852 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
6853 ins_pipe(ialu_imm);
6854 %}
6855
6856 // This instruction also works with CmpN so we don't need cmovPN_reg.
6857 instruct cmovPI_reg(cmpOp cmp, flagsReg icc, iRegP dst, iRegP src) %{
6858 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6859 ins_cost(150);
6860
6861 size(4);
6862 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6863 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6864 ins_pipe(ialu_reg);
6865 %}
6866
6867 instruct cmovPIu_reg(cmpOpU cmp, flagsRegU icc, iRegP dst, iRegP src) %{
6868 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6869 ins_cost(150);
6870
6871 size(4);
6872 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6873 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6874 ins_pipe(ialu_reg);
6875 %}
6876
6877 instruct cmovPI_imm(cmpOp cmp, flagsReg icc, iRegP dst, immP0 src) %{
6878 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6879 ins_cost(140);
6880
6881 size(4);
6882 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6883 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6884 ins_pipe(ialu_imm);
6885 %}
6886
6887 instruct cmovPIu_imm(cmpOpU cmp, flagsRegU icc, iRegP dst, immP0 src) %{
6888 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6889 ins_cost(140);
6890
6891 size(4);
6892 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6893 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6894 ins_pipe(ialu_imm);
6895 %}
6896
6897 instruct cmovPF_reg(cmpOpF cmp, flagsRegF fcc, iRegP dst, iRegP src) %{
6898 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src)));
6899 ins_cost(150);
6900 size(4);
6901 format %{ "MOV$cmp $fcc,$src,$dst" %}
6902 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6903 ins_pipe(ialu_imm);
6904 %}
6905
6906 instruct cmovPF_imm(cmpOpF cmp, flagsRegF fcc, iRegP dst, immP0 src) %{
6907 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src)));
6908 ins_cost(140);
6909 size(4);
6910 format %{ "MOV$cmp $fcc,$src,$dst" %}
6911 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) );
6912 ins_pipe(ialu_imm);
6913 %}
6914
6915 // Conditional move
6916 instruct cmovFP_reg(cmpOpP cmp, flagsRegP pcc, regF dst, regF src) %{
6917 match(Set dst (CMoveF (Binary cmp pcc) (Binary dst src)));
6918 ins_cost(150);
6919 opcode(0x101);
6920 format %{ "FMOVD$cmp $pcc,$src,$dst" %}
6921 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6922 ins_pipe(int_conditional_float_move);
6923 %}
6924
6925 instruct cmovFI_reg(cmpOp cmp, flagsReg icc, regF dst, regF src) %{
6926 match(Set dst (CMoveF (Binary cmp icc) (Binary dst src)));
6927 ins_cost(150);
6928
6929 size(4);
6930 format %{ "FMOVS$cmp $icc,$src,$dst" %}
6931 opcode(0x101);
6932 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
6933 ins_pipe(int_conditional_float_move);
6934 %}
6935
6936 instruct cmovFIu_reg(cmpOpU cmp, flagsRegU icc, regF dst, regF src) %{
6937 match(Set dst (CMoveF (Binary cmp icc) (Binary dst src)));
6938 ins_cost(150);
6939
6940 size(4);
6941 format %{ "FMOVS$cmp $icc,$src,$dst" %}
6942 opcode(0x101);
6943 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
6944 ins_pipe(int_conditional_float_move);
6945 %}
6946
6947 // Conditional move,
6948 instruct cmovFF_reg(cmpOpF cmp, flagsRegF fcc, regF dst, regF src) %{
6949 match(Set dst (CMoveF (Binary cmp fcc) (Binary dst src)));
6950 ins_cost(150);
6951 size(4);
6952 format %{ "FMOVF$cmp $fcc,$src,$dst" %}
6953 opcode(0x1);
6954 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) );
6955 ins_pipe(int_conditional_double_move);
6956 %}
6957
6958 // Conditional move
6959 instruct cmovDP_reg(cmpOpP cmp, flagsRegP pcc, regD dst, regD src) %{
6960 match(Set dst (CMoveD (Binary cmp pcc) (Binary dst src)));
6961 ins_cost(150);
6962 size(4);
6963 opcode(0x102);
6964 format %{ "FMOVD$cmp $pcc,$src,$dst" %}
6965 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6966 ins_pipe(int_conditional_double_move);
6967 %}
6968
6969 instruct cmovDI_reg(cmpOp cmp, flagsReg icc, regD dst, regD src) %{
6970 match(Set dst (CMoveD (Binary cmp icc) (Binary dst src)));
6971 ins_cost(150);
6972
6973 size(4);
6974 format %{ "FMOVD$cmp $icc,$src,$dst" %}
6975 opcode(0x102);
6976 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
6977 ins_pipe(int_conditional_double_move);
6978 %}
6979
6980 instruct cmovDIu_reg(cmpOpU cmp, flagsRegU icc, regD dst, regD src) %{
6981 match(Set dst (CMoveD (Binary cmp icc) (Binary dst src)));
6982 ins_cost(150);
6983
6984 size(4);
6985 format %{ "FMOVD$cmp $icc,$src,$dst" %}
6986 opcode(0x102);
6987 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
6988 ins_pipe(int_conditional_double_move);
6989 %}
6990
6991 // Conditional move,
6992 instruct cmovDF_reg(cmpOpF cmp, flagsRegF fcc, regD dst, regD src) %{
6993 match(Set dst (CMoveD (Binary cmp fcc) (Binary dst src)));
6994 ins_cost(150);
6995 size(4);
6996 format %{ "FMOVD$cmp $fcc,$src,$dst" %}
6997 opcode(0x2);
6998 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) );
6999 ins_pipe(int_conditional_double_move);
7000 %}
7001
7002 // Conditional move
7003 instruct cmovLP_reg(cmpOpP cmp, flagsRegP pcc, iRegL dst, iRegL src) %{
7004 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src)));
7005 ins_cost(150);
7006 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %}
7007 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
7008 ins_pipe(ialu_reg);
7009 %}
7010
7011 instruct cmovLP_imm(cmpOpP cmp, flagsRegP pcc, iRegL dst, immI11 src) %{
7012 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src)));
7013 ins_cost(140);
7014 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %}
7015 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
7016 ins_pipe(ialu_imm);
7017 %}
7018
7019 instruct cmovLI_reg(cmpOp cmp, flagsReg icc, iRegL dst, iRegL src) %{
7020 match(Set dst (CMoveL (Binary cmp icc) (Binary dst src)));
7021 ins_cost(150);
7022
7023 size(4);
7024 format %{ "MOV$cmp $icc,$src,$dst\t! long" %}
7025 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
7026 ins_pipe(ialu_reg);
7027 %}
7028
7029
7030 instruct cmovLIu_reg(cmpOpU cmp, flagsRegU icc, iRegL dst, iRegL src) %{
7031 match(Set dst (CMoveL (Binary cmp icc) (Binary dst src)));
7032 ins_cost(150);
7033
7034 size(4);
7035 format %{ "MOV$cmp $icc,$src,$dst\t! long" %}
7036 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
7037 ins_pipe(ialu_reg);
7038 %}
7039
7040
7041 instruct cmovLF_reg(cmpOpF cmp, flagsRegF fcc, iRegL dst, iRegL src) %{
7042 match(Set dst (CMoveL (Binary cmp fcc) (Binary dst src)));
7043 ins_cost(150);
7044
7045 size(4);
7046 format %{ "MOV$cmp $fcc,$src,$dst\t! long" %}
7047 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
7048 ins_pipe(ialu_reg);
7049 %}
7050
7051
7052
7053 //----------OS and Locking Instructions----------------------------------------
7054
7055 // This name is KNOWN by the ADLC and cannot be changed.
7056 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
7057 // for this guy.
7058 instruct tlsLoadP(g2RegP dst) %{
7059 match(Set dst (ThreadLocal));
7060
7061 size(0);
7062 ins_cost(0);
7063 format %{ "# TLS is in G2" %}
7064 ins_encode( /*empty encoding*/ );
7065 ins_pipe(ialu_none);
7066 %}
7067
7068 instruct checkCastPP( iRegP dst ) %{
7069 match(Set dst (CheckCastPP dst));
7070
7071 size(0);
7072 format %{ "# checkcastPP of $dst" %}
7073 ins_encode( /*empty encoding*/ );
7074 ins_pipe(empty);
7075 %}
7076
7077
7078 instruct castPP( iRegP dst ) %{
7079 match(Set dst (CastPP dst));
7080 format %{ "# castPP of $dst" %}
7081 ins_encode( /*empty encoding*/ );
7082 ins_pipe(empty);
7083 %}
7084
7085 instruct castII( iRegI dst ) %{
7086 match(Set dst (CastII dst));
7087 format %{ "# castII of $dst" %}
7088 ins_encode( /*empty encoding*/ );
7089 ins_cost(0);
7090 ins_pipe(empty);
7091 %}
7092
7093 //----------Arithmetic Instructions--------------------------------------------
7094 // Addition Instructions
7095 // Register Addition
7096 instruct addI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7097 match(Set dst (AddI src1 src2));
7098
7099 size(4);
7100 format %{ "ADD $src1,$src2,$dst" %}
7101 ins_encode %{
7102 __ add($src1$$Register, $src2$$Register, $dst$$Register);
7103 %}
7104 ins_pipe(ialu_reg_reg);
7105 %}
7106
7107 // Immediate Addition
7108 instruct addI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7109 match(Set dst (AddI src1 src2));
7110
7111 size(4);
7112 format %{ "ADD $src1,$src2,$dst" %}
7113 opcode(Assembler::add_op3, Assembler::arith_op);
7114 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7115 ins_pipe(ialu_reg_imm);
7116 %}
7117
7118 // Pointer Register Addition
7119 instruct addP_reg_reg(iRegP dst, iRegP src1, iRegX src2) %{
7120 match(Set dst (AddP src1 src2));
7121
7122 size(4);
7123 format %{ "ADD $src1,$src2,$dst" %}
7124 opcode(Assembler::add_op3, Assembler::arith_op);
7125 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7126 ins_pipe(ialu_reg_reg);
7127 %}
7128
7129 // Pointer Immediate Addition
7130 instruct addP_reg_imm13(iRegP dst, iRegP src1, immX13 src2) %{
7131 match(Set dst (AddP src1 src2));
7132
7133 size(4);
7134 format %{ "ADD $src1,$src2,$dst" %}
7135 opcode(Assembler::add_op3, Assembler::arith_op);
7136 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7137 ins_pipe(ialu_reg_imm);
7138 %}
7139
7140 // Long Addition
7141 instruct addL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7142 match(Set dst (AddL src1 src2));
7143
7144 size(4);
7145 format %{ "ADD $src1,$src2,$dst\t! long" %}
7146 opcode(Assembler::add_op3, Assembler::arith_op);
7147 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7148 ins_pipe(ialu_reg_reg);
7149 %}
7150
7151 instruct addL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7152 match(Set dst (AddL src1 con));
7153
7154 size(4);
7155 format %{ "ADD $src1,$con,$dst" %}
7156 opcode(Assembler::add_op3, Assembler::arith_op);
7157 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7158 ins_pipe(ialu_reg_imm);
7159 %}
7160
7161 //----------Conditional_store--------------------------------------------------
7162 // Conditional-store of the updated heap-top.
7163 // Used during allocation of the shared heap.
7164 // Sets flags (EQ) on success. Implemented with a CASA on Sparc.
7165
7166 // LoadP-locked. Same as a regular pointer load when used with a compare-swap
7167 instruct loadPLocked(iRegP dst, memory mem) %{
7168 match(Set dst (LoadPLocked mem));
7169 ins_cost(MEMORY_REF_COST);
7170
7171 #ifndef _LP64
7172 size(4);
7173 format %{ "LDUW $mem,$dst\t! ptr" %}
7174 opcode(Assembler::lduw_op3, 0, REGP_OP);
7175 #else
7176 format %{ "LDX $mem,$dst\t! ptr" %}
7177 opcode(Assembler::ldx_op3, 0, REGP_OP);
7178 #endif
7179 ins_encode( form3_mem_reg( mem, dst ) );
7180 ins_pipe(iload_mem);
7181 %}
7182
7183 // LoadL-locked. Same as a regular long load when used with a compare-swap
7184 instruct loadLLocked(iRegL dst, memory mem) %{
7185 match(Set dst (LoadLLocked mem));
7186 ins_cost(MEMORY_REF_COST);
7187 size(4);
7188 format %{ "LDX $mem,$dst\t! long" %}
7189 opcode(Assembler::ldx_op3);
7190 ins_encode(simple_form3_mem_reg( mem, dst ) );
7191 ins_pipe(iload_mem);
7192 %}
7193
7194 instruct storePConditional( iRegP heap_top_ptr, iRegP oldval, g3RegP newval, flagsRegP pcc ) %{
7195 match(Set pcc (StorePConditional heap_top_ptr (Binary oldval newval)));
7196 effect( KILL newval );
7197 format %{ "CASA [$heap_top_ptr],$oldval,R_G3\t! If $oldval==[$heap_top_ptr] Then store R_G3 into [$heap_top_ptr], set R_G3=[$heap_top_ptr] in any case\n\t"
7198 "CMP R_G3,$oldval\t\t! See if we made progress" %}
7199 ins_encode( enc_cas(heap_top_ptr,oldval,newval) );
7200 ins_pipe( long_memory_op );
7201 %}
7202
7203 // Conditional-store of an int value.
7204 instruct storeIConditional( iRegP mem_ptr, iRegI oldval, g3RegI newval, flagsReg icc ) %{
7205 match(Set icc (StoreIConditional mem_ptr (Binary oldval newval)));
7206 effect( KILL newval );
7207 format %{ "CASA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t"
7208 "CMP $oldval,$newval\t\t! See if we made progress" %}
7209 ins_encode( enc_cas(mem_ptr,oldval,newval) );
7210 ins_pipe( long_memory_op );
7211 %}
7212
7213 // Conditional-store of a long value.
7214 instruct storeLConditional( iRegP mem_ptr, iRegL oldval, g3RegL newval, flagsRegL xcc ) %{
7215 match(Set xcc (StoreLConditional mem_ptr (Binary oldval newval)));
7216 effect( KILL newval );
7217 format %{ "CASXA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t"
7218 "CMP $oldval,$newval\t\t! See if we made progress" %}
7219 ins_encode( enc_cas(mem_ptr,oldval,newval) );
7220 ins_pipe( long_memory_op );
7221 %}
7222
7223 // No flag versions for CompareAndSwap{P,I,L} because matcher can't match them
7224
7225 instruct compareAndSwapL_bool(iRegP mem_ptr, iRegL oldval, iRegL newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
7226 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
7227 effect( USE mem_ptr, KILL ccr, KILL tmp1);
7228 format %{
7229 "MOV $newval,O7\n\t"
7230 "CASXA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
7231 "CMP $oldval,O7\t\t! See if we made progress\n\t"
7232 "MOV 1,$res\n\t"
7233 "MOVne xcc,R_G0,$res"
7234 %}
7235 ins_encode( enc_casx(mem_ptr, oldval, newval),
7236 enc_lflags_ne_to_boolean(res) );
7237 ins_pipe( long_memory_op );
7238 %}
7239
7240
7241 instruct compareAndSwapI_bool(iRegP mem_ptr, iRegI oldval, iRegI newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
7242 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
7243 effect( USE mem_ptr, KILL ccr, KILL tmp1);
7244 format %{
7245 "MOV $newval,O7\n\t"
7246 "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
7247 "CMP $oldval,O7\t\t! See if we made progress\n\t"
7248 "MOV 1,$res\n\t"
7249 "MOVne icc,R_G0,$res"
7250 %}
7251 ins_encode( enc_casi(mem_ptr, oldval, newval),
7252 enc_iflags_ne_to_boolean(res) );
7253 ins_pipe( long_memory_op );
7254 %}
7255
7256 instruct compareAndSwapP_bool(iRegP mem_ptr, iRegP oldval, iRegP newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
7257 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
7258 effect( USE mem_ptr, KILL ccr, KILL tmp1);
7259 format %{
7260 "MOV $newval,O7\n\t"
7261 "CASA_PTR [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
7262 "CMP $oldval,O7\t\t! See if we made progress\n\t"
7263 "MOV 1,$res\n\t"
7264 "MOVne xcc,R_G0,$res"
7265 %}
7266 #ifdef _LP64
7267 ins_encode( enc_casx(mem_ptr, oldval, newval),
7268 enc_lflags_ne_to_boolean(res) );
7269 #else
7270 ins_encode( enc_casi(mem_ptr, oldval, newval),
7271 enc_iflags_ne_to_boolean(res) );
7272 #endif
7273 ins_pipe( long_memory_op );
7274 %}
7275
7276 instruct compareAndSwapN_bool(iRegP mem_ptr, iRegN oldval, iRegN newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
7277 match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval)));
7278 effect( USE mem_ptr, KILL ccr, KILL tmp1);
7279 format %{
7280 "MOV $newval,O7\n\t"
7281 "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
7282 "CMP $oldval,O7\t\t! See if we made progress\n\t"
7283 "MOV 1,$res\n\t"
7284 "MOVne icc,R_G0,$res"
7285 %}
7286 ins_encode( enc_casi(mem_ptr, oldval, newval),
7287 enc_iflags_ne_to_boolean(res) );
7288 ins_pipe( long_memory_op );
7289 %}
7290
7291 //---------------------
7292 // Subtraction Instructions
7293 // Register Subtraction
7294 instruct subI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7295 match(Set dst (SubI src1 src2));
7296
7297 size(4);
7298 format %{ "SUB $src1,$src2,$dst" %}
7299 opcode(Assembler::sub_op3, Assembler::arith_op);
7300 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7301 ins_pipe(ialu_reg_reg);
7302 %}
7303
7304 // Immediate Subtraction
7305 instruct subI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7306 match(Set dst (SubI src1 src2));
7307
7308 size(4);
7309 format %{ "SUB $src1,$src2,$dst" %}
7310 opcode(Assembler::sub_op3, Assembler::arith_op);
7311 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7312 ins_pipe(ialu_reg_imm);
7313 %}
7314
7315 instruct subI_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{
7316 match(Set dst (SubI zero src2));
7317
7318 size(4);
7319 format %{ "NEG $src2,$dst" %}
7320 opcode(Assembler::sub_op3, Assembler::arith_op);
7321 ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) );
7322 ins_pipe(ialu_zero_reg);
7323 %}
7324
7325 // Long subtraction
7326 instruct subL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7327 match(Set dst (SubL src1 src2));
7328
7329 size(4);
7330 format %{ "SUB $src1,$src2,$dst\t! long" %}
7331 opcode(Assembler::sub_op3, Assembler::arith_op);
7332 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7333 ins_pipe(ialu_reg_reg);
7334 %}
7335
7336 // Immediate Subtraction
7337 instruct subL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7338 match(Set dst (SubL src1 con));
7339
7340 size(4);
7341 format %{ "SUB $src1,$con,$dst\t! long" %}
7342 opcode(Assembler::sub_op3, Assembler::arith_op);
7343 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7344 ins_pipe(ialu_reg_imm);
7345 %}
7346
7347 // Long negation
7348 instruct negL_reg_reg(iRegL dst, immL0 zero, iRegL src2) %{
7349 match(Set dst (SubL zero src2));
7350
7351 size(4);
7352 format %{ "NEG $src2,$dst\t! long" %}
7353 opcode(Assembler::sub_op3, Assembler::arith_op);
7354 ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) );
7355 ins_pipe(ialu_zero_reg);
7356 %}
7357
7358 // Multiplication Instructions
7359 // Integer Multiplication
7360 // Register Multiplication
7361 instruct mulI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7362 match(Set dst (MulI src1 src2));
7363
7364 size(4);
7365 format %{ "MULX $src1,$src2,$dst" %}
7366 opcode(Assembler::mulx_op3, Assembler::arith_op);
7367 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7368 ins_pipe(imul_reg_reg);
7369 %}
7370
7371 // Immediate Multiplication
7372 instruct mulI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7373 match(Set dst (MulI src1 src2));
7374
7375 size(4);
7376 format %{ "MULX $src1,$src2,$dst" %}
7377 opcode(Assembler::mulx_op3, Assembler::arith_op);
7378 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7379 ins_pipe(imul_reg_imm);
7380 %}
7381
7382 instruct mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7383 match(Set dst (MulL src1 src2));
7384 ins_cost(DEFAULT_COST * 5);
7385 size(4);
7386 format %{ "MULX $src1,$src2,$dst\t! long" %}
7387 opcode(Assembler::mulx_op3, Assembler::arith_op);
7388 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7389 ins_pipe(mulL_reg_reg);
7390 %}
7391
7392 // Immediate Multiplication
7393 instruct mulL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{
7394 match(Set dst (MulL src1 src2));
7395 ins_cost(DEFAULT_COST * 5);
7396 size(4);
7397 format %{ "MULX $src1,$src2,$dst" %}
7398 opcode(Assembler::mulx_op3, Assembler::arith_op);
7399 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7400 ins_pipe(mulL_reg_imm);
7401 %}
7402
7403 // Integer Division
7404 // Register Division
7405 instruct divI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2) %{
7406 match(Set dst (DivI src1 src2));
7407 ins_cost((2+71)*DEFAULT_COST);
7408
7409 format %{ "SRA $src2,0,$src2\n\t"
7410 "SRA $src1,0,$src1\n\t"
7411 "SDIVX $src1,$src2,$dst" %}
7412 ins_encode( idiv_reg( src1, src2, dst ) );
7413 ins_pipe(sdiv_reg_reg);
7414 %}
7415
7416 // Immediate Division
7417 instruct divI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2) %{
7418 match(Set dst (DivI src1 src2));
7419 ins_cost((2+71)*DEFAULT_COST);
7420
7421 format %{ "SRA $src1,0,$src1\n\t"
7422 "SDIVX $src1,$src2,$dst" %}
7423 ins_encode( idiv_imm( src1, src2, dst ) );
7424 ins_pipe(sdiv_reg_imm);
7425 %}
7426
7427 //----------Div-By-10-Expansion------------------------------------------------
7428 // Extract hi bits of a 32x32->64 bit multiply.
7429 // Expand rule only, not matched
7430 instruct mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2 ) %{
7431 effect( DEF dst, USE src1, USE src2 );
7432 format %{ "MULX $src1,$src2,$dst\t! Used in div-by-10\n\t"
7433 "SRLX $dst,#32,$dst\t\t! Extract only hi word of result" %}
7434 ins_encode( enc_mul_hi(dst,src1,src2));
7435 ins_pipe(sdiv_reg_reg);
7436 %}
7437
7438 // Magic constant, reciprocal of 10
7439 instruct loadConI_x66666667(iRegIsafe dst) %{
7440 effect( DEF dst );
7441
7442 size(8);
7443 format %{ "SET 0x66666667,$dst\t! Used in div-by-10" %}
7444 ins_encode( Set32(0x66666667, dst) );
7445 ins_pipe(ialu_hi_lo_reg);
7446 %}
7447
7448 // Register Shift Right Arithmetic Long by 32-63
7449 instruct sra_31( iRegI dst, iRegI src ) %{
7450 effect( DEF dst, USE src );
7451 format %{ "SRA $src,31,$dst\t! Used in div-by-10" %}
7452 ins_encode( form3_rs1_rd_copysign_hi(src,dst) );
7453 ins_pipe(ialu_reg_reg);
7454 %}
7455
7456 // Arithmetic Shift Right by 8-bit immediate
7457 instruct sra_reg_2( iRegI dst, iRegI src ) %{
7458 effect( DEF dst, USE src );
7459 format %{ "SRA $src,2,$dst\t! Used in div-by-10" %}
7460 opcode(Assembler::sra_op3, Assembler::arith_op);
7461 ins_encode( form3_rs1_simm13_rd( src, 0x2, dst ) );
7462 ins_pipe(ialu_reg_imm);
7463 %}
7464
7465 // Integer DIV with 10
7466 instruct divI_10( iRegI dst, iRegIsafe src, immI10 div ) %{
7467 match(Set dst (DivI src div));
7468 ins_cost((6+6)*DEFAULT_COST);
7469 expand %{
7470 iRegIsafe tmp1; // Killed temps;
7471 iRegIsafe tmp2; // Killed temps;
7472 iRegI tmp3; // Killed temps;
7473 iRegI tmp4; // Killed temps;
7474 loadConI_x66666667( tmp1 ); // SET 0x66666667 -> tmp1
7475 mul_hi( tmp2, src, tmp1 ); // MUL hibits(src * tmp1) -> tmp2
7476 sra_31( tmp3, src ); // SRA src,31 -> tmp3
7477 sra_reg_2( tmp4, tmp2 ); // SRA tmp2,2 -> tmp4
7478 subI_reg_reg( dst,tmp4,tmp3); // SUB tmp4 - tmp3 -> dst
7479 %}
7480 %}
7481
7482 // Register Long Division
7483 instruct divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7484 match(Set dst (DivL src1 src2));
7485 ins_cost(DEFAULT_COST*71);
7486 size(4);
7487 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7488 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7489 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7490 ins_pipe(divL_reg_reg);
7491 %}
7492
7493 // Register Long Division
7494 instruct divL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{
7495 match(Set dst (DivL src1 src2));
7496 ins_cost(DEFAULT_COST*71);
7497 size(4);
7498 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7499 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7500 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7501 ins_pipe(divL_reg_imm);
7502 %}
7503
7504 // Integer Remainder
7505 // Register Remainder
7506 instruct modI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2, o7RegP temp, flagsReg ccr ) %{
7507 match(Set dst (ModI src1 src2));
7508 effect( KILL ccr, KILL temp);
7509
7510 format %{ "SREM $src1,$src2,$dst" %}
7511 ins_encode( irem_reg(src1, src2, dst, temp) );
7512 ins_pipe(sdiv_reg_reg);
7513 %}
7514
7515 // Immediate Remainder
7516 instruct modI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2, o7RegP temp, flagsReg ccr ) %{
7517 match(Set dst (ModI src1 src2));
7518 effect( KILL ccr, KILL temp);
7519
7520 format %{ "SREM $src1,$src2,$dst" %}
7521 ins_encode( irem_imm(src1, src2, dst, temp) );
7522 ins_pipe(sdiv_reg_imm);
7523 %}
7524
7525 // Register Long Remainder
7526 instruct divL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{
7527 effect(DEF dst, USE src1, USE src2);
7528 size(4);
7529 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7530 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7531 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7532 ins_pipe(divL_reg_reg);
7533 %}
7534
7535 // Register Long Division
7536 instruct divL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{
7537 effect(DEF dst, USE src1, USE src2);
7538 size(4);
7539 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7540 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7541 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7542 ins_pipe(divL_reg_imm);
7543 %}
7544
7545 instruct mulL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{
7546 effect(DEF dst, USE src1, USE src2);
7547 size(4);
7548 format %{ "MULX $src1,$src2,$dst\t! long" %}
7549 opcode(Assembler::mulx_op3, Assembler::arith_op);
7550 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7551 ins_pipe(mulL_reg_reg);
7552 %}
7553
7554 // Immediate Multiplication
7555 instruct mulL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{
7556 effect(DEF dst, USE src1, USE src2);
7557 size(4);
7558 format %{ "MULX $src1,$src2,$dst" %}
7559 opcode(Assembler::mulx_op3, Assembler::arith_op);
7560 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7561 ins_pipe(mulL_reg_imm);
7562 %}
7563
7564 instruct subL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{
7565 effect(DEF dst, USE src1, USE src2);
7566 size(4);
7567 format %{ "SUB $src1,$src2,$dst\t! long" %}
7568 opcode(Assembler::sub_op3, Assembler::arith_op);
7569 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7570 ins_pipe(ialu_reg_reg);
7571 %}
7572
7573 instruct subL_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{
7574 effect(DEF dst, USE src1, USE src2);
7575 size(4);
7576 format %{ "SUB $src1,$src2,$dst\t! long" %}
7577 opcode(Assembler::sub_op3, Assembler::arith_op);
7578 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7579 ins_pipe(ialu_reg_reg);
7580 %}
7581
7582 // Register Long Remainder
7583 instruct modL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7584 match(Set dst (ModL src1 src2));
7585 ins_cost(DEFAULT_COST*(71 + 6 + 1));
7586 expand %{
7587 iRegL tmp1;
7588 iRegL tmp2;
7589 divL_reg_reg_1(tmp1, src1, src2);
7590 mulL_reg_reg_1(tmp2, tmp1, src2);
7591 subL_reg_reg_1(dst, src1, tmp2);
7592 %}
7593 %}
7594
7595 // Register Long Remainder
7596 instruct modL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{
7597 match(Set dst (ModL src1 src2));
7598 ins_cost(DEFAULT_COST*(71 + 6 + 1));
7599 expand %{
7600 iRegL tmp1;
7601 iRegL tmp2;
7602 divL_reg_imm13_1(tmp1, src1, src2);
7603 mulL_reg_imm13_1(tmp2, tmp1, src2);
7604 subL_reg_reg_2 (dst, src1, tmp2);
7605 %}
7606 %}
7607
7608 // Integer Shift Instructions
7609 // Register Shift Left
7610 instruct shlI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7611 match(Set dst (LShiftI src1 src2));
7612
7613 size(4);
7614 format %{ "SLL $src1,$src2,$dst" %}
7615 opcode(Assembler::sll_op3, Assembler::arith_op);
7616 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7617 ins_pipe(ialu_reg_reg);
7618 %}
7619
7620 // Register Shift Left Immediate
7621 instruct shlI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{
7622 match(Set dst (LShiftI src1 src2));
7623
7624 size(4);
7625 format %{ "SLL $src1,$src2,$dst" %}
7626 opcode(Assembler::sll_op3, Assembler::arith_op);
7627 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7628 ins_pipe(ialu_reg_imm);
7629 %}
7630
7631 // Register Shift Left
7632 instruct shlL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
7633 match(Set dst (LShiftL src1 src2));
7634
7635 size(4);
7636 format %{ "SLLX $src1,$src2,$dst" %}
7637 opcode(Assembler::sllx_op3, Assembler::arith_op);
7638 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) );
7639 ins_pipe(ialu_reg_reg);
7640 %}
7641
7642 // Register Shift Left Immediate
7643 instruct shlL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
7644 match(Set dst (LShiftL src1 src2));
7645
7646 size(4);
7647 format %{ "SLLX $src1,$src2,$dst" %}
7648 opcode(Assembler::sllx_op3, Assembler::arith_op);
7649 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7650 ins_pipe(ialu_reg_imm);
7651 %}
7652
7653 // Register Arithmetic Shift Right
7654 instruct sarI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7655 match(Set dst (RShiftI src1 src2));
7656 size(4);
7657 format %{ "SRA $src1,$src2,$dst" %}
7658 opcode(Assembler::sra_op3, Assembler::arith_op);
7659 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7660 ins_pipe(ialu_reg_reg);
7661 %}
7662
7663 // Register Arithmetic Shift Right Immediate
7664 instruct sarI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{
7665 match(Set dst (RShiftI src1 src2));
7666
7667 size(4);
7668 format %{ "SRA $src1,$src2,$dst" %}
7669 opcode(Assembler::sra_op3, Assembler::arith_op);
7670 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7671 ins_pipe(ialu_reg_imm);
7672 %}
7673
7674 // Register Shift Right Arithmatic Long
7675 instruct sarL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
7676 match(Set dst (RShiftL src1 src2));
7677
7678 size(4);
7679 format %{ "SRAX $src1,$src2,$dst" %}
7680 opcode(Assembler::srax_op3, Assembler::arith_op);
7681 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) );
7682 ins_pipe(ialu_reg_reg);
7683 %}
7684
7685 // Register Shift Left Immediate
7686 instruct sarL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
7687 match(Set dst (RShiftL src1 src2));
7688
7689 size(4);
7690 format %{ "SRAX $src1,$src2,$dst" %}
7691 opcode(Assembler::srax_op3, Assembler::arith_op);
7692 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7693 ins_pipe(ialu_reg_imm);
7694 %}
7695
7696 // Register Shift Right
7697 instruct shrI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7698 match(Set dst (URShiftI src1 src2));
7699
7700 size(4);
7701 format %{ "SRL $src1,$src2,$dst" %}
7702 opcode(Assembler::srl_op3, Assembler::arith_op);
7703 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7704 ins_pipe(ialu_reg_reg);
7705 %}
7706
7707 // Register Shift Right Immediate
7708 instruct shrI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{
7709 match(Set dst (URShiftI src1 src2));
7710
7711 size(4);
7712 format %{ "SRL $src1,$src2,$dst" %}
7713 opcode(Assembler::srl_op3, Assembler::arith_op);
7714 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7715 ins_pipe(ialu_reg_imm);
7716 %}
7717
7718 // Register Shift Right
7719 instruct shrL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
7720 match(Set dst (URShiftL src1 src2));
7721
7722 size(4);
7723 format %{ "SRLX $src1,$src2,$dst" %}
7724 opcode(Assembler::srlx_op3, Assembler::arith_op);
7725 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) );
7726 ins_pipe(ialu_reg_reg);
7727 %}
7728
7729 // Register Shift Right Immediate
7730 instruct shrL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
7731 match(Set dst (URShiftL src1 src2));
7732
7733 size(4);
7734 format %{ "SRLX $src1,$src2,$dst" %}
7735 opcode(Assembler::srlx_op3, Assembler::arith_op);
7736 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7737 ins_pipe(ialu_reg_imm);
7738 %}
7739
7740 // Register Shift Right Immediate with a CastP2X
7741 #ifdef _LP64
7742 instruct shrP_reg_imm6(iRegL dst, iRegP src1, immU6 src2) %{
7743 match(Set dst (URShiftL (CastP2X src1) src2));
7744 size(4);
7745 format %{ "SRLX $src1,$src2,$dst\t! Cast ptr $src1 to long and shift" %}
7746 opcode(Assembler::srlx_op3, Assembler::arith_op);
7747 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7748 ins_pipe(ialu_reg_imm);
7749 %}
7750 #else
7751 instruct shrP_reg_imm5(iRegI dst, iRegP src1, immU5 src2) %{
7752 match(Set dst (URShiftI (CastP2X src1) src2));
7753 size(4);
7754 format %{ "SRL $src1,$src2,$dst\t! Cast ptr $src1 to int and shift" %}
7755 opcode(Assembler::srl_op3, Assembler::arith_op);
7756 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7757 ins_pipe(ialu_reg_imm);
7758 %}
7759 #endif
7760
7761
7762 //----------Floating Point Arithmetic Instructions-----------------------------
7763
7764 // Add float single precision
7765 instruct addF_reg_reg(regF dst, regF src1, regF src2) %{
7766 match(Set dst (AddF src1 src2));
7767
7768 size(4);
7769 format %{ "FADDS $src1,$src2,$dst" %}
7770 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fadds_opf);
7771 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7772 ins_pipe(faddF_reg_reg);
7773 %}
7774
7775 // Add float double precision
7776 instruct addD_reg_reg(regD dst, regD src1, regD src2) %{
7777 match(Set dst (AddD src1 src2));
7778
7779 size(4);
7780 format %{ "FADDD $src1,$src2,$dst" %}
7781 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf);
7782 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7783 ins_pipe(faddD_reg_reg);
7784 %}
7785
7786 // Sub float single precision
7787 instruct subF_reg_reg(regF dst, regF src1, regF src2) %{
7788 match(Set dst (SubF src1 src2));
7789
7790 size(4);
7791 format %{ "FSUBS $src1,$src2,$dst" %}
7792 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubs_opf);
7793 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7794 ins_pipe(faddF_reg_reg);
7795 %}
7796
7797 // Sub float double precision
7798 instruct subD_reg_reg(regD dst, regD src1, regD src2) %{
7799 match(Set dst (SubD src1 src2));
7800
7801 size(4);
7802 format %{ "FSUBD $src1,$src2,$dst" %}
7803 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf);
7804 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7805 ins_pipe(faddD_reg_reg);
7806 %}
7807
7808 // Mul float single precision
7809 instruct mulF_reg_reg(regF dst, regF src1, regF src2) %{
7810 match(Set dst (MulF src1 src2));
7811
7812 size(4);
7813 format %{ "FMULS $src1,$src2,$dst" %}
7814 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuls_opf);
7815 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7816 ins_pipe(fmulF_reg_reg);
7817 %}
7818
7819 // Mul float double precision
7820 instruct mulD_reg_reg(regD dst, regD src1, regD src2) %{
7821 match(Set dst (MulD src1 src2));
7822
7823 size(4);
7824 format %{ "FMULD $src1,$src2,$dst" %}
7825 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf);
7826 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7827 ins_pipe(fmulD_reg_reg);
7828 %}
7829
7830 // Div float single precision
7831 instruct divF_reg_reg(regF dst, regF src1, regF src2) %{
7832 match(Set dst (DivF src1 src2));
7833
7834 size(4);
7835 format %{ "FDIVS $src1,$src2,$dst" %}
7836 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivs_opf);
7837 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7838 ins_pipe(fdivF_reg_reg);
7839 %}
7840
7841 // Div float double precision
7842 instruct divD_reg_reg(regD dst, regD src1, regD src2) %{
7843 match(Set dst (DivD src1 src2));
7844
7845 size(4);
7846 format %{ "FDIVD $src1,$src2,$dst" %}
7847 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivd_opf);
7848 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7849 ins_pipe(fdivD_reg_reg);
7850 %}
7851
7852 // Absolute float double precision
7853 instruct absD_reg(regD dst, regD src) %{
7854 match(Set dst (AbsD src));
7855
7856 format %{ "FABSd $src,$dst" %}
7857 ins_encode(fabsd(dst, src));
7858 ins_pipe(faddD_reg);
7859 %}
7860
7861 // Absolute float single precision
7862 instruct absF_reg(regF dst, regF src) %{
7863 match(Set dst (AbsF src));
7864
7865 format %{ "FABSs $src,$dst" %}
7866 ins_encode(fabss(dst, src));
7867 ins_pipe(faddF_reg);
7868 %}
7869
7870 instruct negF_reg(regF dst, regF src) %{
7871 match(Set dst (NegF src));
7872
7873 size(4);
7874 format %{ "FNEGs $src,$dst" %}
7875 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fnegs_opf);
7876 ins_encode(form3_opf_rs2F_rdF(src, dst));
7877 ins_pipe(faddF_reg);
7878 %}
7879
7880 instruct negD_reg(regD dst, regD src) %{
7881 match(Set dst (NegD src));
7882
7883 format %{ "FNEGd $src,$dst" %}
7884 ins_encode(fnegd(dst, src));
7885 ins_pipe(faddD_reg);
7886 %}
7887
7888 // Sqrt float double precision
7889 instruct sqrtF_reg_reg(regF dst, regF src) %{
7890 match(Set dst (ConvD2F (SqrtD (ConvF2D src))));
7891
7892 size(4);
7893 format %{ "FSQRTS $src,$dst" %}
7894 ins_encode(fsqrts(dst, src));
7895 ins_pipe(fdivF_reg_reg);
7896 %}
7897
7898 // Sqrt float double precision
7899 instruct sqrtD_reg_reg(regD dst, regD src) %{
7900 match(Set dst (SqrtD src));
7901
7902 size(4);
7903 format %{ "FSQRTD $src,$dst" %}
7904 ins_encode(fsqrtd(dst, src));
7905 ins_pipe(fdivD_reg_reg);
7906 %}
7907
7908 //----------Logical Instructions-----------------------------------------------
7909 // And Instructions
7910 // Register And
7911 instruct andI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7912 match(Set dst (AndI src1 src2));
7913
7914 size(4);
7915 format %{ "AND $src1,$src2,$dst" %}
7916 opcode(Assembler::and_op3, Assembler::arith_op);
7917 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7918 ins_pipe(ialu_reg_reg);
7919 %}
7920
7921 // Immediate And
7922 instruct andI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7923 match(Set dst (AndI src1 src2));
7924
7925 size(4);
7926 format %{ "AND $src1,$src2,$dst" %}
7927 opcode(Assembler::and_op3, Assembler::arith_op);
7928 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7929 ins_pipe(ialu_reg_imm);
7930 %}
7931
7932 // Register And Long
7933 instruct andL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7934 match(Set dst (AndL src1 src2));
7935
7936 ins_cost(DEFAULT_COST);
7937 size(4);
7938 format %{ "AND $src1,$src2,$dst\t! long" %}
7939 opcode(Assembler::and_op3, Assembler::arith_op);
7940 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7941 ins_pipe(ialu_reg_reg);
7942 %}
7943
7944 instruct andL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7945 match(Set dst (AndL src1 con));
7946
7947 ins_cost(DEFAULT_COST);
7948 size(4);
7949 format %{ "AND $src1,$con,$dst\t! long" %}
7950 opcode(Assembler::and_op3, Assembler::arith_op);
7951 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7952 ins_pipe(ialu_reg_imm);
7953 %}
7954
7955 // Or Instructions
7956 // Register Or
7957 instruct orI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7958 match(Set dst (OrI src1 src2));
7959
7960 size(4);
7961 format %{ "OR $src1,$src2,$dst" %}
7962 opcode(Assembler::or_op3, Assembler::arith_op);
7963 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7964 ins_pipe(ialu_reg_reg);
7965 %}
7966
7967 // Immediate Or
7968 instruct orI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7969 match(Set dst (OrI src1 src2));
7970
7971 size(4);
7972 format %{ "OR $src1,$src2,$dst" %}
7973 opcode(Assembler::or_op3, Assembler::arith_op);
7974 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7975 ins_pipe(ialu_reg_imm);
7976 %}
7977
7978 // Register Or Long
7979 instruct orL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7980 match(Set dst (OrL src1 src2));
7981
7982 ins_cost(DEFAULT_COST);
7983 size(4);
7984 format %{ "OR $src1,$src2,$dst\t! long" %}
7985 opcode(Assembler::or_op3, Assembler::arith_op);
7986 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7987 ins_pipe(ialu_reg_reg);
7988 %}
7989
7990 instruct orL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7991 match(Set dst (OrL src1 con));
7992 ins_cost(DEFAULT_COST*2);
7993
7994 ins_cost(DEFAULT_COST);
7995 size(4);
7996 format %{ "OR $src1,$con,$dst\t! long" %}
7997 opcode(Assembler::or_op3, Assembler::arith_op);
7998 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7999 ins_pipe(ialu_reg_imm);
8000 %}
8001
8002 #ifndef _LP64
8003
8004 // Use sp_ptr_RegP to match G2 (TLS register) without spilling.
8005 instruct orI_reg_castP2X(iRegI dst, iRegI src1, sp_ptr_RegP src2) %{
8006 match(Set dst (OrI src1 (CastP2X src2)));
8007
8008 size(4);
8009 format %{ "OR $src1,$src2,$dst" %}
8010 opcode(Assembler::or_op3, Assembler::arith_op);
8011 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
8012 ins_pipe(ialu_reg_reg);
8013 %}
8014
8015 #else
8016
8017 instruct orL_reg_castP2X(iRegL dst, iRegL src1, sp_ptr_RegP src2) %{
8018 match(Set dst (OrL src1 (CastP2X src2)));
8019
8020 ins_cost(DEFAULT_COST);
8021 size(4);
8022 format %{ "OR $src1,$src2,$dst\t! long" %}
8023 opcode(Assembler::or_op3, Assembler::arith_op);
8024 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
8025 ins_pipe(ialu_reg_reg);
8026 %}
8027
8028 #endif
8029
8030 // Xor Instructions
8031 // Register Xor
8032 instruct xorI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
8033 match(Set dst (XorI src1 src2));
8034
8035 size(4);
8036 format %{ "XOR $src1,$src2,$dst" %}
8037 opcode(Assembler::xor_op3, Assembler::arith_op);
8038 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
8039 ins_pipe(ialu_reg_reg);
8040 %}
8041
8042 // Immediate Xor
8043 instruct xorI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
8044 match(Set dst (XorI src1 src2));
8045
8046 size(4);
8047 format %{ "XOR $src1,$src2,$dst" %}
8048 opcode(Assembler::xor_op3, Assembler::arith_op);
8049 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
8050 ins_pipe(ialu_reg_imm);
8051 %}
8052
8053 // Register Xor Long
8054 instruct xorL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
8055 match(Set dst (XorL src1 src2));
8056
8057 ins_cost(DEFAULT_COST);
8058 size(4);
8059 format %{ "XOR $src1,$src2,$dst\t! long" %}
8060 opcode(Assembler::xor_op3, Assembler::arith_op);
8061 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
8062 ins_pipe(ialu_reg_reg);
8063 %}
8064
8065 instruct xorL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
8066 match(Set dst (XorL src1 con));
8067
8068 ins_cost(DEFAULT_COST);
8069 size(4);
8070 format %{ "XOR $src1,$con,$dst\t! long" %}
8071 opcode(Assembler::xor_op3, Assembler::arith_op);
8072 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
8073 ins_pipe(ialu_reg_imm);
8074 %}
8075
8076 //----------Convert to Boolean-------------------------------------------------
8077 // Nice hack for 32-bit tests but doesn't work for
8078 // 64-bit pointers.
8079 instruct convI2B( iRegI dst, iRegI src, flagsReg ccr ) %{
8080 match(Set dst (Conv2B src));
8081 effect( KILL ccr );
8082 ins_cost(DEFAULT_COST*2);
8083 format %{ "CMP R_G0,$src\n\t"
8084 "ADDX R_G0,0,$dst" %}
8085 ins_encode( enc_to_bool( src, dst ) );
8086 ins_pipe(ialu_reg_ialu);
8087 %}
8088
8089 #ifndef _LP64
8090 instruct convP2B( iRegI dst, iRegP src, flagsReg ccr ) %{
8091 match(Set dst (Conv2B src));
8092 effect( KILL ccr );
8093 ins_cost(DEFAULT_COST*2);
8094 format %{ "CMP R_G0,$src\n\t"
8095 "ADDX R_G0,0,$dst" %}
8096 ins_encode( enc_to_bool( src, dst ) );
8097 ins_pipe(ialu_reg_ialu);
8098 %}
8099 #else
8100 instruct convP2B( iRegI dst, iRegP src ) %{
8101 match(Set dst (Conv2B src));
8102 ins_cost(DEFAULT_COST*2);
8103 format %{ "MOV $src,$dst\n\t"
8104 "MOVRNZ $src,1,$dst" %}
8105 ins_encode( form3_g0_rs2_rd_move( src, dst ), enc_convP2B( dst, src ) );
8106 ins_pipe(ialu_clr_and_mover);
8107 %}
8108 #endif
8109
8110 instruct cmpLTMask0( iRegI dst, iRegI src, immI0 zero, flagsReg ccr ) %{
8111 match(Set dst (CmpLTMask src zero));
8112 effect(KILL ccr);
8113 size(4);
8114 format %{ "SRA $src,#31,$dst\t# cmpLTMask0" %}
8115 ins_encode %{
8116 __ sra($src$$Register, 31, $dst$$Register);
8117 %}
8118 ins_pipe(ialu_reg_imm);
8119 %}
8120
8121 instruct cmpLTMask_reg_reg( iRegI dst, iRegI p, iRegI q, flagsReg ccr ) %{
8122 match(Set dst (CmpLTMask p q));
8123 effect( KILL ccr );
8124 ins_cost(DEFAULT_COST*4);
8125 format %{ "CMP $p,$q\n\t"
8126 "MOV #0,$dst\n\t"
8127 "BLT,a .+8\n\t"
8128 "MOV #-1,$dst" %}
8129 ins_encode( enc_ltmask(p,q,dst) );
8130 ins_pipe(ialu_reg_reg_ialu);
8131 %}
8132
8133 instruct cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp, flagsReg ccr ) %{
8134 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)));
8135 effect(KILL ccr, TEMP tmp);
8136 ins_cost(DEFAULT_COST*3);
8137
8138 format %{ "SUBcc $p,$q,$p\t! p' = p-q\n\t"
8139 "ADD $p,$y,$tmp\t! g3=p-q+y\n\t"
8140 "MOVlt $tmp,$p\t! p' < 0 ? p'+y : p'" %}
8141 ins_encode( enc_cadd_cmpLTMask(p, q, y, tmp) );
8142 ins_pipe( cadd_cmpltmask );
8143 %}
8144
8145 //----------Arithmetic Conversion Instructions---------------------------------
8146 // The conversions operations are all Alpha sorted. Please keep it that way!
8147
8148 instruct convD2F_reg(regF dst, regD src) %{
8149 match(Set dst (ConvD2F src));
8150 size(4);
8151 format %{ "FDTOS $src,$dst" %}
8152 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdtos_opf);
8153 ins_encode(form3_opf_rs2D_rdF(src, dst));
8154 ins_pipe(fcvtD2F);
8155 %}
8156
8157
8158 // Convert a double to an int in a float register.
8159 // If the double is a NAN, stuff a zero in instead.
8160 instruct convD2I_helper(regF dst, regD src, flagsRegF0 fcc0) %{
8161 effect(DEF dst, USE src, KILL fcc0);
8162 format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t"
8163 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8164 "FDTOI $src,$dst\t! convert in delay slot\n\t"
8165 "FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t"
8166 "FSUBs $dst,$dst,$dst\t! cleared only if nan\n"
8167 "skip:" %}
8168 ins_encode(form_d2i_helper(src,dst));
8169 ins_pipe(fcvtD2I);
8170 %}
8171
8172 instruct convD2I_reg(stackSlotI dst, regD src) %{
8173 match(Set dst (ConvD2I src));
8174 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8175 expand %{
8176 regF tmp;
8177 convD2I_helper(tmp, src);
8178 regF_to_stkI(dst, tmp);
8179 %}
8180 %}
8181
8182 // Convert a double to a long in a double register.
8183 // If the double is a NAN, stuff a zero in instead.
8184 instruct convD2L_helper(regD dst, regD src, flagsRegF0 fcc0) %{
8185 effect(DEF dst, USE src, KILL fcc0);
8186 format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t"
8187 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8188 "FDTOX $src,$dst\t! convert in delay slot\n\t"
8189 "FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t"
8190 "FSUBd $dst,$dst,$dst\t! cleared only if nan\n"
8191 "skip:" %}
8192 ins_encode(form_d2l_helper(src,dst));
8193 ins_pipe(fcvtD2L);
8194 %}
8195
8196
8197 // Double to Long conversion
8198 instruct convD2L_reg(stackSlotL dst, regD src) %{
8199 match(Set dst (ConvD2L src));
8200 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8201 expand %{
8202 regD tmp;
8203 convD2L_helper(tmp, src);
8204 regD_to_stkL(dst, tmp);
8205 %}
8206 %}
8207
8208
8209 instruct convF2D_reg(regD dst, regF src) %{
8210 match(Set dst (ConvF2D src));
8211 format %{ "FSTOD $src,$dst" %}
8212 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fstod_opf);
8213 ins_encode(form3_opf_rs2F_rdD(src, dst));
8214 ins_pipe(fcvtF2D);
8215 %}
8216
8217
8218 instruct convF2I_helper(regF dst, regF src, flagsRegF0 fcc0) %{
8219 effect(DEF dst, USE src, KILL fcc0);
8220 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t"
8221 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8222 "FSTOI $src,$dst\t! convert in delay slot\n\t"
8223 "FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t"
8224 "FSUBs $dst,$dst,$dst\t! cleared only if nan\n"
8225 "skip:" %}
8226 ins_encode(form_f2i_helper(src,dst));
8227 ins_pipe(fcvtF2I);
8228 %}
8229
8230 instruct convF2I_reg(stackSlotI dst, regF src) %{
8231 match(Set dst (ConvF2I src));
8232 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8233 expand %{
8234 regF tmp;
8235 convF2I_helper(tmp, src);
8236 regF_to_stkI(dst, tmp);
8237 %}
8238 %}
8239
8240
8241 instruct convF2L_helper(regD dst, regF src, flagsRegF0 fcc0) %{
8242 effect(DEF dst, USE src, KILL fcc0);
8243 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t"
8244 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8245 "FSTOX $src,$dst\t! convert in delay slot\n\t"
8246 "FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t"
8247 "FSUBd $dst,$dst,$dst\t! cleared only if nan\n"
8248 "skip:" %}
8249 ins_encode(form_f2l_helper(src,dst));
8250 ins_pipe(fcvtF2L);
8251 %}
8252
8253 // Float to Long conversion
8254 instruct convF2L_reg(stackSlotL dst, regF src) %{
8255 match(Set dst (ConvF2L src));
8256 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8257 expand %{
8258 regD tmp;
8259 convF2L_helper(tmp, src);
8260 regD_to_stkL(dst, tmp);
8261 %}
8262 %}
8263
8264
8265 instruct convI2D_helper(regD dst, regF tmp) %{
8266 effect(USE tmp, DEF dst);
8267 format %{ "FITOD $tmp,$dst" %}
8268 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf);
8269 ins_encode(form3_opf_rs2F_rdD(tmp, dst));
8270 ins_pipe(fcvtI2D);
8271 %}
8272
8273 instruct convI2D_reg(stackSlotI src, regD dst) %{
8274 match(Set dst (ConvI2D src));
8275 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8276 expand %{
8277 regF tmp;
8278 stkI_to_regF( tmp, src);
8279 convI2D_helper( dst, tmp);
8280 %}
8281 %}
8282
8283 instruct convI2D_mem( regD_low dst, memory mem ) %{
8284 match(Set dst (ConvI2D (LoadI mem)));
8285 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8286 size(8);
8287 format %{ "LDF $mem,$dst\n\t"
8288 "FITOD $dst,$dst" %}
8289 opcode(Assembler::ldf_op3, Assembler::fitod_opf);
8290 ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst));
8291 ins_pipe(floadF_mem);
8292 %}
8293
8294
8295 instruct convI2F_helper(regF dst, regF tmp) %{
8296 effect(DEF dst, USE tmp);
8297 format %{ "FITOS $tmp,$dst" %}
8298 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitos_opf);
8299 ins_encode(form3_opf_rs2F_rdF(tmp, dst));
8300 ins_pipe(fcvtI2F);
8301 %}
8302
8303 instruct convI2F_reg( regF dst, stackSlotI src ) %{
8304 match(Set dst (ConvI2F src));
8305 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8306 expand %{
8307 regF tmp;
8308 stkI_to_regF(tmp,src);
8309 convI2F_helper(dst, tmp);
8310 %}
8311 %}
8312
8313 instruct convI2F_mem( regF dst, memory mem ) %{
8314 match(Set dst (ConvI2F (LoadI mem)));
8315 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8316 size(8);
8317 format %{ "LDF $mem,$dst\n\t"
8318 "FITOS $dst,$dst" %}
8319 opcode(Assembler::ldf_op3, Assembler::fitos_opf);
8320 ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst));
8321 ins_pipe(floadF_mem);
8322 %}
8323
8324
8325 instruct convI2L_reg(iRegL dst, iRegI src) %{
8326 match(Set dst (ConvI2L src));
8327 size(4);
8328 format %{ "SRA $src,0,$dst\t! int->long" %}
8329 opcode(Assembler::sra_op3, Assembler::arith_op);
8330 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
8331 ins_pipe(ialu_reg_reg);
8332 %}
8333
8334 // Zero-extend convert int to long
8335 instruct convI2L_reg_zex(iRegL dst, iRegI src, immL_32bits mask ) %{
8336 match(Set dst (AndL (ConvI2L src) mask) );
8337 size(4);
8338 format %{ "SRL $src,0,$dst\t! zero-extend int to long" %}
8339 opcode(Assembler::srl_op3, Assembler::arith_op);
8340 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
8341 ins_pipe(ialu_reg_reg);
8342 %}
8343
8344 // Zero-extend long
8345 instruct zerox_long(iRegL dst, iRegL src, immL_32bits mask ) %{
8346 match(Set dst (AndL src mask) );
8347 size(4);
8348 format %{ "SRL $src,0,$dst\t! zero-extend long" %}
8349 opcode(Assembler::srl_op3, Assembler::arith_op);
8350 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
8351 ins_pipe(ialu_reg_reg);
8352 %}
8353
8354 instruct MoveF2I_stack_reg(iRegI dst, stackSlotF src) %{
8355 match(Set dst (MoveF2I src));
8356 effect(DEF dst, USE src);
8357 ins_cost(MEMORY_REF_COST);
8358
8359 size(4);
8360 format %{ "LDUW $src,$dst\t! MoveF2I" %}
8361 opcode(Assembler::lduw_op3);
8362 ins_encode(simple_form3_mem_reg( src, dst ) );
8363 ins_pipe(iload_mem);
8364 %}
8365
8366 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{
8367 match(Set dst (MoveI2F src));
8368 effect(DEF dst, USE src);
8369 ins_cost(MEMORY_REF_COST);
8370
8371 size(4);
8372 format %{ "LDF $src,$dst\t! MoveI2F" %}
8373 opcode(Assembler::ldf_op3);
8374 ins_encode(simple_form3_mem_reg(src, dst));
8375 ins_pipe(floadF_stk);
8376 %}
8377
8378 instruct MoveD2L_stack_reg(iRegL dst, stackSlotD src) %{
8379 match(Set dst (MoveD2L src));
8380 effect(DEF dst, USE src);
8381 ins_cost(MEMORY_REF_COST);
8382
8383 size(4);
8384 format %{ "LDX $src,$dst\t! MoveD2L" %}
8385 opcode(Assembler::ldx_op3);
8386 ins_encode(simple_form3_mem_reg( src, dst ) );
8387 ins_pipe(iload_mem);
8388 %}
8389
8390 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{
8391 match(Set dst (MoveL2D src));
8392 effect(DEF dst, USE src);
8393 ins_cost(MEMORY_REF_COST);
8394
8395 size(4);
8396 format %{ "LDDF $src,$dst\t! MoveL2D" %}
8397 opcode(Assembler::lddf_op3);
8398 ins_encode(simple_form3_mem_reg(src, dst));
8399 ins_pipe(floadD_stk);
8400 %}
8401
8402 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{
8403 match(Set dst (MoveF2I src));
8404 effect(DEF dst, USE src);
8405 ins_cost(MEMORY_REF_COST);
8406
8407 size(4);
8408 format %{ "STF $src,$dst\t!MoveF2I" %}
8409 opcode(Assembler::stf_op3);
8410 ins_encode(simple_form3_mem_reg(dst, src));
8411 ins_pipe(fstoreF_stk_reg);
8412 %}
8413
8414 instruct MoveI2F_reg_stack(stackSlotF dst, iRegI src) %{
8415 match(Set dst (MoveI2F src));
8416 effect(DEF dst, USE src);
8417 ins_cost(MEMORY_REF_COST);
8418
8419 size(4);
8420 format %{ "STW $src,$dst\t!MoveI2F" %}
8421 opcode(Assembler::stw_op3);
8422 ins_encode(simple_form3_mem_reg( dst, src ) );
8423 ins_pipe(istore_mem_reg);
8424 %}
8425
8426 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{
8427 match(Set dst (MoveD2L src));
8428 effect(DEF dst, USE src);
8429 ins_cost(MEMORY_REF_COST);
8430
8431 size(4);
8432 format %{ "STDF $src,$dst\t!MoveD2L" %}
8433 opcode(Assembler::stdf_op3);
8434 ins_encode(simple_form3_mem_reg(dst, src));
8435 ins_pipe(fstoreD_stk_reg);
8436 %}
8437
8438 instruct MoveL2D_reg_stack(stackSlotD dst, iRegL src) %{
8439 match(Set dst (MoveL2D src));
8440 effect(DEF dst, USE src);
8441 ins_cost(MEMORY_REF_COST);
8442
8443 size(4);
8444 format %{ "STX $src,$dst\t!MoveL2D" %}
8445 opcode(Assembler::stx_op3);
8446 ins_encode(simple_form3_mem_reg( dst, src ) );
8447 ins_pipe(istore_mem_reg);
8448 %}
8449
8450
8451 //-----------
8452 // Long to Double conversion using V8 opcodes.
8453 // Still useful because cheetah traps and becomes
8454 // amazingly slow for some common numbers.
8455
8456 // Magic constant, 0x43300000
8457 instruct loadConI_x43300000(iRegI dst) %{
8458 effect(DEF dst);
8459 size(4);
8460 format %{ "SETHI HI(0x43300000),$dst\t! 2^52" %}
8461 ins_encode(SetHi22(0x43300000, dst));
8462 ins_pipe(ialu_none);
8463 %}
8464
8465 // Magic constant, 0x41f00000
8466 instruct loadConI_x41f00000(iRegI dst) %{
8467 effect(DEF dst);
8468 size(4);
8469 format %{ "SETHI HI(0x41f00000),$dst\t! 2^32" %}
8470 ins_encode(SetHi22(0x41f00000, dst));
8471 ins_pipe(ialu_none);
8472 %}
8473
8474 // Construct a double from two float halves
8475 instruct regDHi_regDLo_to_regD(regD_low dst, regD_low src1, regD_low src2) %{
8476 effect(DEF dst, USE src1, USE src2);
8477 size(8);
8478 format %{ "FMOVS $src1.hi,$dst.hi\n\t"
8479 "FMOVS $src2.lo,$dst.lo" %}
8480 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmovs_opf);
8481 ins_encode(form3_opf_rs2D_hi_rdD_hi(src1, dst), form3_opf_rs2D_lo_rdD_lo(src2, dst));
8482 ins_pipe(faddD_reg_reg);
8483 %}
8484
8485 // Convert integer in high half of a double register (in the lower half of
8486 // the double register file) to double
8487 instruct convI2D_regDHi_regD(regD dst, regD_low src) %{
8488 effect(DEF dst, USE src);
8489 size(4);
8490 format %{ "FITOD $src,$dst" %}
8491 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf);
8492 ins_encode(form3_opf_rs2D_rdD(src, dst));
8493 ins_pipe(fcvtLHi2D);
8494 %}
8495
8496 // Add float double precision
8497 instruct addD_regD_regD(regD dst, regD src1, regD src2) %{
8498 effect(DEF dst, USE src1, USE src2);
8499 size(4);
8500 format %{ "FADDD $src1,$src2,$dst" %}
8501 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf);
8502 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
8503 ins_pipe(faddD_reg_reg);
8504 %}
8505
8506 // Sub float double precision
8507 instruct subD_regD_regD(regD dst, regD src1, regD src2) %{
8508 effect(DEF dst, USE src1, USE src2);
8509 size(4);
8510 format %{ "FSUBD $src1,$src2,$dst" %}
8511 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf);
8512 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
8513 ins_pipe(faddD_reg_reg);
8514 %}
8515
8516 // Mul float double precision
8517 instruct mulD_regD_regD(regD dst, regD src1, regD src2) %{
8518 effect(DEF dst, USE src1, USE src2);
8519 size(4);
8520 format %{ "FMULD $src1,$src2,$dst" %}
8521 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf);
8522 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
8523 ins_pipe(fmulD_reg_reg);
8524 %}
8525
8526 instruct convL2D_reg_slow_fxtof(regD dst, stackSlotL src) %{
8527 match(Set dst (ConvL2D src));
8528 ins_cost(DEFAULT_COST*8 + MEMORY_REF_COST*6);
8529
8530 expand %{
8531 regD_low tmpsrc;
8532 iRegI ix43300000;
8533 iRegI ix41f00000;
8534 stackSlotL lx43300000;
8535 stackSlotL lx41f00000;
8536 regD_low dx43300000;
8537 regD dx41f00000;
8538 regD tmp1;
8539 regD_low tmp2;
8540 regD tmp3;
8541 regD tmp4;
8542
8543 stkL_to_regD(tmpsrc, src);
8544
8545 loadConI_x43300000(ix43300000);
8546 loadConI_x41f00000(ix41f00000);
8547 regI_to_stkLHi(lx43300000, ix43300000);
8548 regI_to_stkLHi(lx41f00000, ix41f00000);
8549 stkL_to_regD(dx43300000, lx43300000);
8550 stkL_to_regD(dx41f00000, lx41f00000);
8551
8552 convI2D_regDHi_regD(tmp1, tmpsrc);
8553 regDHi_regDLo_to_regD(tmp2, dx43300000, tmpsrc);
8554 subD_regD_regD(tmp3, tmp2, dx43300000);
8555 mulD_regD_regD(tmp4, tmp1, dx41f00000);
8556 addD_regD_regD(dst, tmp3, tmp4);
8557 %}
8558 %}
8559
8560 // Long to Double conversion using fast fxtof
8561 instruct convL2D_helper(regD dst, regD tmp) %{
8562 effect(DEF dst, USE tmp);
8563 size(4);
8564 format %{ "FXTOD $tmp,$dst" %}
8565 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtod_opf);
8566 ins_encode(form3_opf_rs2D_rdD(tmp, dst));
8567 ins_pipe(fcvtL2D);
8568 %}
8569
8570 instruct convL2D_reg_fast_fxtof(regD dst, stackSlotL src) %{
8571 predicate(VM_Version::has_fast_fxtof());
8572 match(Set dst (ConvL2D src));
8573 ins_cost(DEFAULT_COST + 3 * MEMORY_REF_COST);
8574 expand %{
8575 regD tmp;
8576 stkL_to_regD(tmp, src);
8577 convL2D_helper(dst, tmp);
8578 %}
8579 %}
8580
8581 //-----------
8582 // Long to Float conversion using V8 opcodes.
8583 // Still useful because cheetah traps and becomes
8584 // amazingly slow for some common numbers.
8585
8586 // Long to Float conversion using fast fxtof
8587 instruct convL2F_helper(regF dst, regD tmp) %{
8588 effect(DEF dst, USE tmp);
8589 size(4);
8590 format %{ "FXTOS $tmp,$dst" %}
8591 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtos_opf);
8592 ins_encode(form3_opf_rs2D_rdF(tmp, dst));
8593 ins_pipe(fcvtL2F);
8594 %}
8595
8596 instruct convL2F_reg_fast_fxtof(regF dst, stackSlotL src) %{
8597 match(Set dst (ConvL2F src));
8598 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8599 expand %{
8600 regD tmp;
8601 stkL_to_regD(tmp, src);
8602 convL2F_helper(dst, tmp);
8603 %}
8604 %}
8605 //-----------
8606
8607 instruct convL2I_reg(iRegI dst, iRegL src) %{
8608 match(Set dst (ConvL2I src));
8609 #ifndef _LP64
8610 format %{ "MOV $src.lo,$dst\t! long->int" %}
8611 ins_encode( form3_g0_rs2_rd_move_lo2( src, dst ) );
8612 ins_pipe(ialu_move_reg_I_to_L);
8613 #else
8614 size(4);
8615 format %{ "SRA $src,R_G0,$dst\t! long->int" %}
8616 ins_encode( form3_rs1_rd_signextend_lo1( src, dst ) );
8617 ins_pipe(ialu_reg);
8618 #endif
8619 %}
8620
8621 // Register Shift Right Immediate
8622 instruct shrL_reg_imm6_L2I(iRegI dst, iRegL src, immI_32_63 cnt) %{
8623 match(Set dst (ConvL2I (RShiftL src cnt)));
8624
8625 size(4);
8626 format %{ "SRAX $src,$cnt,$dst" %}
8627 opcode(Assembler::srax_op3, Assembler::arith_op);
8628 ins_encode( form3_sd_rs1_imm6_rd( src, cnt, dst ) );
8629 ins_pipe(ialu_reg_imm);
8630 %}
8631
8632 // Replicate scalar to packed byte values in Double register
8633 instruct Repl8B_reg_helper(iRegL dst, iRegI src) %{
8634 effect(DEF dst, USE src);
8635 format %{ "SLLX $src,56,$dst\n\t"
8636 "SRLX $dst, 8,O7\n\t"
8637 "OR $dst,O7,$dst\n\t"
8638 "SRLX $dst,16,O7\n\t"
8639 "OR $dst,O7,$dst\n\t"
8640 "SRLX $dst,32,O7\n\t"
8641 "OR $dst,O7,$dst\t! replicate8B" %}
8642 ins_encode( enc_repl8b(src, dst));
8643 ins_pipe(ialu_reg);
8644 %}
8645
8646 // Replicate scalar to packed byte values in Double register
8647 instruct Repl8B_reg(stackSlotD dst, iRegI src) %{
8648 match(Set dst (Replicate8B src));
8649 expand %{
8650 iRegL tmp;
8651 Repl8B_reg_helper(tmp, src);
8652 regL_to_stkD(dst, tmp);
8653 %}
8654 %}
8655
8656 // Replicate scalar constant to packed byte values in Double register
8657 instruct Repl8B_immI(regD dst, immI13 con, o7RegI tmp) %{
8658 match(Set dst (Replicate8B con));
8659 effect(KILL tmp);
8660 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl8B($con)" %}
8661 ins_encode %{
8662 // XXX This is a quick fix for 6833573.
8663 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 8, 1)), $dst$$FloatRegister);
8664 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 8, 1)), $tmp$$Register);
8665 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
8666 %}
8667 ins_pipe(loadConFD);
8668 %}
8669
8670 // Replicate scalar to packed char values into stack slot
8671 instruct Repl4C_reg_helper(iRegL dst, iRegI src) %{
8672 effect(DEF dst, USE src);
8673 format %{ "SLLX $src,48,$dst\n\t"
8674 "SRLX $dst,16,O7\n\t"
8675 "OR $dst,O7,$dst\n\t"
8676 "SRLX $dst,32,O7\n\t"
8677 "OR $dst,O7,$dst\t! replicate4C" %}
8678 ins_encode( enc_repl4s(src, dst) );
8679 ins_pipe(ialu_reg);
8680 %}
8681
8682 // Replicate scalar to packed char values into stack slot
8683 instruct Repl4C_reg(stackSlotD dst, iRegI src) %{
8684 match(Set dst (Replicate4C src));
8685 expand %{
8686 iRegL tmp;
8687 Repl4C_reg_helper(tmp, src);
8688 regL_to_stkD(dst, tmp);
8689 %}
8690 %}
8691
8692 // Replicate scalar constant to packed char values in Double register
8693 instruct Repl4C_immI(regD dst, immI con, o7RegI tmp) %{
8694 match(Set dst (Replicate4C con));
8695 effect(KILL tmp);
8696 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl4C($con)" %}
8697 ins_encode %{
8698 // XXX This is a quick fix for 6833573.
8699 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 4, 2)), $dst$$FloatRegister);
8700 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 4, 2)), $tmp$$Register);
8701 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
8702 %}
8703 ins_pipe(loadConFD);
8704 %}
8705
8706 // Replicate scalar to packed short values into stack slot
8707 instruct Repl4S_reg_helper(iRegL dst, iRegI src) %{
8708 effect(DEF dst, USE src);
8709 format %{ "SLLX $src,48,$dst\n\t"
8710 "SRLX $dst,16,O7\n\t"
8711 "OR $dst,O7,$dst\n\t"
8712 "SRLX $dst,32,O7\n\t"
8713 "OR $dst,O7,$dst\t! replicate4S" %}
8714 ins_encode( enc_repl4s(src, dst) );
8715 ins_pipe(ialu_reg);
8716 %}
8717
8718 // Replicate scalar to packed short values into stack slot
8719 instruct Repl4S_reg(stackSlotD dst, iRegI src) %{
8720 match(Set dst (Replicate4S src));
8721 expand %{
8722 iRegL tmp;
8723 Repl4S_reg_helper(tmp, src);
8724 regL_to_stkD(dst, tmp);
8725 %}
8726 %}
8727
8728 // Replicate scalar constant to packed short values in Double register
8729 instruct Repl4S_immI(regD dst, immI con, o7RegI tmp) %{
8730 match(Set dst (Replicate4S con));
8731 effect(KILL tmp);
8732 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl4S($con)" %}
8733 ins_encode %{
8734 // XXX This is a quick fix for 6833573.
8735 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 4, 2)), $dst$$FloatRegister);
8736 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 4, 2)), $tmp$$Register);
8737 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
8738 %}
8739 ins_pipe(loadConFD);
8740 %}
8741
8742 // Replicate scalar to packed int values in Double register
8743 instruct Repl2I_reg_helper(iRegL dst, iRegI src) %{
8744 effect(DEF dst, USE src);
8745 format %{ "SLLX $src,32,$dst\n\t"
8746 "SRLX $dst,32,O7\n\t"
8747 "OR $dst,O7,$dst\t! replicate2I" %}
8748 ins_encode( enc_repl2i(src, dst));
8749 ins_pipe(ialu_reg);
8750 %}
8751
8752 // Replicate scalar to packed int values in Double register
8753 instruct Repl2I_reg(stackSlotD dst, iRegI src) %{
8754 match(Set dst (Replicate2I src));
8755 expand %{
8756 iRegL tmp;
8757 Repl2I_reg_helper(tmp, src);
8758 regL_to_stkD(dst, tmp);
8759 %}
8760 %}
8761
8762 // Replicate scalar zero constant to packed int values in Double register
8763 instruct Repl2I_immI(regD dst, immI con, o7RegI tmp) %{
8764 match(Set dst (Replicate2I con));
8765 effect(KILL tmp);
8766 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl2I($con)" %}
8767 ins_encode %{
8768 // XXX This is a quick fix for 6833573.
8769 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 2, 4)), $dst$$FloatRegister);
8770 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 2, 4)), $tmp$$Register);
8771 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
8772 %}
8773 ins_pipe(loadConFD);
8774 %}
8775
8776 //----------Control Flow Instructions------------------------------------------
8777 // Compare Instructions
8778 // Compare Integers
8779 instruct compI_iReg(flagsReg icc, iRegI op1, iRegI op2) %{
8780 match(Set icc (CmpI op1 op2));
8781 effect( DEF icc, USE op1, USE op2 );
8782
8783 size(4);
8784 format %{ "CMP $op1,$op2" %}
8785 opcode(Assembler::subcc_op3, Assembler::arith_op);
8786 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8787 ins_pipe(ialu_cconly_reg_reg);
8788 %}
8789
8790 instruct compU_iReg(flagsRegU icc, iRegI op1, iRegI op2) %{
8791 match(Set icc (CmpU op1 op2));
8792
8793 size(4);
8794 format %{ "CMP $op1,$op2\t! unsigned" %}
8795 opcode(Assembler::subcc_op3, Assembler::arith_op);
8796 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8797 ins_pipe(ialu_cconly_reg_reg);
8798 %}
8799
8800 instruct compI_iReg_imm13(flagsReg icc, iRegI op1, immI13 op2) %{
8801 match(Set icc (CmpI op1 op2));
8802 effect( DEF icc, USE op1 );
8803
8804 size(4);
8805 format %{ "CMP $op1,$op2" %}
8806 opcode(Assembler::subcc_op3, Assembler::arith_op);
8807 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8808 ins_pipe(ialu_cconly_reg_imm);
8809 %}
8810
8811 instruct testI_reg_reg( flagsReg icc, iRegI op1, iRegI op2, immI0 zero ) %{
8812 match(Set icc (CmpI (AndI op1 op2) zero));
8813
8814 size(4);
8815 format %{ "BTST $op2,$op1" %}
8816 opcode(Assembler::andcc_op3, Assembler::arith_op);
8817 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8818 ins_pipe(ialu_cconly_reg_reg_zero);
8819 %}
8820
8821 instruct testI_reg_imm( flagsReg icc, iRegI op1, immI13 op2, immI0 zero ) %{
8822 match(Set icc (CmpI (AndI op1 op2) zero));
8823
8824 size(4);
8825 format %{ "BTST $op2,$op1" %}
8826 opcode(Assembler::andcc_op3, Assembler::arith_op);
8827 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8828 ins_pipe(ialu_cconly_reg_imm_zero);
8829 %}
8830
8831 instruct compL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2 ) %{
8832 match(Set xcc (CmpL op1 op2));
8833 effect( DEF xcc, USE op1, USE op2 );
8834
8835 size(4);
8836 format %{ "CMP $op1,$op2\t\t! long" %}
8837 opcode(Assembler::subcc_op3, Assembler::arith_op);
8838 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8839 ins_pipe(ialu_cconly_reg_reg);
8840 %}
8841
8842 instruct compL_reg_con(flagsRegL xcc, iRegL op1, immL13 con) %{
8843 match(Set xcc (CmpL op1 con));
8844 effect( DEF xcc, USE op1, USE con );
8845
8846 size(4);
8847 format %{ "CMP $op1,$con\t\t! long" %}
8848 opcode(Assembler::subcc_op3, Assembler::arith_op);
8849 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) );
8850 ins_pipe(ialu_cconly_reg_reg);
8851 %}
8852
8853 instruct testL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2, immL0 zero) %{
8854 match(Set xcc (CmpL (AndL op1 op2) zero));
8855 effect( DEF xcc, USE op1, USE op2 );
8856
8857 size(4);
8858 format %{ "BTST $op1,$op2\t\t! long" %}
8859 opcode(Assembler::andcc_op3, Assembler::arith_op);
8860 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8861 ins_pipe(ialu_cconly_reg_reg);
8862 %}
8863
8864 // useful for checking the alignment of a pointer:
8865 instruct testL_reg_con(flagsRegL xcc, iRegL op1, immL13 con, immL0 zero) %{
8866 match(Set xcc (CmpL (AndL op1 con) zero));
8867 effect( DEF xcc, USE op1, USE con );
8868
8869 size(4);
8870 format %{ "BTST $op1,$con\t\t! long" %}
8871 opcode(Assembler::andcc_op3, Assembler::arith_op);
8872 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) );
8873 ins_pipe(ialu_cconly_reg_reg);
8874 %}
8875
8876 instruct compU_iReg_imm13(flagsRegU icc, iRegI op1, immU13 op2 ) %{
8877 match(Set icc (CmpU op1 op2));
8878
8879 size(4);
8880 format %{ "CMP $op1,$op2\t! unsigned" %}
8881 opcode(Assembler::subcc_op3, Assembler::arith_op);
8882 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8883 ins_pipe(ialu_cconly_reg_imm);
8884 %}
8885
8886 // Compare Pointers
8887 instruct compP_iRegP(flagsRegP pcc, iRegP op1, iRegP op2 ) %{
8888 match(Set pcc (CmpP op1 op2));
8889
8890 size(4);
8891 format %{ "CMP $op1,$op2\t! ptr" %}
8892 opcode(Assembler::subcc_op3, Assembler::arith_op);
8893 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8894 ins_pipe(ialu_cconly_reg_reg);
8895 %}
8896
8897 instruct compP_iRegP_imm13(flagsRegP pcc, iRegP op1, immP13 op2 ) %{
8898 match(Set pcc (CmpP op1 op2));
8899
8900 size(4);
8901 format %{ "CMP $op1,$op2\t! ptr" %}
8902 opcode(Assembler::subcc_op3, Assembler::arith_op);
8903 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8904 ins_pipe(ialu_cconly_reg_imm);
8905 %}
8906
8907 // Compare Narrow oops
8908 instruct compN_iRegN(flagsReg icc, iRegN op1, iRegN op2 ) %{
8909 match(Set icc (CmpN op1 op2));
8910
8911 size(4);
8912 format %{ "CMP $op1,$op2\t! compressed ptr" %}
8913 opcode(Assembler::subcc_op3, Assembler::arith_op);
8914 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8915 ins_pipe(ialu_cconly_reg_reg);
8916 %}
8917
8918 instruct compN_iRegN_immN0(flagsReg icc, iRegN op1, immN0 op2 ) %{
8919 match(Set icc (CmpN op1 op2));
8920
8921 size(4);
8922 format %{ "CMP $op1,$op2\t! compressed ptr" %}
8923 opcode(Assembler::subcc_op3, Assembler::arith_op);
8924 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8925 ins_pipe(ialu_cconly_reg_imm);
8926 %}
8927
8928 //----------Max and Min--------------------------------------------------------
8929 // Min Instructions
8930 // Conditional move for min
8931 instruct cmovI_reg_lt( iRegI op2, iRegI op1, flagsReg icc ) %{
8932 effect( USE_DEF op2, USE op1, USE icc );
8933
8934 size(4);
8935 format %{ "MOVlt icc,$op1,$op2\t! min" %}
8936 opcode(Assembler::less);
8937 ins_encode( enc_cmov_reg_minmax(op2,op1) );
8938 ins_pipe(ialu_reg_flags);
8939 %}
8940
8941 // Min Register with Register.
8942 instruct minI_eReg(iRegI op1, iRegI op2) %{
8943 match(Set op2 (MinI op1 op2));
8944 ins_cost(DEFAULT_COST*2);
8945 expand %{
8946 flagsReg icc;
8947 compI_iReg(icc,op1,op2);
8948 cmovI_reg_lt(op2,op1,icc);
8949 %}
8950 %}
8951
8952 // Max Instructions
8953 // Conditional move for max
8954 instruct cmovI_reg_gt( iRegI op2, iRegI op1, flagsReg icc ) %{
8955 effect( USE_DEF op2, USE op1, USE icc );
8956 format %{ "MOVgt icc,$op1,$op2\t! max" %}
8957 opcode(Assembler::greater);
8958 ins_encode( enc_cmov_reg_minmax(op2,op1) );
8959 ins_pipe(ialu_reg_flags);
8960 %}
8961
8962 // Max Register with Register
8963 instruct maxI_eReg(iRegI op1, iRegI op2) %{
8964 match(Set op2 (MaxI op1 op2));
8965 ins_cost(DEFAULT_COST*2);
8966 expand %{
8967 flagsReg icc;
8968 compI_iReg(icc,op1,op2);
8969 cmovI_reg_gt(op2,op1,icc);
8970 %}
8971 %}
8972
8973
8974 //----------Float Compares----------------------------------------------------
8975 // Compare floating, generate condition code
8976 instruct cmpF_cc(flagsRegF fcc, regF src1, regF src2) %{
8977 match(Set fcc (CmpF src1 src2));
8978
8979 size(4);
8980 format %{ "FCMPs $fcc,$src1,$src2" %}
8981 opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmps_opf);
8982 ins_encode( form3_opf_rs1F_rs2F_fcc( src1, src2, fcc ) );
8983 ins_pipe(faddF_fcc_reg_reg_zero);
8984 %}
8985
8986 instruct cmpD_cc(flagsRegF fcc, regD src1, regD src2) %{
8987 match(Set fcc (CmpD src1 src2));
8988
8989 size(4);
8990 format %{ "FCMPd $fcc,$src1,$src2" %}
8991 opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmpd_opf);
8992 ins_encode( form3_opf_rs1D_rs2D_fcc( src1, src2, fcc ) );
8993 ins_pipe(faddD_fcc_reg_reg_zero);
8994 %}
8995
8996
8997 // Compare floating, generate -1,0,1
8998 instruct cmpF_reg(iRegI dst, regF src1, regF src2, flagsRegF0 fcc0) %{
8999 match(Set dst (CmpF3 src1 src2));
9000 effect(KILL fcc0);
9001 ins_cost(DEFAULT_COST*3+BRANCH_COST*3);
9002 format %{ "fcmpl $dst,$src1,$src2" %}
9003 // Primary = float
9004 opcode( true );
9005 ins_encode( floating_cmp( dst, src1, src2 ) );
9006 ins_pipe( floating_cmp );
9007 %}
9008
9009 instruct cmpD_reg(iRegI dst, regD src1, regD src2, flagsRegF0 fcc0) %{
9010 match(Set dst (CmpD3 src1 src2));
9011 effect(KILL fcc0);
9012 ins_cost(DEFAULT_COST*3+BRANCH_COST*3);
9013 format %{ "dcmpl $dst,$src1,$src2" %}
9014 // Primary = double (not float)
9015 opcode( false );
9016 ins_encode( floating_cmp( dst, src1, src2 ) );
9017 ins_pipe( floating_cmp );
9018 %}
9019
9020 //----------Branches---------------------------------------------------------
9021 // Jump
9022 // (compare 'operand indIndex' and 'instruct addP_reg_reg' above)
9023 instruct jumpXtnd(iRegX switch_val, o7RegI table) %{
9024 match(Jump switch_val);
9025
9026 ins_cost(350);
9027
9028 format %{ "ADD $constanttablebase, $constantoffset, O7\n\t"
9029 "LD [O7 + $switch_val], O7\n\t"
9030 "JUMP O7"
9031 %}
9032 ins_encode %{
9033 // Calculate table address into a register.
9034 Register table_reg;
9035 Register label_reg = O7;
9036 if (constant_offset() == 0) {
9037 table_reg = $constanttablebase;
9038 } else {
9039 table_reg = O7;
9040 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset, O7);
9041 __ add($constanttablebase, con_offset, table_reg);
9042 }
9043
9044 // Jump to base address + switch value
9045 __ ld_ptr(table_reg, $switch_val$$Register, label_reg);
9046 __ jmp(label_reg, G0);
9047 __ delayed()->nop();
9048 %}
9049 ins_pc_relative(1);
9050 ins_pipe(ialu_reg_reg);
9051 %}
9052
9053 // Direct Branch. Use V8 version with longer range.
9054 instruct branch(label labl) %{
9055 match(Goto);
9056 effect(USE labl);
9057
9058 size(8);
9059 ins_cost(BRANCH_COST);
9060 format %{ "BA $labl" %}
9061 // Prim = bits 24-22, Secnd = bits 31-30, Tert = cond
9062 opcode(Assembler::br_op2, Assembler::branch_op, Assembler::always);
9063 ins_encode( enc_ba( labl ) );
9064 ins_pc_relative(1);
9065 ins_pipe(br);
9066 %}
9067
9068 // Conditional Direct Branch
9069 instruct branchCon(cmpOp cmp, flagsReg icc, label labl) %{
9070 match(If cmp icc);
9071 effect(USE labl);
9072
9073 size(8);
9074 ins_cost(BRANCH_COST);
9075 format %{ "BP$cmp $icc,$labl" %}
9076 // Prim = bits 24-22, Secnd = bits 31-30
9077 ins_encode( enc_bp( labl, cmp, icc ) );
9078 ins_pc_relative(1);
9079 ins_pipe(br_cc);
9080 %}
9081
9082 // Branch-on-register tests all 64 bits. We assume that values
9083 // in 64-bit registers always remains zero or sign extended
9084 // unless our code munges the high bits. Interrupts can chop
9085 // the high order bits to zero or sign at any time.
9086 instruct branchCon_regI(cmpOp_reg cmp, iRegI op1, immI0 zero, label labl) %{
9087 match(If cmp (CmpI op1 zero));
9088 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
9089 effect(USE labl);
9090
9091 size(8);
9092 ins_cost(BRANCH_COST);
9093 format %{ "BR$cmp $op1,$labl" %}
9094 ins_encode( enc_bpr( labl, cmp, op1 ) );
9095 ins_pc_relative(1);
9096 ins_pipe(br_reg);
9097 %}
9098
9099 instruct branchCon_regP(cmpOp_reg cmp, iRegP op1, immP0 null, label labl) %{
9100 match(If cmp (CmpP op1 null));
9101 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
9102 effect(USE labl);
9103
9104 size(8);
9105 ins_cost(BRANCH_COST);
9106 format %{ "BR$cmp $op1,$labl" %}
9107 ins_encode( enc_bpr( labl, cmp, op1 ) );
9108 ins_pc_relative(1);
9109 ins_pipe(br_reg);
9110 %}
9111
9112 instruct branchCon_regL(cmpOp_reg cmp, iRegL op1, immL0 zero, label labl) %{
9113 match(If cmp (CmpL op1 zero));
9114 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
9115 effect(USE labl);
9116
9117 size(8);
9118 ins_cost(BRANCH_COST);
9119 format %{ "BR$cmp $op1,$labl" %}
9120 ins_encode( enc_bpr( labl, cmp, op1 ) );
9121 ins_pc_relative(1);
9122 ins_pipe(br_reg);
9123 %}
9124
9125 instruct branchConU(cmpOpU cmp, flagsRegU icc, label labl) %{
9126 match(If cmp icc);
9127 effect(USE labl);
9128
9129 format %{ "BP$cmp $icc,$labl" %}
9130 // Prim = bits 24-22, Secnd = bits 31-30
9131 ins_encode( enc_bp( labl, cmp, icc ) );
9132 ins_pc_relative(1);
9133 ins_pipe(br_cc);
9134 %}
9135
9136 instruct branchConP(cmpOpP cmp, flagsRegP pcc, label labl) %{
9137 match(If cmp pcc);
9138 effect(USE labl);
9139
9140 size(8);
9141 ins_cost(BRANCH_COST);
9142 format %{ "BP$cmp $pcc,$labl" %}
9143 // Prim = bits 24-22, Secnd = bits 31-30
9144 ins_encode( enc_bpx( labl, cmp, pcc ) );
9145 ins_pc_relative(1);
9146 ins_pipe(br_cc);
9147 %}
9148
9149 instruct branchConF(cmpOpF cmp, flagsRegF fcc, label labl) %{
9150 match(If cmp fcc);
9151 effect(USE labl);
9152
9153 size(8);
9154 ins_cost(BRANCH_COST);
9155 format %{ "FBP$cmp $fcc,$labl" %}
9156 // Prim = bits 24-22, Secnd = bits 31-30
9157 ins_encode( enc_fbp( labl, cmp, fcc ) );
9158 ins_pc_relative(1);
9159 ins_pipe(br_fcc);
9160 %}
9161
9162 instruct branchLoopEnd(cmpOp cmp, flagsReg icc, label labl) %{
9163 match(CountedLoopEnd cmp icc);
9164 effect(USE labl);
9165
9166 size(8);
9167 ins_cost(BRANCH_COST);
9168 format %{ "BP$cmp $icc,$labl\t! Loop end" %}
9169 // Prim = bits 24-22, Secnd = bits 31-30
9170 ins_encode( enc_bp( labl, cmp, icc ) );
9171 ins_pc_relative(1);
9172 ins_pipe(br_cc);
9173 %}
9174
9175 instruct branchLoopEndU(cmpOpU cmp, flagsRegU icc, label labl) %{
9176 match(CountedLoopEnd cmp icc);
9177 effect(USE labl);
9178
9179 size(8);
9180 ins_cost(BRANCH_COST);
9181 format %{ "BP$cmp $icc,$labl\t! Loop end" %}
9182 // Prim = bits 24-22, Secnd = bits 31-30
9183 ins_encode( enc_bp( labl, cmp, icc ) );
9184 ins_pc_relative(1);
9185 ins_pipe(br_cc);
9186 %}
9187
9188 // ============================================================================
9189 // Long Compare
9190 //
9191 // Currently we hold longs in 2 registers. Comparing such values efficiently
9192 // is tricky. The flavor of compare used depends on whether we are testing
9193 // for LT, LE, or EQ. For a simple LT test we can check just the sign bit.
9194 // The GE test is the negated LT test. The LE test can be had by commuting
9195 // the operands (yielding a GE test) and then negating; negate again for the
9196 // GT test. The EQ test is done by ORcc'ing the high and low halves, and the
9197 // NE test is negated from that.
9198
9199 // Due to a shortcoming in the ADLC, it mixes up expressions like:
9200 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the
9201 // difference between 'Y' and '0L'. The tree-matches for the CmpI sections
9202 // are collapsed internally in the ADLC's dfa-gen code. The match for
9203 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the
9204 // foo match ends up with the wrong leaf. One fix is to not match both
9205 // reg-reg and reg-zero forms of long-compare. This is unfortunate because
9206 // both forms beat the trinary form of long-compare and both are very useful
9207 // on Intel which has so few registers.
9208
9209 instruct branchCon_long(cmpOp cmp, flagsRegL xcc, label labl) %{
9210 match(If cmp xcc);
9211 effect(USE labl);
9212
9213 size(8);
9214 ins_cost(BRANCH_COST);
9215 format %{ "BP$cmp $xcc,$labl" %}
9216 // Prim = bits 24-22, Secnd = bits 31-30
9217 ins_encode( enc_bpl( labl, cmp, xcc ) );
9218 ins_pc_relative(1);
9219 ins_pipe(br_cc);
9220 %}
9221
9222 // Manifest a CmpL3 result in an integer register. Very painful.
9223 // This is the test to avoid.
9224 instruct cmpL3_reg_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg ccr ) %{
9225 match(Set dst (CmpL3 src1 src2) );
9226 effect( KILL ccr );
9227 ins_cost(6*DEFAULT_COST);
9228 size(24);
9229 format %{ "CMP $src1,$src2\t\t! long\n"
9230 "\tBLT,a,pn done\n"
9231 "\tMOV -1,$dst\t! delay slot\n"
9232 "\tBGT,a,pn done\n"
9233 "\tMOV 1,$dst\t! delay slot\n"
9234 "\tCLR $dst\n"
9235 "done:" %}
9236 ins_encode( cmpl_flag(src1,src2,dst) );
9237 ins_pipe(cmpL_reg);
9238 %}
9239
9240 // Conditional move
9241 instruct cmovLL_reg(cmpOp cmp, flagsRegL xcc, iRegL dst, iRegL src) %{
9242 match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src)));
9243 ins_cost(150);
9244 format %{ "MOV$cmp $xcc,$src,$dst\t! long" %}
9245 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9246 ins_pipe(ialu_reg);
9247 %}
9248
9249 instruct cmovLL_imm(cmpOp cmp, flagsRegL xcc, iRegL dst, immL0 src) %{
9250 match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src)));
9251 ins_cost(140);
9252 format %{ "MOV$cmp $xcc,$src,$dst\t! long" %}
9253 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
9254 ins_pipe(ialu_imm);
9255 %}
9256
9257 instruct cmovIL_reg(cmpOp cmp, flagsRegL xcc, iRegI dst, iRegI src) %{
9258 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src)));
9259 ins_cost(150);
9260 format %{ "MOV$cmp $xcc,$src,$dst" %}
9261 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9262 ins_pipe(ialu_reg);
9263 %}
9264
9265 instruct cmovIL_imm(cmpOp cmp, flagsRegL xcc, iRegI dst, immI11 src) %{
9266 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src)));
9267 ins_cost(140);
9268 format %{ "MOV$cmp $xcc,$src,$dst" %}
9269 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
9270 ins_pipe(ialu_imm);
9271 %}
9272
9273 instruct cmovNL_reg(cmpOp cmp, flagsRegL xcc, iRegN dst, iRegN src) %{
9274 match(Set dst (CMoveN (Binary cmp xcc) (Binary dst src)));
9275 ins_cost(150);
9276 format %{ "MOV$cmp $xcc,$src,$dst" %}
9277 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9278 ins_pipe(ialu_reg);
9279 %}
9280
9281 instruct cmovPL_reg(cmpOp cmp, flagsRegL xcc, iRegP dst, iRegP src) %{
9282 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src)));
9283 ins_cost(150);
9284 format %{ "MOV$cmp $xcc,$src,$dst" %}
9285 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9286 ins_pipe(ialu_reg);
9287 %}
9288
9289 instruct cmovPL_imm(cmpOp cmp, flagsRegL xcc, iRegP dst, immP0 src) %{
9290 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src)));
9291 ins_cost(140);
9292 format %{ "MOV$cmp $xcc,$src,$dst" %}
9293 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
9294 ins_pipe(ialu_imm);
9295 %}
9296
9297 instruct cmovFL_reg(cmpOp cmp, flagsRegL xcc, regF dst, regF src) %{
9298 match(Set dst (CMoveF (Binary cmp xcc) (Binary dst src)));
9299 ins_cost(150);
9300 opcode(0x101);
9301 format %{ "FMOVS$cmp $xcc,$src,$dst" %}
9302 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) );
9303 ins_pipe(int_conditional_float_move);
9304 %}
9305
9306 instruct cmovDL_reg(cmpOp cmp, flagsRegL xcc, regD dst, regD src) %{
9307 match(Set dst (CMoveD (Binary cmp xcc) (Binary dst src)));
9308 ins_cost(150);
9309 opcode(0x102);
9310 format %{ "FMOVD$cmp $xcc,$src,$dst" %}
9311 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) );
9312 ins_pipe(int_conditional_float_move);
9313 %}
9314
9315 // ============================================================================
9316 // Safepoint Instruction
9317 instruct safePoint_poll(iRegP poll) %{
9318 match(SafePoint poll);
9319 effect(USE poll);
9320
9321 size(4);
9322 #ifdef _LP64
9323 format %{ "LDX [$poll],R_G0\t! Safepoint: poll for GC" %}
9324 #else
9325 format %{ "LDUW [$poll],R_G0\t! Safepoint: poll for GC" %}
9326 #endif
9327 ins_encode %{
9328 __ relocate(relocInfo::poll_type);
9329 __ ld_ptr($poll$$Register, 0, G0);
9330 %}
9331 ins_pipe(loadPollP);
9332 %}
9333
9334 // ============================================================================
9335 // Call Instructions
9336 // Call Java Static Instruction
9337 instruct CallStaticJavaDirect( method meth ) %{
9338 match(CallStaticJava);
9339 predicate(! ((CallStaticJavaNode*)n)->is_method_handle_invoke());
9340 effect(USE meth);
9341
9342 size(8);
9343 ins_cost(CALL_COST);
9344 format %{ "CALL,static ; NOP ==> " %}
9345 ins_encode( Java_Static_Call( meth ), call_epilog );
9346 ins_pc_relative(1);
9347 ins_pipe(simple_call);
9348 %}
9349
9350 // Call Java Static Instruction (method handle version)
9351 instruct CallStaticJavaHandle(method meth, l7RegP l7_mh_SP_save) %{
9352 match(CallStaticJava);
9353 predicate(((CallStaticJavaNode*)n)->is_method_handle_invoke());
9354 effect(USE meth, KILL l7_mh_SP_save);
9355
9356 size(8);
9357 ins_cost(CALL_COST);
9358 format %{ "CALL,static/MethodHandle" %}
9359 ins_encode(preserve_SP, Java_Static_Call(meth), restore_SP, call_epilog);
9360 ins_pc_relative(1);
9361 ins_pipe(simple_call);
9362 %}
9363
9364 // Call Java Dynamic Instruction
9365 instruct CallDynamicJavaDirect( method meth ) %{
9366 match(CallDynamicJava);
9367 effect(USE meth);
9368
9369 ins_cost(CALL_COST);
9370 format %{ "SET (empty),R_G5\n\t"
9371 "CALL,dynamic ; NOP ==> " %}
9372 ins_encode( Java_Dynamic_Call( meth ), call_epilog );
9373 ins_pc_relative(1);
9374 ins_pipe(call);
9375 %}
9376
9377 // Call Runtime Instruction
9378 instruct CallRuntimeDirect(method meth, l7RegP l7) %{
9379 match(CallRuntime);
9380 effect(USE meth, KILL l7);
9381 ins_cost(CALL_COST);
9382 format %{ "CALL,runtime" %}
9383 ins_encode( Java_To_Runtime( meth ),
9384 call_epilog, adjust_long_from_native_call );
9385 ins_pc_relative(1);
9386 ins_pipe(simple_call);
9387 %}
9388
9389 // Call runtime without safepoint - same as CallRuntime
9390 instruct CallLeafDirect(method meth, l7RegP l7) %{
9391 match(CallLeaf);
9392 effect(USE meth, KILL l7);
9393 ins_cost(CALL_COST);
9394 format %{ "CALL,runtime leaf" %}
9395 ins_encode( Java_To_Runtime( meth ),
9396 call_epilog,
9397 adjust_long_from_native_call );
9398 ins_pc_relative(1);
9399 ins_pipe(simple_call);
9400 %}
9401
9402 // Call runtime without safepoint - same as CallLeaf
9403 instruct CallLeafNoFPDirect(method meth, l7RegP l7) %{
9404 match(CallLeafNoFP);
9405 effect(USE meth, KILL l7);
9406 ins_cost(CALL_COST);
9407 format %{ "CALL,runtime leaf nofp" %}
9408 ins_encode( Java_To_Runtime( meth ),
9409 call_epilog,
9410 adjust_long_from_native_call );
9411 ins_pc_relative(1);
9412 ins_pipe(simple_call);
9413 %}
9414
9415 // Tail Call; Jump from runtime stub to Java code.
9416 // Also known as an 'interprocedural jump'.
9417 // Target of jump will eventually return to caller.
9418 // TailJump below removes the return address.
9419 instruct TailCalljmpInd(g3RegP jump_target, inline_cache_regP method_oop) %{
9420 match(TailCall jump_target method_oop );
9421
9422 ins_cost(CALL_COST);
9423 format %{ "Jmp $jump_target ; NOP \t! $method_oop holds method oop" %}
9424 ins_encode(form_jmpl(jump_target));
9425 ins_pipe(tail_call);
9426 %}
9427
9428
9429 // Return Instruction
9430 instruct Ret() %{
9431 match(Return);
9432
9433 // The epilogue node did the ret already.
9434 size(0);
9435 format %{ "! return" %}
9436 ins_encode();
9437 ins_pipe(empty);
9438 %}
9439
9440
9441 // Tail Jump; remove the return address; jump to target.
9442 // TailCall above leaves the return address around.
9443 // TailJump is used in only one place, the rethrow_Java stub (fancy_jump=2).
9444 // ex_oop (Exception Oop) is needed in %o0 at the jump. As there would be a
9445 // "restore" before this instruction (in Epilogue), we need to materialize it
9446 // in %i0.
9447 instruct tailjmpInd(g1RegP jump_target, i0RegP ex_oop) %{
9448 match( TailJump jump_target ex_oop );
9449 ins_cost(CALL_COST);
9450 format %{ "! discard R_O7\n\t"
9451 "Jmp $jump_target ; ADD O7,8,O1 \t! $ex_oop holds exc. oop" %}
9452 ins_encode(form_jmpl_set_exception_pc(jump_target));
9453 // opcode(Assembler::jmpl_op3, Assembler::arith_op);
9454 // The hack duplicates the exception oop into G3, so that CreateEx can use it there.
9455 // ins_encode( form3_rs1_simm13_rd( jump_target, 0x00, R_G0 ), move_return_pc_to_o1() );
9456 ins_pipe(tail_call);
9457 %}
9458
9459 // Create exception oop: created by stack-crawling runtime code.
9460 // Created exception is now available to this handler, and is setup
9461 // just prior to jumping to this handler. No code emitted.
9462 instruct CreateException( o0RegP ex_oop )
9463 %{
9464 match(Set ex_oop (CreateEx));
9465 ins_cost(0);
9466
9467 size(0);
9468 // use the following format syntax
9469 format %{ "! exception oop is in R_O0; no code emitted" %}
9470 ins_encode();
9471 ins_pipe(empty);
9472 %}
9473
9474
9475 // Rethrow exception:
9476 // The exception oop will come in the first argument position.
9477 // Then JUMP (not call) to the rethrow stub code.
9478 instruct RethrowException()
9479 %{
9480 match(Rethrow);
9481 ins_cost(CALL_COST);
9482
9483 // use the following format syntax
9484 format %{ "Jmp rethrow_stub" %}
9485 ins_encode(enc_rethrow);
9486 ins_pipe(tail_call);
9487 %}
9488
9489
9490 // Die now
9491 instruct ShouldNotReachHere( )
9492 %{
9493 match(Halt);
9494 ins_cost(CALL_COST);
9495
9496 size(4);
9497 // Use the following format syntax
9498 format %{ "ILLTRAP ; ShouldNotReachHere" %}
9499 ins_encode( form2_illtrap() );
9500 ins_pipe(tail_call);
9501 %}
9502
9503 // ============================================================================
9504 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass
9505 // array for an instance of the superklass. Set a hidden internal cache on a
9506 // hit (cache is checked with exposed code in gen_subtype_check()). Return
9507 // not zero for a miss or zero for a hit. The encoding ALSO sets flags.
9508 instruct partialSubtypeCheck( o0RegP index, o1RegP sub, o2RegP super, flagsRegP pcc, o7RegP o7 ) %{
9509 match(Set index (PartialSubtypeCheck sub super));
9510 effect( KILL pcc, KILL o7 );
9511 ins_cost(DEFAULT_COST*10);
9512 format %{ "CALL PartialSubtypeCheck\n\tNOP" %}
9513 ins_encode( enc_PartialSubtypeCheck() );
9514 ins_pipe(partial_subtype_check_pipe);
9515 %}
9516
9517 instruct partialSubtypeCheck_vs_zero( flagsRegP pcc, o1RegP sub, o2RegP super, immP0 zero, o0RegP idx, o7RegP o7 ) %{
9518 match(Set pcc (CmpP (PartialSubtypeCheck sub super) zero));
9519 effect( KILL idx, KILL o7 );
9520 ins_cost(DEFAULT_COST*10);
9521 format %{ "CALL PartialSubtypeCheck\n\tNOP\t# (sets condition codes)" %}
9522 ins_encode( enc_PartialSubtypeCheck() );
9523 ins_pipe(partial_subtype_check_pipe);
9524 %}
9525
9526
9527 // ============================================================================
9528 // inlined locking and unlocking
9529
9530 instruct cmpFastLock(flagsRegP pcc, iRegP object, iRegP box, iRegP scratch2, o7RegP scratch ) %{
9531 match(Set pcc (FastLock object box));
9532
9533 effect(KILL scratch, TEMP scratch2);
9534 ins_cost(100);
9535
9536 size(4*112); // conservative overestimation ...
9537 format %{ "FASTLOCK $object, $box; KILL $scratch, $scratch2, $box" %}
9538 ins_encode( Fast_Lock(object, box, scratch, scratch2) );
9539 ins_pipe(long_memory_op);
9540 %}
9541
9542
9543 instruct cmpFastUnlock(flagsRegP pcc, iRegP object, iRegP box, iRegP scratch2, o7RegP scratch ) %{
9544 match(Set pcc (FastUnlock object box));
9545 effect(KILL scratch, TEMP scratch2);
9546 ins_cost(100);
9547
9548 size(4*120); // conservative overestimation ...
9549 format %{ "FASTUNLOCK $object, $box; KILL $scratch, $scratch2, $box" %}
9550 ins_encode( Fast_Unlock(object, box, scratch, scratch2) );
9551 ins_pipe(long_memory_op);
9552 %}
9553
9554 // Count and Base registers are fixed because the allocator cannot
9555 // kill unknown registers. The encodings are generic.
9556 instruct clear_array(iRegX cnt, iRegP base, iRegX temp, Universe dummy, flagsReg ccr) %{
9557 match(Set dummy (ClearArray cnt base));
9558 effect(TEMP temp, KILL ccr);
9559 ins_cost(300);
9560 format %{ "MOV $cnt,$temp\n"
9561 "loop: SUBcc $temp,8,$temp\t! Count down a dword of bytes\n"
9562 " BRge loop\t\t! Clearing loop\n"
9563 " STX G0,[$base+$temp]\t! delay slot" %}
9564 ins_encode( enc_Clear_Array(cnt, base, temp) );
9565 ins_pipe(long_memory_op);
9566 %}
9567
9568 instruct string_compare(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result,
9569 o7RegI tmp, flagsReg ccr) %{
9570 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
9571 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL ccr, KILL tmp);
9572 ins_cost(300);
9573 format %{ "String Compare $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp" %}
9574 ins_encode( enc_String_Compare(str1, str2, cnt1, cnt2, result) );
9575 ins_pipe(long_memory_op);
9576 %}
9577
9578 instruct string_equals(o0RegP str1, o1RegP str2, g3RegI cnt, notemp_iRegI result,
9579 o7RegI tmp, flagsReg ccr) %{
9580 match(Set result (StrEquals (Binary str1 str2) cnt));
9581 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp, KILL ccr);
9582 ins_cost(300);
9583 format %{ "String Equals $str1,$str2,$cnt -> $result // KILL $tmp" %}
9584 ins_encode( enc_String_Equals(str1, str2, cnt, result) );
9585 ins_pipe(long_memory_op);
9586 %}
9587
9588 instruct array_equals(o0RegP ary1, o1RegP ary2, g3RegI tmp1, notemp_iRegI result,
9589 o7RegI tmp2, flagsReg ccr) %{
9590 match(Set result (AryEq ary1 ary2));
9591 effect(USE_KILL ary1, USE_KILL ary2, KILL tmp1, KILL tmp2, KILL ccr);
9592 ins_cost(300);
9593 format %{ "Array Equals $ary1,$ary2 -> $result // KILL $tmp1,$tmp2" %}
9594 ins_encode( enc_Array_Equals(ary1, ary2, tmp1, result));
9595 ins_pipe(long_memory_op);
9596 %}
9597
9598
9599 //---------- Zeros Count Instructions ------------------------------------------
9600
9601 instruct countLeadingZerosI(iRegI dst, iRegI src, iRegI tmp, flagsReg cr) %{
9602 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
9603 match(Set dst (CountLeadingZerosI src));
9604 effect(TEMP dst, TEMP tmp, KILL cr);
9605
9606 // x |= (x >> 1);
9607 // x |= (x >> 2);
9608 // x |= (x >> 4);
9609 // x |= (x >> 8);
9610 // x |= (x >> 16);
9611 // return (WORDBITS - popc(x));
9612 format %{ "SRL $src,1,$tmp\t! count leading zeros (int)\n\t"
9613 "SRL $src,0,$dst\t! 32-bit zero extend\n\t"
9614 "OR $dst,$tmp,$dst\n\t"
9615 "SRL $dst,2,$tmp\n\t"
9616 "OR $dst,$tmp,$dst\n\t"
9617 "SRL $dst,4,$tmp\n\t"
9618 "OR $dst,$tmp,$dst\n\t"
9619 "SRL $dst,8,$tmp\n\t"
9620 "OR $dst,$tmp,$dst\n\t"
9621 "SRL $dst,16,$tmp\n\t"
9622 "OR $dst,$tmp,$dst\n\t"
9623 "POPC $dst,$dst\n\t"
9624 "MOV 32,$tmp\n\t"
9625 "SUB $tmp,$dst,$dst" %}
9626 ins_encode %{
9627 Register Rdst = $dst$$Register;
9628 Register Rsrc = $src$$Register;
9629 Register Rtmp = $tmp$$Register;
9630 __ srl(Rsrc, 1, Rtmp);
9631 __ srl(Rsrc, 0, Rdst);
9632 __ or3(Rdst, Rtmp, Rdst);
9633 __ srl(Rdst, 2, Rtmp);
9634 __ or3(Rdst, Rtmp, Rdst);
9635 __ srl(Rdst, 4, Rtmp);
9636 __ or3(Rdst, Rtmp, Rdst);
9637 __ srl(Rdst, 8, Rtmp);
9638 __ or3(Rdst, Rtmp, Rdst);
9639 __ srl(Rdst, 16, Rtmp);
9640 __ or3(Rdst, Rtmp, Rdst);
9641 __ popc(Rdst, Rdst);
9642 __ mov(BitsPerInt, Rtmp);
9643 __ sub(Rtmp, Rdst, Rdst);
9644 %}
9645 ins_pipe(ialu_reg);
9646 %}
9647
9648 instruct countLeadingZerosL(iRegIsafe dst, iRegL src, iRegL tmp, flagsReg cr) %{
9649 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
9650 match(Set dst (CountLeadingZerosL src));
9651 effect(TEMP dst, TEMP tmp, KILL cr);
9652
9653 // x |= (x >> 1);
9654 // x |= (x >> 2);
9655 // x |= (x >> 4);
9656 // x |= (x >> 8);
9657 // x |= (x >> 16);
9658 // x |= (x >> 32);
9659 // return (WORDBITS - popc(x));
9660 format %{ "SRLX $src,1,$tmp\t! count leading zeros (long)\n\t"
9661 "OR $src,$tmp,$dst\n\t"
9662 "SRLX $dst,2,$tmp\n\t"
9663 "OR $dst,$tmp,$dst\n\t"
9664 "SRLX $dst,4,$tmp\n\t"
9665 "OR $dst,$tmp,$dst\n\t"
9666 "SRLX $dst,8,$tmp\n\t"
9667 "OR $dst,$tmp,$dst\n\t"
9668 "SRLX $dst,16,$tmp\n\t"
9669 "OR $dst,$tmp,$dst\n\t"
9670 "SRLX $dst,32,$tmp\n\t"
9671 "OR $dst,$tmp,$dst\n\t"
9672 "POPC $dst,$dst\n\t"
9673 "MOV 64,$tmp\n\t"
9674 "SUB $tmp,$dst,$dst" %}
9675 ins_encode %{
9676 Register Rdst = $dst$$Register;
9677 Register Rsrc = $src$$Register;
9678 Register Rtmp = $tmp$$Register;
9679 __ srlx(Rsrc, 1, Rtmp);
9680 __ or3( Rsrc, Rtmp, Rdst);
9681 __ srlx(Rdst, 2, Rtmp);
9682 __ or3( Rdst, Rtmp, Rdst);
9683 __ srlx(Rdst, 4, Rtmp);
9684 __ or3( Rdst, Rtmp, Rdst);
9685 __ srlx(Rdst, 8, Rtmp);
9686 __ or3( Rdst, Rtmp, Rdst);
9687 __ srlx(Rdst, 16, Rtmp);
9688 __ or3( Rdst, Rtmp, Rdst);
9689 __ srlx(Rdst, 32, Rtmp);
9690 __ or3( Rdst, Rtmp, Rdst);
9691 __ popc(Rdst, Rdst);
9692 __ mov(BitsPerLong, Rtmp);
9693 __ sub(Rtmp, Rdst, Rdst);
9694 %}
9695 ins_pipe(ialu_reg);
9696 %}
9697
9698 instruct countTrailingZerosI(iRegI dst, iRegI src, flagsReg cr) %{
9699 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
9700 match(Set dst (CountTrailingZerosI src));
9701 effect(TEMP dst, KILL cr);
9702
9703 // return popc(~x & (x - 1));
9704 format %{ "SUB $src,1,$dst\t! count trailing zeros (int)\n\t"
9705 "ANDN $dst,$src,$dst\n\t"
9706 "SRL $dst,R_G0,$dst\n\t"
9707 "POPC $dst,$dst" %}
9708 ins_encode %{
9709 Register Rdst = $dst$$Register;
9710 Register Rsrc = $src$$Register;
9711 __ sub(Rsrc, 1, Rdst);
9712 __ andn(Rdst, Rsrc, Rdst);
9713 __ srl(Rdst, G0, Rdst);
9714 __ popc(Rdst, Rdst);
9715 %}
9716 ins_pipe(ialu_reg);
9717 %}
9718
9719 instruct countTrailingZerosL(iRegI dst, iRegL src, flagsReg cr) %{
9720 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
9721 match(Set dst (CountTrailingZerosL src));
9722 effect(TEMP dst, KILL cr);
9723
9724 // return popc(~x & (x - 1));
9725 format %{ "SUB $src,1,$dst\t! count trailing zeros (long)\n\t"
9726 "ANDN $dst,$src,$dst\n\t"
9727 "POPC $dst,$dst" %}
9728 ins_encode %{
9729 Register Rdst = $dst$$Register;
9730 Register Rsrc = $src$$Register;
9731 __ sub(Rsrc, 1, Rdst);
9732 __ andn(Rdst, Rsrc, Rdst);
9733 __ popc(Rdst, Rdst);
9734 %}
9735 ins_pipe(ialu_reg);
9736 %}
9737
9738
9739 //---------- Population Count Instructions -------------------------------------
9740
9741 instruct popCountI(iRegI dst, iRegI src) %{
9742 predicate(UsePopCountInstruction);
9743 match(Set dst (PopCountI src));
9744
9745 format %{ "POPC $src, $dst" %}
9746 ins_encode %{
9747 __ popc($src$$Register, $dst$$Register);
9748 %}
9749 ins_pipe(ialu_reg);
9750 %}
9751
9752 // Note: Long.bitCount(long) returns an int.
9753 instruct popCountL(iRegI dst, iRegL src) %{
9754 predicate(UsePopCountInstruction);
9755 match(Set dst (PopCountL src));
9756
9757 format %{ "POPC $src, $dst" %}
9758 ins_encode %{
9759 __ popc($src$$Register, $dst$$Register);
9760 %}
9761 ins_pipe(ialu_reg);
9762 %}
9763
9764
9765 // ============================================================================
9766 //------------Bytes reverse--------------------------------------------------
9767
9768 instruct bytes_reverse_int(iRegI dst, stackSlotI src) %{
9769 match(Set dst (ReverseBytesI src));
9770
9771 // Op cost is artificially doubled to make sure that load or store
9772 // instructions are preferred over this one which requires a spill
9773 // onto a stack slot.
9774 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
9775 format %{ "LDUWA $src, $dst\t!asi=primary_little" %}
9776
9777 ins_encode %{
9778 __ set($src$$disp + STACK_BIAS, O7);
9779 __ lduwa($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
9780 %}
9781 ins_pipe( iload_mem );
9782 %}
9783
9784 instruct bytes_reverse_long(iRegL dst, stackSlotL src) %{
9785 match(Set dst (ReverseBytesL src));
9786
9787 // Op cost is artificially doubled to make sure that load or store
9788 // instructions are preferred over this one which requires a spill
9789 // onto a stack slot.
9790 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
9791 format %{ "LDXA $src, $dst\t!asi=primary_little" %}
9792
9793 ins_encode %{
9794 __ set($src$$disp + STACK_BIAS, O7);
9795 __ ldxa($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
9796 %}
9797 ins_pipe( iload_mem );
9798 %}
9799
9800 instruct bytes_reverse_unsigned_short(iRegI dst, stackSlotI src) %{
9801 match(Set dst (ReverseBytesUS src));
9802
9803 // Op cost is artificially doubled to make sure that load or store
9804 // instructions are preferred over this one which requires a spill
9805 // onto a stack slot.
9806 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
9807 format %{ "LDUHA $src, $dst\t!asi=primary_little\n\t" %}
9808
9809 ins_encode %{
9810 // the value was spilled as an int so bias the load
9811 __ set($src$$disp + STACK_BIAS + 2, O7);
9812 __ lduha($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
9813 %}
9814 ins_pipe( iload_mem );
9815 %}
9816
9817 instruct bytes_reverse_short(iRegI dst, stackSlotI src) %{
9818 match(Set dst (ReverseBytesS src));
9819
9820 // Op cost is artificially doubled to make sure that load or store
9821 // instructions are preferred over this one which requires a spill
9822 // onto a stack slot.
9823 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
9824 format %{ "LDSHA $src, $dst\t!asi=primary_little\n\t" %}
9825
9826 ins_encode %{
9827 // the value was spilled as an int so bias the load
9828 __ set($src$$disp + STACK_BIAS + 2, O7);
9829 __ ldsha($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
9830 %}
9831 ins_pipe( iload_mem );
9832 %}
9833
9834 // Load Integer reversed byte order
9835 instruct loadI_reversed(iRegI dst, indIndexMemory src) %{
9836 match(Set dst (ReverseBytesI (LoadI src)));
9837
9838 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
9839 size(4);
9840 format %{ "LDUWA $src, $dst\t!asi=primary_little" %}
9841
9842 ins_encode %{
9843 __ lduwa($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
9844 %}
9845 ins_pipe(iload_mem);
9846 %}
9847
9848 // Load Long - aligned and reversed
9849 instruct loadL_reversed(iRegL dst, indIndexMemory src) %{
9850 match(Set dst (ReverseBytesL (LoadL src)));
9851
9852 ins_cost(MEMORY_REF_COST);
9853 size(4);
9854 format %{ "LDXA $src, $dst\t!asi=primary_little" %}
9855
9856 ins_encode %{
9857 __ ldxa($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
9858 %}
9859 ins_pipe(iload_mem);
9860 %}
9861
9862 // Load unsigned short / char reversed byte order
9863 instruct loadUS_reversed(iRegI dst, indIndexMemory src) %{
9864 match(Set dst (ReverseBytesUS (LoadUS src)));
9865
9866 ins_cost(MEMORY_REF_COST);
9867 size(4);
9868 format %{ "LDUHA $src, $dst\t!asi=primary_little" %}
9869
9870 ins_encode %{
9871 __ lduha($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
9872 %}
9873 ins_pipe(iload_mem);
9874 %}
9875
9876 // Load short reversed byte order
9877 instruct loadS_reversed(iRegI dst, indIndexMemory src) %{
9878 match(Set dst (ReverseBytesS (LoadS src)));
9879
9880 ins_cost(MEMORY_REF_COST);
9881 size(4);
9882 format %{ "LDSHA $src, $dst\t!asi=primary_little" %}
9883
9884 ins_encode %{
9885 __ ldsha($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
9886 %}
9887 ins_pipe(iload_mem);
9888 %}
9889
9890 // Store Integer reversed byte order
9891 instruct storeI_reversed(indIndexMemory dst, iRegI src) %{
9892 match(Set dst (StoreI dst (ReverseBytesI src)));
9893
9894 ins_cost(MEMORY_REF_COST);
9895 size(4);
9896 format %{ "STWA $src, $dst\t!asi=primary_little" %}
9897
9898 ins_encode %{
9899 __ stwa($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
9900 %}
9901 ins_pipe(istore_mem_reg);
9902 %}
9903
9904 // Store Long reversed byte order
9905 instruct storeL_reversed(indIndexMemory dst, iRegL src) %{
9906 match(Set dst (StoreL dst (ReverseBytesL src)));
9907
9908 ins_cost(MEMORY_REF_COST);
9909 size(4);
9910 format %{ "STXA $src, $dst\t!asi=primary_little" %}
9911
9912 ins_encode %{
9913 __ stxa($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
9914 %}
9915 ins_pipe(istore_mem_reg);
9916 %}
9917
9918 // Store unsighed short/char reversed byte order
9919 instruct storeUS_reversed(indIndexMemory dst, iRegI src) %{
9920 match(Set dst (StoreC dst (ReverseBytesUS src)));
9921
9922 ins_cost(MEMORY_REF_COST);
9923 size(4);
9924 format %{ "STHA $src, $dst\t!asi=primary_little" %}
9925
9926 ins_encode %{
9927 __ stha($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
9928 %}
9929 ins_pipe(istore_mem_reg);
9930 %}
9931
9932 // Store short reversed byte order
9933 instruct storeS_reversed(indIndexMemory dst, iRegI src) %{
9934 match(Set dst (StoreC dst (ReverseBytesS src)));
9935
9936 ins_cost(MEMORY_REF_COST);
9937 size(4);
9938 format %{ "STHA $src, $dst\t!asi=primary_little" %}
9939
9940 ins_encode %{
9941 __ stha($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
9942 %}
9943 ins_pipe(istore_mem_reg);
9944 %}
9945
9946 //----------PEEPHOLE RULES-----------------------------------------------------
9947 // These must follow all instruction definitions as they use the names
9948 // defined in the instructions definitions.
9949 //
9950 // peepmatch ( root_instr_name [preceding_instruction]* );
9951 //
9952 // peepconstraint %{
9953 // (instruction_number.operand_name relational_op instruction_number.operand_name
9954 // [, ...] );
9955 // // instruction numbers are zero-based using left to right order in peepmatch
9956 //
9957 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
9958 // // provide an instruction_number.operand_name for each operand that appears
9959 // // in the replacement instruction's match rule
9960 //
9961 // ---------VM FLAGS---------------------------------------------------------
9962 //
9963 // All peephole optimizations can be turned off using -XX:-OptoPeephole
9964 //
9965 // Each peephole rule is given an identifying number starting with zero and
9966 // increasing by one in the order seen by the parser. An individual peephole
9967 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
9968 // on the command-line.
9969 //
9970 // ---------CURRENT LIMITATIONS----------------------------------------------
9971 //
9972 // Only match adjacent instructions in same basic block
9973 // Only equality constraints
9974 // Only constraints between operands, not (0.dest_reg == EAX_enc)
9975 // Only one replacement instruction
9976 //
9977 // ---------EXAMPLE----------------------------------------------------------
9978 //
9979 // // pertinent parts of existing instructions in architecture description
9980 // instruct movI(eRegI dst, eRegI src) %{
9981 // match(Set dst (CopyI src));
9982 // %}
9983 //
9984 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{
9985 // match(Set dst (AddI dst src));
9986 // effect(KILL cr);
9987 // %}
9988 //
9989 // // Change (inc mov) to lea
9990 // peephole %{
9991 // // increment preceeded by register-register move
9992 // peepmatch ( incI_eReg movI );
9993 // // require that the destination register of the increment
9994 // // match the destination register of the move
9995 // peepconstraint ( 0.dst == 1.dst );
9996 // // construct a replacement instruction that sets
9997 // // the destination to ( move's source register + one )
9998 // peepreplace ( incI_eReg_immI1( 0.dst 1.src 0.src ) );
9999 // %}
10000 //
10001
10002 // // Change load of spilled value to only a spill
10003 // instruct storeI(memory mem, eRegI src) %{
10004 // match(Set mem (StoreI mem src));
10005 // %}
10006 //
10007 // instruct loadI(eRegI dst, memory mem) %{
10008 // match(Set dst (LoadI mem));
10009 // %}
10010 //
10011 // peephole %{
10012 // peepmatch ( loadI storeI );
10013 // peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem );
10014 // peepreplace ( storeI( 1.mem 1.mem 1.src ) );
10015 // %}
10016
10017 //----------SMARTSPILL RULES---------------------------------------------------
10018 // These must follow all instruction definitions as they use the names
10019 // defined in the instructions definitions.
10020 //
10021 // SPARC will probably not have any of these rules due to RISC instruction set.
10022
10023 //----------PIPELINE-----------------------------------------------------------
10024 // Rules which define the behavior of the target architectures pipeline.