528
529 // Allocate argument register save area
530 if (frame::arg_reg_save_area_bytes != 0) {
531 __ subptr(rsp, frame::arg_reg_save_area_bytes);
532 }
533 __ mov(c_rarg0, rbx);
534 __ mov(c_rarg1, rax);
535 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::fixup_callers_callsite)));
536
537 // De-allocate argument register save area
538 if (frame::arg_reg_save_area_bytes != 0) {
539 __ addptr(rsp, frame::arg_reg_save_area_bytes);
540 }
541
542 __ pop_CPU_state();
543 // restore sp
544 __ mov(rsp, r13);
545 __ bind(L);
546 }
547
548
549 static void gen_c2i_adapter(MacroAssembler *masm,
550 int total_args_passed,
551 int comp_args_on_stack,
552 const BasicType *sig_bt,
553 const VMRegPair *regs,
554 Label& skip_fixup) {
555 // Before we get into the guts of the C2I adapter, see if we should be here
556 // at all. We've come from compiled code and are attempting to jump to the
557 // interpreter, which means the caller made a static call to get here
558 // (vcalls always get a compiled target if there is one). Check for a
559 // compiled target. If there is one, we need to patch the caller's call.
560 patch_callers_callsite(masm);
561
562 __ bind(skip_fixup);
563
564 // Since all args are passed on the stack, total_args_passed *
565 // Interpreter::stackElementSize is the space we need. Plus 1 because
566 // we also account for the return address location since
567 // we store it first rather than hold it in rax across all the shuffling
568
569 int extraspace = (total_args_passed * Interpreter::stackElementSize) + wordSize;
570
571 // stack is aligned, keep it that way
572 extraspace = round_to(extraspace, 2*wordSize);
573
574 // Get return address
575 __ pop(rax);
576
577 // set senderSP value
578 __ mov(r13, rsp);
579
580 __ subptr(rsp, extraspace);
581
582 // Store the return address in the expected location
583 __ movptr(Address(rsp, 0), rax);
584
585 // Now write the args into the outgoing interpreter space
586 for (int i = 0; i < total_args_passed; i++) {
587 if (sig_bt[i] == T_VOID) {
588 assert(i > 0 && (sig_bt[i-1] == T_LONG || sig_bt[i-1] == T_DOUBLE), "missing half");
589 continue;
590 }
591
592 // offset to start parameters
593 int st_off = (total_args_passed - i) * Interpreter::stackElementSize;
594 int next_off = st_off - Interpreter::stackElementSize;
595
596 // Say 4 args:
597 // i st_off
598 // 0 32 T_LONG
599 // 1 24 T_VOID
600 // 2 16 T_OBJECT
601 // 3 8 T_BOOL
602 // - 0 return address
603 //
604 // However to make thing extra confusing. Because we can fit a long/double in
605 // a single slot on a 64 bt vm and it would be silly to break them up, the interpreter
606 // leaves one slot empty and only stores to a single slot. In this case the
607 // slot that is occupied is the T_VOID slot. See I said it was confusing.
608
609 VMReg r_1 = regs[i].first();
610 VMReg r_2 = regs[i].second();
611 if (!r_1->is_valid()) {
612 assert(!r_2->is_valid(), "");
613 continue;
614 }
615 if (r_1->is_stack()) {
616 // memory to memory use rax
617 int ld_off = r_1->reg2stack() * VMRegImpl::stack_slot_size + extraspace;
618 if (!r_2->is_valid()) {
619 // sign extend??
620 __ movl(rax, Address(rsp, ld_off));
621 __ movptr(Address(rsp, st_off), rax);
622
623 } else {
624
625 __ movq(rax, Address(rsp, ld_off));
626
627 // Two VMREgs|OptoRegs can be T_OBJECT, T_ADDRESS, T_DOUBLE, T_LONG
628 // T_DOUBLE and T_LONG use two slots in the interpreter
629 if ( sig_bt[i] == T_LONG || sig_bt[i] == T_DOUBLE) {
630 // ld_off == LSW, ld_off+wordSize == MSW
631 // st_off == MSW, next_off == LSW
632 __ movq(Address(rsp, next_off), rax);
633 #ifdef ASSERT
634 // Overwrite the unused slot with known junk
635 __ mov64(rax, CONST64(0xdeadffffdeadaaaa));
636 __ movptr(Address(rsp, st_off), rax);
637 #endif /* ASSERT */
638 } else {
639 __ movq(Address(rsp, st_off), rax);
640 }
641 }
642 } else if (r_1->is_Register()) {
643 Register r = r_1->as_Register();
644 if (!r_2->is_valid()) {
645 // must be only an int (or less ) so move only 32bits to slot
646 // why not sign extend??
647 __ movl(Address(rsp, st_off), r);
648 } else {
649 // Two VMREgs|OptoRegs can be T_OBJECT, T_ADDRESS, T_DOUBLE, T_LONG
650 // T_DOUBLE and T_LONG use two slots in the interpreter
651 if ( sig_bt[i] == T_LONG || sig_bt[i] == T_DOUBLE) {
652 // long/double in gpr
653 #ifdef ASSERT
654 // Overwrite the unused slot with known junk
655 __ mov64(rax, CONST64(0xdeadffffdeadaaab));
656 __ movptr(Address(rsp, st_off), rax);
657 #endif /* ASSERT */
658 __ movq(Address(rsp, next_off), r);
659 } else {
660 __ movptr(Address(rsp, st_off), r);
661 }
662 }
663 } else {
664 assert(r_1->is_XMMRegister(), "");
665 if (!r_2->is_valid()) {
666 // only a float use just part of the slot
667 __ movflt(Address(rsp, st_off), r_1->as_XMMRegister());
668 } else {
669 #ifdef ASSERT
670 // Overwrite the unused slot with known junk
671 __ mov64(rax, CONST64(0xdeadffffdeadaaac));
672 __ movptr(Address(rsp, st_off), rax);
673 #endif /* ASSERT */
674 __ movdbl(Address(rsp, next_off), r_1->as_XMMRegister());
675 }
676 }
677 }
678
679 // Schedule the branch target address early.
680 __ movptr(rcx, Address(rbx, in_bytes(Method::interpreter_entry_offset())));
681 __ jmp(rcx);
682 }
683
684 static void range_check(MacroAssembler* masm, Register pc_reg, Register temp_reg,
685 address code_start, address code_end,
686 Label& L_ok) {
687 Label L_fail;
688 __ lea(temp_reg, ExternalAddress(code_start));
689 __ cmpptr(pc_reg, temp_reg);
690 __ jcc(Assembler::belowEqual, L_fail);
691 __ lea(temp_reg, ExternalAddress(code_end));
692 __ cmpptr(pc_reg, temp_reg);
693 __ jcc(Assembler::below, L_ok);
694 __ bind(L_fail);
695 }
696
697 void SharedRuntime::gen_i2c_adapter(MacroAssembler *masm,
698 int total_args_passed,
699 int comp_args_on_stack,
700 const BasicType *sig_bt,
701 const VMRegPair *regs) {
702
703 // Note: r13 contains the senderSP on entry. We must preserve it since
704 // we may do a i2c -> c2i transition if we lose a race where compiled
705 // code goes non-entrant while we get args ready.
706 // In addition we use r13 to locate all the interpreter args as
707 // we must align the stack to 16 bytes on an i2c entry else we
708 // lose alignment we expect in all compiled code and register
709 // save code can segv when fxsave instructions find improperly
710 // aligned stack pointer.
711
712 // Adapters can be frameless because they do not require the caller
713 // to perform additional cleanup work, such as correcting the stack pointer.
714 // An i2c adapter is frameless because the *caller* frame, which is interpreted,
715 // routinely repairs its own stack pointer (from interpreter_frame_last_sp),
716 // even if a callee has modified the stack pointer.
717 // A c2i adapter is frameless because the *callee* frame, which is interpreted,
718 // routinely repairs its caller's stack pointer (from sender_sp, which is set
719 // up via the senderSP register).
720 // In other words, if *either* the caller or callee is interpreted, we can
786 // Put saved SP in another register
787 const Register saved_sp = rax;
788 __ movptr(saved_sp, r11);
789
790 // Will jump to the compiled code just as if compiled code was doing it.
791 // Pre-load the register-jump target early, to schedule it better.
792 __ movptr(r11, Address(rbx, in_bytes(Method::from_compiled_offset())));
793
794 #if INCLUDE_JVMCI
795 if (EnableJVMCI) {
796 // check if this call should be routed towards a specific entry point
797 __ cmpptr(Address(r15_thread, in_bytes(JavaThread::jvmci_alternate_call_target_offset())), 0);
798 Label no_alternative_target;
799 __ jcc(Assembler::equal, no_alternative_target);
800 __ movptr(r11, Address(r15_thread, in_bytes(JavaThread::jvmci_alternate_call_target_offset())));
801 __ movptr(Address(r15_thread, in_bytes(JavaThread::jvmci_alternate_call_target_offset())), 0);
802 __ bind(no_alternative_target);
803 }
804 #endif // INCLUDE_JVMCI
805
806 // Now generate the shuffle code. Pick up all register args and move the
807 // rest through the floating point stack top.
808 for (int i = 0; i < total_args_passed; i++) {
809 if (sig_bt[i] == T_VOID) {
810 // Longs and doubles are passed in native word order, but misaligned
811 // in the 32-bit build.
812 assert(i > 0 && (sig_bt[i-1] == T_LONG || sig_bt[i-1] == T_DOUBLE), "missing half");
813 continue;
814 }
815
816 // Pick up 0, 1 or 2 words from SP+offset.
817
818 assert(!regs[i].second()->is_valid() || regs[i].first()->next() == regs[i].second(),
819 "scrambled load targets?");
820 // Load in argument order going down.
821 int ld_off = (total_args_passed - i)*Interpreter::stackElementSize;
822 // Point to interpreter value (vs. tag)
823 int next_off = ld_off - Interpreter::stackElementSize;
824 //
825 //
826 //
827 VMReg r_1 = regs[i].first();
828 VMReg r_2 = regs[i].second();
829 if (!r_1->is_valid()) {
830 assert(!r_2->is_valid(), "");
831 continue;
832 }
833 if (r_1->is_stack()) {
834 // Convert stack slot to an SP offset (+ wordSize to account for return address )
835 int st_off = regs[i].first()->reg2stack()*VMRegImpl::stack_slot_size + wordSize;
836
837 // We can use r13 as a temp here because compiled code doesn't need r13 as an input
838 // and if we end up going thru a c2i because of a miss a reasonable value of r13
839 // will be generated.
840 if (!r_2->is_valid()) {
841 // sign extend???
842 __ movl(r13, Address(saved_sp, ld_off));
843 __ movptr(Address(rsp, st_off), r13);
844 } else {
845 //
846 // We are using two optoregs. This can be either T_OBJECT, T_ADDRESS, T_LONG, or T_DOUBLE
847 // the interpreter allocates two slots but only uses one for thr T_LONG or T_DOUBLE case
848 // So we must adjust where to pick up the data to match the interpreter.
849 //
850 // Interpreter local[n] == MSW, local[n+1] == LSW however locals
851 // are accessed as negative so LSW is at LOW address
852
853 // ld_off is MSW so get LSW
854 const int offset = (sig_bt[i]==T_LONG||sig_bt[i]==T_DOUBLE)?
855 next_off : ld_off;
856 __ movq(r13, Address(saved_sp, offset));
857 // st_off is LSW (i.e. reg.first())
858 __ movq(Address(rsp, st_off), r13);
859 }
860 } else if (r_1->is_Register()) { // Register argument
861 Register r = r_1->as_Register();
862 assert(r != rax, "must be different");
863 if (r_2->is_valid()) {
864 //
865 // We are using two VMRegs. This can be either T_OBJECT, T_ADDRESS, T_LONG, or T_DOUBLE
866 // the interpreter allocates two slots but only uses one for thr T_LONG or T_DOUBLE case
867 // So we must adjust where to pick up the data to match the interpreter.
868
869 const int offset = (sig_bt[i]==T_LONG||sig_bt[i]==T_DOUBLE)?
870 next_off : ld_off;
871
872 // this can be a misaligned move
873 __ movq(r, Address(saved_sp, offset));
874 } else {
875 // sign extend and use a full word?
876 __ movl(r, Address(saved_sp, ld_off));
877 }
878 } else {
879 if (!r_2->is_valid()) {
880 __ movflt(r_1->as_XMMRegister(), Address(saved_sp, ld_off));
881 } else {
882 __ movdbl(r_1->as_XMMRegister(), Address(saved_sp, next_off));
883 }
884 }
885 }
886
887 // 6243940 We might end up in handle_wrong_method if
888 // the callee is deoptimized as we race thru here. If that
889 // happens we don't want to take a safepoint because the
890 // caller frame will look interpreted and arguments are now
891 // "compiled" so it is much better to make this transition
892 // invisible to the stack walking code. Unfortunately if
893 // we try and find the callee by normal means a safepoint
894 // is possible. So we stash the desired callee in the thread
895 // and the vm will find there should this case occur.
896
897 __ movptr(Address(r15_thread, JavaThread::callee_target_offset()), rbx);
898
899 // put Method* where a c2i would expect should we end up there
900 // only needed becaus eof c2 resolve stubs return Method* as a result in
901 // rax
902 __ mov(rax, rbx);
903 __ jmp(r11);
904 }
905
906 // ---------------------------------------------------------------
907 AdapterHandlerEntry* SharedRuntime::generate_i2c2i_adapters(MacroAssembler *masm,
908 int total_args_passed,
909 int comp_args_on_stack,
910 const BasicType *sig_bt,
911 const VMRegPair *regs,
912 AdapterFingerPrint* fingerprint) {
913 address i2c_entry = __ pc();
914
915 gen_i2c_adapter(masm, total_args_passed, comp_args_on_stack, sig_bt, regs);
916
917 // -------------------------------------------------------------------------
918 // Generate a C2I adapter. On entry we know rbx holds the Method* during calls
919 // to the interpreter. The args start out packed in the compiled layout. They
920 // need to be unpacked into the interpreter layout. This will almost always
921 // require some stack space. We grow the current (compiled) stack, then repack
922 // the args. We finally end in a jump to the generic interpreter entry point.
923 // On exit from the interpreter, the interpreter will restore our SP (lest the
924 // compiled code, which relys solely on SP and not RBP, get sick).
925
926 address c2i_unverified_entry = __ pc();
927 Label skip_fixup;
928 Label ok;
929
930 Register holder = rax;
931 Register receiver = j_rarg0;
932 Register temp = rbx;
933
934 {
935 __ load_klass(temp, receiver);
936 __ cmpptr(temp, Address(holder, CompiledICHolder::holder_klass_offset()));
937 __ movptr(rbx, Address(holder, CompiledICHolder::holder_method_offset()));
938 __ jcc(Assembler::equal, ok);
939 __ jump(RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
940
941 __ bind(ok);
942 // Method might have been compiled since the call site was patched to
943 // interpreted if that is the case treat it as a miss so we can get
944 // the call site corrected.
945 __ cmpptr(Address(rbx, in_bytes(Method::code_offset())), (int32_t)NULL_WORD);
946 __ jcc(Assembler::equal, skip_fixup);
947 __ jump(RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
948 }
949
950 address c2i_entry = __ pc();
951
952 gen_c2i_adapter(masm, total_args_passed, comp_args_on_stack, sig_bt, regs, skip_fixup);
953
954 __ flush();
955 return AdapterHandlerLibrary::new_entry(fingerprint, i2c_entry, c2i_entry, c2i_unverified_entry);
956 }
957
958 int SharedRuntime::c_calling_convention(const BasicType *sig_bt,
959 VMRegPair *regs,
960 VMRegPair *regs2,
961 int total_args_passed) {
962 assert(regs2 == NULL, "not needed on x86");
963 // We return the amount of VMRegImpl stack slots we need to reserve for all
964 // the arguments NOT counting out_preserve_stack_slots.
965
966 // NOTE: These arrays will have to change when c1 is ported
967 #ifdef _WIN64
968 static const Register INT_ArgReg[Argument::n_int_register_parameters_c] = {
969 c_rarg0, c_rarg1, c_rarg2, c_rarg3
970 };
971 static const XMMRegister FP_ArgReg[Argument::n_float_register_parameters_c] = {
972 c_farg0, c_farg1, c_farg2, c_farg3
973 };
974 #else
|
528
529 // Allocate argument register save area
530 if (frame::arg_reg_save_area_bytes != 0) {
531 __ subptr(rsp, frame::arg_reg_save_area_bytes);
532 }
533 __ mov(c_rarg0, rbx);
534 __ mov(c_rarg1, rax);
535 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::fixup_callers_callsite)));
536
537 // De-allocate argument register save area
538 if (frame::arg_reg_save_area_bytes != 0) {
539 __ addptr(rsp, frame::arg_reg_save_area_bytes);
540 }
541
542 __ pop_CPU_state();
543 // restore sp
544 __ mov(rsp, r13);
545 __ bind(L);
546 }
547
548 // For each value type argument, sig includes the list of fields of
549 // the value type. This utility function computes the number of
550 // arguments for the call if value types are passed by reference (the
551 // calling convention the interpreter expects).
552 static int compute_total_args_passed(const GrowableArray<SigEntry>& sig) {
553 int total_args_passed = 0;
554 if (ValueTypePassFieldsAsArgs) {
555 for (int i = 0; i < sig.length(); i++) {
556 BasicType bt = sig.at(i)._bt;
557 if (bt == T_VALUETYPE) {
558 // In sig, a value type argument starts with: T_VALUETYPE,
559 // followed by the types of the fields of the value type and
560 // T_VOID to mark the end of the value type. Value types are
561 // flattened so, for instance: T_VALUETYPE T_INT T_VALUETYPE
562 // T_INT T_LONG T_VOID T_VOID T_VOID is a value type with a
563 // int field an a value type field that itself has 2 fields, a
564 // int and a long
565 total_args_passed++;
566 int vt = 1;
567 do {
568 i++;
569 BasicType bt = sig.at(i)._bt;
570 BasicType prev_bt = sig.at(i-1)._bt;
571 if (bt == T_VALUETYPE) {
572 vt++;
573 } else if (bt == T_VOID &&
574 prev_bt != T_LONG &&
575 prev_bt != T_DOUBLE) {
576 vt--;
577 }
578 } while (vt != 0);
579 } else {
580 total_args_passed++;
581 }
582 }
583 } else {
584 total_args_passed = sig.length();
585 }
586 return total_args_passed;
587 }
588
589
590 static void gen_c2i_adapter_helper(MacroAssembler *masm,
591 BasicType bt,
592 BasicType prev_bt,
593 const VMRegPair& reg_pair,
594 const Address& to,
595 int extraspace) {
596 assert(bt != T_VALUETYPE || !ValueTypePassFieldsAsArgs, "no value type here");
597 if (bt == T_VOID) {
598 assert(prev_bt == T_LONG || prev_bt == T_DOUBLE, "missing half");
599 return;
600 }
601
602 // Say 4 args:
603 // i st_off
604 // 0 32 T_LONG
605 // 1 24 T_VOID
606 // 2 16 T_OBJECT
607 // 3 8 T_BOOL
608 // - 0 return address
609 //
610 // However to make thing extra confusing. Because we can fit a long/double in
611 // a single slot on a 64 bt vm and it would be silly to break them up, the interpreter
612 // leaves one slot empty and only stores to a single slot. In this case the
613 // slot that is occupied is the T_VOID slot. See I said it was confusing.
614
615 VMReg r_1 = reg_pair.first();
616 VMReg r_2 = reg_pair.second();
617 if (!r_1->is_valid()) {
618 assert(!r_2->is_valid(), "");
619 return;
620 }
621 if (r_1->is_stack()) {
622 // memory to memory use rax
623 int ld_off = r_1->reg2stack() * VMRegImpl::stack_slot_size + extraspace;
624 if (!r_2->is_valid()) {
625 // sign extend??
626 __ movl(rax, Address(rsp, ld_off));
627 __ movl(to, rax);
628
629 } else {
630
631 __ movq(rax, Address(rsp, ld_off));
632
633 // Two VMREgs|OptoRegs can be T_OBJECT, T_ADDRESS, T_DOUBLE, T_LONG
634 // T_DOUBLE and T_LONG use two slots in the interpreter
635 if ( bt == T_LONG || bt == T_DOUBLE) {
636 // ld_off == LSW, ld_off+wordSize == MSW
637 // st_off == MSW, next_off == LSW
638 __ movq(to, rax);
639 } else {
640 __ movq(to, rax);
641 }
642 }
643 } else if (r_1->is_Register()) {
644 Register r = r_1->as_Register();
645 if (!r_2->is_valid()) {
646 // must be only an int (or less ) so move only 32bits to slot
647 // why not sign extend??
648 __ movl(to, r);
649 } else {
650 // Two VMREgs|OptoRegs can be T_OBJECT, T_ADDRESS, T_DOUBLE, T_LONG
651 // T_DOUBLE and T_LONG use two slots in the interpreter
652 if ( bt == T_LONG || bt == T_DOUBLE) {
653 // long/double in gpr
654 __ movq(to, r);
655 } else {
656 __ movptr(to, r);
657 }
658 }
659 } else {
660 assert(r_1->is_XMMRegister(), "");
661 if (!r_2->is_valid()) {
662 // only a float use just part of the slot
663 __ movflt(to, r_1->as_XMMRegister());
664 } else {
665 __ movdbl(to, r_1->as_XMMRegister());
666 }
667 }
668 }
669
670 static void gen_c2i_adapter(MacroAssembler *masm,
671 const GrowableArray<SigEntry>& sig,
672 const VMRegPair *regs,
673 Label& skip_fixup,
674 address start,
675 OopMapSet*& oop_maps,
676 int& frame_complete,
677 int& frame_size_in_words) {
678 // Before we get into the guts of the C2I adapter, see if we should be here
679 // at all. We've come from compiled code and are attempting to jump to the
680 // interpreter, which means the caller made a static call to get here
681 // (vcalls always get a compiled target if there is one). Check for a
682 // compiled target. If there is one, we need to patch the caller's call.
683 patch_callers_callsite(masm);
684
685 __ bind(skip_fixup);
686
687 if (ValueTypePassFieldsAsArgs) {
688 // Is there a value type arguments?
689 int i = 0;
690 for (; i < sig.length() && sig.at(i)._bt != T_VALUETYPE; i++);
691
692 if (i != sig.length()) {
693 // There is at least a value type argument: we're coming from
694 // compiled code so we have no buffers to back the value
695 // types. Allocate the buffers here with a runtime call.
696 oop_maps = new OopMapSet();
697 OopMap* map = NULL;
698
699 map = RegisterSaver::save_live_registers(masm, 0, &frame_size_in_words);
700
701 frame_complete = __ offset();
702
703 __ set_last_Java_frame(noreg, noreg, NULL);
704
705 __ mov(c_rarg0, r15_thread);
706
707 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::allocate_value_types)));
708
709 oop_maps->add_gc_map((int)(__ pc() - start), map);
710 __ reset_last_Java_frame(false, false);
711
712 RegisterSaver::restore_live_registers(masm);
713
714 Label no_exception;
715 __ cmpptr(Address(r15_thread, Thread::pending_exception_offset()), (int32_t)NULL_WORD);
716 __ jcc(Assembler::equal, no_exception);
717
718 __ movptr(Address(r15_thread, JavaThread::vm_result_offset()), (int)NULL_WORD);
719 __ movptr(rax, Address(r15_thread, Thread::pending_exception_offset()));
720 __ jump(RuntimeAddress(StubRoutines::forward_exception_entry()));
721
722 __ bind(no_exception);
723
724 // We get an array of objects from the runtime call
725 int offset_in_bytes = arrayOopDesc::base_offset_in_bytes(T_OBJECT);
726 __ get_vm_result(r13, r15_thread);
727 __ addptr(r13, offset_in_bytes);
728 __ mov(r10, r13);
729 }
730 }
731
732
733 // Since all args are passed on the stack, total_args_passed *
734 // Interpreter::stackElementSize is the space we need. Plus 1 because
735 // we also account for the return address location since
736 // we store it first rather than hold it in rax across all the shuffling
737 int total_args_passed = compute_total_args_passed(sig);
738 int extraspace = (total_args_passed * Interpreter::stackElementSize) + wordSize;
739
740 // stack is aligned, keep it that way
741 extraspace = round_to(extraspace, 2*wordSize);
742
743 // Get return address
744 __ pop(rax);
745
746 // set senderSP value
747 __ mov(r13, rsp);
748
749 __ subptr(rsp, extraspace);
750
751 // Store the return address in the expected location
752 __ movptr(Address(rsp, 0), rax);
753
754 // Now write the args into the outgoing interpreter space
755
756 // i is the next argument from the compiler point of view (value
757 // type fields are passed in registers/on the stack). In sig, a
758 // value type argument starts with: T_VALUETYPE, followed by the
759 // types of the fields of the value type and T_VOID to mark the end
760 // of the value type. ignored counts the number of
761 // T_VALUETYPE/T_VOID. j is the next value type argument: used to
762 // get the buffer for that argument from the pool of buffers we
763 // allocated above and want to pass to the interpreter. k is the
764 // next argument from the interpreter point of view (value types are
765 // passed by reference).
766 for (int i = 0, ignored = 0, j = 0, k = 0; i < sig.length(); i++) {
767 assert((i == 0 && ignored == 0) || ignored < i, "");
768 assert(k < total_args_passed, "");
769 BasicType bt = sig.at(i)._bt;
770 int st_off = (total_args_passed - k) * Interpreter::stackElementSize;
771 if (!ValueTypePassFieldsAsArgs || bt != T_VALUETYPE) {
772 int next_off = st_off - Interpreter::stackElementSize;
773 const int offset = (bt==T_LONG||bt==T_DOUBLE) ? next_off : st_off;
774 gen_c2i_adapter_helper(masm, bt, i > 0 ? sig.at(i-1)._bt : T_ILLEGAL, regs[i-ignored], Address(rsp, offset), extraspace);
775 k++;
776 #ifdef ASSERT
777 if (bt==T_LONG || bt==T_DOUBLE) {
778 // Overwrite the unused slot with known junk
779 __ mov64(rax, CONST64(0xdeadffffdeadaaaa));
780 __ movptr(Address(rsp, st_off), rax);
781 }
782 #endif /* ASSERT */
783 } else {
784 ignored++;
785 // get the buffer from the just allocated pool of buffers
786 __ load_heap_oop(r11, Address(r10, j * type2aelembytes(T_VALUETYPE)));
787 j++; k++;
788 int vt = 1;
789 // write fields we get from compiled code in registers/stack
790 // slots to the buffer: we know we are done with that value type
791 // argument when we hit the T_VOID that acts as an end of value
792 // type delimiter for this value type. Value types are flattened
793 // so we might encounter a embedded value types. Each entry in
794 // sig contains a field offset in the buffer.
795 do {
796 i++;
797 BasicType bt = sig.at(i)._bt;
798 BasicType prev_bt = sig.at(i-1)._bt;
799 if (bt == T_VALUETYPE) {
800 vt++;
801 ignored++;
802 } else if (bt == T_VOID &&
803 prev_bt != T_LONG &&
804 prev_bt != T_DOUBLE) {
805 vt--;
806 ignored++;
807 } else {
808 int off = sig.at(i)._offset;
809 assert(off > 0, "");
810 gen_c2i_adapter_helper(masm, bt, i > 0 ? sig.at(i-1)._bt : T_ILLEGAL, regs[i-ignored], Address(r11, off), extraspace);
811 }
812 } while (vt != 0);
813 // pass the buffer to the interpreter
814 __ movptr(Address(rsp, st_off), r11);
815 }
816 }
817
818 // Schedule the branch target address early.
819 __ movptr(rcx, Address(rbx, in_bytes(Method::interpreter_entry_offset())));
820 __ jmp(rcx);
821 }
822
823 static void range_check(MacroAssembler* masm, Register pc_reg, Register temp_reg,
824 address code_start, address code_end,
825 Label& L_ok) {
826 Label L_fail;
827 __ lea(temp_reg, ExternalAddress(code_start));
828 __ cmpptr(pc_reg, temp_reg);
829 __ jcc(Assembler::belowEqual, L_fail);
830 __ lea(temp_reg, ExternalAddress(code_end));
831 __ cmpptr(pc_reg, temp_reg);
832 __ jcc(Assembler::below, L_ok);
833 __ bind(L_fail);
834 }
835
836 static void gen_i2c_adapter_helper(MacroAssembler *masm,
837 BasicType bt,
838 BasicType prev_bt,
839 const VMRegPair& reg_pair,
840 const Address& from) {
841 assert(bt != T_VALUETYPE || !ValueTypePassFieldsAsArgs, "no value type here");
842 if (bt == T_VOID) {
843 // Longs and doubles are passed in native word order, but misaligned
844 // in the 32-bit build.
845 assert(prev_bt == T_LONG || prev_bt == T_DOUBLE, "missing half");
846 return;
847 }
848 // Pick up 0, 1 or 2 words from SP+offset.
849
850 assert(!reg_pair.second()->is_valid() || reg_pair.first()->next() == reg_pair.second(),
851 "scrambled load targets?");
852 //
853 //
854 //
855 VMReg r_1 = reg_pair.first();
856 VMReg r_2 = reg_pair.second();
857 if (!r_1->is_valid()) {
858 assert(!r_2->is_valid(), "");
859 return;
860 }
861 if (r_1->is_stack()) {
862 // Convert stack slot to an SP offset (+ wordSize to account for return address )
863 int st_off = reg_pair.first()->reg2stack()*VMRegImpl::stack_slot_size + wordSize;
864
865 // We can use r13 as a temp here because compiled code doesn't need r13 as an input
866 // and if we end up going thru a c2i because of a miss a reasonable value of r13
867 // will be generated.
868 if (!r_2->is_valid()) {
869 // sign extend???
870 __ movl(r13, from);
871 __ movptr(Address(rsp, st_off), r13);
872 } else {
873 //
874 // We are using two optoregs. This can be either T_OBJECT, T_ADDRESS, T_LONG, or T_DOUBLE
875 // the interpreter allocates two slots but only uses one for thr T_LONG or T_DOUBLE case
876 // So we must adjust where to pick up the data to match the interpreter.
877 //
878 // Interpreter local[n] == MSW, local[n+1] == LSW however locals
879 // are accessed as negative so LSW is at LOW address
880
881 // ld_off is MSW so get LSW
882 __ movq(r13, from);
883 // st_off is LSW (i.e. reg.first())
884 __ movq(Address(rsp, st_off), r13);
885 }
886 } else if (r_1->is_Register()) { // Register argument
887 Register r = r_1->as_Register();
888 assert(r != rax, "must be different");
889 if (r_2->is_valid()) {
890 //
891 // We are using two VMRegs. This can be either T_OBJECT, T_ADDRESS, T_LONG, or T_DOUBLE
892 // the interpreter allocates two slots but only uses one for thr T_LONG or T_DOUBLE case
893 // So we must adjust where to pick up the data to match the interpreter.
894
895 // this can be a misaligned move
896 __ movq(r, from);
897 } else {
898 // sign extend and use a full word?
899 __ movl(r, from);
900 }
901 } else {
902 if (!r_2->is_valid()) {
903 __ movflt(r_1->as_XMMRegister(), from);
904 } else {
905 __ movdbl(r_1->as_XMMRegister(), from);
906 }
907 }
908 }
909
910 void SharedRuntime::gen_i2c_adapter(MacroAssembler *masm,
911 int comp_args_on_stack,
912 const GrowableArray<SigEntry>& sig,
913 const VMRegPair *regs) {
914
915 // Note: r13 contains the senderSP on entry. We must preserve it since
916 // we may do a i2c -> c2i transition if we lose a race where compiled
917 // code goes non-entrant while we get args ready.
918 // In addition we use r13 to locate all the interpreter args as
919 // we must align the stack to 16 bytes on an i2c entry else we
920 // lose alignment we expect in all compiled code and register
921 // save code can segv when fxsave instructions find improperly
922 // aligned stack pointer.
923
924 // Adapters can be frameless because they do not require the caller
925 // to perform additional cleanup work, such as correcting the stack pointer.
926 // An i2c adapter is frameless because the *caller* frame, which is interpreted,
927 // routinely repairs its own stack pointer (from interpreter_frame_last_sp),
928 // even if a callee has modified the stack pointer.
929 // A c2i adapter is frameless because the *callee* frame, which is interpreted,
930 // routinely repairs its caller's stack pointer (from sender_sp, which is set
931 // up via the senderSP register).
932 // In other words, if *either* the caller or callee is interpreted, we can
998 // Put saved SP in another register
999 const Register saved_sp = rax;
1000 __ movptr(saved_sp, r11);
1001
1002 // Will jump to the compiled code just as if compiled code was doing it.
1003 // Pre-load the register-jump target early, to schedule it better.
1004 __ movptr(r11, Address(rbx, in_bytes(Method::from_compiled_offset())));
1005
1006 #if INCLUDE_JVMCI
1007 if (EnableJVMCI) {
1008 // check if this call should be routed towards a specific entry point
1009 __ cmpptr(Address(r15_thread, in_bytes(JavaThread::jvmci_alternate_call_target_offset())), 0);
1010 Label no_alternative_target;
1011 __ jcc(Assembler::equal, no_alternative_target);
1012 __ movptr(r11, Address(r15_thread, in_bytes(JavaThread::jvmci_alternate_call_target_offset())));
1013 __ movptr(Address(r15_thread, in_bytes(JavaThread::jvmci_alternate_call_target_offset())), 0);
1014 __ bind(no_alternative_target);
1015 }
1016 #endif // INCLUDE_JVMCI
1017
1018 int total_args_passed = compute_total_args_passed(sig);
1019 // Now generate the shuffle code. Pick up all register args and move the
1020 // rest through the floating point stack top.
1021
1022 // i is the next argument from the compiler point of view (value
1023 // type fields are passed in registers/on the stack). In sig, a
1024 // value type argument starts with: T_VALUETYPE, followed by the
1025 // types of the fields of the value type and T_VOID to mark the end
1026 // of the value type. ignored counts the number of
1027 // T_VALUETYPE/T_VOID. k is the next argument from the interpreter
1028 // point of view (value types are passed by reference).
1029 for (int i = 0, ignored = 0, k = 0; i < sig.length(); i++) {
1030 assert((i == 0 && ignored == 0) || ignored < i, "");
1031 assert(k < total_args_passed, "");
1032 BasicType bt = sig.at(i)._bt;
1033 int ld_off = (total_args_passed - k)*Interpreter::stackElementSize;
1034 if (!ValueTypePassFieldsAsArgs || bt != T_VALUETYPE) {
1035 // Load in argument order going down.
1036 // Point to interpreter value (vs. tag)
1037 int next_off = ld_off - Interpreter::stackElementSize;
1038 const int offset = (bt==T_LONG||bt==T_DOUBLE) ? next_off : ld_off;
1039 gen_i2c_adapter_helper(masm, bt, i > 0 ? sig.at(i-1)._bt : T_ILLEGAL, regs[i-ignored], Address(saved_sp, offset));
1040 k++;
1041 } else {
1042 k++;
1043 ignored++;
1044 // get the buffer for that value type
1045 __ movptr(r10, Address(saved_sp, ld_off));
1046 int vt = 1;
1047 // load fields to registers/stack slots from the buffer: we know
1048 // we are done with that value type argument when we hit the
1049 // T_VOID that acts as an end of value type delimiter for this
1050 // value type. Value types are flattened so we might encounter a
1051 // embedded value types. Each entry in sig contains a field
1052 // offset in the buffer.
1053 do {
1054 i++;
1055 BasicType bt = sig.at(i)._bt;
1056 BasicType prev_bt = sig.at(i-1)._bt;
1057 if (bt == T_VALUETYPE) {
1058 vt++;
1059 ignored++;
1060 } else if (bt == T_VOID &&
1061 prev_bt != T_LONG &&
1062 prev_bt != T_DOUBLE) {
1063 vt--;
1064 ignored++;
1065 } else {
1066 int off = sig.at(i)._offset;
1067 assert(off > 0, "");
1068 gen_i2c_adapter_helper(masm, bt, prev_bt, regs[i - ignored], Address(r10, off));
1069 }
1070 } while (vt != 0);
1071 }
1072 }
1073
1074 // 6243940 We might end up in handle_wrong_method if
1075 // the callee is deoptimized as we race thru here. If that
1076 // happens we don't want to take a safepoint because the
1077 // caller frame will look interpreted and arguments are now
1078 // "compiled" so it is much better to make this transition
1079 // invisible to the stack walking code. Unfortunately if
1080 // we try and find the callee by normal means a safepoint
1081 // is possible. So we stash the desired callee in the thread
1082 // and the vm will find there should this case occur.
1083
1084 __ movptr(Address(r15_thread, JavaThread::callee_target_offset()), rbx);
1085
1086 // put Method* where a c2i would expect should we end up there
1087 // only needed because of c2 resolve stubs return Method* as a result in
1088 // rax
1089 __ mov(rax, rbx);
1090 __ jmp(r11);
1091 }
1092
1093 // ---------------------------------------------------------------
1094 AdapterHandlerEntry* SharedRuntime::generate_i2c2i_adapters(MacroAssembler *masm,
1095 int comp_args_on_stack,
1096 const GrowableArray<SigEntry>& sig,
1097 const VMRegPair *regs,
1098 AdapterFingerPrint* fingerprint,
1099 AdapterBlob*& new_adapter) {
1100 address i2c_entry = __ pc();
1101
1102 gen_i2c_adapter(masm, comp_args_on_stack, sig, regs);
1103
1104 // -------------------------------------------------------------------------
1105 // Generate a C2I adapter. On entry we know rbx holds the Method* during calls
1106 // to the interpreter. The args start out packed in the compiled layout. They
1107 // need to be unpacked into the interpreter layout. This will almost always
1108 // require some stack space. We grow the current (compiled) stack, then repack
1109 // the args. We finally end in a jump to the generic interpreter entry point.
1110 // On exit from the interpreter, the interpreter will restore our SP (lest the
1111 // compiled code, which relys solely on SP and not RBP, get sick).
1112
1113 address c2i_unverified_entry = __ pc();
1114 Label skip_fixup;
1115 Label ok;
1116
1117 Register holder = rax;
1118 Register receiver = j_rarg0;
1119 Register temp = rbx;
1120
1121 {
1122 __ load_klass(temp, receiver);
1123 __ cmpptr(temp, Address(holder, CompiledICHolder::holder_klass_offset()));
1124 __ movptr(rbx, Address(holder, CompiledICHolder::holder_method_offset()));
1125 __ jcc(Assembler::equal, ok);
1126 __ jump(RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
1127
1128 __ bind(ok);
1129 // Method might have been compiled since the call site was patched to
1130 // interpreted if that is the case treat it as a miss so we can get
1131 // the call site corrected.
1132 __ cmpptr(Address(rbx, in_bytes(Method::code_offset())), (int32_t)NULL_WORD);
1133 __ jcc(Assembler::equal, skip_fixup);
1134 __ jump(RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
1135 }
1136
1137 address c2i_entry = __ pc();
1138
1139 OopMapSet* oop_maps = NULL;
1140 int frame_complete = CodeOffsets::frame_never_safe;
1141 int frame_size_in_words = 0;
1142 gen_c2i_adapter(masm, sig, regs, skip_fixup, i2c_entry, oop_maps, frame_complete, frame_size_in_words);
1143
1144 __ flush();
1145 new_adapter = AdapterBlob::create(masm->code(), frame_complete, frame_size_in_words, oop_maps);
1146 return AdapterHandlerLibrary::new_entry(fingerprint, i2c_entry, c2i_entry, c2i_unverified_entry);
1147 }
1148
1149 int SharedRuntime::c_calling_convention(const BasicType *sig_bt,
1150 VMRegPair *regs,
1151 VMRegPair *regs2,
1152 int total_args_passed) {
1153 assert(regs2 == NULL, "not needed on x86");
1154 // We return the amount of VMRegImpl stack slots we need to reserve for all
1155 // the arguments NOT counting out_preserve_stack_slots.
1156
1157 // NOTE: These arrays will have to change when c1 is ported
1158 #ifdef _WIN64
1159 static const Register INT_ArgReg[Argument::n_int_register_parameters_c] = {
1160 c_rarg0, c_rarg1, c_rarg2, c_rarg3
1161 };
1162 static const XMMRegister FP_ArgReg[Argument::n_float_register_parameters_c] = {
1163 c_farg0, c_farg1, c_farg2, c_farg3
1164 };
1165 #else
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