1 /*
2 * Copyright (c) 1997, 2020, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #ifndef SHARE_OPTO_MACHNODE_HPP
26 #define SHARE_OPTO_MACHNODE_HPP
27
28 #include "opto/callnode.hpp"
29 #include "opto/constantTable.hpp"
30 #include "opto/matcher.hpp"
31 #include "opto/multnode.hpp"
32 #include "opto/node.hpp"
33 #include "opto/regmask.hpp"
34
35 class BiasedLockingCounters;
36 class BufferBlob;
37 class CodeBuffer;
38 class JVMState;
39 class MachCallDynamicJavaNode;
40 class MachCallJavaNode;
41 class MachCallLeafNode;
42 class MachCallNode;
43 class MachCallRuntimeNode;
44 class MachCallStaticJavaNode;
45 class MachEpilogNode;
46 class MachIfNode;
47 class MachNullCheckNode;
48 class MachOper;
49 class MachProjNode;
50 class MachPrologNode;
51 class MachReturnNode;
52 class MachSafePointNode;
53 class MachSpillCopyNode;
54 class Matcher;
55 class PhaseRegAlloc;
56 class RegMask;
57 class RTMLockingCounters;
58 class State;
59
60 //---------------------------MachOper------------------------------------------
61 class MachOper : public ResourceObj {
62 public:
63 // Allocate right next to the MachNodes in the same arena
64 void *operator new(size_t x) throw() {
65 Compile* C = Compile::current();
66 return C->node_arena()->Amalloc_D(x);
67 }
68
69 // Opcode
70 virtual uint opcode() const = 0;
71
72 // Number of input edges.
73 // Generally at least 1
74 virtual uint num_edges() const { return 1; }
75 // Array of Register masks
76 virtual const RegMask *in_RegMask(int index) const;
77
78 // Methods to output the encoding of the operand
79
80 // Negate conditional branches. Error for non-branch Nodes
81 virtual void negate();
82
83 // Return the value requested
84 // result register lookup, corresponding to int_format
85 virtual int reg(PhaseRegAlloc *ra_, const Node *node) const;
86 // input register lookup, corresponding to ext_format
87 virtual int reg(PhaseRegAlloc *ra_, const Node *node, int idx) const;
88
89 // helpers for MacroAssembler generation from ADLC
90 Register as_Register(PhaseRegAlloc *ra_, const Node *node) const {
91 return ::as_Register(reg(ra_, node));
92 }
93 Register as_Register(PhaseRegAlloc *ra_, const Node *node, int idx) const {
94 return ::as_Register(reg(ra_, node, idx));
95 }
96 FloatRegister as_FloatRegister(PhaseRegAlloc *ra_, const Node *node) const {
97 return ::as_FloatRegister(reg(ra_, node));
98 }
99 FloatRegister as_FloatRegister(PhaseRegAlloc *ra_, const Node *node, int idx) const {
100 return ::as_FloatRegister(reg(ra_, node, idx));
101 }
102
103 #if defined(IA32) || defined(AMD64)
104 XMMRegister as_XMMRegister(PhaseRegAlloc *ra_, const Node *node) const {
105 return ::as_XMMRegister(reg(ra_, node));
106 }
107 XMMRegister as_XMMRegister(PhaseRegAlloc *ra_, const Node *node, int idx) const {
108 return ::as_XMMRegister(reg(ra_, node, idx));
109 }
110 #endif
111 // CondRegister reg converter
112 #if defined(PPC64)
113 ConditionRegister as_ConditionRegister(PhaseRegAlloc *ra_, const Node *node) const {
114 return ::as_ConditionRegister(reg(ra_, node));
115 }
116 ConditionRegister as_ConditionRegister(PhaseRegAlloc *ra_, const Node *node, int idx) const {
117 return ::as_ConditionRegister(reg(ra_, node, idx));
118 }
119 VectorRegister as_VectorRegister(PhaseRegAlloc *ra_, const Node *node) const {
120 return ::as_VectorRegister(reg(ra_, node));
121 }
122 VectorRegister as_VectorRegister(PhaseRegAlloc *ra_, const Node *node, int idx) const {
123 return ::as_VectorRegister(reg(ra_, node, idx));
124 }
125 VectorSRegister as_VectorSRegister(PhaseRegAlloc *ra_, const Node *node) const {
126 return ::as_VectorSRegister(reg(ra_, node));
127 }
128 VectorSRegister as_VectorSRegister(PhaseRegAlloc *ra_, const Node *node, int idx) const {
129 return ::as_VectorSRegister(reg(ra_, node, idx));
130 }
131 #endif
132
133 virtual intptr_t constant() const;
134 virtual relocInfo::relocType constant_reloc() const;
135 virtual jdouble constantD() const;
136 virtual jfloat constantF() const;
137 virtual jlong constantL() const;
138 virtual TypeOopPtr *oop() const;
139 virtual int ccode() const;
140 // A zero, default, indicates this value is not needed.
141 // May need to lookup the base register, as done in int_ and ext_format
142 virtual int base (PhaseRegAlloc *ra_, const Node *node, int idx) const;
143 virtual int index(PhaseRegAlloc *ra_, const Node *node, int idx) const;
144 virtual int scale() const;
145 // Parameters needed to support MEMORY_INTERFACE access to stackSlot
146 virtual int disp (PhaseRegAlloc *ra_, const Node *node, int idx) const;
147 // Check for PC-Relative displacement
148 virtual relocInfo::relocType disp_reloc() const;
149 virtual int constant_disp() const; // usu. 0, may return Type::OffsetBot
150 virtual int base_position() const; // base edge position, or -1
151 virtual int index_position() const; // index edge position, or -1
152
153 // Access the TypeKlassPtr of operands with a base==RegI and disp==RegP
154 // Only returns non-null value for i486.ad's indOffset32X
155 virtual const TypePtr *disp_as_type() const { return NULL; }
156
157 // Return the label
158 virtual Label *label() const;
159
160 // Return the method's address
161 virtual intptr_t method() const;
162
163 // Hash and compare over operands are currently identical
164 virtual uint hash() const;
165 virtual bool cmp( const MachOper &oper ) const;
166
167 // Virtual clone, since I do not know how big the MachOper is.
168 virtual MachOper *clone() const = 0;
169
170 // Return ideal Type from simple operands. Fail for complex operands.
171 virtual const Type *type() const;
172
173 // Set an integer offset if we have one, or error otherwise
174 virtual void set_con( jint c0 ) { ShouldNotReachHere(); }
175
176 #ifndef PRODUCT
177 // Return name of operand
178 virtual const char *Name() const { return "???";}
179
180 // Methods to output the text version of the operand
181 virtual void int_format(PhaseRegAlloc *,const MachNode *node, outputStream *st) const = 0;
182 virtual void ext_format(PhaseRegAlloc *,const MachNode *node,int idx, outputStream *st) const=0;
183
184 virtual void dump_spec(outputStream *st) const; // Print per-operand info
185
186 // Check whether o is a valid oper.
187 static bool notAnOper(const MachOper *o) {
188 if (o == NULL) return true;
189 if (((intptr_t)o & 1) != 0) return true;
190 if (*(address*)o == badAddress) return true; // kill by Node::destruct
191 return false;
192 }
193 #endif // !PRODUCT
194 };
195
196 //------------------------------MachNode---------------------------------------
197 // Base type for all machine specific nodes. All node classes generated by the
198 // ADLC inherit from this class.
199 class MachNode : public Node {
200 public:
201 MachNode() : Node((uint)0), _barrier(0), _num_opnds(0), _opnds(NULL) {
202 init_class_id(Class_Mach);
203 }
204 // Required boilerplate
205 virtual uint size_of() const { return sizeof(MachNode); }
206 virtual int Opcode() const; // Always equal to MachNode
207 virtual uint rule() const = 0; // Machine-specific opcode
208 // Number of inputs which come before the first operand.
209 // Generally at least 1, to skip the Control input
210 virtual uint oper_input_base() const { return 1; }
211 // Position of constant base node in node's inputs. -1 if
212 // no constant base node input.
213 virtual uint mach_constant_base_node_input() const { return (uint)-1; }
214
215 uint8_t barrier_data() const { return _barrier; }
216 void set_barrier_data(uint data) { _barrier = data; }
217
218 // Copy inputs and operands to new node of instruction.
219 // Called from cisc_version() and short_branch_version().
220 // !!!! The method's body is defined in ad_<arch>.cpp file.
221 void fill_new_machnode(MachNode *n) const;
222
223 // Return an equivalent instruction using memory for cisc_operand position
224 virtual MachNode *cisc_version(int offset);
225 // Modify this instruction's register mask to use stack version for cisc_operand
226 virtual void use_cisc_RegMask();
227
228 // Support for short branches
229 bool may_be_short_branch() const { return (flags() & Flag_may_be_short_branch) != 0; }
230
231 // Avoid back to back some instructions on some CPUs.
232 enum AvoidBackToBackFlag { AVOID_NONE = 0,
233 AVOID_BEFORE = Flag_avoid_back_to_back_before,
234 AVOID_AFTER = Flag_avoid_back_to_back_after,
235 AVOID_BEFORE_AND_AFTER = AVOID_BEFORE | AVOID_AFTER };
236
237 bool avoid_back_to_back(AvoidBackToBackFlag flag_value) const {
238 return (flags() & flag_value) == flag_value;
239 }
240
241 // instruction implemented with a call
242 bool has_call() const { return (flags() & Flag_has_call) != 0; }
243
244 // First index in _in[] corresponding to operand, or -1 if there is none
245 int operand_index(uint operand) const;
246 int operand_index(const MachOper *oper) const;
247 int operand_index(Node* m) const;
248
249 // Register class input is expected in
250 virtual const RegMask &in_RegMask(uint) const;
251
252 // cisc-spillable instructions redefine for use by in_RegMask
253 virtual const RegMask *cisc_RegMask() const { return NULL; }
254
255 // If this instruction is a 2-address instruction, then return the
256 // index of the input which must match the output. Not nessecary
257 // for instructions which bind the input and output register to the
258 // same singleton regiser (e.g., Intel IDIV which binds AX to be
259 // both an input and an output). It is nessecary when the input and
260 // output have choices - but they must use the same choice.
261 virtual uint two_adr( ) const { return 0; }
262
263 // The GC might require some barrier metadata for machine code emission.
264 uint8_t _barrier;
265
266 // Array of complex operand pointers. Each corresponds to zero or
267 // more leafs. Must be set by MachNode constructor to point to an
268 // internal array of MachOpers. The MachOper array is sized by
269 // specific MachNodes described in the ADL.
270 uint _num_opnds;
271 MachOper **_opnds;
272 uint num_opnds() const { return _num_opnds; }
273
274 // Emit bytes into cbuf
275 virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const;
276 // Expand node after register allocation.
277 // Node is replaced by several nodes in the postalloc expand phase.
278 // Corresponding methods are generated for nodes if they specify
279 // postalloc_expand. See block.cpp for more documentation.
280 virtual bool requires_postalloc_expand() const { return false; }
281 virtual void postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_);
282 // Size of instruction in bytes
283 virtual uint size(PhaseRegAlloc *ra_) const;
284 // Helper function that computes size by emitting code
285 virtual uint emit_size(PhaseRegAlloc *ra_) const;
286
287 // Return the alignment required (in units of relocInfo::addr_unit())
288 // for this instruction (must be a power of 2)
289 int pd_alignment_required() const;
290 virtual int alignment_required() const { return pd_alignment_required(); }
291
292 // Return the padding (in bytes) to be emitted before this
293 // instruction to properly align it.
294 virtual int compute_padding(int current_offset) const;
295
296 // Return number of relocatable values contained in this instruction
297 virtual int reloc() const { return 0; }
298
299 // Return number of words used for double constants in this instruction
300 virtual int ins_num_consts() const { return 0; }
301
302 // Hash and compare over operands. Used to do GVN on machine Nodes.
303 virtual uint hash() const;
304 virtual bool cmp( const Node &n ) const;
305
306 // Expand method for MachNode, replaces nodes representing pseudo
307 // instructions with a set of nodes which represent real machine
308 // instructions and compute the same value.
309 virtual MachNode *Expand( State *, Node_List &proj_list, Node* mem ) { return this; }
310
311 // Bottom_type call; value comes from operand0
312 virtual const class Type *bottom_type() const { return _opnds[0]->type(); }
313 virtual uint ideal_reg() const {
314 const Type *t = _opnds[0]->type();
315 if (t == TypeInt::CC) {
316 return Op_RegFlags;
317 } else {
318 return t->ideal_reg();
319 }
320 }
321
322 // If this is a memory op, return the base pointer and fixed offset.
323 // If there are no such, return NULL. If there are multiple addresses
324 // or the address is indeterminate (rare cases) then return (Node*)-1,
325 // which serves as node bottom.
326 // If the offset is not statically determined, set it to Type::OffsetBot.
327 // This method is free to ignore stack slots if that helps.
328 #define TYPE_PTR_SENTINAL ((const TypePtr*)-1)
329 // Passing TYPE_PTR_SENTINAL as adr_type asks for computation of the adr_type if possible
330 const Node* get_base_and_disp(intptr_t &offset, const TypePtr* &adr_type) const;
331
332 // Helper for get_base_and_disp: find the base and index input nodes.
333 // Returns the MachOper as determined by memory_operand(), for use, if
334 // needed by the caller. If (MachOper *)-1 is returned, base and index
335 // are set to NodeSentinel. If (MachOper *) NULL is returned, base and
336 // index are set to NULL.
337 const MachOper* memory_inputs(Node* &base, Node* &index) const;
338
339 // Helper for memory_inputs: Which operand carries the necessary info?
340 // By default, returns NULL, which means there is no such operand.
341 // If it returns (MachOper*)-1, this means there are multiple memories.
342 virtual const MachOper* memory_operand() const { return NULL; }
343
344 // Call "get_base_and_disp" to decide which category of memory is used here.
345 virtual const class TypePtr *adr_type() const;
346
347 // Apply peephole rule(s) to this instruction
348 virtual MachNode *peephole(Block *block, int block_index, PhaseRegAlloc *ra_, int &deleted);
349
350 // Top-level ideal Opcode matched
351 virtual int ideal_Opcode() const { return Op_Node; }
352
353 // Adds the label for the case
354 virtual void add_case_label( int switch_val, Label* blockLabel);
355
356 // Set the absolute address for methods
357 virtual void method_set( intptr_t addr );
358
359 // Should we clone rather than spill this instruction?
360 bool rematerialize() const;
361
362 // Get the pipeline info
363 static const Pipeline *pipeline_class();
364 virtual const Pipeline *pipeline() const;
365
366 // Returns true if this node is a check that can be implemented with a trap.
367 virtual bool is_TrapBasedCheckNode() const { return false; }
368
369 #ifndef PRODUCT
370 virtual const char *Name() const = 0; // Machine-specific name
371 virtual void dump_spec(outputStream *st) const; // Print per-node info
372 void dump_format(PhaseRegAlloc *ra, outputStream *st) const; // access to virtual
373 #endif
374 };
375
376 //------------------------------MachIdealNode----------------------------
377 // Machine specific versions of nodes that must be defined by user.
378 // These are not converted by matcher from ideal nodes to machine nodes
379 // but are inserted into the code by the compiler.
380 class MachIdealNode : public MachNode {
381 public:
382 MachIdealNode( ) {}
383
384 // Define the following defaults for non-matched machine nodes
385 virtual uint oper_input_base() const { return 0; }
386 virtual uint rule() const { return 9999999; }
387 virtual const class Type *bottom_type() const { return _opnds == NULL ? Type::CONTROL : MachNode::bottom_type(); }
388 };
389
390 //------------------------------MachTypeNode----------------------------
391 // Machine Nodes that need to retain a known Type.
392 class MachTypeNode : public MachNode {
393 virtual uint size_of() const { return sizeof(*this); } // Size is bigger
394 public:
395 MachTypeNode( ) {}
396 const Type *_bottom_type;
397
398 virtual const class Type *bottom_type() const { return _bottom_type; }
399 #ifndef PRODUCT
400 virtual void dump_spec(outputStream *st) const;
401 #endif
402 };
403
404 //------------------------------MachBreakpointNode----------------------------
405 // Machine breakpoint or interrupt Node
406 class MachBreakpointNode : public MachIdealNode {
407 public:
408 MachBreakpointNode( ) {}
409 virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const;
410 virtual uint size(PhaseRegAlloc *ra_) const;
411
412 #ifndef PRODUCT
413 virtual const char *Name() const { return "Breakpoint"; }
414 virtual void format( PhaseRegAlloc *, outputStream *st ) const;
415 #endif
416 };
417
418 //------------------------------MachConstantBaseNode--------------------------
419 // Machine node that represents the base address of the constant table.
420 class MachConstantBaseNode : public MachIdealNode {
421 public:
422 static const RegMask& _out_RegMask; // We need the out_RegMask statically in MachConstantNode::in_RegMask().
423
424 public:
425 MachConstantBaseNode() : MachIdealNode() {
426 init_class_id(Class_MachConstantBase);
427 }
428 virtual const class Type* bottom_type() const { return TypeRawPtr::NOTNULL; }
429 virtual uint ideal_reg() const { return Op_RegP; }
430 virtual uint oper_input_base() const { return 1; }
431
432 virtual bool requires_postalloc_expand() const;
433 virtual void postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_);
434
435 virtual void emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const;
436 virtual uint size(PhaseRegAlloc* ra_) const;
437 virtual bool pinned() const { return UseRDPCForConstantTableBase; }
438
439 static const RegMask& static_out_RegMask() { return _out_RegMask; }
440 virtual const RegMask& out_RegMask() const { return static_out_RegMask(); }
441
442 #ifndef PRODUCT
443 virtual const char* Name() const { return "MachConstantBaseNode"; }
444 virtual void format(PhaseRegAlloc*, outputStream* st) const;
445 #endif
446 };
447
448 //------------------------------MachConstantNode-------------------------------
449 // Machine node that holds a constant which is stored in the constant table.
450 class MachConstantNode : public MachTypeNode {
451 protected:
452 ConstantTable::Constant _constant; // This node's constant.
453
454 public:
455 MachConstantNode() : MachTypeNode() {
456 init_class_id(Class_MachConstant);
457 }
458
459 virtual void eval_constant(Compile* C) {
460 #ifdef ASSERT
461 tty->print("missing MachConstantNode eval_constant function: ");
462 dump();
463 #endif
464 ShouldNotCallThis();
465 }
466
467 virtual const RegMask &in_RegMask(uint idx) const {
468 if (idx == mach_constant_base_node_input())
469 return MachConstantBaseNode::static_out_RegMask();
470 return MachNode::in_RegMask(idx);
471 }
472
473 // Input edge of MachConstantBaseNode.
474 virtual uint mach_constant_base_node_input() const { return req() - 1; }
475
476 int constant_offset();
477 int constant_offset() const { return ((MachConstantNode*) this)->constant_offset(); }
478 // Unchecked version to avoid assertions in debug output.
479 int constant_offset_unchecked() const;
480 };
481
482 //------------------------------MachUEPNode-----------------------------------
483 // Machine Unvalidated Entry Point Node
484 class MachUEPNode : public MachIdealNode {
485 public:
486 MachUEPNode( ) {}
487 virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const;
488 virtual uint size(PhaseRegAlloc *ra_) const;
489
490 #ifndef PRODUCT
491 virtual const char *Name() const { return "Unvalidated-Entry-Point"; }
492 virtual void format( PhaseRegAlloc *, outputStream *st ) const;
493 #endif
494 };
495
496 //------------------------------MachPrologNode--------------------------------
497 // Machine function Prolog Node
498 class MachPrologNode : public MachIdealNode {
499 public:
500 MachPrologNode( ) {}
501 virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const;
502 virtual uint size(PhaseRegAlloc *ra_) const;
503 virtual int reloc() const;
504
505 #ifndef PRODUCT
506 virtual const char *Name() const { return "Prolog"; }
507 virtual void format( PhaseRegAlloc *, outputStream *st ) const;
508 #endif
509 };
510
511 //------------------------------MachEpilogNode--------------------------------
512 // Machine function Epilog Node
513 class MachEpilogNode : public MachIdealNode {
514 public:
515 MachEpilogNode(bool do_poll = false) : _do_polling(do_poll) {}
516 virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const;
517 virtual uint size(PhaseRegAlloc *ra_) const;
518 virtual int reloc() const;
519 virtual const Pipeline *pipeline() const;
520
521 private:
522 bool _do_polling;
523
524 public:
525 bool do_polling() const { return _do_polling; }
526
527 #ifndef PRODUCT
528 virtual const char *Name() const { return "Epilog"; }
529 virtual void format( PhaseRegAlloc *, outputStream *st ) const;
530 #endif
531 };
532
533 //------------------------------MachNopNode-----------------------------------
534 // Machine function Nop Node
535 class MachNopNode : public MachIdealNode {
536 private:
537 int _count;
538 public:
539 MachNopNode( ) : _count(1) {}
540 MachNopNode( int count ) : _count(count) {}
541 virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const;
542 virtual uint size(PhaseRegAlloc *ra_) const;
543
544 virtual const class Type *bottom_type() const { return Type::CONTROL; }
545
546 virtual int ideal_Opcode() const { return Op_Con; } // bogus; see output.cpp
547 virtual const Pipeline *pipeline() const;
548 #ifndef PRODUCT
549 virtual const char *Name() const { return "Nop"; }
550 virtual void format( PhaseRegAlloc *, outputStream *st ) const;
551 virtual void dump_spec(outputStream *st) const { } // No per-operand info
552 #endif
553 };
554
555 //------------------------------MachSpillCopyNode------------------------------
556 // Machine SpillCopy Node. Copies 1 or 2 words from any location to any
557 // location (stack or register).
558 class MachSpillCopyNode : public MachIdealNode {
559 public:
560 enum SpillType {
561 TwoAddress, // Inserted when coalescing of a two-address-instruction node and its input fails
562 PhiInput, // Inserted when coalescing of a phi node and its input fails
563 DebugUse, // Inserted as debug info spills to safepoints in non-frequent blocks
564 LoopPhiInput, // Pre-split compares of loop-phis
565 Definition, // An lrg marked as spilled will be spilled to memory right after its definition,
566 // if in high pressure region or the lrg is bound
567 RegToReg, // A register to register move
568 RegToMem, // A register to memory move
569 MemToReg, // A memory to register move
570 PhiLocationDifferToInputLocation, // When coalescing phi nodes in PhaseChaitin::Split(), a move spill is inserted if
571 // the phi and its input resides at different locations (i.e. reg or mem)
572 BasePointerToMem, // Spill base pointer to memory at safepoint
573 InputToRematerialization, // When rematerializing a node we stretch the inputs live ranges, and they might be
574 // stretched beyond a new definition point, therefore we split out new copies instead
575 CallUse, // Spill use at a call
576 Bound // An lrg marked as spill that is bound and needs to be spilled at a use
577 };
578 private:
579 const RegMask *_in; // RegMask for input
580 const RegMask *_out; // RegMask for output
581 const Type *_type;
582 const SpillType _spill_type;
583 public:
584 MachSpillCopyNode(SpillType spill_type, Node *n, const RegMask &in, const RegMask &out ) :
585 MachIdealNode(), _in(&in), _out(&out), _type(n->bottom_type()), _spill_type(spill_type) {
586 init_class_id(Class_MachSpillCopy);
587 init_flags(Flag_is_Copy);
588 add_req(NULL);
589 add_req(n);
590 }
591 virtual uint size_of() const { return sizeof(*this); }
592 void set_out_RegMask(const RegMask &out) { _out = &out; }
593 void set_in_RegMask(const RegMask &in) { _in = ∈ }
594 virtual const RegMask &out_RegMask() const { return *_out; }
595 virtual const RegMask &in_RegMask(uint) const { return *_in; }
596 virtual const class Type *bottom_type() const { return _type; }
597 virtual uint ideal_reg() const { return _type->ideal_reg(); }
598 virtual uint oper_input_base() const { return 1; }
599 uint implementation( CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, outputStream* st ) const;
600
601 virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const;
602 virtual uint size(PhaseRegAlloc *ra_) const;
603
604
605 #ifndef PRODUCT
606 static const char *spill_type(SpillType st) {
607 switch (st) {
608 case TwoAddress:
609 return "TwoAddressSpillCopy";
610 case PhiInput:
611 return "PhiInputSpillCopy";
612 case DebugUse:
613 return "DebugUseSpillCopy";
614 case LoopPhiInput:
615 return "LoopPhiInputSpillCopy";
616 case Definition:
617 return "DefinitionSpillCopy";
618 case RegToReg:
619 return "RegToRegSpillCopy";
620 case RegToMem:
621 return "RegToMemSpillCopy";
622 case MemToReg:
623 return "MemToRegSpillCopy";
624 case PhiLocationDifferToInputLocation:
625 return "PhiLocationDifferToInputLocationSpillCopy";
626 case BasePointerToMem:
627 return "BasePointerToMemSpillCopy";
628 case InputToRematerialization:
629 return "InputToRematerializationSpillCopy";
630 case CallUse:
631 return "CallUseSpillCopy";
632 case Bound:
633 return "BoundSpillCopy";
634 default:
635 assert(false, "Must have valid spill type");
636 return "MachSpillCopy";
637 }
638 }
639
640 virtual const char *Name() const {
641 return spill_type(_spill_type);
642 }
643
644 virtual void format( PhaseRegAlloc *, outputStream *st ) const;
645 #endif
646 };
647
648 // MachMergeNode is similar to a PhiNode in a sense it merges multiple values,
649 // however it doesn't have a control input and is more like a MergeMem.
650 // It is inserted after the register allocation is done to ensure that nodes use single
651 // definition of a multidef lrg in a block.
652 class MachMergeNode : public MachIdealNode {
653 public:
654 MachMergeNode(Node *n1) {
655 init_class_id(Class_MachMerge);
656 add_req(NULL);
657 add_req(n1);
658 }
659 virtual const RegMask &out_RegMask() const { return in(1)->out_RegMask(); }
660 virtual const RegMask &in_RegMask(uint idx) const { return in(1)->in_RegMask(idx); }
661 virtual const class Type *bottom_type() const { return in(1)->bottom_type(); }
662 virtual uint ideal_reg() const { return bottom_type()->ideal_reg(); }
663 virtual uint oper_input_base() const { return 1; }
664 virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { }
665 virtual uint size(PhaseRegAlloc *ra_) const { return 0; }
666 #ifndef PRODUCT
667 virtual const char *Name() const { return "MachMerge"; }
668 #endif
669 };
670
671 //------------------------------MachBranchNode--------------------------------
672 // Abstract machine branch Node
673 class MachBranchNode : public MachIdealNode {
674 public:
675 MachBranchNode() : MachIdealNode() {
676 init_class_id(Class_MachBranch);
677 }
678 virtual void label_set(Label* label, uint block_num) = 0;
679 virtual void save_label(Label** label, uint* block_num) = 0;
680
681 // Support for short branches
682 virtual MachNode *short_branch_version() { return NULL; }
683
684 virtual bool pinned() const { return true; };
685 };
686
687 //------------------------------MachNullChkNode--------------------------------
688 // Machine-dependent null-pointer-check Node. Points a real MachNode that is
689 // also some kind of memory op. Turns the indicated MachNode into a
690 // conditional branch with good latency on the ptr-not-null path and awful
691 // latency on the pointer-is-null path.
692
693 class MachNullCheckNode : public MachBranchNode {
694 public:
695 const uint _vidx; // Index of memop being tested
696 MachNullCheckNode( Node *ctrl, Node *memop, uint vidx ) : MachBranchNode(), _vidx(vidx) {
697 init_class_id(Class_MachNullCheck);
698 add_req(ctrl);
699 add_req(memop);
700 }
701 virtual uint size_of() const { return sizeof(*this); }
702
703 virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const;
704 virtual void label_set(Label* label, uint block_num);
705 virtual void save_label(Label** label, uint* block_num);
706 virtual void negate() { }
707 virtual const class Type *bottom_type() const { return TypeTuple::IFBOTH; }
708 virtual uint ideal_reg() const { return NotAMachineReg; }
709 virtual const RegMask &in_RegMask(uint) const;
710 virtual const RegMask &out_RegMask() const { return RegMask::Empty; }
711 #ifndef PRODUCT
712 virtual const char *Name() const { return "NullCheck"; }
713 virtual void format( PhaseRegAlloc *, outputStream *st ) const;
714 #endif
715 };
716
717 //------------------------------MachProjNode----------------------------------
718 // Machine-dependent Ideal projections (how is that for an oxymoron). Really
719 // just MachNodes made by the Ideal world that replicate simple projections
720 // but with machine-dependent input & output register masks. Generally
721 // produced as part of calling conventions. Normally I make MachNodes as part
722 // of the Matcher process, but the Matcher is ill suited to issues involving
723 // frame handling, so frame handling is all done in the Ideal world with
724 // occasional callbacks to the machine model for important info.
725 class MachProjNode : public ProjNode {
726 public:
727 MachProjNode( Node *multi, uint con, const RegMask &out, uint ideal_reg ) : ProjNode(multi,con), _rout(out), _ideal_reg(ideal_reg) {
728 init_class_id(Class_MachProj);
729 }
730 RegMask _rout;
731 const uint _ideal_reg;
732 enum projType {
733 unmatched_proj = 0, // Projs for Control, I/O, memory not matched
734 fat_proj = 999 // Projs killing many regs, defined by _rout
735 };
736 virtual int Opcode() const;
737 virtual const Type *bottom_type() const;
738 virtual const TypePtr *adr_type() const;
739 virtual const RegMask &in_RegMask(uint) const { return RegMask::Empty; }
740 virtual const RegMask &out_RegMask() const { return _rout; }
741 virtual uint ideal_reg() const { return _ideal_reg; }
742 // Need size_of() for virtual ProjNode::clone()
743 virtual uint size_of() const { return sizeof(MachProjNode); }
744 #ifndef PRODUCT
745 virtual void dump_spec(outputStream *st) const;
746 #endif
747 };
748
749 //------------------------------MachIfNode-------------------------------------
750 // Machine-specific versions of IfNodes
751 class MachIfNode : public MachBranchNode {
752 virtual uint size_of() const { return sizeof(*this); } // Size is bigger
753 public:
754 float _prob; // Probability branch goes either way
755 float _fcnt; // Frequency counter
756 MachIfNode() : MachBranchNode() {
757 init_class_id(Class_MachIf);
758 }
759 // Negate conditional branches.
760 virtual void negate() = 0;
761 #ifndef PRODUCT
762 virtual void dump_spec(outputStream *st) const;
763 #endif
764 };
765
766 //------------------------------MachJumpNode-----------------------------------
767 // Machine-specific versions of JumpNodes
768 class MachJumpNode : public MachConstantNode {
769 public:
770 float* _probs;
771 MachJumpNode() : MachConstantNode() {
772 init_class_id(Class_MachJump);
773 }
774 };
775
776 //------------------------------MachGotoNode-----------------------------------
777 // Machine-specific versions of GotoNodes
778 class MachGotoNode : public MachBranchNode {
779 public:
780 MachGotoNode() : MachBranchNode() {
781 init_class_id(Class_MachGoto);
782 }
783 };
784
785 //------------------------------MachFastLockNode-------------------------------------
786 // Machine-specific versions of FastLockNodes
787 class MachFastLockNode : public MachNode {
788 virtual uint size_of() const { return sizeof(*this); } // Size is bigger
789 public:
790 BiasedLockingCounters* _counters;
791 RTMLockingCounters* _rtm_counters; // RTM lock counters for inflated locks
792 RTMLockingCounters* _stack_rtm_counters; // RTM lock counters for stack locks
793 MachFastLockNode() : MachNode() {}
794 };
795
796 //------------------------------MachReturnNode--------------------------------
797 // Machine-specific versions of subroutine returns
798 class MachReturnNode : public MachNode {
799 virtual uint size_of() const; // Size is bigger
800 public:
801 RegMask *_in_rms; // Input register masks, set during allocation
802 ReallocMark _nesting; // assertion check for reallocations
803 const TypePtr* _adr_type; // memory effects of call or return
804 MachReturnNode() : MachNode() {
805 init_class_id(Class_MachReturn);
806 _adr_type = TypePtr::BOTTOM; // the default: all of memory
807 }
808
809 void set_adr_type(const TypePtr* atp) { _adr_type = atp; }
810
811 virtual const RegMask &in_RegMask(uint) const;
812 virtual bool pinned() const { return true; };
813 virtual const TypePtr *adr_type() const;
814 };
815
816 //------------------------------MachSafePointNode-----------------------------
817 // Machine-specific versions of safepoints
818 class MachSafePointNode : public MachReturnNode {
819 public:
820 OopMap* _oop_map; // Array of OopMap info (8-bit char) for GC
821 JVMState* _jvms; // Pointer to list of JVM State Objects
822 uint _jvmadj; // Extra delta to jvms indexes (mach. args)
823 OopMap* oop_map() const { return _oop_map; }
824 void set_oop_map(OopMap* om) { _oop_map = om; }
825
826 MachSafePointNode() : MachReturnNode(), _oop_map(NULL), _jvms(NULL), _jvmadj(0) {
827 init_class_id(Class_MachSafePoint);
828 }
829
830 virtual JVMState* jvms() const { return _jvms; }
831 void set_jvms(JVMState* s) {
832 _jvms = s;
833 }
834 virtual const Type *bottom_type() const;
835
836 virtual const RegMask &in_RegMask(uint) const;
837
838 // Functionality from old debug nodes
839 Node *returnadr() const { return in(TypeFunc::ReturnAdr); }
840 Node *frameptr () const { return in(TypeFunc::FramePtr); }
841
842 Node *local(const JVMState* jvms, uint idx) const {
843 assert(verify_jvms(jvms), "jvms must match");
844 return in(_jvmadj + jvms->locoff() + idx);
845 }
846 Node *stack(const JVMState* jvms, uint idx) const {
847 assert(verify_jvms(jvms), "jvms must match");
848 return in(_jvmadj + jvms->stkoff() + idx);
849 }
850 Node *monitor_obj(const JVMState* jvms, uint idx) const {
851 assert(verify_jvms(jvms), "jvms must match");
852 return in(_jvmadj + jvms->monitor_obj_offset(idx));
853 }
854 Node *monitor_box(const JVMState* jvms, uint idx) const {
855 assert(verify_jvms(jvms), "jvms must match");
856 return in(_jvmadj + jvms->monitor_box_offset(idx));
857 }
858 void set_local(const JVMState* jvms, uint idx, Node *c) {
859 assert(verify_jvms(jvms), "jvms must match");
860 set_req(_jvmadj + jvms->locoff() + idx, c);
861 }
862 void set_stack(const JVMState* jvms, uint idx, Node *c) {
863 assert(verify_jvms(jvms), "jvms must match");
864 set_req(_jvmadj + jvms->stkoff() + idx, c);
865 }
866 void set_monitor(const JVMState* jvms, uint idx, Node *c) {
867 assert(verify_jvms(jvms), "jvms must match");
868 set_req(_jvmadj + jvms->monoff() + idx, c);
869 }
870 };
871
872 //------------------------------MachCallNode----------------------------------
873 // Machine-specific versions of subroutine calls
874 class MachCallNode : public MachSafePointNode {
875 protected:
876 virtual uint hash() const { return NO_HASH; } // CFG nodes do not hash
877 virtual bool cmp( const Node &n ) const;
878 virtual uint size_of() const = 0; // Size is bigger
879 public:
880 const TypeFunc *_tf; // Function type
881 address _entry_point; // Address of the method being called
882 float _cnt; // Estimate of number of times called
883 uint _argsize; // Size of argument block on stack
884
885 const TypeFunc* tf() const { return _tf; }
886 const address entry_point() const { return _entry_point; }
887 const float cnt() const { return _cnt; }
888 uint argsize() const { return _argsize; }
889
890 void set_tf(const TypeFunc* tf) { _tf = tf; }
891 void set_entry_point(address p) { _entry_point = p; }
892 void set_cnt(float c) { _cnt = c; }
893 void set_argsize(int s) { _argsize = s; }
894
895 MachCallNode() : MachSafePointNode() {
896 init_class_id(Class_MachCall);
897 }
898
899 virtual const Type *bottom_type() const;
900 virtual bool pinned() const { return false; }
901 virtual const Type* Value(PhaseGVN* phase) const;
902 virtual const RegMask &in_RegMask(uint) const;
903 virtual int ret_addr_offset() { return 0; }
904
905 bool returns_long() const { return tf()->return_type() == T_LONG; }
906 bool return_value_is_used() const;
907
908 // Similar to cousin class CallNode::returns_pointer
909 bool returns_pointer() const;
910
911 #ifndef PRODUCT
912 virtual void dump_spec(outputStream *st) const;
913 #endif
914 };
915
916 //------------------------------MachCallJavaNode------------------------------
917 // "Base" class for machine-specific versions of subroutine calls
918 class MachCallJavaNode : public MachCallNode {
919 protected:
920 virtual bool cmp( const Node &n ) const;
921 virtual uint size_of() const; // Size is bigger
922 public:
923 ciMethod* _method; // Method being direct called
924 bool _override_symbolic_info; // Override symbolic call site info from bytecode
925 int _bci; // Byte Code index of call byte code
926 bool _optimized_virtual; // Tells if node is a static call or an optimized virtual
927 bool _method_handle_invoke; // Tells if the call has to preserve SP
928 MachCallJavaNode() : MachCallNode(), _override_symbolic_info(false) {
929 init_class_id(Class_MachCallJava);
930 }
931
932 virtual const RegMask &in_RegMask(uint) const;
933
934 int resolved_method_index(CodeBuffer &cbuf) const {
935 if (_override_symbolic_info) {
936 // Attach corresponding Method* to the call site, so VM can use it during resolution
937 // instead of querying symbolic info from bytecode.
938 assert(_method != NULL, "method should be set");
939 assert(_method->constant_encoding()->is_method(), "should point to a Method");
940 return cbuf.oop_recorder()->find_index(_method->constant_encoding());
941 }
942 return 0; // Use symbolic info from bytecode (resolved_method == NULL).
943 }
944
945 #ifndef PRODUCT
946 virtual void dump_spec(outputStream *st) const;
947 #endif
948 };
949
950 //------------------------------MachCallStaticJavaNode------------------------
951 // Machine-specific versions of monomorphic subroutine calls
952 class MachCallStaticJavaNode : public MachCallJavaNode {
953 virtual bool cmp( const Node &n ) const;
954 virtual uint size_of() const; // Size is bigger
955 public:
956 const char *_name; // Runtime wrapper name
957 MachCallStaticJavaNode() : MachCallJavaNode() {
958 init_class_id(Class_MachCallStaticJava);
959 }
960
961 // If this is an uncommon trap, return the request code, else zero.
962 int uncommon_trap_request() const;
963
964 virtual int ret_addr_offset();
965 #ifndef PRODUCT
966 virtual void dump_spec(outputStream *st) const;
967 void dump_trap_args(outputStream *st) const;
968 #endif
969 };
970
971 //------------------------------MachCallDynamicJavaNode------------------------
972 // Machine-specific versions of possibly megamorphic subroutine calls
973 class MachCallDynamicJavaNode : public MachCallJavaNode {
974 public:
975 int _vtable_index;
976 MachCallDynamicJavaNode() : MachCallJavaNode() {
977 init_class_id(Class_MachCallDynamicJava);
978 DEBUG_ONLY(_vtable_index = -99); // throw an assert if uninitialized
979 }
980 virtual int ret_addr_offset();
981 #ifndef PRODUCT
982 virtual void dump_spec(outputStream *st) const;
983 #endif
984 };
985
986 //------------------------------MachCallRuntimeNode----------------------------
987 // Machine-specific versions of subroutine calls
988 class MachCallRuntimeNode : public MachCallNode {
989 virtual bool cmp( const Node &n ) const;
990 virtual uint size_of() const; // Size is bigger
991 public:
992 const char *_name; // Printable name, if _method is NULL
993 MachCallRuntimeNode() : MachCallNode() {
994 init_class_id(Class_MachCallRuntime);
995 }
996 virtual int ret_addr_offset();
997 #ifndef PRODUCT
998 virtual void dump_spec(outputStream *st) const;
999 #endif
1000 };
1001
1002 class MachCallLeafNode: public MachCallRuntimeNode {
1003 public:
1004 MachCallLeafNode() : MachCallRuntimeNode() {
1005 init_class_id(Class_MachCallLeaf);
1006 }
1007 };
1008
1009 //------------------------------MachHaltNode-----------------------------------
1010 // Machine-specific versions of halt nodes
1011 class MachHaltNode : public MachReturnNode {
1012 public:
1013 bool _reachable;
1014 const char* _halt_reason;
1015 virtual JVMState* jvms() const;
1016 bool is_reachable() const {
1017 return _reachable;
1018 }
1019 };
1020
1021 class MachMemBarNode : public MachNode {
1022 virtual uint size_of() const; // Size is bigger
1023 public:
1024 const TypePtr* _adr_type; // memory effects
1025 MachMemBarNode() : MachNode() {
1026 init_class_id(Class_MachMemBar);
1027 _adr_type = TypePtr::BOTTOM; // the default: all of memory
1028 }
1029
1030 void set_adr_type(const TypePtr* atp) { _adr_type = atp; }
1031 virtual const TypePtr *adr_type() const;
1032 };
1033
1034
1035 //------------------------------MachTempNode-----------------------------------
1036 // Node used by the adlc to construct inputs to represent temporary registers
1037 class MachTempNode : public MachNode {
1038 private:
1039 MachOper *_opnd_array[1];
1040
1041 public:
1042 virtual const RegMask &out_RegMask() const { return *_opnds[0]->in_RegMask(0); }
1043 virtual uint rule() const { return 9999999; }
1044 virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {}
1045
1046 MachTempNode(MachOper* oper) {
1047 init_class_id(Class_MachTemp);
1048 _num_opnds = 1;
1049 _opnds = _opnd_array;
1050 add_req(NULL);
1051 _opnds[0] = oper;
1052 }
1053 virtual uint size_of() const { return sizeof(MachTempNode); }
1054
1055 #ifndef PRODUCT
1056 virtual void format(PhaseRegAlloc *, outputStream *st ) const {}
1057 virtual const char *Name() const { return "MachTemp";}
1058 #endif
1059 };
1060
1061
1062
1063 //------------------------------labelOper--------------------------------------
1064 // Machine-independent version of label operand
1065 class labelOper : public MachOper {
1066 private:
1067 virtual uint num_edges() const { return 0; }
1068 public:
1069 // Supported for fixed size branches
1070 Label* _label; // Label for branch(es)
1071
1072 uint _block_num;
1073
1074 labelOper() : _label(0), _block_num(0) {}
1075
1076 labelOper(Label* label, uint block_num) : _label(label), _block_num(block_num) {}
1077
1078 labelOper(labelOper* l) : _label(l->_label) , _block_num(l->_block_num) {}
1079
1080 virtual MachOper *clone() const;
1081
1082 virtual Label *label() const { assert(_label != NULL, "need Label"); return _label; }
1083
1084 virtual uint opcode() const;
1085
1086 virtual uint hash() const;
1087 virtual bool cmp( const MachOper &oper ) const;
1088 #ifndef PRODUCT
1089 virtual const char *Name() const { return "Label";}
1090
1091 virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const;
1092 virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const { int_format( ra, node, st ); }
1093 #endif
1094 };
1095
1096
1097 //------------------------------methodOper--------------------------------------
1098 // Machine-independent version of method operand
1099 class methodOper : public MachOper {
1100 private:
1101 virtual uint num_edges() const { return 0; }
1102 public:
1103 intptr_t _method; // Address of method
1104 methodOper() : _method(0) {}
1105 methodOper(intptr_t method) : _method(method) {}
1106
1107 virtual MachOper *clone() const;
1108
1109 virtual intptr_t method() const { return _method; }
1110
1111 virtual uint opcode() const;
1112
1113 virtual uint hash() const;
1114 virtual bool cmp( const MachOper &oper ) const;
1115 #ifndef PRODUCT
1116 virtual const char *Name() const { return "Method";}
1117
1118 virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const;
1119 virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const { int_format( ra, node, st ); }
1120 #endif
1121 };
1122
1123 #endif // SHARE_OPTO_MACHNODE_HPP