src/cpu/aarch64/vm/assembler_aarch64.hpp

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 975 #undef INSN
 976 
 977   // System
 978   void system(int op0, int op1, int CRn, int CRm, int op2,
 979               Register rt = (Register)0b11111)
 980   {
 981     starti;
 982     f(0b11010101000, 31, 21);
 983     f(op0, 20, 19);
 984     f(op1, 18, 16);
 985     f(CRn, 15, 12);
 986     f(CRm, 11, 8);
 987     f(op2, 7, 5);
 988     rf(rt, 0);
 989   }
 990 
 991   void hint(int imm) {
 992     system(0b00, 0b011, 0b0010, imm, 0b000);
 993   }
 994 
 995   void nop() {

 996     hint(0);
 997   }
 998   // we only provide mrs and msr for the special purpose system
 999   // registers where op1 (instr[20:19]) == 11 and, (currently) only
1000   // use it for FPSR n.b msr has L (instr[21]) == 0 mrs has L == 1
1001 
1002   void msr(int op1, int CRn, int CRm, int op2, Register rt) {
1003     starti;
1004     f(0b1101010100011, 31, 19);
1005     f(op1, 18, 16);
1006     f(CRn, 15, 12);
1007     f(CRm, 11, 8);
1008     f(op2, 7, 5);
1009     // writing zr is ok
1010     zrf(rt, 0);
1011   }
1012 
1013   void mrs(int op1, int CRn, int CRm, int op2, Register rt) {
1014     starti;
1015     f(0b1101010100111, 31, 19);




 975 #undef INSN
 976 
 977   // System
 978   void system(int op0, int op1, int CRn, int CRm, int op2,
 979               Register rt = (Register)0b11111)
 980   {
 981     starti;
 982     f(0b11010101000, 31, 21);
 983     f(op0, 20, 19);
 984     f(op1, 18, 16);
 985     f(CRn, 15, 12);
 986     f(CRm, 11, 8);
 987     f(op2, 7, 5);
 988     rf(rt, 0);
 989   }
 990 
 991   void hint(int imm) {
 992     system(0b00, 0b011, 0b0010, imm, 0b000);
 993   }
 994 
 995   void nop(int count = 1) {
 996     for (int i = 0; i < count; i++)
 997       hint(0);
 998   }
 999   // we only provide mrs and msr for the special purpose system
1000   // registers where op1 (instr[20:19]) == 11 and, (currently) only
1001   // use it for FPSR n.b msr has L (instr[21]) == 0 mrs has L == 1
1002 
1003   void msr(int op1, int CRn, int CRm, int op2, Register rt) {
1004     starti;
1005     f(0b1101010100011, 31, 19);
1006     f(op1, 18, 16);
1007     f(CRn, 15, 12);
1008     f(CRm, 11, 8);
1009     f(op2, 7, 5);
1010     // writing zr is ok
1011     zrf(rt, 0);
1012   }
1013 
1014   void mrs(int op1, int CRn, int CRm, int op2, Register rt) {
1015     starti;
1016     f(0b1101010100111, 31, 19);