1 /* 2 * Copyright (c) 1997, 2015, Oracle and/or its affiliates. All rights reserved. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 * 5 * This code is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 only, as 7 * published by the Free Software Foundation. 8 * 9 * This code is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * version 2 for more details (a copy is included in the LICENSE file that 13 * accompanied this code). 14 * 15 * You should have received a copy of the GNU General Public License version 16 * 2 along with this work; if not, write to the Free Software Foundation, 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 20 * or visit www.oracle.com if you need additional information or have any 21 * questions. 22 * 23 */ 24 25 #ifndef CPU_SPARC_VM_ASSEMBLER_SPARC_HPP 26 #define CPU_SPARC_VM_ASSEMBLER_SPARC_HPP 27 28 #include "asm/register.hpp" 29 30 // The SPARC Assembler: Pure assembler doing NO optimizations on the instruction 31 // level; i.e., what you write 32 // is what you get. The Assembler is generating code into a CodeBuffer. 33 34 class Assembler : public AbstractAssembler { 35 friend class AbstractAssembler; 36 friend class AddressLiteral; 37 38 // code patchers need various routines like inv_wdisp() 39 friend class NativeInstruction; 40 friend class NativeGeneralJump; 41 friend class Relocation; 42 friend class Label; 43 44 public: 45 // op carries format info; see page 62 & 267 46 47 enum ops { 48 call_op = 1, // fmt 1 49 branch_op = 0, // also sethi (fmt2) 50 arith_op = 2, // fmt 3, arith & misc 51 ldst_op = 3 // fmt 3, load/store 52 }; 53 54 enum op2s { 55 bpr_op2 = 3, 56 fb_op2 = 6, 57 fbp_op2 = 5, 58 br_op2 = 2, 59 bp_op2 = 1, 60 sethi_op2 = 4 61 }; 62 63 enum op3s { 64 // selected op3s 65 add_op3 = 0x00, 66 and_op3 = 0x01, 67 or_op3 = 0x02, 68 xor_op3 = 0x03, 69 sub_op3 = 0x04, 70 andn_op3 = 0x05, 71 orn_op3 = 0x06, 72 xnor_op3 = 0x07, 73 addc_op3 = 0x08, 74 mulx_op3 = 0x09, 75 umul_op3 = 0x0a, 76 smul_op3 = 0x0b, 77 subc_op3 = 0x0c, 78 udivx_op3 = 0x0d, 79 udiv_op3 = 0x0e, 80 sdiv_op3 = 0x0f, 81 82 addcc_op3 = 0x10, 83 andcc_op3 = 0x11, 84 orcc_op3 = 0x12, 85 xorcc_op3 = 0x13, 86 subcc_op3 = 0x14, 87 andncc_op3 = 0x15, 88 orncc_op3 = 0x16, 89 xnorcc_op3 = 0x17, 90 addccc_op3 = 0x18, 91 aes4_op3 = 0x19, 92 umulcc_op3 = 0x1a, 93 smulcc_op3 = 0x1b, 94 subccc_op3 = 0x1c, 95 udivcc_op3 = 0x1e, 96 sdivcc_op3 = 0x1f, 97 98 taddcc_op3 = 0x20, 99 tsubcc_op3 = 0x21, 100 taddcctv_op3 = 0x22, 101 tsubcctv_op3 = 0x23, 102 mulscc_op3 = 0x24, 103 sll_op3 = 0x25, 104 sllx_op3 = 0x25, 105 srl_op3 = 0x26, 106 srlx_op3 = 0x26, 107 sra_op3 = 0x27, 108 srax_op3 = 0x27, 109 rdreg_op3 = 0x28, 110 membar_op3 = 0x28, 111 112 flushw_op3 = 0x2b, 113 movcc_op3 = 0x2c, 114 sdivx_op3 = 0x2d, 115 popc_op3 = 0x2e, 116 movr_op3 = 0x2f, 117 118 sir_op3 = 0x30, 119 wrreg_op3 = 0x30, 120 saved_op3 = 0x31, 121 122 fpop1_op3 = 0x34, 123 fpop2_op3 = 0x35, 124 impdep1_op3 = 0x36, 125 aes3_op3 = 0x36, 126 sha_op3 = 0x36, 127 alignaddr_op3 = 0x36, 128 faligndata_op3 = 0x36, 129 flog3_op3 = 0x36, 130 edge_op3 = 0x36, 131 fzero_op3 = 0x36, 132 fsrc_op3 = 0x36, 133 fnot_op3 = 0x36, 134 xmulx_op3 = 0x36, 135 crc32c_op3 = 0x36, 136 impdep2_op3 = 0x37, 137 stpartialf_op3 = 0x37, 138 jmpl_op3 = 0x38, 139 rett_op3 = 0x39, 140 trap_op3 = 0x3a, 141 flush_op3 = 0x3b, 142 save_op3 = 0x3c, 143 restore_op3 = 0x3d, 144 done_op3 = 0x3e, 145 retry_op3 = 0x3e, 146 147 lduw_op3 = 0x00, 148 ldub_op3 = 0x01, 149 lduh_op3 = 0x02, 150 ldd_op3 = 0x03, 151 stw_op3 = 0x04, 152 stb_op3 = 0x05, 153 sth_op3 = 0x06, 154 std_op3 = 0x07, 155 ldsw_op3 = 0x08, 156 ldsb_op3 = 0x09, 157 ldsh_op3 = 0x0a, 158 ldx_op3 = 0x0b, 159 160 stx_op3 = 0x0e, 161 swap_op3 = 0x0f, 162 163 stwa_op3 = 0x14, 164 stxa_op3 = 0x1e, 165 166 ldf_op3 = 0x20, 167 ldfsr_op3 = 0x21, 168 ldqf_op3 = 0x22, 169 lddf_op3 = 0x23, 170 stf_op3 = 0x24, 171 stfsr_op3 = 0x25, 172 stqf_op3 = 0x26, 173 stdf_op3 = 0x27, 174 175 prefetch_op3 = 0x2d, 176 177 casa_op3 = 0x3c, 178 casxa_op3 = 0x3e, 179 180 mftoi_op3 = 0x36, 181 182 alt_bit_op3 = 0x10, 183 cc_bit_op3 = 0x10 184 }; 185 186 enum opfs { 187 // selected opfs 188 edge8n_opf = 0x01, 189 190 fmovs_opf = 0x01, 191 fmovd_opf = 0x02, 192 193 fnegs_opf = 0x05, 194 fnegd_opf = 0x06, 195 196 alignaddr_opf = 0x18, 197 198 fadds_opf = 0x41, 199 faddd_opf = 0x42, 200 fsubs_opf = 0x45, 201 fsubd_opf = 0x46, 202 203 faligndata_opf = 0x48, 204 205 fmuls_opf = 0x49, 206 fmuld_opf = 0x4a, 207 fdivs_opf = 0x4d, 208 fdivd_opf = 0x4e, 209 210 fcmps_opf = 0x51, 211 fcmpd_opf = 0x52, 212 213 fstox_opf = 0x81, 214 fdtox_opf = 0x82, 215 fxtos_opf = 0x84, 216 fxtod_opf = 0x88, 217 fitos_opf = 0xc4, 218 fdtos_opf = 0xc6, 219 fitod_opf = 0xc8, 220 fstod_opf = 0xc9, 221 fstoi_opf = 0xd1, 222 fdtoi_opf = 0xd2, 223 224 mdtox_opf = 0x110, 225 mstouw_opf = 0x111, 226 mstosw_opf = 0x113, 227 xmulx_opf = 0x115, 228 xmulxhi_opf = 0x116, 229 mxtod_opf = 0x118, 230 mwtos_opf = 0x119, 231 232 aes_kexpand0_opf = 0x130, 233 aes_kexpand2_opf = 0x131, 234 235 sha1_opf = 0x141, 236 sha256_opf = 0x142, 237 sha512_opf = 0x143, 238 239 crc32c_opf = 0x147 240 }; 241 242 enum op5s { 243 aes_eround01_op5 = 0x00, 244 aes_eround23_op5 = 0x01, 245 aes_dround01_op5 = 0x02, 246 aes_dround23_op5 = 0x03, 247 aes_eround01_l_op5 = 0x04, 248 aes_eround23_l_op5 = 0x05, 249 aes_dround01_l_op5 = 0x06, 250 aes_dround23_l_op5 = 0x07, 251 aes_kexpand1_op5 = 0x08 252 }; 253 254 enum RCondition { rc_z = 1, rc_lez = 2, rc_lz = 3, rc_nz = 5, rc_gz = 6, rc_gez = 7, rc_last = rc_gez }; 255 256 enum Condition { 257 // for FBfcc & FBPfcc instruction 258 f_never = 0, 259 f_notEqual = 1, 260 f_notZero = 1, 261 f_lessOrGreater = 2, 262 f_unorderedOrLess = 3, 263 f_less = 4, 264 f_unorderedOrGreater = 5, 265 f_greater = 6, 266 f_unordered = 7, 267 f_always = 8, 268 f_equal = 9, 269 f_zero = 9, 270 f_unorderedOrEqual = 10, 271 f_greaterOrEqual = 11, 272 f_unorderedOrGreaterOrEqual = 12, 273 f_lessOrEqual = 13, 274 f_unorderedOrLessOrEqual = 14, 275 f_ordered = 15, 276 277 // V8 coproc, pp 123 v8 manual 278 279 cp_always = 8, 280 cp_never = 0, 281 cp_3 = 7, 282 cp_2 = 6, 283 cp_2or3 = 5, 284 cp_1 = 4, 285 cp_1or3 = 3, 286 cp_1or2 = 2, 287 cp_1or2or3 = 1, 288 cp_0 = 9, 289 cp_0or3 = 10, 290 cp_0or2 = 11, 291 cp_0or2or3 = 12, 292 cp_0or1 = 13, 293 cp_0or1or3 = 14, 294 cp_0or1or2 = 15, 295 296 297 // for integers 298 299 never = 0, 300 equal = 1, 301 zero = 1, 302 lessEqual = 2, 303 less = 3, 304 lessEqualUnsigned = 4, 305 lessUnsigned = 5, 306 carrySet = 5, 307 negative = 6, 308 overflowSet = 7, 309 always = 8, 310 notEqual = 9, 311 notZero = 9, 312 greater = 10, 313 greaterEqual = 11, 314 greaterUnsigned = 12, 315 greaterEqualUnsigned = 13, 316 carryClear = 13, 317 positive = 14, 318 overflowClear = 15 319 }; 320 321 enum CC { 322 icc = 0, xcc = 2, 323 // ptr_cc is the correct condition code for a pointer or intptr_t: 324 ptr_cc = NOT_LP64(icc) LP64_ONLY(xcc), 325 fcc0 = 0, fcc1 = 1, fcc2 = 2, fcc3 = 3 326 }; 327 328 enum PrefetchFcn { 329 severalReads = 0, oneRead = 1, severalWritesAndPossiblyReads = 2, oneWrite = 3, page = 4 330 }; 331 332 public: 333 // Helper functions for groups of instructions 334 335 enum Predict { pt = 1, pn = 0 }; // pt = predict taken 336 337 enum Membar_mask_bits { // page 184, v9 338 StoreStore = 1 << 3, 339 LoadStore = 1 << 2, 340 StoreLoad = 1 << 1, 341 LoadLoad = 1 << 0, 342 343 Sync = 1 << 6, 344 MemIssue = 1 << 5, 345 Lookaside = 1 << 4 346 }; 347 348 static bool is_in_wdisp_range(address a, address b, int nbits) { 349 intptr_t d = intptr_t(b) - intptr_t(a); 350 return is_simm(d, nbits + 2); 351 } 352 353 address target_distance(Label& L) { 354 // Assembler::target(L) should be called only when 355 // a branch instruction is emitted since non-bound 356 // labels record current pc() as a branch address. 357 if (L.is_bound()) return target(L); 358 // Return current address for non-bound labels. 359 return pc(); 360 } 361 362 // test if label is in simm16 range in words (wdisp16). 363 bool is_in_wdisp16_range(Label& L) { 364 return is_in_wdisp_range(target_distance(L), pc(), 16); 365 } 366 // test if the distance between two addresses fits in simm30 range in words 367 static bool is_in_wdisp30_range(address a, address b) { 368 return is_in_wdisp_range(a, b, 30); 369 } 370 371 enum ASIs { // page 72, v9 372 ASI_PRIMARY = 0x80, 373 ASI_PRIMARY_NOFAULT = 0x82, 374 ASI_PRIMARY_LITTLE = 0x88, 375 // 8x8-bit partial store 376 ASI_PST8_PRIMARY = 0xC0, 377 // Block initializing store 378 ASI_ST_BLKINIT_PRIMARY = 0xE2, 379 // Most-Recently-Used (MRU) BIS variant 380 ASI_ST_BLKINIT_MRU_PRIMARY = 0xF2 381 // add more from book as needed 382 }; 383 384 protected: 385 // helpers 386 387 // x is supposed to fit in a field "nbits" wide 388 // and be sign-extended. Check the range. 389 390 static void assert_signed_range(intptr_t x, int nbits) { 391 assert(nbits == 32 || (-(1 << nbits-1) <= x && x < ( 1 << nbits-1)), 392 err_msg("value out of range: x=" INTPTR_FORMAT ", nbits=%d", x, nbits)); 393 } 394 395 static void assert_signed_word_disp_range(intptr_t x, int nbits) { 396 assert( (x & 3) == 0, "not word aligned"); 397 assert_signed_range(x, nbits + 2); 398 } 399 400 static void assert_unsigned_const(int x, int nbits) { 401 assert( juint(x) < juint(1 << nbits), "unsigned constant out of range"); 402 } 403 404 // fields: note bits numbered from LSB = 0, 405 // fields known by inclusive bit range 406 407 static int fmask(juint hi_bit, juint lo_bit) { 408 assert( hi_bit >= lo_bit && 0 <= lo_bit && hi_bit < 32, "bad bits"); 409 return (1 << ( hi_bit-lo_bit + 1 )) - 1; 410 } 411 412 // inverse of u_field 413 414 static int inv_u_field(int x, int hi_bit, int lo_bit) { 415 juint r = juint(x) >> lo_bit; 416 r &= fmask( hi_bit, lo_bit); 417 return int(r); 418 } 419 420 421 // signed version: extract from field and sign-extend 422 423 static int inv_s_field(int x, int hi_bit, int lo_bit) { 424 int sign_shift = 31 - hi_bit; 425 return inv_u_field( ((x << sign_shift) >> sign_shift), hi_bit, lo_bit); 426 } 427 428 // given a field that ranges from hi_bit to lo_bit (inclusive, 429 // LSB = 0), and an unsigned value for the field, 430 // shift it into the field 431 432 #ifdef ASSERT 433 static int u_field(int x, int hi_bit, int lo_bit) { 434 assert( ( x & ~fmask(hi_bit, lo_bit)) == 0, 435 "value out of range"); 436 int r = x << lo_bit; 437 assert( inv_u_field(r, hi_bit, lo_bit) == x, "just checking"); 438 return r; 439 } 440 #else 441 // make sure this is inlined as it will reduce code size significantly 442 #define u_field(x, hi_bit, lo_bit) ((x) << (lo_bit)) 443 #endif 444 445 static int inv_op( int x ) { return inv_u_field(x, 31, 30); } 446 static int inv_op2( int x ) { return inv_u_field(x, 24, 22); } 447 static int inv_op3( int x ) { return inv_u_field(x, 24, 19); } 448 static int inv_cond( int x ){ return inv_u_field(x, 28, 25); } 449 450 static bool inv_immed( int x ) { return (x & Assembler::immed(true)) != 0; } 451 452 static Register inv_rd( int x ) { return as_Register(inv_u_field(x, 29, 25)); } 453 static Register inv_rs1( int x ) { return as_Register(inv_u_field(x, 18, 14)); } 454 static Register inv_rs2( int x ) { return as_Register(inv_u_field(x, 4, 0)); } 455 456 static int op( int x) { return u_field(x, 31, 30); } 457 static int rd( Register r) { return u_field(r->encoding(), 29, 25); } 458 static int fcn( int x) { return u_field(x, 29, 25); } 459 static int op3( int x) { return u_field(x, 24, 19); } 460 static int rs1( Register r) { return u_field(r->encoding(), 18, 14); } 461 static int rs2( Register r) { return u_field(r->encoding(), 4, 0); } 462 static int annul( bool a) { return u_field(a ? 1 : 0, 29, 29); } 463 static int cond( int x) { return u_field(x, 28, 25); } 464 static int cond_mov( int x) { return u_field(x, 17, 14); } 465 static int rcond( RCondition x) { return u_field(x, 12, 10); } 466 static int op2( int x) { return u_field(x, 24, 22); } 467 static int predict( bool p) { return u_field(p ? 1 : 0, 19, 19); } 468 static int branchcc( CC fcca) { return u_field(fcca, 21, 20); } 469 static int cmpcc( CC fcca) { return u_field(fcca, 26, 25); } 470 static int imm_asi( int x) { return u_field(x, 12, 5); } 471 static int immed( bool i) { return u_field(i ? 1 : 0, 13, 13); } 472 static int opf_low6( int w) { return u_field(w, 10, 5); } 473 static int opf_low5( int w) { return u_field(w, 9, 5); } 474 static int op5( int x) { return u_field(x, 8, 5); } 475 static int trapcc( CC cc) { return u_field(cc, 12, 11); } 476 static int sx( int i) { return u_field(i, 12, 12); } // shift x=1 means 64-bit 477 static int opf( int x) { return u_field(x, 13, 5); } 478 479 static bool is_cbcond( int x ) { 480 return (VM_Version::has_cbcond() && (inv_cond(x) > rc_last) && 481 inv_op(x) == branch_op && inv_op2(x) == bpr_op2); 482 } 483 static bool is_cxb( int x ) { 484 assert(is_cbcond(x), "wrong instruction"); 485 return (x & (1<<21)) != 0; 486 } 487 static int cond_cbcond( int x) { return u_field((((x & 8)<<1) + 8 + (x & 7)), 29, 25); } 488 static int inv_cond_cbcond(int x) { 489 assert(is_cbcond(x), "wrong instruction"); 490 return inv_u_field(x, 27, 25) | (inv_u_field(x, 29, 29)<<3); 491 } 492 493 static int opf_cc( CC c, bool useFloat ) { return u_field((useFloat ? 0 : 4) + c, 13, 11); } 494 static int mov_cc( CC c, bool useFloat ) { return u_field(useFloat ? 0 : 1, 18, 18) | u_field(c, 12, 11); } 495 496 static int fd( FloatRegister r, FloatRegisterImpl::Width fwa) { return u_field(r->encoding(fwa), 29, 25); }; 497 static int fs1(FloatRegister r, FloatRegisterImpl::Width fwa) { return u_field(r->encoding(fwa), 18, 14); }; 498 static int fs2(FloatRegister r, FloatRegisterImpl::Width fwa) { return u_field(r->encoding(fwa), 4, 0); }; 499 static int fs3(FloatRegister r, FloatRegisterImpl::Width fwa) { return u_field(r->encoding(fwa), 13, 9); }; 500 501 // some float instructions use this encoding on the op3 field 502 static int alt_op3(int op, FloatRegisterImpl::Width w) { 503 int r; 504 switch(w) { 505 case FloatRegisterImpl::S: r = op + 0; break; 506 case FloatRegisterImpl::D: r = op + 3; break; 507 case FloatRegisterImpl::Q: r = op + 2; break; 508 default: ShouldNotReachHere(); break; 509 } 510 return op3(r); 511 } 512 513 514 // compute inverse of simm 515 static int inv_simm(int x, int nbits) { 516 return (int)(x << (32 - nbits)) >> (32 - nbits); 517 } 518 519 static int inv_simm13( int x ) { return inv_simm(x, 13); } 520 521 // signed immediate, in low bits, nbits long 522 static int simm(int x, int nbits) { 523 assert_signed_range(x, nbits); 524 return x & (( 1 << nbits ) - 1); 525 } 526 527 // compute inverse of wdisp16 528 static intptr_t inv_wdisp16(int x, intptr_t pos) { 529 int lo = x & (( 1 << 14 ) - 1); 530 int hi = (x >> 20) & 3; 531 if (hi >= 2) hi |= ~1; 532 return (((hi << 14) | lo) << 2) + pos; 533 } 534 535 // word offset, 14 bits at LSend, 2 bits at B21, B20 536 static int wdisp16(intptr_t x, intptr_t off) { 537 intptr_t xx = x - off; 538 assert_signed_word_disp_range(xx, 16); 539 int r = (xx >> 2) & ((1 << 14) - 1) 540 | ( ( (xx>>(2+14)) & 3 ) << 20 ); 541 assert( inv_wdisp16(r, off) == x, "inverse is not inverse"); 542 return r; 543 } 544 545 // compute inverse of wdisp10 546 static intptr_t inv_wdisp10(int x, intptr_t pos) { 547 assert(is_cbcond(x), "wrong instruction"); 548 int lo = inv_u_field(x, 12, 5); 549 int hi = (x >> 19) & 3; 550 if (hi >= 2) hi |= ~1; 551 return (((hi << 8) | lo) << 2) + pos; 552 } 553 554 // word offset for cbcond, 8 bits at [B12,B5], 2 bits at [B20,B19] 555 static int wdisp10(intptr_t x, intptr_t off) { 556 assert(VM_Version::has_cbcond(), "This CPU does not have CBCOND instruction"); 557 intptr_t xx = x - off; 558 assert_signed_word_disp_range(xx, 10); 559 int r = ( ( (xx >> 2 ) & ((1 << 8) - 1) ) << 5 ) 560 | ( ( (xx >> (2+8)) & 3 ) << 19 ); 561 // Have to fake cbcond instruction to pass assert in inv_wdisp10() 562 assert(inv_wdisp10((r | op(branch_op) | cond_cbcond(rc_last+1) | op2(bpr_op2)), off) == x, "inverse is not inverse"); 563 return r; 564 } 565 566 // word displacement in low-order nbits bits 567 568 static intptr_t inv_wdisp( int x, intptr_t pos, int nbits ) { 569 int pre_sign_extend = x & (( 1 << nbits ) - 1); 570 int r = pre_sign_extend >= ( 1 << (nbits-1) ) 571 ? pre_sign_extend | ~(( 1 << nbits ) - 1) 572 : pre_sign_extend; 573 return (r << 2) + pos; 574 } 575 576 static int wdisp( intptr_t x, intptr_t off, int nbits ) { 577 intptr_t xx = x - off; 578 assert_signed_word_disp_range(xx, nbits); 579 int r = (xx >> 2) & (( 1 << nbits ) - 1); 580 assert( inv_wdisp( r, off, nbits ) == x, "inverse not inverse"); 581 return r; 582 } 583 584 585 // Extract the top 32 bits in a 64 bit word 586 static int32_t hi32( int64_t x ) { 587 int32_t r = int32_t( (uint64_t)x >> 32 ); 588 return r; 589 } 590 591 // given a sethi instruction, extract the constant, left-justified 592 static int inv_hi22( int x ) { 593 return x << 10; 594 } 595 596 // create an imm22 field, given a 32-bit left-justified constant 597 static int hi22( int x ) { 598 int r = int( juint(x) >> 10 ); 599 assert( (r & ~((1 << 22) - 1)) == 0, "just checkin'"); 600 return r; 601 } 602 603 // create a low10 __value__ (not a field) for a given a 32-bit constant 604 static int low10( int x ) { 605 return x & ((1 << 10) - 1); 606 } 607 608 // create a low12 __value__ (not a field) for a given a 32-bit constant 609 static int low12( int x ) { 610 return x & ((1 << 12) - 1); 611 } 612 613 // AES crypto instructions supported only on certain processors 614 static void aes_only() { assert( VM_Version::has_aes(), "This instruction only works on SPARC with AES instructions support"); } 615 616 // SHA crypto instructions supported only on certain processors 617 static void sha1_only() { assert( VM_Version::has_sha1(), "This instruction only works on SPARC with SHA1"); } 618 static void sha256_only() { assert( VM_Version::has_sha256(), "This instruction only works on SPARC with SHA256"); } 619 static void sha512_only() { assert( VM_Version::has_sha512(), "This instruction only works on SPARC with SHA512"); } 620 621 // CRC32C instruction supported only on certain processors 622 static void crc32c_only() { assert( VM_Version::has_crc32c(), "This instruction only works on SPARC with CRC32C"); } 623 624 // instruction only in VIS1 625 static void vis1_only() { assert( VM_Version::has_vis1(), "This instruction only works on SPARC with VIS1"); } 626 627 // instruction only in VIS2 628 static void vis2_only() { assert( VM_Version::has_vis2(), "This instruction only works on SPARC with VIS2"); } 629 630 // instruction only in VIS3 631 static void vis3_only() { assert( VM_Version::has_vis3(), "This instruction only works on SPARC with VIS3"); } 632 633 // instruction only in v9 634 static void v9_only() { } // do nothing 635 636 // instruction deprecated in v9 637 static void v9_dep() { } // do nothing for now 638 639 // v8 has no CC field 640 static void v8_no_cc(CC cc) { if (cc) v9_only(); } 641 642 protected: 643 // Simple delay-slot scheme: 644 // In order to check the programmer, the assembler keeps track of deley slots. 645 // It forbids CTIs in delay slots (conservative, but should be OK). 646 // Also, when putting an instruction into a delay slot, you must say 647 // asm->delayed()->add(...), in order to check that you don't omit 648 // delay-slot instructions. 649 // To implement this, we use a simple FSA 650 651 #ifdef ASSERT 652 #define CHECK_DELAY 653 #endif 654 #ifdef CHECK_DELAY 655 enum Delay_state { no_delay, at_delay_slot, filling_delay_slot } delay_state; 656 #endif 657 658 public: 659 // Tells assembler next instruction must NOT be in delay slot. 660 // Use at start of multinstruction macros. 661 void assert_not_delayed() { 662 // This is a separate overloading to avoid creation of string constants 663 // in non-asserted code--with some compilers this pollutes the object code. 664 #ifdef CHECK_DELAY 665 assert_not_delayed("next instruction should not be a delay slot"); 666 #endif 667 } 668 void assert_not_delayed(const char* msg) { 669 #ifdef CHECK_DELAY 670 assert(delay_state == no_delay, msg); 671 #endif 672 } 673 674 protected: 675 // Insert a nop if the previous is cbcond 676 void insert_nop_after_cbcond() { 677 if (UseCBCond && cbcond_before()) { 678 nop(); 679 } 680 } 681 // Delay slot helpers 682 // cti is called when emitting control-transfer instruction, 683 // BEFORE doing the emitting. 684 // Only effective when assertion-checking is enabled. 685 void cti() { 686 // A cbcond instruction immediately followed by a CTI 687 // instruction introduces pipeline stalls, we need to avoid that. 688 no_cbcond_before(); 689 #ifdef CHECK_DELAY 690 assert_not_delayed("cti should not be in delay slot"); 691 #endif 692 } 693 694 // called when emitting cti with a delay slot, AFTER emitting 695 void has_delay_slot() { 696 #ifdef CHECK_DELAY 697 assert_not_delayed("just checking"); 698 delay_state = at_delay_slot; 699 #endif 700 } 701 702 // cbcond instruction should not be generated one after an other 703 bool cbcond_before() { 704 if (offset() == 0) return false; // it is first instruction 705 int x = *(int*)(intptr_t(pc()) - 4); // previous instruction 706 return is_cbcond(x); 707 } 708 709 void no_cbcond_before() { 710 assert(offset() == 0 || !cbcond_before(), "cbcond should not follow an other cbcond"); 711 } 712 public: 713 714 bool use_cbcond(Label& L) { 715 if (!UseCBCond || cbcond_before()) return false; 716 intptr_t x = intptr_t(target_distance(L)) - intptr_t(pc()); 717 assert( (x & 3) == 0, "not word aligned"); 718 return is_simm12(x); 719 } 720 721 // Tells assembler you know that next instruction is delayed 722 Assembler* delayed() { 723 #ifdef CHECK_DELAY 724 assert ( delay_state == at_delay_slot, "delayed instruction is not in delay slot"); 725 delay_state = filling_delay_slot; 726 #endif 727 return this; 728 } 729 730 void flush() { 731 #ifdef CHECK_DELAY 732 assert ( delay_state == no_delay, "ending code with a delay slot"); 733 #endif 734 AbstractAssembler::flush(); 735 } 736 737 inline void emit_int32(int); // shadows AbstractAssembler::emit_int32 738 inline void emit_data(int x) { emit_int32(x); } 739 inline void emit_data(int, RelocationHolder const&); 740 inline void emit_data(int, relocInfo::relocType rtype); 741 // helper for above fcns 742 inline void check_delay(); 743 744 745 public: 746 // instructions, refer to page numbers in the SPARC Architecture Manual, V9 747 748 // pp 135 (addc was addx in v8) 749 750 inline void add(Register s1, Register s2, Register d ); 751 inline void add(Register s1, int simm13a, Register d ); 752 753 void addcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(add_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); } 754 void addcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(add_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 755 void addc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(addc_op3 ) | rs1(s1) | rs2(s2) ); } 756 void addc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(addc_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 757 void addccc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(addc_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); } 758 void addccc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(addc_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 759 760 761 // 4-operand AES instructions 762 763 void aes_eround01( FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d ) { aes_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | fs3(s3, FloatRegisterImpl::D) | op5(aes_eround01_op5) | fs2(s2, FloatRegisterImpl::D) ); } 764 void aes_eround23( FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d ) { aes_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | fs3(s3, FloatRegisterImpl::D) | op5(aes_eround23_op5) | fs2(s2, FloatRegisterImpl::D) ); } 765 void aes_dround01( FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d ) { aes_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | fs3(s3, FloatRegisterImpl::D) | op5(aes_dround01_op5) | fs2(s2, FloatRegisterImpl::D) ); } 766 void aes_dround23( FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d ) { aes_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | fs3(s3, FloatRegisterImpl::D) | op5(aes_dround23_op5) | fs2(s2, FloatRegisterImpl::D) ); } 767 void aes_eround01_l( FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d ) { aes_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | fs3(s3, FloatRegisterImpl::D) | op5(aes_eround01_l_op5) | fs2(s2, FloatRegisterImpl::D) ); } 768 void aes_eround23_l( FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d ) { aes_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | fs3(s3, FloatRegisterImpl::D) | op5(aes_eround23_l_op5) | fs2(s2, FloatRegisterImpl::D) ); } 769 void aes_dround01_l( FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d ) { aes_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | fs3(s3, FloatRegisterImpl::D) | op5(aes_dround01_l_op5) | fs2(s2, FloatRegisterImpl::D) ); } 770 void aes_dround23_l( FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d ) { aes_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | fs3(s3, FloatRegisterImpl::D) | op5(aes_dround23_l_op5) | fs2(s2, FloatRegisterImpl::D) ); } 771 void aes_kexpand1( FloatRegister s1, FloatRegister s2, int imm5a, FloatRegister d ) { aes_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | u_field(imm5a, 13, 9) | op5(aes_kexpand1_op5) | fs2(s2, FloatRegisterImpl::D) ); } 772 773 774 // 3-operand AES instructions 775 776 void aes_kexpand0( FloatRegister s1, FloatRegister s2, FloatRegister d ) { aes_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes3_op3) | fs1(s1, FloatRegisterImpl::D) | opf(aes_kexpand0_opf) | fs2(s2, FloatRegisterImpl::D) ); } 777 void aes_kexpand2( FloatRegister s1, FloatRegister s2, FloatRegister d ) { aes_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes3_op3) | fs1(s1, FloatRegisterImpl::D) | opf(aes_kexpand2_opf) | fs2(s2, FloatRegisterImpl::D) ); } 778 779 // pp 136 780 781 inline void bpr(RCondition c, bool a, Predict p, Register s1, address d, relocInfo::relocType rt = relocInfo::none); 782 inline void bpr(RCondition c, bool a, Predict p, Register s1, Label& L); 783 784 // compare and branch 785 inline void cbcond(Condition c, CC cc, Register s1, Register s2, Label& L); 786 inline void cbcond(Condition c, CC cc, Register s1, int simm5, Label& L); 787 788 protected: // use MacroAssembler::br instead 789 790 // pp 138 791 792 inline void fb( Condition c, bool a, address d, relocInfo::relocType rt = relocInfo::none ); 793 inline void fb( Condition c, bool a, Label& L ); 794 795 // pp 141 796 797 inline void fbp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt = relocInfo::none ); 798 inline void fbp( Condition c, bool a, CC cc, Predict p, Label& L ); 799 800 // pp 144 801 802 inline void br( Condition c, bool a, address d, relocInfo::relocType rt = relocInfo::none ); 803 inline void br( Condition c, bool a, Label& L ); 804 805 // pp 146 806 807 inline void bp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt = relocInfo::none ); 808 inline void bp( Condition c, bool a, CC cc, Predict p, Label& L ); 809 810 // pp 149 811 812 inline void call( address d, relocInfo::relocType rt = relocInfo::runtime_call_type ); 813 inline void call( Label& L, relocInfo::relocType rt = relocInfo::runtime_call_type ); 814 815 public: 816 817 // pp 150 818 819 // These instructions compare the contents of s2 with the contents of 820 // memory at address in s1. If the values are equal, the contents of memory 821 // at address s1 is swapped with the data in d. If the values are not equal, 822 // the the contents of memory at s1 is loaded into d, without the swap. 823 824 void casa( Register s1, Register s2, Register d, int ia = -1 ) { v9_only(); emit_int32( op(ldst_op) | rd(d) | op3(casa_op3 ) | rs1(s1) | (ia == -1 ? immed(true) : imm_asi(ia)) | rs2(s2)); } 825 void casxa( Register s1, Register s2, Register d, int ia = -1 ) { v9_only(); emit_int32( op(ldst_op) | rd(d) | op3(casxa_op3) | rs1(s1) | (ia == -1 ? immed(true) : imm_asi(ia)) | rs2(s2)); } 826 827 // pp 152 828 829 void udiv( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(udiv_op3 ) | rs1(s1) | rs2(s2)); } 830 void udiv( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(udiv_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 831 void sdiv( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sdiv_op3 ) | rs1(s1) | rs2(s2)); } 832 void sdiv( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sdiv_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 833 void udivcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(udiv_op3 | cc_bit_op3) | rs1(s1) | rs2(s2)); } 834 void udivcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(udiv_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 835 void sdivcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sdiv_op3 | cc_bit_op3) | rs1(s1) | rs2(s2)); } 836 void sdivcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sdiv_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 837 838 // pp 155 839 840 void done() { v9_only(); cti(); emit_int32( op(arith_op) | fcn(0) | op3(done_op3) ); } 841 void retry() { v9_only(); cti(); emit_int32( op(arith_op) | fcn(1) | op3(retry_op3) ); } 842 843 // pp 156 844 845 void fadd( FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | fs1(s1, w) | opf(0x40 + w) | fs2(s2, w)); } 846 void fsub( FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | fs1(s1, w) | opf(0x44 + w) | fs2(s2, w)); } 847 848 // pp 157 849 850 void fcmp( FloatRegisterImpl::Width w, CC cc, FloatRegister s1, FloatRegister s2) { emit_int32( op(arith_op) | cmpcc(cc) | op3(fpop2_op3) | fs1(s1, w) | opf(0x50 + w) | fs2(s2, w)); } 851 void fcmpe( FloatRegisterImpl::Width w, CC cc, FloatRegister s1, FloatRegister s2) { emit_int32( op(arith_op) | cmpcc(cc) | op3(fpop2_op3) | fs1(s1, w) | opf(0x54 + w) | fs2(s2, w)); } 852 853 // pp 159 854 855 void ftox( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { v9_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(fpop1_op3) | opf(0x80 + w) | fs2(s, w)); } 856 void ftoi( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::S) | op3(fpop1_op3) | opf(0xd0 + w) | fs2(s, w)); } 857 858 // pp 160 859 860 void ftof( FloatRegisterImpl::Width sw, FloatRegisterImpl::Width dw, FloatRegister s, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, dw) | op3(fpop1_op3) | opf(0xc0 + sw + dw*4) | fs2(s, sw)); } 861 862 // pp 161 863 864 void fxtof( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { v9_only(); emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x80 + w*4) | fs2(s, FloatRegisterImpl::D)); } 865 void fitof( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0xc0 + w*4) | fs2(s, FloatRegisterImpl::S)); } 866 867 // pp 162 868 869 void fmov( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x00 + w) | fs2(s, w)); } 870 871 void fneg( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x04 + w) | fs2(s, w)); } 872 873 void fabs( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x08 + w) | fs2(s, w)); } 874 875 // pp 163 876 877 void fmul( FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | fs1(s1, w) | opf(0x48 + w) | fs2(s2, w)); } 878 void fmul( FloatRegisterImpl::Width sw, FloatRegisterImpl::Width dw, FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, dw) | op3(fpop1_op3) | fs1(s1, sw) | opf(0x60 + sw + dw*4) | fs2(s2, sw)); } 879 void fdiv( FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | fs1(s1, w) | opf(0x4c + w) | fs2(s2, w)); } 880 881 // FXORs/FXORd instructions 882 883 void fxor( FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d ) { vis1_only(); emit_int32( op(arith_op) | fd(d, w) | op3(flog3_op3) | fs1(s1, w) | opf(0x6E - w) | fs2(s2, w)); } 884 885 // pp 164 886 887 void fsqrt( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x28 + w) | fs2(s, w)); } 888 889 // pp 165 890 891 inline void flush( Register s1, Register s2 ); 892 inline void flush( Register s1, int simm13a); 893 894 // pp 167 895 896 void flushw() { v9_only(); emit_int32( op(arith_op) | op3(flushw_op3) ); } 897 898 // pp 168 899 900 void illtrap( int const22a) { if (const22a != 0) v9_only(); emit_int32( op(branch_op) | u_field(const22a, 21, 0) ); } 901 // v8 unimp == illtrap(0) 902 903 // pp 169 904 905 void impdep1( int id1, int const19a ) { v9_only(); emit_int32( op(arith_op) | fcn(id1) | op3(impdep1_op3) | u_field(const19a, 18, 0)); } 906 void impdep2( int id1, int const19a ) { v9_only(); emit_int32( op(arith_op) | fcn(id1) | op3(impdep2_op3) | u_field(const19a, 18, 0)); } 907 908 // pp 170 909 910 void jmpl( Register s1, Register s2, Register d ); 911 void jmpl( Register s1, int simm13a, Register d, RelocationHolder const& rspec = RelocationHolder() ); 912 913 // 171 914 915 inline void ldf(FloatRegisterImpl::Width w, Register s1, Register s2, FloatRegister d); 916 inline void ldf(FloatRegisterImpl::Width w, Register s1, int simm13a, FloatRegister d, RelocationHolder const& rspec = RelocationHolder()); 917 918 919 inline void ldfsr( Register s1, Register s2 ); 920 inline void ldfsr( Register s1, int simm13a); 921 inline void ldxfsr( Register s1, Register s2 ); 922 inline void ldxfsr( Register s1, int simm13a); 923 924 // 173 925 926 void ldfa( FloatRegisterImpl::Width w, Register s1, Register s2, int ia, FloatRegister d ) { v9_only(); emit_int32( op(ldst_op) | fd(d, w) | alt_op3(ldf_op3 | alt_bit_op3, w) | rs1(s1) | imm_asi(ia) | rs2(s2) ); } 927 void ldfa( FloatRegisterImpl::Width w, Register s1, int simm13a, FloatRegister d ) { v9_only(); emit_int32( op(ldst_op) | fd(d, w) | alt_op3(ldf_op3 | alt_bit_op3, w) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 928 929 // pp 175, lduw is ld on v8 930 931 inline void ldsb( Register s1, Register s2, Register d ); 932 inline void ldsb( Register s1, int simm13a, Register d); 933 inline void ldsh( Register s1, Register s2, Register d ); 934 inline void ldsh( Register s1, int simm13a, Register d); 935 inline void ldsw( Register s1, Register s2, Register d ); 936 inline void ldsw( Register s1, int simm13a, Register d); 937 inline void ldub( Register s1, Register s2, Register d ); 938 inline void ldub( Register s1, int simm13a, Register d); 939 inline void lduh( Register s1, Register s2, Register d ); 940 inline void lduh( Register s1, int simm13a, Register d); 941 inline void lduw( Register s1, Register s2, Register d ); 942 inline void lduw( Register s1, int simm13a, Register d); 943 inline void ldx( Register s1, Register s2, Register d ); 944 inline void ldx( Register s1, int simm13a, Register d); 945 inline void ldd( Register s1, Register s2, Register d ); 946 inline void ldd( Register s1, int simm13a, Register d); 947 948 // pp 177 949 950 void ldsba( Register s1, Register s2, int ia, Register d ) { emit_int32( op(ldst_op) | rd(d) | op3(ldsb_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); } 951 void ldsba( Register s1, int simm13a, Register d ) { emit_int32( op(ldst_op) | rd(d) | op3(ldsb_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 952 void ldsha( Register s1, Register s2, int ia, Register d ) { emit_int32( op(ldst_op) | rd(d) | op3(ldsh_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); } 953 void ldsha( Register s1, int simm13a, Register d ) { emit_int32( op(ldst_op) | rd(d) | op3(ldsh_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 954 void ldswa( Register s1, Register s2, int ia, Register d ) { v9_only(); emit_int32( op(ldst_op) | rd(d) | op3(ldsw_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); } 955 void ldswa( Register s1, int simm13a, Register d ) { v9_only(); emit_int32( op(ldst_op) | rd(d) | op3(ldsw_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 956 void lduba( Register s1, Register s2, int ia, Register d ) { emit_int32( op(ldst_op) | rd(d) | op3(ldub_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); } 957 void lduba( Register s1, int simm13a, Register d ) { emit_int32( op(ldst_op) | rd(d) | op3(ldub_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 958 void lduha( Register s1, Register s2, int ia, Register d ) { emit_int32( op(ldst_op) | rd(d) | op3(lduh_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); } 959 void lduha( Register s1, int simm13a, Register d ) { emit_int32( op(ldst_op) | rd(d) | op3(lduh_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 960 void lduwa( Register s1, Register s2, int ia, Register d ) { emit_int32( op(ldst_op) | rd(d) | op3(lduw_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); } 961 void lduwa( Register s1, int simm13a, Register d ) { emit_int32( op(ldst_op) | rd(d) | op3(lduw_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 962 void ldxa( Register s1, Register s2, int ia, Register d ) { v9_only(); emit_int32( op(ldst_op) | rd(d) | op3(ldx_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); } 963 void ldxa( Register s1, int simm13a, Register d ) { v9_only(); emit_int32( op(ldst_op) | rd(d) | op3(ldx_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 964 965 // pp 181 966 967 void and3( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(and_op3 ) | rs1(s1) | rs2(s2) ); } 968 void and3( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(and_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 969 void andcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(and_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); } 970 void andcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(and_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 971 void andn( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(andn_op3 ) | rs1(s1) | rs2(s2) ); } 972 void andn( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(andn_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 973 void andncc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(andn_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); } 974 void andncc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(andn_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 975 void or3( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(or_op3 ) | rs1(s1) | rs2(s2) ); } 976 void or3( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(or_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 977 void orcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(or_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); } 978 void orcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(or_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 979 void orn( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(orn_op3) | rs1(s1) | rs2(s2) ); } 980 void orn( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(orn_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 981 void orncc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(orn_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); } 982 void orncc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(orn_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 983 void xor3( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(xor_op3 ) | rs1(s1) | rs2(s2) ); } 984 void xor3( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(xor_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 985 void xorcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(xor_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); } 986 void xorcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(xor_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 987 void xnor( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(xnor_op3 ) | rs1(s1) | rs2(s2) ); } 988 void xnor( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(xnor_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 989 void xnorcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(xnor_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); } 990 void xnorcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(xnor_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 991 992 // pp 183 993 994 void membar( Membar_mask_bits const7a ) { v9_only(); emit_int32( op(arith_op) | op3(membar_op3) | rs1(O7) | immed(true) | u_field( int(const7a), 6, 0)); } 995 996 // pp 185 997 998 void fmov( FloatRegisterImpl::Width w, Condition c, bool floatCC, CC cca, FloatRegister s2, FloatRegister d ) { v9_only(); emit_int32( op(arith_op) | fd(d, w) | op3(fpop2_op3) | cond_mov(c) | opf_cc(cca, floatCC) | opf_low6(w) | fs2(s2, w)); } 999 1000 // pp 189 1001 1002 void fmov( FloatRegisterImpl::Width w, RCondition c, Register s1, FloatRegister s2, FloatRegister d ) { v9_only(); emit_int32( op(arith_op) | fd(d, w) | op3(fpop2_op3) | rs1(s1) | rcond(c) | opf_low5(4 + w) | fs2(s2, w)); } 1003 1004 // pp 191 1005 1006 void movcc( Condition c, bool floatCC, CC cca, Register s2, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(movcc_op3) | mov_cc(cca, floatCC) | cond_mov(c) | rs2(s2) ); } 1007 void movcc( Condition c, bool floatCC, CC cca, int simm11a, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(movcc_op3) | mov_cc(cca, floatCC) | cond_mov(c) | immed(true) | simm(simm11a, 11) ); } 1008 1009 // pp 195 1010 1011 void movr( RCondition c, Register s1, Register s2, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(movr_op3) | rs1(s1) | rcond(c) | rs2(s2) ); } 1012 void movr( RCondition c, Register s1, int simm10a, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(movr_op3) | rs1(s1) | rcond(c) | immed(true) | simm(simm10a, 10) ); } 1013 1014 // pp 196 1015 1016 void mulx( Register s1, Register s2, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(mulx_op3 ) | rs1(s1) | rs2(s2) ); } 1017 void mulx( Register s1, int simm13a, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(mulx_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 1018 void sdivx( Register s1, Register s2, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(sdivx_op3) | rs1(s1) | rs2(s2) ); } 1019 void sdivx( Register s1, int simm13a, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(sdivx_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 1020 void udivx( Register s1, Register s2, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(udivx_op3) | rs1(s1) | rs2(s2) ); } 1021 void udivx( Register s1, int simm13a, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(udivx_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 1022 1023 // pp 197 1024 1025 void umul( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(umul_op3 ) | rs1(s1) | rs2(s2) ); } 1026 void umul( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(umul_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 1027 void smul( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(smul_op3 ) | rs1(s1) | rs2(s2) ); } 1028 void smul( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(smul_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 1029 void umulcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(umul_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); } 1030 void umulcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(umul_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 1031 void smulcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(smul_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); } 1032 void smulcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(smul_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 1033 1034 // pp 201 1035 1036 void nop(int count = 1) { 1037 for(int i = 0; i < count; i++) 1038 emit_int32( op(branch_op) | op2(sethi_op2) ); 1039 } 1040 1041 void sw_count() { emit_int32( op(branch_op) | op2(sethi_op2) | 0x3f0 ); } 1042 1043 // pp 202 1044 1045 void popc( Register s, Register d) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(popc_op3) | rs2(s)); } 1046 void popc( int simm13a, Register d) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(popc_op3) | immed(true) | simm(simm13a, 13)); } 1047 1048 // pp 203 1049 1050 void prefetch( Register s1, Register s2, PrefetchFcn f) { v9_only(); emit_int32( op(ldst_op) | fcn(f) | op3(prefetch_op3) | rs1(s1) | rs2(s2) ); } 1051 void prefetch( Register s1, int simm13a, PrefetchFcn f) { v9_only(); emit_data( op(ldst_op) | fcn(f) | op3(prefetch_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); } 1052 1053 void prefetcha( Register s1, Register s2, int ia, PrefetchFcn f ) { v9_only(); emit_int32( op(ldst_op) | fcn(f) | op3(prefetch_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); } 1054 void prefetcha( Register s1, int simm13a, PrefetchFcn f ) { v9_only(); emit_int32( op(ldst_op) | fcn(f) | op3(prefetch_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 1055 1056 // pp 208 1057 1058 // not implementing read privileged register 1059 1060 inline void rdy( Register d) { v9_dep(); emit_int32( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(0, 18, 14)); } 1061 inline void rdccr( Register d) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(2, 18, 14)); } 1062 inline void rdasi( Register d) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(3, 18, 14)); } 1063 inline void rdtick( Register d) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(4, 18, 14)); } // Spoon! 1064 inline void rdpc( Register d) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(5, 18, 14)); } 1065 inline void rdfprs( Register d) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(6, 18, 14)); } 1066 1067 // pp 213 1068 1069 inline void rett( Register s1, Register s2); 1070 inline void rett( Register s1, int simm13a, relocInfo::relocType rt = relocInfo::none); 1071 1072 // pp 214 1073 1074 void save( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(save_op3) | rs1(s1) | rs2(s2) ); } 1075 void save( Register s1, int simm13a, Register d ) { 1076 // make sure frame is at least large enough for the register save area 1077 assert(-simm13a >= 16 * wordSize, "frame too small"); 1078 emit_int32( op(arith_op) | rd(d) | op3(save_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); 1079 } 1080 1081 void restore( Register s1 = G0, Register s2 = G0, Register d = G0 ) { emit_int32( op(arith_op) | rd(d) | op3(restore_op3) | rs1(s1) | rs2(s2) ); } 1082 void restore( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(restore_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 1083 1084 // pp 216 1085 1086 void saved() { v9_only(); emit_int32( op(arith_op) | fcn(0) | op3(saved_op3)); } 1087 void restored() { v9_only(); emit_int32( op(arith_op) | fcn(1) | op3(saved_op3)); } 1088 1089 // pp 217 1090 1091 inline void sethi( int imm22a, Register d, RelocationHolder const& rspec = RelocationHolder() ); 1092 // pp 218 1093 1094 void sll( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sll_op3) | rs1(s1) | sx(0) | rs2(s2) ); } 1095 void sll( Register s1, int imm5a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sll_op3) | rs1(s1) | sx(0) | immed(true) | u_field(imm5a, 4, 0) ); } 1096 void srl( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(srl_op3) | rs1(s1) | sx(0) | rs2(s2) ); } 1097 void srl( Register s1, int imm5a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(srl_op3) | rs1(s1) | sx(0) | immed(true) | u_field(imm5a, 4, 0) ); } 1098 void sra( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sra_op3) | rs1(s1) | sx(0) | rs2(s2) ); } 1099 void sra( Register s1, int imm5a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sra_op3) | rs1(s1) | sx(0) | immed(true) | u_field(imm5a, 4, 0) ); } 1100 1101 void sllx( Register s1, Register s2, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(sll_op3) | rs1(s1) | sx(1) | rs2(s2) ); } 1102 void sllx( Register s1, int imm6a, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(sll_op3) | rs1(s1) | sx(1) | immed(true) | u_field(imm6a, 5, 0) ); } 1103 void srlx( Register s1, Register s2, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(srl_op3) | rs1(s1) | sx(1) | rs2(s2) ); } 1104 void srlx( Register s1, int imm6a, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(srl_op3) | rs1(s1) | sx(1) | immed(true) | u_field(imm6a, 5, 0) ); } 1105 void srax( Register s1, Register s2, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(sra_op3) | rs1(s1) | sx(1) | rs2(s2) ); } 1106 void srax( Register s1, int imm6a, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(sra_op3) | rs1(s1) | sx(1) | immed(true) | u_field(imm6a, 5, 0) ); } 1107 1108 // pp 220 1109 1110 void sir( int simm13a ) { emit_int32( op(arith_op) | fcn(15) | op3(sir_op3) | immed(true) | simm(simm13a, 13)); } 1111 1112 // pp 221 1113 1114 void stbar() { emit_int32( op(arith_op) | op3(membar_op3) | u_field(15, 18, 14)); } 1115 1116 // pp 222 1117 1118 inline void stf( FloatRegisterImpl::Width w, FloatRegister d, Register s1, Register s2); 1119 inline void stf( FloatRegisterImpl::Width w, FloatRegister d, Register s1, int simm13a); 1120 1121 inline void stfsr( Register s1, Register s2 ); 1122 inline void stfsr( Register s1, int simm13a); 1123 inline void stxfsr( Register s1, Register s2 ); 1124 inline void stxfsr( Register s1, int simm13a); 1125 1126 // pp 224 1127 1128 void stfa( FloatRegisterImpl::Width w, FloatRegister d, Register s1, Register s2, int ia ) { v9_only(); emit_int32( op(ldst_op) | fd(d, w) | alt_op3(stf_op3 | alt_bit_op3, w) | rs1(s1) | imm_asi(ia) | rs2(s2) ); } 1129 void stfa( FloatRegisterImpl::Width w, FloatRegister d, Register s1, int simm13a ) { v9_only(); emit_int32( op(ldst_op) | fd(d, w) | alt_op3(stf_op3 | alt_bit_op3, w) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 1130 1131 // p 226 1132 1133 inline void stb( Register d, Register s1, Register s2 ); 1134 inline void stb( Register d, Register s1, int simm13a); 1135 inline void sth( Register d, Register s1, Register s2 ); 1136 inline void sth( Register d, Register s1, int simm13a); 1137 inline void stw( Register d, Register s1, Register s2 ); 1138 inline void stw( Register d, Register s1, int simm13a); 1139 inline void stx( Register d, Register s1, Register s2 ); 1140 inline void stx( Register d, Register s1, int simm13a); 1141 inline void std( Register d, Register s1, Register s2 ); 1142 inline void std( Register d, Register s1, int simm13a); 1143 1144 // pp 177 1145 1146 void stba( Register d, Register s1, Register s2, int ia ) { emit_int32( op(ldst_op) | rd(d) | op3(stb_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); } 1147 void stba( Register d, Register s1, int simm13a ) { emit_int32( op(ldst_op) | rd(d) | op3(stb_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 1148 void stha( Register d, Register s1, Register s2, int ia ) { emit_int32( op(ldst_op) | rd(d) | op3(sth_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); } 1149 void stha( Register d, Register s1, int simm13a ) { emit_int32( op(ldst_op) | rd(d) | op3(sth_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 1150 void stwa( Register d, Register s1, Register s2, int ia ) { emit_int32( op(ldst_op) | rd(d) | op3(stw_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); } 1151 void stwa( Register d, Register s1, int simm13a ) { emit_int32( op(ldst_op) | rd(d) | op3(stw_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 1152 void stxa( Register d, Register s1, Register s2, int ia ) { v9_only(); emit_int32( op(ldst_op) | rd(d) | op3(stx_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); } 1153 void stxa( Register d, Register s1, int simm13a ) { v9_only(); emit_int32( op(ldst_op) | rd(d) | op3(stx_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 1154 void stda( Register d, Register s1, Register s2, int ia ) { emit_int32( op(ldst_op) | rd(d) | op3(std_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); } 1155 void stda( Register d, Register s1, int simm13a ) { emit_int32( op(ldst_op) | rd(d) | op3(std_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 1156 1157 // pp 230 1158 1159 void sub( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sub_op3 ) | rs1(s1) | rs2(s2) ); } 1160 void sub( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sub_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 1161 1162 void subcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sub_op3 | cc_bit_op3 ) | rs1(s1) | rs2(s2) ); } 1163 void subcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sub_op3 | cc_bit_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 1164 void subc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(subc_op3 ) | rs1(s1) | rs2(s2) ); } 1165 void subc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(subc_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 1166 void subccc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(subc_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); } 1167 void subccc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(subc_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 1168 1169 // pp 231 1170 1171 inline void swap( Register s1, Register s2, Register d ); 1172 inline void swap( Register s1, int simm13a, Register d); 1173 1174 // pp 232 1175 1176 void swapa( Register s1, Register s2, int ia, Register d ) { v9_dep(); emit_int32( op(ldst_op) | rd(d) | op3(swap_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); } 1177 void swapa( Register s1, int simm13a, Register d ) { v9_dep(); emit_int32( op(ldst_op) | rd(d) | op3(swap_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 1178 1179 // pp 234, note op in book is wrong, see pp 268 1180 1181 void taddcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(taddcc_op3 ) | rs1(s1) | rs2(s2) ); } 1182 void taddcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(taddcc_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 1183 1184 // pp 235 1185 1186 void tsubcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(tsubcc_op3 ) | rs1(s1) | rs2(s2) ); } 1187 void tsubcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(tsubcc_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 1188 1189 // pp 237 1190 1191 void trap( Condition c, CC cc, Register s1, Register s2 ) { emit_int32( op(arith_op) | cond(c) | op3(trap_op3) | rs1(s1) | trapcc(cc) | rs2(s2)); } 1192 void trap( Condition c, CC cc, Register s1, int trapa ) { emit_int32( op(arith_op) | cond(c) | op3(trap_op3) | rs1(s1) | trapcc(cc) | immed(true) | u_field(trapa, 6, 0)); } 1193 // simple uncond. trap 1194 void trap( int trapa ) { trap( always, icc, G0, trapa ); } 1195 1196 // pp 239 omit write priv register for now 1197 1198 inline void wry( Register d) { v9_dep(); emit_int32( op(arith_op) | rs1(d) | op3(wrreg_op3) | u_field(0, 29, 25)); } 1199 inline void wrccr(Register s) { v9_only(); emit_int32( op(arith_op) | rs1(s) | op3(wrreg_op3) | u_field(2, 29, 25)); } 1200 inline void wrccr(Register s, int simm13a) { v9_only(); emit_int32( op(arith_op) | 1201 rs1(s) | 1202 op3(wrreg_op3) | 1203 u_field(2, 29, 25) | 1204 immed(true) | 1205 simm(simm13a, 13)); } 1206 inline void wrasi(Register d) { v9_only(); emit_int32( op(arith_op) | rs1(d) | op3(wrreg_op3) | u_field(3, 29, 25)); } 1207 // wrasi(d, imm) stores (d xor imm) to asi 1208 inline void wrasi(Register d, int simm13a) { v9_only(); emit_int32( op(arith_op) | rs1(d) | op3(wrreg_op3) | 1209 u_field(3, 29, 25) | immed(true) | simm(simm13a, 13)); } 1210 inline void wrfprs( Register d) { v9_only(); emit_int32( op(arith_op) | rs1(d) | op3(wrreg_op3) | u_field(6, 29, 25)); } 1211 1212 // VIS1 instructions 1213 1214 void alignaddr( Register s1, Register s2, Register d ) { vis1_only(); emit_int32( op(arith_op) | rd(d) | op3(alignaddr_op3) | rs1(s1) | opf(alignaddr_opf) | rs2(s2)); } 1215 1216 void faligndata( FloatRegister s1, FloatRegister s2, FloatRegister d ) { vis1_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(faligndata_op3) | fs1(s1, FloatRegisterImpl::D) | opf(faligndata_opf) | fs2(s2, FloatRegisterImpl::D)); } 1217 1218 void fzero( FloatRegisterImpl::Width w, FloatRegister d ) { vis1_only(); emit_int32( op(arith_op) | fd(d, w) | op3(fzero_op3) | opf(0x62 - w)); } 1219 1220 void fsrc2( FloatRegisterImpl::Width w, FloatRegister s2, FloatRegister d ) { vis1_only(); emit_int32( op(arith_op) | fd(d, w) | op3(fsrc_op3) | opf(0x7A - w) | fs2(s2, w)); } 1221 1222 void fnot1( FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister d ) { vis1_only(); emit_int32( op(arith_op) | fd(d, w) | op3(fnot_op3) | fs1(s1, w) | opf(0x6C - w)); } 1223 1224 void fpmerge( FloatRegister s1, FloatRegister s2, FloatRegister d ) { vis1_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(0x36) | fs1(s1, FloatRegisterImpl::S) | opf(0x4b) | fs2(s2, FloatRegisterImpl::S)); } 1225 1226 void stpartialf( Register s1, Register s2, FloatRegister d, int ia = -1 ) { vis1_only(); emit_int32( op(ldst_op) | fd(d, FloatRegisterImpl::D) | op3(stpartialf_op3) | rs1(s1) | imm_asi(ia) | rs2(s2)); } 1227 1228 // VIS2 instructions 1229 1230 void edge8n( Register s1, Register s2, Register d ) { vis2_only(); emit_int32( op(arith_op) | rd(d) | op3(edge_op3) | rs1(s1) | opf(edge8n_opf) | rs2(s2)); } 1231 1232 // VIS3 instructions 1233 1234 void movstosw( FloatRegister s, Register d ) { vis3_only(); emit_int32( op(arith_op) | rd(d) | op3(mftoi_op3) | opf(mstosw_opf) | fs2(s, FloatRegisterImpl::S)); } 1235 void movstouw( FloatRegister s, Register d ) { vis3_only(); emit_int32( op(arith_op) | rd(d) | op3(mftoi_op3) | opf(mstouw_opf) | fs2(s, FloatRegisterImpl::S)); } 1236 void movdtox( FloatRegister s, Register d ) { vis3_only(); emit_int32( op(arith_op) | rd(d) | op3(mftoi_op3) | opf(mdtox_opf) | fs2(s, FloatRegisterImpl::D)); } 1237 1238 void movwtos( Register s, FloatRegister d ) { vis3_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::S) | op3(mftoi_op3) | opf(mwtos_opf) | rs2(s)); } 1239 void movxtod( Register s, FloatRegister d ) { vis3_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(mftoi_op3) | opf(mxtod_opf) | rs2(s)); } 1240 1241 void xmulx(Register s1, Register s2, Register d) { vis3_only(); emit_int32( op(arith_op) | rd(d) | op3(xmulx_op3) | rs1(s1) | opf(xmulx_opf) | rs2(s2)); } 1242 void xmulxhi(Register s1, Register s2, Register d) { vis3_only(); emit_int32( op(arith_op) | rd(d) | op3(xmulx_op3) | rs1(s1) | opf(xmulxhi_opf) | rs2(s2)); } 1243 1244 // Crypto SHA instructions 1245 1246 void sha1() { sha1_only(); emit_int32( op(arith_op) | op3(sha_op3) | opf(sha1_opf)); } 1247 void sha256() { sha256_only(); emit_int32( op(arith_op) | op3(sha_op3) | opf(sha256_opf)); } 1248 void sha512() { sha512_only(); emit_int32( op(arith_op) | op3(sha_op3) | opf(sha512_opf)); } 1249 1250 // CRC32C instruction 1251 1252 void crc32c( FloatRegister s1, FloatRegister s2, FloatRegister d ) { crc32c_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(crc32c_op3) | fs1(s1, FloatRegisterImpl::D) | opf(crc32c_opf) | fs2(s2, FloatRegisterImpl::D)); } 1253 1254 // Creation 1255 Assembler(CodeBuffer* code) : AbstractAssembler(code) { 1256 #ifdef CHECK_DELAY 1257 delay_state = no_delay; 1258 #endif 1259 } 1260 }; 1261 1262 #endif // CPU_SPARC_VM_ASSEMBLER_SPARC_HPP