1 /*
2 * Copyright (c) 2000, 2014, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "c1/c1_Compilation.hpp"
27 #include "c1/c1_Instruction.hpp"
28 #include "c1/c1_InstructionPrinter.hpp"
29 #include "c1/c1_LIRAssembler.hpp"
30 #include "c1/c1_MacroAssembler.hpp"
31 #include "c1/c1_ValueStack.hpp"
32 #include "ci/ciInstance.hpp"
33 #include "runtime/os.hpp"
34
35 void LIR_Assembler::patching_epilog(PatchingStub* patch, LIR_PatchCode patch_code, Register obj, CodeEmitInfo* info) {
36 // We must have enough patching space so that call can be inserted.
37 // We cannot use fat nops here, since the concurrent code rewrite may transiently
38 // create the illegal instruction sequence.
39 while ((intx) _masm->pc() - (intx) patch->pc_start() < NativeCall::instruction_size) {
40 _masm->nop();
41 }
42 patch->install(_masm, patch_code, obj, info);
43 append_code_stub(patch);
44
45 #ifdef ASSERT
46 Bytecodes::Code code = info->scope()->method()->java_code_at_bci(info->stack()->bci());
47 if (patch->id() == PatchingStub::access_field_id) {
48 switch (code) {
49 case Bytecodes::_putstatic:
50 case Bytecodes::_getstatic:
51 case Bytecodes::_putfield:
52 case Bytecodes::_getfield:
53 break;
54 default:
55 ShouldNotReachHere();
56 }
57 } else if (patch->id() == PatchingStub::load_klass_id) {
58 switch (code) {
59 case Bytecodes::_new:
60 case Bytecodes::_anewarray:
61 case Bytecodes::_multianewarray:
62 case Bytecodes::_instanceof:
63 case Bytecodes::_checkcast:
64 break;
65 default:
66 ShouldNotReachHere();
67 }
68 } else if (patch->id() == PatchingStub::load_mirror_id) {
69 switch (code) {
70 case Bytecodes::_putstatic:
71 case Bytecodes::_getstatic:
72 case Bytecodes::_ldc:
73 case Bytecodes::_ldc_w:
74 break;
75 default:
76 ShouldNotReachHere();
77 }
78 } else if (patch->id() == PatchingStub::load_appendix_id) {
79 Bytecodes::Code bc_raw = info->scope()->method()->raw_code_at_bci(info->stack()->bci());
80 assert(Bytecodes::has_optional_appendix(bc_raw), "unexpected appendix resolution");
81 } else {
82 ShouldNotReachHere();
83 }
84 #endif
85 }
86
87 PatchingStub::PatchID LIR_Assembler::patching_id(CodeEmitInfo* info) {
88 IRScope* scope = info->scope();
89 Bytecodes::Code bc_raw = scope->method()->raw_code_at_bci(info->stack()->bci());
90 if (Bytecodes::has_optional_appendix(bc_raw)) {
91 return PatchingStub::load_appendix_id;
92 }
93 return PatchingStub::load_mirror_id;
94 }
95
96 //---------------------------------------------------------------
97
98
99 LIR_Assembler::LIR_Assembler(Compilation* c):
100 _compilation(c)
101 , _masm(c->masm())
102 , _bs(Universe::heap()->barrier_set())
103 , _frame_map(c->frame_map())
104 , _current_block(NULL)
105 , _pending_non_safepoint(NULL)
106 , _pending_non_safepoint_offset(0)
107 {
108 _slow_case_stubs = new CodeStubList();
109 }
110
111
112 LIR_Assembler::~LIR_Assembler() {
113 }
114
115
116 void LIR_Assembler::check_codespace() {
117 CodeSection* cs = _masm->code_section();
118 if (cs->remaining() < (int)(NOT_LP64(1*K)LP64_ONLY(2*K))) {
119 BAILOUT("CodeBuffer overflow");
120 }
121 }
122
123
124 void LIR_Assembler::append_code_stub(CodeStub* stub) {
125 _slow_case_stubs->append(stub);
126 }
127
128 void LIR_Assembler::emit_stubs(CodeStubList* stub_list) {
129 for (int m = 0; m < stub_list->length(); m++) {
130 CodeStub* s = (*stub_list)[m];
131
132 check_codespace();
133 CHECK_BAILOUT();
134
135 #ifndef PRODUCT
136 if (CommentedAssembly) {
137 stringStream st;
138 s->print_name(&st);
139 st.print(" slow case");
140 _masm->block_comment(st.as_string());
141 }
142 #endif
143 s->emit_code(this);
144 #ifdef ASSERT
145 s->assert_no_unbound_labels();
146 #endif
147 }
148 }
149
150
151 void LIR_Assembler::emit_slow_case_stubs() {
152 emit_stubs(_slow_case_stubs);
153 }
154
155
156 bool LIR_Assembler::needs_icache(ciMethod* method) const {
157 return !method->is_static();
158 }
159
160
161 int LIR_Assembler::code_offset() const {
162 return _masm->offset();
163 }
164
165
166 address LIR_Assembler::pc() const {
167 return _masm->pc();
168 }
169
170 // To bang the stack of this compiled method we use the stack size
171 // that the interpreter would need in case of a deoptimization. This
172 // removes the need to bang the stack in the deoptimization blob which
173 // in turn simplifies stack overflow handling.
174 int LIR_Assembler::bang_size_in_bytes() const {
175 return MAX2(initial_frame_size_in_bytes() + os::extra_bang_size_in_bytes(), _compilation->interpreter_frame_size());
176 }
177
178 void LIR_Assembler::emit_exception_entries(ExceptionInfoList* info_list) {
179 for (int i = 0; i < info_list->length(); i++) {
180 XHandlers* handlers = info_list->at(i)->exception_handlers();
181
182 for (int j = 0; j < handlers->length(); j++) {
183 XHandler* handler = handlers->handler_at(j);
184 assert(handler->lir_op_id() != -1, "handler not processed by LinearScan");
185 assert(handler->entry_code() == NULL ||
186 handler->entry_code()->instructions_list()->last()->code() == lir_branch ||
187 handler->entry_code()->instructions_list()->last()->code() == lir_delay_slot, "last operation must be branch");
188
189 if (handler->entry_pco() == -1) {
190 // entry code not emitted yet
191 if (handler->entry_code() != NULL && handler->entry_code()->instructions_list()->length() > 1) {
192 handler->set_entry_pco(code_offset());
193 if (CommentedAssembly) {
194 _masm->block_comment("Exception adapter block");
195 }
196 emit_lir_list(handler->entry_code());
197 } else {
198 handler->set_entry_pco(handler->entry_block()->exception_handler_pco());
199 }
200
201 assert(handler->entry_pco() != -1, "must be set now");
202 }
203 }
204 }
205 }
206
207
208 void LIR_Assembler::emit_code(BlockList* hir) {
209 if (PrintLIR) {
210 print_LIR(hir);
211 }
212
213 int n = hir->length();
214 for (int i = 0; i < n; i++) {
215 emit_block(hir->at(i));
216 CHECK_BAILOUT();
217 }
218
219 flush_debug_info(code_offset());
220
221 DEBUG_ONLY(check_no_unbound_labels());
222 }
223
224
225 void LIR_Assembler::emit_block(BlockBegin* block) {
226 if (block->is_set(BlockBegin::backward_branch_target_flag)) {
227 align_backward_branch_target();
228 }
229
230 // if this block is the start of an exception handler, record the
231 // PC offset of the first instruction for later construction of
232 // the ExceptionHandlerTable
233 if (block->is_set(BlockBegin::exception_entry_flag)) {
234 block->set_exception_handler_pco(code_offset());
235 }
236
237 #ifndef PRODUCT
238 if (PrintLIRWithAssembly) {
239 // don't print Phi's
240 InstructionPrinter ip(false);
241 block->print(ip);
242 }
243 #endif /* PRODUCT */
244
245 assert(block->lir() != NULL, "must have LIR");
246 X86_ONLY(assert(_masm->rsp_offset() == 0, "frame size should be fixed"));
247
248 #ifndef PRODUCT
249 if (CommentedAssembly) {
250 stringStream st;
251 st.print_cr(" block B%d [%d, %d]", block->block_id(), block->bci(), block->end()->printable_bci());
252 _masm->block_comment(st.as_string());
253 }
254 #endif
255
256 emit_lir_list(block->lir());
257
258 X86_ONLY(assert(_masm->rsp_offset() == 0, "frame size should be fixed"));
259 }
260
261
262 void LIR_Assembler::emit_lir_list(LIR_List* list) {
263 peephole(list);
264
265 int n = list->length();
266 for (int i = 0; i < n; i++) {
267 LIR_Op* op = list->at(i);
268
269 check_codespace();
270 CHECK_BAILOUT();
271
272 #ifndef PRODUCT
273 if (CommentedAssembly) {
274 // Don't record out every op since that's too verbose. Print
275 // branches since they include block and stub names. Also print
276 // patching moves since they generate funny looking code.
277 if (op->code() == lir_branch ||
278 (op->code() == lir_move && op->as_Op1()->patch_code() != lir_patch_none)) {
279 stringStream st;
280 op->print_on(&st);
281 _masm->block_comment(st.as_string());
282 }
283 }
284 if (PrintLIRWithAssembly) {
285 // print out the LIR operation followed by the resulting assembly
286 list->at(i)->print(); tty->cr();
287 }
288 #endif /* PRODUCT */
289
290 op->emit_code(this);
291
292 if (compilation()->debug_info_recorder()->recording_non_safepoints()) {
293 process_debug_info(op);
294 }
295
296 #ifndef PRODUCT
297 if (PrintLIRWithAssembly) {
298 _masm->code()->decode();
299 }
300 #endif /* PRODUCT */
301 }
302 }
303
304 #ifdef ASSERT
305 void LIR_Assembler::check_no_unbound_labels() {
306 CHECK_BAILOUT();
307
308 for (int i = 0; i < _branch_target_blocks.length() - 1; i++) {
309 if (!_branch_target_blocks.at(i)->label()->is_bound()) {
310 tty->print_cr("label of block B%d is not bound", _branch_target_blocks.at(i)->block_id());
311 assert(false, "unbound label");
312 }
313 }
314 }
315 #endif
316
317 //----------------------------------debug info--------------------------------
318
319
320 void LIR_Assembler::add_debug_info_for_branch(CodeEmitInfo* info) {
321 int pc_offset = code_offset();
322 flush_debug_info(pc_offset);
323 info->record_debug_info(compilation()->debug_info_recorder(), pc_offset);
324 if (info->exception_handlers() != NULL) {
325 compilation()->add_exception_handlers_for_pco(pc_offset, info->exception_handlers());
326 }
327 }
328
329
330 void LIR_Assembler::add_call_info(int pc_offset, CodeEmitInfo* cinfo) {
331 flush_debug_info(pc_offset);
332 cinfo->record_debug_info(compilation()->debug_info_recorder(), pc_offset);
333 if (cinfo->exception_handlers() != NULL) {
334 compilation()->add_exception_handlers_for_pco(pc_offset, cinfo->exception_handlers());
335 }
336 }
337
338 static ValueStack* debug_info(Instruction* ins) {
339 StateSplit* ss = ins->as_StateSplit();
340 if (ss != NULL) return ss->state();
341 return ins->state_before();
342 }
343
344 void LIR_Assembler::process_debug_info(LIR_Op* op) {
345 Instruction* src = op->source();
346 if (src == NULL) return;
347 int pc_offset = code_offset();
348 if (_pending_non_safepoint == src) {
349 _pending_non_safepoint_offset = pc_offset;
350 return;
351 }
352 ValueStack* vstack = debug_info(src);
353 if (vstack == NULL) return;
354 if (_pending_non_safepoint != NULL) {
355 // Got some old debug info. Get rid of it.
356 if (debug_info(_pending_non_safepoint) == vstack) {
357 _pending_non_safepoint_offset = pc_offset;
358 return;
359 }
360 if (_pending_non_safepoint_offset < pc_offset) {
361 record_non_safepoint_debug_info();
362 }
363 _pending_non_safepoint = NULL;
364 }
365 // Remember the debug info.
366 if (pc_offset > compilation()->debug_info_recorder()->last_pc_offset()) {
367 _pending_non_safepoint = src;
368 _pending_non_safepoint_offset = pc_offset;
369 }
370 }
371
372 // Index caller states in s, where 0 is the oldest, 1 its callee, etc.
373 // Return NULL if n is too large.
374 // Returns the caller_bci for the next-younger state, also.
375 static ValueStack* nth_oldest(ValueStack* s, int n, int& bci_result) {
376 ValueStack* t = s;
377 for (int i = 0; i < n; i++) {
378 if (t == NULL) break;
379 t = t->caller_state();
380 }
381 if (t == NULL) return NULL;
382 for (;;) {
383 ValueStack* tc = t->caller_state();
384 if (tc == NULL) return s;
385 t = tc;
386 bci_result = tc->bci();
387 s = s->caller_state();
388 }
389 }
390
391 void LIR_Assembler::record_non_safepoint_debug_info() {
392 int pc_offset = _pending_non_safepoint_offset;
393 ValueStack* vstack = debug_info(_pending_non_safepoint);
394 int bci = vstack->bci();
395
396 DebugInformationRecorder* debug_info = compilation()->debug_info_recorder();
397 assert(debug_info->recording_non_safepoints(), "sanity");
398
399 debug_info->add_non_safepoint(pc_offset);
400
401 // Visit scopes from oldest to youngest.
402 for (int n = 0; ; n++) {
403 int s_bci = bci;
404 ValueStack* s = nth_oldest(vstack, n, s_bci);
405 if (s == NULL) break;
406 IRScope* scope = s->scope();
407 //Always pass false for reexecute since these ScopeDescs are never used for deopt
408 debug_info->describe_scope(pc_offset, scope->method(), s->bci(), false/*reexecute*/);
409 }
410
411 debug_info->end_non_safepoint(pc_offset);
412 }
413
414
415 void LIR_Assembler::add_debug_info_for_null_check_here(CodeEmitInfo* cinfo) {
416 add_debug_info_for_null_check(code_offset(), cinfo);
417 }
418
419 void LIR_Assembler::add_debug_info_for_null_check(int pc_offset, CodeEmitInfo* cinfo) {
420 ImplicitNullCheckStub* stub = new ImplicitNullCheckStub(pc_offset, cinfo);
421 append_code_stub(stub);
422 }
423
424 void LIR_Assembler::add_debug_info_for_div0_here(CodeEmitInfo* info) {
425 add_debug_info_for_div0(code_offset(), info);
426 }
427
428 void LIR_Assembler::add_debug_info_for_div0(int pc_offset, CodeEmitInfo* cinfo) {
429 DivByZeroStub* stub = new DivByZeroStub(pc_offset, cinfo);
430 append_code_stub(stub);
431 }
432
433 void LIR_Assembler::emit_rtcall(LIR_OpRTCall* op) {
434 rt_call(op->result_opr(), op->addr(), op->arguments(), op->tmp(), op->info());
435 }
436
437
438 void LIR_Assembler::emit_call(LIR_OpJavaCall* op) {
439 verify_oop_map(op->info());
440
441 if (os::is_MP()) {
442 // must align calls sites, otherwise they can't be updated atomically on MP hardware
443 align_call(op->code());
444 }
445
446 // emit the static call stub stuff out of line
447 emit_static_call_stub();
448
449 switch (op->code()) {
450 case lir_static_call:
451 case lir_dynamic_call:
452 call(op, relocInfo::static_call_type);
453 break;
454 case lir_optvirtual_call:
455 call(op, relocInfo::opt_virtual_call_type);
456 break;
457 case lir_icvirtual_call:
458 ic_call(op);
459 break;
460 case lir_virtual_call:
461 vtable_call(op);
462 break;
463 default:
464 fatal(err_msg_res("unexpected op code: %s", op->name()));
465 break;
466 }
467
468 // JSR 292
469 // Record if this method has MethodHandle invokes.
470 if (op->is_method_handle_invoke()) {
471 compilation()->set_has_method_handle_invokes(true);
472 }
473
474 #if defined(X86) && defined(TIERED)
475 // C2 leave fpu stack dirty clean it
476 if (UseSSE < 2) {
477 int i;
478 for ( i = 1; i <= 7 ; i++ ) {
479 ffree(i);
480 }
481 if (!op->result_opr()->is_float_kind()) {
482 ffree(0);
483 }
484 }
485 #endif // X86 && TIERED
486 }
487
488
489 void LIR_Assembler::emit_opLabel(LIR_OpLabel* op) {
490 _masm->bind (*(op->label()));
491 }
492
493
494 void LIR_Assembler::emit_op1(LIR_Op1* op) {
495 switch (op->code()) {
496 case lir_move:
497 if (op->move_kind() == lir_move_volatile) {
498 assert(op->patch_code() == lir_patch_none, "can't patch volatiles");
499 volatile_move_op(op->in_opr(), op->result_opr(), op->type(), op->info());
500 } else {
501 move_op(op->in_opr(), op->result_opr(), op->type(),
502 op->patch_code(), op->info(), op->pop_fpu_stack(),
503 op->move_kind() == lir_move_unaligned,
504 op->move_kind() == lir_move_wide);
505 }
506 break;
507
508 case lir_roundfp: {
509 LIR_OpRoundFP* round_op = op->as_OpRoundFP();
510 roundfp_op(round_op->in_opr(), round_op->tmp(), round_op->result_opr(), round_op->pop_fpu_stack());
511 break;
512 }
513
514 case lir_return:
515 return_op(op->in_opr());
516 break;
517
518 case lir_safepoint:
519 if (compilation()->debug_info_recorder()->last_pc_offset() == code_offset()) {
520 _masm->nop();
521 }
522 safepoint_poll(op->in_opr(), op->info());
523 break;
524
525 case lir_fxch:
526 fxch(op->in_opr()->as_jint());
527 break;
528
529 case lir_fld:
530 fld(op->in_opr()->as_jint());
531 break;
532
533 case lir_ffree:
534 ffree(op->in_opr()->as_jint());
535 break;
536
537 case lir_branch:
538 break;
539
540 case lir_push:
541 push(op->in_opr());
542 break;
543
544 case lir_pop:
545 pop(op->in_opr());
546 break;
547
548 case lir_neg:
549 negate(op->in_opr(), op->result_opr());
550 break;
551
552 case lir_leal:
553 leal(op->in_opr(), op->result_opr());
554 break;
555
556 case lir_null_check:
557 if (GenerateCompilerNullChecks) {
558 add_debug_info_for_null_check_here(op->info());
559
560 if (op->in_opr()->is_single_cpu()) {
561 _masm->null_check(op->in_opr()->as_register());
562 } else {
563 Unimplemented();
564 }
565 }
566 break;
567
568 case lir_monaddr:
569 monitor_address(op->in_opr()->as_constant_ptr()->as_jint(), op->result_opr());
570 break;
571
572 #ifdef SPARC
573 case lir_pack64:
574 pack64(op->in_opr(), op->result_opr());
575 break;
576
577 case lir_unpack64:
578 unpack64(op->in_opr(), op->result_opr());
579 break;
580 #endif
581
582 case lir_unwind:
583 unwind_op(op->in_opr());
584 break;
585
586 default:
587 Unimplemented();
588 break;
589 }
590 }
591
592
593 void LIR_Assembler::emit_op0(LIR_Op0* op) {
594 switch (op->code()) {
595 case lir_word_align: {
596 _masm->align(BytesPerWord);
597 break;
598 }
599
600 case lir_nop:
601 assert(op->info() == NULL, "not supported");
602 _masm->nop();
603 break;
604
605 case lir_label:
606 Unimplemented();
607 break;
608
609 case lir_build_frame:
610 build_frame();
611 break;
612
613 case lir_std_entry:
614 // init offsets
615 offsets()->set_value(CodeOffsets::OSR_Entry, _masm->offset());
616 _masm->align(CodeEntryAlignment);
617 if (needs_icache(compilation()->method())) {
618 check_icache();
619 }
620 offsets()->set_value(CodeOffsets::Verified_Entry, _masm->offset());
621 _masm->verified_entry();
622 build_frame();
623 offsets()->set_value(CodeOffsets::Frame_Complete, _masm->offset());
624 break;
625
626 case lir_osr_entry:
627 offsets()->set_value(CodeOffsets::OSR_Entry, _masm->offset());
628 osr_entry();
629 break;
630
631 case lir_24bit_FPU:
632 set_24bit_FPU();
633 break;
634
635 case lir_reset_FPU:
636 reset_FPU();
637 break;
638
639 case lir_breakpoint:
640 breakpoint();
641 break;
642
643 case lir_fpop_raw:
644 fpop();
645 break;
646
647 case lir_membar:
648 membar();
649 break;
650
651 case lir_membar_acquire:
652 membar_acquire();
653 break;
654
655 case lir_membar_release:
656 membar_release();
657 break;
658
659 case lir_membar_loadload:
660 membar_loadload();
661 break;
662
663 case lir_membar_storestore:
664 membar_storestore();
665 break;
666
667 case lir_membar_loadstore:
668 membar_loadstore();
669 break;
670
671 case lir_membar_storeload:
672 membar_storeload();
673 break;
674
675 case lir_get_thread:
676 get_thread(op->result_opr());
677 break;
678
679 default:
680 ShouldNotReachHere();
681 break;
682 }
683 }
684
685
686 void LIR_Assembler::emit_op2(LIR_Op2* op) {
687 switch (op->code()) {
688 case lir_cmp:
689 if (op->info() != NULL) {
690 assert(op->in_opr1()->is_address() || op->in_opr2()->is_address(),
691 "shouldn't be codeemitinfo for non-address operands");
692 add_debug_info_for_null_check_here(op->info()); // exception possible
693 }
694 comp_op(op->condition(), op->in_opr1(), op->in_opr2(), op);
695 break;
696
697 case lir_cmp_l2i:
698 case lir_cmp_fd2i:
699 case lir_ucmp_fd2i:
700 comp_fl2i(op->code(), op->in_opr1(), op->in_opr2(), op->result_opr(), op);
701 break;
702
703 case lir_cmove:
704 cmove(op->condition(), op->in_opr1(), op->in_opr2(), op->result_opr(), op->type());
705 break;
706
707 case lir_shl:
708 case lir_shr:
709 case lir_ushr:
710 if (op->in_opr2()->is_constant()) {
711 shift_op(op->code(), op->in_opr1(), op->in_opr2()->as_constant_ptr()->as_jint(), op->result_opr());
712 } else {
713 shift_op(op->code(), op->in_opr1(), op->in_opr2(), op->result_opr(), op->tmp1_opr());
714 }
715 break;
716
717 case lir_add:
718 case lir_sub:
719 case lir_mul:
720 case lir_mul_strictfp:
721 case lir_div:
722 case lir_div_strictfp:
723 case lir_rem:
724 assert(op->fpu_pop_count() < 2, "");
725 arith_op(
726 op->code(),
727 op->in_opr1(),
728 op->in_opr2(),
729 op->result_opr(),
730 op->info(),
731 op->fpu_pop_count() == 1);
732 break;
733
734 case lir_abs:
735 case lir_sqrt:
736 case lir_sin:
737 case lir_tan:
738 case lir_cos:
739 case lir_log:
740 case lir_log10:
741 case lir_exp:
742 case lir_pow:
743 intrinsic_op(op->code(), op->in_opr1(), op->in_opr2(), op->result_opr(), op);
744 break;
745
746 case lir_logic_and:
747 case lir_logic_or:
748 case lir_logic_xor:
749 logic_op(
750 op->code(),
751 op->in_opr1(),
752 op->in_opr2(),
753 op->result_opr());
754 break;
755
756 case lir_throw:
757 throw_op(op->in_opr1(), op->in_opr2(), op->info());
758 break;
759
760 case lir_xadd:
761 case lir_xchg:
762 atomic_op(op->code(), op->in_opr1(), op->in_opr2(), op->result_opr(), op->tmp1_opr());
763 break;
764
765 default:
766 Unimplemented();
767 break;
768 }
769 }
770
771
772 void LIR_Assembler::build_frame() {
773 _masm->build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes());
774 }
775
776
777 void LIR_Assembler::roundfp_op(LIR_Opr src, LIR_Opr tmp, LIR_Opr dest, bool pop_fpu_stack) {
778 assert((src->is_single_fpu() && dest->is_single_stack()) ||
779 (src->is_double_fpu() && dest->is_double_stack()),
780 "round_fp: rounds register -> stack location");
781
782 reg2stack (src, dest, src->type(), pop_fpu_stack);
783 }
784
785
786 void LIR_Assembler::move_op(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, bool unaligned, bool wide) {
787 if (src->is_register()) {
788 if (dest->is_register()) {
789 assert(patch_code == lir_patch_none && info == NULL, "no patching and info allowed here");
790 reg2reg(src, dest);
791 } else if (dest->is_stack()) {
792 assert(patch_code == lir_patch_none && info == NULL, "no patching and info allowed here");
793 reg2stack(src, dest, type, pop_fpu_stack);
794 } else if (dest->is_address()) {
795 reg2mem(src, dest, type, patch_code, info, pop_fpu_stack, wide, unaligned);
796 } else {
797 ShouldNotReachHere();
798 }
799
800 } else if (src->is_stack()) {
801 assert(patch_code == lir_patch_none && info == NULL, "no patching and info allowed here");
802 if (dest->is_register()) {
803 stack2reg(src, dest, type);
804 } else if (dest->is_stack()) {
805 stack2stack(src, dest, type);
806 } else {
807 ShouldNotReachHere();
808 }
809
810 } else if (src->is_constant()) {
811 if (dest->is_register()) {
812 const2reg(src, dest, patch_code, info); // patching is possible
813 } else if (dest->is_stack()) {
814 assert(patch_code == lir_patch_none && info == NULL, "no patching and info allowed here");
815 const2stack(src, dest);
816 } else if (dest->is_address()) {
817 assert(patch_code == lir_patch_none, "no patching allowed here");
818 const2mem(src, dest, type, info, wide);
819 } else {
820 ShouldNotReachHere();
821 }
822
823 } else if (src->is_address()) {
824 mem2reg(src, dest, type, patch_code, info, wide, unaligned);
825
826 } else {
827 ShouldNotReachHere();
828 }
829 }
830
831
832 void LIR_Assembler::verify_oop_map(CodeEmitInfo* info) {
833 #ifndef PRODUCT
834 if (VerifyOops) {
835 OopMapStream s(info->oop_map());
836 while (!s.is_done()) {
837 OopMapValue v = s.current();
838 if (v.is_oop()) {
839 VMReg r = v.reg();
840 if (!r->is_stack()) {
841 stringStream st;
842 st.print("bad oop %s at %d", r->as_Register()->name(), _masm->offset());
843 #ifdef SPARC
844 _masm->_verify_oop(r->as_Register(), os::strdup(st.as_string(), mtCompiler), __FILE__, __LINE__);
845 #else
846 _masm->verify_oop(r->as_Register());
847 #endif
848 } else {
849 _masm->verify_stack_oop(r->reg2stack() * VMRegImpl::stack_slot_size);
850 }
851 }
852 check_codespace();
853 CHECK_BAILOUT();
854
855 s.next();
856 }
857 }
858 #endif
859 }