2546 is_64bit = true; 2547 } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj) { 2548 cmp_value = op->cmp_value()->as_register(); 2549 new_value = op->new_value()->as_register(); 2550 if (op->code() == lir_cas_obj) { 2551 if (UseCompressedOops) { 2552 Register t1 = op->tmp1()->as_register(); 2553 Register t2 = op->tmp2()->as_register(); 2554 cmp_value = __ encode_heap_oop(t1, cmp_value); 2555 new_value = __ encode_heap_oop(t2, new_value); 2556 } else { 2557 is_64bit = true; 2558 } 2559 } 2560 } else { 2561 Unimplemented(); 2562 } 2563 2564 if (is_64bit) { 2565 __ cmpxchgd(BOOL_RESULT, /*current_value=*/R0, cmp_value, new_value, addr, 2566 MacroAssembler::MemBarFenceAfter, 2567 MacroAssembler::cmpxchgx_hint_atomic_update(), 2568 noreg, NULL, /*check without ldarx first*/true); 2569 } else { 2570 __ cmpxchgw(BOOL_RESULT, /*current_value=*/R0, cmp_value, new_value, addr, 2571 MacroAssembler::MemBarFenceAfter, 2572 MacroAssembler::cmpxchgx_hint_atomic_update(), 2573 noreg, /*check without ldarx first*/true); 2574 } 2575 } 2576 2577 2578 void LIR_Assembler::set_24bit_FPU() { 2579 Unimplemented(); 2580 } 2581 2582 void LIR_Assembler::reset_FPU() { 2583 Unimplemented(); 2584 } 2585 2586 2587 void LIR_Assembler::breakpoint() { 2588 __ illtrap(); 2589 } 2590 2591 2592 void LIR_Assembler::push(LIR_Opr opr) { 2593 Unimplemented(); | 2546 is_64bit = true; 2547 } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj) { 2548 cmp_value = op->cmp_value()->as_register(); 2549 new_value = op->new_value()->as_register(); 2550 if (op->code() == lir_cas_obj) { 2551 if (UseCompressedOops) { 2552 Register t1 = op->tmp1()->as_register(); 2553 Register t2 = op->tmp2()->as_register(); 2554 cmp_value = __ encode_heap_oop(t1, cmp_value); 2555 new_value = __ encode_heap_oop(t2, new_value); 2556 } else { 2557 is_64bit = true; 2558 } 2559 } 2560 } else { 2561 Unimplemented(); 2562 } 2563 2564 if (is_64bit) { 2565 __ cmpxchgd(BOOL_RESULT, /*current_value=*/R0, cmp_value, new_value, addr, 2566 MacroAssembler::MemBarNone, 2567 MacroAssembler::cmpxchgx_hint_atomic_update(), 2568 noreg, NULL, /*check without ldarx first*/true); 2569 } else { 2570 __ cmpxchgw(BOOL_RESULT, /*current_value=*/R0, cmp_value, new_value, addr, 2571 MacroAssembler::MemBarNone, 2572 MacroAssembler::cmpxchgx_hint_atomic_update(), 2573 noreg, /*check without ldarx first*/true); 2574 } 2575 2576 if (support_IRIW_for_not_multiple_copy_atomic_cpu) { 2577 __ isync(); 2578 } else { 2579 __ sync(); 2580 } 2581 } 2582 2583 2584 void LIR_Assembler::set_24bit_FPU() { 2585 Unimplemented(); 2586 } 2587 2588 void LIR_Assembler::reset_FPU() { 2589 Unimplemented(); 2590 } 2591 2592 2593 void LIR_Assembler::breakpoint() { 2594 __ illtrap(); 2595 } 2596 2597 2598 void LIR_Assembler::push(LIR_Opr opr) { 2599 Unimplemented(); |