src/cpu/ppc/vm/assembler_ppc.hpp

rev 7958 : 8152172: PPC64: Support AES intrinsics
Reviewed-by: kvn, mdoerr, simonis
Contributed-by: horii@jp.ibm.com

@@ -587,10 +587,11 @@
     VAND_OPCODE    = (4u  << OPCODE_SHIFT | 1028u     ),
     VANDC_OPCODE   = (4u  << OPCODE_SHIFT | 1092u     ),
     VNOR_OPCODE    = (4u  << OPCODE_SHIFT | 1284u     ),
     VOR_OPCODE     = (4u  << OPCODE_SHIFT | 1156u     ),
     VXOR_OPCODE    = (4u  << OPCODE_SHIFT | 1220u     ),
+    VRLD_OPCODE    = (4u  << OPCODE_SHIFT |  196u     ),
     VRLB_OPCODE    = (4u  << OPCODE_SHIFT |    4u     ),
     VRLW_OPCODE    = (4u  << OPCODE_SHIFT |  132u     ),
     VRLH_OPCODE    = (4u  << OPCODE_SHIFT |   68u     ),
     VSLB_OPCODE    = (4u  << OPCODE_SHIFT |  260u     ),
     VSKW_OPCODE    = (4u  << OPCODE_SHIFT |  388u     ),

@@ -1916,10 +1917,11 @@
   inline void vand(     VectorRegister d, VectorRegister a, VectorRegister b);
   inline void vandc(    VectorRegister d, VectorRegister a, VectorRegister b);
   inline void vnor(     VectorRegister d, VectorRegister a, VectorRegister b);
   inline void vor(      VectorRegister d, VectorRegister a, VectorRegister b);
   inline void vxor(     VectorRegister d, VectorRegister a, VectorRegister b);
+  inline void vrld(     VectorRegister d, VectorRegister a, VectorRegister b);
   inline void vrlb(     VectorRegister d, VectorRegister a, VectorRegister b);
   inline void vrlw(     VectorRegister d, VectorRegister a, VectorRegister b);
   inline void vrlh(     VectorRegister d, VectorRegister a, VectorRegister b);
   inline void vslb(     VectorRegister d, VectorRegister a, VectorRegister b);
   inline void vskw(     VectorRegister d, VectorRegister a, VectorRegister b);