1 /*
2 * Copyright (c) 1997, 2009, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 inline void MacroAssembler::pd_patch_instruction(address branch, address target) {
26 jint& stub_inst = *(jint*) branch;
27 stub_inst = patched_branch(target - branch, stub_inst, 0);
28 }
29
30 #ifndef PRODUCT
31 inline void MacroAssembler::pd_print_patched_instruction(address branch) {
32 jint stub_inst = *(jint*) branch;
33 print_instruction(stub_inst);
34 ::tty->print("%s", " (unresolved)");
35 }
36 #endif // PRODUCT
37
38 inline bool Address::is_simm13(int offset) { return Assembler::is_simm13(disp() + offset); }
39
40
41 inline int AddressLiteral::low10() const {
42 return Assembler::low10(value());
43 }
44
800 // of the mmask subfield of const7a that does anything that isn't done
801 // implicitly is StoreLoad.
802 const Membar_mask_bits effective_mask =
803 Membar_mask_bits(const7a & ~(LoadLoad | LoadStore | StoreStore));
804 if ( effective_mask != 0 ) {
805 Assembler::membar( effective_mask );
806 }
807 } else {
808 // stbar is the closest there is on v8. Equivalent to membar(StoreStore). We
809 // do not issue the stbar because to my knowledge all v8 machines implement TSO,
810 // which guarantees that all stores behave as if an stbar were issued just after
811 // each one of them. On these machines, stbar ought to be a nop. There doesn't
812 // appear to be an equivalent of membar(StoreLoad) on v8: TSO doesn't require it,
813 // it can't be specified by stbar, nor have I come up with a way to simulate it.
814 //
815 // Addendum. Dave says that ldstub guarantees a write buffer flush to coherent
816 // space. Put one here to be on the safe side.
817 Assembler::ldstub(SP, 0, G0);
818 }
819 }
|
1 /*
2 * Copyright (c) 1997, 2010, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #ifndef CPU_SPARC_VM_ASSEMBLER_SPARC_INLINE_HPP
26 #define CPU_SPARC_VM_ASSEMBLER_SPARC_INLINE_HPP
27
28 #include "asm/assembler.inline.hpp"
29 #include "asm/codeBuffer.hpp"
30 #include "code/codeCache.hpp"
31 #include "runtime/handles.inline.hpp"
32
33 inline void MacroAssembler::pd_patch_instruction(address branch, address target) {
34 jint& stub_inst = *(jint*) branch;
35 stub_inst = patched_branch(target - branch, stub_inst, 0);
36 }
37
38 #ifndef PRODUCT
39 inline void MacroAssembler::pd_print_patched_instruction(address branch) {
40 jint stub_inst = *(jint*) branch;
41 print_instruction(stub_inst);
42 ::tty->print("%s", " (unresolved)");
43 }
44 #endif // PRODUCT
45
46 inline bool Address::is_simm13(int offset) { return Assembler::is_simm13(disp() + offset); }
47
48
49 inline int AddressLiteral::low10() const {
50 return Assembler::low10(value());
51 }
52
808 // of the mmask subfield of const7a that does anything that isn't done
809 // implicitly is StoreLoad.
810 const Membar_mask_bits effective_mask =
811 Membar_mask_bits(const7a & ~(LoadLoad | LoadStore | StoreStore));
812 if ( effective_mask != 0 ) {
813 Assembler::membar( effective_mask );
814 }
815 } else {
816 // stbar is the closest there is on v8. Equivalent to membar(StoreStore). We
817 // do not issue the stbar because to my knowledge all v8 machines implement TSO,
818 // which guarantees that all stores behave as if an stbar were issued just after
819 // each one of them. On these machines, stbar ought to be a nop. There doesn't
820 // appear to be an equivalent of membar(StoreLoad) on v8: TSO doesn't require it,
821 // it can't be specified by stbar, nor have I come up with a way to simulate it.
822 //
823 // Addendum. Dave says that ldstub guarantees a write buffer flush to coherent
824 // space. Put one here to be on the safe side.
825 Assembler::ldstub(SP, 0, G0);
826 }
827 }
828
829 #endif // CPU_SPARC_VM_ASSEMBLER_SPARC_INLINE_HPP
|