1 /*
2 * Copyright (c) 2000, 2010, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 # include "incls/_precompiled.incl"
26 # include "incls/_c1_LIRAssembler_sparc.cpp.incl"
27
28 #define __ _masm->
29
30
31 //------------------------------------------------------------
32
33
34 bool LIR_Assembler::is_small_constant(LIR_Opr opr) {
35 if (opr->is_constant()) {
36 LIR_Const* constant = opr->as_constant_ptr();
37 switch (constant->type()) {
38 case T_INT: {
39 jint value = constant->as_jint();
40 return Assembler::is_simm13(value);
41 }
42
43 default:
44 return false;
45 }
46 }
47 return false;
48 }
49
50
51 bool LIR_Assembler::is_single_instruction(LIR_Op* op) {
52 switch (op->code()) {
53 case lir_null_check:
54 return true;
55
56
57 case lir_add:
58 case lir_ushr:
59 case lir_shr:
60 case lir_shl:
61 // integer shifts and adds are always one instruction
62 return op->result_opr()->is_single_cpu();
63
64
65 case lir_move: {
66 LIR_Op1* op1 = op->as_Op1();
67 LIR_Opr src = op1->in_opr();
68 LIR_Opr dst = op1->result_opr();
69
70 if (src == dst) {
71 NEEDS_CLEANUP;
72 // this works around a problem where moves with the same src and dst
73 // end up in the delay slot and then the assembler swallows the mov
74 // since it has no effect and then it complains because the delay slot
75 // is empty. returning false stops the optimizer from putting this in
76 // the delay slot
77 return false;
78 }
79
80 // don't put moves involving oops into the delay slot since the VerifyOops code
81 // will make it much larger than a single instruction.
82 if (VerifyOops) {
83 return false;
84 }
85
86 if (src->is_double_cpu() || dst->is_double_cpu() || op1->patch_code() != lir_patch_none ||
87 ((src->is_double_fpu() || dst->is_double_fpu()) && op1->move_kind() != lir_move_normal)) {
88 return false;
89 }
90
91 if (dst->is_register()) {
92 if (src->is_address() && Assembler::is_simm13(src->as_address_ptr()->disp())) {
93 return !PatchALot;
94 } else if (src->is_single_stack()) {
95 return true;
96 }
97 }
98
99 if (src->is_register()) {
100 if (dst->is_address() && Assembler::is_simm13(dst->as_address_ptr()->disp())) {
101 return !PatchALot;
102 } else if (dst->is_single_stack()) {
103 return true;
104 }
105 }
106
107 if (dst->is_register() &&
108 ((src->is_register() && src->is_single_word() && src->is_same_type(dst)) ||
109 (src->is_constant() && LIR_Assembler::is_small_constant(op->as_Op1()->in_opr())))) {
110 return true;
111 }
112
113 return false;
114 }
115
116 default:
117 return false;
118 }
119 ShouldNotReachHere();
120 }
121
122
123 LIR_Opr LIR_Assembler::receiverOpr() {
124 return FrameMap::O0_oop_opr;
125 }
126
127
128 LIR_Opr LIR_Assembler::incomingReceiverOpr() {
129 return FrameMap::I0_oop_opr;
130 }
131
132
133 LIR_Opr LIR_Assembler::osrBufferPointer() {
134 return FrameMap::I0_opr;
135 }
136
137
138 int LIR_Assembler::initial_frame_size_in_bytes() {
139 return in_bytes(frame_map()->framesize_in_bytes());
140 }
141
142
143 // inline cache check: the inline cached class is in G5_inline_cache_reg(G5);
144 // we fetch the class of the receiver (O0) and compare it with the cached class.
145 // If they do not match we jump to slow case.
146 int LIR_Assembler::check_icache() {
147 int offset = __ offset();
148 __ inline_cache_check(O0, G5_inline_cache_reg);
149 return offset;
150 }
151
152
153 void LIR_Assembler::osr_entry() {
154 // On-stack-replacement entry sequence (interpreter frame layout described in interpreter_sparc.cpp):
155 //
156 // 1. Create a new compiled activation.
157 // 2. Initialize local variables in the compiled activation. The expression stack must be empty
158 // at the osr_bci; it is not initialized.
159 // 3. Jump to the continuation address in compiled code to resume execution.
160
161 // OSR entry point
162 offsets()->set_value(CodeOffsets::OSR_Entry, code_offset());
163 BlockBegin* osr_entry = compilation()->hir()->osr_entry();
164 ValueStack* entry_state = osr_entry->end()->state();
165 int number_of_locks = entry_state->locks_size();
166
167 // Create a frame for the compiled activation.
168 __ build_frame(initial_frame_size_in_bytes());
169
170 // OSR buffer is
171 //
172 // locals[nlocals-1..0]
173 // monitors[number_of_locks-1..0]
174 //
175 // locals is a direct copy of the interpreter frame so in the osr buffer
176 // so first slot in the local array is the last local from the interpreter
177 // and last slot is local[0] (receiver) from the interpreter
178 //
179 // Similarly with locks. The first lock slot in the osr buffer is the nth lock
180 // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock
181 // in the interpreter frame (the method lock if a sync method)
182
183 // Initialize monitors in the compiled activation.
184 // I0: pointer to osr buffer
185 //
186 // All other registers are dead at this point and the locals will be
187 // copied into place by code emitted in the IR.
188
189 Register OSR_buf = osrBufferPointer()->as_register();
190 { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");
191 int monitor_offset = BytesPerWord * method()->max_locals() +
192 (2 * BytesPerWord) * (number_of_locks - 1);
193 // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in
194 // the OSR buffer using 2 word entries: first the lock and then
195 // the oop.
196 for (int i = 0; i < number_of_locks; i++) {
197 int slot_offset = monitor_offset - ((i * 2) * BytesPerWord);
198 #ifdef ASSERT
199 // verify the interpreter's monitor has a non-null object
200 {
201 Label L;
202 __ ld_ptr(OSR_buf, slot_offset + 1*BytesPerWord, O7);
203 __ cmp(G0, O7);
204 __ br(Assembler::notEqual, false, Assembler::pt, L);
205 __ delayed()->nop();
206 __ stop("locked object is NULL");
207 __ bind(L);
208 }
209 #endif // ASSERT
210 // Copy the lock field into the compiled activation.
211 __ ld_ptr(OSR_buf, slot_offset + 0, O7);
212 __ st_ptr(O7, frame_map()->address_for_monitor_lock(i));
213 __ ld_ptr(OSR_buf, slot_offset + 1*BytesPerWord, O7);
214 __ st_ptr(O7, frame_map()->address_for_monitor_object(i));
215 }
216 }
217 }
218
219
220 // Optimized Library calls
221 // This is the fast version of java.lang.String.compare; it has not
222 // OSR-entry and therefore, we generate a slow version for OSR's
223 void LIR_Assembler::emit_string_compare(LIR_Opr left, LIR_Opr right, LIR_Opr dst, CodeEmitInfo* info) {
224 Register str0 = left->as_register();
225 Register str1 = right->as_register();
226
227 Label Ldone;
228
229 Register result = dst->as_register();
230 {
231 // Get a pointer to the first character of string0 in tmp0 and get string0.count in str0
232 // Get a pointer to the first character of string1 in tmp1 and get string1.count in str1
233 // Also, get string0.count-string1.count in o7 and get the condition code set
234 // Note: some instructions have been hoisted for better instruction scheduling
235
236 Register tmp0 = L0;
237 Register tmp1 = L1;
238 Register tmp2 = L2;
239
240 int value_offset = java_lang_String:: value_offset_in_bytes(); // char array
241 int offset_offset = java_lang_String::offset_offset_in_bytes(); // first character position
242 int count_offset = java_lang_String:: count_offset_in_bytes();
243
244 __ ld_ptr(str0, value_offset, tmp0);
245 __ ld(str0, offset_offset, tmp2);
246 __ add(tmp0, arrayOopDesc::base_offset_in_bytes(T_CHAR), tmp0);
247 __ ld(str0, count_offset, str0);
248 __ sll(tmp2, exact_log2(sizeof(jchar)), tmp2);
249
250 // str1 may be null
251 add_debug_info_for_null_check_here(info);
252
253 __ ld_ptr(str1, value_offset, tmp1);
254 __ add(tmp0, tmp2, tmp0);
255
256 __ ld(str1, offset_offset, tmp2);
257 __ add(tmp1, arrayOopDesc::base_offset_in_bytes(T_CHAR), tmp1);
258 __ ld(str1, count_offset, str1);
259 __ sll(tmp2, exact_log2(sizeof(jchar)), tmp2);
260 __ subcc(str0, str1, O7);
261 __ add(tmp1, tmp2, tmp1);
262 }
263
264 {
265 // Compute the minimum of the string lengths, scale it and store it in limit
266 Register count0 = I0;
267 Register count1 = I1;
268 Register limit = L3;
269
270 Label Lskip;
271 __ sll(count0, exact_log2(sizeof(jchar)), limit); // string0 is shorter
272 __ br(Assembler::greater, true, Assembler::pt, Lskip);
273 __ delayed()->sll(count1, exact_log2(sizeof(jchar)), limit); // string1 is shorter
274 __ bind(Lskip);
275
276 // If either string is empty (or both of them) the result is the difference in lengths
277 __ cmp(limit, 0);
278 __ br(Assembler::equal, true, Assembler::pn, Ldone);
279 __ delayed()->mov(O7, result); // result is difference in lengths
280 }
281
282 {
283 // Neither string is empty
284 Label Lloop;
285
286 Register base0 = L0;
287 Register base1 = L1;
288 Register chr0 = I0;
289 Register chr1 = I1;
290 Register limit = L3;
291
292 // Shift base0 and base1 to the end of the arrays, negate limit
293 __ add(base0, limit, base0);
294 __ add(base1, limit, base1);
295 __ neg(limit); // limit = -min{string0.count, strin1.count}
296
297 __ lduh(base0, limit, chr0);
298 __ bind(Lloop);
299 __ lduh(base1, limit, chr1);
300 __ subcc(chr0, chr1, chr0);
301 __ br(Assembler::notZero, false, Assembler::pn, Ldone);
302 assert(chr0 == result, "result must be pre-placed");
303 __ delayed()->inccc(limit, sizeof(jchar));
304 __ br(Assembler::notZero, true, Assembler::pt, Lloop);
305 __ delayed()->lduh(base0, limit, chr0);
306 }
307
308 // If strings are equal up to min length, return the length difference.
309 __ mov(O7, result);
310
311 // Otherwise, return the difference between the first mismatched chars.
312 __ bind(Ldone);
313 }
314
315
316 // --------------------------------------------------------------------------------------------
317
318 void LIR_Assembler::monitorexit(LIR_Opr obj_opr, LIR_Opr lock_opr, Register hdr, int monitor_no) {
319 if (!GenerateSynchronizationCode) return;
320
321 Register obj_reg = obj_opr->as_register();
322 Register lock_reg = lock_opr->as_register();
323
324 Address mon_addr = frame_map()->address_for_monitor_lock(monitor_no);
325 Register reg = mon_addr.base();
326 int offset = mon_addr.disp();
327 // compute pointer to BasicLock
328 if (mon_addr.is_simm13()) {
329 __ add(reg, offset, lock_reg);
330 }
331 else {
332 __ set(offset, lock_reg);
333 __ add(reg, lock_reg, lock_reg);
334 }
335 // unlock object
336 MonitorAccessStub* slow_case = new MonitorExitStub(lock_opr, UseFastLocking, monitor_no);
337 // _slow_case_stubs->append(slow_case);
338 // temporary fix: must be created after exceptionhandler, therefore as call stub
339 _slow_case_stubs->append(slow_case);
340 if (UseFastLocking) {
341 // try inlined fast unlocking first, revert to slow locking if it fails
342 // note: lock_reg points to the displaced header since the displaced header offset is 0!
343 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
344 __ unlock_object(hdr, obj_reg, lock_reg, *slow_case->entry());
345 } else {
346 // always do slow unlocking
347 // note: the slow unlocking code could be inlined here, however if we use
348 // slow unlocking, speed doesn't matter anyway and this solution is
349 // simpler and requires less duplicated code - additionally, the
350 // slow unlocking code is the same in either case which simplifies
351 // debugging
352 __ br(Assembler::always, false, Assembler::pt, *slow_case->entry());
353 __ delayed()->nop();
354 }
355 // done
356 __ bind(*slow_case->continuation());
357 }
358
359
360 int LIR_Assembler::emit_exception_handler() {
361 // if the last instruction is a call (typically to do a throw which
362 // is coming at the end after block reordering) the return address
363 // must still point into the code area in order to avoid assertion
364 // failures when searching for the corresponding bci => add a nop
365 // (was bug 5/14/1999 - gri)
366 __ nop();
367
368 // generate code for exception handler
369 ciMethod* method = compilation()->method();
370
371 address handler_base = __ start_a_stub(exception_handler_size);
372
373 if (handler_base == NULL) {
374 // not enough space left for the handler
375 bailout("exception handler overflow");
376 return -1;
377 }
378
379 int offset = code_offset();
380
381 __ call(Runtime1::entry_for(Runtime1::handle_exception_id), relocInfo::runtime_call_type);
382 __ delayed()->nop();
383 debug_only(__ stop("should have gone to the caller");)
384 assert(code_offset() - offset <= exception_handler_size, "overflow");
385 __ end_a_stub();
386
387 return offset;
388 }
389
390
391 // Emit the code to remove the frame from the stack in the exception
392 // unwind path.
393 int LIR_Assembler::emit_unwind_handler() {
394 #ifndef PRODUCT
395 if (CommentedAssembly) {
396 _masm->block_comment("Unwind handler");
397 }
398 #endif
399
400 int offset = code_offset();
401
402 // Fetch the exception from TLS and clear out exception related thread state
403 __ ld_ptr(G2_thread, in_bytes(JavaThread::exception_oop_offset()), O0);
404 __ st_ptr(G0, G2_thread, in_bytes(JavaThread::exception_oop_offset()));
405 __ st_ptr(G0, G2_thread, in_bytes(JavaThread::exception_pc_offset()));
406
407 __ bind(_unwind_handler_entry);
408 __ verify_not_null_oop(O0);
409 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
410 __ mov(O0, I0); // Preserve the exception
411 }
412
413 // Preform needed unlocking
414 MonitorExitStub* stub = NULL;
415 if (method()->is_synchronized()) {
416 monitor_address(0, FrameMap::I1_opr);
417 stub = new MonitorExitStub(FrameMap::I1_opr, true, 0);
418 __ unlock_object(I3, I2, I1, *stub->entry());
419 __ bind(*stub->continuation());
420 }
421
422 if (compilation()->env()->dtrace_method_probes()) {
423 __ mov(G2_thread, O0);
424 jobject2reg(method()->constant_encoding(), O1);
425 __ call(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit), relocInfo::runtime_call_type);
426 __ delayed()->nop();
427 }
428
429 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
430 __ mov(I0, O0); // Restore the exception
431 }
432
433 // dispatch to the unwind logic
434 __ call(Runtime1::entry_for(Runtime1::unwind_exception_id), relocInfo::runtime_call_type);
435 __ delayed()->nop();
436
437 // Emit the slow path assembly
438 if (stub != NULL) {
439 stub->emit_code(this);
440 }
441
442 return offset;
443 }
444
445
446 int LIR_Assembler::emit_deopt_handler() {
447 // if the last instruction is a call (typically to do a throw which
448 // is coming at the end after block reordering) the return address
449 // must still point into the code area in order to avoid assertion
450 // failures when searching for the corresponding bci => add a nop
451 // (was bug 5/14/1999 - gri)
452 __ nop();
453
454 // generate code for deopt handler
455 ciMethod* method = compilation()->method();
456 address handler_base = __ start_a_stub(deopt_handler_size);
457 if (handler_base == NULL) {
458 // not enough space left for the handler
459 bailout("deopt handler overflow");
460 return -1;
461 }
462
463 int offset = code_offset();
464 AddressLiteral deopt_blob(SharedRuntime::deopt_blob()->unpack());
465 __ JUMP(deopt_blob, G3_scratch, 0); // sethi;jmp
466 __ delayed()->nop();
467 assert(code_offset() - offset <= deopt_handler_size, "overflow");
468 debug_only(__ stop("should have gone to the caller");)
469 __ end_a_stub();
470
471 return offset;
472 }
473
474
475 void LIR_Assembler::jobject2reg(jobject o, Register reg) {
476 if (o == NULL) {
477 __ set(NULL_WORD, reg);
478 } else {
479 int oop_index = __ oop_recorder()->find_index(o);
480 RelocationHolder rspec = oop_Relocation::spec(oop_index);
481 __ set(NULL_WORD, reg, rspec); // Will be set when the nmethod is created
482 }
483 }
484
485
486 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo *info) {
487 // Allocate a new index in oop table to hold the oop once it's been patched
488 int oop_index = __ oop_recorder()->allocate_index((jobject)NULL);
489 PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id, oop_index);
490
491 AddressLiteral addrlit(NULL, oop_Relocation::spec(oop_index));
492 assert(addrlit.rspec().type() == relocInfo::oop_type, "must be an oop reloc");
493 // It may not seem necessary to use a sethi/add pair to load a NULL into dest, but the
494 // NULL will be dynamically patched later and the patched value may be large. We must
495 // therefore generate the sethi/add as a placeholders
496 __ patchable_set(addrlit, reg);
497
498 patching_epilog(patch, lir_patch_normal, reg, info);
499 }
500
501
502 void LIR_Assembler::emit_op3(LIR_Op3* op) {
503 Register Rdividend = op->in_opr1()->as_register();
504 Register Rdivisor = noreg;
505 Register Rscratch = op->in_opr3()->as_register();
506 Register Rresult = op->result_opr()->as_register();
507 int divisor = -1;
508
509 if (op->in_opr2()->is_register()) {
510 Rdivisor = op->in_opr2()->as_register();
511 } else {
512 divisor = op->in_opr2()->as_constant_ptr()->as_jint();
513 assert(Assembler::is_simm13(divisor), "can only handle simm13");
514 }
515
516 assert(Rdividend != Rscratch, "");
517 assert(Rdivisor != Rscratch, "");
518 assert(op->code() == lir_idiv || op->code() == lir_irem, "Must be irem or idiv");
519
520 if (Rdivisor == noreg && is_power_of_2(divisor)) {
521 // convert division by a power of two into some shifts and logical operations
522 if (op->code() == lir_idiv) {
523 if (divisor == 2) {
524 __ srl(Rdividend, 31, Rscratch);
525 } else {
526 __ sra(Rdividend, 31, Rscratch);
527 __ and3(Rscratch, divisor - 1, Rscratch);
528 }
529 __ add(Rdividend, Rscratch, Rscratch);
530 __ sra(Rscratch, log2_intptr(divisor), Rresult);
531 return;
532 } else {
533 if (divisor == 2) {
534 __ srl(Rdividend, 31, Rscratch);
535 } else {
536 __ sra(Rdividend, 31, Rscratch);
537 __ and3(Rscratch, divisor - 1,Rscratch);
538 }
539 __ add(Rdividend, Rscratch, Rscratch);
540 __ andn(Rscratch, divisor - 1,Rscratch);
541 __ sub(Rdividend, Rscratch, Rresult);
542 return;
543 }
544 }
545
546 __ sra(Rdividend, 31, Rscratch);
547 __ wry(Rscratch);
548 if (!VM_Version::v9_instructions_work()) {
549 // v9 doesn't require these nops
550 __ nop();
551 __ nop();
552 __ nop();
553 __ nop();
554 }
555
556 add_debug_info_for_div0_here(op->info());
557
558 if (Rdivisor != noreg) {
559 __ sdivcc(Rdividend, Rdivisor, (op->code() == lir_idiv ? Rresult : Rscratch));
560 } else {
561 assert(Assembler::is_simm13(divisor), "can only handle simm13");
562 __ sdivcc(Rdividend, divisor, (op->code() == lir_idiv ? Rresult : Rscratch));
563 }
564
565 Label skip;
566 __ br(Assembler::overflowSet, true, Assembler::pn, skip);
567 __ delayed()->Assembler::sethi(0x80000000, (op->code() == lir_idiv ? Rresult : Rscratch));
568 __ bind(skip);
569
570 if (op->code() == lir_irem) {
571 if (Rdivisor != noreg) {
572 __ smul(Rscratch, Rdivisor, Rscratch);
573 } else {
574 __ smul(Rscratch, divisor, Rscratch);
575 }
576 __ sub(Rdividend, Rscratch, Rresult);
577 }
578 }
579
580
581 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {
582 #ifdef ASSERT
583 assert(op->block() == NULL || op->block()->label() == op->label(), "wrong label");
584 if (op->block() != NULL) _branch_target_blocks.append(op->block());
585 if (op->ublock() != NULL) _branch_target_blocks.append(op->ublock());
586 #endif
587 assert(op->info() == NULL, "shouldn't have CodeEmitInfo");
588
589 if (op->cond() == lir_cond_always) {
590 __ br(Assembler::always, false, Assembler::pt, *(op->label()));
591 } else if (op->code() == lir_cond_float_branch) {
592 assert(op->ublock() != NULL, "must have unordered successor");
593 bool is_unordered = (op->ublock() == op->block());
594 Assembler::Condition acond;
595 switch (op->cond()) {
596 case lir_cond_equal: acond = Assembler::f_equal; break;
597 case lir_cond_notEqual: acond = Assembler::f_notEqual; break;
598 case lir_cond_less: acond = (is_unordered ? Assembler::f_unorderedOrLess : Assembler::f_less); break;
599 case lir_cond_greater: acond = (is_unordered ? Assembler::f_unorderedOrGreater : Assembler::f_greater); break;
600 case lir_cond_lessEqual: acond = (is_unordered ? Assembler::f_unorderedOrLessOrEqual : Assembler::f_lessOrEqual); break;
601 case lir_cond_greaterEqual: acond = (is_unordered ? Assembler::f_unorderedOrGreaterOrEqual: Assembler::f_greaterOrEqual); break;
602 default : ShouldNotReachHere();
603 };
604
605 if (!VM_Version::v9_instructions_work()) {
606 __ nop();
607 }
608 __ fb( acond, false, Assembler::pn, *(op->label()));
609 } else {
610 assert (op->code() == lir_branch, "just checking");
611
612 Assembler::Condition acond;
613 switch (op->cond()) {
614 case lir_cond_equal: acond = Assembler::equal; break;
615 case lir_cond_notEqual: acond = Assembler::notEqual; break;
616 case lir_cond_less: acond = Assembler::less; break;
617 case lir_cond_lessEqual: acond = Assembler::lessEqual; break;
618 case lir_cond_greaterEqual: acond = Assembler::greaterEqual; break;
619 case lir_cond_greater: acond = Assembler::greater; break;
620 case lir_cond_aboveEqual: acond = Assembler::greaterEqualUnsigned; break;
621 case lir_cond_belowEqual: acond = Assembler::lessEqualUnsigned; break;
622 default: ShouldNotReachHere();
623 };
624
625 // sparc has different condition codes for testing 32-bit
626 // vs. 64-bit values. We could always test xcc is we could
627 // guarantee that 32-bit loads always sign extended but that isn't
628 // true and since sign extension isn't free, it would impose a
629 // slight cost.
630 #ifdef _LP64
631 if (op->type() == T_INT) {
632 __ br(acond, false, Assembler::pn, *(op->label()));
633 } else
634 #endif
635 __ brx(acond, false, Assembler::pn, *(op->label()));
636 }
637 // The peephole pass fills the delay slot
638 }
639
640
641 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
642 Bytecodes::Code code = op->bytecode();
643 LIR_Opr dst = op->result_opr();
644
645 switch(code) {
646 case Bytecodes::_i2l: {
647 Register rlo = dst->as_register_lo();
648 Register rhi = dst->as_register_hi();
649 Register rval = op->in_opr()->as_register();
650 #ifdef _LP64
651 __ sra(rval, 0, rlo);
652 #else
653 __ mov(rval, rlo);
654 __ sra(rval, BitsPerInt-1, rhi);
655 #endif
656 break;
657 }
658 case Bytecodes::_i2d:
659 case Bytecodes::_i2f: {
660 bool is_double = (code == Bytecodes::_i2d);
661 FloatRegister rdst = is_double ? dst->as_double_reg() : dst->as_float_reg();
662 FloatRegisterImpl::Width w = is_double ? FloatRegisterImpl::D : FloatRegisterImpl::S;
663 FloatRegister rsrc = op->in_opr()->as_float_reg();
664 if (rsrc != rdst) {
665 __ fmov(FloatRegisterImpl::S, rsrc, rdst);
666 }
667 __ fitof(w, rdst, rdst);
668 break;
669 }
670 case Bytecodes::_f2i:{
671 FloatRegister rsrc = op->in_opr()->as_float_reg();
672 Address addr = frame_map()->address_for_slot(dst->single_stack_ix());
673 Label L;
674 // result must be 0 if value is NaN; test by comparing value to itself
675 __ fcmp(FloatRegisterImpl::S, Assembler::fcc0, rsrc, rsrc);
676 if (!VM_Version::v9_instructions_work()) {
677 __ nop();
678 }
679 __ fb(Assembler::f_unordered, true, Assembler::pn, L);
680 __ delayed()->st(G0, addr); // annuled if contents of rsrc is not NaN
681 __ ftoi(FloatRegisterImpl::S, rsrc, rsrc);
682 // move integer result from float register to int register
683 __ stf(FloatRegisterImpl::S, rsrc, addr.base(), addr.disp());
684 __ bind (L);
685 break;
686 }
687 case Bytecodes::_l2i: {
688 Register rlo = op->in_opr()->as_register_lo();
689 Register rhi = op->in_opr()->as_register_hi();
690 Register rdst = dst->as_register();
691 #ifdef _LP64
692 __ sra(rlo, 0, rdst);
693 #else
694 __ mov(rlo, rdst);
695 #endif
696 break;
697 }
698 case Bytecodes::_d2f:
699 case Bytecodes::_f2d: {
700 bool is_double = (code == Bytecodes::_f2d);
701 assert((!is_double && dst->is_single_fpu()) || (is_double && dst->is_double_fpu()), "check");
702 LIR_Opr val = op->in_opr();
703 FloatRegister rval = (code == Bytecodes::_d2f) ? val->as_double_reg() : val->as_float_reg();
704 FloatRegister rdst = is_double ? dst->as_double_reg() : dst->as_float_reg();
705 FloatRegisterImpl::Width vw = is_double ? FloatRegisterImpl::S : FloatRegisterImpl::D;
706 FloatRegisterImpl::Width dw = is_double ? FloatRegisterImpl::D : FloatRegisterImpl::S;
707 __ ftof(vw, dw, rval, rdst);
708 break;
709 }
710 case Bytecodes::_i2s:
711 case Bytecodes::_i2b: {
712 Register rval = op->in_opr()->as_register();
713 Register rdst = dst->as_register();
714 int shift = (code == Bytecodes::_i2b) ? (BitsPerInt - T_BYTE_aelem_bytes * BitsPerByte) : (BitsPerInt - BitsPerShort);
715 __ sll (rval, shift, rdst);
716 __ sra (rdst, shift, rdst);
717 break;
718 }
719 case Bytecodes::_i2c: {
720 Register rval = op->in_opr()->as_register();
721 Register rdst = dst->as_register();
722 int shift = BitsPerInt - T_CHAR_aelem_bytes * BitsPerByte;
723 __ sll (rval, shift, rdst);
724 __ srl (rdst, shift, rdst);
725 break;
726 }
727
728 default: ShouldNotReachHere();
729 }
730 }
731
732
733 void LIR_Assembler::align_call(LIR_Code) {
734 // do nothing since all instructions are word aligned on sparc
735 }
736
737
738 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) {
739 __ call(op->addr(), rtype);
740 // The peephole pass fills the delay slot, add_call_info is done in
741 // LIR_Assembler::emit_delay.
742 }
743
744
745 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) {
746 RelocationHolder rspec = virtual_call_Relocation::spec(pc());
747 __ set_oop((jobject)Universe::non_oop_word(), G5_inline_cache_reg);
748 __ relocate(rspec);
749 __ call(op->addr(), relocInfo::none);
750 // The peephole pass fills the delay slot, add_call_info is done in
751 // LIR_Assembler::emit_delay.
752 }
753
754
755 void LIR_Assembler::vtable_call(LIR_OpJavaCall* op) {
756 add_debug_info_for_null_check_here(op->info());
757 __ ld_ptr(O0, oopDesc::klass_offset_in_bytes(), G3_scratch);
758 if (__ is_simm13(op->vtable_offset())) {
759 __ ld_ptr(G3_scratch, op->vtable_offset(), G5_method);
760 } else {
761 // This will generate 2 instructions
762 __ set(op->vtable_offset(), G5_method);
763 // ld_ptr, set_hi, set
764 __ ld_ptr(G3_scratch, G5_method, G5_method);
765 }
766 __ ld_ptr(G5_method, methodOopDesc::from_compiled_offset(), G3_scratch);
767 __ callr(G3_scratch, G0);
768 // the peephole pass fills the delay slot
769 }
770
771
772 // load with 32-bit displacement
773 int LIR_Assembler::load(Register s, int disp, Register d, BasicType ld_type, CodeEmitInfo *info) {
774 int load_offset = code_offset();
775 if (Assembler::is_simm13(disp)) {
776 if (info != NULL) add_debug_info_for_null_check_here(info);
777 switch(ld_type) {
778 case T_BOOLEAN: // fall through
779 case T_BYTE : __ ldsb(s, disp, d); break;
780 case T_CHAR : __ lduh(s, disp, d); break;
781 case T_SHORT : __ ldsh(s, disp, d); break;
782 case T_INT : __ ld(s, disp, d); break;
783 case T_ADDRESS:// fall through
784 case T_ARRAY : // fall through
785 case T_OBJECT: __ ld_ptr(s, disp, d); break;
786 default : ShouldNotReachHere();
787 }
788 } else {
789 __ set(disp, O7);
790 if (info != NULL) add_debug_info_for_null_check_here(info);
791 load_offset = code_offset();
792 switch(ld_type) {
793 case T_BOOLEAN: // fall through
794 case T_BYTE : __ ldsb(s, O7, d); break;
795 case T_CHAR : __ lduh(s, O7, d); break;
796 case T_SHORT : __ ldsh(s, O7, d); break;
797 case T_INT : __ ld(s, O7, d); break;
798 case T_ADDRESS:// fall through
799 case T_ARRAY : // fall through
800 case T_OBJECT: __ ld_ptr(s, O7, d); break;
801 default : ShouldNotReachHere();
802 }
803 }
804 if (ld_type == T_ARRAY || ld_type == T_OBJECT) __ verify_oop(d);
805 return load_offset;
806 }
807
808
809 // store with 32-bit displacement
810 void LIR_Assembler::store(Register value, Register base, int offset, BasicType type, CodeEmitInfo *info) {
811 if (Assembler::is_simm13(offset)) {
812 if (info != NULL) add_debug_info_for_null_check_here(info);
813 switch (type) {
814 case T_BOOLEAN: // fall through
815 case T_BYTE : __ stb(value, base, offset); break;
816 case T_CHAR : __ sth(value, base, offset); break;
817 case T_SHORT : __ sth(value, base, offset); break;
818 case T_INT : __ stw(value, base, offset); break;
819 case T_ADDRESS:// fall through
820 case T_ARRAY : // fall through
821 case T_OBJECT: __ st_ptr(value, base, offset); break;
822 default : ShouldNotReachHere();
823 }
824 } else {
825 __ set(offset, O7);
826 if (info != NULL) add_debug_info_for_null_check_here(info);
827 switch (type) {
828 case T_BOOLEAN: // fall through
829 case T_BYTE : __ stb(value, base, O7); break;
830 case T_CHAR : __ sth(value, base, O7); break;
831 case T_SHORT : __ sth(value, base, O7); break;
832 case T_INT : __ stw(value, base, O7); break;
833 case T_ADDRESS:// fall through
834 case T_ARRAY : //fall through
835 case T_OBJECT: __ st_ptr(value, base, O7); break;
836 default : ShouldNotReachHere();
837 }
838 }
839 // Note: Do the store before verification as the code might be patched!
840 if (type == T_ARRAY || type == T_OBJECT) __ verify_oop(value);
841 }
842
843
844 // load float with 32-bit displacement
845 void LIR_Assembler::load(Register s, int disp, FloatRegister d, BasicType ld_type, CodeEmitInfo *info) {
846 FloatRegisterImpl::Width w;
847 switch(ld_type) {
848 case T_FLOAT : w = FloatRegisterImpl::S; break;
849 case T_DOUBLE: w = FloatRegisterImpl::D; break;
850 default : ShouldNotReachHere();
851 }
852
853 if (Assembler::is_simm13(disp)) {
854 if (info != NULL) add_debug_info_for_null_check_here(info);
855 if (disp % BytesPerLong != 0 && w == FloatRegisterImpl::D) {
856 __ ldf(FloatRegisterImpl::S, s, disp + BytesPerWord, d->successor());
857 __ ldf(FloatRegisterImpl::S, s, disp , d);
858 } else {
859 __ ldf(w, s, disp, d);
860 }
861 } else {
862 __ set(disp, O7);
863 if (info != NULL) add_debug_info_for_null_check_here(info);
864 __ ldf(w, s, O7, d);
865 }
866 }
867
868
869 // store float with 32-bit displacement
870 void LIR_Assembler::store(FloatRegister value, Register base, int offset, BasicType type, CodeEmitInfo *info) {
871 FloatRegisterImpl::Width w;
872 switch(type) {
873 case T_FLOAT : w = FloatRegisterImpl::S; break;
874 case T_DOUBLE: w = FloatRegisterImpl::D; break;
875 default : ShouldNotReachHere();
876 }
877
878 if (Assembler::is_simm13(offset)) {
879 if (info != NULL) add_debug_info_for_null_check_here(info);
880 if (w == FloatRegisterImpl::D && offset % BytesPerLong != 0) {
881 __ stf(FloatRegisterImpl::S, value->successor(), base, offset + BytesPerWord);
882 __ stf(FloatRegisterImpl::S, value , base, offset);
883 } else {
884 __ stf(w, value, base, offset);
885 }
886 } else {
887 __ set(offset, O7);
888 if (info != NULL) add_debug_info_for_null_check_here(info);
889 __ stf(w, value, O7, base);
890 }
891 }
892
893
894 int LIR_Assembler::store(LIR_Opr from_reg, Register base, int offset, BasicType type, bool unaligned) {
895 int store_offset;
896 if (!Assembler::is_simm13(offset + (type == T_LONG) ? wordSize : 0)) {
897 assert(!unaligned, "can't handle this");
898 // for offsets larger than a simm13 we setup the offset in O7
899 __ set(offset, O7);
900 store_offset = store(from_reg, base, O7, type);
901 } else {
902 if (type == T_ARRAY || type == T_OBJECT) __ verify_oop(from_reg->as_register());
903 store_offset = code_offset();
904 switch (type) {
905 case T_BOOLEAN: // fall through
906 case T_BYTE : __ stb(from_reg->as_register(), base, offset); break;
907 case T_CHAR : __ sth(from_reg->as_register(), base, offset); break;
908 case T_SHORT : __ sth(from_reg->as_register(), base, offset); break;
909 case T_INT : __ stw(from_reg->as_register(), base, offset); break;
910 case T_LONG :
911 #ifdef _LP64
912 if (unaligned || PatchALot) {
913 __ srax(from_reg->as_register_lo(), 32, O7);
914 __ stw(from_reg->as_register_lo(), base, offset + lo_word_offset_in_bytes);
915 __ stw(O7, base, offset + hi_word_offset_in_bytes);
916 } else {
917 __ stx(from_reg->as_register_lo(), base, offset);
918 }
919 #else
920 assert(Assembler::is_simm13(offset + 4), "must be");
921 __ stw(from_reg->as_register_lo(), base, offset + lo_word_offset_in_bytes);
922 __ stw(from_reg->as_register_hi(), base, offset + hi_word_offset_in_bytes);
923 #endif
924 break;
925 case T_ADDRESS:// fall through
926 case T_ARRAY : // fall through
927 case T_OBJECT: __ st_ptr(from_reg->as_register(), base, offset); break;
928 case T_FLOAT : __ stf(FloatRegisterImpl::S, from_reg->as_float_reg(), base, offset); break;
929 case T_DOUBLE:
930 {
931 FloatRegister reg = from_reg->as_double_reg();
932 // split unaligned stores
933 if (unaligned || PatchALot) {
934 assert(Assembler::is_simm13(offset + 4), "must be");
935 __ stf(FloatRegisterImpl::S, reg->successor(), base, offset + 4);
936 __ stf(FloatRegisterImpl::S, reg, base, offset);
937 } else {
938 __ stf(FloatRegisterImpl::D, reg, base, offset);
939 }
940 break;
941 }
942 default : ShouldNotReachHere();
943 }
944 }
945 return store_offset;
946 }
947
948
949 int LIR_Assembler::store(LIR_Opr from_reg, Register base, Register disp, BasicType type) {
950 if (type == T_ARRAY || type == T_OBJECT) __ verify_oop(from_reg->as_register());
951 int store_offset = code_offset();
952 switch (type) {
953 case T_BOOLEAN: // fall through
954 case T_BYTE : __ stb(from_reg->as_register(), base, disp); break;
955 case T_CHAR : __ sth(from_reg->as_register(), base, disp); break;
956 case T_SHORT : __ sth(from_reg->as_register(), base, disp); break;
957 case T_INT : __ stw(from_reg->as_register(), base, disp); break;
958 case T_LONG :
959 #ifdef _LP64
960 __ stx(from_reg->as_register_lo(), base, disp);
961 #else
962 assert(from_reg->as_register_hi()->successor() == from_reg->as_register_lo(), "must match");
963 __ std(from_reg->as_register_hi(), base, disp);
964 #endif
965 break;
966 case T_ADDRESS:// fall through
967 case T_ARRAY : // fall through
968 case T_OBJECT: __ st_ptr(from_reg->as_register(), base, disp); break;
969 case T_FLOAT : __ stf(FloatRegisterImpl::S, from_reg->as_float_reg(), base, disp); break;
970 case T_DOUBLE: __ stf(FloatRegisterImpl::D, from_reg->as_double_reg(), base, disp); break;
971 default : ShouldNotReachHere();
972 }
973 return store_offset;
974 }
975
976
977 int LIR_Assembler::load(Register base, int offset, LIR_Opr to_reg, BasicType type, bool unaligned) {
978 int load_offset;
979 if (!Assembler::is_simm13(offset + (type == T_LONG) ? wordSize : 0)) {
980 assert(base != O7, "destroying register");
981 assert(!unaligned, "can't handle this");
982 // for offsets larger than a simm13 we setup the offset in O7
983 __ set(offset, O7);
984 load_offset = load(base, O7, to_reg, type);
985 } else {
986 load_offset = code_offset();
987 switch(type) {
988 case T_BOOLEAN: // fall through
989 case T_BYTE : __ ldsb(base, offset, to_reg->as_register()); break;
990 case T_CHAR : __ lduh(base, offset, to_reg->as_register()); break;
991 case T_SHORT : __ ldsh(base, offset, to_reg->as_register()); break;
992 case T_INT : __ ld(base, offset, to_reg->as_register()); break;
993 case T_LONG :
994 if (!unaligned) {
995 #ifdef _LP64
996 __ ldx(base, offset, to_reg->as_register_lo());
997 #else
998 assert(to_reg->as_register_hi()->successor() == to_reg->as_register_lo(),
999 "must be sequential");
1000 __ ldd(base, offset, to_reg->as_register_hi());
1001 #endif
1002 } else {
1003 #ifdef _LP64
1004 assert(base != to_reg->as_register_lo(), "can't handle this");
1005 assert(O7 != to_reg->as_register_lo(), "can't handle this");
1006 __ ld(base, offset + hi_word_offset_in_bytes, to_reg->as_register_lo());
1007 __ lduw(base, offset + lo_word_offset_in_bytes, O7); // in case O7 is base or offset, use it last
1008 __ sllx(to_reg->as_register_lo(), 32, to_reg->as_register_lo());
1009 __ or3(to_reg->as_register_lo(), O7, to_reg->as_register_lo());
1010 #else
1011 if (base == to_reg->as_register_lo()) {
1012 __ ld(base, offset + hi_word_offset_in_bytes, to_reg->as_register_hi());
1013 __ ld(base, offset + lo_word_offset_in_bytes, to_reg->as_register_lo());
1014 } else {
1015 __ ld(base, offset + lo_word_offset_in_bytes, to_reg->as_register_lo());
1016 __ ld(base, offset + hi_word_offset_in_bytes, to_reg->as_register_hi());
1017 }
1018 #endif
1019 }
1020 break;
1021 case T_ADDRESS:// fall through
1022 case T_ARRAY : // fall through
1023 case T_OBJECT: __ ld_ptr(base, offset, to_reg->as_register()); break;
1024 case T_FLOAT: __ ldf(FloatRegisterImpl::S, base, offset, to_reg->as_float_reg()); break;
1025 case T_DOUBLE:
1026 {
1027 FloatRegister reg = to_reg->as_double_reg();
1028 // split unaligned loads
1029 if (unaligned || PatchALot) {
1030 __ ldf(FloatRegisterImpl::S, base, offset + 4, reg->successor());
1031 __ ldf(FloatRegisterImpl::S, base, offset, reg);
1032 } else {
1033 __ ldf(FloatRegisterImpl::D, base, offset, to_reg->as_double_reg());
1034 }
1035 break;
1036 }
1037 default : ShouldNotReachHere();
1038 }
1039 if (type == T_ARRAY || type == T_OBJECT) __ verify_oop(to_reg->as_register());
1040 }
1041 return load_offset;
1042 }
1043
1044
1045 int LIR_Assembler::load(Register base, Register disp, LIR_Opr to_reg, BasicType type) {
1046 int load_offset = code_offset();
1047 switch(type) {
1048 case T_BOOLEAN: // fall through
1049 case T_BYTE : __ ldsb(base, disp, to_reg->as_register()); break;
1050 case T_CHAR : __ lduh(base, disp, to_reg->as_register()); break;
1051 case T_SHORT : __ ldsh(base, disp, to_reg->as_register()); break;
1052 case T_INT : __ ld(base, disp, to_reg->as_register()); break;
1053 case T_ADDRESS:// fall through
1054 case T_ARRAY : // fall through
1055 case T_OBJECT: __ ld_ptr(base, disp, to_reg->as_register()); break;
1056 case T_FLOAT: __ ldf(FloatRegisterImpl::S, base, disp, to_reg->as_float_reg()); break;
1057 case T_DOUBLE: __ ldf(FloatRegisterImpl::D, base, disp, to_reg->as_double_reg()); break;
1058 case T_LONG :
1059 #ifdef _LP64
1060 __ ldx(base, disp, to_reg->as_register_lo());
1061 #else
1062 assert(to_reg->as_register_hi()->successor() == to_reg->as_register_lo(),
1063 "must be sequential");
1064 __ ldd(base, disp, to_reg->as_register_hi());
1065 #endif
1066 break;
1067 default : ShouldNotReachHere();
1068 }
1069 if (type == T_ARRAY || type == T_OBJECT) __ verify_oop(to_reg->as_register());
1070 return load_offset;
1071 }
1072
1073
1074 // load/store with an Address
1075 void LIR_Assembler::load(const Address& a, Register d, BasicType ld_type, CodeEmitInfo *info, int offset) {
1076 load(a.base(), a.disp() + offset, d, ld_type, info);
1077 }
1078
1079
1080 void LIR_Assembler::store(Register value, const Address& dest, BasicType type, CodeEmitInfo *info, int offset) {
1081 store(value, dest.base(), dest.disp() + offset, type, info);
1082 }
1083
1084
1085 // loadf/storef with an Address
1086 void LIR_Assembler::load(const Address& a, FloatRegister d, BasicType ld_type, CodeEmitInfo *info, int offset) {
1087 load(a.base(), a.disp() + offset, d, ld_type, info);
1088 }
1089
1090
1091 void LIR_Assembler::store(FloatRegister value, const Address& dest, BasicType type, CodeEmitInfo *info, int offset) {
1092 store(value, dest.base(), dest.disp() + offset, type, info);
1093 }
1094
1095
1096 // load/store with an Address
1097 void LIR_Assembler::load(LIR_Address* a, Register d, BasicType ld_type, CodeEmitInfo *info) {
1098 load(as_Address(a), d, ld_type, info);
1099 }
1100
1101
1102 void LIR_Assembler::store(Register value, LIR_Address* dest, BasicType type, CodeEmitInfo *info) {
1103 store(value, as_Address(dest), type, info);
1104 }
1105
1106
1107 // loadf/storef with an Address
1108 void LIR_Assembler::load(LIR_Address* a, FloatRegister d, BasicType ld_type, CodeEmitInfo *info) {
1109 load(as_Address(a), d, ld_type, info);
1110 }
1111
1112
1113 void LIR_Assembler::store(FloatRegister value, LIR_Address* dest, BasicType type, CodeEmitInfo *info) {
1114 store(value, as_Address(dest), type, info);
1115 }
1116
1117
1118 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
1119 LIR_Const* c = src->as_constant_ptr();
1120 switch (c->type()) {
1121 case T_INT:
1122 case T_FLOAT:
1123 case T_ADDRESS: {
1124 Register src_reg = O7;
1125 int value = c->as_jint_bits();
1126 if (value == 0) {
1127 src_reg = G0;
1128 } else {
1129 __ set(value, O7);
1130 }
1131 Address addr = frame_map()->address_for_slot(dest->single_stack_ix());
1132 __ stw(src_reg, addr.base(), addr.disp());
1133 break;
1134 }
1135 case T_OBJECT: {
1136 Register src_reg = O7;
1137 jobject2reg(c->as_jobject(), src_reg);
1138 Address addr = frame_map()->address_for_slot(dest->single_stack_ix());
1139 __ st_ptr(src_reg, addr.base(), addr.disp());
1140 break;
1141 }
1142 case T_LONG:
1143 case T_DOUBLE: {
1144 Address addr = frame_map()->address_for_double_slot(dest->double_stack_ix());
1145
1146 Register tmp = O7;
1147 int value_lo = c->as_jint_lo_bits();
1148 if (value_lo == 0) {
1149 tmp = G0;
1150 } else {
1151 __ set(value_lo, O7);
1152 }
1153 __ stw(tmp, addr.base(), addr.disp() + lo_word_offset_in_bytes);
1154 int value_hi = c->as_jint_hi_bits();
1155 if (value_hi == 0) {
1156 tmp = G0;
1157 } else {
1158 __ set(value_hi, O7);
1159 }
1160 __ stw(tmp, addr.base(), addr.disp() + hi_word_offset_in_bytes);
1161 break;
1162 }
1163 default:
1164 Unimplemented();
1165 }
1166 }
1167
1168
1169 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info ) {
1170 LIR_Const* c = src->as_constant_ptr();
1171 LIR_Address* addr = dest->as_address_ptr();
1172 Register base = addr->base()->as_pointer_register();
1173
1174 if (info != NULL) {
1175 add_debug_info_for_null_check_here(info);
1176 }
1177 switch (c->type()) {
1178 case T_INT:
1179 case T_FLOAT:
1180 case T_ADDRESS: {
1181 LIR_Opr tmp = FrameMap::O7_opr;
1182 int value = c->as_jint_bits();
1183 if (value == 0) {
1184 tmp = FrameMap::G0_opr;
1185 } else if (Assembler::is_simm13(value)) {
1186 __ set(value, O7);
1187 }
1188 if (addr->index()->is_valid()) {
1189 assert(addr->disp() == 0, "must be zero");
1190 store(tmp, base, addr->index()->as_pointer_register(), type);
1191 } else {
1192 assert(Assembler::is_simm13(addr->disp()), "can't handle larger addresses");
1193 store(tmp, base, addr->disp(), type);
1194 }
1195 break;
1196 }
1197 case T_LONG:
1198 case T_DOUBLE: {
1199 assert(!addr->index()->is_valid(), "can't handle reg reg address here");
1200 assert(Assembler::is_simm13(addr->disp()) &&
1201 Assembler::is_simm13(addr->disp() + 4), "can't handle larger addresses");
1202
1203 Register tmp = O7;
1204 int value_lo = c->as_jint_lo_bits();
1205 if (value_lo == 0) {
1206 tmp = G0;
1207 } else {
1208 __ set(value_lo, O7);
1209 }
1210 store(tmp, base, addr->disp() + lo_word_offset_in_bytes, T_INT);
1211 int value_hi = c->as_jint_hi_bits();
1212 if (value_hi == 0) {
1213 tmp = G0;
1214 } else {
1215 __ set(value_hi, O7);
1216 }
1217 store(tmp, base, addr->disp() + hi_word_offset_in_bytes, T_INT);
1218 break;
1219 }
1220 case T_OBJECT: {
1221 jobject obj = c->as_jobject();
1222 LIR_Opr tmp;
1223 if (obj == NULL) {
1224 tmp = FrameMap::G0_opr;
1225 } else {
1226 tmp = FrameMap::O7_opr;
1227 jobject2reg(c->as_jobject(), O7);
1228 }
1229 // handle either reg+reg or reg+disp address
1230 if (addr->index()->is_valid()) {
1231 assert(addr->disp() == 0, "must be zero");
1232 store(tmp, base, addr->index()->as_pointer_register(), type);
1233 } else {
1234 assert(Assembler::is_simm13(addr->disp()), "can't handle larger addresses");
1235 store(tmp, base, addr->disp(), type);
1236 }
1237
1238 break;
1239 }
1240 default:
1241 Unimplemented();
1242 }
1243 }
1244
1245
1246 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
1247 LIR_Const* c = src->as_constant_ptr();
1248 LIR_Opr to_reg = dest;
1249
1250 switch (c->type()) {
1251 case T_INT:
1252 case T_ADDRESS:
1253 {
1254 jint con = c->as_jint();
1255 if (to_reg->is_single_cpu()) {
1256 assert(patch_code == lir_patch_none, "no patching handled here");
1257 __ set(con, to_reg->as_register());
1258 } else {
1259 ShouldNotReachHere();
1260 assert(to_reg->is_single_fpu(), "wrong register kind");
1261
1262 __ set(con, O7);
1263 Address temp_slot(SP, (frame::register_save_words * wordSize) + STACK_BIAS);
1264 __ st(O7, temp_slot);
1265 __ ldf(FloatRegisterImpl::S, temp_slot, to_reg->as_float_reg());
1266 }
1267 }
1268 break;
1269
1270 case T_LONG:
1271 {
1272 jlong con = c->as_jlong();
1273
1274 if (to_reg->is_double_cpu()) {
1275 #ifdef _LP64
1276 __ set(con, to_reg->as_register_lo());
1277 #else
1278 __ set(low(con), to_reg->as_register_lo());
1279 __ set(high(con), to_reg->as_register_hi());
1280 #endif
1281 #ifdef _LP64
1282 } else if (to_reg->is_single_cpu()) {
1283 __ set(con, to_reg->as_register());
1284 #endif
1285 } else {
1286 ShouldNotReachHere();
1287 assert(to_reg->is_double_fpu(), "wrong register kind");
1288 Address temp_slot_lo(SP, ((frame::register_save_words ) * wordSize) + STACK_BIAS);
1289 Address temp_slot_hi(SP, ((frame::register_save_words) * wordSize) + (longSize/2) + STACK_BIAS);
1290 __ set(low(con), O7);
1291 __ st(O7, temp_slot_lo);
1292 __ set(high(con), O7);
1293 __ st(O7, temp_slot_hi);
1294 __ ldf(FloatRegisterImpl::D, temp_slot_lo, to_reg->as_double_reg());
1295 }
1296 }
1297 break;
1298
1299 case T_OBJECT:
1300 {
1301 if (patch_code == lir_patch_none) {
1302 jobject2reg(c->as_jobject(), to_reg->as_register());
1303 } else {
1304 jobject2reg_with_patching(to_reg->as_register(), info);
1305 }
1306 }
1307 break;
1308
1309 case T_FLOAT:
1310 {
1311 address const_addr = __ float_constant(c->as_jfloat());
1312 if (const_addr == NULL) {
1313 bailout("const section overflow");
1314 break;
1315 }
1316 RelocationHolder rspec = internal_word_Relocation::spec(const_addr);
1317 AddressLiteral const_addrlit(const_addr, rspec);
1318 if (to_reg->is_single_fpu()) {
1319 __ patchable_sethi(const_addrlit, O7);
1320 __ relocate(rspec);
1321 __ ldf(FloatRegisterImpl::S, O7, const_addrlit.low10(), to_reg->as_float_reg());
1322
1323 } else {
1324 assert(to_reg->is_single_cpu(), "Must be a cpu register.");
1325
1326 __ set(const_addrlit, O7);
1327 load(O7, 0, to_reg->as_register(), T_INT);
1328 }
1329 }
1330 break;
1331
1332 case T_DOUBLE:
1333 {
1334 address const_addr = __ double_constant(c->as_jdouble());
1335 if (const_addr == NULL) {
1336 bailout("const section overflow");
1337 break;
1338 }
1339 RelocationHolder rspec = internal_word_Relocation::spec(const_addr);
1340
1341 if (to_reg->is_double_fpu()) {
1342 AddressLiteral const_addrlit(const_addr, rspec);
1343 __ patchable_sethi(const_addrlit, O7);
1344 __ relocate(rspec);
1345 __ ldf (FloatRegisterImpl::D, O7, const_addrlit.low10(), to_reg->as_double_reg());
1346 } else {
1347 assert(to_reg->is_double_cpu(), "Must be a long register.");
1348 #ifdef _LP64
1349 __ set(jlong_cast(c->as_jdouble()), to_reg->as_register_lo());
1350 #else
1351 __ set(low(jlong_cast(c->as_jdouble())), to_reg->as_register_lo());
1352 __ set(high(jlong_cast(c->as_jdouble())), to_reg->as_register_hi());
1353 #endif
1354 }
1355
1356 }
1357 break;
1358
1359 default:
1360 ShouldNotReachHere();
1361 }
1362 }
1363
1364 Address LIR_Assembler::as_Address(LIR_Address* addr) {
1365 Register reg = addr->base()->as_register();
1366 return Address(reg, addr->disp());
1367 }
1368
1369
1370 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
1371 switch (type) {
1372 case T_INT:
1373 case T_FLOAT: {
1374 Register tmp = O7;
1375 Address from = frame_map()->address_for_slot(src->single_stack_ix());
1376 Address to = frame_map()->address_for_slot(dest->single_stack_ix());
1377 __ lduw(from.base(), from.disp(), tmp);
1378 __ stw(tmp, to.base(), to.disp());
1379 break;
1380 }
1381 case T_OBJECT: {
1382 Register tmp = O7;
1383 Address from = frame_map()->address_for_slot(src->single_stack_ix());
1384 Address to = frame_map()->address_for_slot(dest->single_stack_ix());
1385 __ ld_ptr(from.base(), from.disp(), tmp);
1386 __ st_ptr(tmp, to.base(), to.disp());
1387 break;
1388 }
1389 case T_LONG:
1390 case T_DOUBLE: {
1391 Register tmp = O7;
1392 Address from = frame_map()->address_for_double_slot(src->double_stack_ix());
1393 Address to = frame_map()->address_for_double_slot(dest->double_stack_ix());
1394 __ lduw(from.base(), from.disp(), tmp);
1395 __ stw(tmp, to.base(), to.disp());
1396 __ lduw(from.base(), from.disp() + 4, tmp);
1397 __ stw(tmp, to.base(), to.disp() + 4);
1398 break;
1399 }
1400
1401 default:
1402 ShouldNotReachHere();
1403 }
1404 }
1405
1406
1407 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) {
1408 Address base = as_Address(addr);
1409 return Address(base.base(), base.disp() + hi_word_offset_in_bytes);
1410 }
1411
1412
1413 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) {
1414 Address base = as_Address(addr);
1415 return Address(base.base(), base.disp() + lo_word_offset_in_bytes);
1416 }
1417
1418
1419 void LIR_Assembler::mem2reg(LIR_Opr src_opr, LIR_Opr dest, BasicType type,
1420 LIR_PatchCode patch_code, CodeEmitInfo* info, bool unaligned) {
1421
1422 LIR_Address* addr = src_opr->as_address_ptr();
1423 LIR_Opr to_reg = dest;
1424
1425 Register src = addr->base()->as_pointer_register();
1426 Register disp_reg = noreg;
1427 int disp_value = addr->disp();
1428 bool needs_patching = (patch_code != lir_patch_none);
1429
1430 if (addr->base()->type() == T_OBJECT) {
1431 __ verify_oop(src);
1432 }
1433
1434 PatchingStub* patch = NULL;
1435 if (needs_patching) {
1436 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1437 assert(!to_reg->is_double_cpu() ||
1438 patch_code == lir_patch_none ||
1439 patch_code == lir_patch_normal, "patching doesn't match register");
1440 }
1441
1442 if (addr->index()->is_illegal()) {
1443 if (!Assembler::is_simm13(disp_value) && (!unaligned || Assembler::is_simm13(disp_value + 4))) {
1444 if (needs_patching) {
1445 __ patchable_set(0, O7);
1446 } else {
1447 __ set(disp_value, O7);
1448 }
1449 disp_reg = O7;
1450 }
1451 } else if (unaligned || PatchALot) {
1452 __ add(src, addr->index()->as_register(), O7);
1453 src = O7;
1454 } else {
1455 disp_reg = addr->index()->as_pointer_register();
1456 assert(disp_value == 0, "can't handle 3 operand addresses");
1457 }
1458
1459 // remember the offset of the load. The patching_epilog must be done
1460 // before the call to add_debug_info, otherwise the PcDescs don't get
1461 // entered in increasing order.
1462 int offset = code_offset();
1463
1464 assert(disp_reg != noreg || Assembler::is_simm13(disp_value), "should have set this up");
1465 if (disp_reg == noreg) {
1466 offset = load(src, disp_value, to_reg, type, unaligned);
1467 } else {
1468 assert(!unaligned, "can't handle this");
1469 offset = load(src, disp_reg, to_reg, type);
1470 }
1471
1472 if (patch != NULL) {
1473 patching_epilog(patch, patch_code, src, info);
1474 }
1475
1476 if (info != NULL) add_debug_info_for_null_check(offset, info);
1477 }
1478
1479
1480 void LIR_Assembler::prefetchr(LIR_Opr src) {
1481 LIR_Address* addr = src->as_address_ptr();
1482 Address from_addr = as_Address(addr);
1483
1484 if (VM_Version::has_v9()) {
1485 __ prefetch(from_addr, Assembler::severalReads);
1486 }
1487 }
1488
1489
1490 void LIR_Assembler::prefetchw(LIR_Opr src) {
1491 LIR_Address* addr = src->as_address_ptr();
1492 Address from_addr = as_Address(addr);
1493
1494 if (VM_Version::has_v9()) {
1495 __ prefetch(from_addr, Assembler::severalWritesAndPossiblyReads);
1496 }
1497 }
1498
1499
1500 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
1501 Address addr;
1502 if (src->is_single_word()) {
1503 addr = frame_map()->address_for_slot(src->single_stack_ix());
1504 } else if (src->is_double_word()) {
1505 addr = frame_map()->address_for_double_slot(src->double_stack_ix());
1506 }
1507
1508 bool unaligned = (addr.disp() - STACK_BIAS) % 8 != 0;
1509 load(addr.base(), addr.disp(), dest, dest->type(), unaligned);
1510 }
1511
1512
1513 void LIR_Assembler::reg2stack(LIR_Opr from_reg, LIR_Opr dest, BasicType type, bool pop_fpu_stack) {
1514 Address addr;
1515 if (dest->is_single_word()) {
1516 addr = frame_map()->address_for_slot(dest->single_stack_ix());
1517 } else if (dest->is_double_word()) {
1518 addr = frame_map()->address_for_slot(dest->double_stack_ix());
1519 }
1520 bool unaligned = (addr.disp() - STACK_BIAS) % 8 != 0;
1521 store(from_reg, addr.base(), addr.disp(), from_reg->type(), unaligned);
1522 }
1523
1524
1525 void LIR_Assembler::reg2reg(LIR_Opr from_reg, LIR_Opr to_reg) {
1526 if (from_reg->is_float_kind() && to_reg->is_float_kind()) {
1527 if (from_reg->is_double_fpu()) {
1528 // double to double moves
1529 assert(to_reg->is_double_fpu(), "should match");
1530 __ fmov(FloatRegisterImpl::D, from_reg->as_double_reg(), to_reg->as_double_reg());
1531 } else {
1532 // float to float moves
1533 assert(to_reg->is_single_fpu(), "should match");
1534 __ fmov(FloatRegisterImpl::S, from_reg->as_float_reg(), to_reg->as_float_reg());
1535 }
1536 } else if (!from_reg->is_float_kind() && !to_reg->is_float_kind()) {
1537 if (from_reg->is_double_cpu()) {
1538 #ifdef _LP64
1539 __ mov(from_reg->as_pointer_register(), to_reg->as_pointer_register());
1540 #else
1541 assert(to_reg->is_double_cpu() &&
1542 from_reg->as_register_hi() != to_reg->as_register_lo() &&
1543 from_reg->as_register_lo() != to_reg->as_register_hi(),
1544 "should both be long and not overlap");
1545 // long to long moves
1546 __ mov(from_reg->as_register_hi(), to_reg->as_register_hi());
1547 __ mov(from_reg->as_register_lo(), to_reg->as_register_lo());
1548 #endif
1549 #ifdef _LP64
1550 } else if (to_reg->is_double_cpu()) {
1551 // int to int moves
1552 __ mov(from_reg->as_register(), to_reg->as_register_lo());
1553 #endif
1554 } else {
1555 // int to int moves
1556 __ mov(from_reg->as_register(), to_reg->as_register());
1557 }
1558 } else {
1559 ShouldNotReachHere();
1560 }
1561 if (to_reg->type() == T_OBJECT || to_reg->type() == T_ARRAY) {
1562 __ verify_oop(to_reg->as_register());
1563 }
1564 }
1565
1566
1567 void LIR_Assembler::reg2mem(LIR_Opr from_reg, LIR_Opr dest, BasicType type,
1568 LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack,
1569 bool unaligned) {
1570 LIR_Address* addr = dest->as_address_ptr();
1571
1572 Register src = addr->base()->as_pointer_register();
1573 Register disp_reg = noreg;
1574 int disp_value = addr->disp();
1575 bool needs_patching = (patch_code != lir_patch_none);
1576
1577 if (addr->base()->is_oop_register()) {
1578 __ verify_oop(src);
1579 }
1580
1581 PatchingStub* patch = NULL;
1582 if (needs_patching) {
1583 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1584 assert(!from_reg->is_double_cpu() ||
1585 patch_code == lir_patch_none ||
1586 patch_code == lir_patch_normal, "patching doesn't match register");
1587 }
1588
1589 if (addr->index()->is_illegal()) {
1590 if (!Assembler::is_simm13(disp_value) && (!unaligned || Assembler::is_simm13(disp_value + 4))) {
1591 if (needs_patching) {
1592 __ patchable_set(0, O7);
1593 } else {
1594 __ set(disp_value, O7);
1595 }
1596 disp_reg = O7;
1597 }
1598 } else if (unaligned || PatchALot) {
1599 __ add(src, addr->index()->as_register(), O7);
1600 src = O7;
1601 } else {
1602 disp_reg = addr->index()->as_pointer_register();
1603 assert(disp_value == 0, "can't handle 3 operand addresses");
1604 }
1605
1606 // remember the offset of the store. The patching_epilog must be done
1607 // before the call to add_debug_info_for_null_check, otherwise the PcDescs don't get
1608 // entered in increasing order.
1609 int offset;
1610
1611 assert(disp_reg != noreg || Assembler::is_simm13(disp_value), "should have set this up");
1612 if (disp_reg == noreg) {
1613 offset = store(from_reg, src, disp_value, type, unaligned);
1614 } else {
1615 assert(!unaligned, "can't handle this");
1616 offset = store(from_reg, src, disp_reg, type);
1617 }
1618
1619 if (patch != NULL) {
1620 patching_epilog(patch, patch_code, src, info);
1621 }
1622
1623 if (info != NULL) add_debug_info_for_null_check(offset, info);
1624 }
1625
1626
1627 void LIR_Assembler::return_op(LIR_Opr result) {
1628 // the poll may need a register so just pick one that isn't the return register
1629 #if defined(TIERED) && !defined(_LP64)
1630 if (result->type_field() == LIR_OprDesc::long_type) {
1631 // Must move the result to G1
1632 // Must leave proper result in O0,O1 and G1 (TIERED only)
1633 __ sllx(I0, 32, G1); // Shift bits into high G1
1634 __ srl (I1, 0, I1); // Zero extend O1 (harmless?)
1635 __ or3 (I1, G1, G1); // OR 64 bits into G1
1636 #ifdef ASSERT
1637 // mangle it so any problems will show up
1638 __ set(0xdeadbeef, I0);
1639 __ set(0xdeadbeef, I1);
1640 #endif
1641 }
1642 #endif // TIERED
1643 __ set((intptr_t)os::get_polling_page(), L0);
1644 __ relocate(relocInfo::poll_return_type);
1645 __ ld_ptr(L0, 0, G0);
1646 __ ret();
1647 __ delayed()->restore();
1648 }
1649
1650
1651 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) {
1652 __ set((intptr_t)os::get_polling_page(), tmp->as_register());
1653 if (info != NULL) {
1654 add_debug_info_for_branch(info);
1655 } else {
1656 __ relocate(relocInfo::poll_type);
1657 }
1658
1659 int offset = __ offset();
1660 __ ld_ptr(tmp->as_register(), 0, G0);
1661
1662 return offset;
1663 }
1664
1665
1666 void LIR_Assembler::emit_static_call_stub() {
1667 address call_pc = __ pc();
1668 address stub = __ start_a_stub(call_stub_size);
1669 if (stub == NULL) {
1670 bailout("static call stub overflow");
1671 return;
1672 }
1673
1674 int start = __ offset();
1675 __ relocate(static_stub_Relocation::spec(call_pc));
1676
1677 __ set_oop(NULL, G5);
1678 // must be set to -1 at code generation time
1679 AddressLiteral addrlit(-1);
1680 __ jump_to(addrlit, G3);
1681 __ delayed()->nop();
1682
1683 assert(__ offset() - start <= call_stub_size, "stub too big");
1684 __ end_a_stub();
1685 }
1686
1687
1688 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) {
1689 if (opr1->is_single_fpu()) {
1690 __ fcmp(FloatRegisterImpl::S, Assembler::fcc0, opr1->as_float_reg(), opr2->as_float_reg());
1691 } else if (opr1->is_double_fpu()) {
1692 __ fcmp(FloatRegisterImpl::D, Assembler::fcc0, opr1->as_double_reg(), opr2->as_double_reg());
1693 } else if (opr1->is_single_cpu()) {
1694 if (opr2->is_constant()) {
1695 switch (opr2->as_constant_ptr()->type()) {
1696 case T_INT:
1697 { jint con = opr2->as_constant_ptr()->as_jint();
1698 if (Assembler::is_simm13(con)) {
1699 __ cmp(opr1->as_register(), con);
1700 } else {
1701 __ set(con, O7);
1702 __ cmp(opr1->as_register(), O7);
1703 }
1704 }
1705 break;
1706
1707 case T_OBJECT:
1708 // there are only equal/notequal comparisions on objects
1709 { jobject con = opr2->as_constant_ptr()->as_jobject();
1710 if (con == NULL) {
1711 __ cmp(opr1->as_register(), 0);
1712 } else {
1713 jobject2reg(con, O7);
1714 __ cmp(opr1->as_register(), O7);
1715 }
1716 }
1717 break;
1718
1719 default:
1720 ShouldNotReachHere();
1721 break;
1722 }
1723 } else {
1724 if (opr2->is_address()) {
1725 LIR_Address * addr = opr2->as_address_ptr();
1726 BasicType type = addr->type();
1727 if ( type == T_OBJECT ) __ ld_ptr(as_Address(addr), O7);
1728 else __ ld(as_Address(addr), O7);
1729 __ cmp(opr1->as_register(), O7);
1730 } else {
1731 __ cmp(opr1->as_register(), opr2->as_register());
1732 }
1733 }
1734 } else if (opr1->is_double_cpu()) {
1735 Register xlo = opr1->as_register_lo();
1736 Register xhi = opr1->as_register_hi();
1737 if (opr2->is_constant() && opr2->as_jlong() == 0) {
1738 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "only handles these cases");
1739 #ifdef _LP64
1740 __ orcc(xhi, G0, G0);
1741 #else
1742 __ orcc(xhi, xlo, G0);
1743 #endif
1744 } else if (opr2->is_register()) {
1745 Register ylo = opr2->as_register_lo();
1746 Register yhi = opr2->as_register_hi();
1747 #ifdef _LP64
1748 __ cmp(xlo, ylo);
1749 #else
1750 __ subcc(xlo, ylo, xlo);
1751 __ subccc(xhi, yhi, xhi);
1752 if (condition == lir_cond_equal || condition == lir_cond_notEqual) {
1753 __ orcc(xhi, xlo, G0);
1754 }
1755 #endif
1756 } else {
1757 ShouldNotReachHere();
1758 }
1759 } else if (opr1->is_address()) {
1760 LIR_Address * addr = opr1->as_address_ptr();
1761 BasicType type = addr->type();
1762 assert (opr2->is_constant(), "Checking");
1763 if ( type == T_OBJECT ) __ ld_ptr(as_Address(addr), O7);
1764 else __ ld(as_Address(addr), O7);
1765 __ cmp(O7, opr2->as_constant_ptr()->as_jint());
1766 } else {
1767 ShouldNotReachHere();
1768 }
1769 }
1770
1771
1772 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op){
1773 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) {
1774 bool is_unordered_less = (code == lir_ucmp_fd2i);
1775 if (left->is_single_fpu()) {
1776 __ float_cmp(true, is_unordered_less ? -1 : 1, left->as_float_reg(), right->as_float_reg(), dst->as_register());
1777 } else if (left->is_double_fpu()) {
1778 __ float_cmp(false, is_unordered_less ? -1 : 1, left->as_double_reg(), right->as_double_reg(), dst->as_register());
1779 } else {
1780 ShouldNotReachHere();
1781 }
1782 } else if (code == lir_cmp_l2i) {
1783 #ifdef _LP64
1784 __ lcmp(left->as_register_lo(), right->as_register_lo(), dst->as_register());
1785 #else
1786 __ lcmp(left->as_register_hi(), left->as_register_lo(),
1787 right->as_register_hi(), right->as_register_lo(),
1788 dst->as_register());
1789 #endif
1790 } else {
1791 ShouldNotReachHere();
1792 }
1793 }
1794
1795
1796 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result) {
1797
1798 Assembler::Condition acond;
1799 switch (condition) {
1800 case lir_cond_equal: acond = Assembler::equal; break;
1801 case lir_cond_notEqual: acond = Assembler::notEqual; break;
1802 case lir_cond_less: acond = Assembler::less; break;
1803 case lir_cond_lessEqual: acond = Assembler::lessEqual; break;
1804 case lir_cond_greaterEqual: acond = Assembler::greaterEqual; break;
1805 case lir_cond_greater: acond = Assembler::greater; break;
1806 case lir_cond_aboveEqual: acond = Assembler::greaterEqualUnsigned; break;
1807 case lir_cond_belowEqual: acond = Assembler::lessEqualUnsigned; break;
1808 default: ShouldNotReachHere();
1809 };
1810
1811 if (opr1->is_constant() && opr1->type() == T_INT) {
1812 Register dest = result->as_register();
1813 // load up first part of constant before branch
1814 // and do the rest in the delay slot.
1815 if (!Assembler::is_simm13(opr1->as_jint())) {
1816 __ sethi(opr1->as_jint(), dest);
1817 }
1818 } else if (opr1->is_constant()) {
1819 const2reg(opr1, result, lir_patch_none, NULL);
1820 } else if (opr1->is_register()) {
1821 reg2reg(opr1, result);
1822 } else if (opr1->is_stack()) {
1823 stack2reg(opr1, result, result->type());
1824 } else {
1825 ShouldNotReachHere();
1826 }
1827 Label skip;
1828 __ br(acond, false, Assembler::pt, skip);
1829 if (opr1->is_constant() && opr1->type() == T_INT) {
1830 Register dest = result->as_register();
1831 if (Assembler::is_simm13(opr1->as_jint())) {
1832 __ delayed()->or3(G0, opr1->as_jint(), dest);
1833 } else {
1834 // the sethi has been done above, so just put in the low 10 bits
1835 __ delayed()->or3(dest, opr1->as_jint() & 0x3ff, dest);
1836 }
1837 } else {
1838 // can't do anything useful in the delay slot
1839 __ delayed()->nop();
1840 }
1841 if (opr2->is_constant()) {
1842 const2reg(opr2, result, lir_patch_none, NULL);
1843 } else if (opr2->is_register()) {
1844 reg2reg(opr2, result);
1845 } else if (opr2->is_stack()) {
1846 stack2reg(opr2, result, result->type());
1847 } else {
1848 ShouldNotReachHere();
1849 }
1850 __ bind(skip);
1851 }
1852
1853
1854 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack) {
1855 assert(info == NULL, "unused on this code path");
1856 assert(left->is_register(), "wrong items state");
1857 assert(dest->is_register(), "wrong items state");
1858
1859 if (right->is_register()) {
1860 if (dest->is_float_kind()) {
1861
1862 FloatRegister lreg, rreg, res;
1863 FloatRegisterImpl::Width w;
1864 if (right->is_single_fpu()) {
1865 w = FloatRegisterImpl::S;
1866 lreg = left->as_float_reg();
1867 rreg = right->as_float_reg();
1868 res = dest->as_float_reg();
1869 } else {
1870 w = FloatRegisterImpl::D;
1871 lreg = left->as_double_reg();
1872 rreg = right->as_double_reg();
1873 res = dest->as_double_reg();
1874 }
1875
1876 switch (code) {
1877 case lir_add: __ fadd(w, lreg, rreg, res); break;
1878 case lir_sub: __ fsub(w, lreg, rreg, res); break;
1879 case lir_mul: // fall through
1880 case lir_mul_strictfp: __ fmul(w, lreg, rreg, res); break;
1881 case lir_div: // fall through
1882 case lir_div_strictfp: __ fdiv(w, lreg, rreg, res); break;
1883 default: ShouldNotReachHere();
1884 }
1885
1886 } else if (dest->is_double_cpu()) {
1887 #ifdef _LP64
1888 Register dst_lo = dest->as_register_lo();
1889 Register op1_lo = left->as_pointer_register();
1890 Register op2_lo = right->as_pointer_register();
1891
1892 switch (code) {
1893 case lir_add:
1894 __ add(op1_lo, op2_lo, dst_lo);
1895 break;
1896
1897 case lir_sub:
1898 __ sub(op1_lo, op2_lo, dst_lo);
1899 break;
1900
1901 default: ShouldNotReachHere();
1902 }
1903 #else
1904 Register op1_lo = left->as_register_lo();
1905 Register op1_hi = left->as_register_hi();
1906 Register op2_lo = right->as_register_lo();
1907 Register op2_hi = right->as_register_hi();
1908 Register dst_lo = dest->as_register_lo();
1909 Register dst_hi = dest->as_register_hi();
1910
1911 switch (code) {
1912 case lir_add:
1913 __ addcc(op1_lo, op2_lo, dst_lo);
1914 __ addc (op1_hi, op2_hi, dst_hi);
1915 break;
1916
1917 case lir_sub:
1918 __ subcc(op1_lo, op2_lo, dst_lo);
1919 __ subc (op1_hi, op2_hi, dst_hi);
1920 break;
1921
1922 default: ShouldNotReachHere();
1923 }
1924 #endif
1925 } else {
1926 assert (right->is_single_cpu(), "Just Checking");
1927
1928 Register lreg = left->as_register();
1929 Register res = dest->as_register();
1930 Register rreg = right->as_register();
1931 switch (code) {
1932 case lir_add: __ add (lreg, rreg, res); break;
1933 case lir_sub: __ sub (lreg, rreg, res); break;
1934 case lir_mul: __ mult (lreg, rreg, res); break;
1935 default: ShouldNotReachHere();
1936 }
1937 }
1938 } else {
1939 assert (right->is_constant(), "must be constant");
1940
1941 if (dest->is_single_cpu()) {
1942 Register lreg = left->as_register();
1943 Register res = dest->as_register();
1944 int simm13 = right->as_constant_ptr()->as_jint();
1945
1946 switch (code) {
1947 case lir_add: __ add (lreg, simm13, res); break;
1948 case lir_sub: __ sub (lreg, simm13, res); break;
1949 case lir_mul: __ mult (lreg, simm13, res); break;
1950 default: ShouldNotReachHere();
1951 }
1952 } else {
1953 Register lreg = left->as_pointer_register();
1954 Register res = dest->as_register_lo();
1955 long con = right->as_constant_ptr()->as_jlong();
1956 assert(Assembler::is_simm13(con), "must be simm13");
1957
1958 switch (code) {
1959 case lir_add: __ add (lreg, (int)con, res); break;
1960 case lir_sub: __ sub (lreg, (int)con, res); break;
1961 case lir_mul: __ mult (lreg, (int)con, res); break;
1962 default: ShouldNotReachHere();
1963 }
1964 }
1965 }
1966 }
1967
1968
1969 void LIR_Assembler::fpop() {
1970 // do nothing
1971 }
1972
1973
1974 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr thread, LIR_Opr dest, LIR_Op* op) {
1975 switch (code) {
1976 case lir_sin:
1977 case lir_tan:
1978 case lir_cos: {
1979 assert(thread->is_valid(), "preserve the thread object for performance reasons");
1980 assert(dest->as_double_reg() == F0, "the result will be in f0/f1");
1981 break;
1982 }
1983 case lir_sqrt: {
1984 assert(!thread->is_valid(), "there is no need for a thread_reg for dsqrt");
1985 FloatRegister src_reg = value->as_double_reg();
1986 FloatRegister dst_reg = dest->as_double_reg();
1987 __ fsqrt(FloatRegisterImpl::D, src_reg, dst_reg);
1988 break;
1989 }
1990 case lir_abs: {
1991 assert(!thread->is_valid(), "there is no need for a thread_reg for fabs");
1992 FloatRegister src_reg = value->as_double_reg();
1993 FloatRegister dst_reg = dest->as_double_reg();
1994 __ fabs(FloatRegisterImpl::D, src_reg, dst_reg);
1995 break;
1996 }
1997 default: {
1998 ShouldNotReachHere();
1999 break;
2000 }
2001 }
2002 }
2003
2004
2005 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest) {
2006 if (right->is_constant()) {
2007 if (dest->is_single_cpu()) {
2008 int simm13 = right->as_constant_ptr()->as_jint();
2009 switch (code) {
2010 case lir_logic_and: __ and3 (left->as_register(), simm13, dest->as_register()); break;
2011 case lir_logic_or: __ or3 (left->as_register(), simm13, dest->as_register()); break;
2012 case lir_logic_xor: __ xor3 (left->as_register(), simm13, dest->as_register()); break;
2013 default: ShouldNotReachHere();
2014 }
2015 } else {
2016 long c = right->as_constant_ptr()->as_jlong();
2017 assert(c == (int)c && Assembler::is_simm13(c), "out of range");
2018 int simm13 = (int)c;
2019 switch (code) {
2020 case lir_logic_and:
2021 #ifndef _LP64
2022 __ and3 (left->as_register_hi(), 0, dest->as_register_hi());
2023 #endif
2024 __ and3 (left->as_register_lo(), simm13, dest->as_register_lo());
2025 break;
2026
2027 case lir_logic_or:
2028 #ifndef _LP64
2029 __ or3 (left->as_register_hi(), 0, dest->as_register_hi());
2030 #endif
2031 __ or3 (left->as_register_lo(), simm13, dest->as_register_lo());
2032 break;
2033
2034 case lir_logic_xor:
2035 #ifndef _LP64
2036 __ xor3 (left->as_register_hi(), 0, dest->as_register_hi());
2037 #endif
2038 __ xor3 (left->as_register_lo(), simm13, dest->as_register_lo());
2039 break;
2040
2041 default: ShouldNotReachHere();
2042 }
2043 }
2044 } else {
2045 assert(right->is_register(), "right should be in register");
2046
2047 if (dest->is_single_cpu()) {
2048 switch (code) {
2049 case lir_logic_and: __ and3 (left->as_register(), right->as_register(), dest->as_register()); break;
2050 case lir_logic_or: __ or3 (left->as_register(), right->as_register(), dest->as_register()); break;
2051 case lir_logic_xor: __ xor3 (left->as_register(), right->as_register(), dest->as_register()); break;
2052 default: ShouldNotReachHere();
2053 }
2054 } else {
2055 #ifdef _LP64
2056 Register l = (left->is_single_cpu() && left->is_oop_register()) ? left->as_register() :
2057 left->as_register_lo();
2058 Register r = (right->is_single_cpu() && right->is_oop_register()) ? right->as_register() :
2059 right->as_register_lo();
2060
2061 switch (code) {
2062 case lir_logic_and: __ and3 (l, r, dest->as_register_lo()); break;
2063 case lir_logic_or: __ or3 (l, r, dest->as_register_lo()); break;
2064 case lir_logic_xor: __ xor3 (l, r, dest->as_register_lo()); break;
2065 default: ShouldNotReachHere();
2066 }
2067 #else
2068 switch (code) {
2069 case lir_logic_and:
2070 __ and3 (left->as_register_hi(), right->as_register_hi(), dest->as_register_hi());
2071 __ and3 (left->as_register_lo(), right->as_register_lo(), dest->as_register_lo());
2072 break;
2073
2074 case lir_logic_or:
2075 __ or3 (left->as_register_hi(), right->as_register_hi(), dest->as_register_hi());
2076 __ or3 (left->as_register_lo(), right->as_register_lo(), dest->as_register_lo());
2077 break;
2078
2079 case lir_logic_xor:
2080 __ xor3 (left->as_register_hi(), right->as_register_hi(), dest->as_register_hi());
2081 __ xor3 (left->as_register_lo(), right->as_register_lo(), dest->as_register_lo());
2082 break;
2083
2084 default: ShouldNotReachHere();
2085 }
2086 #endif
2087 }
2088 }
2089 }
2090
2091
2092 int LIR_Assembler::shift_amount(BasicType t) {
2093 int elem_size = type2aelembytes(t);
2094 switch (elem_size) {
2095 case 1 : return 0;
2096 case 2 : return 1;
2097 case 4 : return 2;
2098 case 8 : return 3;
2099 }
2100 ShouldNotReachHere();
2101 return -1;
2102 }
2103
2104
2105 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) {
2106 assert(exceptionOop->as_register() == Oexception, "should match");
2107 assert(exceptionPC->as_register() == Oissuing_pc, "should match");
2108
2109 info->add_register_oop(exceptionOop);
2110
2111 // reuse the debug info from the safepoint poll for the throw op itself
2112 address pc_for_athrow = __ pc();
2113 int pc_for_athrow_offset = __ offset();
2114 RelocationHolder rspec = internal_word_Relocation::spec(pc_for_athrow);
2115 __ set(pc_for_athrow, Oissuing_pc, rspec);
2116 add_call_info(pc_for_athrow_offset, info); // for exception handler
2117
2118 __ call(Runtime1::entry_for(Runtime1::handle_exception_id), relocInfo::runtime_call_type);
2119 __ delayed()->nop();
2120 }
2121
2122
2123 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) {
2124 assert(exceptionOop->as_register() == Oexception, "should match");
2125
2126 __ br(Assembler::always, false, Assembler::pt, _unwind_handler_entry);
2127 __ delayed()->nop();
2128 }
2129
2130
2131 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
2132 Register src = op->src()->as_register();
2133 Register dst = op->dst()->as_register();
2134 Register src_pos = op->src_pos()->as_register();
2135 Register dst_pos = op->dst_pos()->as_register();
2136 Register length = op->length()->as_register();
2137 Register tmp = op->tmp()->as_register();
2138 Register tmp2 = O7;
2139
2140 int flags = op->flags();
2141 ciArrayKlass* default_type = op->expected_type();
2142 BasicType basic_type = default_type != NULL ? default_type->element_type()->basic_type() : T_ILLEGAL;
2143 if (basic_type == T_ARRAY) basic_type = T_OBJECT;
2144
2145 // set up the arraycopy stub information
2146 ArrayCopyStub* stub = op->stub();
2147
2148 // always do stub if no type information is available. it's ok if
2149 // the known type isn't loaded since the code sanity checks
2150 // in debug mode and the type isn't required when we know the exact type
2151 // also check that the type is an array type.
2152 // We also, for now, always call the stub if the barrier set requires a
2153 // write_ref_pre barrier (which the stub does, but none of the optimized
2154 // cases currently does).
2155 if (op->expected_type() == NULL ||
2156 Universe::heap()->barrier_set()->has_write_ref_pre_barrier()) {
2157 __ mov(src, O0);
2158 __ mov(src_pos, O1);
2159 __ mov(dst, O2);
2160 __ mov(dst_pos, O3);
2161 __ mov(length, O4);
2162 __ call_VM_leaf(tmp, CAST_FROM_FN_PTR(address, Runtime1::arraycopy));
2163
2164 __ br_zero(Assembler::less, false, Assembler::pn, O0, *stub->entry());
2165 __ delayed()->nop();
2166 __ bind(*stub->continuation());
2167 return;
2168 }
2169
2170 assert(default_type != NULL && default_type->is_array_klass(), "must be true at this point");
2171
2172 // make sure src and dst are non-null and load array length
2173 if (flags & LIR_OpArrayCopy::src_null_check) {
2174 __ tst(src);
2175 __ br(Assembler::equal, false, Assembler::pn, *stub->entry());
2176 __ delayed()->nop();
2177 }
2178
2179 if (flags & LIR_OpArrayCopy::dst_null_check) {
2180 __ tst(dst);
2181 __ br(Assembler::equal, false, Assembler::pn, *stub->entry());
2182 __ delayed()->nop();
2183 }
2184
2185 if (flags & LIR_OpArrayCopy::src_pos_positive_check) {
2186 // test src_pos register
2187 __ tst(src_pos);
2188 __ br(Assembler::less, false, Assembler::pn, *stub->entry());
2189 __ delayed()->nop();
2190 }
2191
2192 if (flags & LIR_OpArrayCopy::dst_pos_positive_check) {
2193 // test dst_pos register
2194 __ tst(dst_pos);
2195 __ br(Assembler::less, false, Assembler::pn, *stub->entry());
2196 __ delayed()->nop();
2197 }
2198
2199 if (flags & LIR_OpArrayCopy::length_positive_check) {
2200 // make sure length isn't negative
2201 __ tst(length);
2202 __ br(Assembler::less, false, Assembler::pn, *stub->entry());
2203 __ delayed()->nop();
2204 }
2205
2206 if (flags & LIR_OpArrayCopy::src_range_check) {
2207 __ ld(src, arrayOopDesc::length_offset_in_bytes(), tmp2);
2208 __ add(length, src_pos, tmp);
2209 __ cmp(tmp2, tmp);
2210 __ br(Assembler::carrySet, false, Assembler::pn, *stub->entry());
2211 __ delayed()->nop();
2212 }
2213
2214 if (flags & LIR_OpArrayCopy::dst_range_check) {
2215 __ ld(dst, arrayOopDesc::length_offset_in_bytes(), tmp2);
2216 __ add(length, dst_pos, tmp);
2217 __ cmp(tmp2, tmp);
2218 __ br(Assembler::carrySet, false, Assembler::pn, *stub->entry());
2219 __ delayed()->nop();
2220 }
2221
2222 if (flags & LIR_OpArrayCopy::type_check) {
2223 __ ld_ptr(src, oopDesc::klass_offset_in_bytes(), tmp);
2224 __ ld_ptr(dst, oopDesc::klass_offset_in_bytes(), tmp2);
2225 __ cmp(tmp, tmp2);
2226 __ br(Assembler::notEqual, false, Assembler::pt, *stub->entry());
2227 __ delayed()->nop();
2228 }
2229
2230 #ifdef ASSERT
2231 if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) {
2232 // Sanity check the known type with the incoming class. For the
2233 // primitive case the types must match exactly with src.klass and
2234 // dst.klass each exactly matching the default type. For the
2235 // object array case, if no type check is needed then either the
2236 // dst type is exactly the expected type and the src type is a
2237 // subtype which we can't check or src is the same array as dst
2238 // but not necessarily exactly of type default_type.
2239 Label known_ok, halt;
2240 jobject2reg(op->expected_type()->constant_encoding(), tmp);
2241 __ ld_ptr(dst, oopDesc::klass_offset_in_bytes(), tmp2);
2242 if (basic_type != T_OBJECT) {
2243 __ cmp(tmp, tmp2);
2244 __ br(Assembler::notEqual, false, Assembler::pn, halt);
2245 __ delayed()->ld_ptr(src, oopDesc::klass_offset_in_bytes(), tmp2);
2246 __ cmp(tmp, tmp2);
2247 __ br(Assembler::equal, false, Assembler::pn, known_ok);
2248 __ delayed()->nop();
2249 } else {
2250 __ cmp(tmp, tmp2);
2251 __ br(Assembler::equal, false, Assembler::pn, known_ok);
2252 __ delayed()->cmp(src, dst);
2253 __ br(Assembler::equal, false, Assembler::pn, known_ok);
2254 __ delayed()->nop();
2255 }
2256 __ bind(halt);
2257 __ stop("incorrect type information in arraycopy");
2258 __ bind(known_ok);
2259 }
2260 #endif
2261
2262 int shift = shift_amount(basic_type);
2263
2264 Register src_ptr = O0;
2265 Register dst_ptr = O1;
2266 Register len = O2;
2267
2268 __ add(src, arrayOopDesc::base_offset_in_bytes(basic_type), src_ptr);
2269 LP64_ONLY(__ sra(src_pos, 0, src_pos);) //higher 32bits must be null
2270 if (shift == 0) {
2271 __ add(src_ptr, src_pos, src_ptr);
2272 } else {
2273 __ sll(src_pos, shift, tmp);
2274 __ add(src_ptr, tmp, src_ptr);
2275 }
2276
2277 __ add(dst, arrayOopDesc::base_offset_in_bytes(basic_type), dst_ptr);
2278 LP64_ONLY(__ sra(dst_pos, 0, dst_pos);) //higher 32bits must be null
2279 if (shift == 0) {
2280 __ add(dst_ptr, dst_pos, dst_ptr);
2281 } else {
2282 __ sll(dst_pos, shift, tmp);
2283 __ add(dst_ptr, tmp, dst_ptr);
2284 }
2285
2286 if (basic_type != T_OBJECT) {
2287 if (shift == 0) {
2288 __ mov(length, len);
2289 } else {
2290 __ sll(length, shift, len);
2291 }
2292 __ call_VM_leaf(tmp, CAST_FROM_FN_PTR(address, Runtime1::primitive_arraycopy));
2293 } else {
2294 // oop_arraycopy takes a length in number of elements, so don't scale it.
2295 __ mov(length, len);
2296 __ call_VM_leaf(tmp, CAST_FROM_FN_PTR(address, Runtime1::oop_arraycopy));
2297 }
2298
2299 __ bind(*stub->continuation());
2300 }
2301
2302
2303 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) {
2304 if (dest->is_single_cpu()) {
2305 #ifdef _LP64
2306 if (left->type() == T_OBJECT) {
2307 switch (code) {
2308 case lir_shl: __ sllx (left->as_register(), count->as_register(), dest->as_register()); break;
2309 case lir_shr: __ srax (left->as_register(), count->as_register(), dest->as_register()); break;
2310 case lir_ushr: __ srl (left->as_register(), count->as_register(), dest->as_register()); break;
2311 default: ShouldNotReachHere();
2312 }
2313 } else
2314 #endif
2315 switch (code) {
2316 case lir_shl: __ sll (left->as_register(), count->as_register(), dest->as_register()); break;
2317 case lir_shr: __ sra (left->as_register(), count->as_register(), dest->as_register()); break;
2318 case lir_ushr: __ srl (left->as_register(), count->as_register(), dest->as_register()); break;
2319 default: ShouldNotReachHere();
2320 }
2321 } else {
2322 #ifdef _LP64
2323 switch (code) {
2324 case lir_shl: __ sllx (left->as_register_lo(), count->as_register(), dest->as_register_lo()); break;
2325 case lir_shr: __ srax (left->as_register_lo(), count->as_register(), dest->as_register_lo()); break;
2326 case lir_ushr: __ srlx (left->as_register_lo(), count->as_register(), dest->as_register_lo()); break;
2327 default: ShouldNotReachHere();
2328 }
2329 #else
2330 switch (code) {
2331 case lir_shl: __ lshl (left->as_register_hi(), left->as_register_lo(), count->as_register(), dest->as_register_hi(), dest->as_register_lo(), G3_scratch); break;
2332 case lir_shr: __ lshr (left->as_register_hi(), left->as_register_lo(), count->as_register(), dest->as_register_hi(), dest->as_register_lo(), G3_scratch); break;
2333 case lir_ushr: __ lushr (left->as_register_hi(), left->as_register_lo(), count->as_register(), dest->as_register_hi(), dest->as_register_lo(), G3_scratch); break;
2334 default: ShouldNotReachHere();
2335 }
2336 #endif
2337 }
2338 }
2339
2340
2341 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) {
2342 #ifdef _LP64
2343 if (left->type() == T_OBJECT) {
2344 count = count & 63; // shouldn't shift by more than sizeof(intptr_t)
2345 Register l = left->as_register();
2346 Register d = dest->as_register_lo();
2347 switch (code) {
2348 case lir_shl: __ sllx (l, count, d); break;
2349 case lir_shr: __ srax (l, count, d); break;
2350 case lir_ushr: __ srlx (l, count, d); break;
2351 default: ShouldNotReachHere();
2352 }
2353 return;
2354 }
2355 #endif
2356
2357 if (dest->is_single_cpu()) {
2358 count = count & 0x1F; // Java spec
2359 switch (code) {
2360 case lir_shl: __ sll (left->as_register(), count, dest->as_register()); break;
2361 case lir_shr: __ sra (left->as_register(), count, dest->as_register()); break;
2362 case lir_ushr: __ srl (left->as_register(), count, dest->as_register()); break;
2363 default: ShouldNotReachHere();
2364 }
2365 } else if (dest->is_double_cpu()) {
2366 count = count & 63; // Java spec
2367 switch (code) {
2368 case lir_shl: __ sllx (left->as_pointer_register(), count, dest->as_pointer_register()); break;
2369 case lir_shr: __ srax (left->as_pointer_register(), count, dest->as_pointer_register()); break;
2370 case lir_ushr: __ srlx (left->as_pointer_register(), count, dest->as_pointer_register()); break;
2371 default: ShouldNotReachHere();
2372 }
2373 } else {
2374 ShouldNotReachHere();
2375 }
2376 }
2377
2378
2379 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) {
2380 assert(op->tmp1()->as_register() == G1 &&
2381 op->tmp2()->as_register() == G3 &&
2382 op->tmp3()->as_register() == G4 &&
2383 op->obj()->as_register() == O0 &&
2384 op->klass()->as_register() == G5, "must be");
2385 if (op->init_check()) {
2386 __ ld(op->klass()->as_register(),
2387 instanceKlass::init_state_offset_in_bytes() + sizeof(oopDesc),
2388 op->tmp1()->as_register());
2389 add_debug_info_for_null_check_here(op->stub()->info());
2390 __ cmp(op->tmp1()->as_register(), instanceKlass::fully_initialized);
2391 __ br(Assembler::notEqual, false, Assembler::pn, *op->stub()->entry());
2392 __ delayed()->nop();
2393 }
2394 __ allocate_object(op->obj()->as_register(),
2395 op->tmp1()->as_register(),
2396 op->tmp2()->as_register(),
2397 op->tmp3()->as_register(),
2398 op->header_size(),
2399 op->object_size(),
2400 op->klass()->as_register(),
2401 *op->stub()->entry());
2402 __ bind(*op->stub()->continuation());
2403 __ verify_oop(op->obj()->as_register());
2404 }
2405
2406
2407 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) {
2408 assert(op->tmp1()->as_register() == G1 &&
2409 op->tmp2()->as_register() == G3 &&
2410 op->tmp3()->as_register() == G4 &&
2411 op->tmp4()->as_register() == O1 &&
2412 op->klass()->as_register() == G5, "must be");
2413 if (UseSlowPath ||
2414 (!UseFastNewObjectArray && (op->type() == T_OBJECT || op->type() == T_ARRAY)) ||
2415 (!UseFastNewTypeArray && (op->type() != T_OBJECT && op->type() != T_ARRAY))) {
2416 __ br(Assembler::always, false, Assembler::pt, *op->stub()->entry());
2417 __ delayed()->nop();
2418 } else {
2419 __ allocate_array(op->obj()->as_register(),
2420 op->len()->as_register(),
2421 op->tmp1()->as_register(),
2422 op->tmp2()->as_register(),
2423 op->tmp3()->as_register(),
2424 arrayOopDesc::header_size(op->type()),
2425 type2aelembytes(op->type()),
2426 op->klass()->as_register(),
2427 *op->stub()->entry());
2428 }
2429 __ bind(*op->stub()->continuation());
2430 }
2431
2432
2433 void LIR_Assembler::type_profile_helper(Register mdo, int mdo_offset_bias,
2434 ciMethodData *md, ciProfileData *data,
2435 Register recv, Register tmp1, Label* update_done) {
2436 uint i;
2437 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2438 Label next_test;
2439 // See if the receiver is receiver[n].
2440 Address receiver_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)) -
2441 mdo_offset_bias);
2442 __ ld_ptr(receiver_addr, tmp1);
2443 __ verify_oop(tmp1);
2444 __ cmp(recv, tmp1);
2445 __ brx(Assembler::notEqual, false, Assembler::pt, next_test);
2446 __ delayed()->nop();
2447 Address data_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)) -
2448 mdo_offset_bias);
2449 __ ld_ptr(data_addr, tmp1);
2450 __ add(tmp1, DataLayout::counter_increment, tmp1);
2451 __ st_ptr(tmp1, data_addr);
2452 __ ba(false, *update_done);
2453 __ delayed()->nop();
2454 __ bind(next_test);
2455 }
2456
2457 // Didn't find receiver; find next empty slot and fill it in
2458 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2459 Label next_test;
2460 Address recv_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)) -
2461 mdo_offset_bias);
2462 load(recv_addr, tmp1, T_OBJECT);
2463 __ br_notnull(tmp1, false, Assembler::pt, next_test);
2464 __ delayed()->nop();
2465 __ st_ptr(recv, recv_addr);
2466 __ set(DataLayout::counter_increment, tmp1);
2467 __ st_ptr(tmp1, mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)) -
2468 mdo_offset_bias);
2469 __ ba(false, *update_done);
2470 __ delayed()->nop();
2471 __ bind(next_test);
2472 }
2473 }
2474
2475
2476 void LIR_Assembler::setup_md_access(ciMethod* method, int bci,
2477 ciMethodData*& md, ciProfileData*& data, int& mdo_offset_bias) {
2478 md = method->method_data();
2479 if (md == NULL) {
2480 bailout("out of memory building methodDataOop");
2481 return;
2482 }
2483 data = md->bci_to_data(bci);
2484 assert(data != NULL, "need data for checkcast");
2485 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
2486 if (!Assembler::is_simm13(md->byte_offset_of_slot(data, DataLayout::header_offset()) + data->size_in_bytes())) {
2487 // The offset is large so bias the mdo by the base of the slot so
2488 // that the ld can use simm13s to reference the slots of the data
2489 mdo_offset_bias = md->byte_offset_of_slot(data, DataLayout::header_offset());
2490 }
2491 }
2492
2493 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) {
2494 // we always need a stub for the failure case.
2495 CodeStub* stub = op->stub();
2496 Register obj = op->object()->as_register();
2497 Register k_RInfo = op->tmp1()->as_register();
2498 Register klass_RInfo = op->tmp2()->as_register();
2499 Register dst = op->result_opr()->as_register();
2500 Register Rtmp1 = op->tmp3()->as_register();
2501 ciKlass* k = op->klass();
2502
2503
2504 if (obj == k_RInfo) {
2505 k_RInfo = klass_RInfo;
2506 klass_RInfo = obj;
2507 }
2508
2509 ciMethodData* md;
2510 ciProfileData* data;
2511 int mdo_offset_bias = 0;
2512 if (op->should_profile()) {
2513 ciMethod* method = op->profiled_method();
2514 assert(method != NULL, "Should have method");
2515 setup_md_access(method, op->profiled_bci(), md, data, mdo_offset_bias);
2516
2517 Label not_null;
2518 __ br_notnull(obj, false, Assembler::pn, not_null);
2519 __ delayed()->nop();
2520 Register mdo = k_RInfo;
2521 Register data_val = Rtmp1;
2522 jobject2reg(md->constant_encoding(), mdo);
2523 if (mdo_offset_bias > 0) {
2524 __ set(mdo_offset_bias, data_val);
2525 __ add(mdo, data_val, mdo);
2526 }
2527 Address flags_addr(mdo, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias);
2528 __ ldub(flags_addr, data_val);
2529 __ or3(data_val, BitData::null_seen_byte_constant(), data_val);
2530 __ stb(data_val, flags_addr);
2531 __ ba(false, *obj_is_null);
2532 __ delayed()->nop();
2533 __ bind(not_null);
2534 } else {
2535 __ br_null(obj, false, Assembler::pn, *obj_is_null);
2536 __ delayed()->nop();
2537 }
2538
2539 Label profile_cast_failure, profile_cast_success;
2540 Label *failure_target = op->should_profile() ? &profile_cast_failure : failure;
2541 Label *success_target = op->should_profile() ? &profile_cast_success : success;
2542
2543 // patching may screw with our temporaries on sparc,
2544 // so let's do it before loading the class
2545 if (k->is_loaded()) {
2546 jobject2reg(k->constant_encoding(), k_RInfo);
2547 } else {
2548 jobject2reg_with_patching(k_RInfo, op->info_for_patch());
2549 }
2550 assert(obj != k_RInfo, "must be different");
2551
2552 // get object class
2553 // not a safepoint as obj null check happens earlier
2554 load(obj, oopDesc::klass_offset_in_bytes(), klass_RInfo, T_OBJECT, NULL);
2555 if (op->fast_check()) {
2556 assert_different_registers(klass_RInfo, k_RInfo);
2557 __ cmp(k_RInfo, klass_RInfo);
2558 __ brx(Assembler::notEqual, false, Assembler::pt, *failure_target);
2559 __ delayed()->nop();
2560 } else {
2561 bool need_slow_path = true;
2562 if (k->is_loaded()) {
2563 if (k->super_check_offset() != sizeof(oopDesc) + Klass::secondary_super_cache_offset_in_bytes())
2564 need_slow_path = false;
2565 // perform the fast part of the checking logic
2566 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, noreg,
2567 (need_slow_path ? success_target : NULL),
2568 failure_target, NULL,
2569 RegisterOrConstant(k->super_check_offset()));
2570 } else {
2571 // perform the fast part of the checking logic
2572 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, O7, success_target,
2573 failure_target, NULL);
2574 }
2575 if (need_slow_path) {
2576 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
2577 assert(klass_RInfo == G3 && k_RInfo == G1, "incorrect call setup");
2578 __ call(Runtime1::entry_for(Runtime1::slow_subtype_check_id), relocInfo::runtime_call_type);
2579 __ delayed()->nop();
2580 __ cmp(G3, 0);
2581 __ br(Assembler::equal, false, Assembler::pn, *failure_target);
2582 __ delayed()->nop();
2583 // Fall through to success case
2584 }
2585 }
2586
2587 if (op->should_profile()) {
2588 Register mdo = klass_RInfo, recv = k_RInfo, tmp1 = Rtmp1;
2589 assert_different_registers(obj, mdo, recv, tmp1);
2590 __ bind(profile_cast_success);
2591 jobject2reg(md->constant_encoding(), mdo);
2592 if (mdo_offset_bias > 0) {
2593 __ set(mdo_offset_bias, tmp1);
2594 __ add(mdo, tmp1, mdo);
2595 }
2596 load(Address(obj, oopDesc::klass_offset_in_bytes()), recv, T_OBJECT);
2597 type_profile_helper(mdo, mdo_offset_bias, md, data, recv, tmp1, success);
2598 // Jump over the failure case
2599 __ ba(false, *success);
2600 __ delayed()->nop();
2601 // Cast failure case
2602 __ bind(profile_cast_failure);
2603 jobject2reg(md->constant_encoding(), mdo);
2604 if (mdo_offset_bias > 0) {
2605 __ set(mdo_offset_bias, tmp1);
2606 __ add(mdo, tmp1, mdo);
2607 }
2608 Address data_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias);
2609 __ ld_ptr(data_addr, tmp1);
2610 __ sub(tmp1, DataLayout::counter_increment, tmp1);
2611 __ st_ptr(tmp1, data_addr);
2612 __ ba(false, *failure);
2613 __ delayed()->nop();
2614 }
2615 __ ba(false, *success);
2616 __ delayed()->nop();
2617 }
2618
2619 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
2620 LIR_Code code = op->code();
2621 if (code == lir_store_check) {
2622 Register value = op->object()->as_register();
2623 Register array = op->array()->as_register();
2624 Register k_RInfo = op->tmp1()->as_register();
2625 Register klass_RInfo = op->tmp2()->as_register();
2626 Register Rtmp1 = op->tmp3()->as_register();
2627
2628 __ verify_oop(value);
2629 CodeStub* stub = op->stub();
2630 // check if it needs to be profiled
2631 ciMethodData* md;
2632 ciProfileData* data;
2633 int mdo_offset_bias = 0;
2634 if (op->should_profile()) {
2635 ciMethod* method = op->profiled_method();
2636 assert(method != NULL, "Should have method");
2637 setup_md_access(method, op->profiled_bci(), md, data, mdo_offset_bias);
2638 }
2639 Label profile_cast_success, profile_cast_failure, done;
2640 Label *success_target = op->should_profile() ? &profile_cast_success : &done;
2641 Label *failure_target = op->should_profile() ? &profile_cast_failure : stub->entry();
2642
2643 if (op->should_profile()) {
2644 Label not_null;
2645 __ br_notnull(value, false, Assembler::pn, not_null);
2646 __ delayed()->nop();
2647 Register mdo = k_RInfo;
2648 Register data_val = Rtmp1;
2649 jobject2reg(md->constant_encoding(), mdo);
2650 if (mdo_offset_bias > 0) {
2651 __ set(mdo_offset_bias, data_val);
2652 __ add(mdo, data_val, mdo);
2653 }
2654 Address flags_addr(mdo, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias);
2655 __ ldub(flags_addr, data_val);
2656 __ or3(data_val, BitData::null_seen_byte_constant(), data_val);
2657 __ stb(data_val, flags_addr);
2658 __ ba(false, done);
2659 __ delayed()->nop();
2660 __ bind(not_null);
2661 } else {
2662 __ br_null(value, false, Assembler::pn, done);
2663 __ delayed()->nop();
2664 }
2665 load(array, oopDesc::klass_offset_in_bytes(), k_RInfo, T_OBJECT, op->info_for_exception());
2666 load(value, oopDesc::klass_offset_in_bytes(), klass_RInfo, T_OBJECT, NULL);
2667
2668 // get instance klass
2669 load(k_RInfo, objArrayKlass::element_klass_offset_in_bytes() + sizeof(oopDesc), k_RInfo, T_OBJECT, NULL);
2670 // perform the fast part of the checking logic
2671 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, O7, success_target, failure_target, NULL);
2672
2673 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
2674 assert(klass_RInfo == G3 && k_RInfo == G1, "incorrect call setup");
2675 __ call(Runtime1::entry_for(Runtime1::slow_subtype_check_id), relocInfo::runtime_call_type);
2676 __ delayed()->nop();
2677 __ cmp(G3, 0);
2678 __ br(Assembler::equal, false, Assembler::pn, *failure_target);
2679 __ delayed()->nop();
2680 // fall through to the success case
2681
2682 if (op->should_profile()) {
2683 Register mdo = klass_RInfo, recv = k_RInfo, tmp1 = Rtmp1;
2684 assert_different_registers(value, mdo, recv, tmp1);
2685 __ bind(profile_cast_success);
2686 jobject2reg(md->constant_encoding(), mdo);
2687 if (mdo_offset_bias > 0) {
2688 __ set(mdo_offset_bias, tmp1);
2689 __ add(mdo, tmp1, mdo);
2690 }
2691 load(Address(value, oopDesc::klass_offset_in_bytes()), recv, T_OBJECT);
2692 type_profile_helper(mdo, mdo_offset_bias, md, data, recv, tmp1, &done);
2693 __ ba(false, done);
2694 __ delayed()->nop();
2695 // Cast failure case
2696 __ bind(profile_cast_failure);
2697 jobject2reg(md->constant_encoding(), mdo);
2698 if (mdo_offset_bias > 0) {
2699 __ set(mdo_offset_bias, tmp1);
2700 __ add(mdo, tmp1, mdo);
2701 }
2702 Address data_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias);
2703 __ ld_ptr(data_addr, tmp1);
2704 __ sub(tmp1, DataLayout::counter_increment, tmp1);
2705 __ st_ptr(tmp1, data_addr);
2706 __ ba(false, *stub->entry());
2707 __ delayed()->nop();
2708 }
2709 __ bind(done);
2710 } else if (code == lir_checkcast) {
2711 Register obj = op->object()->as_register();
2712 Register dst = op->result_opr()->as_register();
2713 Label success;
2714 emit_typecheck_helper(op, &success, op->stub()->entry(), &success);
2715 __ bind(success);
2716 __ mov(obj, dst);
2717 } else if (code == lir_instanceof) {
2718 Register obj = op->object()->as_register();
2719 Register dst = op->result_opr()->as_register();
2720 Label success, failure, done;
2721 emit_typecheck_helper(op, &success, &failure, &failure);
2722 __ bind(failure);
2723 __ set(0, dst);
2724 __ ba(false, done);
2725 __ delayed()->nop();
2726 __ bind(success);
2727 __ set(1, dst);
2728 __ bind(done);
2729 } else {
2730 ShouldNotReachHere();
2731 }
2732
2733 }
2734
2735
2736 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
2737 if (op->code() == lir_cas_long) {
2738 assert(VM_Version::supports_cx8(), "wrong machine");
2739 Register addr = op->addr()->as_pointer_register();
2740 Register cmp_value_lo = op->cmp_value()->as_register_lo();
2741 Register cmp_value_hi = op->cmp_value()->as_register_hi();
2742 Register new_value_lo = op->new_value()->as_register_lo();
2743 Register new_value_hi = op->new_value()->as_register_hi();
2744 Register t1 = op->tmp1()->as_register();
2745 Register t2 = op->tmp2()->as_register();
2746 #ifdef _LP64
2747 __ mov(cmp_value_lo, t1);
2748 __ mov(new_value_lo, t2);
2749 #else
2750 // move high and low halves of long values into single registers
2751 __ sllx(cmp_value_hi, 32, t1); // shift high half into temp reg
2752 __ srl(cmp_value_lo, 0, cmp_value_lo); // clear upper 32 bits of low half
2753 __ or3(t1, cmp_value_lo, t1); // t1 holds 64-bit compare value
2754 __ sllx(new_value_hi, 32, t2);
2755 __ srl(new_value_lo, 0, new_value_lo);
2756 __ or3(t2, new_value_lo, t2); // t2 holds 64-bit value to swap
2757 #endif
2758 // perform the compare and swap operation
2759 __ casx(addr, t1, t2);
2760 // generate condition code - if the swap succeeded, t2 ("new value" reg) was
2761 // overwritten with the original value in "addr" and will be equal to t1.
2762 __ cmp(t1, t2);
2763
2764 } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj) {
2765 Register addr = op->addr()->as_pointer_register();
2766 Register cmp_value = op->cmp_value()->as_register();
2767 Register new_value = op->new_value()->as_register();
2768 Register t1 = op->tmp1()->as_register();
2769 Register t2 = op->tmp2()->as_register();
2770 __ mov(cmp_value, t1);
2771 __ mov(new_value, t2);
2772 #ifdef _LP64
2773 if (op->code() == lir_cas_obj) {
2774 __ casx(addr, t1, t2);
2775 } else
2776 #endif
2777 {
2778 __ cas(addr, t1, t2);
2779 }
2780 __ cmp(t1, t2);
2781 } else {
2782 Unimplemented();
2783 }
2784 }
2785
2786 void LIR_Assembler::set_24bit_FPU() {
2787 Unimplemented();
2788 }
2789
2790
2791 void LIR_Assembler::reset_FPU() {
2792 Unimplemented();
2793 }
2794
2795
2796 void LIR_Assembler::breakpoint() {
2797 __ breakpoint_trap();
2798 }
2799
2800
2801 void LIR_Assembler::push(LIR_Opr opr) {
2802 Unimplemented();
2803 }
2804
2805
2806 void LIR_Assembler::pop(LIR_Opr opr) {
2807 Unimplemented();
2808 }
2809
2810
2811 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst_opr) {
2812 Address mon_addr = frame_map()->address_for_monitor_lock(monitor_no);
2813 Register dst = dst_opr->as_register();
2814 Register reg = mon_addr.base();
2815 int offset = mon_addr.disp();
2816 // compute pointer to BasicLock
2817 if (mon_addr.is_simm13()) {
2818 __ add(reg, offset, dst);
2819 } else {
2820 __ set(offset, dst);
2821 __ add(dst, reg, dst);
2822 }
2823 }
2824
2825
2826 void LIR_Assembler::emit_lock(LIR_OpLock* op) {
2827 Register obj = op->obj_opr()->as_register();
2828 Register hdr = op->hdr_opr()->as_register();
2829 Register lock = op->lock_opr()->as_register();
2830
2831 // obj may not be an oop
2832 if (op->code() == lir_lock) {
2833 MonitorEnterStub* stub = (MonitorEnterStub*)op->stub();
2834 if (UseFastLocking) {
2835 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
2836 // add debug info for NullPointerException only if one is possible
2837 if (op->info() != NULL) {
2838 add_debug_info_for_null_check_here(op->info());
2839 }
2840 __ lock_object(hdr, obj, lock, op->scratch_opr()->as_register(), *op->stub()->entry());
2841 } else {
2842 // always do slow locking
2843 // note: the slow locking code could be inlined here, however if we use
2844 // slow locking, speed doesn't matter anyway and this solution is
2845 // simpler and requires less duplicated code - additionally, the
2846 // slow locking code is the same in either case which simplifies
2847 // debugging
2848 __ br(Assembler::always, false, Assembler::pt, *op->stub()->entry());
2849 __ delayed()->nop();
2850 }
2851 } else {
2852 assert (op->code() == lir_unlock, "Invalid code, expected lir_unlock");
2853 if (UseFastLocking) {
2854 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
2855 __ unlock_object(hdr, obj, lock, *op->stub()->entry());
2856 } else {
2857 // always do slow unlocking
2858 // note: the slow unlocking code could be inlined here, however if we use
2859 // slow unlocking, speed doesn't matter anyway and this solution is
2860 // simpler and requires less duplicated code - additionally, the
2861 // slow unlocking code is the same in either case which simplifies
2862 // debugging
2863 __ br(Assembler::always, false, Assembler::pt, *op->stub()->entry());
2864 __ delayed()->nop();
2865 }
2866 }
2867 __ bind(*op->stub()->continuation());
2868 }
2869
2870
2871 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
2872 ciMethod* method = op->profiled_method();
2873 int bci = op->profiled_bci();
2874
2875 // Update counter for all call types
2876 ciMethodData* md = method->method_data();
2877 if (md == NULL) {
2878 bailout("out of memory building methodDataOop");
2879 return;
2880 }
2881 ciProfileData* data = md->bci_to_data(bci);
2882 assert(data->is_CounterData(), "need CounterData for calls");
2883 assert(op->mdo()->is_single_cpu(), "mdo must be allocated");
2884 Register mdo = op->mdo()->as_register();
2885 #ifdef _LP64
2886 assert(op->tmp1()->is_double_cpu(), "tmp1 must be allocated");
2887 Register tmp1 = op->tmp1()->as_register_lo();
2888 #else
2889 assert(op->tmp1()->is_single_cpu(), "tmp1 must be allocated");
2890 Register tmp1 = op->tmp1()->as_register();
2891 #endif
2892 jobject2reg(md->constant_encoding(), mdo);
2893 int mdo_offset_bias = 0;
2894 if (!Assembler::is_simm13(md->byte_offset_of_slot(data, CounterData::count_offset()) +
2895 data->size_in_bytes())) {
2896 // The offset is large so bias the mdo by the base of the slot so
2897 // that the ld can use simm13s to reference the slots of the data
2898 mdo_offset_bias = md->byte_offset_of_slot(data, CounterData::count_offset());
2899 __ set(mdo_offset_bias, O7);
2900 __ add(mdo, O7, mdo);
2901 }
2902
2903 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias);
2904 Bytecodes::Code bc = method->java_code_at_bci(bci);
2905 // Perform additional virtual call profiling for invokevirtual and
2906 // invokeinterface bytecodes
2907 if ((bc == Bytecodes::_invokevirtual || bc == Bytecodes::_invokeinterface) &&
2908 C1ProfileVirtualCalls) {
2909 assert(op->recv()->is_single_cpu(), "recv must be allocated");
2910 Register recv = op->recv()->as_register();
2911 assert_different_registers(mdo, tmp1, recv);
2912 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls");
2913 ciKlass* known_klass = op->known_holder();
2914 if (C1OptimizeVirtualCallProfiling && known_klass != NULL) {
2915 // We know the type that will be seen at this call site; we can
2916 // statically update the methodDataOop rather than needing to do
2917 // dynamic tests on the receiver type
2918
2919 // NOTE: we should probably put a lock around this search to
2920 // avoid collisions by concurrent compilations
2921 ciVirtualCallData* vc_data = (ciVirtualCallData*) data;
2922 uint i;
2923 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2924 ciKlass* receiver = vc_data->receiver(i);
2925 if (known_klass->equals(receiver)) {
2926 Address data_addr(mdo, md->byte_offset_of_slot(data,
2927 VirtualCallData::receiver_count_offset(i)) -
2928 mdo_offset_bias);
2929 __ ld_ptr(data_addr, tmp1);
2930 __ add(tmp1, DataLayout::counter_increment, tmp1);
2931 __ st_ptr(tmp1, data_addr);
2932 return;
2933 }
2934 }
2935
2936 // Receiver type not found in profile data; select an empty slot
2937
2938 // Note that this is less efficient than it should be because it
2939 // always does a write to the receiver part of the
2940 // VirtualCallData rather than just the first time
2941 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2942 ciKlass* receiver = vc_data->receiver(i);
2943 if (receiver == NULL) {
2944 Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)) -
2945 mdo_offset_bias);
2946 jobject2reg(known_klass->constant_encoding(), tmp1);
2947 __ st_ptr(tmp1, recv_addr);
2948 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) -
2949 mdo_offset_bias);
2950 __ ld_ptr(data_addr, tmp1);
2951 __ add(tmp1, DataLayout::counter_increment, tmp1);
2952 __ st_ptr(tmp1, data_addr);
2953 return;
2954 }
2955 }
2956 } else {
2957 load(Address(recv, oopDesc::klass_offset_in_bytes()), recv, T_OBJECT);
2958 Label update_done;
2959 type_profile_helper(mdo, mdo_offset_bias, md, data, recv, tmp1, &update_done);
2960 // Receiver did not match any saved receiver and there is no empty row for it.
2961 // Increment total counter to indicate polymorphic case.
2962 __ ld_ptr(counter_addr, tmp1);
2963 __ add(tmp1, DataLayout::counter_increment, tmp1);
2964 __ st_ptr(tmp1, counter_addr);
2965
2966 __ bind(update_done);
2967 }
2968 } else {
2969 // Static call
2970 __ ld_ptr(counter_addr, tmp1);
2971 __ add(tmp1, DataLayout::counter_increment, tmp1);
2972 __ st_ptr(tmp1, counter_addr);
2973 }
2974 }
2975
2976 void LIR_Assembler::align_backward_branch_target() {
2977 __ align(OptoLoopAlignment);
2978 }
2979
2980
2981 void LIR_Assembler::emit_delay(LIR_OpDelay* op) {
2982 // make sure we are expecting a delay
2983 // this has the side effect of clearing the delay state
2984 // so we can use _masm instead of _masm->delayed() to do the
2985 // code generation.
2986 __ delayed();
2987
2988 // make sure we only emit one instruction
2989 int offset = code_offset();
2990 op->delay_op()->emit_code(this);
2991 #ifdef ASSERT
2992 if (code_offset() - offset != NativeInstruction::nop_instruction_size) {
2993 op->delay_op()->print();
2994 }
2995 assert(code_offset() - offset == NativeInstruction::nop_instruction_size,
2996 "only one instruction can go in a delay slot");
2997 #endif
2998
2999 // we may also be emitting the call info for the instruction
3000 // which we are the delay slot of.
3001 CodeEmitInfo* call_info = op->call_info();
3002 if (call_info) {
3003 add_call_info(code_offset(), call_info);
3004 }
3005
3006 if (VerifyStackAtCalls) {
3007 _masm->sub(FP, SP, O7);
3008 _masm->cmp(O7, initial_frame_size_in_bytes());
3009 _masm->trap(Assembler::notEqual, Assembler::ptr_cc, G0, ST_RESERVED_FOR_USER_0+2 );
3010 }
3011 }
3012
3013
3014 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest) {
3015 assert(left->is_register(), "can only handle registers");
3016
3017 if (left->is_single_cpu()) {
3018 __ neg(left->as_register(), dest->as_register());
3019 } else if (left->is_single_fpu()) {
3020 __ fneg(FloatRegisterImpl::S, left->as_float_reg(), dest->as_float_reg());
3021 } else if (left->is_double_fpu()) {
3022 __ fneg(FloatRegisterImpl::D, left->as_double_reg(), dest->as_double_reg());
3023 } else {
3024 assert (left->is_double_cpu(), "Must be a long");
3025 Register Rlow = left->as_register_lo();
3026 Register Rhi = left->as_register_hi();
3027 #ifdef _LP64
3028 __ sub(G0, Rlow, dest->as_register_lo());
3029 #else
3030 __ subcc(G0, Rlow, dest->as_register_lo());
3031 __ subc (G0, Rhi, dest->as_register_hi());
3032 #endif
3033 }
3034 }
3035
3036
3037 void LIR_Assembler::fxch(int i) {
3038 Unimplemented();
3039 }
3040
3041 void LIR_Assembler::fld(int i) {
3042 Unimplemented();
3043 }
3044
3045 void LIR_Assembler::ffree(int i) {
3046 Unimplemented();
3047 }
3048
3049 void LIR_Assembler::rt_call(LIR_Opr result, address dest,
3050 const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
3051
3052 // if tmp is invalid, then the function being called doesn't destroy the thread
3053 if (tmp->is_valid()) {
3054 __ save_thread(tmp->as_register());
3055 }
3056 __ call(dest, relocInfo::runtime_call_type);
3057 __ delayed()->nop();
3058 if (info != NULL) {
3059 add_call_info_here(info);
3060 }
3061 if (tmp->is_valid()) {
3062 __ restore_thread(tmp->as_register());
3063 }
3064
3065 #ifdef ASSERT
3066 __ verify_thread();
3067 #endif // ASSERT
3068 }
3069
3070
3071 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) {
3072 #ifdef _LP64
3073 ShouldNotReachHere();
3074 #endif
3075
3076 NEEDS_CLEANUP;
3077 if (type == T_LONG) {
3078 LIR_Address* mem_addr = dest->is_address() ? dest->as_address_ptr() : src->as_address_ptr();
3079
3080 // (extended to allow indexed as well as constant displaced for JSR-166)
3081 Register idx = noreg; // contains either constant offset or index
3082
3083 int disp = mem_addr->disp();
3084 if (mem_addr->index() == LIR_OprFact::illegalOpr) {
3085 if (!Assembler::is_simm13(disp)) {
3086 idx = O7;
3087 __ set(disp, idx);
3088 }
3089 } else {
3090 assert(disp == 0, "not both indexed and disp");
3091 idx = mem_addr->index()->as_register();
3092 }
3093
3094 int null_check_offset = -1;
3095
3096 Register base = mem_addr->base()->as_register();
3097 if (src->is_register() && dest->is_address()) {
3098 // G4 is high half, G5 is low half
3099 if (VM_Version::v9_instructions_work()) {
3100 // clear the top bits of G5, and scale up G4
3101 __ srl (src->as_register_lo(), 0, G5);
3102 __ sllx(src->as_register_hi(), 32, G4);
3103 // combine the two halves into the 64 bits of G4
3104 __ or3(G4, G5, G4);
3105 null_check_offset = __ offset();
3106 if (idx == noreg) {
3107 __ stx(G4, base, disp);
3108 } else {
3109 __ stx(G4, base, idx);
3110 }
3111 } else {
3112 __ mov (src->as_register_hi(), G4);
3113 __ mov (src->as_register_lo(), G5);
3114 null_check_offset = __ offset();
3115 if (idx == noreg) {
3116 __ std(G4, base, disp);
3117 } else {
3118 __ std(G4, base, idx);
3119 }
3120 }
3121 } else if (src->is_address() && dest->is_register()) {
3122 null_check_offset = __ offset();
3123 if (VM_Version::v9_instructions_work()) {
3124 if (idx == noreg) {
3125 __ ldx(base, disp, G5);
3126 } else {
3127 __ ldx(base, idx, G5);
3128 }
3129 __ srax(G5, 32, dest->as_register_hi()); // fetch the high half into hi
3130 __ mov (G5, dest->as_register_lo()); // copy low half into lo
3131 } else {
3132 if (idx == noreg) {
3133 __ ldd(base, disp, G4);
3134 } else {
3135 __ ldd(base, idx, G4);
3136 }
3137 // G4 is high half, G5 is low half
3138 __ mov (G4, dest->as_register_hi());
3139 __ mov (G5, dest->as_register_lo());
3140 }
3141 } else {
3142 Unimplemented();
3143 }
3144 if (info != NULL) {
3145 add_debug_info_for_null_check(null_check_offset, info);
3146 }
3147
3148 } else {
3149 // use normal move for all other volatiles since they don't need
3150 // special handling to remain atomic.
3151 move_op(src, dest, type, lir_patch_none, info, false, false);
3152 }
3153 }
3154
3155 void LIR_Assembler::membar() {
3156 // only StoreLoad membars are ever explicitly needed on sparcs in TSO mode
3157 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad) );
3158 }
3159
3160 void LIR_Assembler::membar_acquire() {
3161 // no-op on TSO
3162 }
3163
3164 void LIR_Assembler::membar_release() {
3165 // no-op on TSO
3166 }
3167
3168 // Pack two sequential registers containing 32 bit values
3169 // into a single 64 bit register.
3170 // src and src->successor() are packed into dst
3171 // src and dst may be the same register.
3172 // Note: src is destroyed
3173 void LIR_Assembler::pack64(LIR_Opr src, LIR_Opr dst) {
3174 Register rs = src->as_register();
3175 Register rd = dst->as_register_lo();
3176 __ sllx(rs, 32, rs);
3177 __ srl(rs->successor(), 0, rs->successor());
3178 __ or3(rs, rs->successor(), rd);
3179 }
3180
3181 // Unpack a 64 bit value in a register into
3182 // two sequential registers.
3183 // src is unpacked into dst and dst->successor()
3184 void LIR_Assembler::unpack64(LIR_Opr src, LIR_Opr dst) {
3185 Register rs = src->as_register_lo();
3186 Register rd = dst->as_register_hi();
3187 assert_different_registers(rs, rd, rd->successor());
3188 __ srlx(rs, 32, rd);
3189 __ srl (rs, 0, rd->successor());
3190 }
3191
3192
3193 void LIR_Assembler::leal(LIR_Opr addr_opr, LIR_Opr dest) {
3194 LIR_Address* addr = addr_opr->as_address_ptr();
3195 assert(addr->index()->is_illegal() && addr->scale() == LIR_Address::times_1 && Assembler::is_simm13(addr->disp()), "can't handle complex addresses yet");
3196
3197 __ add(addr->base()->as_pointer_register(), addr->disp(), dest->as_pointer_register());
3198 }
3199
3200
3201 void LIR_Assembler::get_thread(LIR_Opr result_reg) {
3202 assert(result_reg->is_register(), "check");
3203 __ mov(G2_thread, result_reg->as_register());
3204 }
3205
3206
3207 void LIR_Assembler::peephole(LIR_List* lir) {
3208 LIR_OpList* inst = lir->instructions_list();
3209 for (int i = 0; i < inst->length(); i++) {
3210 LIR_Op* op = inst->at(i);
3211 switch (op->code()) {
3212 case lir_cond_float_branch:
3213 case lir_branch: {
3214 LIR_OpBranch* branch = op->as_OpBranch();
3215 assert(branch->info() == NULL, "shouldn't be state on branches anymore");
3216 LIR_Op* delay_op = NULL;
3217 // we'd like to be able to pull following instructions into
3218 // this slot but we don't know enough to do it safely yet so
3219 // only optimize block to block control flow.
3220 if (LIRFillDelaySlots && branch->block()) {
3221 LIR_Op* prev = inst->at(i - 1);
3222 if (prev && LIR_Assembler::is_single_instruction(prev) && prev->info() == NULL) {
3223 // swap previous instruction into delay slot
3224 inst->at_put(i - 1, op);
3225 inst->at_put(i, new LIR_OpDelay(prev, op->info()));
3226 #ifndef PRODUCT
3227 if (LIRTracePeephole) {
3228 tty->print_cr("delayed");
3229 inst->at(i - 1)->print();
3230 inst->at(i)->print();
3231 tty->cr();
3232 }
3233 #endif
3234 continue;
3235 }
3236 }
3237
3238 if (!delay_op) {
3239 delay_op = new LIR_OpDelay(new LIR_Op0(lir_nop), NULL);
3240 }
3241 inst->insert_before(i + 1, delay_op);
3242 break;
3243 }
3244 case lir_static_call:
3245 case lir_virtual_call:
3246 case lir_icvirtual_call:
3247 case lir_optvirtual_call:
3248 case lir_dynamic_call: {
3249 LIR_Op* prev = inst->at(i - 1);
3250 if (LIRFillDelaySlots && prev && prev->code() == lir_move && prev->info() == NULL &&
3251 (op->code() != lir_virtual_call ||
3252 !prev->result_opr()->is_single_cpu() ||
3253 prev->result_opr()->as_register() != O0) &&
3254 LIR_Assembler::is_single_instruction(prev)) {
3255 // Only moves without info can be put into the delay slot.
3256 // Also don't allow the setup of the receiver in the delay
3257 // slot for vtable calls.
3258 inst->at_put(i - 1, op);
3259 inst->at_put(i, new LIR_OpDelay(prev, op->info()));
3260 #ifndef PRODUCT
3261 if (LIRTracePeephole) {
3262 tty->print_cr("delayed");
3263 inst->at(i - 1)->print();
3264 inst->at(i)->print();
3265 tty->cr();
3266 }
3267 #endif
3268 } else {
3269 LIR_Op* delay_op = new LIR_OpDelay(new LIR_Op0(lir_nop), op->as_OpJavaCall()->info());
3270 inst->insert_before(i + 1, delay_op);
3271 i++;
3272 }
3273
3274 #if defined(TIERED) && !defined(_LP64)
3275 // fixup the return value from G1 to O0/O1 for long returns.
3276 // It's done here instead of in LIRGenerator because there's
3277 // such a mismatch between the single reg and double reg
3278 // calling convention.
3279 LIR_OpJavaCall* callop = op->as_OpJavaCall();
3280 if (callop->result_opr() == FrameMap::out_long_opr) {
3281 LIR_OpJavaCall* call;
3282 LIR_OprList* arguments = new LIR_OprList(callop->arguments()->length());
3283 for (int a = 0; a < arguments->length(); a++) {
3284 arguments[a] = callop->arguments()[a];
3285 }
3286 if (op->code() == lir_virtual_call) {
3287 call = new LIR_OpJavaCall(op->code(), callop->method(), callop->receiver(), FrameMap::g1_long_single_opr,
3288 callop->vtable_offset(), arguments, callop->info());
3289 } else {
3290 call = new LIR_OpJavaCall(op->code(), callop->method(), callop->receiver(), FrameMap::g1_long_single_opr,
3291 callop->addr(), arguments, callop->info());
3292 }
3293 inst->at_put(i - 1, call);
3294 inst->insert_before(i + 1, new LIR_Op1(lir_unpack64, FrameMap::g1_long_single_opr, callop->result_opr(),
3295 T_LONG, lir_patch_none, NULL));
3296 }
3297 #endif
3298 break;
3299 }
3300 }
3301 }
3302 }
3303
3304
3305
3306
3307 #undef __